diff --git a/src/hg_mp/drx_top/huagao_mipi_top.v b/src/hg_mp/drx_top/huagao_mipi_top.v
index 4740d9c..c98d920 100644
--- a/src/hg_mp/drx_top/huagao_mipi_top.v
+++ b/src/hg_mp/drx_top/huagao_mipi_top.v
@@ -345,6 +345,28 @@ reg[31:0]                       mipi_rst_d0 ;
 
 reg[1:0]                        ubus_lpclk_d0 , ubus_lpclk_d1 ;
 
+wire O_clk_lp_p_sync;
+wire O_clk_lp_n_sync;
+cdc_sync # (
+         .DEPTH (20),
+		 .WIDTH (13)
+) u_O_clk_lp_p( /* synthesis keep_hierarchy=true */
+      .to_clk     (clk_ubus          ),
+	  .rest_n     (rst_n             ),
+	  .signal_from(O_clk_lp_p      ),
+	  .signal_to  (O_clk_lp_p_sync )
+);
+
+cdc_sync # (
+         .DEPTH (20),
+		 .WIDTH (13)
+) u_O_clk_lp_n( /* synthesis keep_hierarchy=true */
+      .to_clk     (clk_ubus          ),
+	  .rest_n     (rst_n             ),
+	  .signal_from(O_clk_lp_n      ),
+	  .signal_to  (O_clk_lp_n_sync )
+);
+
 
 always @ (posedge clk_ubus) begin
     if (~rst_n) begin
@@ -354,7 +376,7 @@ always @ (posedge clk_ubus) begin
     else begin 
 
          //ubus_lpclk_d0  <= MP1_LPCLK ;
-         ubus_lpclk_d0  <= {O_clk_lp_p,O_clk_lp_n} ;
+         ubus_lpclk_d0  <= {O_clk_lp_p_sync,O_clk_lp_n_sync} ;
          ubus_lpclk_d1  <= ubus_lpclk_d0 ;
     end
 end
@@ -740,7 +762,7 @@ exdev_ctl #
 .adc_freqdiv             (adc_freqdiv                          ),
 .line_sync				(line_sycn_b),
 .en_work			     (en_work_b							   ),
-.bg_sp_t				 (bg_sp_t_a							   )
+.bg_sp_t				 (bg_sp_t_b							   )
 );
 
 
diff --git a/src/hg_mp/fe/rddpram_ctl.v b/src/hg_mp/fe/rddpram_ctl.v
index e8711a0..319ffb8 100644
--- a/src/hg_mp/fe/rddpram_ctl.v
+++ b/src/hg_mp/fe/rddpram_ctl.v
@@ -127,7 +127,7 @@ end
 
 reg cis_sel_d0,cis_sel_d1;
 
-always @ (posedge pclk  ) begin 
+always @ (posedge clk  ) begin 
     if (!reset_n)
       begin
           cis_sel_d0 <= 1'b0;
diff --git a/src/hg_mp/fe/rddpram_ctl_rev.v b/src/hg_mp/fe/rddpram_ctl_rev.v
index 7ce706a..5feafa5 100644
--- a/src/hg_mp/fe/rddpram_ctl_rev.v
+++ b/src/hg_mp/fe/rddpram_ctl_rev.v
@@ -127,7 +127,7 @@ end
 
 reg cis_sel_d0,cis_sel_d1;
 
-always @ (posedge pclk  ) begin 
+always @ (posedge clk  ) begin 
     if (!reset_n)
       begin
           cis_sel_d0 <= 1'b0;
diff --git a/src/hg_mp/local_bus/ubus_top.v b/src/hg_mp/local_bus/ubus_top.v
index 27392aa..72d67b3 100644
--- a/src/hg_mp/local_bus/ubus_top.v
+++ b/src/hg_mp/local_bus/ubus_top.v
@@ -245,8 +245,8 @@ local_bus_slve_cis u_local_bus_slve_cis(
        ,.reg2nd_17      (                  ) //output reg [31:0]  
        ,.reg2nd_18      (                  ) //output reg [31:0]  
        ,.reg2nd_19      (  bg_sp_t_a       ) //output reg [31:0]  
-       ,.reg2nd_20      (  bg_sp_t_b       ) //output reg [31:0]  
-
+       ,.reg2nd_20      (         ) //output reg [31:0]  
+		,.reg2nd_21      (  bg_sp_t_b       )
 );
 assign debug = cis_sel;
 
diff --git a/src/prj/td_project/al_devicechain/hg_anlogic_L1.svf b/src/prj/td_project/al_devicechain/hg_anlogic_L1.svf
new file mode 100644
index 0000000..a82fc54
--- /dev/null
+++ b/src/prj/td_project/al_devicechain/hg_anlogic_L1.svf
@@ -0,0 +1,7934 @@
+// Created using Anlogic Software, 5.6.71036
+// Date: 2024/ 3/11 11:49
+// Architecture: eagle_s20
+
+TRST OFF;
+ENDIR IDLE;
+ENDDR IDLE;
+STATE RESET;
+STATE IDLE;
+FREQUENCY 1E6 HZ ;
+TDR 0 ;
+TIR 0 ;
+HDR 0 ;
+HIR 0 ;
+SIR 8 TDI (ff) ;
+SIR 8 TDI (ff) ;
+SIR 8 TDI (06) ;
+RUNTEST 15 TCK ;
+SDR 32 TDI (00000000) TDO (04014C35) MASK (FFFFFFFF) ;
+SIR 8 TDI (01) ;
+SIR 8 TDI (FF) ;
+SIR 8 TDI (39) ;
+RUNTEST 50000 TCK ;
+RUNTEST 50000 TCK ;
+RUNTEST 50000 TCK ;
+RUNTEST 50000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00000004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00080004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00040004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000c0004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00020004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000a0004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00060004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000e0004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00010004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00090004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00050004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000d0004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00030004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000b0004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00070004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000f0004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00008004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00088004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00048004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000c8004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00028004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000a8004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00068004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000e8004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00018004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00098004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00058004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000d8004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00038004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000b8004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00078004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000f8004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00004004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00084004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00044004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000c4004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00024004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000a4004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00064004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000e4004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00014004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00094004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00054004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000d4004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00034004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000b4004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00074004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000f4004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0000c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0008c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0004c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000cc004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0002c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ac004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0006c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ec004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0001c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0009c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0005c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000dc004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0003c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000bc004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0007c004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000fc004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00002004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00082004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00042004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000c2004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00022004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000a2004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00062004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000e2004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00012004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00092004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00052004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000d2004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00032004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000b2004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00072004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000f2004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0000a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0008a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0004a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ca004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0002a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000aa004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0006a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ea004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0001a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0009a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0005a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000da004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0003a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ba004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0007a004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000fa004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00006004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00086004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00046004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000c6004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00026004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000a6004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00066004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000e6004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00016004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00096004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00056004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000d6004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00036004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000b6004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00076004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000f6004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0000e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0008e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0004e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ce004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0002e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ae004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0006e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000ee004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0001e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0009e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0005e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000de004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0003e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000be004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (0007e004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000fe004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00001004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00081004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00041004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000c1004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00021004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000a1004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00061004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000e1004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00011004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00091004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00051004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000d1004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00031004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000b1004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00071004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000f1004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00009004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00089004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00049004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000c9004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00029004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000a9004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00069004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (000e9004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00019004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00099004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 32 TDI (00059004) ;
+RUNTEST 300000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000001610054000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7200f37f51e00002000008fccc31c0000006000002322c900000fc060000053786800001200600000831119012000006000001363541780d720600000e3cf980dd20c2b600000c3059400a08080600000437ddfac3280206000000fcc55aa33ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000081312200000000000000000000000000000000000000000000000000500000000000000000000000000000000000000000000000000000000000000000000000000000804504400000000000000420504000220a201000201141100000840100000000000000000000000000448c81000171005400000000000008131220000011232040005c40150000000000000000000000000000000000000000000000000000000000000000000000000005c401500000000000000000000000000000000000000000000042050410000000000000102120400018401000000000000000000000000000000000000000000000000000000000000000000000000000800040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000895142200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028000000000000000000000000000000000000000000008ffe0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500000000a0000000000000000000000000000000000000000000000000000000000000000000000000400040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000008a1440610000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002100000040000000000000005000602000000840084000001224010080000000000000000000000000860228518950422000000000000008a14406100021808a1462541088000000000000000a40000000000000000000000000000000000000000000000000000000022541088000000000000000000000000000000000000000000000000104020000000000002180aa1462401008000000000000000000000000000000000000000c00040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f5b8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000000a4000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a00040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000322d000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000060000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000e00040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000702a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000900040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0480100000000000001100000004000081000000000000000000000000000000002000000000000000080000000000002000100000000000004088000010000000000000000000000000000000000000000000000000000000000000100000080000000002082000000000000000000000000002000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000120040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000040000000000020a00002000000000008000000000000000000000000000000000000000000000000000000ef7f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000920040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000020000000000000000000100000000800000000000000200000000000000000000000001400000000800058000000020021408000000000000000100000801600000000000000000000000000008000000000058000000000001600000000000000000000000000200000000000000000000000001400000000000008000000000001600000000000000000000000000200000000000100000200000000000000000000000000200000000000000000000008000000ae0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000400000000000000000000000000000000000000010000000000000000000000000010000000000000000000000000000000020000000000000000000000000000000080004000010000080100002000000004000000000c001000000020000c40000000000000000080000000002080000000000000000000000040000000000000080000000000000000000000000000000000010000000000100000000000000000000000000000000000000000000000000000000000000000000000000ef53000000000000000000000000000000000080000000000016000200000000500000008008014200800200000000000000006e0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000008000004008000000200000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000080000000000100000000002002002000000000000000000000000000000000000801000000000000000000000000000000000000000040802000000000000000000000000080002000001000000000000000000000000000008000000000040000000002001020004000000000000000020001000020800000000000000000000000000022000040000000000001000002000000000000000000001000000000000000000200000000080000000000ee0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000004000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000004000000000000000000000080000000000000000000000000000000800000000400001000000020000000000000000000000000000040000c000000010000000200400000000010200000000000000000000000000000000400000400000000000000000010000000001000000040000000002000000000200000000000000000000000000000000000000000000000000000000000000005a75000000000000000000000000000840001420008000000010000000000000001e0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00030000400801000000000000020000000000000001021000000020040000800000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000800000000000000000000008408010000000000000000000000010000000000010000000000000000000000000000000000000010000010010000400200040000000000000400008008000000000000000000000000000000000000000000000000000008000400040000000000000000400000000410000000000000000000000000000408000000000000000000000008000000000000000000000009e0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000020010000000000000000000000020000001000010000000000000000000000000000000000000000000000010000000800000000000000000000040040000000000000020000000000000000000000000020000020000000010000000000400000000000000000000000000000000000040000008000000000000200000000000008000000000000200000000000108000000000000000000000000000000000000000000000000000808000000000000000000000000000000000000000000008000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000c986000000000000000000000000005e0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000d83a000000000000000000000000000300080084012020000002000000000000000000000000100000000000000000000000000000008000000080000002000000000010000000000000000000000080000000000000000001000000000000000000800001002000000000000000000000000000000000802000000000000000010000000000000010000000000200020000000020000000000000000000000000000000000000000a000000000000000200000000000100100000000200008000000000100000000000000000000000008000000000000200020110000002100000000000200000000000000000000000000000000000000008000000de0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000200000000000000000000000000200000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000004000000000000002000000000000000000000000000000000000008000000000000002000000000000000000000000002000040000000080000000000002000000000000000000000000000000000000000000000000000000000000003e0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000501d00000000000000000000000000084010000100c008000002000000000000080000000600002000400000000002c000000000000200000000000000000000000000200000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000002000000000000000000000000000000000000000000000800000040000000000000000000000000000000200000000000008800000000000200000000000000000000000000200010000000000100000000000008000000000008000000000000200080000000000800000000000000000000000be0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000208800000200100000000720000000000000000000000002800000002000014000100000000000200000000000000000000000500080000000000000000000000000000000000000004000000000000004200000000000000000100000000000200200000000000000000000000000000000000000000500080200000000000000000000000080000000000000100000000000000000000000140200000000005020000000000080000000000002000000000000080000008020000000000000000000000000000000000000020000000800000800020000000000000000000008000010000000004840800008000300020000000000000000000000000007e0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000041000000000000000000000000000000000000000000000000000000000056a8000000000000000000000000040000000140b6000000002d008000021000a0004100000c0a80000400000000020000000000000000000208800000020008000000008000000000000210000000800010000000000000220000000000000000008000020020000000000010000000000000000000000050290000000000000210400000000000010000020000024200040000500810000000000000000800001000000000000000020800090102800200000000000202000010802d00000000000000000000000000008000002122008020180800001000fe0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000100000000000001001001080040014400000800000000000000000000000000000000200000000000000000008401040000000000000000000000800000000000000000001000040300000000000020000008000000000000010000000000008000002000001000000102000000000000000020000000000000000000000000000200000200400040000008020000000000000000000000000000000000000000000000004000002000000000001014000000001080010000000000085000080000030140490001018010400000000000400000000000000000000010000000012500010010400000000080000000000000020000000000400010040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000014000080000000080000000000000010948004000000000000000000000000000000000000000000000000000000000000000000000893d0000000000000000000000000000000000000000000400000001020000800040841041000000100000000020000000000000000001000000000000000000000000001000000000008800000000000200020000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000020000000800000000000000000000000000000000000000000000000000000000000004010000000800100400000012000000200000004000002000000000400008000000000810040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (802000000004890000020300000000000000000000000000000010406148c00381218000b0520c00000000000000000004000678900000000000000000000000000000000008060400060001202998000000000000000000000200800000000000000010000000002000000000000000000024000000000000100008000600000800000000000000000000000000000202000000000000000000080000200000000000400000010000000000100000000000010000002000000400000001000080406000000002014880000000010000001001000420000020000000c000000802000a000000080000002000000000000000000000000002100004000002400000410040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010000004000000008200010208000000000008400800000000040200400000022006200008000010000410000000000000000000000000000000000000000000000000000000000c32c0000000000000000000000000000000000004800001010120110800408440008000006920100000000000400000000000001000000000000000000000000000000000000000000000000000000000000020040400000800000000000000000000000000000000000000009000010000000240000000000100000000000000080000000004000100000000000000800280400001088000000000000801080000000000002000808000000008000000000000000c10040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000040002489080800000000000004400400000010008200000000030000008000000000000000000000000000002000022230010149232100820000010000000008080800a000000000000000000000000002000000080004000000012014000000000000100000000002020000000100000121080000000001104000000000000000400000000000088000080200000108000008200000000000000004000002004100000000000000000000002040000001001000001080000000000004000000000100000000000004000000000000800000000000020040000000800000000020000000000220000000080a481000081000808000000000010200000000210040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (220002008000050901000800000810100000000000000008000000200000112000048802000100000461100008000108200000200001000000000000000000000000000000000000000000000000000000000000000000000000000000002baf0000000000000000000000000000000010000040001000120000020801020000420400000100201000000040000010000000800000800000000000000000000000010800000000000401000000001000400040000000000000000000000000000000000001000000000000800000000000040000000000000000000000000090400002004000404000020000020800000410000000000000000000800000000000a10040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0402000020482000004000000000000000000000400802000400220022080100502000002000008a100020801290800100000000000000000000000000000c0200002048040000400000020041000000040000000020000040000000000000000100100000000480040c050004200002100220000000000000000000000300000010020000181000400000011080008840000024900030a00000010000250004030000000200000000000000000000000000000100000000820000000000041010300000200000000442000000000000a840000200000209000110000000501000820800c040000020010300000000000000080404009100000000002040000200610040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010010000000006000401048400000010100600040000000000000000200000008000000000000010000000001200040001010000004000000100404040000804000400008040000000000001000010000000000000000000000000000000000000000000000000000000000000000898e0000000000000000000000001000000010820040400000b304000100084140184408400003000090000024000480800000000002080000820000000000020000010080000000000442400000800001190400008000022400000800000000000020200042000000000002130000c2000004080001000020000000000000000052000000000000a84004820000084900e10040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000040080000000021045000100060000000800000000000400008000000010004201000000082000000904040004001001100000000440000000000000000000000000000000800000c2100000100010f0020a00000000000000000000040400010000000000000000000000000040400010000020000000400140000000000000000000000000104800408000001000010000000409040400000008000400000000000001400000000000000000000000000000000000000000000000141000200000000000000000401104810000000010000000000000600440000000000200000000000008010204000000089000000004001248000110040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000010108000040000404200000000000100200000000024000000000000902800000004000888000000200050000000000000000000000000000000000000000080008008000201100001000002000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000b6330000000000000000000000000000000060014910400820400520810120010000001000000000000000000000010000000000000008000000000000000000000000840000400000020001000000001000010000000008000000000000000000000020010201400000000000010200000000000000000000124000204000910040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0042000400000800000080004000400000800000000a000000000002440001040000040000200000400000000000000000000000004000000020040100302000009000800000008000000290000000000c0000000000000000000000000000000004000003930000000000444c01900000000000000000000040c80000000000000000000000080000000000001010000000000c00400000000000000000000000040500800000000008040000000000000000200000000220808100000000000880400014400000000000000000000000000000000000000400000008000000000000000040400000000000000200000000000800000004000008000000400000510040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4000000000020001080020000040000080000000001000400001010000000000020e1000000000180000080000004000000060040000004021001000020001000002020020000000040000000800000001020000000840000001000040020020000000000041001000000000000000000000000000080080000018000018000000000000000000000000000000000000000000008bf100000000000000000000000000000000010000400000004c0500800000002000000000000480009000004000004240000000000100000000000000000000000000000000800000000000000100000005400000000001010000100000000000000000020000800000000100d10040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000000000208008000200000000008010800008000000000000000000000080002000000000000010000100000002080002000200100002008200000000000000000010000000404000000000000000080000002000200200004000408080008000000000000000000000000080000000000000001000400008000000020c00208000210180502000000000000004800000000000000100002000000802010000000020400040000000000000000500000000000000100400000200010002000000002000d0020000000400000000000100800000000000000000000000000000008000020000000000000002000000000000000000000000001000310040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000008200000005204000000000004000000800000000000080000000001000100000000000000000000000000000000001000000000000000000000000000000000000040841001008000100800000000040000000200000000000000000000800000008001000001008000000000000200010500000000000020000020000000000000000000000000000000000000000000000000000000000000000000000000000068de0000000000000000000000000000000000000000000000000000000001000001200000000000000048000020000008800000000000200000000000000000000000008000000000000208000008000000200020000020000000b10040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000200200000000000040000040000000001000000000208000000000000000000000001001000000000000000000000000000000000010000000004000000000104100000000000480000000010400000000000000001000000000000050002000080000000091000080400082000000010100010000000000400000000000000000000000008002000002000d4800400000000000000040000000000000000000000000000000200004000000000800000000010120100000000000000000000000000080000000000240000000028000000000008000000000040000000000000000000801000000000000000008000100200000000000000002080000710040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000080100001100000000400000010020800000000080820000000120400000000000210400000000000000000000000000000000000000000000104000040100104000000004000000000000040000000001000000000004042084100000020100000000000000000000000000000000000000080000000000100000080000000000000000000010000000000004000004000000080000000000000000000000000000000000000000000000000000000000000000000008d580000000000000000000000000008400000210000000000920000040000040000041200000908808000008020200000a00200000000008000000000000000200000200000208000f10040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000001000000000000000000000000000001000000000040000000000000000000000000000001040000000000000080000000080000000000208000000000008000000000000400000000000000000400000000010000000002008000000400084000000000000000008800000000000008000400000000000000000100000000000000000000800804000000020c0212002000008210000200001041011080080000000000104000000000002000000000400140001000211082040000000000000000000010200000000000020040020000001000000000000000120000000000000000000000440000440200000090040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000008000000000000000040000000000008800000200000000000040000000000000000010000000010000000000000100000000000000100020000000208800000000000800000080000000000000000000400000200000000210210000008008000000000000000000000000041000000000000001001000080008000000000001000000000001000000002000201001000080004000200200000040000000000011000000000000000000000000000000000000000000000000000000000000000000000ccd00020000000000000000000000000000000000000000000a11000440011040001020800001201000840000000000000000000000000890040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000820000100800000000000400000800000010000000000000000000000000400000000000110400000000000010000000000020900000800404000800000010400400000000000000004000020000000000001400000000000000000000000800000000020000000060000000000414008240000020101000000000000000000800000000000000000a04000008808200140001000000210608000000020020000010200400408000000008400000000000014000000000000020000000000011000000000000020000010000600800000000000400000800000000000000800000020000000000010000000000000200000000000000000100000000220000490040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000400000000000000000000100000000000000080000000000c000100008000000204080004000000004000000100000000000000001001000040800060000000000000000000000000000000000022400000000000040000029040000801001650014420040020400000020000010000800000000000000200400000000000000000000000000000000004000400000000000008400000000000000000200220000008028000004000000000020000000800000000000001001000000000000000000000000000000000000000000000000000000000045b70020000020000800000400800000000010400000000000218001020040408010200000c90040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000021002001000901080000000000000000000800000000000080000000000000800000000000000000000000000000000000000000000000000000000000000000000000020800000800000000400000000000000000000000000000000020000000008041000008020000200040000000400000000000000200010000008200000008000000010000000020000000000000000000104000000000400000008000200000000000000000a084000000100100000101004000000004908a0210010482090000002010000000051080000041000080080000000020002000000800800000400000200048400000001820000802000020000210000000210400000290040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010400000000000000000c000000a0c100000000004a28000000200000000000200000004000000000100000000000000000000000000000000000000000a280002000000000000000000000000040001002001080000000200000002000000000000000100020040000000000280040010000004200011414450108a000100000000001004000000040000a90080008100152202000800a02000000010140000000080000000400a00022315000200310a2800420009000000040c14400028000000000440000010000001000000000000000000000000000000000000000000000000000000000000000000000103a0050000010000400000000400000008400a90040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (81b0000000000000000000040a0000030030108c00c0040040d20041010c0040401000010000010400400000280008000008008000000000200000000000000008000008000008200008000008008400000000000000000000000000000800000008200000000000010000000000202000000400000005100800000000004100100000000001000000000041140104000104102408000000000000200000040000c0000000040080008348a0020001000020005000002020808000001040010000000000000000000000004000010410449401410000c0008001040000000000000000024000100000000000000800010000000000041000100880004100040000690040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000000000000180000000804800080000000020000000000000000800800280280040000000000001408000000000040060010000000000000000800200000000008000000000000000000000000000000000000000000000000000060000000000080200050200000000008000400000000000000000000000000001c000000010000002000800000000004010000000000000000000000000800000008008000000a80280800200006000008008000000000800000000000018000018000900000800030000000000007828040a00000c000000000000004160000400000000000000000000000000000000000000000000000000000000000000000000e90040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000760a0000000000000000000000000000000000000404920820000a028022010a0020000220428000004800080210000000001002000000000000010000010006c030000000000c0240010010004006001001c000000000000600000000000000000100800400000000000010000000000000000000014000000000000008000000000000800640000000010002000000000000800000000000000000000000000000000000002018000000038001800080400020008000000000000200118006000000000000000000000000000000000000000002050080022081000000000000000940e400010310000000000000190040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000020000000200400000000000000000000010000002000000000000214000002802000000000000000008008000200001002494000000080036d00000002000130000100000000000004000000000010000000000000000000000000000000040000000006000000000000100000000014001000800894000000030032d0000000200033000000000000000000400001000000000108000000001000300000000000000000000000020000302094000000008006d000800008008b2000000000000020020000000000000802090002500000000500db400000002800ad0001400001402000000080000c04008080000000000000000000000000000990040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000404000000000000000000000000000000000000000000000000000000000000000002f2100000000000000000000000000000800000000000240200008888001404094200800a00226d00000000500cb4000000004006d000000000000004000000080025100040000009b400000001008ad00000000000420000100000000000000002802494100100030014c0400800000000000000000004000000010000402a94000000034092d000000034021b4000000004004002000100000000000000000000000000002102494000000010456d08000000d005b4000000804404000040000000000000000000000000000000000000000000080000040002a0000590040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000100400001100000000000000000000100020000000000000000000000000000200000020000000502020080004008000000000000000080080000002000200000000000000000000000000000000000000000000100000000004000080000000000000000000000000000000000080046008000000001000000000000000000010000000000000040400000000008000000000000000000000000000100080008000000000000100400000000000000000000000000000000000000000000000000000000020020000000000000000000000000000000004000000000000000000000000000000402000000000000000000000104000d90040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08408403088a12211210080808000008240000408041200000000000000000000000000000000000000000000000000000000000000072a4000000000000000000000000000004000000000202411000080090400000002020002022000000000000000000000000400400000000000000001000000000400080000010000000004000400000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004800000800000000000000000000000200000000000000000000000000000390040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08501028000408200000000000000000000000000000000000000000004402204080090000000000000008401000098020000000000000080040001008000000000000000014882200240080000000000000004004000140120912090408408402402a102102100a00084286184000000090080000000102412440000000000000000000000000000040002010484800000002402000020020086490c021014040840840500521021021022004840840840000000000840000040080204a450000000090c90100000000000800000000044080000a02404885184040042102182100800a8618488400000002404000000000001214002842810210210040098400b90040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000100101000006102082100a002840840840800061021021a080820000408140000808024000000000000000000000000000000000000000000000000000000000000000061f40000000000000000000000000000210080002000004102804222128110880408608503084612a10210110148408408402804a10210210000000040218000008810a11210110228628618401001218610210080028210408000000000000000140220418618405001210611210000000000010000802000100040000c0220408408408800a10210210020088408408400802000100240000000000000000000000000000200010408408402814a10210210220228408400790040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (d0018408008604008210210210200018408408400000a00010200000000000000000000000000000000000000000008404400200110000000000000000400400092000000000000000280060000000000100000004000012800000200140000000000000004004000120101000118408008400008610210210000010018628000000008008000000000200a02000000000000000000000000000000000000008500000000200220000000008108a4010021840800840840061021021000000000840800000000040800000000008209a42000000008001020000000100080000000002400000120018418088400000a14210210020068218408400000000000400f90040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (090000000000000000000000000000000000000000000008000004100000000000002000000000000000000000000000000000000100800000102000000000000000000000000000000000000000000000000000000000000000f2e5000000000000000000000000000000000000000088400080422402000005840800840a001610a10210020018408408400400210210210000020010428000800618209210000208408628400004a10618610000000000428000000000000000010018418008400000800210200000000000000000800000100000000000184080084000002102102100202e8408408400408400110210000000000000000000000000000000050040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000420008000c000000000000000000000000000000000000000000000001000000000000001000000280000008000001000000000000000200200000000020000000000000000000000000000000004000000000000040100000000000004000000000000000000000000000000000008100000000000004000000400400000101000000000000000000000000000004000000000000000000000000000000000050400400000001010080000000200000000000000000000200000200000000400850040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000010000000800400030430000000000c00c00000000430030000000010000000000000008420020220000c00c00000000030030000080000c00c0000010000002002200000001000000000000000000000000000000000000000000000000000000000000000065e8000000000000000000000000000001021000200010100080002002001000000000000800000480100000000000000000000000000000000000000000000000000000000000000004000000200000000000000000000000000000000000000000000000000000000000000040000000000000000000800008000000000000000000000000000000000000000000000000000000450040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (030000000000c00c00100000030030008020000000c00000000000000000000000000000000000030030020000000c80c00002000030030010000000000800000000000000000000000000000000000000000000829000000000000000000000000000000000800000000000000000000000000000100000014000000020000100000000000000000080080000000400000800030030020000000c00c00800000030c30000000020020000000000d00900000000000000000000000000000000000000030000000000800800040040020420000000400030030000000000c00c000000000300300000000000300000020000082080000000002002200000000000c50040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000042202428000000080c090000000000030000000000c40200000009009800840480400021221028000001870840000000400c4000000003110120028244002002100801000084084208840422112100000000004080421200010015000000000000000000000000000000000000000000000000000000000000000df4200000000000000000000000000000000800000010004828020200a00000000030030010800048c24c00000000030030020008000c00c00000000000c20000000000c00c00000000830830000000020c00c00800100c10020000000000000000400000030c30080000000c00c000000000004000000000020004000000000003000250040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000002000000040002b0090008008405003000210210080000008408400000000010200000000000000000000000000000080090008008401021000a142100401000084084010000000102000000000000000000000000000000000000000000000000000400000000000000000040040000800a00000000000000000000000000000200a000880280008b28002002000000000000000080080001004015001000800840280000021021008000000860800000000880900008000022022200000000000000000000000000000000080082800000000022020000200200925844002001000800840000200021021008004000840800000000000900000a50040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (86425148000052190945203060000000000000c1828200000043060a080000010c18000000000030600000000000c18521909452030614864251480c18521909452030600000000000c1828000000000001486425148000052190945200401486425148000052190000000400a000000000000000000000000000000000000000000000000000000000000000000000040fc00000000000000000000000000000200a000a8005208ca2890008820a12900481085210a428221ca1028010000840840400500021021000000000040800a004408a0921015004002860840340040021821000002000040800000000000000008009000804840400000121120000000650040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000c18521909452030614864251480c00000000000000000080000010000005219094520000148642514800005219094520000148e40000100000000000000000000000000000005219094520000148642514800005219094520000148e400000000000000000000000000000000000000000000000000a08000001000000000000000000a08000001000000000000000000000000000000028200000040000a08000001000000000000000000a080000010000521909452000014864251480c18521909452030600000000000c1828000000000000000000000000000000000003060a000000000c1800000000003060a08000001000052190945200001400e50040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0003aba820100440100004c0ddd36440001383774d9100004e0ddd3647aba800000000000eaea080413511baba804211884655550000000001555400000000055554c0ddd36455555393774d9155554e0ddd36455554000000000555518842000000c21303774d9100004e0ddd36440001383774d9103034e0dc000000c00200000000000000000000000000000000000000000000000000000000000000000000009c88000000000000000000000000000000008200000040000a080000010000521909452000014864251480000521909452000014864251480c18521900000030614864251480c18521909452030614864251480c1852190000000000000000150040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (55555383774d9155554e0dc00000000000000000055554c0ddd36455555383774d910000000000000000000000489520000004c0ddd36440001383774d9100004e0ddd3644000138374880000000000000000000000000000000004c4ddd36444445383774d9100004e0ddd3644440138370401f00000000000000000000000000000000000000000000000000460000000000000001540000000082000000000000001540c0000000000000181cb8c00000004110a011800000000000000000000100440100004c0ddd36440001383774d91eaea4e0ddd3647aba8000000000eaea18a2000000000000000000000000000000003aba8401080000eaea00000000950040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000005455a010800001515000000000054542010044010000480e3dc63800012638f718e0000498e3dc6385454000000000001515080413711854540421188466a6a0000000001a9a80000000006a6a480e3dc639a9a92738f718e6a6a498e3dc639a9a80000000006a6a18842000000c212038f718e0000498e3dc63800012738f718e0303498e2000000e0000880000000000000000000000000000000000000000000000000000000000000000000257700000000000000000000000000000000000091800080063008002002004c0ddd36440809393774d9100004e0ddd36440001383774d9155554e0dc000015555303774d9155554e0ddd36400550040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (498e200001a9a92038f718e6a6a498e3dc639a9a92638f718e6a6a498e20000000000000000006a6a480e3dc639a9a92638f718e000000000000000000000018046000000480e3dc63800012638f718e0000498e3dc63800012638980040000000000000000000100000000000484e3dc6386c6d2638f718e0000498e3dc6386c0126388000000000000000000000000000000000000000000000000001100000000000000000001540000201540500000000000000040c00000000000006a9cb8c0000001a110800800000000000000000002000000000000480e3dc63800012638f718e1515498e3dc6385454000000000151518800000000000000000000000d50040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000151500800000000000000000000000000000000000054001080000151500000000005454030480028000064308031c8000198c200c72000066308031c8005400000000000151500c120a1205454c52600848006a0000000001a9a80004000006a6a64318031c801a998c200c726a6a66308031c9a9a80000000006a6a00c5200000000190c200c72000066308031c8003d98c200c72000066308808000000020000000000000000000000000000000000000000000000000000000000000000000007792000000000000000000000000000000008000b50000e004310844210320480e3dc6380c0d2738f718e0000498e3dc63800012638f718e6a6a00350040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20e72000066308031c8000198c200c72006a6630800001a9a990c200c726a6a66308031c9a9a998c200c726a6a66308000000000000000000006a64308031c9a9a998c200c726a6a0000000000000000000080800000064308031c8000198c200c72000066308031c8000198c200800000000000000000000000000000000064308031c8000198c220e72000066308031c8000198c2000160000000000000000000000000000000000100082200000004800080000000000000000000404080a8000000000000000000000000000000000a6b4c0100c0c001081000000000000000000000010400008300064308031c8000198c200c72001566308031c85454000b50040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c190000186c883064c0ea61b220c193aba8000000000eaea008140000000000000000000000000000000303a8021580000eaea0000000003aba80205801290000603220c190000186c883064000061b220c19303a800000000000eaea008164a527aba8c42700949c055000100000155540004000005555603320c193015586c883064555561b220c191555400000000055550085600000000180c887264000061b220c190103186c883064000061b2210801000000000420000000000000000000000000000000000000000000000000000000000000000bd8e000000000000000000000000000000000000250000c0c03148842a000064308031c80c0d98c200750040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4080800150c70b0000603221c990080986c887264000061b220c190000186c883064c05561b2200001555580c883064555561b220c191555586c883064555561b22000000000000000000c055603220c191555586c883064555500000000000000000002949000000603220c190000186c883064000061b220c190000186c8828490000000000000000000000000000000603320c190000186c887264000061b220c190000186c88420100000000000000000000000000000000001000804000008040001100000000000000000080061054f000000000000000000000004200000002a7f4c2200c0c021580000000000000000000000020580129300060322000f50040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010000000000020000008000000a000000000000200000080000050000000000000200000000000050020000000001400000080000008000000000000000040000000050100000000001600000000000008000000000000200000000080008000000000000200000000000000588000000000014208000000000080000000000000000000400011080000000000002000000000010080000000000400000000000000580008000000016000000000000580000000004016400000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000007a3b0000000000000000000000000000000008006706000d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000002000000000000000000000002000000000000000000000000080000000000000000040000000500000000000014000000000000000000000000000000000000000580040000000214000000000000080000000000002000000000000580000000000004000000000200580000000000002000000000000000800000000000000000000000000800000000000560000000400000800000000000000000000000000800000000000160400000000020800000000000020000400000000000000000000000000000000000800000000000020000000000000000000000000020000000000000010000000000020400000000005800000000000020000000008d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000000000020400000008000010000000000000000000000000010000000000000400000000000010000200000000000000008000010000000000000000000000000000000000000000440000000000000000000000000000000000000010000000000000400000000000010000000000008400000000200010000000000000004000000000000000000000000004000000000000000000000202004000000080080100000080000004080000000000000000008000004200000000000100000000002004000000000000100400000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000084d50000004d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000b95300000300000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000800040800000000021000000000000040000000002000100000000800040020000000001000000000000200408000000000000000000000000408200008008010000000208000400000000000000000000000200400000000000010000000008030400000800000210200200000000000000000000000000000000000400000000000010000000000000000000008020810008000000000000600000000000cd0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010008200010000000000000000000000000000000000008000000010000000000000000000000000000000000000000000000000000000000000000800000000000000010000000000000000000000200000000000000000000000100000000000000000400000000000000000000000000000000000000000000000000000000000010000000000400000000000000000000080000000000002080000000000000000000000000000004084100000000100100000000100000080100000000004000000002000000080080000000000000000004000000000000010003000000004000000000400000000000000000000000000000000000000000000000002d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000da9400000000000400000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000001000001000000000040000000000000000000000001000000000001020000040000000000000000000000400010000000000000000000000000010400010010000000000410000000000000000000000000000400000000000000000000000010004000000200000400400400000000000000000000000000000000000000000000000000000000000000000000ad0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080080000000000082000000000001001000000000002080080000080001000000000002040080000080080000012000082480000000000001001000000002040000000080082000000000002000040040000000000002001002080040000000001000000000040000000040001182000000000000000080000001001000000002002800000000000080000000040002000000000000080000000000002000000000000000800000000000000000000000000800000000000000000002000010800820020000020000000000000800000000000000000000000000800000000000020000000000000800000000000020000000000000000000000000000000006d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005c72000000000000000000000000000000000004000000000000000000000000080000000000000040040000000000000000000000000000000000000001000000000000000000002080002000000040000080000000080000000000002000000000000081000000010000000000000020080002080000082000080000000000800000000000000000000000000a1000000000002000000040000081000000000800000080000000090020000000102040000001000080001200000802040040000040021000000000000040080000ed0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004000000000000900000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000c000000300000000000000000002000000000000400000010000000000000000000400002080000000000000000000000000080000000000042000000400001800000000080000000000000001080000000000002200000000000000000000000000000000000400000000000000000000000000000000800000000000020000000000000000000000000000000008000000001040040000000000000000000000000000000000000000000000800000000000020000000000000800000000001d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004102800000000100080010008004000000000000404000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fa9f000000000000000000000000000000000000000000000000000000000006000002000080000000000000000080000000000002000000000000000000000000000000000000000080080000000002000000002000000000000000000000000000000080000000020022000000000008080000100000000000000000000000000000000000000000000000000090000000000820000000000000000000000002000000000000800000000000000020000000010000000008000002009d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (11000000080805000008000000002a000000050000400000800000000000000000000800000801402000000000800000000000020020040000000050800800000800000000000200000000800080c0b40820000000085000800000000000002002000005080000000080142000000000005000080088a42a0000000200200508038000000000200000000c028000000080000002000000080000000080000000a0000000000202d000040000800000000000280005000840000200140020000008000000200000000000002080000080280000000000001400010000000000000000000000000008000000050048000000000000000000000000000008010008005d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000400000003000000000000080040000000000006214000102040010000000c821042000481200040020000001020000000000000000000000000000000000000000000000000000000000000000000000000000047d8000000000000000000000000000000000002000000000000000000000000140042000080000080000001100a0000000000000000000000020000000200000000000820000104214000a0000000a800008000220000000100000000500c000001000b42009000100000008000004000b4020a00000008000008000000000140020000200000000040009040140105000000005000040000100002000000001000001080000080038000dd0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000003020000000000000000081040849100000100800081401010040040e400001000001520000000000000200000000000000000000000000000048008000828000000000000000000000000c000000000000000000008000000000001004004040100100100008080000000000002000000000020840000500000081000410100011004001000000000000000000014840000001000000000300000000000000000004000000000000008000000001000000000010000000000000000000200004000000014100088004000080000000000000800000000000000040001400001080010000000000000000000000000800000010104001040440001083003d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000200144458500000002110484060004090618300008000000000000000000000000980050198004044000800480009058041102000000000000000000000000020000000000000800000000000000000000000000000000000000000000000000005d05000000000000000000000000000000140000000000000000008000000000000000000014000002000000a000060200000000000200040208000000000008000000000000009060004201003000000000000010000000080000000000004000102000044001044001001000001005020000040004400000082c000094004000000004000000000080000000000210004200000012084000bd0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000804920005860120126840000010804d8000000000000000000040004690a2003000051208c000200034882100b041021925800000000000200000000000000000000000004000000200020174000200000000000010001828431c00000000000010000000020200400100000800070000000020000c0000000000000000000002001000000000086000000000002010840000000001000000000002002080006000400000000072000000000000000080041000000000000000000000000000004010000010006000000080c20100000002013080000004080680000000002000180000460004801820000960101000000000000000000000007d0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8020800000001004800000200000040000000800000010000080006400004000400208400405020104010490002000000010000000200020001220c06200400108c10000000408a20206010030400400000010400000000000000000000000000000000000000000000000000000000000000000000000000000dd770000000000000000200000000000000000000000000000000000000000000806010000000000000000004004022001809b001000800000000000000000003000000010000668040051000049e01000000600000008061600000000201258011044048045001000010000000411b480480c5000000000203100000001000080781000000000fd0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002000820003000004c4000800000002000000101020080000800000000000120000010000810800040000000000000000081010a400030000008210002400880208220090048a04200000000000000000400000000000000000000000000000028004200010000000000000400400000211000000000000000000000800200000004000208000000010000200c20000000000000400000000200000000030008010000020800200000000820000200000000000200820000040040000000048000000000000000408000000000000000800000000000000000200000000000000000008000004020000200000012020108000000000800200020000080000400030040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000c00000000000010000000000000084000000000003000000200000008000000000000000000000000200220c8841000030040020080000000080000000000000008400000812000120000020800022800020020001000000800900020000000000000000000000080000000000002000000000000000000000000000000000000000000000000000058b800000000000000000000000000000010000000000000000000800000000008000000000c00000400000008040020000000001000800000020000000000000000000830000000440010000000001000000000020008000000000000200000210000048000000026004000830108000148000400830040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004cc0000022000100040000100000cc2000100100001000004000010040c20000820000800081000145000c00040040000230002020000000400000800040000040000800420a04004100080028041080040000910949004000030000020000000000080000000000000000000000800000000080010000020080800000020000000038000820000000000040004080010001008040004c40800000080830000000000000000000000000030080000000000c000000000000300000008420040000000000000300010000000080000000010801000040010080004000c00020000000000000000240000000000009200000000020004000000000000300000000430040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000080000000000410000000000012480000000000410000000000000400020000000000000000800000000000040000000020000000000000000000000928a1000000000000481000000000002000000000000000002004402a8200040000500208104000254148210008000200008400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2210000000000000000080000000000001000000000000000000000000000020c0000000000000000000004000c0400800020802010800100820000000000020800000000000410488000810100003000020200400004000400000000300000000400c30040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000000000020040000810000820100000000002000020000024820400001000120810200000000101204000008000800402080000008000000000000008000000000008004000000000000008000400000210008001500002000000414060104000000000208100000000000000000000000000000000000008200000000000200100000000000000000000000200100000000000000000000001000050008400041200000000001468000000000000000000000000248000000000048200000000001248008008000000000000000001040000000000000000000000000000004080400008000000000000000000000000000000000000230040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02000040000000000000000020000000000000c008000000000001000002000004050000000002101400000000000040000000000010010000000000480800000000001002000000080000000000000001110002000000040c208000800000911000000000000000000000004000000000000000000000000008000200200400000030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef6100000000000000000000000000000000000000000000000000000000000100008200000000000000000040000000000000000004000000000000000000000000000000000040000040000200000000a30040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000000000110040000000004800080000000000100000000000404200000000130300008800800000010000000130100200000000004000000000200101000000000000020000000000101080000000044040800000000001000000000000000000000000143000000080c2c24000008000210900000000000404000000000000000000000000000000000000010008200000000004000000008000000200000000404000000000000000000080000004000000000230100008001000405000000000000000000000000404000000000010148000000008405000200000020000000000000405000000020300000000000000800040000000000300630040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000020000820000000000000000000000000000000000000000000000000000000000000000000000048010001000000800000000100000000002000000000000800000001000000000000001038000401000002000000000000000000000500002000000001000000080040000000002080100000000018600600000000000000420400080000010000000000014000400100000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000008bce00000000000000000000000000000000000000000000000000000000000010100000000000000000000000120000000000804000000000000000000000e30040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00140000000080000080000000000000000000000000000000000000000020000000000000000000020000000000010000000000000000008000000d0080001000080000004820000000000000000000001208208280000821020010000000020108800000001000000000000000200000000000040000000201020800800100040040000001200000000004001001000000000000000000000000000000000000000000000020000001108040000000800800002000040030000041400000000000000000000000000041000001800000010008000440200000000000000000000580000040040000000001001000008000000400a00000200000000200000000130040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (002100000000002820012400000000000000400000010400000040a0040008c8000010800000000000000000000000000000104000104000000010001000200010000400020000000200000808000000000020000000000000009008000001000000020000000005000000000000000000024000408000000000000510000000000010410000000000000000004000000120000020005250000000040008000200800001040000000000000000000000800000020000000000000800000000000000000000000000000000000000000000000000006500000000000000000000000000004000000100100000000000040000000014010001041240004008080000930040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000200000000000000008204000000100000410a12000000000010000000000000000000000000000000000011000440000000010428c024100000001000000000000020010004004000000000000000000000000820800040000800000040000000000510501400000000008000000000000000000000040801209000000000208000000000040000000000804008000000021020500000200000114000000800c00500000000000000000000000040000000000000004000000000040420000000000000000000022100220020800000000000000000000240100020822108000004080000200000400001000000000000004000000000000014000000000000530040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000050100000000000004000100020000120020000102000010820000010010000028800081022080000020040010c0000000400000000000004208400000000004082000082000000000080000480000080200011082000001000400000001000010200000010000045010000000800040000000008002000000000000040000010100005200000021000100000000800004000104000000000000000000000080002000101220008030020008128c0444800103000400004800000020000204000000000000000000200000000000000000000000000000000000000000000000000086c300000000000000000000080000000000000040000000000000d30040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000180000000000000000000000004010000008000000000020020800c00000000002000000000000000000000080000020000000800080080800000822020420800480004000c30010400100000020020040020a2240200001000201041000000001000020010002000000000002000802080084010024030480402400c00020402130c28400440004000200000000000008000082006020800800c10130840028820a04820800000400120830800000000000200000080000000000000800880800820080100180802002000020a00010030120800400000000000200000000140000000040004000000810480100400000001000000330040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000808400000000001010000000000000020000000001018800000000010420000000000010000000000000201208400000840000001090000020000000400200000000000810000000000000000000000800004002000000000100804000010000220000000400010800000a00000420210000400000000800000000000000040000000000100000010404200000000000000004100000204200000000800100000000100000000000000008000000000000048000000001000200000000000248410800000000200000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000a25000000000000000b30040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000651b00000000008000000000080000000000000000000008080044000000000004000100010008000000020000000000000000000001000000000100000000020000061000000000004000000000002008000100000000000c3400000010000000000007000040000000000000400000003000800000040000002000004000010080000000000008020120000010000904000000160430402408000200000000100000010400000004000000000000120a20010000404020000000000100000000000001000400000000000000000000005800000000010008400800200000022c00000000008000000000100200400000000008000000730040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (002088000000000002000000000000080000000040000002029004a00040220000000002000001001200040040240a61021825808a28000200a2000000240002086002018210002000100000200000000000000000000004002000000000000020830008000200000000000102204048000820000a0080080000401482008801000220010001400008000800210000022288000000001020100000004000100000000000020004100500100d00000020104004000080800000006400000004000000000000100000004904520000010034800200020110030120000010000030000000500000020000000000000000000000000000000000000000000000000000f30040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000003fa300000000004000000000000008000000000400000000080040000000004100000000000828000000000000040000208000000000000000000200000000000000000000000000001002800000200008000100400000000004000400000000004100108028a28000000000004004104148008000004000004000002008040080008000008080040101104004086005040004000000000000240001004000001000000000000000000208048006110140008208208008008000000000208308000000000000000000000000000000048000009008208800080200002000000000000100000b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000240000000000000000000000014c00100000000000100000000000300000400000000c48002c10c200402100008000000000000004004100000100100510008214200208002000408000004000000008008001000008000000000000000000410000000200000008000000000000000000000002800000000004001000104001003000004000000102000002200000088200a00000000200a280000200000c300800002000000004000100000000000000000000000104000080000002004100100080401003000110000000000000000100004484000104104102000000100000483004000004002000000000000000000000000000000000000000008b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d6e0000000000000000000a000000800800000020c200004000004000000010400300100000000008000040000200000410020000042000000000000000000000000082000000200000814800000400020000000000000000000000000200200010400484010410200000000000010410484000000010000010000000044104040000000000080000000000002042000000000002800000020000000000000000000000000000100080002100004020101000000004000080000000000000000000000020000000000000000000000105020004b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000010000000000000000001000000000000000000000000003028000000000000000000000000008010140005090200200040018002000000000000000b80200008028010010000000100a80480029000000000000000000a80a80028028000000000000010001000000400008005000000000000000000000000080000000000047000000004004000000140000a0000001500001001400004080040000000500000000000000140000014000000800000000000000000000000400080002000c0018004000000000002802000400000000000000000000000200000008000006840001003001201000281000582800040400cb0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (002020080140000000100140a0020008000100800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f2e20000000000000000000000000000000000000000000000000000000020000000000800000000000008803c00000020040100000000800000000000000000000000000000000000000000086050800040100000000000804008000000010354000000008000aa028000a0200000700a000ac0a0000000000102800012010000200000a00000000000024010000280104c800800280090000020000404000000000000000040080000001000000000000000140050000c0100002140014008002b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000080010000200000142a00000002000000000000000000000000000000000000000000a00000000020000000000000000a0000001008500000000000000000000000400002000400024014000000002501000000000000000000000000200001001000000000008040000400000014000000000008008000000008000002800000000000000020002000020010000000000000000000000000000000000000000800000000000000010000000000000502000000010014000000000000000000000000000010000000000000000000000000080000000000000000000000240000080000010004008000000000c0000000000000003000200000000000ab0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000100000000000000000000000800500805002200a800020280084000000000800000081400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000026e0000000000000000000000000000000000000000000000000000000000002000200080000000000000080000005002000000000000080000000000000000000000000000140000000200000000040000000000000000000000000000000000080200000000300000000001010020a02000008000c0000000000000012000040800140000100001000000000000000000080000400002020002000000400000000000000001000000200000000006b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000400000000000000000010000000080000000000000000000000000080a00000000000000000000000000000000000000005000000800080000000000008000000000000000000000014000000000000000000000100001000a00000000000400000000000001000000000000000000400020001015015000a0000008040000000120000000000000008008000400008080000000002000000000000000000000000000000000000000080000000000000800080000000100000000000020000000000800800000000020020000000000000800000a0000000002002a00000000000000800000000000000000000000500600000010008000001000200000000eb0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002000c00020085028050002402402000440010020000000000000020810c0048082a10a40003022444000848804408828201000091220000000000000000000000000000000000000000000000000000000000000000000000000000000000000000092b500000000000000000000000000000000000000000000000000000002002a000400080000000000000080800000002000000000000000000000000000000000000000000000200000000000008008000010000000000000000000000008000280008000000880000000000140b481620201001800001400000000000002200000060000000000000800901e0009000012a0180400160000002000001b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00a00100040050400840121405400800000010000000000000000000102000080004000000000000004401100080044824050000102400000000000000000000000000000400000020010080010000401000000000000002080008002004900000000000000000004000400820004400140024020088000100800000000000000040048001401200100100088044040000001101420004000000000040040001401410020002000000000100000000000800140010020000000000000020000000000000800020002000200900800028028040020000200a0000040002402400000000020080010880000008020c001000000000002008000400104010000000009b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0020000808000000000000000040080000000000000080004400402800000200200000012000008000000000000000240004000000a9060000002060604084400a488828a004000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c61c00000000000000000000000000000000000000000000000000000001000c00088040000000000000020080001201000200000040000000000000000000000000000000004020000080012400a00800400000000000000000000008000c0020883080004808202240803005082a08a000842050020004000401000000004000500300800040002020005b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001010000000080809000400000000050000110000000000800000040100400280000000400000000000000000010008000000000000000000000000000000400480404000080000000000000000000000000000000000000004000008000000010000000000000000088001800010200000000000000000000000010000200600010400800001000010040000000000000004000800000100010010008004004000000110100000400000000004004000100100000000200000100020000000000100020000004000000000000002000000000000000400000000000000008000800004000000020020200000000800400000000020000000080000008040000db0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000011000000000080400000000000000400000020000000000000000000002040000080080080000400000000200000000000000000000020008800200022010081000800880010100402010000088020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d448000000000000000000000000000000000000000000000000000000008000000000000000000000000a0000001a01800000000020008000000000000000000000000000004000000000010000214000000000000000000020080010000200a0881000008000200200001014000a088000045040080004003b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000400010004400000000000800000000000000400000001000000000000000000000010000000000000a000088000040000000000001000000000000000000000000004000000000000000000010000001000000000000200000000000000000000000000000000000080000000000001000040000000000000000000000400000000000000000000000000000000200080100008080000000000000200000000000000000000800000000000000000002000001000000008000000000000000000000010050000000000000080000000000000000000000002000000000000000000000000000200000000000000100000002000000004000000000000000000bb0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100080000000000004000200000080080008000002000000000000005000000000020100000000000000000000000000000000020010003000040000040800030000100000000000004000000000000000080008000244810000000000420200004000100004000000080000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b0fb00000000000000000000000000000000000000000000000000000000400000010040000000000000000000002002000102800080000000000000000000000000000000000080000000006000000000100800000000000000000000002400080004000024007b0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000100800000000000000000800000100001c04000000220000000000000000000000000000000000040000400000000400000000000000000400000002000010000000000000000000000000000000000008000000000000000000000300200008002000000000010200000000000000000000000000000000200002001000000400000000000000000000000000000000000000000000000000000000000000000000000a000080040000000000000000000000004008000100400000000014084000004000000c0000000000000000000000000000002000000000000020000000000000000000400000000000000000001000000000000004000200000fb0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000002000c0000000008002200008004008000400000a00000200010028000030000200200c0000000003000088000a0000000a01002804000000000000000000000000000000000c014000800200400540002004010000000100000000000000000200100004328240004404329a040100044020100000002044281080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020500000000000000000000000000000000000000000000000000000000010000000002000000000000000000000000000000000000000000000000000000000000000000000000000008000048200000000000000070040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000400a0020010d4080280040080000000000c0200000000008008400300a0008030240500030091020200aa08020100000000000000000320120001002002000800000080000120003004444884a820200c00000200000040000000000000000000800040010000000000000000c00c000200c0020010000c00d000000000000000000000000000004010000000100000100000010000000000000000000000010002000000000000000c0000000000820000000041020020010000800c000000000000000100200014004010010000100100080480000024200000000000000080080004002100200a000000000000000000000000000000808000000870040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000028000000000000000000000000000000000000000008000001000028200000000000a08000001000028200000040000a0000000000000028000000000000000000000000000200000000000000000000000028200000040000a08000001000028000000000000000000000000128200000040404a08000001000128200000040400a080000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076ea00000000000000000000000000000000000000000000000000000000a00a0002c0480000000000000080280a000020020100082000400000000000000000000000470040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000200000040000a00000000000028000000000000a08000001000028200000040404a00000000000028200000040000a0000000000000028200000040000a00000000000028200000040000a08000001000028000000000000000000000000000200000040000000000000000028200000040000a08000001000000000000000000000000000000000200000040000a00000000000000000000000000a08000001000000000000000000a00000000000128200000040000a08000001000000000000000000a08000001000028200000040000a08000001000000000000000000a080000010000000000c70040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1030300000000000000001004401000000400000015c0c000000000000025100000000000000000000030300000000000c0c0000046000000080400000000002010044010000080001100400002010000000000000844000000300001000000000000000022000000000000000000000000201800cc00a02308800000000000000000000000000000000808220600840080621098000040c090806008400000400044000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097100000000000000000000000000000000000000000000000000000000000282000000400000000000000000000000000270040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0018800000800000000000000020200400000000000000000000000000000000000000000000000000000400110840c0c0120000000000188420000000006200044210303244430c0840021081000000d0d00548522548000014210000000000010011220100000008800000000005141220140000150048952000005084000000000000000000000000000008000000000000000000042000000040c00a27285c21000000000000000000000000000000000000020800000a2228000000000000000000cc00a222a10210000000000000000006288000005555398041100400015c041dc210000000000000000000010046000000000401100400000010044000a70040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0200000000000008000000000000200000000030300000000000000200000000000000400000015c0c000000000000028008000000000000000000030300000000000c0c0000044000000080400200000002010044010000080001100400002010000000000000844000000308001000000000000000055000000000000000000000000000000cc00045015447000000000000000000000000000000f0800070084000063109c000000f100c470084000001010442000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb350000000000000000000000000000000000000000000000000000000000670040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000010800110840000000000000030300400000000000010000000000000000000000000000000000000000400110840c0c0100000000000188420000000006220044210303244430c0840001080000000d0d0014046011800000401000000000002880060000000108000000000000108a600800000050018046000001004000000000000000000000000000080000000000000000000000000800000c00e0521540500000000000000000000000000000000000055014000040500000000000000000000cc00405021021000000000000000000620000000111039800110040001aa001dc210000000000000000000e70040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0310800001740018c2a000000000000000000010400000000000410000200000010400008000000000808000000010400008575700000000000000000000000000052800000000000000000000000000000808000000000020200000000c12000000000030480028000000a20000a00000030480000000c0c00c120000030300000000000000000000200000000000000000000000100002000008b26808a8000040230000000000000000000000000800300a8003c031488080000030490300a8003c4000084020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084d90000000000000000000000170040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000e01e000000000000000000000000000000000000000000000000000000000000a20210a80000000000000030300000808000c00000000000000000000000000000000000000030300000210a80c0c000220200000000c5200000000002000842a03034e453c88a80000000000000d0d070498828200001c1260000000000001000020000000000000000000070450021380001c000008080000704980000000000000000000000000100002000000004002080f00002300002000008b06980ac000000000000000000000000000000000000202a000008b06800000000000000000000008b06910220000000000000000000200000000000338800970040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (3000000000000000000020500000000033814218a400008a4518d2b000000000000000000020580019000000816004a40000020580129000000000108000000020580129575700000000000000000004200000002814000000000000000000000000000108000000000004219000000816000000000020580129000000814004a40000020580000000c0c0081600000303000000420000000000040025000000000000000000205000044000044051014d00000001000000000000000000000000080002cac002002158080d0000300d402cac10300020084090000000000000000000000000000000000000000000000000000000000000000000000000000000570040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000002cb50000000000000000000000000000000000000000000000000000000000000142142c0000000000000020200000108000804000000000000000000000000000000000000030300000214ac0c0c08000420000000085600000000002070852b03034e05758cae0000000080000d0d0112b41ad24000044ad00000000000229140a024000000000000000001101e0a6a46c6c4485029490000112b40000000000000000000000000100004400000004002010f00000100408400000e15905ef0000000000000000000000000000000000004153c000004150000000000000000003fc000415110200d70040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0014000000000040500000000000014000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000001000000002040000000000000000000400002000000000840d00025000000014000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000010000000000000000000000000005000000000000000000000000000020000000000000000000000000000000000000000000000000005000000000000020000000000000000000000370040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000010000000000000000000000000000000000000000000000000000000000000000000002dbb000000000000000000016000000000000080000000000002000000000000000000000000014000000000000080000000000016000000000000500000000000016000000000000580000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400004000800000000000000000020000000000000000000000000000000000000000000000000000140000000100000000000000000000000000000000800000000000024008000000000800000000000b70040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000010400000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000010000000000000100000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000060000000000000000000000000000000000000000000000000770040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c30000000000000000000100000000000004000000000000100000000000000000000000000000000000000004000c00c0000010000000000000000000000000010000000000000400000000000000000000000000400100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000100080000030000000000000000000000000000000000000000000000000000100000000000000000000000000000004000f70040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000042000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000d37b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000001000000000000000000000000000000000000000000000000000000000008f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000008000000000000000000200000000000000000000008000000000000200000000000008000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000002000000000000000000000000000100000000204000000000000000000000000240000000030440000c0000000000000000000000010000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000008000000000000000000000000100000000000000000000000000000000000004f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00060000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000030000000000000000000000000000000000000000000000000000000072b50000000000000000000020000000000000800000000000020000000000000000000000000000000000000000800000000000020000000000000000000000000020000000000000800000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000800c0000000020000000000000000000000000cf0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (800c0000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000100000004000000000000000000000020000000000000800000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000040800000000000020000000000000000000000000000004000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000002f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000000140804000000000000000000000000000000000000000000020100a000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000008000000000000000000200000000000000000000000000000000000000084bb000000000000000000002000000000000000010000000000000000000000000010000000002000400000000000000000000002000000000000080000000000002000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000100000000000000000000200000000000000000000000000000000000000000080000000000000000002000000000000000020000140100000010000000000001000000000000001000000000828000a00000000008028000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000808005001800000900a000000008000280000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086000000006f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000040a000000000000000000020000020000000100000020010a2000000000000000000000000000000000000000000000000000000000002000000000000000000018000000000040000000200500000020004400001000000000000000000000000000000000000000000000040bb00020000020000080000002004002000000001020000000020000800010000001000000000000040000080014002000020002d000000000040a0000000000802d008000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000800000000000000000000000000010000000000800000000000000000000000000000400000000000000000000018000000000000000000000000000000000000000040000000000000004000000000c2010001080001000001020000060000000000000000000040000000000003000000080000010000002000000000000080040000000000000000400000000000000040040000000041000000040000000000000000000000000000000000000000000010000000000080000040800011000001000000000000000000000000000000000000000000000000000000000000041000008200008001f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000100000000000000000000000000000000000000000000000000000800c2000000000000000000000000000000000000000100012c8040000000000000000000000000000000000000000000000000000000000000000000000000002001020000000000008401800000000000000000000000000000200000000000000000000000000000000000d6e6000000000000000020200000020000001088900000000080000840000000000000000800000000000000001000a000000100001001000000000000000004800000008010020000040000400000000000000000000002040000000000000000000000000000000000009f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (9a0000000000000000000000004000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000201760000000000000000000000000000000180000000000001e010002004000000000000000000000000000000800080c980009040020060000001000805a00040540100000000108010020000000100000000000080000000000000000000000000000400000400040080000000000000000000000000000000000000000000000001800000000000000000000000100000000020000060000000000000000000020000000266c04048001000800900801000000000000000000000000000000000000005f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8400000000001000000000000000000000000000000000000000000000410000010000000000000000000000000000000000000000000000000000080000000000000000000000800000800000000000000300000000400000000000000000000000000000000000000000000000000000000200000000000000000400000800000004000001201024000004000804000080000100100000000000000000000000000000000000002f930000000000000000180000000000000400000800000000000a40000000000000400000240100000001000020804400014100120180030020000000000044d0010010000000640480a08000008000000000100000080500df0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02004480208100008000004000080000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000001000000000020000000004000000000000000000000000000000000000000000900800020000000000000000000000000000000000800000001040021000000003000880000020820100400000041010000000000000000000000120000000000005100000080000000000002000040200000240000000000000000000080000000000000000000000000040000000000000000000000000000020000000000000000000000080020880020100004040410800000100040003f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (04003000001044300c01460000000030088800000000000000000000000000000000000000000000000000000000000000000808000400000000000000000000000000002880000000800000000c1000000000000000000000000000000000084000000000100000c00000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000004800008202000889100208000020800000000000000000000000000000000000008883000400000400010000820000004000000060000200000082804008000100000000000002010000000100000080000084100012000080000000000000002000010000000000bf0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (33000000000000400000000000032000404000204841000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000800000010000020000000000000000000000000020024000000000043080200800000000000000000000000000000000082000c020000020808108000000c00004220200200402008000084080040200000000001004000000000000000000000000000000000a28400010000000000000000000000400000000010000000000000000400000c0000081000004000000000000000000000010002000000000000000002007f0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000011a48505000000004000048010010080400000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000492000000000000000000000000000000000000000000012400000000000000000000000000000000000000000000000000000000000000000000000000000012400000000004000100014884000001000001040000000100904000000000000000000000000000000000003caf0000000000000002000000000200081040000000000000000000000000000000400000100200000000002040c0408000000000ff0040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000040000000000000000400008010010004000000100608000000000008200000000000008500040010000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000002000000000000040000000000000000000000000000000000002001000000000000000000000000000000000000000001000140000001000000000000000000000000000000000000002000000040140080020000000810001080000100000010100000000000002000040000000000000000000000000000000060001000000000000000000000040001000000000000000000000000000000001000000000000000000080000008040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000020200000100000008020000400000080000000000408000000000000000000000040500800010012000240020800480240000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100200000000000000000000000000000008000000000000200120000000000000000000000000000000000000000000000000000000000000000000000000020000100000000000000024100001000000082400041000000000000000000000000000000000000000000000c08a00000000000000001000b810084000000000400040000004110480000000000000808040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010000800000000400000000000000000000000400000000000001010000000000cc0c000200200020000000000204c000000000801001000080000000000000000000001000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000008600c0004002000000000000000000000000000000000101002000010000040000000200001000000000040000000000000200000000002008000000000000000000000008000000000080800000000000000000004002080000000000000008000000000408040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000004000004000000000000000000000000000002000000010000000000000000000000000000000000004000000000000010220001400004008000000000000000000000006000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000014000000000000000000000000000000000800000020800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010282000000000002000000010410002000000000000000000000000000000000000000f18f000000000000008000044400000000c08040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000da6200000000000000000001000000004000000100000000000201001000000000000000100001004080000000000000000000000000000000040000000800000000001000000450000200000100000000000000000000000000000000000000000000001000000000000000000000800000000001000000000000000000000002000000000000000000808000000000000000000000000000000000000000000080000000000000000021000000010008100000000000000000000000000000000000000000000000000000040040000004000000000000000000000000000000000000000000000000000000000000001000041000000000010000000000208040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100000000000000000000000000001040000000008000000000000000000000000100000000000000000000000000000000000000000000000000004000004000000000000000000002001001020408a0080201008000801402000000000000000002000040000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000400000000000000000080090a02090404000100000000000000000000000000000000000000000010000000000000000000000000400000000020000000000000840000000000020000800020000000000000000000000000000000000a08040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000006d1b00000000000002000001004100000000000000000000000001001000000000040000000400000010000004014000001001042d00000000000080000000040002945008000000031000000000000000000000000010000000000000000000000000000000000000000000000000000000000001000000000000000000000000000020000000000000100000004000000000004000000000000000001000000000000800000000001000000000488080000000000000000000000000000000000000140000000000004000000000041080000020000408000004100000800100000000000000000000000000608040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0410000000010000000000080000000000000010000000180000000000000000000804000000006000100000000000000080000090000000000000000000000000000004082000000000000400000140000400000000000000080000100000020020880000410a10002000a000000080000000000000000400000000000000010000800000000200000000000000000000000000001000200000000000000000000000001000000400000000000000000000000000008000a0208000820000120108804108201002040000000000000000000000010000000000000000010000000000000000400000000800000000000100000000000000004000000041080000e08040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000441000000004001401000000000001000000000000000000000000000000000000000260c0000000000000000000000000001000000800000004004800400000004000008000004044000001002002100501000082082212000800000000000200202088202001002240408480080008000000000090000000480000000000000000000008000000000000000000000000100080100100000000000004000000000001000000000000000000012000001400000030000100000110400000000200000000000000000000000c110000000440120040000080000050000010000880000000000040000000000001000000000100044000000000420400000108040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4000008004000010000000002000004000000000000001000000000002020000000000000000000100020000000000000000000906080000000000000000000000000020020020020100000000000100000000000000000800000100000000000008000000008000000100020028100000120000081282000000002040000000010000000000000000000000000000000000800020000000020000000000000000000000000000000008000002002020001000081000000000040000000000000800020000000000041120208800000000000000800000000004000000000000000000000000008000000000000002000000000000000000200000000002000000908040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0200000000000000000000008000000000002000000000000000000000000000000000000000000000000000000000000000000000000000a6b60000000000000200000000410008400001010000000001001000000000400000000010800800420820000400481000000000210001000800008000000000000210000000000000000080010000000000080000000000000000000000000000002000080000000000000000000000080200090000000000002000000000000400002000000000004000000000000000000000000000010400000000500000010000000000000001d108020020000400000000100000008000008000280000000000041000000000508040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2010000000000010000002080002200000008000002100000100000100000008000028000000000040000000000108000008000000000000000000400000000000000000800012080000010000400000000000000000000000000100000000000100000000000010000000000000000400000024000000008000000002000004080086000040000402000401060000040000000000000000000000000000000000000000000000000000000000000000000000000000000000402000000006001000002000042000100000000800000000000800020080000000041010000400400400008000000000000000000000000000000000000000000000000000000000d08040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000100000001000008008000000000a002000000200000080002000080000000000000000000000000000000000002ba00000000000000000000340002010000000000000020020404000000020000000000024024800100120020800000000020100020000000028200000000800a20000200020820000400000020000000000400000000800000000000000000000000000000000000000000000000000001800200000000000000002000000008000000000000000040000000008000000300000000004000000000000000000000000000000000000000020020000080800000000000308040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002802802000c00000000090040000000001000000000000004000000820000800000000000004c00010410400400000010004010000000000002000000000211000010000000000000000100400010400014000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100da0000220430800820400100010000821000020800000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000080005000000000000000400400000000000000000000000000b08040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000004000120000000000000000000000000000000000000000000000000000000000000000000000000000000000000008400000001000010180040020008000000001000000000000000000000000000000000000023bb000000000000000000000200008800000000000000000000100140000068000000000000000000240000000000000000004000000000040104000000000004000104000000000005000000000000000000000000000000000000c0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000400708040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000001010000000000000000000000040040000000000004000020000c00000000000000000000000000000000000000000080880400000040048010000000400210010000a00140100800015028010000000000000000000001000000000000000080000000002001000000100101000000000002000000000000000000028004000000400000000040000000000000000000800000003008000000000000000000a0000c030027006004000031020000c00a8000000000000000000000000000000000000000000000000000000000000000000200000000008008000000000000000000000000000000030000000e00000000000000000000000000000000f08040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020032510004000c004b410010003002ec100040000000000000000000000000000000000007766000000000000000000000000000000000004001000000000000100000000000001000000000000000001007000000032002480002182000000000000000010800010006060c0000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000100040000080000010000400088040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000000001000000000000000000000000000080000000000000000000000000000000000000010010000000000800000000000000000000000000000000000000802800000001041000000080000801020050000002000403400000000000000000000000000000000000000000000000000000000010040000000000040280000000010000000000000000000000002000c000000000010000000000000000000020000000000000000000000000000000000101400082096000000004c26c00000000000000000000000000000000000000000000000000000000000000000000100000000000010000000000000000000000000000000000000000888040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000a0000000000000000000000000000000000000000004008000000800000000000000000000000000000000000000000000000000000000000000000000000000000200000010080008000001000000000400000000000000000000000000000000000000000000000000d39c000000000000000000000040000000000000000000000000000040000000004004000000000000000004000000200200100200940048000000000000015002000008009100000000040000000000000000000000000000a0000000000000000000000000000000000000000000000000000000000000000000000000000000488040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000020000000400000000014000002000000000400000000000000000000000000000000000000000004000000000000000000000000000000000000048108000008000200000000000004000002800000000000000000000001000000000000000000000000000000000004004000000000000000040000004004000000000000000000000000000000000100100000000000000000000000000100000000008000006000000000000000040000002000004000000100800400200000000000000000000000000000000000000000000400100000000008004000000000000000000000000000c88040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000001009000000000240200000000000000000000000000000000000000000000000001000008088000000000000000000000000000000000000000050008000000a0000000000000000000000000000000000000000000000000000000000000000000000000000020010008409011218a10110048418608402802a19210610000000000000000000000000000000000064f300000000000000000000010000000000000000000000000000000000000000000000000000000000002800000080080004840002000020000000000002002208000000000000400010020000000000000000000000000000000000000000000000000000000000000000000000288040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000040210000000000800802000000040010000000400040000000000010010000000000800800000000210020040100000000800000000000000000000000000000000000022212000000000440a00020100001013040020005009005004400040100000020000000000000000040210000000008808000000000200220004001000448600000000000020000000000000400080014041210000000000409000000000240240004001000401100000000000000000804800220043080880448488442a22610a142100000000000000000000000000000000000402100000a88040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000020000000000800800000000000000000000000040100000000000000000000000000000000080000001809800000000000000000000000000000000000000006000800000060000000000000000000000000000000000000000000000000000000000000000000000000000000000008000610a08210000008628408408000a086102100000000000000000000000000000000000c25a00000000000000000000010004000000000100400000000008004000000000200200000000004008001101000088088051000048842020008000000000c20200000002004000400010020000000000000000000000008000000000688040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000000000000000000180800000000000000000000000000000000000000000000000000000000000000000000000000000010020000000000800000001000000000000000400010100000000020000000000000408000000000000020040200008000000000000000000000000000000000000000000000002000000000000080000002800000010005004406408400000100080020000000000000000000220000000008008400000000210200006000400020100000000010040000000000000000200000000606000000008408800000000000000008000001400000000000000000000804000020206919818408028684421a00a142100000000e88040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00110004000001100080000008000000000000000000000000000000000000000000000000000000000000000000400500000000000000000000000000000000000000000000000000000040040000000000000000000000000000000000000000800000028001000000000000000000000000000000000000000000000000000000000000000000000000000004001000000000000000000000000000000000000000000000000000000000000000000000000000004f92000000000000000000000000040000000001004000000000100000000000002000000000000800140011008000080028620500a8068000008000000000021a080002002020a0001000188040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8001000000000000000010000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000008000000000000000800020000000400000000000000100000000010010000000000000000000000020000000000000000000000000000000000000000000000000000000000000400000000082900000000080080000000800000000400000000000000000000000000000010010000000000400000000008000000000000000400000000000000000000000000400000000000000010000000000400500000010000000000000000000000010000000000988040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000210000000000000000004010000000000800800030030030000028c10c00000000000000000000000000000000000100c0000000001003000000000080080000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000010020000402000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000c20c00002000030830000000020c00c00000000000000000000000000000000000736a00000000000000000000000004000000000100000000000000000000000000000000000000000000000001000008008282004000080200588040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010000000000000008008400400000c0040000400000000000400040200000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00000000000000000000000000400080000000000000000000100400000000000000000000000c00000000800000000000000000000000000000000000000000000520c00000000000000000000000080404000000000000000000000000000000100000000000000000400c00000000020020000000000800800000000000030000000000000000000000000010000000000000d00000000000020000000000800800000d88040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00202480000000080084000000000400200000008004410800000000000000020000000800480000921481084400802822102100000000000000000000000000000000000402400000000090090000000000200200000000004010000000000000000000000000000000008028000400000000000000000000000000000000000000000000100c00a0b008000000000000000000000000000000000000000000000000000000000000000000000000000002004000100240020921012015020844840140000861121000000000000000000000000000000000008ed400000000000000000000000010000000000000000000000000000000000000000000000000388040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000000000c010000000000100400000002080004000001200020028210308800b02a20000000000000c0804280090001000002200022000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000040000000000000000000000400000000000088000000000000000400000800008000000000000000000000000000000000000428448000008008408002800000020029401002800000000000000400000800000000000000000000402100000000090080000000002002200000000010010000000000000300000000000000000000200b88040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000c18000000000030000000000000c18280000000030600000000000c1800000000003060a00000000000000000000000000a080000010000521909452000014864251480000000000000000000000000000c18000000000030600000000000c1800000000003060000000000000000000000000000000000000000000282000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c18000000000030614864251480c185219094520306148642514800000000000000000000000000000000000b48000000000000000000000010000000000000000788040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000030600000000000c18000000000030600000000000c1800000000003060000000000000028200000040000a08000001000000000000000000208000001000028000000000000000000000000028000000000000000000000000000000000000000000000000000000000000000000000000000000c18000000000030600000000000c0000000000000000a000000000c18000000000030600000000000c18000000000000000000000000000000000000000000000000000c1828200000043060a000000000c00282000000400000000000000001000000000000000000000000c18000000000030600000000000c1800000000003060a0000000f88040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (ba8000000000eaea00000000015554001000000555500000000000000000000000555500080000015554000000000555500000000015554001000000000000000000000001880015405ff204c0ddd36446c6d393774d9100000000000000000000000000055550000000001555400000000055550000000001555400000000000000000000000000000000000000000001046311080000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000555500400000015555303774d9155554e0ddd36455555383774d91000000000000000000000000000000000004d6500048040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000042ee000000000000015554010000000555500000000015554000000000555500000000015554010000000000018802002000808620080200030300000000000c0c0100044000000188020000000000000000000000188420000000000000000000000000000000000000000000000000000000000000000000000000055550000000001555400000000001000000000000000040500000055550000000001555400000000055550000000000000000000000000000000000000000000000000055551884211085555454ce0000000002014c000841080010000000011100000000000c0c000000000eaea0000000003a00848040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000c0c00000000015150000000000545400000000015150000000001a9a80000000006a6a000000000000000000000006a6a0000000001a9a80000000006a6a0000000001a9a82000000000000000000000000018804008202000480e3dc63800012738f718e0000000000000000000000000006a6a0000000001a9a80000000006a6a0000000001a9a8000000000000000000000000000000000000000000010463110800000000000000000000000000000000000000001d1d004000000000000000000000000000000000000000000000000000000000000000000000000006a6a0040000001a9a92038f718e6a6a498e3dc639a9a92638f718e00000448040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (600c726a6a66308031c9a9a998c200c7200000000000000000000000000000000000077f00000000000001a9a80100000006a6a0000000001a9a80000000006a6a0000000001a9a8000000000000010842110200c0c431084400030300000000000c0c110004400000018c00000000000000000000000018842000000000000000000000000000000000000000000000000000000000000000000000000006a6a0000000001a9a8000000000000000000000000000a222800006a6a0000000001a9a80000000006a6a000000000000000100000000000000000000000000000000006a6a1884211085a9a8a2ce0000000002014c20084048001000000000110000c48040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0006a6a024920008804040000000001303000001000000000000202000015000000000054540000000001515000000000001a83000000006a6a0000000001a9a8000000000006a0100800001a9a80000000006a6a0000000001a9a800000000000000000000000000008401044ef01164308031c8044d98c220e72000000000000000000000000000006a0000000001a9a80000000006a6a0000000001a9a8000000000000000000000000000000000000000000104d22302000000000000000000000000000000000000000001d1d00000808000000000000000000000000000000000000000000000000000000000000000000000006a0000000001a9a990c00248040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000c0550000000001555580cc83064555561b220c191555586c88306400000000000000000000000000000000000f88d0000000000000001a80000000086a6a0001000001a9a80004000006a6a0000000001a9a8000000000000000c52210000e000314a8600000000000808000c0c000028610030000800000000000000000000000000c5200000000000000000000000000000000000000000000000000000000000000000000000000006a0000000001a9a80000000006a6a00000000000000051400000006a0000000001a9a80000000006a6a00000000007400000000000000000000000000000000000000006a00c52210a9a9a941c80000a48040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000c05500856214ad55540acd00000555502092020884040000000000130300000008000000000004200c0ea0000000003aba8000000000eaea00000000030154000080000555500000000015554000000000c05500000000015554000000000555500000000015554020580000000000000000000000088d081a9f045603221c991544d86c887264000000000000000000000000000c05500000000015554000000000555500000000015554000000000000000000000000000000000000000000100d623424000000000000000000000000000000000000000000000000010800000000000000000000000000000000000000000000000000000000648040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002000000000000000000000000000000000000000000000000000000000000000000060000000000005800000000000160000000000000000000000000000000000000000033d000000000000003015400000000155550001000001555400040000055550000000001555400000000000000005421024080000150c619000000000108000c0d00000c60903400085400000000000000000000000085600000000000000000000000000000000000000000000000000000000000000000000000000c055000000000155540000000005555000000000000008a0780000c0550000000001555400000000055550000000000000400000000000000000000000000e48040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000020160000400000000000000000000000800800000005000040800008140000800000005000000000000144004000000000800010000000200800000000000000000200000000000000000005000000000000140000000000000800000000000001000000000000000000000100000000000400000000020000000000000000000000000000000000000000000000005800004000000160000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000100000000000000000000000008000000000000200200000000000000000000000000000000000000000000000000000000000000148040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000110000000000004000000000000100000000000000000000000000000000000000000039250000000000000000000020000001000005000010000000160100100000000000000000400000000400000000800000000000020008000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050000000000001400000000000000000000000000004000000004050200200080000408008000000000948040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000040000000000000010000000000034000000000020d00000000000000000000c000000008008000000001800000000000000008000000000000000000000000000010000040000000000000900000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000040000000000001000000000000000000000000000000000000000000000000000000000000020000000c0000000000000000000000000000000000000000000000000000040000000000001000200000000000000000000000000548040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000697d001000000000000000010040000000000000001000000810040000000000000000000000000c0000000022140000080000021000000000000000000000000001000000000000000000000000000000000000000000000000000000000000300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0000000000d48040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000400100200000000004008000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000080040008000000000000000000408000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000002000000000000000000000400000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000020000000c0000000000000000000000000000000000000000000000000000000000000348040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000001000000000000000000000000080000000000002000000000000000000000000000008000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000002000000002000082000000000082000000000000000000000000000000000000000004a1200100000000000000000004000008000000000200000080012001000000000000000000000000000000040c0000002000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b48040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000800080040000000000000000000000000000000000010000010020000000000400000001000000000000008008000000000000800800000000020001000000010000020000000000000400200000000000000000000000000000000000000000000000000004800000910010000000040000800000000000000000000000000000000000000000000000000000000000000a00020000000000400000800000020000000000000000000400000000000000000000000000000000000020000000000000008200000a00000000000020000000000000000000000000000000000000000010000000000000000000000000000000000000000400000000000748040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000002200000000400008400000000010200000000000000000000000000000000000000000e1fd0000000010400000000020000000000000000000000000020000000000000020000000000400000000000000820000000000020000000000000000020000000020000000000400000440000800400000800000000000000000000000000000000000080020000000000000000000000000f48040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000080000000000000000000000000000000002000000000000000000008000000000000218000000400000100000000000000000000200008000000040022220000000000000010000000000200000000000000000000000000000000000800008000000000040200000000000008000000000000200000030000000800000000002800000008000000200001000000000000000000008000001000000200000000000000800000000000040000000000000000000000000000000000000000000000000000000000000000000000000600000000000020000008800000000000200000000000000000000000000000040000000000000000000000000000c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000040000000000200000004000000000000000000000000000000000000000000000000000000000000000000000000140001000000005000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000040000008040a0010002000180090802d00100000000000000000000000000000000000000d16500000000104000000000000000000000008000200000000200000000000000000200009800000008000000000000000000000000040000000000000000000000000000000010000010100000000000000000000000000000000000000000008c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00800000800000000000000000000000000000000000000020000000000000000000000000000000000800a000000000000a00000000024028000000000000000002000000000000000022040a0000000000000000000000000014084900004002d02c800000002000002000000000000080000200a00040000800028000200000000000008000920028000000000000002000000000000000080080000002000000000000000000000200a00000010005028000000000000000002000000000480000080000002000000000000000000000000000000000000000000000000000000002000200000000000011240b4012000080802d00804000000000010000004c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000405400002400010000400000000000200000000000000000000000000000000000000000080000000000000000000000000000000000000000000820000000000001000000800000000000000000000001000000100020000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000004000100000004000000a3010040010010a204000000000002000000000000000000000007c4e0000000000000000000002002008010000000000000002000080400000000020020000000800000000000001420000000000050000000000000000020002000050000000000000000000000800cc8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000c30000220000004000000000010000000420004440000000010400000000000000000000000000000000000440000040800010010000000000020102000000000000000000000400000000000000000000000000000000000000000000001000000000000009000000000000000000000000000000000000000004000000002100000000000000000000000000000000000000000000000000000084000000820400000002c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000600800000080000040008068200001000003000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000040000000000000000080000080000000000002040400000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001800000000680ac441000c09610c41258e0000000000000000000000000000000000067930000000000000040080001110101024000002020000800000004000000000000020000000000040000000000043490004800000000000000000000ac8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000400000000000000000000000000000000000030d00000000000200000080000000000000000000000000000000000000000000000000000000000000000000000000000000020e8040000008000200000000000000000000000080000000000000000000202000000000000080000100008041600100000011200400100000000000000000000000002040040000000040000000100001e200400004000080000020800000800082fa600000008000080000000000000000000200000000001040000000000309200000000008000008000000000000000000000000000000000000004000084000014000000000000000000006c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000100000000000100000000000000000000000000000000000000210000008200000000080008000004000000000000000000084000000000000000000000000000000000000000000001200000000000000000000000000000000000000000000000000000000000800000000800000000000800000004000002000000000000002000000000000000000000000000000000001000000000000000000000000000000000000000000000000008000000240000084008840008840001222002610000200000000000040000000000000000000000060cc0000000000000000000004000061020200040010100181000100200000000000000000000000000000ec8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08600002000000000000040000000000040000000000004900002800000000010000000000000002000000000000000000004920000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000001248000080000000000000000000000008000000120000008010100000000000000000000000000000000040082000002000000c84400020040020c00000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000001c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00400000000000000000000001000000000108000000004800003000000000000000000000000000000000000002800000004000001004c4000080010012108000000000000000000000000000000000000000000000100000000000208200000000000000000000000000000000000000003080000000000040000c400010000000200000400000100000008002000000000000000000020000000000000000000080000000000000000000000000000000008000000000000000000000000000000210000050000084000406040448000011208800200000000000000000000000000000000000044800000000000000000800102082010020100122104010009c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000400000010204048002000110208000000020002000000000000000000000000000000000008208200000000200000000000000000000000400200000000000000000200000000000000000080000000000000000000000000000000000000000000000000000040000040000000000000800000000000c0440010000001000000100000000000000020000000000000000040000800208108000020000a0020c1000081200092000004001000000000000000000000200000000c040400010000100a204000000080000402000801000820000020004210800002000002020000000000000000000000000000000000040000000000001000000010000005c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000082000000000180002000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000012400000492040400000002480000000000000000000000000000000000000000000000000000000000800000000000000000004000020000000000000000000000000000000000014021401000000000850000000000000002000000000000000000000000000000000000000008000000001000100000000000000000000000000000000000000000000000000020000020102a014000148109010048020022208000000000000000000000000000000000000cac50000000000dc8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000083e5000000000000000000004000000002004c0104814000000a8020800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000201040000180014041000000000100000000000000000000000000001008000000000100104000000000000100049200008004001040000000000000000000000000000001000000000804140000000404400000000000000040000000000000000000440300002010002000000000000000000000000000003c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000400000000000000020000000008000800000000000200100000000000000000000000000000000200000000000000040000000000000000000000000000000000000000000000000201040030140200000000c0024020000000000000000000000000000000000000000000000000000000242000000000000000000000000000000000000000000000000000000000010100000000000400008000020000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000800401001000000130308000008004c0400800000000000000bc8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008aa00000001000001000000000000000000000000000000000000000078b9000000000000000000000040040000000200000008000045002000000000000000000000000000000000000100000000000004000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000800000000000000000000000012000000004000080000000000000000000000000000000000000002000000000000000000000a000010101000080000c00000000000000000000000000000040000000120000008000000801800000000100000000000000800000000000000104000007c8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400400000000000000000002000200000000000000000000000000400400000000000000000000000200000000000804000000000000000000000000000000000000000400200000000000000000000000200000000000001000000000000400000001800000000000000000000000020000001404000000000000000000000000000000000000000200000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000fc8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000008080100000000240009200200200000000000000000000000000000000000717200000000000000020000200000000000000011000000001000000000000201000000000000000008000000c00000020000000000000000001800000000000000000000000020000000400001000000000000000000000000000000040060000000000000400000000000000400000800800800000004000020000000008008000000000520000000281000010000100000200200200020000000000200001000001008000000001002000000000800008000000000000000000100100000000000a000002000000000080800000000028040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000002000000000000041000200040008000001400000004000100010004000000000000000000000000000002000004000000000000000001040000000000040000000000000001001000040040000000000000000000040000000000000000000100400000000000000000000000000000800000000800001014000000000000000000000000000000000000000040000000000001000001000000000000020000000c000000000000020000000000000081009000200000000000008000104000000000000000000000000000000001000004040000000000100000000000000000000000000000000000040000000000000000000000000000000828040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000100000000000002000000002000000080000000800000000002000020040020030822080c00800c28812128404c00008000000200000000000000000000000839a0000000000000000000000002400400010000014030000000124000000100000000000000000000000000000404000400000010000000000000000000000000010000000000400100010000004000000000000000100000000000000000000000000000000000000000000000000000000000000000000008000001000400009200000040000041200001001000000000000000000000000c8000100000000000000000000041400000000022004004008010000100000000000004200428040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004420040020800008001000000000244048000000000080000020000000086020800440081010000000a00040008000040000000000000000002000000000200000000000000000000000820000000820000000000020002080008000002002000000000001001001000001220080080000000000000400001181288000100000000000000000000800080000804880804200000001220002048000000000000000000000000080000000002000101000000080000020000000c000001000000000000000000000200400400000000000000001000500000000040000000010000000200000001000004040000004000100000000000000000000000000000000c28040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000000000000400000000000000000000000000000000000000000800000000800000008000000904000000000000008108004008800290800000000002100000000010000000400000000000000000000000db3a00000000000000020000020840000000000010020200010004c44100002000202040000004000000001020c0004002100082008002200000000000000000082000002080002000100140000004000000000000000100000000000000000000000000041010000000001040010000100100100000000004004000002001482010c00000008008020c80102000000008220080040040000000c00000840000000000002010010404c1081200228040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000000008000000000000000004000800000002102000040110001000000000000000000000040180200000000002010010000020000004100000002008000040120000000000000000080000000000501000000000004040000000820080000000000002000000000000001000000000000000080000000000000000020400000000000000001400100000000000000000000000000000000008008000000000084000000000c021000300000000000020800000000400000000000000004000000000000000000000000000000000000010000000000000000008000200000800040008000400000000000010000040000000080000000000000000004000a28040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002400000010400000000010012402402402002000860190480080002001080000000000000000000000000000000000036e3000000000000000000000000000000000402000000000000100000000040004000000001000080002000000040000000000001000000000000000000000000001000008000000000008000000000000000000000001000000000000000000000000004100000000000104000000080000080000000000000800000000008000008000000000000000040000000000042000000000000200000628040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000010000000000000000000000000000000040000200000000000000014110100c10414810000002000000000000000000000420000000000044000000000000000020000000000000804100000000020050004000002102000000000082800000000000000000000000000000000000000000000000000000000082820010080000000000000000000800800800000c00000000000000000000000000820c300204200000000000000000000040080000108601021020000020a00008400000000000020800000000000000000000000000000000000000000000000000000004000000200000020000000004000000000000400008401210000000000048000e28040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000030000c00000000000020200010000000000000000000000000800080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200200200000004020004c00c100000012000000000000000000000000000000000000000001e1a00000000000000100000420900000000080200800000010b08010400000400800820000010000010100820000000000800820020020800000000000000000820000020000000000000000000800000000000000000000000000000020000000000000000000000000000000000008000008000000000020000002000400a000000000000101000128040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080000000000002000000008000000000000000020000000000000000000000000000000200040000440000040001040020040001000000212000000000000200000000001400100000000810010100000000d014000000000000000000000001004028090000000c11000000000001000000000102000001000000080000000000040000000000001000000020800002020000000000000080000000000000000000000000000000000002500000000000000000000000000000000000000000000000020400c008000008412000200000000000000000000000800000000000000000000000000000000000000004000000000000000000000000000004000928040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002000000000000000000000000000000000000000000000000300000200004000000000002000000000200200000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac008010084288000500004a080000000000000000000000000000000000082a4000000000000004000000004100080004000002002000000100000000040000000000001000040000000000000000100000000000000000000000000000000000000000000100000004000000000000000000000001000000000000000000000000000000000000000000000000000000000000000528040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000004000000000000020000006000000000000000000000000000000000000000000000000000000000320000030420200000000082000000000000000000000000000000000a000000003000000000000000020000000000000000000000000000000008000000000000000000000000000000000000000000000008000000001000200000000000000000000040000000000000000000000000000000000000800000000000000000000000000000000000000000000000200000800042a02a002528010140000128200000000000000000000000000000000000000000000000000000000400000d28040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000a802800050000000000000000000000000000000000000000000000000000000000000000000000000000000000800800000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500020004034440014000000000000000000000000000000000000000ee7a000000000000000200100000000000001000000000000000000000000000000000000000000000000002000000000000140000000002000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000328040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000008000000000000800000000000000000000000000000a00000000000000000000100000000030000000040002a0000014500000000000000000000000000040040494000000008032c000000140000000000000000000000000000004000000000000000000000000000000000000000000000000000140000000000005000000a000080000001004000000000000000000000000000280052000000000000000000000000000000000000000000000000000050000002000020c2002040160004400000003000000000000000000000000b28040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000140000000000000000000000000000000000000000000000000000000000000000088002002d0000000000000000000000000000000000000000000000000000002000000000002800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200080000080000240802000200000000000000000000000000000000000420e000000000000000000825000000014004b40000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000010000000000000000000000728040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000400000000000004010000000000000000000000000000000000000000000000000000000000000080002000000000000000000000000000000000000000000000000100000000000000000000080000000000a04000000000100800000000000000000000000000000009800000000000800080000000000000000000000000000000000000001000000800000000000000000000000000000000000000000200000000028008000000000000000000000000800000000000000000000000000000000000140a04000000000000000000000000000000000000000010000000000000802002002a00200f28040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000810020002080401009000005030008220008840400000000000000000000000000000000000000000000000000000008050000800a0000000000000000000000000000000000000000000000001000128808000040022024200000002102100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001142400080482090206010940a00000000000000000000000000000000000ba020000000000000001802000000000010000000000000000000000000000000000000000000000000000020200008000400000000080000000000000000000000a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004000800404000100000000000000000000000000100020040080002001000000000000000000000010210000000000808400000000000010000000000000000000000000000000000000000000050008000000800800000000000000000000000000000000000000020004000001000000000004084000001402032030810240092090200000000000000000000000000090c8220408408403048a10210211002000000000080040000804000080020000002000000000000000000000000000000000000000002000000000100000000000008000080000001000000000000000000000000000000201014000484040000000000000000000000000000000008a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (404000000000000000000000000000000000000000000100002000000002100900000100880800000a00000000000000000000000000000000000000000000000000000000000800000280010000000000000000000000000000000000000000000000800001008808000000006000200000002000100000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001220080808000000204000040000000000000000000000000000000000000a5a10000000000000009002410210210090118408408400000000000200000000000000000000000000000000100004a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000000000000000000000000000004008000000000040600010000000000000000000000000000002004000000000000000000000000000000002022000000000040880000000000000000000000000000000000000000000000000000000000007000000000000000000004000000000000000000000000000000000000000000000000000008000080140210211201000008000810000000000000000000000000008241298408008682040a0021020000000000000000000000180400008001000000600000000000000000000000000000000000000000000000000010000000000000800000000000000000000000000000000000000000020101000000ca8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000080280000800a0080200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000050012040008000a020000000000000000000000000000000000004d120000000000000000008610200210100018408408400000000010002a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000002000000000000004000000000000000000000000000000000000000000000000000080001000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000a00000000000008000000000000000000000000000000000000000000080000008000000000040000004001004101208000000000000000000000000000000000000000020040000000000001000000000000000000000008000000040000020000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000aa8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000020000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000080042808800002000001020000000040040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000040000000000000000000000000000000000000770000000000000008006a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000007d9c00000000000000000000000c00c00000800030030000000000000800000000000000000000000000000000000040008000000000000400000000000000000000001000400000000000008000000000000000000000100d0000000000002000000000000040000000000000000000000000000000000000000000010000000002002000400000000000000000000000000000000000000000000000000000000000030000100000800880000100026000000000000000000000000000000090000000030030000000000c00c000000000000020004000000200000000000140000000000000000000000000000000000000000000000000ea8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000200080000000008002000000000000000000080400000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000402002002300a0800220004020400000000000000000000000000000000000000000000000000000040030000200800000000000000000000000000000000000000000000008010000a084000004002404000000000000090000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140004403085004001120140000000000000000000001a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00040000a080000010000000000000000000000000000000000023d100000000000000030004002002102401000084084000010000102000000000000000000000000000000400800020010000000000000300000000000000000000001000100000000000000000000000000000000000002000000000000080000000000000000000000000000000000000000000000000000000000540880a0401000800300000000000000000000000000000000000040010000000000000000008090000a004020320300002200888400000000000000000000000000000142281a00800840204000021020100a00a000000080050000008000100000001000000000000009a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00004000000000000028000000000000000000000000000000000000000000000000000000000000000000000000000000028000000000000000000000000000000000000004008000000000000000000000000000000000000000000000000000008000000000028200000040000008000001000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000c18282000000430600080000010c18000000000030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000282000005a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000002888a01080000001000082000000000000000000000000000000000000773c0000000000000000014864251480000521909452000014864000000000000000000000000000000000000002000000400000080000010000000000000000000080000010000002000000000000000000000c18000000000030600000000000c0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030600000000000c1828200000043000008000001000000000000000000000000000000052190945200001486425148000000000000000da8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4c4ddd36440c0d383774d910000004000000155740000000000000152320000000000000000000000000000000000000000000001f1f00000000007c7c00000000000003984200000000000000000000000000000001000000001880000000000000000000000000000000000000000002000c0000008001b1b10140550146c10000015405000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000005555010043110955540000080635555000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000010540000006c6c0100154050000000000000000000000000000000000062a6000000000000000001303774d9100004e0ddd36440001393700000000000000000000000000000000000000000000040000000000020000000000000000000000004421000000000620000000000000000555500000000015554000000000000000000000000000000000000000000000000000000000000000000d010040000000343400000000000000000000000000000000000027030000000003aba8000000000eaea2808c220000004000008888000000000000000000000000000030300ba8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (154880000000000000000000000000000303484e3dc6380c0d2638f718e00000040000000000000000000000006a8000000000000000000000000000000000000000000000001f1f00000000007c7c00000000000003984200000000000000000000000000000000000000001cc0000000000000000000000000000000000000000002000c00001000000002888a020800000000000820000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a6a0100431109a9a80000080636a6a000000000000000000000000000000000000000000000000000000000000000000000007a8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008800022c1a000200001008c282a8000000000000000000000000000000000001a8e0000000000000000012038f718e0000498e3dc63800012738800000000000000000000000000000000000000001100000000000044210000000000000000000000044210000000007300000000000000006a6a0000000001a9a8000000000000000000000000000000000000000000000000000000000000000000d00004000000034340000000000000000000000000000000000002703000000000054540000000001515011405511c7400000000fa8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00054000000000151522c9a022a05454000000800000000000000000000000000000030364308839c8000198c220e7203030000000000000000000400000007d000000000000000000000000000000000000000000000000000000000808000000000020200000033c52000000000000000000000000000000000000000008c00000000000000000000000000000000000000000000000000000000000001450c1938000000001044e0000000000000000000000000000000000000000000000000000000f000000000000000000000000000000000000000000000000000000006a1049023021a9a800000082a6a6a0000000001a9a8000000000000000000000068040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (555000000000155540000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000010540080c000000041474f0000000000000000000000000000000000096d100000000000000000190c600c72000066308039c8000198c20000800000000000000000000000000000000000021000000000000842a00000000000000000000000842a000000000230000000000000000006a0000000001a9a80000000006a6a0000000000000000000000000000000000000000000000000000030300000000000000000020200000000000000000000000000000000000000000000868040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000001080303a8000000000eaea1101440537aba80000142090000000000000000000000000000303603221c990000186c887264030300000000000000000000200000023954000000000000000000000000000000000000000000000000000000108000000000004200000033856000000000000000000000000000000000000000008c0000000000000000000000000000000000000000000000000000000000002281e30ea4000000000c3a90000000000000000000000000000000000000000000000000000000e010000000000000000000000000000000000000000000000000000c0551009423425555400000092b500468040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000200000000000000000000000000000000000000000000000000058000000000001400000000000050000200000000000000000000000000000000000200000000000000000040000000000000000000008000000000000000000000000000000000000000000000000000000b4cb00000000000000000180cc83064000061b220c990000186c880001000000000000000000000000000000000000210a4000000000850b00000000000000000000000852b000000000230000000000000000c0550000000001555400000000055550000000000000000000000000000000000000000000000000000030300000108000000000004200000000c68040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000008005000280000004000000008800805120020000400140400000000000820000000000020000000000000000020008400020000000000000800000000000144000000000040140000000000404000000000000020000008000020000000000005020000000000340000000000000000000200008168000000000000000000000000008000000000005800000000000140000000000000000000000000020000000000000800000000000020400000000000800000000000140000400000000000000000000020000000000080000000000000020000000008000a000000000000000000000000000000000000000200000000000000000000000000000268040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000001000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000404000000000000000000000000000000000000000000000000000006f9c0000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005a000000000003400000000000058000400000000000000a68040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000004000000000000000008000000000000000000000000000000000000000000000000000000000000002040000000000001000000000000000000000000005000002006000040180000000000000000000000000000000000000000000000000000200000000001000000000000000000000020000800000000000000000000000421000000000000000000000000000000000000000040000000000080000000000000000000000000001000000000002140002100000001000000000000040000000000020000000000001804000000000001000000000001000000000000001000000000000040000000000000000000000000600000000668040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000800000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000200000000000000000000002000000000000000000000000000000000000000000000000000002d7e0000000000000000000000004c000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000e68040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000080000000000000000040000000000008000000000000002000000040000000008004002200100000000000000000002000200000000000000000000000000000100000010000000810800000420000000000020000000000100900000000000020000000000000000000000000000000000000000400000080000000000000000000000000000280000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000c00000c00000000000000000000000000000000020000000000000008000000000000000000000000000000000000000000000000000168040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000820000002000000a00000000000800000000000000010000000400020000000000000000000000000000000000000000000000000000000000000000000002000000080000000000000000008000000000030000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000200008400000000000000000000000000000000000000000000000000000170900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000968040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000000000000000000000000000000000000000000000880000000000000000000000000800000000000000000000000020000000800000000000000081002000000000004000004000000000008000000000000280000000000000000000004000200000030c20008c10c00009000008000000000000800000000404080010000000000000000008010204000008204100100104000000008000000000000000000000200200000800000000000000008008000000000080008100280000000008000000000000000100000210200000000000008000000000084204000000000008000000000010000004002000000000200000208200568040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000001020000000004009000000000000000000000000000000000000100000000008004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000020000000000000000008000000000030200000000000008000000000000000000000000000000000000000000000000000000000000000000000000000400000100000000000000000000000000000000000000000000000000000f62a00000000000400000000000000000000000000000000000000000000000000100020000000000000000000000100000000000000000000000000000000000000000000d68040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000008000000000001200000000000008000000000000000000000000000080000000000000000000000000080000000000002000000002000000000000000000800000000000000000000400000000000861800021061000000002000cc000200000000300000400080004000000200000000040000004000000000008000000000000a00000000000000200001000040240000800000000000000000000040000000020008000020000000200000000000000000000000000000000000000000000000000020000000000000000000000368040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000010000000850000000000000000000008480280000000104000000020000020800200200000000000000008300800210000000000088000000000800000000000000020000000800050000000000000000000000000000000800000000000000000000000000000000000000000000000000000004002100000000400086000000000002080000080000000000002000000000000004100000000100400000000000000000000000000004000000014010400000000000000000000000000000000000000000000000000f0d100000000600000000000000000000000000000000000000008000000000200000020000000000000000000000000000000b68040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (002000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b40300000104028008000020000b4002000000000000000000001000a00001000000000008000030070a0000002000002800004002200014000c80000000500022000020000000000000800500d2000000001402000080900000800000022000100000000000000000000000020000000000c0085008040086082a0220a08094002808000000000000200000096602d000040000000000000000080080020000001100b4200300000002808000000000000000200000208500180000000768040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800000000000000000000800000400000000001080040000001000800000000048010002010000000000010400040480002000400482000000000000000000000000100000000000000840000000000000000000000000000000000000000000000000000000000000000000000000400000028000000000000000000000000000000000000000000001000008040000410100000400004000400104000004008010000000000000000000000000000000000000000000000004000000000000000100000800051000000000000000000000000000000000000000000000416000000000004200000000000000000000000000000000000008000000000200f68040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008140040000000000800400800000010000000000001000000020000200400000000000010000000000000000048000000000000800400444000000000090010002000000020800000000000010000000000000000001000000000000000400000000000000000804001040000000000020000000040010000000000410000400000004000000000000000000000000c900000000000002000000000000000010c00004d00100000000000e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000018400000800804800001040000000000000400000000000000000000000008000802660000000000000800000000801e000009000000000000000000000000000210100000400190000000000004100101004000000014008200000000002000000000000000000004000000000000000000000100100000000000000000000000000000000000000000000000000000000000000001800110000800c03000000040000004000001800000000000000000000000000000904000000040002001000000000000000000000000000000000084082100000000000000000000000000000000000000000000000008c0e000000000000000000000000008e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000f5110000000000000000000000000000000000000000000000000000000200000000000001000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000002000000004800f2000082000000204001080000000000001100000800000000020008000000000000000000000000000000004000000000001000040905b3400004000024400000000000080000000000112400000000000c0000004021000000000000000000000000000000110000404000000000000000003040001a600400000100080100100000020000002a00004082000020002000000000000004e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000002001010000000120800000000000040000000000000000082040800000401040000001040000000000000000000800000020000000804900000000000000000000000800000004000000000000008000000080002000800102020001000000000000000000000040000000600001000000000000000000000000000000000000000000000000000008108000000002000000400000028000000000000000000000000000000000000000000010000408200010008004000204100000100000010000004008000400000000010400000004000000200000000000000000000000000000000008420810030800000000000000000000000000000000000000ce8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000e5a00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000004842000800000000083020000000000000000000800040800000040000200c00000000001010000000000000000010000000000004800108000010000400000208000020000020800000800010008000000000010c00800841000000000020000040000000000001008000c200000000000200000000000000004400322040001080041204000002e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (048002100200c0080004400001002028000820000444900000009200840400000000000000000000000a4800004024c400008020001000000000004000000000000004200408200020104000408200000204000000000004200000000201000000000410000410000000000084001000a20000000000430c000004080000004000008000000000008000000000000000000100002000000000000000048200000000000090400000000001240000000000000000000000000000004000000025000000020810080820020800200040800010018810002880000a42400002000003090000080000000000000000000000001000000001000400040c230400000000ae8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000040000001841000000000000000000000000000000000000000000000000005c63000000000080000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000202cc4000002000010020000084000484002000009000021440000000004005010000000000000008000104000000201000100001000080020e220888000800204802002000000000000000000200000200000008850c000000020004000000004000480000000000002080000040000100000100002006e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000800810120040001000014800000000040000000050011004900400000850000000000000000000000000000020050004921000100000000040000000000000000000800004060000010000900400000000000000000000004920005800000000000000000000000000040024120000000000000000010000028100060000010a04201000000000000000000000000000000000000000800200000000100000000000002004000000000000100000000000000000000000000000000000000000009240540648214049006000010101040040000010000000010104400000000002000000000201000000000000000ee8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00040000000000001000001000000000000000000000000000000000000010120000000000000000000000000000000000000000000000000000e7f700000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200100549210001000002000001000000101004000000000404002002004000000000000000000000412080000000000000400000000000000010882140000000000400000000000000000000000002001000000000100000080000000000000000000840001e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00012006d000000040002000000000000200000000000000000000000000080000000004000000012801200800000000008024a0000040000006000000000c000000000000000000000000000000000000000301090000410008000000000000000000000000004000000000000001000000000004000000000000001000000000008000000000200000000000000084002000010000000000000000004400002000000111000000000000000000000000000000000000004000080000000000008140000000000010000000000000500000000000000000000000000000008000000000000804000400a0000000010010000000000000001000410000000800009e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0c0000021004000000000800000000001801000000000000000000000020020000000000000000000000200000000000002000000100000100000000000000000000000000000000000000007ed000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000280130100200001000800000000000030000008001000001100000000000200048000000000000000002000200000000080408000000000000109000200010004400400000000000100000000004000000000005e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10004000000000000000000020008200010800004500000000020000000000000000000200060020000000000000000008200200040100008000050000201800000000080004000000002080000060070000000400000000000000000000000000000000000000000000042000040000000000000000000000000000000000800000c0000004000004000800000000000000000000000000000040000000000020000000800000000000000000020010000800000001400000000000000000000000000000000000000000000000000001800000000020800000000800000200000000000008000000000000000000000000000000000000000000000000010400de8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000184000000004000008000000000000010010000000000112800000004000004000082000000000000000000000000001000040000000000000000000000214200000000000000000000000000000000000000000000000000000719f00000000040000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000001000000000000000000000000000000004000000000000000000000000000000000000000040020000000800000400000010000000000000400000001000080000000000000002800800000000400000001000004000000000000000000000014000000000000080003e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002000000000000810000040800000000000000000000001001000000800000000841800020840002080000082000000000000000000000000000002000000002082000020000000000010400402404000020c200004008000010000000008200000000a0000000000000000021000400040010000080000000002400000402000000000000000000001000800000001100041000000000000000080000100000000010200100008000000000000000000000000c010000000000000000020000000800000000000000000004000000000000000000000000000018000000002004000400080000000000800000000000800000000000000000000000000000be8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000100208000000000008200000000000000000000000000000000100800000001040000800800040800000900000000400000000000000020000001041000000000000200008000000000008002000082010503100000900000800000000000000000000000000000000000000003d5000000000000000000000000000000000000000000000000000000000000000000000002000000000000000010000000000000000000000000000000000000000400000000010010000000000000000000000000010000000000000000420040000ac000000000102000001004000080000000001000000000000000000800000000000000000000100000000000007e8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00101002080004200000082004000000200000000400040000000000204000000000000004010400040000000800001124020040110800000100200410082010480000048202020020001020080040100000000100000000004080000001010080040200100220004140008008200208008000404000010400008000000000000000040000001000004000000000400000000400000000000000001000000000000000804000c0000041004001000000000400000000202004400088004120000100000104000008000000000000040000000000000000000000400000000004000000040004000000000000000000000000000000000200000020800001000800fe8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1800000000000400000000000000000000000000000000000000000000000000000000000000000010400000000410004a200000000011080000002010040000000000000000200280080002400001010000202002000000000000000000000000020000000004000800000800000000000000000000000000000000000000000000661c0000200000000000000000000000000000000000000000000000000000000000000000000000000000000000100040000008008000000000000000000000008004000000000100100000000000000000000000000100000000000000000004000008540081010020000400880800000020080000000000000000000000018040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01000420008400000000000004000000000000002c40000000400000000000000080000000008002008000000000004000000000010000084000020000000804000c10138420500000004100400000000080000000034100020620000800080020000000000100000402000188000001000081208000400400058448010210401450210000001202080100010200100000000000000000001008284000002000002000004000000000000000000800100000100000001000000000008008080000000001001000000002008100000020001000800000c0010001010000000000440000200000800000000000400000000000000000840002000000000000000000818040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000080000000000000000000000000040020000000000000000000000000000000040000082000001000002080000000000020000000000000000008490200100800020008000000200000000000000001000800008000000200000000041000000000000000000000000000000000000082000083000000000000000000000000000000000000000000000000000091540010080002000000000000400000000010000000000000000000000000000000000000000000000000000000000040000002002000000000080000000000002000000000000000100000000000000000000000010020000400000000800200400008400000000040200000418040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000400011024819500010800000410102040000018400000000000000020000044100082001000002002080000000000020000020a0200000820020140820000000002000924000000000000040000001001041000000000000000000008800200000004008000000000000a00000000000000000000000300600101410090012090000000010041410002000000022000004821020800000002000000000000000080000810882020020020010400000400000000000000000000000000001040000000000020024342200b000200000100100000000002810002000480000010000012000000000000000000000000208020800020000000200200c18040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000400c00002000000020000000080080000000000000000000000000000000000000001000000800000000020000000000000000000000000000000014000000000500500000200000020000000000130448114810000211000000c000000404008200000100a80300000010000000160000002000000000000000000000000000000000c00000000000000000000000000000000000000000000000000000000000008fc60020000000000000000000800000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010020000000218040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0020080000000000000000000000000000040000000a4000020000c00820c2c000a400000208000100068008200000000000000000000000050002000000000000000020008000040000441000450002082080003082000000010000080000000020020000002000421003042000083000c00000000000c300004100000100000000000000000000300100000000000004000420010840000800000840000200820000400001000041040000000900000000100000000c000080b002002004880080000082000002400000000000000000000000004001000040201040100080010400000080000000000000000100000000000800200021400040020002000000a18040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01008000000000000000000c0000100000000000000002000180000010006000008800480c8000000000000000000000000000000000001000000025004000000000000000000000020002000000000000000000000000000000000000000000000004408004001480800100000040c00c0104101000003060080014040001000100000000010020002800200000000000000000000000000000200040008030000000000000000000000000000000000000000000000000747a0000000000000000000000000000000010000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000618040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000400000000020140000800140000000000000000020000800080100000000000004100000040000000000000000000000000000000000000000000000260000002004800c00000000000000000000000000000000080040000000000000000000008800000000000200180000000000100000000000000000000804000000000098200200010001001800800000240070000000200010000884000000000000000000000000000020000000001400380000000000000000000000000000000000080000000010008002000008000100030080004000000000010000e18040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0100000200020000000000000000200004000000000000000000000000000000020002000000000000000000020020000004000000040000000000000000000000000000000000400000000000000209400000004000ad0000000000003000000000000000000000000000000000000008000000000001400044f0008844025000000024128b4000000004022d00000000000020000000004080000000000000000000000000000000000003000c00020000000000000000000000000000000000000000000000000000d1b80000000000040000000000000000000000000000000000000000004000000040100000000000000000000000000000000000000000118040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000002300200000000208005000000000200140000000000c40125000000000040c030000800000000000000000000000000000000000000000000900a000100000000400000000000000000000000000000020000000000000000000000000000000000000001000000000000028000000000000000000000000000000024084940000010042a6d000000000008b400000080000000c0800000000000000000000000008000000110001000a800050000000000000000000000000400000200000000000002000918040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000100000000000000000000005200000028000000000000000000002001000000a000080410000000000000000000000000000000000000000000000000000000000000000000000000000280000000000000000000084008000000000000000000000000000000000000000000000000014020002800101402000040000000000000020000000000402000000008000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000c1ef0000000000000000000000000000000000000000000000000000004000c00000100000518040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000100000000000000000000004020000000020000000000000000000000000000000000000000000000000000000000000000000000200000200000000020004000000000000000000200000000000000000080000000000040640000000000010000000a0000000000000000000000000000000000108028000000c0100010000002000000000000000000000000002020000000000000000000000000000000100004100800000000000000000d18040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100002000900002504800020000004000000000000000000004000200040100000009003000802000000000100010001002080020000804000000000040010000002009081020000000210000000004000000000220088000000000000000000000000000000000000002000000020000900904084084030032102102100800084004080000000000000000000000000000008080001000202110a0010105103014810a102100a0528448608400823210a102100000080000080004020001000000000000000000000000000000000801400080090000000000000000000000000000000000000000000000000fe8b0000000000000000000000000000000000318040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4148000000000002000000000000000000000000000000000000000000000080002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000010004290440000480248001000000000200048000400000500281021021000010848448508400000000000000000000000000000000000000000200128008800000002000100010000000000000000004000200010000000002804800000000008400000000120040000808002400820000000000000000000000100045099090528498502428210212210090108408408480822000200020000000000000000000000b18040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08600002000100000000000000000000000000000000000900010400a0002000000600000000000000000040000020006020000000800400000400000000000001000000010000000000000000000000002000140020000000000000000004000000200010000000000000040200000000000000000000000000000000000000006000000018408008405000a10210210100000000408000000000000000000000000000000800000000020000000010a0b008001610600218200858428408680461210a10210000000000408000400000100040000000000000000000000000000140000000004000000000000000000000000000000000000000000000000000718040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000073da000000000000000000000000000000000000000000000000000000000080000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020040010000040001000000000000068000800000040061020021004000840008408000000000000000000000000000000000000000000000004000004001804000200000000000000000000000000000020000000000005000000004000000000000150000000808000001020000000000000001002000100005010818628208500000a11218210020018408400f18040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000004000000800000040000000000000000000000000020000000000000000000000000000000800000000000000000000000800000000000000000000800000001018000000000040040000008000020000000080800000000000200000000004000000000000040100000000000000000000010008000000000200800100000000000000000000000000000000800000001000000000000000000002000000000080040000000000000000000000000000000000000000300000000010010000000400000000000000000000020000000010000000000080000000000000000000000010000000000000000000000000000000000001400000000000000000098040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000140000000000000000000000000000000000000000000000000000000d9f7000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000008800000180800000000000000001000080000000000800000000000080000000000000000000000000000000000000000000000000000000010000409400000000080020000000000000000000000000010000000002002000000000000000000000080040001000008000040000000000000000408000080002000898040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (030000100000000000000000000002000480000800932030020000000c80c00802000030030008200000000200000000000000000000000000420000000020800000000000000000000000000000000020000000000000000004000008000000000200000000010000000000000000000000000000400000002020000000000000c0010000000000000000100002005000000000000000000000000000000000000000000000000800800030030000080000c00c00000100010020000000000000000000000000000000000500000020000800000000020020010c00c20800001031030010000000c20c0000000000002000000000000000000000000000000000498040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00408000002000000020000000000000000000000000000000040001000000000000000000000000000000000000000000000000000045e300000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000020000000000000000000000000000010000000000c00c00a000010003003000000000000000000000000000000000000000000000000008000000008280000000000000000000000000000000000000000000808000000001001000000000000000000400000c98040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000805000000000000130000000004100c00000000000000000802000000041084112008048403042000a10210110100008408400020001002020000000000000000000000000004000400002082000000000000000000000000000000002000000000000040001008800800000080040100000000802000040000002000000000040000000004001080840000000000040000000000000030000050002004c00000000000000000000000000000002000100000000a009000800840100400021021000004000040800000000000000000000000000000000400008000c0a10c000400128105a40020421002008000850840a00500021c210000020000298040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000521909452000014864251480000521900000000000080000010000000000000000000000000000000282000000000000000000000000000000000000000000000000000000063a1000000000000000000000000000000000000000000000000000000200000003000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b00203220482228000000000000a040000000001402002400200210002800400086880000000000000000000000000000000000000000000c02c4003001000000000000020000000000000000000000080000000000000800a98040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000080000010000282000000030600000000000c18000000000030600080000010000000000000000000080000010000521909452000014864251480000521909452000000080000010000000000000000000080000000000282000000400000000000000000000000000000000080000010000282000000400000080000010000280000000000000000000000c18000000000030600080000010c1800000000000000008000001000028200000040000000000000000000000000000000008000001000000521909452000014864251480000521900000000000000000000000000000000000000080000010000282000000400014864251400698040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000633e0353509002b512cd501303774d9135024e0ddd36440809383774d9100004e0dc00000000000002d44b00000000000000000000000000000000008a02000000000000000000000000000000000000000000000000000a28a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000028200000040000000000000000000200000040001486425148000000521909452000000000000000000000000000000000000000000000282000000400000080000010000e98040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000004010004000000000420000000000000000000000002c7100000010848400155540100000005555000000000155540000080000000000000000000000000154471d1d4c0ddd36447475383774d9100004e0ddd3644c004000018b100000000000000000000000044001f01188427719c7c7c00000000000000000000000000000000440000002814c84118000000004fd5300007c190000006c100000000005555000000000155540000010425555000000000000000000100880000001180022000000000000000000000000000000000000080420000004c0ddd36440001383774d9100004e0dc0000000000000000000000000000000000000198040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000000000000000000000000000000000000000633c005056b0423130c14012038f718e0503498e3dc6380c0d2638f718e0000498e200000000000000c4c300000000000000000000000000000000014055000000000000000000000000000000000000000000000000000384600003000010000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003034a846110840c0c000000000030300000730000001303774d910013104e0ddd364400000000000000000000000000000000000998040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (638000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c71000000108484001a9a80100000006a6a0000000001a9a80000000420000000000000000000000088000000484e3dc63800012638f718e0000498e3dc639d40000005df100000000000000000000000044001f00188427719c7c7c00000000000000000000000000000000444200002914c84118000000007551000007c8980000000100000000006a6a0000000001a9a80000000006a6a00000000000000000000088000000118202200000000000000000000000000000000000008042000000480e3dc63800012638f718e0000498e00598040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000064308031c8000198c200c720000663080000000000000000000000000000000000000000430e0000010842c68b0000190c200c72550066308031c8000198c200c7200006630800000000000001182c00000000000000000000000000000000041a200000000000000000000000000000000000000000000000000007c5e000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000030315446110840c0c0000000000303000007300000012038f718e001f10498e3dc00d98040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000082840000190c200c7200000066308031c80000000000000000000000008000000000000200000004010000200000000000008000000000000000000000009c100000310884400001a80000000006a6a0000000001a9a800000088000000000000000000000001004c008064308839c8000198c220e72000066308031c80000000002810000000000000000000000008400000000c52633b8000000002020000000000000000000000000000000000288244100000000001ac0c000035738000000000000000000006a0000000001a9a80000000086a6a0000000000000000000008c000000510002300000000000000000000000000000000000000808000398040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000909000000603220c190000186c883064000061b2200000000000000000000000000000000000000005304000001285412ea4000180c887264550061b221c990000186c883064000061b220000000000000009a90000000000000000000000000000000020544102400000000000000000000000000000000000000000000000054f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030820cd2a18a80000000020200000000b98040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0080003005d0d631cac000000000420000000000012824000180c88306400000061b221c9900000000000000000000000008000000000000200000000012000840000000000011000000000000000000000009c190000310884400701540000000005555000000000155540000000040000000000000000000000009a91d00603221c990000186c887264000061b220c1900000000014a1900000000000000000000000840000000085673fbc000000000420000000000000000000000000000900001289644100000000005b5a8000035b2c000000000000004200c05500000000015554000000001555500000000000000000000185000002110006140000000798040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000140000000000000000000000000020000000000000000020000000020000000000000008000000000000000000000000000000000000000000000040000000400000000000200000000000008000000000001400000000000000000000000001400000000000050000000000001600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000569d000000a12040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f98040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000002000000000000000000000100000000000004000080000000000002000000000000080000000000000000000000000000800000000000004000000000000000010000000420000000000000800000000000020000000000000020000000000000000000000000000000000000000000000000000101000000000001000000000000020000000000020a0000000000082000000000016040000002000580001000000016000000000000004000000000000100000000000004000000000000000000000000000000000000000000000000000080000000000002000000000000000000000000000040000000000081000000000000400008020000580000058040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000040800000000000040000000000040000000000000000000000000000000000000001000000000000000000000000001000000100000000400000000000000000000000000000000000000000000000400000000000000000010000000000000404000000000000000000000000000000000000000000000000000000000000000010000000000008000000000000000000000000000000006000000000000000000000000000000000000000000000000007eb9000000000000000000000000000000000000000000000000000000000000000001000000000000040000000000000000000000000000000000000000000000000000000000000080000000858040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000040000000000001000000000000000000000000000000000000000040000000000001000000000000040000000000000000000000000000400000000000000000000000000000000000000010000000000000400000000000010000000000000002000000000000000000000000000000000000200000000000000010000000000000000000040000000000000000010000001000000400000000000010000000000000400000000000010000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000400000000000010000000000000000000000000000000000000458040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000020000000000000000020000000000000000000000000000000000000000000000000000000000000000001000000000000001000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000067f7000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200200000000000000000000c58040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000080080000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000100000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000040000000000040000040000002000000000000080001000000002000000000000000000004000000000000000000000000000000001000000000000040000000000001000000000000000000000000004000000000000000000000000000000000000000258040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0100000000000000800000408000000001000200000000000000100000000000004008080800008100200000000000000001000008000000000000000000000000000000000000000200000000000000100000000000200000000000000080000008000000000000000000000000000000000000000000000020000000000002000000080000080000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c6c000000000000000000000000000000000000000000000000000000000000000000000000000000a58040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000008001200000000200008000000000000000000000000000000000008000800000000200000000000008000200000000000008000000000080000000000000000000000000000000000000042000000000002081000480040002040000000000000000000000000000000000000000020200000040000000001000024040000000040800000000000000000000000002000000000000080020000000802040000020010080001000000802800000000000000000000000000000000000000000001000000000000040000000001000658040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000010000000000004000000000000000000000000000000000010000000000080000000000000000000000000000000000000200000000000000000000000000000000800000000000020000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000800000000000000000010000200000000000000200000000000000000000000000200000000000008000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af10000000000044040000000000000000000000000000e58040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000060400400000001800000000000000000000000000000000000000000020000000000000800000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000001000400000030010000000000000060000000000000000000000040000000000e000000100000000000000008000000000000280000000000000000000000000010000000000010008000000202000000000000082000010000202200000000000000000000000000000000000158040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2d0082000000000000000000000000000000003000000000000000000005800000000020020000000000010500000001408010000000050000000001000020000000000000000804000000000020000000000001000010000000040000000000000000000000001000000000000003000000000020000000000050000400000000014004000000000000000000000000000000000000000000000000000000000000000000004000400200080800080800000000000000000020000014c020008000001100000044000804000024100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008d92000000958040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000009b260000000000020000000000000000000000000000000000000000000000000000400000000000000000000000022000000000000000000000000000000000000000000400000001400060000000050208c00000000000000000000000000000000001400100000000050042000000001400030000000000000800000020014020100000000000000000000000000000000000500024001800014200100000000588810000000000000000000000000000040000000000040000000000000000200000208000000008008000000000000000000000000500800000000015004100030802d000100010250b42061010200000558040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0200400000001200410100000010210008410010408000000000000000000100002000004004000008000400000001000000000000000000000000000000000020000030c00000010000a00000000000020c00000000000000000000000000000004000000000000040000000940400000000a00000000000020000410000101000000000000000000000000011000000000400000400000000000000000000000000000000000000000000000000000000000004001000000000000044082004300000122104000000000100000000000000000012840001200080410080108000000000000002000000000000000000000000200000000000000000000000000d58040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000004caf00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000289000082010000008400000000000000000000000000010020400420810000810008010000000400044400040400000000000000000004000000000000000080000000000001000001000002000100004004044100104000022404000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009000000000358040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000004000000000000100000000040000000000900001100800584004846801064080000104860000000000000000000000040000420000000000000001000002000000000000000000000000100000200000804e00020090000000000000000000000000000000000000000000808000000100000000000004408802400000401a000004000000400000010000000001048000000000000000000000001000000000000080400180000000000000000000000000000010000000000000400000000000000000000004000004080630040010020000000001000000044004082000000000112680a000080045120a0002086000000000010000000000000000b58040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000800000000000000400000000000000000000000020000000000000000000000000000000000000000000000000000a210000000000200000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000040080693000000000000000000000000000000000000000000100000000000000200180082400000100080400000000000001001000000000004000000000000000000000000000000000000000024200000000906024000000401124a0000000000000000010000000000000000000000000000000000000000000000000000000000000000000758040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000080020000040002000001040000400004840041001140000040000000000000000020000800020041002800000a000000008002444000010000000000000000000000000040008000a10000c00001400000008000020900000000000000000000004020800000000000010000000004945190000000005490400000200024010010000000000000000000000000000000008000000000200080000000000000000000000000000000000000000000000000000000000002004000000001004001080104040300000004044000480000301002008000008000080004800424104100f58040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004000000000000000000010200210000000010200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000950b000000000200000000000000000000000000000000000000000000000000000000000000000010000000000000400000000000000000000000000000000000000000000000000084000000000000000100000000000000000000000000000108400000208000410000000080008280082004000204000000004000002000000000000000000001000000000000000000000000000000080000800080401040400800040000000000000000000000000000000000000000000000000d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000002001000080004042100012000004100001cc10040480000520000000000000000000000440000100001001000048000020000000000000000000000000000000000021000100040c000000100a102000000000000000010000000000000000000000000104000100000004000000080000220001080000088080000000000000002000000000000000000000000080000042100001000000000c00000800000000040000000000000000000000000000000000000000000000000000000000000000440040020001000900010010000008d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000000000049000040005000000400000000000000008001000000001240540000000040005101008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3b10000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000001000001000c00001004100820000020000000000000000000000000001000000840041000001020000010000020c0000040000000002000000000000800000000000000000000000000000040000010022001201000000e00040000000020100200000000000004d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000184801000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000818000000000800404000000000800120810010900000800000000000000000000000240401000000040040000020000000000000000000000000000000000000000000000000010004921050000000000000000000000200000000000000000000000006080000080000000000020004041a2100000010160304000000000000000000002000000000000000000080000040100081020000000000800400000000000000000000000000000000000000000000c0000000004000000002000cd8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000000020000000000000000200200000000008108100000000000000000030000000000000000000000001000000000000000000008008000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000d381000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000412040000000012480000000000000000000000000000008000000001000000000000001000200004082080000000000000020000000000820000000000000000000000000000000000008020000002d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000400200000000210340828000000440000200000000000000000800000000000000000000000000000000000000000000000000000000000000000000000020000000000400008040000010000000048000c00008001000130100002008000c080000000000000000010000000000000000000000408000000000004000000100000000000000000008000000000101000000014004000000000000000000000000000000000000000001041000000000002000c0000020980003000000800000000000000000000000000400000000000000000000000000400000000000000101000000000000002000000000000000000000ad8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c000002020000000000000802000000040a000000000000000001000000000000000000000000000000040000040000001000000000040040000000000000000000000000000000000000000ca06000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000101010000000004002000000000000000000000000000000000002100000000000004000000008000101000000000000000000000000001020800000000006d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800100000800000000040000400008000000000000000000000600000000000000000000840000020000000400030000000000000800000000000010000000000000a00001000000000000000000000000040000000000000000000000000000000000000000000045000000000800000104000200020000000000000000100000000000000000000000100040000008040802000000020000000000000000000000000000000000000002000000000000000000002002000200000000000000000018000000041010001400000000040040000000008000001000000000000000040800200800000000000000000000000000000000000000000000000000000ed8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000040000000000000000000000080000000000000100000000000000000000000400000000802000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006cfb000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000602000000000000000000000000000000004000004800000000000000000200000008200000000000000000000000000000001d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000000000000000120400000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000400000000000000000000000000000800000000000000020000000000000480000000010030010000000010400000400000000000000000004000400000020880000000200008000000200000000000000000000000000000000000080000840000000000000000000000000000000800000000001001000000000000000000000000000000000000002000204210060000000100000000000000000009d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004024088000200000888400001000000000000000000000000000000000000000820204a082040000000000040000000022000000000000000000000800000820000008200020000300400048010020000000100220820400000010000800800001400024008400800000002100000040000000000000000000000000000000810000000000000000000800000000000000000000000000000000000007392000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000400000000000000000000000000002000000020000000000000000000000000000000000000000000000000000005d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000010010010020000000000800002022000088000100000002040002000000480022000000000000400000000800202000000000000000000000000000000000000000000000800006040800000400048000400000001000000000000008000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000902001030000020010a80848a20800102424000120900008000000000000200000000080104800000840022008000040000000000000000000000000000000000004000000000000040000000000000000004001000000000082000005080202000000000002000000000084000080100dd8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2080080000002802220000019003000000000000800000000000020000000000000800800000000020000000000010000000000000004000000000000000000000000000040000000000000000000020100024804008000200800000020008000804800125000000028824000000900200201000028100800840020000000c01200000040000000000000000000020000020020800800000000020020020000000000000000000000000000000000000a768000000000000000000000000000000000000000000000000000000000400000000000000000000000000000010000000000000400000000000000000000000000000000000000040000000000100003d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000800000000201400000000000010000200000040028248000000000000000000000400000000000000000000000001400000400000000000000000000000000000000000000000000000000200000000000100000000000004000000000000100000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000100000008008000000000100800004000000400048620000002001100004000010000200000000200004000000002001000800000010000000000000000200000000000008000000000004000000000000200080002000000100200000800008000020820900100bd8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0240000020021000000000400000400000280000000000000000a80410000000020082020100000002002000060003000001020800800000000020000000000000000000200820400c10410000000000010000000000c00000000000040000000000200200008000924000000034004102900104000208000000d00100000000010000000004010100000000000000000090000051040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a5d3000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000007d8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000008008400000428000001000000200000000020208000000001000000048000000000080010020000002000400080443400080001001000200020808000810000000000000000000000000000000104000000000024014904800000000000000400000000000000000000000000000000000400000000000004000000000000000040000000000000000000000000000000104000000000120808100c002020012000205120402b4200800400412000400c00000000000000000000004000034426000000100000000000000000000000100000000000000000000000000000000000000120080000fd8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000400000080000800003000000000080080000000000000000004000000001040000090000000000000400811040014000040000040200400031080000000000000000010000000000000000000000000020000000000000008000000000000000000000000000080000000000040000000002800200000004410203000010008408c00400000021000000204204000300100100101008004820002840000000000021200040800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf3300000000000000000000000000000000000000000000000000000000000000000000000000000000000000038040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000040000200300040102200000001000000000000000000000000000000000000200080000000004000000000000100040100000004000000000000000000800000000000000000000000000010000000041010000000001000041000000000010000000000000000000000000000000000000000000000000000000800000000000000000000000000c000000000000000000040410200000004200804200000001001000000400820c00000000002000000004000000000100000000000000000008828000000200000000000000000000000000000000000838040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000040010000000000000000000000000000000002202a0000014000400001001420000000000000000000000000000000000000000000000000000008010480000000208008000800000040020000000000000000d00420000000010040000002000d01000003001000054340000000000000000000000000000000000000000000000000000000000000002800000800140040041010200040040300000000000000800400000000020e0140001901280c020011040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f09000000000000000000000000000000000000000000000000000438040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000010020000000400000000000000000000000000000000000400000000000010010000001000410030000040002800000000000000000000000000000000000800244000000000002000400000000014020000000001000200000008000000080000000000000000000000000000000000000000008000000a00880100000020001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000a0000008000000020400b00501280a4081442001004010000000000000280c000000000000000400000c38040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000041000000400902094000100080006c00000000000000000000000000000000000a00200040054000020202000000000000000000000000000000000000000000040000000000000002008094000000020002d00000003000230000000000000008000000000000000000000000002800000000000000a02b4000000000000000000000000000000000000000000000000000000000000000000502000a00000008000140000000200000000000000000000004020008000002004000000000001080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000680b00000000000000238040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000b3530000000000040000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000100002020000004001000000000000000000000000000000000000000010002000000001100000000000040000000000000000000000000000000014000000000000000000000000000000000000000000000400004000004040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000500000000040054000030010000000000000000a38040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (800140802580408020060a000028000682000000000000000000054000100000100080000000001002000400000000000000000000000000000000020000000408000000000800000000000000000000000000000000000000001000000000000000002040100040000000442000000000000000000000000000000000000000000000020000000000000400000802000000000000000000000000000000000000000000000000000000000000000018040000000000001020010004000000005020000000000000002000000010000000208920401800000000005020000000000000000000000000000000000000000000000000000000000000000000000000638040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000a3a30000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000800800280150004020400004000000000000000000000000000000000000000002002000000000000400800000000004001400000000000000000002000000000000000000000000000000000000000000000000002402000000004000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200214000500018000000e38040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000010020000800420000800440809000120005080452030900092010804480010800400000000000002000120008840100c0090448618403001211211210000000000010000000000000000080088023211000008008909000000000000000000000000000000000000000402000000000000002140910448508489043210214210090008408408400000000008400000000020220000008008008420000000000208008000000000004000000000000000000000000000000000000000000010020001000101000a00010010004040000800000000000000001000400010080084848281420089000220010000200000000000000000000000000000000000138040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d8750000000000020000000000000000000000000000000000000000000000000000000000802000200020000000000000000000000000000000000020210000000000808800240010212649001000000480440000000000000000000000000000080208000212800000008489040000000212648401002000000000000002000040000000000000000000000000000000000000000000002400900090020004040000800400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000938040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000008000100020000500004040810048800400420000800000000000000000200810200806000000218428018408000600210a0000000000000000000000000000010010881022000080000820880000000000000000000000000000000000000000000000000000000808005840800868100861021021020000000840800000000090880000000021020000000000180006000200080020a208000000000000000000000000000000000000000000000000000000000020001000102000100000004800502004000200000000000000000200008000000074000081029014600000000538040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000000000800800000a00800001800000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003bf70000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000008008000200010020000000000000601060000000000000000000000000000080000010600000000008208800000000200404401000100080040000000000040000000000000000000000000000000000000000000000100000004000004042002000100000000000000000000000000000000000000000000000000000000d38040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000080a000080002000000000080081002000000000200100090040600000000000000000000000000001000000008000000000040000002001000001000000000000000000000000000000000008011000000008020080040000000000000000000000000000000000000008000000000000000000000000000000000401000000000010000000000000000280000000000000000000008000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040020004080020880000000000000000000338040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00040080000000000000000000000000000000000000000004002000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c08e0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000020000000008000800000000400000000000000000000000000000000010040001000408000000020000000002050000000000000000000000000020000000000000000000000000000000000000000000000200900000020000080000000400000000000000000000b38040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10008000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000002000480002000002002004000000800000000000000100000000000080400000000000000000000010800100400000030c30000000000c00c00000000000400000000000000000000040480c00000000020020100000000000000000000000000000000000004000000000000000000000000030830000110000c20c0000000003003000000000003040000000020080000000002002000000000000300000000000000010000000000000000000000000000000000000000000000000000000000000000738040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000001002000000000000080004c0230100210008400000000000000008000000000c0053400ca081004400002001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042ca00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00000000000020000200000804800008000000000000000000000000000000000000000000000000d0000000002003000000000080080000002000000000000000000080000000000000000000000000000000000000000000000000000000f38040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000001000c00020030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010040000800420409000400810008020002020410c210a1200a40800040000820400000000000000000040004800401200100180084000000012106000000000000000000000000000000200508032050000020090080400000000000000000000000000000000000010020000000000000000c10900080084030200002102100000400084080000000000080300000002002200000040001008000000008000420400000000000000000000000000000000000000000b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000800000100002820000004000000800000100000000000000000000000000000002820000004000000800000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000509600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000202200000000088088000401000150230010040004010100000000000000000000000000000000400002400010020090080200000002020280000001000000000000008000000080000000000000008b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000000000000002000000400000000000000000000000000000000000000000000282000000400000080000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000010001002000000400000080000010000282000000400000080000010000000000000000040080000010c18521909452030614864251480c00000000000000000000000000c18282000000430600080000010000000000000000000000000000000280000000000000000000000000521909452000014864251480000521909452030600080000010c1800000000003060008000001000c1828200000043004b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000155540000080420055550100431108000000000000000000000000000000000000000000000000000000000000002d44b0000102207711c744000000000000000000000000d408000000000351d1040200800d4d400002d44b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a900000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000c18000000000030600000000000c18282000000430600080000010000000000000000000000000000c18082000000030600080000010c18282000000400000000cb8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (003aba8000004420eaea18842110840000000010000000000000007311c000000000000000000000000000000000000000000000004188a8000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000154478000000019500074740000154471d1d0154055000007400001544700000000000000400000002020055554c0ddd36455555383774d91000000000000000000000000000eaea00012c0013aba80000203bf00000000000000000000000000000006204200000000000000000000304c0ddd364400c1383774d9100004e0ddd3645555400002108855550000002b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (e0000498e3dc639a9a80000210886a6a0000000001a9a8000008042006a6a0100431108000000000000000000000000000000000000000000000000000000000000000c4c30000680007711c740000000080100000000000000140c000000000051d0044211000141400000c4c300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cb4f000000028a400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005555000000000155540000000005555289ce37085555400000dc21000000000000000000000000000eaea010001100ab8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000151505000110005454000004400151518842110840000000000000000000000007311c00000000000000000000000000000000000000000000000018c578000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000880000000000195440000000000880000002848c2280010000000088000000000000000000000000000006a6a480e3dc639a9a92638f718e0000000000000000000000000001515000828000054540000203bf0000000000000000000000000000000620420000000000000000008030480e3dc63880c12638f718006b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000064318839c8000198c220e72000066308031c801a800001108c6a6a0000000001a9a8000000808006a6a1049023021a9a800000000000000000000000000000000000000000000000000000000001182c000058000423b154000000000200000000000000000000000000001d1d00042a18000000000031a2c00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0ce0080800000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000006a6a0000000001a9a80000000006a6a391485511da9a80000154470000eb8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000006a6a22c9a622b1a9a80000188ac00000000000000000000000000000157d000000005454000008400151500c52210a8000000000000000000000000021a000000000000000000000000000000000000000080000000110c220000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001004c0000000006d000000000003024c000011410c0840000000003024c000000000000000000000000000006a64308031c9a9a998c200c726a6a0000000000000000000000000152145124000545400000103600000000000000000000000000000000204200000000001b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000020560000000000000000000000603320c990000186c883264000061b220c193015400001118d555500000000015554000000909005555100942342555540000000000000000000000000000000000000000000000000000000000009a9000020814427b554000000042000000000000000000000000042001d1d00040318400000000004ba9000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008cca000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a0000000001a9a800009b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000c05500000000015554000000000555513856417bd55540000105ef000000000000000000000000000c0ea7d00000027aba800000840beaea00856214ac000000000000000000000000025a4000000000000000000000000000000000000000100000c0134c55c00000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009a90000000006d0240000000004ba91d1d2289e128240000000000ba9000000000000000000000000010c055603220c191555586c883064555500000000000000000000000c0ea7115c25027aba80000010bb00000000005b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010000000000400000000000000010000000000400000000000000000000000000000000000000000200000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000040040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000593e0001000400000000000000000000000000000000000000000000000000000000000000000000010000000000000000db8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000001400000040004001100000000001104100000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000101001000000000000004000000000000000004000000080000000000001000000000000000000000000090000040000000000000000000000100000000000000000000000000000000000000004000000000000000000000000000000003b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000008000000020000000000000000000008000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000200000000000000000000000000000200000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000001800000006000000000000000000000000000000000000000000000000000000c0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009fb20000000100004000000004000000000000000000008000000000000000bb8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000020000000000000000000800000000000000000000000000000300000000000000000000000000000000000000000000000000000000000000000000000024000000000000000000000000000000020000000000000000000000000000000007b8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00008000000000000000000000000000000000000000000000200000000200000000000000000000200000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000008000000000000000000000000000008000000000000000000000000000000000000000000080040000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000546e0210000008000000000000fb8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000770800c000008200400000000200000000000000000000000000000000000000000000000000000000000000000000001400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000210000008000000200000000000200000000000000000000000000000000000000000000000000000000000000008000000000000000000200000000000000000000100100000000000000000000000000000000000000000000000000000200000000000000000000000000000008000000000000000000000000078040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000001002000000000000080040000000001000000000000000001001000000000000000000040080000000020000000000000000080000000001000000000040000002020000001000000000040040080000000000000000000000040000000000000001000000000000000000000000000000000000000081000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000040000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000878040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000b00d00c000008000000000000200000000000000000000000000000000000000000000000880040800000002001000000000000040000000000001000000000000000040000000000000000000000280000000000002000000000000800000000000042000000000000000000000000000000000000000040000000000000000000000000000400010000008020110410000400000000000000000040000000008000000000000000100000000000000000010000020020000000000400000000010000000000000000000400000000000000000400000000010000000020100000000008000000800478040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000400000000000000000000000200000000000000a80000000000000000000000000000000000000000000000080000000000000000000000000000000008000000000000000400000000000000000000000000000008000010000000000000000000000000000000000000000000000000000010000600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060c00000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000c78040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000036710210000000000000800000000c0002000000000000400000000080000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000018000000000000000000000000000200000000000100000000000000400000000000000000000000000100000000000000000000000000000000000000002000000000001000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000c00000000020000000000004000000000000000000000000278040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2000000000000400000000000000000000000000002000000002010000000000000000080000002002000000000000080080000000000000000000000000002082000000000000000000000080000000000000000000000000480008000000000000000000000002000000010000000000000080080000000000000000000000080000008000000002000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a78040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000020000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e64d000000010000000080000400000002000000000000000000000080000000000000000080080400000002002000000000000080000000000002000000000000000080000000200000200000000480000000000002000000000000000000000000002000008000000000000000000000000000000000000000000000000000000000000000000000000000020100000000000000000000000000020000000000000000000000000100000000000000000020000020020000000000800000000000000000678040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000008000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000208000020000000000000000000000000000000000000000000000200000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000e78040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000002000000000000000000000000000000000000000000000000000000000016f3000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000178040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000008200000000000000000000000000000000000000000000000000000000000000000010000004000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000978040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000200000000000000000000000000000000000000000000000200000000000000000008000000000000100000000000000000000200000000000000000000000000000000000000000000000000000000004bde000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000578040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000804000808000000000000000000000000000000000000000000008200000000000000000000000000000000000000000000000000008000000208000000000004000000000000000000000000000000000000000200000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d78040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000010000000000000010000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c60000000000300000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000400000004000008000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000378040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000008000000000008000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b78040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000006e99000000000300000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000778040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000080000000000000000010000000000000000000000000000000000000000000000000000000f78040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000001000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000ebfc0000000003000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000004400000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000802000002000000200000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000200000000000000000000000000000000000000000400000000000000000200000000000000000008f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000400000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000006020000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000077b40000000008400000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000004f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000800000000000000000000000800000000000048000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000010000000000000000000000000001000000000000000010000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018000000000000000000000000000000000000000000000000000000000000000000400000cf8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000004000000100000000000000000000000000000000000000000000000004000000000000000001000000000000000000000000000000000000000000000000100000000000000000000000040800020000000000000000000000c00000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9fb00c0000003080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000180000000006000000000000002f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000400000000000000000af8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010000420000400000400000010000000000000800000000010000000000000000000000000000010010000000400000410000000000000000000000400000000000000000000000000400000000000000000100000000000000004000000000000000000000000000000000004000000000004004000118200008000000100000004000001200000000000000004100000104000004000000100000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000065420210000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000006f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000000000000000000000000000040000000040000000000000000000000000000000000000001000000000000000001000001000000000000000000000002002000000000000000004000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000010000000000400000000000000000000000000000000000000400000000000800000000000020000000000000000020000000020000000000000000000000000010000000010000000000000400000000000000000010010000000000000000000000000400000000000000000000000000000000000000000000000000400000000400000ef8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000002000000080200280000000000000000004000000000002000000000000000000000000002000000000000000080000000002002000000000080000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000100020000000000000000000c00000000040000800000020000010000000000000000020800000820000200000000800040000000000000000000000000000000000000800000000000000040000000000000000000000000000000000000000339200c0000003100000000008008000000000000000000000000000000200000100001f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000008000008000200000000000000000000000000000000000000000000000000000000000000000000000000000418000400000000000010010000000000000000020800000000028000000000200400000000000020800000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000080000008000000000000008000010000000000002000080000000180002000000000000080000000080000000000000000000000000000000000080000000000002000000000000000000080080000000000000000000000002000000200000000000000000000009f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000200000200000000000008000000000000000000000008000000000000000000000000000008000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000002000000000000000000000000000000000000000000000000000000000000000020000000000002000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000099b70000000000000000000000008800005f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000d007000000000000000000000200a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000001801000000000000000000040000000000000000000008040000000000800000000000040000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000df8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000c0000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000020020000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001400000000000000000000030000008000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000003f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000062a400c000000200000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028000820000000000000000000000000000000000000c20000000000020000c0000008000003000000002080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000bf8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff8040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000804040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000404040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c04040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000204040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a04040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000604040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e04040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000104040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000904040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000504040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d04040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000304040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b04040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000704040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f04040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000884040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000484040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0100000000000000000000000000000000004000140000004000005000000000000000000000014400000000000000004004000000000100000008200024000001000000000000000020004000000000000000000000000000000000000000000000000000000000000000000011000000000000200000200000008000000000000000000000000000000000000820000000000000008000000000000040000200000000000000001000200000000000008000000000000000000000000000000000000000200000200000000000000000000000000000000000f00500000014000000000000000000000000000000000000000000000000000000000000000000c84040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000020000000000000800000000000020004000000000800000000000000000000000000000000000000000040000000000800000000000000000000000000040000000000000000000000001000000000000000000000000000000000000000000000000000000050000000000000044000000000050000000000001400000040040001001000400000004000000010010000000000000004000000100000140000004000000040000000000000000080002000000100004008001000000000040000000000001000000000000000000000000001000000000800000001000000000000000000000040000000000051000000000000040000000000000284040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000100000000060000000000000000000000000000000000000000000000000040000000000040000000000000000000000000000000000000000000000000000000000000000000002101000084808000000000000000000000000000000000000000000000000000000000000000000000000000200000000000040000000004010c00000200020408008000000000000000000000000000000010400000000000000430000000000000000800000000000000000c0001000000000020040000c00000060000000000000000800000000001000000200000000000000000000000000000000000841200000000040000000000000000000000008000a84040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000004008000000000100000000000004000000000080100000000000004000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000004000000000000020000000000000000000000000000000000000000000000000000800000000000040020000000000000000000000000400000000000000000000000000000000061000020000000020000000000000000000000684040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000080001000080000000000000000080000000000002100000000000040000000000001000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000040040000000001000000000c0004003100000000000000000020004000000000000000000000000000000000000000000000000000000080000000000001000000000200000000240000801001000000000000000000000000000000000000000000000000000000000000000020080200000000000000000800000000000020000000c0000000000000000000000080000000000000000000000000000000000000000000000000000002cb00e84040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000073210000000008000000000000000000000000002000000000000000000000000000000000100000004000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000040080001000000100000000000000004000000000000000080000000000000080000000000000080000000000000000000000000000000000000041000000000080000000000001400000000000000000000000001000000000184040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0010010000008000000000000000200010000000000010020000000000000000210004000800200000000220000000000000004000000000220000000800000004000800000000000020000000800000000000020001000000000000400020010000000000800000000400000000000000020020408000000000010000008000000000008004000200000000400000000000000000000000000000000000000000000002000000000000200000000008408000210080000000400000000000000000000000000004000000008000000000000000000000000000000000000200200000000000008000000000000000000000000000400000000000200200000000984040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000040000000000000040000000000000000000000000000000000000084ce0000000000000000000000000000000000800000000000020000000000000800000000000020000000000000800000000000000400000000000020000000000000000000000000800000000000000000000000000000000000000000000000000000200000000000000000000000010000000000000000000000000000000000000000000004000000000001000000000000000000000002000000000000004004000000000000000000000000004000000000000000000004004000000000000001000000000080088000100004008000000000000000004000100000584040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000008000000000000020000000000000000800000001018000000000008000000000000100000000000800008600800000000000000000000300000000000000000000000000200000000000000200000000000008000000000000000000010208000000000000000000000000000000000000041000000000000000000000000020000000000020000000800000000000000000000000000000000000000000000000000000888c0000000000000000000010100000404020000000000000000000000000000000000004008000000000000000000000000000000000000000000400000000000000000000000000000000d84040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000500820000000000000100000000000000002000000000000000000000000000000000000000000000000000000000000765c0000000000180000000000001800000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008880000000000000000000000040000000000000000000000000000008000000000000000000000000008000000000000200000000000800000000000010000000000000088000000000000000000000200600200600000010000000000000000200000040020880000384040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000012000000000000080000000000000000000000000000080002080002002000000000000000000000000002000010000002002000080000000000010000400080008000a000020000000000000004000000000120000000800000004000c2000000000143028000080008000a0000200008000000000000000200200000000008000000008000000000000000200108040000000000200000000000000000000040000000000008000000000000000000000000000000000000000008000000000000020005000100000000140a4900000000000200000000000000000000000000104008800000000400000000000000000000000000000b84040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000001080000000000000100000480000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006a1900000000000000000000000000000000014212000000000000000000080014024000000000500110000000000000000000000008000000000000200000000000000004000000014090400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000a00000000000000000000020040a1000000084002800000000000000000000000000000000000000000000000000000000000000000000000000000784040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000200000000000000000100000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000004050000100000000000000000000000000000000000000000000000000000000000000c00000000000404c0000001000000000000000000000000000000000000000000000400000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000040000000000000000000000000000200001000000000f84040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000100004008200000000000c24000200000000000000000001000000434004000000000400000000000000000082000082000203e00200000000008000000000000000000000000e2ac00000000080000000000000000000000400000000000000000000010000000001000000000000000400000600000010000000000000000000000000000000000000000000000000000000000000000008000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000c0000000000002008000000000000000000000000000000000000000000000044040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000008200000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000010430000000000000000000000000000000000000000000000000164c14000000000000000000000000000000000000000000000000000000000000000800000000000121804000000000000000000000008000000200000000000000800000000000000000000008001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000180040000000004100000208000000008059000000000000844040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000008000400020000000000000040000000000000200000800000800000000000000000001248000028000000000000000000020000248000000000000400000000000020000000000000000200000000000000000000000000000000000000000e4e30000000000000000000000000000000000000800000000020200000000000804300000000000000800400020800200000000000000000000000000000000010000000800000000000820000000000000000000000000000000000000000000000000008200000000000000000000000000000000000000000000000000000000000000000000008000100040000000000000000000444040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000000008000024000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040001000000000000040800000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000044000000000000000000000000000000000000000000000000000000000000000120000000000000104000000000000000000000000000000000000000000000000000000000000000000000000800020000000000000000000000000000000000000000000000000000000000000000000000000000000000800040000000c44040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000004100080008000010c0020000000000000c00000000000000000000000800000000000000000041000010000010800000000000000800000000000000000000020000000000800200004000080000000000081000002080002080010080000000000000000000000000000000000000041ea0000000000000000000001000000000000000000000000020001000000000800000000000000000000400000800000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000244040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000880000400000000000000000000800000c00000020004010000002000000000000000000000000000100800000208000000000000000000000000000000000000000000000000000000000000000020000000001040080000400000000000000000000000000000000000000002080000000000000000000000000000000000000000000000000000040c04000000000000000000000000000000000000000000000002100000000001004010002080000101c000000400000000000000002000000080000000000000000001000000000000000008000000000000000000000000000000000000000000000000000000000000000000a44040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000200000000000000000000000000008040000000000000000000000000000000048600000000000000000004000000000000000000000000000000004000000000000000000400000000000000000000000000000009000280000000000000000004000000000000000004000400000000000000000000000000000000000ed9a0000000002000000000000000020000010820000000080010000000402000c00000000000020000020000010400000800000000000000000000000000000040000001000000000800000000000000000000000000008000000000000000000008000002080000000000000000000000000644040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040800000000000000000000000000000000000000000000000000024820000000000000000000000000120840000000004800000000010000000000000000000000000000408000000000000000000000c00000000000000000000000000000000000000000000301000200000000040000400000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010800000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000e44040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000040000000000001010000000000000000000002000000000000000000000000000000800000000000000000000000000000000000000040000000000001000000000100000000000002000000000000000000c000000000000010000000000000000000000000d8c70000000000000000030001000010400000014120000000000101000000c00004920000000000120c00030c00000100000000000000000000000000000000000000000000000000004820000000000000000000000000000000000000000000144040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000002000000000000000001000000012000000000020080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000004000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000800012000000000000000000000000000000000000000000000000020000000000000000080020800000012000000000000000000000000000000000000000000001000000000000000000944040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000100000100000000010002000000000000006000001000000100000000000000002004040000000000080000000004001000000000000000800000000000008000000000000000000008000000080200808000020000000000000020000000100008001860000000000000000000000000400000000000040000000001800840000000000000000000000000000020000000000000000000000000020000000000000000000000000000000000000000ad9a0000000000000000000000000000800001004020000100000400000000001014020000000040100000000000010000000000000000000000000000000000000000001000000001000820000000544040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000000000000200000000000000000000000000000002004000000000000000000000000000006000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800200020000000000000000000000000000000100000000000000200040000400000000000000000000000000400000000000000000000000000000000000000000000010080000000000000000000000000000000000000000000060000000000000000000000000000000004000000000000000000000000000000000000000004000000000000000080400000402002010000000000000000000000000000004100d44040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0080804010412082000000000000000000480000010000000000040400000010000000000000001000000000000000000000000000000000000000000000000000000040000000000000000000000000000000c000000100000004000008100000000200100000004000000000400800010000000000000004000000000000000000000000100000000400001000001040000010101000400010000000800000000000000020000000c0400000000020000000000000000000000000000000000000000007150000000000000000000000000000000000000000000000000000000000000000001900000000000000000000042000000000000000000000000000344040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000100000000000000000000000000010000000000000000000000000002002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000210000000000000000000000010000000000000000000400000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000104104100000000000000000000000000000000000000000100000100000000000000000000200b44040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000001000042020800002040800000080090000408881410400000000000000000004000000020000000080080000081000000020000c0000001000000000000000000000008200020000000040204000000000000400000000001002040000000000000000000080000000000800000000024020800800420004000080102080210000000000100000000020800020800000002000400000000100001000001040002004001000100010000000800000000080000020000000c00000000080140000000000000000000000000000000200000000d3bf0000000000000000000000000000000000010000000000000000000000000000000200000000000000744040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001100000000080042202000000200080800100000042200000000000080080000000020000200000000220820000020011401200000800000000000001002000000000000000000002000000000000000000020000000000000000000000000000000000000000000000000000000000000800028010000000020000000000000020010000000000000000000000400000020000000000040400800000011040000000000010040000000100000000000000000040000000480000000000000000000001000110000100000000000000000000000000000000000000000000000000000080002000000000082080080000000000000000000000000000000000f44040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000000000000000000000000001000000000000020000200020a0000000480000000200004001008000000000000000000000000080100202000080006400010000000000002000000010000000000000000000000000000082000000000040002000000002400000008000000104024000200000104280000101000004000000100000010080010000100000000000000204400000104000400000000020800000008000000000008000000000008200200000000000100000000000004000000000000048008000000000008000000000000000000000000000000000000000000000000000815b00000000000000000000000000000000000000400000000c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000000000400000000000041000000000004000000000000140000020000001000a0000000000002000000000000000000000000000020000000020800882080804820000000020082000000400002080080000000040000080000000000000000000040800000000000000000000000000000000400000800000020020000000000000000a1400000000002000000002090002400400000000000000000010000000000000800000400000000001018400000000000500500000100004004000000000104400008010000000000000080000000010100000000000000000000008008001000000000000000000000004000000000804020000000000000008c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000004000000000000000041000000000000000000000000000000000000000000000220000100000020000001000000000000000000000000000000000000000000000000000000000000000040000000000000c0400000000000080000000000000000000000000000000000000000000000000208000000a08008000200000000140000020200000000800000008120064008800400010000020000000000000000010000000000000000020800000000800004000000000028200100000000020000000000002100002000000080004008000000000000002080020000000000000000000000000000000000400000000bfd400000000004c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000de81000000001000000000080000000000800000004000080000980080861920005a05008000240100860100000001020000000000100100000000000000000000000020000000020000001200000000800800000000004000000000000400000004000000000000000000000000000000000000000000000000000020000000000000200200000000005000040020000000040200000000208040000000000000000000000000000000040000000000000001000000000000000000000020020000000080000000000000000000000400080000000000008000000000000000000080000000000000400400000000000000000000cc4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000020000000000000000000000040000000000000000000000000000400000000000000000000000005020000000000000000000000000000000000000120000004000000400000000000c00000000000000020020000000000800000000400000000000000100000000000000000000000000000000000000000000000000000000000005000000000000000000000000c10000000000220c500000000000008440010404000110000000000000104000000004000000008000000300000008000000000400000000000000000000000000000000000000000c08000800000040080000000000000000000820000000000000000000000002c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000200000002000000000000000000000000000000000000006757000000000000000000080800a0000020004000000008000028008030c208044204000000101000108000000004000000000000000000000000000100000000000010000820808040004c00000000020400000000020800800000000000000800000000000000000000800000000000000000000000000000000008000008000000000000000000002000008240000000000000000000000000000000000000000000000000000000000000000000000000000080020400800000000000000000000000450000000001410000000000000000000000000000000000000000000000ac4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000010040000000000010000000000000000000000000000000008000401000000000000000000000000000000000000000000048008000000000000000000000000000000000000000000000000000000000000000800000010040048050002a012000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000008200801000000120023020000000000c000000000000000100000000000000000002000000000000000000000000000000000000000040000000000000000000000000000000000000006c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000055c30000000000000000000008002000100000082104000001800018000000000003c03c0000000808200000004008080200000000800c0000000000000000000000000000000000000020010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a00000000000000000000000000000000010000028000000140a000000000000000000000000400000000000000040000000000000400000000040000000000000000000000000020000000000000800400000000ec4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000010000000000001000000000050000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000008003400000000000000000000000000000000000000000000000000000000000000000030000000005004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800280010000000008000000000000000000000000000000000000000000008008000001000000000000000000000000001c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000200020004000000000000000000000000004200000000000000000000000000100000000000000000080000000000000000000000000000000000000000009de200000000000000000000000080002000502002000080000080000800000000000000000000020000002000000000800000000000040000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140000010000000000000000a0040001002800000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000009c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000001801000000000000020000000000000000000000020000000000000800000000000000820000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000008004400000050280000000000000000000000000000000000000000000000000000000000000000080040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000002000000c00000000280000000000000000000000000000000000000000000000000000005c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002100200000000000000000000800040010010080000800100000000000000000000000800240008000000000000000000000010020000000000080010000001000000000000000000000000000000000000616a000000000000000000000000000000000000408500000000000010000000000400400000000010400000000000020000000000000000000000000000000000000000000005028000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000004000100000000000000000000000000000000000000001000000000000040000000dc4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000408400000000010220000000008408400000000020020000000000000000000000000210000000000008400080020210a2000000000080080000000000001000000000000000800000004000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000008002000100000000100020000000000000000000000000000000000000000000000000000000000000000000008001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020210000404000088820090000202a048000000000008000003c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08a8880000000000000a8000000008098000000002000600000000000000000000000060000004000000000000000000000000000000000000000010000000000000000000000000000000000000000000000401800000000000000000000000000000000000fc2c0000000000000000000000408000000140094410400000004422480000000114114000000002482420000020210212000000002400400000000100010000000000000000010200002001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040004000200800000000000000090048000200a0100040000404000000000bc4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800480002002010000000040400000000000000000000000080880000000022022000000000000000000000001000000000000000000000000000020000000000800880000002000006000000000100880000000000000000000000000000000000000000000000000000000000000000000000000000000000a000000000000000000000000000000000000000000000000000000000000000000000010000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000202000000020007c4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000001000000000010040040010002000040080000000000080000000000000000000000000000000000000800000080030000000000000000000000000000008000000000000000000000000000000000000000000000800000000020000000000000000000000000000000000000463000000000000000000000840000008001001081080400000042240000000001001000000000840042020000011001000000000240440000000008001000000000000000001020000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000400020000000000000000fc4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000004000000000000000000080100004004000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010004000000000000000000040000000000000000000000000000000000000008000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000020000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000c00000000010020400000400800c00000000000000000000000c000000000000000000000008000000040000000000000000000000000000000200000000000000000000000000000000000000400000000000000000001000000000000000000000000000000000000003e70000000000000000000000000000000008000080000000000000000000000000020000000000000004000000020080800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000824040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000100000000000000000008004000100100000200000000000000000000000000000000034000000000100900000000020020000000000000000000000000000000000000400c000000000100200010001008008200000000000000000000000004000000000000000000100000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000200000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000424040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2800300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023000000200800803010002003302000000000000800000000020000000000000000000000008000000080000c000080030000000000000000000000000000000000000000000000000000000000000000000004001000040000000000000000000000000000000000000056f400000000000000000000010000000000000408444000000030210000000002c00c000000000100101000000004084000000000100100000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000c24040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000100000110008000004000000000000000000000000000000000800000000020020000000000080080000000001002000000000000000000000002024000000000880800008000004080c000000000c0800000000000000000000000000000000000000000000000000000000000000000000000000000000000080280a0000000000000000000000000000000000000000000000000000000000000800000000000050054020a010000000000000000000000000000000000000000000000000000000000000000000224040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000008000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000c18000000000030600080000010c18282000000430600000000000c1800000000000000000000000000000200000040000008000001000000000000000000008000000000000000000000000000000000000000000000000000a00000000000000000000000000000000000000000007b8c000000000000000000000040200008000009409200000000240250000000011489480000000050440000000001111200000000240040000000000001000000000000000000000000000100000000000000a24040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000200000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000101000000000000040000000000000000000000030600000000000c18000000000030600000000000c18000000000000000000000000c18000000000030600000000000c18280000000030600000000000c0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000624040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000004488000000000000000000000000000000000000000000000000000000000000000000000000000000000005555000000000155540000300635555722a02011955540000000005555000000000000000000000000000000007711c0000000000020000000000000000000000061000030000000000000000000000000000000000000000000a02300000000000000000000000000000000000000009b870000000000000030600000000000c1828200000043060a000000000c18282000000430600080000010c18280000000030600000000000c0000000000000000e24040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000155540000000000000000000000000000000000000000000003708400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001555400000000055550000000001555400000000055550000000000000000000000055550000000001555400000000055555294c00001555400000000000000000000000000000000000001000000000000000000000000000000000000000000000000000003030040000000000000000000000000000000000000000000000000000000000000281c000000000000000124040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000881c0000000004c4c00400000000000000000000000000000000000000000000000000000000000000000000004488000000000000000000000000000000000000000000000000000000000000000000000000000000000006a6a0040000001a9a80000200636a6a62aa111119a9a80000000006a6a000000000000000000000000000000007711c00000000020210000000000000000000000610000300000000000000000000000000000000000000000000450000000000000000000000000000000000000000083d4000000000000015554000000000555500040040855554628800000555518842110855554000004421555518800924040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (006a6a1884211085a9a80000044216a6a18a2000001a9a80000000000000000000000000000000000000000000005511c0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000131000000000000000000000000131004000000004c400000000000000000000001a9a80000000006a6a0000000001a9a80000000006a6a000000000000000000000006a6a0000000001a9a80000000006a6a10bee00001a9a8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030300400000000000000000000000000000000000000000000524040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000004c010000080800000000000000000000000000000000000000000000000000000000000000000848c00000000000000000000000000000000000000000000000000000000000000000000000000000000000006a0000000001a9a800000002a6a6a0f0080a101a9a80000000006a6a00000000000000000000000000000000423b000000000000220000000000000000000000130000000000000002000000000000000300000000000000008b268000000000000000000000000000000000000000deff00000000000001a9a80000000006a6a0000004085a9a8620000000d24040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a80000000006a6a00000400a9a9a80200000006a6a00c52210a9a9a800000842a6a6a0080000001a9a80000000006a6a00000000000000000000000000000000622b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000131000001000000000000040000000000000000001a80000000006a6a0000000001a9a80000000006a6a00000000000000000000000006a0000000001a9a80000000006a6a206f200001a9a80000000006a6a00000000000000000000000000000000000000000000000000000000000000000000000000000030300000808000324040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000003030000010800000000000000000000000000000000000000000000000000000000000000000420000010000010800000000000000000000000000000000000000000000000000000000000000000858500000000000000000000000000000000000000000000000000000000000000000000000000000000000c0550000000001555400000812b55552223c001255554000000000555500000000000000000000000000000000427b40000000000002000000000000000000000013009000000000000040000000000000030000000000000000440500000000000000000000000000000000000000002302000000000000000100b24040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000080f400000000000003015400000000055550c002404ad5554020500000555500856214ad555400000852b555500814000015554000000000555500000000000000000000000000000000417bc000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000008000000000000200000000000000030154000000000555500000000015554000000000555500000000000000000000000c0550000000001555400000000055550d2be000015554000000000555500000000000000000000000000000000000000000000000000000000724040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000800000000000020000000000000000010000000020000000000000800000000000000c000000000028000000000000000000400000000000000000400840000000000000000000000040800000004400008000000000001600020000000000000002000000000000008000000000200000000000000000000108000200000000200000000000000010010000000000402000000000580000000000002000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016000000000000500000000000014000000000000000000000000000f24040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000008d73000000000400400000002000000000000080000000400400000000000400000100000400400010010000010000000000000000000000000000000000000000000010000000000000001000000000020000000000500000000000000000000000000080000000000002000000000000010000000000000000000000000005900000000004000000000000005900000000000140008000000000000000400000000000000000800800000010000000000000000000010800000400004000000000000800000000000020000000000000810000000000164000040004000000000000000020000a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000010000108000400000000000000010000000000000440000000000010000000000000000000000000010000000000000400008000000000080000000000440000000000000000002000000000008000002001000000000000000000000000001000000002000400000018000010000000000000000000000000000000000000000000000000000000180000000000430000000000010000020000000000100000000000000000400001004000040400000100000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000008a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b08c0000000000000000000100000c0000000404000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000020000000000000000000000000000000000001000000000000400000000000010000000000000000000000000000000000000000004000000000004000000000000004000000000000000000000000000000000000400400000000000004000000000000010000000000000000800000000000000000000004000041000000100000002400004040041004a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000208000000000000050000000200208000000040009400000000000000000000000000000000008000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000002000000000040000000000000000000000080000000000000000000000000000000020000000000000000000000000000004000000000200000000000000000000000000400000000000002000000000000010000000000404040000080000002100000000000000000020010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ca4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000d44d000000000800400000000000000000000002000000800400000000000400000040000800400020010000010000000000000000000000000000080000000000000008000000000000008000000000000000000000000000000000002000000000000000000000000000000000000000010000000000000000000000000000200000000000000000000000000200000000000000000000000000000000000400400000000001000000000000000020000000000000000000000000004000000000002a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000020010000000400000000010000000800000000120028000000000000810000000000020000000000020000000000000020000000000000800000000020020000000000000000010000001020000000010020800020000000000400000000002a00000010000000000000000000000000000000880000000000420010000000000080001000004000a10100000000020000000000000000000000000800004000000820000000000000000000000001010a000a00000000200408200000000000000000040000000000000000080000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000aa4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000080000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000080000000000002000000000000000000000000000000000000000006049000000000000000000002000000000000080010000000000000000000000000002000000000000000000000001000000000000040000000001000100000000000040000000000001000000000000000000000000020000000000000800000000020080000000000002800000000000020000000001000000000000000000800000000000000000002000040800000000000000012000000000000000000020000000000000000800000010000000006a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000000000000000000000000000000c2400000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000090000000000000000000000000000000000000004000000000100000000400000000000000000008080000200000000000000000000000000000000002000000000004000000000000002000004008000000000000000000200000000000000000001000000000000000000000000000000000000000000010000000c00000000000010400000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000ea4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000800000000000004040a00004000000000000000000000000000000000000000000000000002f340100000000060000000000000c0002000000000000000000000080000000000000000000000000000000000000000000000000000000000000900100000000000000000000000000002000000000010000000000088000000000024200000000008000000000000000200000000000008000000001400000000000000000800000000000000000000000000800000000020020010000000000000000001a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02b4004000082202800000000000000000000000200000000000000014020000000000000004000000200000000000000000000200000014030000081200540400000000014000000000002d00000000c0020000000000000050010400000001400010000020050008000000000000000000010050000000000021402400000200000000000200801508020020200000040000208000000000000000800000000000020020000000000000240000004001521100000010050080000000000000000000000800004000001820000000000000000000400000001502040000000050032000000000000000c0000800000000000000001400440000000050001000009a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000400000000080002204000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000210120000000080000c0810000000000000000000000000000000000000000000e8bc01000000000000000000000000000200000021000000000000008000000000020200000000000000000000000200000002000008000000000200010000000000008000000000000200000000000000000000000000000000000000000004000000000000100000000002800000000000000000000040000000000809040a000000000000000000004208005a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002000000120000000400000000008080000004040202000000821000000000000000000000000000000000000000100000200001200800000000000a0000000080000202120000000808000000000000484000400000000000000000000000000000000000000000000000000000000000202000000000000080000000000000000000000000000000000000820100000000002000000000000444000000000000080000000001080000000000000100000000000000000000000000000000000000c0004100000000200000000000000000000000000000000000000000000000400000000000000000009000000000000208000000000000000000000000da4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000024800000000000000000000000000000000000040040200000000000808000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002412800000280040400100905021000080000000000000000000000000000000000000baa5000000000000000000000028a00001000000811000030000028000081800000000000050000000000000000000000000000000000000000000000002000000000000200004000001010040000000000000400040000000000000000000000000000004540c00000001000000000000000000000000000000003a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00400081410400000000000000000000002000000030000480040000901000100800000000080c00000000000000000000000000800000000000000000000000080410000000000000204000080000a080000000000008000000000814f60000000000084000000000800000000000000000000000000000a00000000000008000000000804400000000000000000000000000000000200000200000040000804000000000000000000002000804230800000000000000010010008000600000000040020008000000000000000000008020002010804b802000010001204000000000000000004000000000000000000000000000000000000000000000049200ba4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000000000010000000000000000000000000000000000000000000000001200000000000000000000040000008000010000c40000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000131146000000040132102120082000800000000000000000000000000000000000000cbe0000000000000000040002011400010400080020000000000100200000000000000000000000000000000000000200000000000020800000000000020080100000020000000006000020000000000000000020010002000000100000000800040000140418080007a4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000000001000000000000400000500802000040000040820000000000000000000000000000080000048a00000010000008000000800008001400020000008410000000000000000000000000000000000008200000000100000424200000000024900000004000080200000008200000000000000c10000020009010000000000000000001200000000000000000000000000004008100400000000000010000000000000000000000000000000400008400000000000000400000080008000000000000000410000000100004108000000000208000000000000010000000000400000080108000200000008000000000000000000000000000000000000000fa4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01004200020000000000004000000000000000000000000000000000010000000008000010000000200000400000400000000000000000000000000000880000400000002000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800084000080000c0206200000804000840000000000000000000000000000000000000846600000000000000000000200000000000008040800000800008820010000000040000000800000000000000000020000400000000000000000400004100010010000040100400000022000000000000000080000000064040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (84000020000000810000000000000000000000000000002000010828010000400200888000000020000000000000000000000000000800000200000c401000004811000002008000004c00000200000100040000084000008000000000000000000000020c00000844200000509000002000004101000000000014400a00000c00001002100020800020000000c00000000001120000000000000000080000000020002000080000c000008020010200000400000000000000000a0020080040000000c04000800080000000000088000c200810000800001400000c2000022200080200000202000002000003210000200000a13000000000c010808200001200864040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (100020000040004000000000404000002020022001000000000000000000000000000000000000000000000000000000000002000492080000000012402020000000000000000000000000000000000000809000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004804100540000124800012000004a000004000000000000000000000000000000000000000145800000000008000010000100000000400404000000000800000800000420000000000010000000000000000000000000000800000820000080000421010000000011400464040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000008040010001410001000408040000000000000000000000000000100882040000000200000400000800020a00a2140000002010000000000000000000000000000000020120800000000000000400000000104000004880004100000000000008000000000000000000000000000010040020410000000040000001000000000400000000000400000000004920400e000005248000000000800000000004000000000000000000000000000001208000000000549204000004001040100000000000000000000000000100000000409000000000000000000080000248214000000000000000000000002400002000000080400000000004000c64040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000002000000000000081100000000000208000000010108001000000c002000000400000000000000000000000000000000000000000000000000000002100492000000004010400000008000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300800082411000020012000580000000400a800000000000000000000000000000000000000d89600000000000000000000001240000000100041200000000000000000000000000300000000000000000000000000000400264040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000008000020000000010400004000022000000000000000000000010000000000000000100000000001190000000000040000000000000000000000000000000000000000120100000000000000000000000030100000000000800200001000000000000000000000000000000010100200040400000080000040000000400000000000200000000010100200000000401248000000010110000000000c00000000000000010000000000401000001010010341000040000401000000000000000000000000400000000000010100000000000000000000000010100000000000002200000000a64040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000008400002000000000000008000000410400000000800040002480010000002000100000000000004000000014000000000010060010000600000000000000000060000000000000400000000000000000000000000200000000000000000000000000002000080000000000e2000000c00000060000000000010008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000206000000000000000000000000082000000000000000000000000000000000000000698600000000008000000000004000000820000100000000000000000000000000664040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0400000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000208000000008200000000080002000000000000000000000104000000000000000000000080020000000000000000000000000000000000000000000000000000000040000000000080008000000000000010000000000000000000000000000000000000000200000000000800200000400000001000008000910080000200004043000000000101040000000000800010040000400800000000000000000000000000200000000010000000000000000000000000010400000000000000000000000000000000000008000000000000000e64040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000200400000000000000c000000000000000000004004014000000000104008000000000002400000000800010000080004100002000100000000140000000000000000000002000000000000000002000000000002000000000001000000000000000000000082000000000000000100000000000000002000080020000000080000020040000000000081000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0200080000000808800000000000000000000000000000000000000d10600100000000000000000000000164040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000008b6200000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000100000000000000000002000000002000000000000000000000800800000000000000000000000000000000000000080080000208400130000000000000400000000410000000000000000000000000a0000000000000008000000008000000000000002000000000000000000000000000000200080004008000200000000012011000000002001000100004002141000000014001440000004100000000000000000000000002000008000000000000200000000000008000000008000000000000004000000000000000000964040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000400000000000000410800000000000000000000000000000000000000000000000000000000020000400000000000000000801041040020000200100000840000400000000000000000000008001041040420000000040400000400200000000021000000000000000000000110000000000000800020000000000400800041008422000000000000000200000000000004000000c80000000000004000010000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000080400000000202011002000008000000000000000000000000564040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00040000000010000000000000000000000000000000d63b0000000000000000000012000000080000480000200008000000000000000024804000000000000000000000000000000000000000000000000000000000000000000000000080102101000000000000000000000000000000000000000000080000410082400004000000810000000010400000000000000000010000004000000000000000000000004004210000000000008000000000200100010000000008000020000005000000000400008008004000002012000000000008000000404c04010400004c10002090030000004412000000000000010000000000200000000000008004000000d64040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000000020000000000010800010800000400000000000010001000000020020000000100010000000000000500000000000000000001400400600000000010404001001000000200000000002004104004020000120120000000004808800000800440000020000214000000000000000041000000000100000000800020000000000001000040008200541001000000011048000000000000000400000208000082000008004000000000000100000000000000001800000004001040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200020200008409000080000080000000000400364040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000004009000140080000201040000000000000000800000000000000000000000000000000000c74d001000000000000000000000040000000120000408000200400000000008000000040000000000000000000000001040000000000000080000010010400000000410000000000010020100000800000000000028002000000000000480000000000041008000000200400100800000000000000000000000000000000000000000200000000000000000008400000000000000000000010000060001000000000000004000400500000000000000200001001000020004000060005a001000010004100208000004102000000000014002000200002100b64040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08012d100020300200200000120002000000040000000000006000000000000040802060800020820000020000000820000001002000000000000000840820060001001000000000000000800001001021800000000000000000000000000000000000000000002000000000000000000080800924984000000812004800000800008000000000000000000000000000000001000000000000000000000000000020800024100200a610200000000000000000104000000000008020000100000000000000010000000801400000008001040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000764040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000100000110002000420000000400820020000000000800000000000000000000000000000000000000090b0000000000000010000002000008080000290000000000004000000000000043402400000000000000000000000000400000000000000000000000000000000000000000000000000200000000000000000820002020000000000004000000208000220008000000030000004000000000000000020000000000290000050200002000200000000000040114501000001001010000000200400100000000000011000024000000004100000000000040000000000000001000200000000000482c02012000f64040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800001400010080400000020800800900000c00000000000000004000000000000100000000000000000000000000200020000820008820800000800208020b00000000000000000010200030020811002400400000000000000020000400400c2000000008000000000000000000000000008000000001040010000040000008040002082000000002100002028002000000000000100000000000000000000400000000000000000000000000000a000820000800000010c00000000000000000010000000000000008000004000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000400400000000a20a2000700700018800020000000000000000000000000000000000000000c6fb000000000000004000000000000400000004000800000000000000000000000080000000000000000000000000000000000000a00000040008020000008000000000000000000020000000000800000000104020000000000000000040400208200088004200000000800000000000000000000002000000000002000000040000000022000000000002048040080000080000000000000000000000000000000100001000000a012c000000000a00400000008e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010028000800200100800000000001030000000000200880000000028028000500a0008000002000000503800010004014440000040100000000000000000000000000000500500004080000000002000000000000000000000000000800200001000094084000000000000001200500020014000000000000001402400000000030088008040000800000000000000000000000000201500014014008080002000000000000000100000000000000000000000000100000000000000000500000020210014000000800000000000000000000000000000000100000000000180040000030000000000000000000000000000000000000000000000000004e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100825000000041105b4000000020014c800100000000000000000000000000000000000008de5000000000000000000000000018000000004002600000000000140000000004000000000000040080000000002000000000000180000007014000002000100940000000002012000000000000000000000000000000000000000000000000002002800800080100000000002000000000000000000000000000005404000020020200010001002004000a000044055000000000000000000000000000000000000ce4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (410000000000a00000000000000000000000000000000000000280000440125000000024004b4000000080002d0000000000020000000000000000000010000040000000000000000000000000000000000000000000080020000000008000c008000000800400000000000000000000000000200002000000020000000000000000200000000040000000000000000100094000000004022d000400020005b4000000010002c00000002000000000000008020000000000000000000000000000008000000000000000000000000000000000000000080204000000000000100000000000000000000000000000000210000000000000002010001000000000002e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000004080010020000810000000040000000000000000000000000000000000001b8500000000000000000000000002000000000100080000000000000000000000000500000000000008000000000000000000000004010002801094000000020022d000000008008b000000000000000000000000000000000000000008000000010020005008000000000000020000000000000000000000000000040040000202a00000000000000040008804042800ae4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400002002000000000000800400080000400010000000140000000000000000000000000000000000000000040440000000000000008000000000000100080000000000002000080080000000000000000000000000028002000000a0000000000000000000000001000000000000000000008000000000000000000000000000000000000000400000000000000000000000002202000000000000000000000000000000000002840500014040000102000000000000010000000000000000000020008000000000000000000000000000000000004000000000100400000000010008000000000000000000000001000000000000000000000000000000000006e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (002000200000000000000000000000000000042208000200000100400000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100041021021514461850848844420121221061000000000000000000000000000000000004bc8000000000000000000000000000000000000146000000000000000000000002000000000000000000000000000000000000000000000000000000000000480000000000004000000000000000000000000000000000020000000000200a000000080200001400000000000000000000000000000000000000000040000ee4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000000000000000000000000000000008008000801000800400010080000c01480210808000400004020000000000000000000000000000000201200090090044024102102102200284084084084022102102101201400104030000040001000400200400048028808200011000200000000000000008040001000401201200050030008040002000400000000000000000000002000000100000050050000000000000000001200088028000000000000000101404084085050222102102102201484084084028026102102100800200048028000080000800200000000402100000000010010000000002202100000000084008000201002180010008020001e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2000000000080800002018000800080080000000002000000000000000000000000000000000000000000401802020200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002001610200214024aa8608408400100804210200000000000000000000000000000000000063c200000000000000000000004480000000002206000000000090084000000002202100000000090080000000002002400000000000084002000106084084084086102102102000084084084000000000000000000000100900000000040044000800801031120004020000009e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000004084001c000021800a000000000000000000000000000000000000000000008008000001000000400000000000000480208008000000004000000000000000000000000000000000201200080000000006102002100000a840840840800221021021012010004040900100600028000002000000600080080000010002000000000000000180400000000012012000440a00080400020000000000000000000000000000000002010800a008800000000000000280220000804800000000000000190098408008500020a10210210010228408408400002a002102002800a00028008000000002000200000000200000000000088084000000000102005e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000004000000000000000000000020000002000000400000000000000000000000000000000000000040200002000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000050000000000000000000000000000000000000000000000007360000000000000000000009008100000000200604000000008008000000000200200000000009808000000000000200000000008808800010018408018404000a10210210000048008408400000000000000000000110210000de4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000002000100800000000000000800000000000000000000000000000000000100000000008000000040000012002284100800002000000000000000000000000000000000000004004000000000800000000000000001000000000000100000000004000000a0000004080000000001000000084010000000001000400000000000000004040000000101001000010000000040000000100000000000000000000000000000000000000000000000000000000000800008000000000000000002000000000000000004000000000400800000000080000000000000000000000080000000000800200003e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000c00c00400000080000000000000000200000000300c00000000004008000000000800800000000024008000000000c0000000004000000040000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00c10800000830830000000000c00c000000000000000000000000000000000004e440000000000000000000000020000000000000000000000001400000000000000000000000000000000000000010040000000000000000000200000000000000000000000200000be4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000000000830430000000000c00c00100100030030000000000000000000002400c0000000000001000000002000540000002000000000000000000000000000000000000000004000800000000000000000000a00000100000000200000000000000000000000000000000000000900100000010000020000c00c00000000030030000000000c00c00100000000000000000000000400000000000040000020011000000000000000000000040000000001001000020000000040000000000000000000000000000000000000100800000008000000000000000000000088000000000000000000000000030030000010000c00c00000000030030020004007e4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08405004000a142100800000084084040000002102000302800020020008020000000000000000000200000000080080000000000002000000000000088000000000000400000020001000000000000000000000000000000000000008200200000000c00000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b00240020021110000a0284a8444000000210a0000000000000000000000000000000000003e9b00000000000000000000004224000000000800800000000020020000000000800800000000020024000000000c0080000000000000fe4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000080090000000000402300000000080084000801100080184010040002102101400400084084000000000000000000000100100000000044004000402c0010801000000000000000000000000000000000000000000040040012a00201000400008040041409440040821000400000020000000000000000000000000000003000000010030050044002002100a010000840840140500021021000004000400100080000000004008010000100c08004c001404000000000000000000000000080040000000000001000000000000040000000000000000000000280030000004001000000000000000000020000002008000000000000000000110008000014040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00282000000400000000000000000521909452000054864251480000521909452000014864251480000282000000400000080000010c18000000000030600000000000c18000000000030600000000000c18002000000400000080000010000000000000000000000000000000000020000004000000800000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000148642514800005219094520000148642514800000000000000000000000000000000000d11c0000000000000000000009049000000000240220000000009009000000000220240000814040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000000030600000000000c18000000000030600000000000c18000000000030600000000000c00521909452000014864251480000521909452000000000000000c18000000000030600000000000c1828200000040000008000000000000000000000000000000000000101000000000000000000000000001282000000400040000000000000000000000000000000000000000282000000400014864251480000521909452000014864251480000282000000400000080000010000282000000400000080000010000000000000000000080000010000282000000400000080000010000000000000000000080000010000282000000400000000000000000414040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00044210000188422780000000000000000000011409512c000000000000000004c0ddd3647cffd383774d9100004e0ddd36440001383774d910000011409512c000000002544b5555000000000155540000000005555000000000155540000000005555000005511c00000000154470000000000000000000000000000000000000020ee0000000004fdb8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001303774d9100004e4ddd36440001393774d91000000000000000000000000000000000003584000000000000003060a000000000c18200c14040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4b2700000000000001555462108000055551884200001555400000000055550000000001555400000000055550000000001555400000000000004c0ddd36440001383774d9100004e0ddd36440000000000000555500400000015554000000000555504220000000000000010000000000000000000000000000000000000000000000001000000000000000682200020000000000000000000000000000000000000000000000289ce370840001303774d9100004e0ddd36440001383774d91ff00289ce37084000000000dc2100000414c3bfcd5c0800003eead0000000000000000000000080a000004a8162028000000000080a00000000000000000000000214040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (12c000000002444b000000000000000000000004421000018843d7000000000000000000006a01c2020000000000000000000480e3dc63b8fbd2638f718e0000498e3dc63800012638f718e00006a01c2020000000000080806a6a0000000001a9a80000000006a6a0000000001a9a80000000006a6a0000037084000000000dc210000000000000000000000000000000000040195ee000000000555df0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012038f718e1d1d49ce3dc63800012738f718e0000000000000000000000000000000000000a14040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (200000000000000000000000000000000000fe3c00000000000001a9a86210800006a6a1884200001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000000000480e3dc63800012638f718e0000498e3dc63800000000000006a6a0040000001a9a80000000006a6a00000004400000000000800000000000000000000000000000000131004000000200000000000000131000009100404c40000000000000000000000000000000000000000391485511c00012038f718e0000498e3dc63800012638f718e0000391485511c000000001544700000414fd557d56a8000077fff00000000000000000000002444b0000110409100614040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000008828000000c92220a00000000008828000000000000000000000008422000000c52230000000000000000000010510440300000000000000000064308031c8000198c200c72000066308031c8000198c200c7200001051044030000000001100c006a0000000001a9a80000000006a6a0000000001a9a80000000006a6a00000413b800000000104ee000000000000000000000000000003f00000000a06800000000128b400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000190c600e721d1d66308839c8100198c200c700e14040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (180cc83264000061b221c990020186c88306400000000000000000000000000000000000bef50000000000000001a80314800006a6a00c5200001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000006a6a64308031c8000198c200c72000066308031c80000000000000006a0000000001a9a80000000006a6a4001000020000000000000000000000000000000000000000000013100000100000000000000000000000800102a00000000004000000000000000000000000000000000022c9a622b0000190c200c72000066308031c8000198c200c72000022c9a622b000000000188ac00004c6f22a2a0000000006befa0000114040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00105ef00004c2b3455fc000000005d77f00000000000000000000000150b0000101540542c000000000150b00000000000000000000000842b000000857430640000000000000000002896026a400000000000000000603220c190000186c883064000061b220c190000186c883064000002896026a40000000000ba9c05500000000015554000000000555500000000015554000000000555500000626b400000000189ad000000000000000000000000000003f00000004406c00000000520de0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000914040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000040000000000000000000000041440000000000008000000000000200000000000000000000000000000000000000000338b0000000000000301540215800005555008560000155540000000005555000000000155540000000005555000000000155540000000005555603220c190000186c883064000061b220c1900000000000000c055000000000155540000000005555000102000400000000000010000000000000000000000000000000000001000800000000000000000000001440c240000000000200000000000000000000000000000000013856417bc000180c883064000061b220c190000186c883064000013856417bc00000000514040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000006000000000000800080000000002040000000042000000000004016400300000000080010000000016000000400000800000000000000000000000000000000000000002000000000000080000000000000400000000000090000000000002000040000000080000000090082000000000000080001802001416000000000000440000000000002000000000020080000000000000000000000000000000080002002000000000000280000000000000400000000000020100000000000004000000000000000000800000020000000000000000000000000000000000000000000000000000000000000000000800000000000000000800000000000d14040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000040000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000001004000000000000000000000000000000000000000cb9d00000000100000000000204000000000000000000004000000001000000000000048000000000001001000008000001000000200000000080008000000000000600008000000008200010000000000000000000000200000000000a000000000000000000000000016000000000000080004000000002400000000000005000000000000002000000000000000000000000144000000000005000000000000000000000000800810000000000060800800000000800000314040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000400000003000011000000000000404000000008811000000000000200020000000010000184000000008000000000010000000000000400000000000010000000000000100000000000000000000000000000000000000010000000000000400000000000000000000020020400000020000011000000300000400000030000c11000000300000404000000000110000000000000000000200000010000000100000400000000000000000000000000000000000000010000004000000440000000000000000000000060020000000000000000000000000000030000000040100001000000000000000000000000000000000000000000000000000000000b14040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000004000000000000000000000040000000000000000000000080040000000000000000000000000010000000000000000000000000000000000000000c179000000000000000000010000000000000000000000000000001000000000000000000000000000000000000400020000000010000000000000400000000000011000000000000400000000000000000000000000000000000000011000000000000000000000000210000100000000400000000000010000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000714040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000000000000000000000000000000100000000000000000040080000000002000000010800000000000000000120000000000000002000004020000000004000400300000000000010000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000800000020020010000020000004000000900000000000000108104000000300000004000001000900000000000000000000200000000000000080000000000000000000000000000000000000080002000000002000000000000000000000400000000000000100000000000004000000000000000001000020000000800000000000000000000f14040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008000010082000402000000000001000000000000000000000000020000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000082080004000002002000000000000000000000000000000000000005a09000000000000000000000000000000000000000000000000002010000000000000480000000000010020000000020020000000000000000000000000000000000000080000000001000040000000000000000000002000000000000000000000000000000000000200000100000000000001000000000800000000000000010000000000008000000000000000000000000000094040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000080000400800000020000000000000004000404000000000020810020010000020000020800000810020808008020000200100000000000000008420000000000420000000000000020000004008000a100000000000200000000000040000000000100000000004000200000001000000200000000000009000100000000004000000000008000000000200600000080008208000000100000600000000000008000180000430200004c4010040100000000000020008000000020800000000010000000000000000080000000000020008220a0000290480100000000000000000000000000200000000000000040000000000894040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000020000000000000000000000000c80c0000810000020400000000000100000000000000000000000202000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000410000100000000400000000000000000000000000000000000000cb6f00000000000000000000200000000000000000000000000000000000000000000000000100000000000000008200000000004288000000000008000000000004200000000000008000000000000000000000000002000000000080a800000000000000000000000902000004000000080000000000802000012000000040000000494040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000c00000000080000000000000000000006000000023000000002000000000000080030000000100000c0000000000000400100002200000410000000000410020022200000800000020000000000030008000000000000000000000000200000000000000900000000000200000000000000000000000100000000000000000000000200200000000000000000000100000000010000000000000000000000002000008080010000000000000002000000000000000000000000030200000c004c0004000000000000000020000001000000000000000000000000000000000000000000000020c108030808330000000000006000000c94040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (050090400000000000000800000000000000000000000000000000000000000202000000009000000000500c90000000000000000000000000000000000000200000000000000004000000004000400000000000000000000000000000000000000000000000000000000000800000000000000000004000000000500804000000000000000000000000000000000000343b000000002000000080000080000000000000000000080000000000000000000000000004000000000000000000000000000000000000000400000000000000022000000000000000000000000000000000000030008000000000220200000000000000000000000302000004000000294040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000080000000102d021a0000000014002000000040500010000001202a000000000000000002000002000000040008c00a800110200000000000800040000040000000000214002400000000500080000000014204000000000500800001000000000000000000500090000000200004100000002d00010040040014000800000000500020000000000000000000000000000008000200000001200200500800000000015020000000000000100000000014000100002200500100000000214082000200000500804000800014000400080002d008280400002a10000000000005001000000002000000000002000000000000000010000000000000a94040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000000000000000000000000000000000000000000000026400000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000002000000000000000000000000000000000000000000000240000008000008204004000100000000000000000000000002000000000000000000000004235000000000000000080005001000000000000000000000000004000000000000000000000000004000000000142000000000085480240000000140001000000085004040000000140048000000000000000000000000020000000000000694040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000800000000000000000000000050000104000044110000080801100000000000000010000000000000040000800000200000008400010200000800000020002020000008020020000000000010000000000000018000000024000040400000048001000000023110400000000200400000000000000000000001220000000000000000000200000200000000000000001004010000808000100000010a10400010000a28400000000000000002000002000412400000110510002000000208000000000000010000000001408000000000004500040000000008400000400440000006d000002084000000000201000000000050000000000000800e94040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000008180204000010000000000080030100000000000800000000000020000000000010800000000080d82100000000000000000000000008000000000000000000000000000000000000000120800000000000000000000000000000000000000000000000000000000000000000020000040000000000000000000000000000000000000000000000000000100201800000000010900003830000023960080000000000000000000000000000000000009d80000000000000000410000100001014000000a0000000000100000040000000010000000000000080000000000242000000000010000010004000202100040000010480000004000302000194040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080c020000000000124000000000804b000000000000000000000000000000000100400804a02000000004018092008001040000080000000000000000080808000006440400000000000000008004000000000000000000000000040020000400000000000000002000000000080c820000000000004000020000804100000000000120000008040008000000000000120800000000000000000020000020820000000000100000000100004000008000060201000000000000040000000000000000000000100000000000804e0000800000000800041000080198100000100010000000000080600040000000010000000000000402000000000012484000994040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000010000c3000000001000240000000040000000002100004020000000000000000800001000000000000000000000000000000000000000000000000800001000010000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000010000400000400000000000000000000000000000000000000000000020000000800000820104000080000000120012400000000000400000000000000000000000cb3b000000000000000000000010000000001000000100040000020000000001000000080000000000000000000084582000000000010400000000594040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010820000000820000000000000000000080000800000000000000001000000000800040000000000001000000000000000001041012128600082010003200001100000000000000000000000000000000100000020800040200000010400001190200820000022100020000010050080000040012100000000000000009000008000000020400000010000808008000000001100000000000000400080000000000000020000000000040000000000000000000000000000000800001000810000000000088c080000000009304000000000000000008000000000004002080002000104000004100080000080004100001080004100008000080002080200000d94040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000080020400020000000c00000800010020001040200010840001000920120000010000024000020800080020800020000000400000000000000022000000000000080000000020002000088000400000000000000000000000000000020000000000000000000800000000000000000200000000000000000000000000000000000000000008000000000000008000000002040040020000000000000000000000000000000000000000000000000000010000000000000000200010408000000200c00000000000000000000000000000000000000ca6b000000000000000000000000000000204000044080000100001300000004000008000000000000394040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000001108001000000000010000000000000400000000c00000000000020001000000000c02000021010020000000000010c00000800000000000000000000000080000240000080000080000048a200020801208080200030009400288000000280000200800000c000000000000000828000000000000480200000100812800000008001010800000800000001000020c00001020010020000000000000c00000010080020000000008000008020000000020000000000000001040020000120000000000000800000411000a20000000042000020111010001000000000000000000000000100020100041140040c20000424100000044040040000c1000b94040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000050000920011000000000010000000020060000000000820010000000004920400011000000004202000004001404000000000000000010000000400000000020010000000004100000000000010000000000000000000000000120800008000004900000000000000000200000000000300000000000000000000000020000000000001248000000000000000000000000000000000000004000000300000000000000009008090000000000000000000000000000000000000000000000000000000000001000000000000000000100000000000108400000000000000000000000000000000000e65b00000000000000010408200000110c000000210000794040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000040002081000000000004000000100000a0000000000000010000000000000400000000008200000000000200000000000000200100100000208000000000009204000000000000000000000000000012410000228400200400002006000200001200100000002141044000300000000002402080000000000000000001100000000000020000480000040800010000000140000000080000000008002000492041001000012480000100000492000008000010400000000000001000000000010400000000000200002400000000004000000000002081000000000080000000001001000000000000000000000000000000008000000000000f94040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000200000000000000000000400000000100010100000000400000000000000010100008000400400000000800010100000000000400000040410010040000000000c0000000000002000000000100040000000000000010000000000000000000000000000000000000040100000100000010000000000000000000000000000000000000000000000000000000000000000000401208000000000000000000000000000000000000000000000000000000000000010008000040000000000000000000000000000000000000000000000000003000000800000000000000b00000000000406010000000000000000000000000000000000000ba43000000054040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000cb6100000000000000000000400008001000000040000000000000010000000000000100000000000008000000010100200000000400200000000210100008000000400200000000010100200000000000000000000000000000000000026010000100000010009000000c0000000000801004000000000040000000020000120000000000000000080000000000004800000000800000000000100000600000000000400000000010110200000000401208000400010140008002400401040200000000020000000000401000000000000000000040000c000000000000100002000000044000080000000000200000000000854040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000800000000000040000200000010080002088000000000000000000000000000000004000800000000008000000000800000000000000000004000000000000000000000000000000000002000000000100008000000210820808000000000000000000800040040000004000000000008000000000000000000000000000000000000000000000000002000000000000000000060000200000000000000200000000000000000000000000000050060000000001a000000000000000000000000000000000000020000000000000000000000000000000000000000000000000001000001000000000000000000000000000000000000208000000000000454040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000400001000400000000050000000000000000000000000000000000000000082f2006000000000000000000000000000500000000000000000200020000200004a0020000000000021000000000800001000000000000000040000000000028030020800800000000000004020000000000000200000000000080000282000000000800120000000000020000100000000000000000000000000000000000402000000080000000004000080000000000000000000060002104401010000080000400000000000160000010008400010000002400002000402800000000000000002000000018000000000600000010000000000000000000000800000041100c54040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000002000020000000000000000208001100000000000000420010000000010020000000000000000000004000020100000004800800000000000000000000008000000000000040000000000808000000000000100000030000004000001002002100000000000000000400000800100020000092008000040100080000000000000001000000000000000080000000010000000000000000000000000000008000000000000000000000000008000000000001000200000000000000000000000204000000020000000000000000000000000000040020000000000000000000000000000000000000000000000000010000000000000000000254040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000400000000000010000000000400400000208400040200208210001410000000000020000000000000000000000000002e4b00000000000000000000100080000000000840410000080000000000000002800804000000004100000000014000000000000100000000000014000000008000100000001000014000000000000000000000200000000000000000000000000200000000020002000000000800000000000100000000100000000000000a020018000800000022000004b0000a008000000200200000020000020100000820004000000000000000100000000010100000020001400004000000000008000000000002008000000010000a0000a54040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002008804004000285008000850002004000000000820000001000000080000000001004000400002024000000400000a48008000800028848000000000000000000000000020000000000800800000200000000020020004001030000820000000000002004004202020020000110825091000100800000400000000800080800000100000c20000020400204204400200000000040000000000002000000000000000020800000004401200000000080040000000000024800000000000000000000000020000200004000400900000000020040000000000800000000000000020000000000000000000000000000000000000800000000000000000000000654040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (6000000000040020001000000000000200000008000000000000100100100000002000000008020000028020000800100000000000000000000000000000000000000000bb2f00000000000000000800000020800010001040a28000000080001000020001221020000000022020020420805000c00000000082082000800004a00a20080884082022012400404c10a1008000000000800001010002000000000002000000010200002004000001002000080001000000020000000400001010080000000000800081000000140400082000240002000000000020000010400400000000100008000000020004002000001400000024430810804810c100000200e54040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000010000010800000100000480a00000000010011000000000040081000000810000000800000082000020000a108000000000004000000000000130000000000002810200000000008000000000000100000000000108000000100104200000000480008000000000004200a10000000100000000000004000400a2000010000020000000440020400000a104000000020880200000000000100100000000000400400100000008000000000001000000000040100060800000000040e00000000000028000000000005200000026000000800000800000000200000001000000400000029682400000000010000000000001008000000000800000000000000154040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000800000000800000000000000400000010000000000002000000040200000000000000000000002200280040208000000000008200000000000000000008000000000000000000000000005d75000000000000000000001000a0800000000000860000000000001800000000240004000000020000000000004000000000000100000000000004200000000000108002100000004000404000000000010004010400220000000000049000000000000040000002002100000000000004000400200010100100400640000000009800008000000000000800020000008000000000a90800000201000800000000180020000000060000954040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0080001000080000000004002004020100000000900520004030431934800510c144000200009008100104000100000008340008840040008000000002008040040010000041008000000000000400040001040000001000002000080100000000000000000001000000000042222102040010000000040000300241001001200008a0000082000001000010000200024000410900a10800000a04000404004000810410000101000000420000010400000000000000000000024000000000000000000002044000000082002000500000000000040000002000400000010000012000000400000004000000000024000200900400000022400400000000010000554040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (080000c0200000c0000004100000000000000000001000100000000000002800000020000000800000000000000000000000000000000000000000000000000100000000401008008000000000000000000000000000000000000000000000000000000000000000ec5200000000000000000904000004000022000000000000000000000000000000000000000000000800824420800000c00800100020820800820000c00c20000804000020110400400c10810000000000000004000000000000000000428000004000000000000000210000000000092000000000000000000010002040080402000000200000000000000000024000000011010000800800d54040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000002800080800020040000a000008000000400008000000000000000000100004000000000004000000000004130004060100200002000400000000000000400000000000310000000000000000000001000008400104002000000000000200100002080000000002002000000200000000001000000004102040004b2801000010001000000000000000010408000000000040200020800001008000000000010000000000200000000000001020000000c000000000008000000000001000000410000000000000400000400000000020000000008102000000208010004801000000000400040020004000011500000000001400c0000800000000a00000354040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004008000200000000000000000000000000000000000000000000000000000000000000000000000000000600100000200100002008000000000000000000000000000000000000fc4000000000000000004100000100000010000000800000200000000000000009000000000000104000100000000000000004000000000000000001000000000100040020000000000000000000000000000000000001000000200000000a0008000000280000000402200000400040804000400100000000100000800100004000000000000b54040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08000000000800300f40a00000007000440000000000003004000000000280280000000030000028005000000000080000000028000042000000a00010080010010000840000000e0002000000000000000000000040001000000000000000000014180002880000000000080000000000000080002800000800800090000080000000000000000000000000010000600201000214000000000010000002200c000140140080200008040001002000a00000080400000005042008010a0408008200000040000104000100000008220000800500800200000000000000000000000000000000000000000000000002800000000000000000000000000000000000754040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000005000040800000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000080040000000000800000000220000000000000000000000000000000000001e6000000000000000000000020000024000000000000200840000000020002000000000200000000000000000000000a00140000000000012010000200040080000000040005000004040000000000080040000000000002000000180000000030004000000030000200008005000020000a0000f54040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (008b40000000284008000000004010000000000100200020000000000000150100000808a500000000a001b400000008000ed000000008400b0000000000000004000000000500400110000000000000501001000008004000001000000100000000000000000040000000500000000000002000400000000000000000000000000000080000000400094000000000012c200000000000000000000000000040001028000000001400000200040042000000000401000080000040100000002800000000080000000000002000010010088084000000000000000000800000082000000000000002000000a00000000000000000000000000000000000028001000d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000800000200001000000000000000000000000000000000000000ebb00000000000000000000000800000900c94000000014022d00000000900db4000000000000c000000000000000000000000000000000002015000800080080a00100002000000000004000000000100000000000001004000280025000000003008d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0401000000000040000000002000000000080000000000000810400002000020000000000000008000000000000000001001000000020000000002001000000002800000000000000440c000000000000000100080000000001400080000000188000010010004201800000000000000000000000000000140400020000000000000000008000000040000000000000200180000000000006001000000020000200280000000000000000000000000000008000001018000004980000000008000008010000800600080800000000008022000000480080800020000002020015011080082000020000004100000020000080800000000000002000000000000004d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400088000800020202020000000080200000000000000000000000000000080200008002010002000100200000000000000000000000000000000000000000000000000000000000000000200020000000000000000000000000000000000000000000000000000000010100002001000000000000000000000000000000000000000000000000000000000000000000000200040000404008803000100240000000000000000000000000000000000030d4000000000000000000000000000000000000000000000100000000000000000000000100080000000000000000000000000a0002000400201000004080008000002000002800500080118000000000cd4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (3000002000888440220110013243000000008008800000000020000008802018211210040118408408404822200208220040100008000001002000200000008048000c00800008048102102100800a8408408604048210a182110420a86084284000000000084000c01100152030008040090080400200200130428008000080804200000000000000010000000000400000000000002004120001000400200800080010008040005024402401406186184024026186106100000000000000000000004884001000002026444000080084890400802400426128000080012008200a0100004813000000000080024802a000420a008000400008002001050000002d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4400800008000100000000000020010000028001000000000000020000000000804000000000000000000000000000001800000100020100020000002000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000080000010000000000000000000000000000000000000000000000000000000000000000000000000100000020000000000c02000000000000000000000000000000000000be4100000000000000000000002000402101104084084028032102102102402084084084088012102102100000000048088008080000800400000200090000ad4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000280080080800000000000002000800000000000080802022011022220000000000080000000000000020000000061020061021000840840848081000001022000020000800000000000000000000804800000000002400610200210120008408408600004a10a18210100028208428400000000408000000110210614000804000000020020020028210801004000201420000000000000000000000000020000000000000000420000904040060000008000001804008400400000098418018400000a0821060000000000000000000000000802014000022060000000000800900020000000081080000000100002000000400880100000200000002006d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000020240000000800000000000080002001000000000200008000080020000280002000080000000000000200000000800000000000000000000000000000000404000000000000000001000000000000000000000000000000000000000000000000000000000000000080000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200004000040000000000000000000000000000000000000000000000a4f500000000000000000000002000000000184080084004006102102102400284084084000010002102000000ed4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000020000000000000000000000000000000900100000000008000008000000100000000000008000000008000100a0000000000000000000000000000004040000010000000100000000000000000000000000000000004000000000000000000100000000000000000000000000008000000000142000100200081002000000000000000000000004000000304200100000000100004004000000000000000008004000000000000000000000000000000000000000000000000000001001010000000000040400000200000000000000000000000000000000000000000000000800000000000000004200000000000000000000000004000000000001d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80800000000020020000400000000c0000000000200020000080000842000000000000008804400000000000002000002020000000000000400000000204000000000000800000000000000000000000000000000004000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000ad09000000000000000000000000002000000000000000800000009d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000200000000030030000000000c00c00000000030030080000000c00c00000000004004000000000000002000000000020000000000030000002000000800000000020020000000000000000000000020c00c0000200003003000000000200080000000000000800000000000020000004000000000080000000c00c00000000030030000280004c80c08000000030030000000000030000900000000800004000022024000100100100230004000820000000000000000000000000000800000000000000000000020000000000001000000000000040012810000000402430430000000010c10c000000000000000000000000300000000008005d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000020012894000200802142450000000090090000300b00320020008020010808000a00a000000300080200008000002a0800c00a080082400008000c000900000080800802000080000080020000000000000000000000000000000000000002000000000000000001002000000000000000000000000000000000000000000000000000000000010000001000400000000000000000000000000000000000000000000000000000000502840040010000000000000000000000000000000000000000000000000000000000000000000000800000010040040014000400000000000000000000000000000000000000cc2c00000000000000dd4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000d09100000000000000000000000000400c029000800840200400021021002008000840840400100021020000000000400200000000008005012010000100300080200050901000000021322500000000000100000000002023000b0044002006100000a000840848000b000090200020000000001000002000080040040000010c00a00020024002002100001400084084030400002102110420010084084000000000090002c00002022090000000010810001001000012020010000000004000000000000000010040000800000000000000000800020000000400000800000010000000005024400c031009809840200000021060003d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0080000010c18521909452030614864251480000000000000030600080000010c18282000000430600080000000c18282000000430600080000010c002820000004000000800000100010020000004000000800000100000020000004000000800000100002800000000000000000000000000000000000000000800000100002800000000000000000000000000000000000000000000000000000000000000000000008000001000000000000000000000000000000000000000000000000000000000000200000040000000000000000000000000000000000000000000000000000000000000000000000028000000000000a0800000000000000000000000bd4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (22000000000000020880000000000000000000000000000000000000ef8d0000000000000000000080000010000521909452000014864251480000521909452000014864251480000282000000400000080000010000282000000430600080000010c18282000000430600000000000c180000000000300148642514800005219094520000148e400001000000200000040000008000001000101000000000000014864251480000521909452000054864251480100521909452030600000000000c18282000000430600080000010c1828200000043000008000001000000000000000000008000001000000000000000000008000001000000200000043060007d4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000c00000002f5560000000002028155540000080a055554c0ddd36455555383774d9100000000000003aba8000004401eaea399cec0003aba80000108005555012209512d555400002544b00000114015000000000002544b0100000009512ca03000002544bf0000000008000200000002544b0000011400000000000000000000000000000000000000000154470000391480000000000000000000000000000000000000000000000000000000000000000000000453000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fd4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000204015400000000000000000000000000000000000008ea500000000000000000000000442100004c0ddd36440001383774d9100004e0ddd36440001383774d9100001884211084000000000dc210000289ce37085555400000dc215555289ce370855554000000000555500000000000001303774d9100004e0ddd3644040d38370808000000000008004000000001897300000000000000000001303774d9100004e0ddd36440001383774d9100004e0ddd364555540000000005555289ce37085555400000dc215555289ce37084000000006542100000000000000000000000dc2100000000000034040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000001544700000000000000c0ec0000656420000000009112da9a801002444b6a6a480e3dc639a9a92638f718e0000000000000054540000044011515399ce0210854540000108006a6a6a00020201a9a800000808000006a01c11004000000000808000000000020200a030000008080f0010000000440200000000808000006a01c00000000000000000000000000000000000000000dc210000289ce0000000000000000000000000000000000000000000000000000000000000000000000455700000000000000000000000000000000000000000000000000000000000000000108000000000000000000000000000000000000000834040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000080100000000000004008000000000000000000000000000000000000097cd0000000000000000000000044210000480e3dc63800012638f718e0000498e3dc63800012638f718e0000188421108400000000154470000391485511da9a80000154476a6a391485511da9a80000000006a6a000000000000012038f718e0000498e3dc638040d2638a544b00000000000000000000001cd73000131004000000000012038f718e0000498e3dc63804c52638f718e000049ce3dc639a9a80000000006a6a391485511da9a80000154476a6a391485511c000000000804700434040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000188ac6a6a22c9a622b1a9a80000114ac0000000000000000000000188ac00000000000000000000003be58000000000220a001a80000088286a6a64308031c9a9a998c200c72000000000000000054000008420151533cda050005454000000000006a1000044031a9a800001100c6a6a1051000080000000001100c00800000044030000000001100c00000000000000000000001100c0000105100000000000000000000000000000000000000000104ee000013c520000000000000000000000000000000000000000000000000000000000000000000000842800000000000000000000000000000000000000000000000000000000000000000020000c34040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000008004000000000000000000000000000000000000000000000000000000000000000020000000001000000000002041000900000000000000000000000000000000000194200000000000000000000000842a000064308031c8000198c200c72000066308031c8000198c200c72000000c52210a800000000188ac000022c9a622b001a80000188ac6a6a22c9a622b1a9a80000000006a6a0000000001a9a990c600c72000066308031c8000198c2008a8000000000000200000000008cae0001310000010000000190c200c72000066308031c8000198c204c72013166308031c801a80000000006a6a22c9a622b1a9a800234040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0c1930154000000000555513856417bd55540000105ef555513856417bd55540000089ef0000000000000000000000105ef00000000000000000000005d7080000000000542f015400000150b5555603220c191555586c8830640000000000000303a8000008429eaea338de20027aba8000000000c05502814026a555540000009a95555028960002400000000009a9450000000026a40000000004ba90000000011080000000000009a90000028960000000000000000000000000000000000000000189ad00002289e0000000000000000000000000000000000000000000000000000000000000000000000854b00000000000000000000000000000000000a34040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2000000000800004000000000002000000000800000000000020004000000005000000000000140000000000000000000000000140000000000000000000000000000000000000008100000000000000000000000000000000000000000000000000000073b100000000000000000000000852b0000603220c190000186c883064000061b220c190000186c883064000000856214ac00000000105ef000013856417bf01540000105ef555513856417bd555400000000055550000000001555580cc83064000061b220c190000186c89130d000000001000840000000008da70000000000000800000180c883064000061b220c190000186c883264000061b2200634040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000110004010144000000000000020000000000000000000800000000000404000400000000000800000020000000000000000000100100000000004000000000000000800000010000000000000000000800000000000164000000000005000040000000000000000000000000000000100140020000000005800010400000140000000000000000000000000020000000000000820000000004004000000000000000000000000104004400000400000000800000000020000000000800000000000020000000000000800000800000000000000000001000000800000000000000000000108000000000000200008100000001010200000000200000e34040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000100002840000000000820000008100004060200004040000c00000000004001000084000000000000100004000000000001000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000002a20000000000010000000020000000000000000000000000020000000000000800000000000000000000000000000000000000000800000000000800000000000000000000000000000000000000000000000000000000000000000160000800000805000000000000140000004000005000000000000000000000000000050100100000041410000000134040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000004000000000000000000000000000000000000000000020000000000000010010800400000c00c00000000000000400000010000000000000000000000000000000000000000000001000004000000001000000000000000004000000000001100000000000000000000000000000000000000000000010000110000000010000004080000000000000000000400000000000000000100001000000004000000000000000000000000000000000000000000000000000080001000000002000000000000004000040000000500000000000004000000000000000000000000000400000000000000000000000000040000000000934040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000000000000000000000000000000000040200000000800000000020000000000800000200040000000000000008002000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000d756000000000000000000210000000000000000c000002000102302000000004000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000400000000000100000000000000000000000000000000000000000000000000000000534040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000400000000000000000000000000000000000000000000000000400000000000000200008000004000000000000000000000000000010010000400000000008000000000000401000010040000000000000000000200200000000004000000000800000000000001000000000000000000000000000000808000000000000000040000000000000000000000000010000010000040010000000100000000000000000000400000000000000000000000800000000010000000008008000000000000000000000000044008000000200001000800008000040000000000000020000001000000000000000000000400000000000000000000000d34040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000040080000001000000001000000000000020000000000000000000000010800440800000020001010000000000000000000020000080800000920000000008000000000000000800000000000020000000000000000000000000000000000000400020010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095d70000000000000000004000000000000000000000004000004004000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000001000000000000000000400001000000000334040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000120000000000002000000000000000000000000000000000000000000000000000000000000008000000240040000010000000004010010000010000040000000000000400000000000000004000000000000000000410008400000000218620210210000100008000000000000010000000000004000000000000810400010008800000000000200800000000004020000000000000000000000200000000000000000000000400010804000400000000800041000010000000000000000000040000500820000000000000800400010000400400800000000000000000022040001040000400080000000000000000000000000800100400008020000000b34040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000080000002000000000001000000000000000000000000000008800200000000000000000000000000000010000000000010000060000000200000000000000010000000400000000000000000000008000000000000008000000000000008000000000000200000000000000000000000000200000000000000200000000000000000000000020000000000000000000000000000000000000000000000000000000d65b0000000000000000000020000000000000000000000000020000000000000800000000000000000000000000010000000000000000000000000800000000000000000000000000000000000000000000000000734040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000008080000000000020000000000000800000000000020000000000000800000000000000000000000000008000000000100200000000400400000000000000200000000004000000000000000000000000000000000000000000000000000c100000004000000000000000000000004000000000000000000000002001000000000000000000000008000c000000002020000000000000800000000000c00000020000000000000000000020006400000000800000000010020000000000830000000000480000000000000000000000000001000000000000000300000000001800000000000000000000000000f34040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000342800000200000001000000000000000100000000014010408000000500024000000014000400200800000200000000000000400000000000100000000000140287000000005008800000000000002000000005000010000000010000000000400000000020080040000000000080000000000800800008000020020000100000080002802000000210020000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000003a2f00000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000140041000000000008000000000000000000000000000000008000000000000009805000200008000a0000002000082800000000000000000000000000000000000c08800a1000000080102800000040000000000000080002800000000000000000000000000040000000000000000000200040000000000041201201000001000040000000000000000000000000040000000000200008000000048000004000000000000000004002d001040000200a0000000001400000000200000000000008000a0a8400000000040a0000000000102800000000008000000200000008500000000000000008000200000008008000000000008b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4004000000221000000100100080000000000000000220000005004000002000000000000000000000000100000408000000000000000000000000311000004100000c00104000000010000001080000000000040040000901000000400020810000000000000000000000080001000000000000000000000000000000000000010000000000000500024000040000000800001000000000000000000008040001800000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000030f200000000000000000000500004000000000000000000000500100000000014000500000000000000000000000200004b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000400040000000000080000000000008000000000000000000000000000000000000100004000000000000000490000008000004000000200100000000010000004000000000000200840000100000100000004000202000000000000080000000000000000000000000080000000080000000000002000000000000000000000000000000000000000000000000400002000000000000000002000000001000000000000000200000000000800101000000020000000000000000000000000000000400000000000000040000080000100000104040000010004081000000000000000cb4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000006000000081046000000000000000000000000004000000000000000000000000000000000000000000001000000482000000000000400001000080c720000001000200040000000000000c0002000000000000000000004920000400000120000000000008000002010000000400000000808200000000000000000000000a000000004010222100000202000222000008000000000400004000000001002100800000002000000082000080000000080000000000042000000000000000000000000000000000000000000000000000019c00000000000000000000000000401010000000010000010000840400002b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000018000000201058000000000000200000000000000000000000000000000000000000000000000040000008000000000000000000000000000000000000000000000000000001002018040001200000000000045000000000040b78e400000000400000000000000114404000000000000000010000000000008000000010000000000000000000000000000000000000002000008000000000000000000000000000000000000000000000000000000000000000000000000000000800400000000000300000000000800060000000001000800004000000000000000000000000000000000000000100000000000000000800060000100ab4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000008010800000000000820000000000022000001000000000000100008420000000000000010000000000000400020000000400000010400000000000000000000000010000000800000000000000000000008104000000c0800008410048000003210000000800000000000400000000000000000000010000000000000000020000000800000000008010000000000000000010000004200000000008140112010020400024c08000010000024200000000000000000220008000000410000000000000000000000000000400000000000000000000000000000000000000000000000000000000193d00000000000000000000006b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000e83a000000000000000000000000000008100000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000008000000000000000010002000000000000000000000000000000000000100000048001008010400200000010000008000008000004000000001040000080000080000002000002000000000000080000000000000000000000000208000000080000000000002000000000000000000000000000000000000000000000000000002000000000800000802000000000400000000800000000000001000000081000040040000020000000000000000000eb4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02000004000000000000000000000000000000000000800100000000800014400000000000100000010000010000000800000020000040000000410080000000400400000000000000000100080100040020080000000000000000000040000010000800000000000020001020040000c00081000001000104001000000000010000010000099000008020208000008008004200000100000000080800000100200010010000004000000000000000000000a00000000000110800000280240802000281000000000008880000010000020000001000008800001040000020800080000000020000000000080800000000000000000000000000000000000000001b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000f7100000000000000000000200000400000000000004000000300000000000008000000000000000000000000000000000000000000000000000008000010000000000000000000000000000000000000000000004000000000000080210000400000040000002008021000000000010480000008000000000000000200000c0040002001001000400000000000080002000101000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000010000000000000004000400000000000810000000004000001000001200000009b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000800000020804000000040000000000000000000000000000000000000000000000820800001000000820000000000000000000000000000000000000000000010820000000000000000000000000030000020000000c0000000000000080000000000000000000000400000000000000002000000004482040000000000100000000000200000004000020000020800000000820000020000124800000000000000000000000000000000c0000512000000000000000101000084002042000000014981900404404104100010100020201000000000003008402000000000000100000000000000000000000000004000a0000005b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000acaa000000000000000000000002080000000000000000000000002080000000000082000000000000000000000000000000000000000000000000000082000100000000000000000000000000000000000000000044000000000082010000080006000000000000000000100004002001000000000000000000000020124800000000004020000000000000000000100004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000801000000db4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000100100000000000800000000000100000000000c0000000000002000000000000000000000000000000000000000080000000020002010000000800080000000000000000000000080040000000000000010000000000000000000000000000000200000080000000201000000000800000000000000000001004000000000040000000000001010000000000000000000002000001010000000000004400200040010008000000100401208000000000001000000000400000000000000100100000000000000000000011100008001000004000002000020040000000001800040200000000000000000004000000000400003b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000200000000000000000000000004000000000000200000000000000000000000000000000000000000000000000000063c900000000000000000000400200000000000000000000008404008200000010008000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000003008000c000080002000200000000000008000000200041000000000208000000000000202012008000000100080000000000000000200000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bb4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00810000000000000002000000006000000010010100000007800000000000001080000000000004080880000842000000000000004881000000000000000000400400000000000000000000000c000000100080000001004200202000000000000000201800000000000461800000000200401040200000001100008000000000000200000000000001001881800000400000000000000000000000002000000000000000000200400000000000400400000800400b4000000000004410000000000000400000000000000010000000000000000020000008000000000020000000000000000000000000000000000000200000000000000500100000080000007b4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010401040000000008000028000000a0000880000000000000000000008000000000000000000000020400800800200200000000000000000800000000000000000000000000000000000000005ef80000000000000000000002000000004000000000000000000000004000000000000000000000000000000000000000000000000000000002000000000000100000000000000000000000000000400000000000010000000000000000000000000000000000000080400000100000000000000000000000000000020000000020020000040000000010820000848a4000000000000000000000000020000000000000000200000040020000000000000000fb4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000800a00000002000000000000000080000000000000000000000000000400000000000000000000000020000000800001010000824400000200000000000002000000080000000800000000000000000800000000020000000000280000008000000100000000000000000400108200000800000020001000000000000102000000000400004010000080000000800800000000000004410000000000400000000000000000000020010000000000000000000144010000000000100110000440000000400001040000000000000000410000000000000000000000000008000100000010100200000000800200000000000000000000001400000000074040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040201000000800000000000000044000000000000082000000000004014200100100000100000000000000000000020000000000000000000000000400100000800810000000000000400000400000000000000000000000000000000000004b12000000000000000000000000000200000000200000000005000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000400000000000400000000000000020000000000000008480000000000000000000000000000100000000000000000000000004004000100008000000000000000000000000874040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10100405080000000000200120000000000000000000000008000010100000000000004000000000000100000004000004000004000100000000000000004018000000503100200204000040900088000092000000040000000084824820000010010400000000000000000020000000022000002088004000500000000000000002001208000100000000040000020000080000400020000004000010800400000020100000000000000000044000000400024044000000000000000000111100000000000000000000400220000000002844a2400408002008010000000420002000000040080012000041000002800400000100000100082002100000000000474040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (218002040001248000000000124004000204000008400000008004104100000004000000000100400000000000080200a20010082000000000004000200000000000000000006008000000000000000030000000000002000001000000000020000000000000000000000000000000000000c34000000000000000000000040000020000002020080820820100000000020802080820000000080002000000000000000000000000000000040800000000000080080000000000100200000000000000000000102000000000000c200000008800220020010820020000000001000080808300040002000004000004100128104084000000000000000a04220100c74040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008808a0800000000022000000000000a00400400030002000000000100000000400000000000000042000000001800000000000120000000000004800000040080022108000100180100000000004020420000010820001900000009012011040010001000000002100020000410000000400410000000040000000201200002002002000020000020080000000000400000100000000100480000000000100000000000202008000000400000010002100002480a400804400000000080000022100001000000000000080080040008000000000000000000000040000000000400200200080040000006002000000880086000000000580200000000000200274040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002082000200000400002120000510200020102040000900001000800002094080008000100000000020000000004084100400000000000004000000005000000000000000000000000008000200000200000000000002008000000000000000000000000000800000000000020000000000000000000000000000000000000000000d217000000000000000000000000000000000000000000000001000000000000040000000000000000000000000000000000000000000000000000040000000000200000000000004000000000000040000000000009000400000000020000000000800808008000000020000000000800200000000004000004000000a74040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000008c0001000000001000000000000000200000400200000000202000040000000400010010000002000040000808c00000000000000000000000000000001000000000000100000000000004000000000040001105000000840000800000004004000008000000000000020004002001040000801000000002000008020020440000000000000000000000000200600000001400000008020200200800a004000090001080000000008000000004000000000049001010040008200000010000110000000401000001010000000040000021000004000200000000040840000004100001002000000000040000000040000400000000240000000000009000674040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000000000003000000410084000000000000024004000004001021c44000000020043010000000053413201000002050000000040041041100302000000000000100b0000000008800000020000000000020000000000000000402800000814004000000300000001000040040000000000000002000000040000000000000000000000000000000000000000ea9e00000000000000000100200000100020000800020920820000000020020800820820000000020000800000000000000000000000000000004800000000000800020000000000000400000000000000000000000000000000000c003000008200008000000288000000e74040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010000000000800400000100000100000100000800000000000000000000000000008008040000000020000002000000010000000000000004002000010800000000000000000000000004000000000000000000000000020000000000000008000000000100010000000000000000000830080800002000200000004050000000000000000000000020000850000000000000000000800800c0000000000000020000110000104002544400004080000100000100000001000000000008000000000104000000000000000000010004c01000020000000002810000000000000000200001000000000000000200080010000014001000000000100000174040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000080002000001000000080000000000000403009001000000000010000000000000005800400800000000000180000000000002004000000000000000000000001000201000000204000000000008010000000000508020000040000008002801100000003000700000000000000000000000000000010004000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000a580000000000000000004001000004000000000000004000000000000000000000000000000000000000000000000000000000000000000000100040000000000000000000000000000000000000000000000000000000800974040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000020000800500014000200000800200000020004000001000000000000000000000000080000010000005000000400000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000002000000000000080008000000040400000000000080000001000040200000000080401000000000010000000000000000000000000000000000000000000400080000010200002000000400100400000000000000000030000000002000000000000000000000000000000000000002000000400000000008000000000400000000574040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000080000100000000000000000200010000004020400000000000200020000028028000000000240025100000000020b42000000ac006d10014000000001000204080000a00008005000000000000000000000010002008000000100000000000100000000000000005000c80825000000001000b4000400090008c00000000000000000000000000004000000000000400400000000000000000000000000000000000000000000000000000000000000000000000000000c6ea000000000000000000000008005040000020003000000000020000000000000000140000000000000000000000000000000000000000000000000800000000000000000000d74040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000008000000000000000000000000000000000000000000000000000000008000000000000000000000000000000008000000000002000400000000000000000000a80010000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000140000000000000100400000000000000000000000000000002000030402000000002010000000000000000000000000000000000000000000000004000000000000000000000000000008000000080000000000000000000000000004000100400000000000000000000374040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000040000200000000000000000000000000000008000000000000000000000000000000000200000000008000040000000500000000040044000000000000002800d0010050000008000000000000000000000200000000000000000000000000000000000000000200000000100000000000004004000000000000040000000000000000001000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000de5a000000000000000000000000000000000000004000000000008000000000000000000000000000000000000000000000000000b74040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000002800000000000000000000000000000000000000000000000000000000000000008000002000060000000500800000000000000000000000000000000000000000000000080010000028000000000000000000000000000000000080a00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000004400000000000000008000000000028000000000400000000002010000000000000000000000000000000002000000000200140000028008005000000000000000000000000000800000002000000000774040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0010000002000200010040000000101000000008040800400004020000000000000001000000010000004020000800400010000000800200200800040008010020002000401201200050090090050106106100c0148448648405000218a1021000020100228049000802000600440000000000000000000000000000000000001212000000000009000000000210228005001011210210220048608418402400a1021021000000000000000000000100840000000022022000000000000000000000000000000000000000000000000000000000000000000000000000001189000000000000000000000010000100a00008000000000000000020000000000800f74040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0020001000000000000002200a0000000002000800000000000000000000000000000000000000000020200002001000000000000000000000000000000000000000000000000000000001008000080022000800000080200000001008001002000000040000000000000000028040000a0020200020001000000000000000000080040000002000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000040200000000008400000200000221020000000000000000200000000802200824000080042001000040000000000000000000000000000000080010000000000000010000804080000000000000f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000804000100000001800000000000000000002000000040000000020200000000000000800000020000400000000000000000100040000000000000000000040001000000000000000000004000000800000000010160160000400008002610208210050008408628400408a10210a1000060190008608801800008201020000000000000000000000000000000000000a0200000000800880000000000001000800a611208a100101184084186800000002102000000000000000000000000080000000002002200000000000000000000000000000000000000000000000000000000000000000000000000000d50c0000000000000000000000200021008f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00005c9e0000000000000000000000000020400000200000000000000220020000000000000800000000000000000000000000000000000000000020200008000000000000000000000000000000000000000000000000000000000000000000000020000800000000000000000000001000000280000000000000000000008040000200a0200020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000240000000000001800100020060a20000000000000400100000000804201000000000012000000000000000000000000000000000000000180004f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000004080001000000000042000000000000000000000000000004020000000002000000008002000000008040000000000000000800100000000000080000000000000000000000000000000000010004000000000000100100010000000000000000000000000000000000020000000000001020000000000040000000000000000000000000000000010000000000004001400000000000000000000000000000000000000040000008000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000008415000000000000000000000000000000000000000000000000002002000000000200000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000020002000000000000a00000000000000000000000001000000040240000000000802000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000020000000008000800002f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002000000008080000040010000000008000000000000000000000000000000000002000200000000080000000004000000000000020000000000000000000000000800200800400008020800000000000000000000000002000000000020000020000000000000000000000400000020080000000000000000000000000020000000000000c10c00000000030830000000020c00c0000000000c00020000000010000000000000000000000000000000000000000000c00000000000020000000000810800000010000c10c00400400830030000000000c00c000000000000000000000000300000000008008000000000000000000000000000000000000000af4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000eb6000000000000000000000000000000000000000000000000000200a000000000000000000000000000000000000000000000000000000002000000200000000000000000000000000000000000000000000000000000000000000000000000000000000020000002000000800000000000000000000000000000002400000010010000000000808000000000000000080020000000000000000000000000000000000000000000000000000000000000000000000000000000000000001400000000000080000000002000000200000080000000000000001006f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000800400000000010214000000000000400000020000000000020000c8400200100004010000000000000000000000000000000002000000000200080000010208002000000c00000000000000000100402000004010003000000210000000000200000000000000000002000100c000c0400000000000000000000000002008000000080000200010000000000000200300100a401609610100120028608402000000a1021000000000040648400002008000800000000000000000000000080020000000020222000000008808000000000020c02001400400e0821008000000841840202080021020000000000000000000000100900000000022021000ef4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000030600000000000c1800000000000000000000000000000000000000000000000000000000000000000000000000000000000004bd100000000000000000000000800000040000000400000000000000800000000040000000000000000000000000000000000000000000000000000000014000000000000000000000000000000000000000000000000000000010040000800020000000201000800200014040010040000000000000000000000000a000801080100000000001004000000000000000280040000802000000000000000000000000000000000000000000000000000000000000000000000000000000c09000000000030250000001f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000030600000000000c18000000000030600000000000c18280000000030000000000000000280000000000040080000010001000000000000000000000000000000000000000000000000000000280000000000000000000000000000000000000000080000010000280000000000000000000000000000000000000040000000000000000000000000000080000000000002000000400000080000010000282000000430614864251480c1852190945203061486425148000c18523900000430600080000010000000000000000000080000010c18280000000030600000000000c18280000000030614864251480c00521909452000014864251480000009f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (74d9100004e0ddd3644c0c1383774d9100000000000003aba8010000000eaea00000000000000000000000000000000000000000000000000000000000000000000000000000000000007214000000000000000000008000001000000000000000000a08000001000000200000040000000000000000000000000000000000000000000000200000040000000000000000000000000000000000000000000000000000000000008000001000000000000000000000000000000000000000000000000000000000101000000000000040000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000005f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000155540000000005555000000000155540000000005555012a200000000000000000000007f8c400000447c000008046f0f000000000000000000000000000000000000000c000000000001f1f01000000007c7c00000000000000000000000000000000440000000114000001400000000000000000000000003fc000000000000000000000000000000000044000000000018428000000000156000000391485511d5555303774d9155554e0ddd36455555383774d910055554e0dc5511d5554000015447000000000000000000000021310555566084000015554000000000555562118000015555303700df4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1a9a80000000006a6a6211800001a9a92038f718e0000498e3dc638c0c12638f718e0000000000000054540100000001515000000000000000000000000000000000000000000000000000000000000000000000000000000000000046f6000000000000000000000004421000000000000000000621084421000000000110840000000000000000000000000000000000000000000000000370840000000000000000000000000000000000000000000000000000000000000008080000000000000000004000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c400000000000000000000000000000000000000000000000000000000000000000000000000001a9a80000000006a6a0000000001a9a80000000006a6a6a2a200000000000000000000003d8c400003fffc000024446507000000000000000000000000000000000000000c800000000001f1f01220000007c7c00000000000000000000000000000000000000006a01c000004454000000000000000000000015c0000000000000000000000000000000000000000000000008464000000000dc000000289ce37085a9a92038f718e6a6a498e3dc639a9a92638f718e006a6a498e237085a9a800000dc210000000000000000000000213106a6a66084000000bf4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000011010006a4208800001a9a80000000006a6a0251000001a9a990c600c726a6a66308039c8000198c220e7200000000000000005400000000015150000000000000000000000000000000000000000000000000000000000000000000000000000000000000119e0000000000000000000000044210000000000000000006210844210000000001108400000000000000000000000000000000000000000000000005511c000000000000000000000000000000000000000000000000000000000000002544b353500000000020000000000000000000400000000000000000000000131004000000004c40000000000000000000000004007f4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000000000000040000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000001a80000000006a6a0000000001a9a80000000006a6a1004800001a9a800000000000007288a00000000000000c8480000000001000000000000000000000000000000000000000000000000310008080000000000202000000000000000000000000000100000105100000000000000000000000000000000000000000040000103000000000000000000000000000000014e2a00000000010400000013c52413b801a990c200c726a6a66308031c9a9a998c200c72006a6a66308413b9a9a80000104ee000000ff4040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (06400555561b22626b555540000189ad000000000000000000000011019c0554209c00001555400000000055550211400005555580cc83064555561b220c990000186c8872640000000000000303a8000000000eaea0000000000000000000000000000000000000000000000000000000000000000000000000000000000000b1d600000000000000000000000842a80800000000000000003148842a000000000210a80000000000000000000000000000000000000000000000000622b00000000000000000000000000000000000000000000000000000000000000000aa80000000008080000000000002000008000000000000000000000000001310000000c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0108000000000000000000000000000000000000800000000000020000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000003015400000000055550000000001555400000000055550285c00001555400000000000005f88e0000000000000017490000000000000000000000000000000000000000000000000042000000310141080000000000042000100000000000000000000000090000028960000000000000000000000000000000000000000000003103000000000000000000000000000000000a43c000000001881900002289e626b7015580c883064555561b220c191555586c8830080c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800004020800000000800000000000000000000000008000000200200000048000000008000000000001400004200000008000000000000000000000000000000000000000200000000000008000000000001600000000000008000000000000200000000000008000000000000200000000000050000000000001400000000000000000000000000000000000000000aa8600000000000000000000000852b00000000000000000002158852b000000000214ac0000000000000000000000000000000000000000000000000417bc000000000000000000000000000000000000000000000000000000000000001130d0000000001080000000000002000040c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002800800100100000020080000000800000000000800100000000020000000000000050000100001001450004000200008000000200040000800000000000000000040041404000000000000001000000000000000000008000000400400000000000000000000040000000000040000000000008000000000011600000000000000008000008008040000000000000001008000001400010000000001000000000000000000001010001000008000008000008000000001440000000000040000000000000000000000000040000000020000000008000009140000200004001100000000000000000000000040000000002001004004000000008000008000c0c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000400000000000000000000000000000000000000000000000000000084082082000020000000800000004080400000000c00000001000004080001800000000000000000000000000000010100000000000004000000000000100000000000004000000000000110000000000004000010000000100000000000000000000000000000000000000000000000000000000000000000000048f90010000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000800000000000000020000000000000000000000000000000000020000000000000000000004000020c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000010000000000000000000003400000000000010000000000000000000080000000000440000000020010000000000000000000000000100000000000000004010000000000000100000000000000000004004000300000000000000100000000000000000000040000000000000000000000000000000000000000010000000000004000000000000100000000000000000200000800000000000000000000100000000000000000000000000000000000008000000100000000000000000000000800000004804000c000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000800000000a0c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000001000000000000000002000000010000000000000400000000000000000004000008000020208000000004000000000000000000000010010410401000000000200000000010100000000000000004080000010000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000004000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000004e540000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000020000000000000000000000000000000000000000000000000000000000000008800400000080000010200000000000000000001000100000080000000000000000000000000000000044000000100000400000200040000000000000000000000000000000000000000000000000000000000000000010400000100100000000000000000000040000000000440000000000000000000000010000000000000000006000000008080000000000000000008000000000010000000002000000000000080000000004002000008000008000000000000002100000000000080000000000000000000000000040000000000000000008000008040000e0c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0020000000000000000000000000000000000820000000010000000000000400800000001000000810220040400400000000800000000000000010000000000000200000000000000000008000008008208000000004400008000008000000000010000010000000009400000000000000000000000000000000000000200000000000008000000000000200000000000008000000000000600000000000008000000000000200000010010000000000000000000000000000000000000000000000000000000000cc5a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000010c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000002001000000000000000000000000000000000000000000000000000000000000000002002000000020020000000000000000000000000000000000000000000000000000000180000000002002000300000000000001041000000000001000000000800000000000000000000100000000000000020000400800004000000000810020000000000000000008000000000000000000000000100000000020040000800000000800000800020020000000000000000200000000000000000000000000000010040000000800000000000000800020000000000000000000001000000000000400000000400000000020000400840000000000000810090c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000001800020000000000000000000000000000000000000000010000000000800000000000000000000000004000000000000000000000000000000000000000000000004000000000000200000000004000000010040000011410001000000040010000000000040001010200040000000000000000000000000000008000000000000000008000000000000000000000000000200000000000000000000000002000000000000000000000000000000000004004008000000000000200000000000000000000000000000000000000000967a0000000000000000000000000000000000000200000000000000000000000000000000000050c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000080080000000000000000000000000000000000000000000000000000008000000000000000008400000000008000000000200200000000000000000000000200000000000000000000000000000200000000000000000000100000000000000000000000000000000000000000000000000000000002000000000000000000000000000200000000000000000000000300000000000000000000000400000200040000000000600000000000000000000000000000000000000000010300200000d0c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000008000000000000000200014000000000200008008200000200000008200a000000000000000000000000000028000082000000000200000000000080080000440a0000008280202800000000000014020800000000000240000000000000000020000040000000000400140010000010000082400000000000000400010028000400000000012000000000000000000080000000000000000080800000000000080000000008000000000000000140001000000005001040000000040801000000002000040004800a00008000000000020000000000000000000000000000000000000004ce20020000000000000000000000000000000000030c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000200200000000000000000000000000000000000000000000000000000000000000000000500000000000000000000000000000000000c00000000000000000000000000800014000980000200500010000020040a0028008080b02800000000000000000000000200000000001000000000000014602800008000040000000008000200000000000000000040000000400000000000000001000000002200000008000100014020008010602d00000000000000001000000000000000000100000000000010202800048000000000000008000200000000b0c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000800000000000000000000100000400000000000000000000000000000000000000020008000208000000200000000000000050400000008000000000000000004000000000000000000000b0a000000000000a0010000000400000020000000000000004000020008000000000000000000000000000004100001100000400408000010048400100400400000000001000001000001400000000400022000000000003400000000020004000400000000008000000000000000000000000000000000000a2f80070c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000d64f000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000002400008000000000040a020000000100000000000000010420000000010008000000000000000000000000010200400002010000000000000000000000000000008000000000000000000000000000000000000000000001200000440000080020000000000000000000000000000000000000000002000f0c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000010000000400000000000000000080000000000000000000020000020000000000000000000000000000000000000000400000400000000000000000000000000000000000000000000010000000000020000000000000000000000000000020000000000000000000001000002080008040000000000410000000000000000000000000000000000000000000000000000804d3100000000008000000000080f8604004000000000000040008081e0000000000000000000000000000020000000100000010010086032200908000000030000000000100000000000100000000010804180000000020811886020000008000007200100008020000008c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (22282200000080002008010001010010000000000000000000000000000000000000edb8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000020002000830000004000002460000004000000000000100000000000000000800060000100000000000000000000000000830000000400000000002120000000000000000100000004000000000000000000000000000000000000000000400000000800200004820000080000000000088c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000400089204100000000010400000000000000000000000000000000000000000000008000080000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000011000020000000000000000001000000004000000000000400000000000000000000000000200100000000020004000000000000000304000000100000000000080000200000000000000000000800000800000000202000000000800000404000000000000000000802000800000000000000000000000000000100000000000040020100008002040000040000000000000000000080800040000000020800000800000000048c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010020000000000010410101000000000800400802004002a10042000200202000000000000000000000000000000000000056f80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000120000000000000000000000000080000000001000040000000800000000000040410020000000000000000009000010020000000008010000000000000000000000000000400100040000000000000000000000000000000008200000000000000000000000000008000000c8c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000090000001000040000c0208084000012800002000000000000000000000000000004000000000010000010000000000000000008000020000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000008002010000000000000000200000020000000000000000400001000000010000040000000080000000002000000000000000000000000100000000000000000000c00000802000000002000800000400000000400100000000001000400080000000000000800000000000000001040802840000010000000000200004000000040000000800000028c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000860000000000000000000000000020000011000020800000000a24029400000001522040520000000011000100001000040000000000000000000000000000000000089060000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000001000000000000000000088020802884000000020000a0008000004000000a000001000400200040004020008100000008000000000000000002000101000004210000200022010000000000000000000400000010000a8c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000030000000000000010000000400000000000000000c00000000000011000000000002000000801400000000000020020000000000000000000000000000000000030000000000000000000000000000000000000000c0000000000000000000000000000000000010003000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000002080000000000410000000000000000000082000000000000000000000000100000000000000000020000000004920400000000000000000000004000000000000000000000000004000000000000000400000000000000040080800400000000068c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000070000000000021c108008000003e00000000000010000000000000400000000000011100040000000024000001200120002000040004000000000000000000000000000000000000000000b3cd0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008050200021000000800000000201008000000008040200000000100000000000010000000004000000000000000001008000000000200000400e8c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000800000000000000080c00000000000000000800000020000000000000000000000000000000000000000000000000010188400000000c000000001000000000000008000000200000000000000000000008000000000000000000000000000000000000000000000000000000000000000200110200000000000000000000000000000000000000000000008000000000000000008000000000000000400000000000000000002000200000000010008000000000000100082000002000000000000000000000000000000000000020000001010100004000000000000000000030000000000080000000002000010200000000000018c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000001000000100610000002000000000000000000004000004000000000000000094000000000000000000000000000000000000000000000000100080004000004002000000000000010900004000010000100000000000000000000000000000000000007391000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000110000000000084c00000000002002000000000000080000000004000098000000080000000098c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000020000000000054080004008011400000101800000005102000010020000020000600000000000010100000000c00002010020000000200000000002082000000000000000040400000000000000000000420100000000014000020100000000100100000000008000000000000000000000000000000002000000000000010000010000000000000000080000100000010000400000000000000000000000000610000000400010000010000000421000080000200000010080000000000000000200000020000004000000000000400400000000000000000000000600600000000008008200200200000000000000000010000000000000000001000000058c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000080000000000040400000000000000000000004000010100000000000000000000000000000400000008410400000040400000400000001000000000480000480000000000000000010000000000000000000020000040004000100000400a02000020020000000000000000000000000000000000000000000004ad80000000000000000000002000000000000000000000000000000000000000000000000000000000000000000080000080000003000000100000000000004000002000014000000100000000000000000000040000000000000000001000000100000000000000000000000000000000000000000080000800000000048080400000000d8c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0060000001000400020004000000000000000000000000000c02000000000000000000000400000000000310000000000000008000000000028000000000000000000000008040000100000000000000000000000000000004000000000000c0000010000040000000000080000000000000000000000000000000000000000020000000000000000000002000000000000800000001000000000000000020000000000001000000000000000000000012000000000000000000000000000008400002000080000000040001801000000000000200000010000000000000000000080000000000000000000000000000000000010001000000000000000000000038c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000100000200208008088000010010404410c20000000040048820000004000000000100041004000000005000000000000000000044000002041240000c00040000842024000420010000c500040520000000000000000020000000000000100008224000004400000080000200804102001002000400040000000000000000000000000000000000003b160000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000004000000100000000000000000000000000000000000000000000000000000000000000004000400400000000000b8c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000080000080000820000000000000c10080010000800000001000000000000088000450801001002020000000401100300000004120000000000800002000000020001000000080400080062020000004000010400000000000000000000000000800400000000104044000010010000440280000041011080060002000440080000000010002000100000000000000000000000000000000040000000020000000000000000000000000100020000000000000000080000020011040000000000400000000000000420400004400400000402040000000000800400400880800010000000002000000400100000000000010000000000000078c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (200280000000000000000000800000000000000000046000200000000000008808100800000041000080000040080308000000000000020000020080000000000018000000004080000000140000000000080000042080000000000101000000000021080000000000042002001001001000000080000102000000000280080000000000800404010014008000000000000000000000000000000000000000005e360000000000000000000004000000000000000000000000000000000000000000000000000000000000000000200000100000004800000000200100000000000004000000000010000000000000000000000010000000000000000004800000f8c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000100000000000001000000000000020000000800000000000000000004004000800004004000000000190010000001200000000000081000008000208048004800040009200004021b00000001805000008000200024000000008010000008000080000304004010400000000000000000000104022000000000000000200000000000000000000201000100000000004000008000000000000000000000000000102000000000000000000080000000000180000009808011000040010000000110000001048008000202000000000000008000000001028080080240008000000200000200000420000000400028400000200000080880000000020000020004c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000100000000200280580000000c000104220028302000002002000800000000000000000000004a00020000000000000800810210010400412c28000000008000020000000100000000000024008004000000000800000000000000004004000000000000800108000800830008820010000c000140008000040002001001001040000000080001088208800001080040000000000018010400000000600000000000000000000000000000000000000005831000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000200000000001000004000000000000084c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000022000000080042410080080002001180400000000002010100040000000100000040000000200000000000000000000002010000000000040000010000000000240100008008008000000000000000000004000011000080000200000000000104084000000008010200200000008008100000004000200000000000000004000002010000000000000000040000000000040000002400008000000010000000000000800000000000001000000100000000000100000010040240080000000008000000000210200000004100044c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000002800000000c0208200c0000880022002000000000000000028000000008200000000000000000000040000000000c0000000000000000000200000000000000002800000081008002000000000000000000004000c20000010000104080000023000000000040000003000080000000040000000000003000000040000000000012000000000100080000000000102000000000004041008200102000000000000000008008200000000200000000000000000000000000000000000000002a2f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c4c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000020000000c0000000000000000000000000000000000000000000804000820040c00100020800000100000000000040000000080085000000800000000000000ca0000000000810000004000000000200080000000200000000000000400000020010000000000000000000000000000080000000080000000000000000000000102000030000000000010000000000000000000000030000000000000000000000000000000000000000000000400000020000040000000000000000201080004000000000000000028030000003001000000000024c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000080000000000000000000000000000000000000000000000000000000000000000000002d000000040000000000000000008000000080008000000000000008000000040000000000000000000000000000000080000010002000004000200080000000008002000000000a00000000000028000000000000940000040100000000004022000008000200000000100000000000000000000000000000000000002b290000000000000000000000000000000000000000000000000000000000000000000000000000000000a4c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000200000000000000000000000000a0000000000002800200000040000800100010000008002000000000000100000003800000000040000000020090070000000000000040000000401000000000000000000000000000000000000000000000c0084009004d0100000030001000000000000000000000000000000000000000028000000000000000000000000000000000000000000000000000000000000000000000000000000080064c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000080000000000000000000000000000080000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000200000000000000000000000000000000010008000030000000000000000000000000000000000000000000000000000004000400200000400025000000028009b450000000000484000000000000000000000000000000000000000053b30000000000000000000000000000000000000000000000e4c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000a0008000000000000000000000000000000002000000a00000000000000000000200008000000000000080a00000000140a00021024000000000000000000000200040000000000000000000000000000000000000000000000000000000000040430001010010000000000000000000000000000000000000000000000000000000a00000000000000000000000000000000000014c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a000000000004001800000000000000000000000000000000000000000000000000080000000000000000000000400000080000000000000000000600000000000000000000000000000000000000000000000000000000050080000000000000000001800000000000080000000000901000000018080000000000000218000002000000000000000000000000000000000000000000000000000d7f4000000000094c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000009fab00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008008000000000200000140000000000002000140000000000000040000000400000000018004000040000000000000000004009000200040000000000000800000000028000000000000000000000000000000000000000000020010200000800004000000000000000000000000000000000000000000000000000000000000054c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000008004000080400000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000010002000000400000000000000000000000000000800080000008020004000000400002008000200100000000000000000000000000000000000000000000220120003003000000000000000200020800002100020000000000200020001004000000000000000000000000000000002000000000080048009004000000000200000000080004000800002000100020090080009005002802410210214091108428488448100208000600000000000000d4c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0081842840840008040001020000000000000000000000000000000000007e2700000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000001000020010000000001000200800040002008010000000040000020004040040400000400008004010002000100800004000080000011024200500100000000000000000080001000000000000000000000000000000000000000000000011012000500000104400000004000000000000000034c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000880890001000090002000000000000000000000000000000000000000000000000080400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000800000000000000000000000000000000180000000020000000000400002000000000000000000000000000000000000000000000000000000220160002401000000000000000000020000000000020000000000100000001800000000000000000000000000000001002100000000200010000000000000000000000000000004000800000000100020000108008006001400610200216100b4c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000002000000000080000040000000080000000000000000000000000000000000000000000000000000000000000b2c700000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000800400800040002000010000000040000000004100040000100400000000000002000080000000000080000001020000880400000000000000800100000010000000000000000000000000000000000000000000000000074c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000200400020000000021000080000000000000000000000000000000000000000000000200008000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000001000000004020000000000000000000000000000000004000001000000000000000000200000000000000000000000000000000000000000000000000000000001000100a000000000000000200020001000000000000000000000000000000000000000000000000000000000000000000000040000020000400000000000000000000000000001000002000f4c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (030000000000000400000000000004000000000000400000800000000000020000c00c00000400030030400000000000800000000000000000000000000000000000ccbf0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000008000200000000000000400000000000000000000000000000000000000000000500000000000000000200000000000800000004080000000000000000000000000000000000000000cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000400020000000000000000000000000000000000000000000020000800000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000040000000000020080002000000000000000000000000000000000000000000000000000800000000000000000000000000008004022000300000000002000000000080000000000000000000000000000000000000000000000040000008cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000280030000000003004c000000000000000000800000000000020000000100a0000001001002004400200210040100008488400000080010200000000000000000000000000000000000036a20000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100800000000000000000000000000020000000802000000000000000000000200000000000000000000000004cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000210004000000400008004000000080000000000000000080005000000000000000000000000000000000000000000000014015000000000000000000400000000000000000000000000000000000000000008004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008003000080000000000000000000000000000000200000000008000005000000000000028000200100000000000000000000000000000000000000000000000200002005000000000000000100000001002080000000000000000020000002000000000000000000ccc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000002800000000000000000000000000000000000000000800000100002820000004000000800000000000020000004000000800000100002820000004000148642514800005219094520000148640000000000000000000000000000000000000000902c00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008008020001000200000000000028000002000000400030004000000a000c000001000201000002cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000028000000000000008000001000028000000000004000000000000028200000040000000000000000000000000000000000000000000000000000000000000000000000028200000040000008000001000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000040000000000000000000000000000000000000000000000282000000400000000000000000280000000000000000acc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (11c00000000000000000390ac00000300c00000000000007ba2000000000000000000000000000000000000000000008800000022084220000000002100000000000015000000000000100000003894a708000001303774d9100004e0ddd364400013837000000000000000000000000000000000000000020fa0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000002000000400000080000010000010000000000000400000006cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000001880100000000000000000000000000000000000000000000000000000200000000220000000000000000000000001264b9824000000000000021000000000000000000000000000000000000000000000000000000006a005f5a83015400000bb1000000000000000000000000000000000000000003c3c00000000000000000000000000000000000000000000000000000000000000000000000010800000000000000000000000000000000000000000000000000000000231f00000000000000000000000000000000000001212000000000048480000000000000000005511c0000000000000000000000000000000000000000000000391485500ecc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000289ce37084000000000000000002894000000300c00000000000001980000000000000000000000000000000000000000000808800000000084220000000002100000000000015000000000000100000003894a3000000012038f718e1d1d49ce3dc6380001273880000000000000000000000000000000000000004af00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000044000000000000000000000000000000000000000000000000000000000000000000808400001cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000840000000018800000131000000000004c40000000000000080200000000000000020000000000000000004c40000000000000480100030800000000000008480000000000000000000000000000000000000000000000000000000720402a0370004000077b100000000000000000000000000000000000000000141c00000000000000000000000000000000000000000000000000000000000000000000000010800000000000000000000000000000000000000000000000000000000231300000000000000000000000000000000000001212000000000048480000000000000000003708400000000000000000009cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20200000000000413b8000000000000000000000000000000000000000000000013c52413b80000000000000000013aaa00000000000000000000001280000000000000000000000000000000000000000000008c00000801044230000000001120000000000061230000000001008c000002c5220020000190c600c72000066308839c8740198c20000000000000000000000000000000000000000fc510000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000044000000000000000000000000000000000000005cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000a800000000008080000000000010000000000000400000000000000000000000000000000000000000000000000000400000000418006000000000000000000000000000000000000000000000000000000000000000000000000006baa3470a00000000029a10000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000001080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000808000000000000dcc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000108000000000004200000000000626b400000000000000000000000000000000000000000000002289e626b4000000000000000002281400000000000000420000001080400000000000000000000000000000000000000000018500000001044634000000001120900000000061634000000001018d00000285620044000180cc83064000061b221c990000186c880000000000000000000000000000000000000004be50000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084003cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000084090000000000000000000000000000000000000000000000000000000000000010008c00000000008210000000000000800000000000020000000081000000000000000001000000c000000000000000000200000000003000c0000000000000000000000000000000000000000000000000000000000000000000000005b8102a5680000000055811000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000001080040000000000000000000000000000000000000000000000000000000000000000200000000000000000bcc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8041080108000041000000200200200400008000008000000000000001120008000000000000000008000108008000001000000a0800020000000800000000000000000000080408000000000000008000000000000048000000000010a000000080000000000000000000000000000000000000800000020000000000000000000000000000000000082000000000000000000000000000000000000014200000000000090000000000002000000000000000000000000000000000000000001f990000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007cc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000400000000000080000080000000000000000002000000000080082000000000000000000000080000000080000000080000000500000000000000000000000000580002080000002000000000000000100100004005000100910802005104110000000000400000100005000020004000140000800000800000008100000000000800900800800000000000140000040100105808020000000142040000000800800004a00000020000000801005808100004000001000210200000000810800010140000000000805810040c0000002000000000080080080000000000000002002001000080100000014004011101000010205080400440000000200000fcc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000006004000000000002000004240004800000000000180000080000086000000000000180000400000000004000000000000000000000000000000000000002000100000000000000000000000000000000000000008000000000000008004000000000008000000000009000010440000810000000000020000000000000000000000000000000000000000000000000000000000000040200000000000000000000000000000000000000040000000000040000000000001000000000000000000000000000000000000000000ec1500000000000040000001400000000012052002002000001482000000000000000000000000000000000000000002c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000004000000000000000000000000800000000008000000c0000000000400000000000000000000121000400040000000000180003000000000000000000000000003000000400000000000010000000000000000000000000000000000000000000000000000000000000000000300000000c000000018000000000000000000000000000000000300340000000000000000000000000040800000000000040000000000040000000000001000004100000040800000000400000000000000000020100000800000000000100040900000300001000000000000040000800000000020000000000048000000000001200082c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000080000200100000004004000000000100804000001000108040080080000000a080110000080000804000022001022001000080000100000040000000020000040000000000000000040000040080000004800002040002000000080000000000000000000002010000000000000000001000000000008000000000000040000820000100800000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000094eb00000000000000000000000000000000000000000000000000000042c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000010000000000000000000000000000000000000000000000000000000000000040000000000008000000000000000080000000100000000000004200000000000000008c00000010000004000000008000000000000000000000000000000000000000208000000000000000000000020010000800440020090080800020810000000000000000008000000002000200000000100000100000000020000000000080088100000000000000000000004010020020002000000000001000000080000000880000000000044040100020010000204000040000000000000881080008000000000004040024004080000000000000000080000050000c2c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000810020400100020000000040000a1300080000000040080000001050000401000001000094001001002041040000040000000010000151804000000004041082000000000000000000000000080000000001020040000080000000000000021000000000004081000000000000020000000000000080000000000020200800008000000000000000020000000000000000000000920800024800000000000000000000000000000000000000000000000000000000000000008000000000810000000000000000000000000000000000000000000000000020840000000000020020000000000000000000000000000000000000079dc00000000000040000022c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000c2a8000020000000000000000000000000008008008008000800208000000000000000000400800040000000000080000000000000000000008000000200000000000000000410000080000000000000000040000000082004000000000000000000000000000000000000000000000000080000000000002000800000000000000000000000000000010000400010010000000000400000000000000000000000400000000000000010048000000000010000008000a10000000000000000400000000818500000008000000000000000a10000200000024000014000000918001000000000400a1021000000041000004000000101000000a2c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010030000400000000020001010020000800840000080c0180000001000009842000000600033003000000000c8020000000200000800000020000000000000000003000000000c00000000000800010400000020000000000000800000000000000000000000000000000000000000800008000000000100000000000002000000000000000000000000400020000000800000000000000000000000000000c0000000010c00000430000000000000000000000000000000040000001000000000000000000000000000000000000000000000000000000000000000000000000000200000000000400100000000000000400000000000000000000000062c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (058000000050002000000000000000000000000000000000000065d3000000000000000000002000000000c00080000000000002000000000000000000000000000100000000000000000000000000000000008000000200000000000000000208000000000000000000000000000000004001000000000000000000000080000000000000000000000000080000000000000000200000000000000000000000000000000001000840000000000000000000000000820020c000010200000000000000400000000000000000000020000800000000000200000000000008000800000020200000000000000800000000000000000020000008c000100000080000e2c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000005401802001000a00000000000080080180000000000000000040028000000006000b408a100000000500080000000014000308000000008008000000015088000280002d0000c00000021420a4080000000000100010000b4000400000002d08a000000000000000000000005000980000000000010080000080000000000000000800080020028080000000000000000000000000000080000000000020000800000000000000000000020000000080000000000000001402000000000000000000000000000000000000000000000000000000000000000000004000000001420000000000000000000000000000000000040280010400000000a800012c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000005000000000000800008180010000800000c080000000000000000000000000000000000009e34000010000000000800028000000000000a000000000004000000000000000000000004004000001000000001400000000000000000000000000000000000200000000000000000000000008000000000c0000000000000000040000008000004300a00000000001000000040008900b48020a0000000580812000000000000000000000000000000004200a0000000000000000000000c100a0200a00014502800000000000000000200000000000204000100014220000086002800008000000014208000020402800000000000000200000092c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000400000000000000000000000888100000000000000000490400080000000410000000000000000000400000800000000080000000820010000000002000000000000014010000000000008000000000000a00000000002008100a0800000000000400000000000010040088004000000000000040000010008001000000400000000000000000000008200000000000000000000000000020000000000000000000000000000000000000000000000000800002000000004008000000000000000000000000000000000008200000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000200000052c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000100000200000000010000000038200010000201348000000000000000000000000000000000000c08e00000000000000000000000000000100000200000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000002000000000400000000000000000000400000000000000000000010100000000000002000000000040024c0008c0000000000000a0000008000000000000200000000000400000000000000080000000000000000000004080000000081000082000000204100000000000000000000000000080084000000000000100d2c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000080000804060000810000000000000804801801004020000041000000000800180000100000000000c0001080020000000000000000000000000000000200000000100002000080018000000000000000001001084e000000000000002000000000000220000001000000800000400000021000010000000000000000840220000000001900040000000800000000200000000800080800000000000000000000000010000000000000020000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000048200000000000000002080000002000000000000000000000000000000000000032c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000200000000000000000000800000000004800101240010010800200000000000000000000000000000000000000000a7210000000000000000000000000000000004000000000200100000000000000000000000000000000000000000800460000000000000000000000000000000000000000400000000809820000000000000000000000803a1000000000000000002480000820000000000001100c3148048029e4000000000100860002000000082000000000000000001bc404000200000080000000000120c0000000001082000000000000800000000180000000000b2c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (410000001000000940000008010000020000000000080000800000800010000020000000004800020800000000041000000000a00820000000000000000020840840041000020000001000000000000010004100000000800000800884000000400000000000020010840840000000000009000000000000200000000800000040141000000000800000000001001000000890084000000000000020000000800000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080810000000000000004000000000000000800000000000000000000000000000000400000000000000072c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000008000000000000000000000820000000800000000000000000000000000000000000000000000000008000000000000000000000000000000100010001000410008000202150480000000300000200000000000000000000000000000000000e69d0000000000000000000000000000000004010000020000100000000000000000000000000000001000400040800001000000000000000000000000000000000000000000000000800000000000000000000000000804040000000000080000000000000000000000000021000000084a040008000000000040000008000000000000200000000000800000400000000108000000000000000000009000f2c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00c040080000000000000002000404000000a00000100020020082010020081000000000001000840000c200410120c0900001040000008c00000000000100000040000000400000000000020000000004024401080002000400000000000000000000001000100000004000044c00000500000020100000010020c00880400000000000000100000900102000001128100810105000800020000810000001011020824d0420080100012000001000002040004040020042000000000000000000000208000000400004000000200000000010000000000000000000000000000000000000000000000000000200000001000000000000000000000000000000000ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000040000000000000000000000000000000049000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000500404010000000001200100000000000000000000000000000000000afa9000000000000000000010100000000000c000000000000200002000000000000000000000000000000000000c0000000000000000000000000000800000008000000100020000040000000200000000100000002040400100108000000000082000400208000024000004300202200cc840490000000200840c000080000002080000000000000002002008ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00102000000000000000000000000000802080001000000000000000000800000000000090082000000001008002001000000004000000000080000002000081080040004002000000000000000000000000002000000000406000000000002400002000005400140000000000000000000000000000000000000000000101000412020000000000400004482001406000000000000000020000010400040482040400004000800000011040000000000002140040010000040000000010000000000000401000000000000400000100000000000000000000000000000000000000010000000000000000000002000000000000000020000000000000000000004ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000020000000002000000000000000000008000000000000000000000000000001004900000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000080000000000001c100008000000405000000000000000000000000000000000000000d8a100000000000000049000004000000240000100000401000000000000000000000000000000000000010000400148010000000000000000000000000000000000000000000000000040000000000000000000000000081604000000000000001002000000000000000000400001008002009014000000000000cac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000004000000033010010000000044100000000000000000000000000000000000000120000000000000000000000000020000000000000800000001000000002000000000000000000000010100100000000800008000000110100000000000800000000000000100000000800400000000000020308408040000000000000000000000000000000800000000000030100000010000400000000084010302000000000000000000000010000088008200c00003002000010000008000000000008000000030100800008000c010000000000001000000000004000000000000000000000000000000800000000000000000000008000000000000000001002ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000600000018000000000800000000000000000000000000000600000000000060000001000000000000000000000000000000000000000000000000000000000200200000000060004000000000c0000000001052800000000000000000000000000000000000000091b800000000000000009000800000000040120200000000004000040000000000000000000000000000000000010340000000000000000000000000000000000000000000000000000100000000000000000000000000100000001000000000001001020000000000aac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000400002001000208000000000008006006000000000000200000020800000000000420000000000000800000010000810c000000000004000040000000000000000000000000000000000080000004c020000000800000802001c00080000800200000000000000821021040000200000040004000140000000000000000000000010000000000000004004000800000000000000012000002020000000000040000040010000000000841c408010000000000010000400000400000000002000010008000001a001000002000000040000000080018008602180000601102000082000000002000000000010000004000040001000000000000006ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800000010010020c000000000000000000000000000000000000000020000200010410000000000000000000000001000000000040000000000000000000000000000041000000400000000000000000000000000000001200000000000000000000000001000000000000000000000040000000000000000000000000000000000000000002000000004000000004000000000000000000000000000000000000000000000000000484f00000000000000000000000020000000040000000000000000000010000000010800000000000000000000000200008010000010200400008000000400040000001000000000000000000000104000000000800000eac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000001100000000000000000000000400000012000000400800000000000002400000000000000000000000100000000000000000000000000000000000000000000000000000038000100000010200000000000000200004020020000000000000000000000000000000000e00820002000020000000000000000004000900000000100000000000000080100003000040004004100000020000000000000000001000400018a00000000080000000200210000008d0000000000000800000041040000000004000000040000001002000000000000024000000000142001000000041000000002000000000000002000001ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0200004000000820804000000044000000000000000000100120004000000000000000000000100000000000000000040000000000000000000000000000000000001000000000040000000000000000004000000000041001000420001005010000000000000000000001100000040040000000000000001000000000040000000000040000000800000040000000000000001001000000000001000020020808c00000c004481400208000000000002000000000000000000000001fc6000000000000000000000000000000000a00000000080000000000000000000000000000080000000800000002000080000000002000000000000000000400000010009ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08000008000204000000400100000000004100200004004400010000000000010410800004200000000020000090008020000200c000000800000000000008844208020000000004084000014200120000000204801000440100928004100000212000080000000010000080004000004000000000200000011000010000000000015040040240000000800801001040828001000810421000820810800800440124080200804800000000080a0000300004000040020402001002000200000280000240080000040002000021400080002040004011020101000000000040002080002081000001000440080000000000002000000000001082104000001000005ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000800060800020000120808024000800040000000000000000040040000800020000000000000200000000010000000000000000000000000000000000000000100000000000000000400020000000000104000000000000100000000000210188000000000000800000004000800000000000000000000001000000000008000000000000000200000000000000000000000004000200000000000000000000000404800008002000004000000008208000000000100000000000000000400000000000000000000000228e00000000000000000000000040000000000000000004001040000004000001009000000004000000000000008000000000dac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000040000008000000000000000080010010000400000000000010400400010010000010000000000010400000000000000200020040010000000080400000000000088000000000095000000000010100410000000000000000002000000500004000000a0200a0020802000480000000018000000002000002000000001000000001000000001000001041000000000001001001000000001041460000001001000040000000000000080090001000000000000008000000000000801000801000000020002000001a0040006000000840002000000001100006100000000000004002040882002802000040004040000081100000100003ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8a10024029000001000004220502008000000000c00040400010000011041160408824100800122320001040202001000002000400000000000080000000000000000000000000000000080000000000300004000000000000000000000000000000200000000104100000000000100000000000200148000000000000000020000010090000000000000000000000000000020024000000000000800200000000020000000000000000000a00000020000000000000000804404004000000840020020814100000c0042001002080000000000000000000000000000000000049ac00000000000000000000000000000000000000000001000000000000000000bac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (090410400410420400410008200000000000008000000010000000000020800160000000000000000800000000000000000000000000000000000004840000000000000000900000024000000000800000000000000000000000000000000000000008a008480080048010000040200000000c0000000003000000000000800012010000080000000000000000000010000000100000000008080000000000000000000000000040860048000000100000000000000020004000060901001001001000000042000210033000000208001208000004000400000402060000060800000000400000811008000000010000802000000028001000aa001000000000007ac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800000000c820c00000a30400000104001040000030400300004040c002000300000004000a0400000004001010000000000014c00000c0800000040080000000000000000010004000000000200104800000000000000000000000000000000000002000000000020820000000000000010200000000000200000000000000000000000000000000000000000000000008000020000000000000000000002000000000000000000000000000000000000000000000000000008000000000000000000000002800000008000000000020010000000000000000000000000000000000000000000000000000000000000d0c800000000000000001001000000fac040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000003ad1000000000000000008020000108208200008210200200000000000000000000000000010000000000008200008000000000000000000000000000000000000000000000000000000300000002080000a002000040080000010004808000000000080000000000004000400000000000603080000002000000000000000000000000100000080000000010080000000104000000000000500000000200000400000000000040000800020000000000000000000000200020000000000010800000008000040000208000000000000000000000100c0c000000000840480820000340000000000000200000008000000401004010010020408b0000006c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000003000020000a200000000000800000000000000000080000000000000000000000000000002000101040000a04010040a00002300400030000c06008020408003000080c3000160000008002400000000000000000004000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000800100000020010000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000150080008009000001400030010000000000000000000000000000086c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000007fcc000000000000000004000000000400440000000000000000000000000000000000000000000000080001004000001400000000000040000000000000000000000000000000000000000000000000000000000000000000200000000000000a0000000000000000000000000000800100010000010040000000000000000000000000000000000000000140000000000000000000000a000000050000000000001600004300000000480000000000000000320200008002200000000804001588020180448000000000000000080010000002000000000000012201040000484200000000004000000046c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0200020080010021004100000000004000000000000000000020000088040020800000000400400000000040040000002000c0000000000000000000000000000040000040002a00008000000120000000080000005100004000100100200000204000000000000c000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000800000000020000000004004000000800000000000000000000000000000000000000000000000000000000000000000000000000000001000020000000000000000000000000000000800000000000002002000020000008000c6c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000400000000088080002800400000000000000000000000000000000000be3d000000000000000001000000000500500000000001000000000000000000000000000000000100000004001000004000000000000000000000000000000000000000000000001000140a0000000000000000800000084084000000000000000004000001000000000000000002000000204050000000000000000000000000000000000000000000b404000000000000000000000000000000000000001000000000058001000030a0000000000000000000015000080140100a000000010004000200005000020000000000000000000000000008010026c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000008000000000000008000000000008000010000008000000000000000000000000000010000800051289280008001400000000000008008000000000000000000000000000100000000082000000000020000000000000004002080020020200000000000000000000014000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000004000000000000010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a6c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800040008000000000000000000000000001000200000000000100c00090030028030001001400000000000000000000000000000000000b63e000000000000028000000000000400400000000000028000000000000000002002000000000040000000000000000000000000040100000000000004000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000005100000a0000000000000000100000000000000000000000000000000400028000000000000000000000000000000000000000000000000006000000800000000000000000000000000800000000060a000000000004000066c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00900030029010480001000208020000028428800400000000001000000008040000000000000442008180406001000200000000000000000000001000000001000220408a0014a021008420011020401102000050030000000000000000000000080010004240002000440100800240008800000000000081010c0029104500004001082020080000000802000000000080040000000000000000000000000000000000000000080020000004000000000000000000000000000000000000000200100000000008080000000002000280000000080008000000800020208000000000000000000000000000000000000000000000000000000000000000000000e6c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002802180080080008000001501800000000000000000000000000000000000d59d0000000000000200010000000000801000000000040200000000000000000020010000000001008000110110245040800000008800400000000000010000000000000000100040000804000000000000000080002005002800000000000002000800000080000000000000002241088012483000400000080020000000000000000000000000000028044000c0140000000000000008000800010100081042000504040000840040504000000000000000000016c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0484010280000010602000000000000000240000004008000020001508000504100000000880000000000000000020000800000804020000008200002000404000010000000000000000000000080020000904010100800010a02900804000080020000020008800800000000000000000000004001800406200800024001000004000100000000400000100000000800000420000a0400000004000100000000000000000000000000000000000000000000000000000000000006000000400000000000000000000000000000000000000040220000000001008800000000020440000000000008000000000004050000000000000000000000000000000000096c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20010000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000200000020020020000002000000000000000000000000000000000000d6d5000000000000020000000000000000000000000002020000000000000000000020000000000040880011010002400080000000040800000000000001000000000000000010000000080400000000000000002010000800000000000000000000080000000000000000000000000000000040000040220010001000000000000000000000000000000804400000100000000000000008000800010100000806000056c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000001000000100000020000004000000000000000000000000000000080000002800080020000080040000040c02000000000000000000000000000000000800000000000000400000000000000000000000000000000000000000000800000000248002000001000300104000000020000000000000000000000000100000000080000200004000000400048080000000000000000000200000084000000000088010000000000000000000000000000000000000000000000000000000000000000000000010000004000000000000000000000000000000000000000000100000000000000000000000100000000000000000000000000000d6c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000c00000000000030000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000014000000000000000000000000000000000000000000000000000a5f3000000000000000000000000000040000000000000000000000000000000004000000000000000180008008000080300000000100000000000000000000000000000000008000000000000000000000000000011200300000000000000000000000000000000000000000000000000200008080080020008004000000000000000000000000000000000000020120036c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000020120000000000000000000400000100080428000004002000000000000000000000000000000000000000000020000000000200200001000400000000000000000000000800000000000000000000000000000000020000000000000000000000000000000000000000102000000000044000004010080000000c040000000000000000000000000000000080010000000000000000000800400000000002000a2008404200048000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000400000000000030000b6c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000030200000000000808000000000000040000000000808800000080000010c00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040004001000c020030000000400000000000000000000000000000000000218100000000000000000000000000000000000000000400000000000000000000000400000000000020002002000b280840000000200000000000000000000000000000000020004000000000000000000000001000000000100000000000000000000000000000000000000000200008000000800000000020000000000076c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000c02c000200480000a000000000000000000000000000000000000020000010c0040000000000000000000000000000280040000080004000c2000000200000000000000000014000100108140400000002005000a10500400000000000000000000000040200000000010004000104000000008000000000400000000000000028000000000000200010000c402000050001082000000000000004000000000000000000080008000480030000102000050900020080800020000004002020920024102d00002000000040280040000c02000000000000000000000000000000000000000000000000000000280000000000000000000000000000000000f6c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000c18000000000030600000000000c18080000000030600000000000c0000200000040000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000028200000040000a0800000100000000000000000000000000000000000f519000000000000000004000000000480480a0000000000002800000000000000202400000000000080000000400090240000000000088000000000000100000000000000000000400000000000000000000000000200008030000000000000020000000000000000000000000ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000282000000400000080000010000000000000000000000000000001010000000000000000000000000010000000000000400800000100002800000000000000000000000002820000004000000800000100002820000004000000000000000002800000000000000800000100002800000000000000000000000000000000000000000800000100012820000004000400800000100002820000004000000000000000000020000004000000800000100000020000004000000000000000002820000004000000800000100002800000000000000800000000000000000000000000000000000000000000008ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000484800000000000000000000000000000000000000555500000000015554000000000555500000000015554000000000000000001846600000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000c00000000000000004000800000000a02308800000000000000000000000000000000000005b690000000000000000000000000000000000000000000000000000000c18000000000030600000000000c18282000000430600000000000c000000000000000000000000000002800000000000000000000000002820000004004ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400000000000000000000000007884262b8c0000000000000750c000000000000000000000000100004400800400000000040010000000000000000000000000000000000000000000000000000000000000000000000000000002e60521090004000000000000000000000003dbf984e64108000001ed5700006e08662f4ff000000000000000046084000000000000063000fb03011400000342c0000000000000000000000003100000004446ffff0100c0080282a8000000000000005085750840000000000000000000000620943ffc00000280c20c8000017b027ab08000000000dfdc0022104083fc040000457ff00007d3e40000000000000044000000cec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00046ad00007cafe000000000000004400000000000000000000000000000000000000000004848000000000000000000000000000000000000006a6a0000000001a9a80000000006a6a0000000001a9a8000000000000000001846600000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000c0000000000000000000200000000004501544700000000000000000000000000000000000c5520000000000000030300000000000c0c0040000000000001000000055550000000001555400000000055550400100441555400000000000000000000000000000000000000000002ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000007d842625ec0000000000000750c00000000000000000000000000000440000000000000000000000000000000000000000000000000131004000000000000000000000131000000000004c400000000084904b00000000000000000000000007bbba0ce67328000005cc0000006e4c662ecff00000000000000000408400000000000006300033032804c0000342c00000000000000000000000030000000044465f7f011440080383b8000000200000000085370840000000000000000000000620953c800000600a0e0cb0000173205df380000000000f1c000000010dfc440000aec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (090000000000000000000001042080000000001007e00004b7ea00000000000000840000000000000000000000000000000000000000000000000002020000000000000000000000000000000006a0000000001a9a80000000006a6a2100000001a9a80000000006a6a000004c21000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000400400022000008b26808a8000000000000000000000000000000000001b050000000000000030300000000000c0c004000000000000100000006a6a0000000001a9a80000000006a6a0000000001a9a800000006ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a9a80000000006a6a4041000021a9a80000000006a6a00000000000000000000000000040410000000000000000000000002842022880000000000000000000000008000000000000000000004012000200000000000008000000000000000000000000000000131000001000000000000000000000000001000000000000058c000000000000000000000000000000007f949442d00000000022a440f374e8ca02358000000000000000004c4980000000000000530000000514120000000000000000000000000000000000000000084400000312a21804000000000008100000510884a0880000000000000000000000023b80000000022a4e0000000002b00eec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000239c00000000456810000000012b2a0000000000000000000c0101a00c00000000061fb00004aaaa00000000000000840900000000000000000000000000000000000000000000000000420000000000000000000000000000000c055000000000155540000000005555210000000155540000000005555000004c634000000000000000000000000000000000000000000000000000000000000000000000000000040024000000000000000000000000000000000000420000000001000014000044051014d000000000000000000000000000000000002e880000000000000000000000202000c0c00000808003030000000000006a0000000001001ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000108003030000000000c05500000000015554000000000555500234084255554000000000555500000000000000000000000000000234000000000000000000000050856020d800000000000000000000001080000000000000000000000130088400000000000210000000000000000000000000000000000000000800000000000000000000000000800000000004023400001c80200000000000000000000003390e486f000000000448a0df374eaec022fc00000000042000000400980000000000000530180000202b610800000000000000000000000000000000000000c64000003109000864000000000280900002009c4a0ac000000000000000009ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000000000804400020000080400000004000804420000802040111000004800004502000000000000000020004000040000000000000000000000000000020800000000004000000000000000000000004000000000000000000000000100000000000004000000800000000000000000000001000000000000000001000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000081480080000002050000000000000000000000000050002000000000000000000000000000000000000000001000000000f1240000000000000000000000042000c0c0005ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c03600000000000040000000000000000000050000000000000000800080040000001000000001620000000000000000000000000028040000800002000008000000208a0000808800820220000000020800800020000100800800000020800000800000820000800000340020820000800800020000000020000000000000058000000000000240008020080808200000000001400000200020858800000000001640000000040058000008000008020000030000358d00000048000228000200000200000000008001400001004040801009000008000000240008200058030201000109600220000000208a0820000020020000100800025000080000100000dec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000211000000400000000000000000031000022402108048000a0000100122000000010800080010004020000000000800084904002000000000000000000006000000000000000000000002004840020000000002000000000006080000000000004030010000000000000000000002040000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000018000000000000000000040000000000000000000000000000000000000020000000000000000800000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000003ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000020000000001f630000000000000000000000000000000000000000000000000000300004000200100000000100002000000000000000000000000004000000000000000000000100000040000004000001000000100000000020000100000800000110001000a1000400000000000008000080000000403000000000010040100000000004000000000200104400000000004020000000200000c000084040041100402000001003003000010040000c0030000004000000000004000006004000104000000000000080000000001000000100000000000800000000000000000000064204800000000100001012003004100000bec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (200000800202000010000428480048100104200000008000001208000400000800001030000040c0090000000200000000008000008010000210010800000000400002000200000008000000000000010008000010000000000000000000008000020000800000008008000000000200000000000000000010000000000000000000048040000000001000000800000000000000000000002000000000000000002000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000002000000000000000000000000000000000000000080000000000000000000000000000000007ec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000080000000000000000000000000000000000000000000000000060d200000000000040000000000000000000000000000000000002000000000002000000000000080020000000000000000000000088000002000000000008000000006100204008000100208000000008008000000000010000000000404008000c0000020001000000000010020000400000010000000000400800000000000000000000800004010080002000000000002000000000230002000400202000000020000000028000000a04000010000000030000100c0000000400000400010000020200000000401000000000004200200100000400000014000400fec040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800400020020421000000000400004000010810000000040820400800000400a100000000080204008000000200000108000200204008000c00204401100100004100408004008000000100000000004000004000004100000100200008004000100100000200000008004000000004004400100000000000000004000000000000100080004004000000100100000000088400000000004010002100000000000000000000000000000020000200000040000002014000000000080000000000000001000000000800000000000000080000000000000040000000002002000000000000000000000000000000000000200000200000008000000000000001c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000024000000000000800000000000000000000000000800000000000000000000000000000000000000000000000000000012f4000000000000000000000000000000000000000000000000000000800000000000000000002000000000000000000000000000000000000000020000000000002000410000800090420000000002000010000000000000000020106000000080000081000000000000000000000000080000000002002000000000000000a000000004400204010000004008100100000004000024030000108c000000010002000400000001080008000002040001080001000080002000000082040080080020001001000000840081c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000880040000000001020030000000000000400000000000000002000000800c200000000200000000000000800000000020004000000008008018000000400010010000100004400000000200000000010000004000400000000100000010000004000000000000000004000000020000000000000000000000004000000100000000000000004000020000000000000000000000000000000000200000000000000004000000100000000000000000400000000000008000000000000000000001000010000000000000000000000018000000000000000000000000000000000000000000000000000000000000000000000000000000041c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000002002000000000000000000000000000000000020028000000000100a00000000000000000000020000a0000000000000000000000000000000000000000000000000000000772000000000000000000000000000000000008000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000020800000000820000000000000000800000000000000002006000000004000000400000000000a000000000000000000000004000000000000000000a0000000001000040000000400004001000000042c000408400040a10000000080020002c000000108200b0000000400010000010020820000c1c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000b4280d0001460000000800000001400020000000850801800800800000020000404280000c000000200200208000000008000000100216200a8201290ad080080020080142000000040005004180004082a00002080000005028040010002000012002002005002080000080000000000044028088000020000a0a0000020020000800000020020000020000000800800000000000022000000000000000000080000000400020004000840800041020020000020044a8001000004000a0001000000000000000000400000000000000000400000080000002010000010000080000000000000002200000000400000000001000140009000000000080000021c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000080200000300000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000001d65000000000000000000000000040021000a0014000000000000000000000000000000080002d00000002000000000100000000000400000000000000100000000500080000000014084c000000005000a0000000000000000000000500c34000000014000800000002800004000020000000000000000502c240000080001400010000800058042c000008014000400010d028000400001900b6002500024c02d00c9000000a1c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000002000000000080000080400042200002080000000000000000200000000008000200000800000000400000000000208000000000004000000000000004000000000000000001101000000000000000000000000000000008000000000000000000200000048000000a000410000000040040000000000800008080000000000000000000000000000001042000100000000000000000000000000000c000804004040001000000000000000000000200000000000000000010008000000000000008009000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000002000000000000000000000000000000880000808900001000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000400000000000000000000000000000000000000000000000080c4000000000000000000000010000100900000000004010000000000000000000000000008000000000000000004008000000080000000004002000000080400000004100101000001000104000000010104000004000008100004000001000000004010a0000020000000030000800100400d0000040000001000000000000000400002010001000000c1000040001000000000e1c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a00080400001240400080008019a00009200000000000668040000200000200000308000810000029200000000000004001e78040000018000800000028000008000000000000000000200000040000000000000000000000000000048021000409000000000000048000000200000000000200000200000000000000400001000604000048002000000000000020022000140020002002200000020000020008080a00000200000000000000008021000000000000020000000008000000000200000000000000008000300000000000000000000000020000008210000008400200000008010000000000000000000000000000000000000000000000000000011c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000080000000000040000000000000000001040008040010008200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000800000000000000000000000000000000000000a18c0000000000000000000000000000000000000010001000000000000000000000020000000000000000010040000001000000000000000000000000000000000400000010000010802330000000000104040100000000000000000000124802000040901d600000c10000000000000009060210000000000242000201188480610091c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800081000040000880800080801048000020010400000000202124008000010000000000000024000240010800030808010820001448000180000010400000000020000040021000082000000040000020000000000041000000000000400000000000000400000000000000048048000200000000000000000000000000002000000008000000000080000001200000020004000048000100000000000088020000c40080000000000001080000040009026040000800000000000000008080000000010000840000020009040800000000000000000a00008100000000000000104000410200040010000804000000100000000000008000000000000000051c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (900012400000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0000c000200020000000000000000000000000000000000000000000000000000000001000000000000040000800000000000000000000040000000000000000000000000000000000000000000000000000000950e00000000000000000000002000000004000088100010800000000000000000000000002000000000000000400082008000008000100000100200040004020008000404100000108080000000000000010200000000000a000001080000000400001080400100414080001840008200d1c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (841000000000c8400088000010000100000000040104000000002000022000080008c21001004100422041040084040c2200049000010000080840200c9010002000001200200010000048000008010a0000000400000008840000000000024000000000000000000000000900000800000000000000000000000000000020008c100282000001200000000800008000000010010200000020000040000000010000208040008400084000400200000200000000000080000001009001000000040000044000200000200000000000000004000000000004000008008000004000000000000000000000000404008000000000004000000000000004100000000031c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0600000000000000000000400000100000004000080000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000400100800000000000000000000000000000000000000000000000000000090000080000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000001dbc00000000000000000000000110010080040004208000000000800000000000000000000009208000200c0000040020000000000010400082000001010000000020001000440000c1000081000002000004000002000000040081002000b1c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010400000000000004000001100040000000000020080150010000000000000000008040000000000110082020020000014020401000000000120000020000001220020000000005420000000520100801000004000000000004820400010000000000000000022000000000000000800000000000c000008004000000000000000000000000000000000000000000000000001200000000000000000000000000008000000040000000000300000000009008000000000001000000000000000001040000000000000000000000041000000240100000500000000000300000000000000000000000000000000000000000000000000000000200400071c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010080000040000000000000000010000000000000000000000000000800000000080001800000002001000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000002000210100000000000000000000000000000000000000000000000000000000000008000808000000000020001000000000000000000000020000000000000000000000000000000000000000000000000000000e5500000000000000000000000000000120800002000800000000000000000000000000004000400400820000000002c0000000000000040000000000200000000000000400000000000492000f1c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000400000000040000800000001010000000000040100000080000000000000800040000000000021010000000100080040000000020030000000000040000000002000110144020000000400201002020010180000000000800008020000130010800000000c00000000000030008000001000000000000000110000000000000400008000010000000000000000800400000020000000000000000000000000000111100000000000c00000000030010000400000000400000000000020000000000000400000000000100100200000000400000000000100000000000000800000000000020320000000000000000000000000100800000000000000000009c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000400001008800000040000000040000000008020008000068000000000000000000e0000012800042600000000200000400000000000808008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000002000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000587a00000000000000000000000100000008020000400200000001000000000000000400000000c00008000000000000000000000000200001040089c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000004200000000400002000100111108000000051000400000000000000000088010000000000000000080000000000000a0000010000000c00000400400000200000000010000008000020020008000000000000a2008000800000820000040228008000800000001000000000004000440400000000008000020000000000000100000000000000010001404008c00000000000000001060402451401000400018000020002800000000001800000020000000001010820000018000000400000002400010002000020000008000000000000042100000018400808210400200000000000420002000002001800062204040800000000011008000800000049c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000c2800880008820081000000040001000000000002001000000000080000000d0000800000000000000000000800001010000800001008000010008020008020800000400024820000820000000000000000040000000000000000000000000000000000000001000000000000000041000000000000000000000000002014000080000000000000000000000000000000100000000000000100000000000000020000000004000000000000000000000000001000000000000000000000000000000000000000000000000000000000671e000000000000000000000000800200008800000008000000000000200100004004800000000000c9c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000800000000000020000000000000000000000020004a2840080104080001000004102101000040000000000000000000001000000000000000000080000001000004004000000100000014000000000000000000001000002000000000000100000000002000202400000000001100403080080140000800010000800000c2040004100000001006000000000000084000800001000000000040001101188100000000000000001080000040001000000000040800000000000000000044000000008020028020400001000100046000000000001000000000000000008000000001100000000100000000100220020200000000000000000040020820029c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800085222004000000008180000048082080240001000002040086004804002082001040000049249400000a0410000100000000001020000212000000000000000000000000441200400002000042800000000040010000441000000000015010040411000000000000000040000000000000000000000000000000000000001000000000000000042001000000000000000000000000404000000000000008008000000000000000000000000000000000001000000000000080000000000000000000000000000000000001000001000000000000000000000000000000000000000000000000000f92e000000000000000820000200020000000000200000a9c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000020040000020000800040000804000000000040008000200200000000000000000424000241000000000008008009000000000100004410000000410410001410010000110004010200000000206008080400008010000c5000440040810000000000802a000000211080080420000090c0000c40080421000808a50010010040000805010000000030000000224832200400000028820008080000090200000c00001008004008030000280801200000020000008000008200a08240100200000020840089002002040040240041080010020084030c20000800000020400004000201008000000044080000040000001002001200000020200069c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (011402000810008010010082000010800000001000010884000000810000000000420000520800280202822000001018090000408000800000000a20000021040200000000012000840001000100000001000400014000000000000010000004000100000000140000800000008000000000000240009000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000004000000000000008000000000000000000000100000000000000100000000000000000000000004280000000000000000000000000080000800000000000000000000000000000000000000000000000000f57d000000e9c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000665a0000000000000000002000004000000000200000210000008008100000000100008000000110000000001000004200000040000000220000000108868001400000000000404001000100000000011000840008000041001400000000800000002000400001040040000011000000001140080000000010000480000000010008000810400108000008000804210000200032040000414800024000000030030100008000000404000000000210018010000040025040080000008000000000040002a0080040000200000008023200090890000010000a200208001005800000000002108004000010204000000000000019c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000280008000000086000000000000000000000008024000100000000c000080a4084040001a0001020018801400000001410024452400040008a140010040102000004000024040010a366088106040000200000000080180000000010000000000000081400000005541040000000400000000000000000000100030800100000000c200008000000000000000200000000000000000000000008000000000000000000000000000000000000800000000000000000000000000000000000000014010000000000000000000000000000000000000800000000001000000008040100000048800000000000000001000000040000000000000000000000099c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000840000020000000000000000000000000000000000000000000000000090e0000000000000000000000000000000004200100a21000000008000000000000000000000000000400000000100000000000000000500000000004104000041020000451051000841009400051000001011000000010000400140020001000001400000000000000100010002000000001000000043000003440200800108000100000010000010000000000200000000002008001000010840008000000001010080000030040001400000200008000001044001000000000028200010000018000200020000000000000040100000004060020600020a00100001101200059c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (280c00010014000000800600000400040820004000044100000080005090900000000100020400000010808000000000140000003002844000080408020042020800c000b00000c2200000001104102284082300090000000000004000020000800001000c00000000010804000000020c000000000004008000000000250208000200000008020000400020000020000000010040040000000000000000000000002000000000000000000000000080000000000000000000000000000000000000000000000000040000a280080000002000000000080000000000000000000000000c0000000000000000000a00020000000085200400000280000000000000d9c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000200000000000000000000000000c000000000000000000000000000000000000000000000000000000000000064c300000000000000020800000000800000000000810000000000002000000000000000000002100010000000801000000020410020008000010400401000004000100012c044800040023300004001000044028000002a000003101010400040001000000000000000d00000030000000000000000000000000030000020c04004400000000004000404000000000020100000008001021000082c080a0000010200024000000000000c00000000000000001010200200280000000100000000008300000300000001000000000039c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000280050000000000000200030000004000000000000000000000000000006c02020000002a8080000010002000000000800000000000000001a000000000000001000000000000c00000000000001000000000000000000000030000010000000000100c26000180000000000000000100000000800000800000080000300002000c0200000000000000000000011014200000c0000000000a00200801002000008000008020000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000001020000000000000000080140000000000000000000000000000000000000000000000b9c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000800000000000000014000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8fb000000000000000100100000000402000000000000000000000000000000000000000080000028000008020000000000a004400000000220000000000000400001000000000000050030801004000001000000000040000000804000000020a4a05080840420000000000000020001000000c00080400030001000000000031004800400000700c2009030000504880000000080000000000012028200000000000404000000000c0010000000000000011102002800040000000079c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000400000000000000000000000000010002000000000000000000000000000000000000008000000040000000000010401000000000000000000000020000000000000000008000000000004080001000000200000800000000040000030002008002000040000030000000080000000000000000030000000000000000000000002000000000000000000000000000000000020010000000225080000021002b4000000828000c00000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000008000800040000000080000000000000f9c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002000004000100000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000260b000000000000000000225000000410085b4000000000004000000000000000000000000400010000000400094000000010042d000000001002b0000000010000000000000400100000200000000000000000000000100000000000000000000800010048000000000000000000000000008020010000000000400002001002400880000000100000000001004c40090000000000000a00000028005028000000080a0000010800000005c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001400000000000050000900008000200040080000000000000000000000006005001000200000000000000000000000000000002000000000000000000000000000000108000000018001000000004000000000002000800000000000040000000000000000000000200000080000000000000002000000020004000000000000000000006000000000040000000000000000000000044001808000008000000010080040810014000000002805800000000001404003000000000400000080010040000000800001000001000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000085c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000801000252144000000080088000000000000000000000000000000000000000000800200000000040008000000000000000000000000008000000000000000000000000000000000000000000000000000000000a82d000000000000000200400000000420000000000000000000000000000000000000000000000000000022008000000000080800000000008001000000000000000080000000000000140a0008000000000000000000000000000020000000000000800000034000400000020000000000000000004080000000000010004000441080000400000102000000000001090005000000a0000045c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (008808000140000210642100010000004009004400000094200010001100044040480040080800000000000001002020088820801004000100020000000000000080000000000000000000000000000000000000000088880002804080044000808000000000004001000000000080012000800040100080442000100020104004081008000804000080040802000080000080040000808004000000011004000000000000000000042000002000002000100020000023020014000000003002800100000020828005001013212a102000885284186030202182142180008000000800000000000000000000000000000000000000000000000000000000000000c5c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000009010041820400000000800800000000000000000000000000000000000000000000006000000000000080000000000000000000000800180000000000000000000000000000000000000000000000000000000009ef300000000000000028028102102100806284084084000000000002000000000000001000220012020402100c04084084024012102102102000c84084084004040009084401100c00146080004000091090400000000100400000000080808002220a8083041080010001008000080000001000000000000000020001401400026100000000025c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000408000200010000001200206000004000086880000500202008061000100000040080044000008102000100000000220202000080008000000000000000921200008608000041101000200000000000001000000000000000000000000000000000000000008000201000280000020008080100000000040010000000002000200008000001000000400002800008020000010040000080000800004040000000201000200018000040000200000040000000000000000000000000000008080000000001000202108100000000000000001800002209200000006142002100100085185286000600002166000000000000000000000000000000000000000a5c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000040000000000000000000000000000000000000000000020001000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000001aab0000000000000000000610200210000098408408400000400010200000000000000081000000202000000218408008400008210210210210088008408400404000108800100090224628000802001100000000000010200001000000001400200020080440180000000000000280010000000065c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000420001800002000100000000000000000000000000000000000090080000002000000000000000200080000000000000001000000802000040400000000000080000000000000200000000000000000a080400010100004020000000000000000000000000000000000000000000000000000000000000000010d00030014000000011000000000000000000000000000000000010000400802000200000000000080000800080000000001000410020000000002000000000000020000100006000000000000000000000000000020018020002000000000100410000000000000020002000000400000084000080010000400102402000000110000080000e5c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10040c40c00002000030930080000020c00c0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000424c28000000020020000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000a2660000000000000008000000000000050000000000000000000000000000000000000000002000000020000000000000000000000000000040000000000000002000080420090200002001000008000000020000000000000004000000080051000015c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2482020000000000040000000002200000400004000000000000000000000000000000400000002000080000000002000000c000000000200204000000008008000000000040000080800001000000000000000000003040001200040000000000000000001000040040000800000000000000000000000000000000000000000000000000000000000000100000000800000004000040004000000000000000000000010000000040001020000000200000001000000420040000000000000000000000000000000000000000000800102000000a000000000000000000000000000000000000000000000000000040000000001000000000000080010000000095c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (030400000000c80500000000000020200500240160d210080140008408404001000210600000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000800000012490000000090090000000000000000000000000000000000000000001000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f70200000000000000000000000c00c00002000030030000000000000800000000000000004080000000200000400030030000010000c00c0000000003003000008000203020200040008080400000000055c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8400000000808040020080200200800004000a00c40000000000230004000000080420802284082044800020000000000000000001002000000000000000001200000022428000040080090401000802040408000000008000010000011200800000000011040120010000401000000000000000009020010840040010000200000000000000000000000400000000000000000000000000000000000000820022030010800500000800000000000000010000000000000020000000400001000400000000200020421010000000000000800200000000800000000000000040000808000008800000000000000000800300008020000000000800200000002000d5c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000280000000000000080000010c18280000000030600000000000c18280000000030614864251480c1852190945203001486425148000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000c18282000000430600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000043170000000000000003402400200214141480008408400000000010200000000000000000802000000040120010008008405001000210210000040008400035c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0521909452000014864251480000521909452030600080000010c18282000000430600080000010c1800000000003000008000001010028200000040000000000000000028000000000000008000001000c18282000000430600080000010c182820000004000400000000001010800000000000400800000100000020000004000000000000001002820000004000000800000100000000000000000000000000000000000000000000000000000000002820000004000400800000100000020000004000000800000100010000000000000000800000100002800000000000000800000100000000000000000000000000000002800000000000000000000000b5c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000001d470426400000000000000000000007d2b600000000000000cf535555052ba00001555400000000055553090a000015555303774d9155554e0ddd36444849383774d9112000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000eaea0500100183aba8000000000000000000000000000000000000000000000000000c0c00000000003030000000000000000000000003030000000000000000000000000000000000000000000000000000000000aacc0000000000000000014864251480000521909452000014864000000000000000000000000080000010000075c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (70000000000000000000ec0000004011000004c0ddd36440001383774d9100004e0ddd3645555400004011055550400100441555400004011055550000000000000000036131000000117e0aa2000c00000000000000000d600000000000000920000eaea0044011007aba8000004401eaea00040112b00000000000000000018800000000000000021021010100000115fc00000000000000000202201189000000000209d700000000000000df0000000000000000000000000000000000000030000114020087fffc000063046000000000622200000000021088ffff0000000000c0f0000055421000040884000000000000008063000000400000028c0800f5c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000005463000000400000000038000000000dd476201000000000000000000000007b2b20000000000000147726a6a0518200001a9a80000000006a6a3090a00001a9a92038f718e6a6a498e3dc63848492638f718e12000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000151505001001805454000000000000000000000000000000000000000000000000000c0c00000000003030000000000000000000000003030000000000000000000000000000000000000000000000000000000000576e000000000000000001303774d910c0c4e0ddd36440001383000dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000012038f718e0c0c498e3dc6380001263880000000000000000003c000000000000000480e3dc63800012638f718e0000498e3dc639a9a80000000006a6a0000000001a9a80000000006a6a000000000000000003033100000051760ba2200c00000000000000080d600000000000000540000151508400000005454000004400151508040003bc04c4000000000013118c000000004c400002102100000000031b9c0000000000000000062410118100000000030bf300000000000000df0000000000000000000000000000000000000030000045a2008551540000430460000000006222000000000210885f7f0000000000c0f0000008821000010484008dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010000000000001002270100008800000000000000082a84840000000000000000000000000001d19000000000000000000000004cdd8000000000000000812006a2526200001a9a80000000006a6a0245000001a9a990c200c726a6a66308031c9a9a998c220e720000000000000000000000000000000000000000000000000000000000003100000000000000000000000000000000000000000000000000157163008180545400000000000000000000000000000000000000000000000000000000002020000000000080800000000000000000000000080800000000000000000000000000000000000000000000000000e79b000000040000004dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000169c00000000200000000190c200c72000066308839c8000198c200000000000000000000000000000008000064308031c8000198c200c72000066308031c801a80000000086a6a4041000021a9a80000000086a6a0000000001a9a80008d101031000016a0725000000000202000000005da00000000000001080800001500010000205454000008408151500002003980000000004000013100800100000000000015022000000000213d800000000000001505023202114000000000084f40000000000000000000000000000000000000000000000000000000c1110142230a8000000005704000000000002230000000001108c00cdc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00005224900000000002634000000001118d00000000000000000000000282b70100009c00000000000001012b21210000000000000000000020000002201200800000000000000000004a948000000000000000030c0556d15200001555400000000055550205400001555580c883064555561b220c191555586c88726400000000010800000000000000000000000000000000000000000000000031000000000000000000000000000000000000000000000000c0ea71234080a7aba8000000000000000000000000000000000000000000000000000000000004200000000000108000000000000000000000000108000000000000000000000000000000002dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000009eab00000000000000000180c883064000061b221c990000186c8800000000000000000000000000063090000603220c190000186c883064000061b220c193015400000210955550023408425555400000210955550000000001555400089201901005017a0f25400000000002000000009da00000000000001001900c0ea00816004a7aba8000008421eaea008160033c000000000020000000080000804000000001122a00000000033fbc000000000000011000e2202116c00000000005a50000000000000000000000042000000000000000000000000000000c45000162308c000000adc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000100200000000000008008248010000008000000000008008000000000001001000000000000000000000000200000008000008200000000000000000000000000000000000000000000000000000000000000000000000000040000200100000000000000200000000000000000000000000000000000000000000000000000000000000200001000000000000400000000000000000000000000010000000000000000000000000014000000102000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b790000002000004000000000000000000000000000000004000000000004000002002000004000000100000100000000000000000800000000000000000000000000000000000000000800800000000000000000000000000000000000800800000000000000000000000800000000000000000800000000000400000000000001000000000000000000000000801000000000022000000000800808000000000020000000000000000001000000000000000000001000000040000028200000000200000048000100008008000000001000edc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000002000000000000200000000000002000000000030000000c000000080000000000800001001000000000000000300000600000000000020008000004000000004000000000004000000000000600000000020000000000000100000020000040000000000000000000000000018300000000000000000000000000000000800000800000000000000000000001000000000000000000000000000000000008000010200200000000008000000000012000000080000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c75d00000004000000000000000000000000000000000000000000000000000002000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000002000000000000000000000000000003000000000000040000000000000010000000000000000000006010000180000000006000000000000000000000000000000000000011000000000000000000009dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000100000020000084100000000200000048000000004008000000002000000000000080000000000002100000000000084008244004000004000000000084008000002000000000000000000000000000000000100000010080000200004000000004000000000004000000000000000000000080000000000000100000080000000000200000000000000000200000000000000000000000000000000000002000002000000000000000000200000000000000000100000000000000000000020000000800800000000020000000000000000000004000000020000000000000000000000000000000000000000000000000000000000000005dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dba10000000000004000000000000000000000000000000004000000000004000208008000404000000100000100000000000000000400000000000000000000000000000000000000000400800000000000000000000000000000000000800400000000000000000000000000000000000200000400000000000000000000000000800000000004000000000002000000000000080000000002000004000000000080000000000000000002000000ddc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100000000004000000000000000000000040008004000000000000200000004008004000000000000200000100000000000000000000000004000000008000400100000200004000004000000000000100000000000000000000000000000000000004004008000200200000200008000000000000000000200100000000000000000000000000000000008000008000200100100000000000004000000100000100100000000000000000000000000100002008004000000000200000000000000080000000000100200000000000000000000000800000020000000000000000000000000000000000000000000000002000000000000000000000000000003dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041d20100002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080004000000000000080000004000002000000000000000bdc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000080300004000008000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000300000000004000000000000000000000000000018000000000000000000200000000000000000000000000000000000000000000000000040000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000100000000000000000000000000000000000020000000000000000000000000000000000000800000020000000000000000000000000000400000000000007dc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000400000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000200000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000008d19000000800000000000000000000000000000000400000000000c000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000006000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000080004000000fdc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000d200000000000000000000000080000000000000000000000000080000000000000000000000400080080000800000002000000080080080000000000002400000000000000000000000000000000000000080002000000002000080000080000000000002002000000000000000000000000000000000080080080002002000402000080000000080000900002002000200000000000000000000000000000080000080002002002000000000000080000000000002000000000000000000000000000000000010080080000000002000000000000000000000000002002000000000000000000000000000000000000003c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a0fb010000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000400000000000000010000000000000000000000000000000000000000000000000000200000000000000000000000083c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002000000000000000000000000000000000000000000000000000000820000000000000800000000000000000000000000000000000000000000000000000000000200000020000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000220000000000000000000200000000000020000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000043c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008000000200000200000000000000000000208000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000052b00000000000000800000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000208000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000408000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000820000000000000200000000000000000000000000000030200000408000000000000000000000000202000000000000000000000000000000400000000000000000000000000000000000000000000000800000000000000080000000000400000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000400023c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000800000020000020000000000000000000020800000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000008000000000000000000000000000000000000000000000000000000000400000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000009a730000000000000000080000000000000000000000000000000080000000000000000000080000000000000000002000000000000000000001000000000000000000000000000000000000000000000000000000a3c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000040000000000000040000000000000000000000000000000000000000008000000000012400000000000008000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000080000000000000000000000000200000000000000000000000000000000800000020000000000000000000000000200000000000000000000000000000000000000000000000000000800000000000000000000280000000000400000000000008000000000000000000000000008000000000000000000000000000000000000000000063c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000026980000000000000800080000100000000000000000000000000080000000000000000000200000100000000000002000000000000000000001000000000000000000e3c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000820000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000208000002000000200000000000000000000000000000000000000000000000000000000000000000008000000000000200000000000000000000000000000000208000000000000000000000000000000000000000000008000000000000000000000000008000000000000000000000000000000000000000000000000000000000000008000000000000000000200000200000008000000000000000000000000000000000000000000000013c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040a0000000000000000000000000400000000000080000000000000000000000000000000000000000000008000000000093c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100053c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022930000000000000000000000080000000000004000000100000000000000d3c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000040000000000088000002000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000200000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000200000000000000000000000000004000000000000000000000000000000200000000000000000000000000000033c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000800000000000000400000000000000000000000248000000080002000900000000004000000000000000008000000004000000000000000000000100200200000000000000000000000000000000000000008000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000060000000000000200000000000000000000000000000000000000000000000000000000f5250000000000000000000000b3c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000088ea000000000000000000000000000010000000002000000000000000000002000000000080400000000000000000000000000000000000000000000000000000000200000000000010000000000000000000000000028000000000000a0000000002000000000000000080000000000003000000000080008000000000000000000000000000080000000000000000000000000000000000008000000000000000200000000000000010000010000000000000000008010000000000200200200008010200000020000800200000000000010000010000000000008600000000000000000000000000000000000000000000000000000010000073c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000400000000010000000000000000000000000000000000000000000000000000000010000000000000000080000000000000000000000000000000010000400000000000400000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000f3c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000a1710000000000000000000000000000100100000040004010000010000000020004000000800000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000400000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002001000000000000000000000000000000000000000000000000000000000001000000000000000000000100000000000000000bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000008100000000004000000000004080000200000000000108008000004000000000100000000008004000000000000000000000001100000000000110000000100004008000000200200008000000000200200000100200000100200008000000000000100000000000001000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000001000000000000000000000000000000001000000000000001000000000000000000000000040000000000002000000000004000000000000008bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000400000000000800000000000000000000000000000000000000000000000000000000000000000009dbe0000000000000000000000000000004200000000008000000040000000000008000000100000000000000000001000002000000000000000000000000000000004000000000000000000000000000000000000000100000000000004000000000000000100000000000000000000000000000000000000004000000040000801000000000040000000040001001000000000000000000001000000000000000040000000002000000000000000000000000000001000000000000040040040081000040000000000000040040080000000000000004bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8800000000000000000000280000008000000000000000200000010000200000000000008000008000000000000200000000000000000000000000000310200400000000040000000400108020000400000810000000000000208000008008200200000000008028800020008000008008000000000000008000000000000000100000000000000000008000000000000000000000000000000000000000020000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000080080000000000000000000000000000000020000000000000020000000000004000000008200200cbc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000200000000000020000000040021000000000000000000000010000400000000000000000000000000000000000000000000000000000000704f0000000000000000000000000000002100100000000010000054000000000000000000082000000000008000001000002000000000000000000000000000000000000000000000000104000000000000010000000000400000000000000000000000000080000000000000000000000000000000000001002000000020000800800000000020000000020000800800000000000000000000000000000000000000000000000800000800000800000000000000000000000000000000000000020000002bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000200040000002000000000000000000000000000000000000000200000000000000000008000000000200000000008000000000000040000000000000000000400000400000000000010000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000090000000abc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000380000000002000000080000000000080000000000000000000000000000000000000000000000000000000000000000000bb1d0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008001000000000000000000000000000000000000000000000000000000000000000000000000000000000006bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000010000000000000000000000000000800000010000400000000000000002000030000000000030000020c02000000000000000000000000000000000000000000000000000000000000000020080830000000000000000000000420000800010000000000000000000080000000000000000000000020000020000000000000000000000000000010010000000000000000000000000000000000000000400000000000000000000000000000020000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ebc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c1c6000000000000000030000000000000020020030000c00000000800000000000000000000000000000c008000000000000000000000000000000000000000000000000000000000000208000000000000000000000100004000000004000000000100000000000000004000000000000100000000004000000000000000000000000000000008001000000000000000000000000000000000000000000000001bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dbc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bbc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007bc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fbc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000087c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000027c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a7c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000067c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e7c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000017c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000060070000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000097c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000109240000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000057c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000fc7500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001092000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024502550a00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000037c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000014000000000000000000000000000000000000000008e170000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002550a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b7c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10016000000000400504020000c020140000000800005920800800020800000820000005800000800000020004000800005020000002800800000000000084400420000000000804000000000020000800000110000000000404800000000800800000840080080020000000000000020820000000800020800000800000008000000000000000800000000000200000008200000000000900000000000000000800000000000000000000000000000000010000000000000050000000000001410000000000000000014000000000000000000008000000000000000002000000050000000000001400000000000000000000000000000000000000000000000077c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000020020000000000000000000020020020000000000000000000000000000000000000000000000000000000000000000000319400000000000000000000000000000000058400000000080200001000000000000040000000000001000001008000000001000000000000000008800800008008080200000008000000200000000000000000000000000000000000000000200000000200200000009400000200008000200a002002000080400000000000800000000000020000020000000900020000000020004000000800008820000020002000000000000080000000010144000420008005a00020000880000800020800800a2092000000f7c040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08002000000000080000000000400000000001810000000200400000600000408240600801080000412008000008080000002048840401221000000050c0041808000000000000040100000000000001048c2000430000122004400000004880080060000120000000400004080010010000000c000a0100106020080002002000000000700004090000000200800008000000006000000000000c0240000000000600000000000018000100000000601000000000000200000000000000080000000000802000000000000001040000000002800000000000000000800000000000000000004000000000000000000000000000000000000000000000000000000fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000080080000000000000000000080080080000000000000000000000000000000000000000000000000000000000000000000d17c0000000000000000000000000001000004020000000000100000000000000000000000000000008000000004080002000000000300000000004000040000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000c0000000000002000000000000080400000000004010010000000100000000000004130000000000500004010000000000000000000004000000000000100000300000004000000000004008fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000400000002000000006000000000204004000106200001420000000080000000400000002290000080400000000006008002100000008011030000440c08000010000000000000000100000008108000000000000000c201040000000840040000000021020080000000000000040000110001001080080000060000000000020000800800004044100000024001080008000000200000000000000000040000840000000000000000000000000088080000000001000080000000800000000000000200000000000008000000000000000410000000008000000000000000000000000000000000000000000000000000000004fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000008004000000080008000000004008004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a32500000000000000000000000000008000000000000000000000001000000000000040000000000081000001001000040002000000000000000002002200004008000100000008000000280000000000000000000000000000000000000000200000000100200000008000000200008000002200100200000000000000000001001000000000000002000000000002000000100000004000040000102000002000000000cfc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (121020400800000010008000400400000400000000010000008010040800001000000000a20090010008400400000014220a00521200a010284000c00000200001100280008000010000002008000000000104000024020210209108408004008284000200000200000200100008000008200040004400100104008108008000000004a000080040881000040000100181001000001080041080000000000000002000000040040080000080000080040000040480000000002001000000080060080000000000820000000000040000020020000040000000080000080000000410210100000000800000800000000000004000000008004000000000000000002fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800000000000020000000000000000000800000000000000002000000000000000000000100000000800000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000063c200000000000000000000000000000000008000000000080200000000000000000000000000000000000000008200000000000024000000004008001000000000080000000000000000000000000000000000000000002000000000000004000008000000000000000000000000000400000000000004080000000000000080000000001042020000000080081000000000afc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000104002000000000000100000000c040040100400001010002440102000100080080001002000800000002000000002400080020080002300000080004220000008060008042200021000000080000000000002180002000020080000000000040080000804040088001000000000240000000000080000004000000000000000200044081000003000000000000000020000000000201000000000000000001000000000000000000000200000000000000000000100000000000000000080000000482000200000000000000008000010000200000000000008000000000000200000000000000000000000000000000000000000000000000000006fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08000000082012010000040080000080024000000000400800000400400000000000000000000080080000000000140040000080080080000000840a000000008000280000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000021aa00000000000000000000000000000000008000000000000000000000000000000000000000000000000000000400000000000010000000010001000800000000000000000000000000040000000000000000000000000000000000000000000000000000000000000200000000000001000000000010080000000000000000efc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002010000000000000000000000000000000000000000050000000000801400000000000050018004000000100024000020000000800800000020000021010a8000000006000b420020821020000800c00040021400c30000c002d0800200001020000020020040a8000082000000000000000002000080480800202b420a0080080085000002000002a000020000000800000820000000000000020800850a00800000001620002a00840ad025080020100a02001000042080082180000000000000002200000080080000000000000080080080080480082000002002000000080080080008000140000000200005080000010010140180000000080000001fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000020000000000004001000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000100000000000000000210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000cfec000000000000000008000020000000000140044000000005000300000000000000000000000000000000000140229000000000400000000000150808000000000000040000000000000400000000000000000000000010000000000000080000080000800000965028000000009fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000004000410000000000004100000000000080000000000000000000100000004004020000000000800000000024020000000000000400000000508000120000800a01a000000000000000000000000400201000000000000000000000000000010000010000000008000200000000000000000000000000003008000200000000000400000c0000001010800800000800800000200000000000100084080120000010000000100000000000000000000000000000000000000000000000001000004000000000000080000001000400000005fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0830220000000000000000000000004000000000000020000000000804980000000000000000002000000000000000000000080080280000002000000000000000000000000000000000000000000000000008001900000000000000000000000000000002000000000000400000000000000000000000000000000000000000000000000000000000000100082001002080000000000000000000000000000000000000e918000000000000000000000000000000000000a0000000000001000400000000000000000000000000000000000000000008000000000000000000008200000000000000000000000000000000000000000000000000000000008000dfc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000002000000000000000000408200002000000000000008000000000000000000000000080018000000000010000000000000410000020000000001000000000000000000000000080000800000000000080000000000002040000000000008000000000100000080416800000100000000000200400000000002100000000218000480e000000000000000400208000b06480000000000000c00000000001000000000000000000380104012200000000000082a0003004080206400802040000000004080081080001000000001002000000080001040000000000000000000080020000002000008280000000003fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000008010400000000001040000000008000000000000000008000800000000000020000000000000000008000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000080000000000000002100000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000001e2b000000000000000000000000000006980480402020000000010480000000000000000000000000000000000080c1000000000000200000000000009200000000000000000000000000bfc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000002000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000020810000000001000000000000000000000400000010000000000000000000000000010001200000000008410000800400000400400004004019004000000000000400000008000404800080000000000000000002000841120000000000000000000000001000000000000000002002004044000000000000104000000020a0500100000100004000904000081000001081080000100008000080044080200000000007fc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0820000520040080000400000400000000000000000000404080000000000000000000020400000000000000000000000010800000000800020000000000000c0000040000000000000000080000000000001000000002008002004000081200000000000040000000000000000000000000000000000c000000000000000000000000040100000000801000800000000000021000040000000000000000000001000040000000000000000000001400000002004820000000000000000000000000000000000000873900000000000000000800000000000000048000000000000000000000000000000000000000000000000000008000000008000000000000ffc040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000c00000000000000000000000000800000000000000040800000000000000000000000000000000000000000000000000080000000000004000040000100080000000000000080000000000000000000000104000000000000200000000000108000000000800200000001000000000000000000000000000020000000000a02001000000040010048a0100100000000001000000010c20008810100124025112200008000000080000100000800200008400000000020000001004082024e02000000000024040900002044000000000020000000001241008100108000020020000800010010e000021040021240000022000444000208000002040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004101000000000120801004020001000000010000000050000000000060400000000000000000000009000000000000000000000000000100000000000020000020000000000000000000000000000000000000000000000000000200000000000000000000000000001000480000004040003000000100000000000000000000000000000000000008200000000000000001048000200000048200000000000000000002000000000000000000040000000000000000000000000000000000000041000000000000000000000000000000000000000000000faa50000000000000000800000080800000008c000001000000200000100000000000000000000802040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (482000000000000000000000000000000000000000000000000000492000000000004000000000000490000000000000000000000000000000000000000000000000000000000010000000000000c000000000014920000000000000000001000000000000000000200000200000000000004000000000000000040200000000001240000000000000000000000000010000000000000200000200000000000000001200000000000000000000000100208204208000000100002000000000001000000000000000000000040800000000000000000008000c89600000000000000000000200000000001100000000000144808000040000000001000000000000402040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000201140000000002084c0001000400010111000000000c0000408008002010000000000000000000200000010000000000000000000000000010040000040000001000000000010000000000000010000010001000000000800040000000000001010000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000210100000000000000000001000020000000008200801000000000000040000040000000000000080000001000080000000000000000000001000000004000000000000000000000000000000000000000000413000000000000000000200000000000040000000c02040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000810000000800000011010010000000040000000000000000000000000000000000000001010800000000000000000000001000900000000000020000000000000000000000000000000000000000000000200000000000000000000000000000080000000000000000100000000000000000000000000100000000008400000000000010040200000000402000001000000000000000000000000000000000000102000000800000000000030000000000000000000000000010100000000000c00008000400100000000000000800000000000100100000000200000000000004030110000000000400210000040020000000002000000000202040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010040040420400000000000461e00010010044001022080000800000000410810008000800018000000020000608080008c4000000001000000800000101860000000128004006028400500a44000000080000000000000010000100000001000000000000000010000000000010000010000001c00000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cd4400a02040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000052280000000000000080000000000400100004000000080000000080000002000000280000000000200000000000000000000002000004000000000000000000000006000000000000000810000000000000000800000080040000000408000004004000100000000008000000000000000000000000000000000010000000800200000000008040000020400000040000000400100000000000001000000000000040000000000001001000000000000000000000000020020044000000020108040400101c00200004140000820000040c01a0020081000008041c805252e00200000000010000010030080c00800000602040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000001000000002000040008040a00020000000404004000000000000101000000004000001009410080200000200010000400000901610000004001410000c01040101010400000000001000802000000000080040020000000040000000080002000200000000080004000310100200000004000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000008000000000040000000000000000000000015000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000800000000000e02040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000001000200000000000000000000000000000000000000000069770000000000000000000000000000000014000010428080000610000000020040000000000000020000000000000000000000000004000010000000440000000000080000001000200082000000000000002800000203000000008000000004004000100000000020000000800000000000000000000000000000000000010000040000088108000000000100000000080000000000000080000000000000000000000000000001002000000000000000000000001000000000400000000008050100000101200000008000100022000000000200080000400040000000102040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10840080001200000008810004100420800005001004000000088810110030105400c00100810000000c40100000000810200010048008112004080800002000000008211008001005400820042010082012000901000c0010010010400400002610000008200010000000000008000420240208800080000080201004000a02004000000404000000000080220080000000000002000080080082080000000000000000000000000000000000000004000000000000000400000000000010000000000040000400010000000000820805000020000000002080000000000000000000000000000000000000010000000000001000041000000000000000000000902040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000080002080000000000000000000000000000000000000000000000000000000000000000000000000000000000000093e800000000000002000800000000010000004020000a0101000080000004010010100000000000010000080000480002000008001000000000040000010000000000200000000400210208000000000000002000000102420000000000400000000020000000100040000001000000000000000000000008000000000802004820080000020004020080120402200830400100000000000000000001000000000001000000000000000000000000000000000090002040440000200040040000004109200202000050004000502040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0104000000800000000810000000000202008200000200000040021000a0100000002004002004080001080048100010002800000004000001000000040000800000002000180000004000000000020000000081500000040001040080800040001068818008800021a0400400400000000010400001128100000008000000224010c1002081000000004080000000001010002000020000000000000000840000000000010000000000000000200000000008000000000000000000401000000010000040000041000000000001000000000000000000000400010000000000000204000000000004000000000000080000000000002000000080000000010000d02040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000008000000000000080000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000ddae0000000000000000080000000500080001400000004000004100200000000008200000000000200000000000400000000000001220000000000408008000000000200000000000141000000000000000000000000200000000208001000000800040100000000000200000000000000100000000000002000000000000000400000000000120008000000008c00000440000100000000040000900000000040020000008000000000100000000000000000228080000000000302040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000a0800020100000800001800c000600021048060204000004014c0004000003020009100000002000000010000800000000020082020080800000800000008100620c00000000080000000080000000000000020000800000006080280800000000010000000000800020040a8200008010800012000000c208028000000000000000080890100820800080802000000020000010010000000000000001000000002000000020000000400000080000080000000000002000080080882180000000004000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000820a00000020000008000820000000b02040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000400000100000010000000000000000000000000000000000000000000000000000000005000000000000000000000000008000000000000000000000000000000000000002f870000000000000000000000000001000000202200000009034000200000000200000000000000000000080201480202400000000000000000040000010000000000000000000000080000000000000000000000000000000000100000000000000000000000080100000000000000000000000000000000000000200801000820000000028000028000020400220a30000180000084008000000200800200040000808000200000702040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (330080000000000002a000000280800420000000100800040200001000010008000040000800804020020001040000024000000900000040000030000000000002101403400800800100000000010000400002c031000800000000010200000004000040000000000000000000030030c05020000000c0408001000000c000c0088000401204609040000000001024000001400000000000820010000800004000050014020800120020000080008000000000020100030100000000000800000000420000000000000000020000000000000000000000000000200000000000002000000000000080000042000000000001000000000000000000000000000000f02040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000020001404000000000000000000000000000000000000004004800000000000000001400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020200000000000000000000000000000000000000000000086fb000000000000000000000000020000002048a0a100000200082000000000010800000000000000000000008000008100000000021a000020000408848c0000000020000003000000034000000000000000000000000000000000080400000a400280200000000084100000000000000200000000000000000020000001000000000000048014500300000406aa0200000440000000082040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000002000038000000080100000020004000000000000000000000000000000000000000000000000000a00400140800000090000000140a00080400028640010000000000000a80a00000002000006200008402080000000085000000000000000400000000228c800800000380020001000000000000000000000000008000004000800000000100000140000008002000040000800020000000050404000800000200001102000000008000000000000000000020000000000000000100020000000000002000000000000000000280000000000000000000000000000000000000000000000000000000000000000000000000000040008000202800882040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000004000000020000000000000004000000000000000000000000000000200000005405400000000000002000000000000300000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000022f90000000000000000000000000001000000004405000021401404000000000000000000000000000000000020004000000000000000000000000000000000000000000000000000020080000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000482040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000001000140a00000000028000000000000a00040000200000000000000000000000000000000000000000000000000004000000000001000000800110002000000000000400000100210104200010000140000000005000100020000002000a0000000020000000000000000000000500008000000000000200000000000000000000000000000002000040010000000001000000901000010002000020011000208000100012a0000400000000040080010000010000000000000000000000000000000000000000020000000000000000000000000000000000008000000000000000000000000000008000000000000000000000c82040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000280280002000000000000000000000000000000000000000000000040000000200000000000000040000000000000000000000000000000801000040040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000b6a4000000000000000000000000000000000020400400000000000a00000000000000000000000000000000004000a000000000000000000000000000000000000000000000000000000000000000000000001008000000000000000000000000000000000000000040000002000000000000282040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000028004000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000010002000000000000408000000190002000020400000140000000000000000000001140000028100000000000000000008000000080000000820000001400000000020000000000000000040000000800040000000000000020004000040000000800000000a90000100002a000004000000020000004000002000000000000000100000000002000000000000000280000000004000000000000000000000002000000000000200a82040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000800040008000040000800201001000050030000000000000000000000000000000000000000000000000000010010000000080000000000000000000000000000000010008000040000000000000000200080000000008002000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000009c31000000000000000000000000000082200000100400a0000002d001000000000000000000000000000006002000140a00000000000000004000000a001400000000000000001000000000000000000000000002000000000000000000000000682040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000400008002000000000000000000000000000008001000000800000000000000000000000000000000200020000404001004000200000040000004000000404000100040000000000000000000000000000000000000000080010001002000040900042080000040001004000000080100425000428000080022002400120100100404000100000082000100042000000000000000080800044a000000040000000040010000000000000000000000010040000000000000000000000200100c20044030810240000840089028205110c0000002000100011004042101028000000000000000000000000804000000000000000100000000808000e82040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000004000000000000000100000001800000000000000000000000000001800006000180060100100000000000000000000000000000000000000000000000000000010000001001000400008000000000000000000000000000000000000800004000000000000000000008000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000c4d600000000000000000000000000010080000008011040010006400a00000000000000000000000000000c0080000804800000000000000040100008000800000000000004000800000080000000182040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08000800000000000000000000000000000000000000000000000000040000000000000000000000000000080000000000000000000000000000000000000000002000000004040010040002000000400000040000000002001800200000000000000000000000000000000000000000800000000000020409000000808000000000040010001001044640000000002000200004001a0180000000100100010000020100008000000000000000000800000200000006000000016000800000000000000000000000014200004000000000000100020210010000808a01828000000028800820110800001400100280000804020281804000000000000000000000982040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000200800000000000000000000000000008000000000000000000000000400000000000000000000000000000400008000000010000000009001000000000000000000000000000000000000000000000004000000000800100000000000000000000000000000000000000000000000000000000000000080000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ee750000000000000000000000000000814000000000104000000600060000000000000000000000000000000000000804800000000000000000100000582040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800800000010000000000000000100800000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000004000000000000000000000000001000000000000000000000000000000000000000020002000080000800000000220040000000000000040020000401000000000000001000000022020000000000000200000002000000800000000000000000082000000000100010000000000000000000000000000000000001200000000000080800010000000002000000400080001080a020084800000000000000000000d82040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80010040000000004820080000000002000000000000020000020000000000000000000040000c000000000000800000000000000000000000000000000000000000000000000000000000000000004024000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000004e420000000000000000000000000000004200000000100040000000080000000000000000000000000000382040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000020000000000000000000000000000020020000000040000000000000000020000000000000000000000000000004000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000010000000000000800000000000000000000000000000000000000000000000000000000000000800000000202040000000000000000000000000000008000000000400020000000020000100008000000000100000000400000000000000002000800000802000000000000000000400000000000000000000000800000000000000000000000030000204004000c00b82040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000001000802000000000000080002000000000000a820000820002000c4000004100000020288000000040000000000000000100000001000000000000000000000000000002000000000000000000080004000000000000000000000000003005000000000000000000000000000000000000000000040008000200000000200000040000000000000000000000000000001000800040048000000000000040000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000200002800000000000000000000000000000000000000000a8130000000000000000000000000000000001008010100000782040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000828830454000210000440800000000000000000000000000000c00c0004000000000000000000040000000000000000000000000000000000000000000000000000c020002800000000000000000000000000000000000000000000000000000000000000000000000000000002000000000100000000002000010000000080000010000000000000000000000000000000000000000000000008002000100200402000005408010004000100000080400000000088002000100400280200100002000000200020000080200100104000000000000000c000040040802000000000080000000000000100000000000000000800000f82040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010000000000000000000000000000000002000000400000080000010000282000000400000080000010101280000000000000080000010000280000000000000000000000000280000000000000080000000000280000000000000000000000000002000000400000080000010000282000000400000000000000000000000000000000000000000000010000000000000400000000000000000000000000000000000000002820000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000244f0000000000042040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000d6fc000000000000000000000000000000028200000040004a08000001000000000000000000000000000000028200000040000000000000000000200000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000280000000000000080000010000002000000400000080000010000000000000000000000000000000000000000000040000000000001002000000400040000000000100282000000400000080000010101000000000000000080000010100280000000000000000000000001282000000000000080000842040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000cdff4211908000000000002aa00308000000000000000000000000000000400628240000000018a09000000040b9824d4840000028d7b8ff282a400000000000006537200007d9dc00000000000000000000007b94000000000000001880000000410a00000000000000000000000000004080000000000102000003090a040800000000000000000000000000000000000000000000a0a00000000002828000000000000000000000000000000000000000005085004400000000000000030300000000000c0c0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000442040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000001000000000000000000000000000000000000000000cb1200000000000000000000000000000000108462400100000001884600000000000000000000000000000000400100440000000000000000000000100440000000000000000000000000000000000000000000000000000000000000000000000000000000001cc000000000000000000000000000000000000000000000004000000000000000440100000000011004000000001084600000000000000000000000000000000000000000007c0000000008a2a00001f019de7c000000000000006211877440c00000000031000000000000003800000007c4200000288420000000c42040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000003800000006cc200000104420000000000000000000101001190800000000000366003080000000000000000000000000000004006230800000000188c20000080000030802100000300d0fcff010a400000000000000a35300007f91a00000000000000000000007ba3e00000000000001880000000410a00000000000000000000000000004080000000000102000003090a04080000000000000000000000000000000000000000000008800000000000220000000000000000000000000000000000000000005085004400000000000000030300000000000c0c0000000000000000000000000000000000000000000000000000000000000000000242040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000c0c00000000000000000000000000000000000000000000e04600000000000000000000000000000000148462000000010009884600000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000001cc0000000000000000000000000000000000000000000008000000000000000000000000000000000040000000011846000000000000000000000000000000000000000000044000000000022000001b018de7fc00000000000006211877440c0800000457108000000a42040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00003e0002510420200000000002018000000000000000000000058c02000022842000000000000000000000000511180000000000009818000000000000000000000000000c00c000000202000000000008080000000100602000000000002a600cc02a28100000000000051030ec317fbe800000000000000000000003394000000000000000080000006145000000000000000000000000000061238000000001848e000002450612380000000000000000000000000000000000000000000000000001000000000000040000000000000000000000000000000000716b80802000000000000000000000008080000000000202000000000000000000000000642040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000000000004200000000000000000000000000000000000000000000000000000000000000000000000c0c00000000000000000000000000000000000000000000b5690000000000000000000000000000c8031498020000000001000848000000000000000000000000000000040410000200000000000000000000000000200000000000000000000000000000000000000000c0a20000000000000000000000000000000000000000000000000000000000000000000000000000000000000410000000000000000008000000000000a000000000400400000000000000000000000000000000000000000000000000040000000000015018800000000000e42040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000002000000000006008c00000000000003eff02114420240000000014211053000000000000000000018e02013301056000000000000000000000000111088040000000001411000000000108000000000000000c00c00000020c40000000000831000000013000c400000000412a523ef1003c0000000000000028122c017ab26000000000000000000000033ab60000000000000008000000610540000000000000000000000000006163c000000001858f0000020546163c0000000000000000000000000000000000000000000000000000080000000000002000000000000000000000000000000000712bc0842400000000000000000000001000142040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000050002500000001400080000000000000000000000208000000000008002000000000000000020000000000000000000200000000000008000000008000200000000000000000000000000000000000000000c3430000000000000000000000000000c003109c02024000100000094900000000000000000000000000000000023408424000000000000000000000008424000000000000000000000000000000000000000040a20000000000000000000000000000000000000000000000420000000000000000000000000000000000000816000000000000000129000000000004a400000000500490000000000000000000000000000000000000000000942040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (85002400000000000000000000105800004000004140080000000030800000000000000000001080025aa01000000000200200000200000040000800000000000008000201000000000000200020048240a502004000000000400002004000510000000010014000000010090510010008000014000041002002000010000000014000000000010501000000400000000000000000500000000200010000280000000400008000000000000000000000000000000000014000000000800000000000000000000000000200000000000000000000000000000085800041000000160000100000005000000000000140001000000005200004000000000000000000542040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000400000000000000000000000000000000000000000000040001000000000010000000000000400000000000000000000000000000000800000010000000000008408000000000210180100000000000000000000000000000000000009bda000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000080880000000000000000000000800000000000004000000000080080080000000080000000000002080080000000580000000000002080000200200080000000000094000080000000100000000000000020000000004080108100000004145004800810800d42040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0108c0000001001000000040048048400000000000000000000000000000001040000040000040001000001800040098000000000000000020084041000000000081000000000000000040001000080020000000000000000100000001000040000000000000000000000040000030000001000000001000000000004308049000001000001200000003004048801100000000000000300000048020000040001800020800020060100800040000020008020020000800081800021818020020020060000000000020000000c000000000000000000000000000200400000008008000000200000000000104000000000000100002100001000080000c00000000342040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (41000000000008000000400200000000000000001000000000000000000000000000000000000000040000000000000000000400010000000000000400000000000000000000000000000004000000000004000000000000000000200200000001008000000800000000000000000000000000000000000092f7000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022000000000000000000000000400000000000010000000000000400000000000010000000000000400000000000000600080000000100000000000000107800b42040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100000000000000000000000000000000000900002200000000000000000000040800a000020000000000000000000000000000000000000000000000000200080000000000000000086030200201000000020000100000200000000000000080080000010000100800100000000000000044182200400400000000000000230400000000000000000000000010800800000800000000000000000404402000100000000000000000000800020000000000000081000020000100800000000480020080080012000880000080000040080080000000000000020000000c000000000000000000000000000800000000020020000000800000000000000000000742040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000100000000000000000000000008000001200080248000000000200000200000008002081000000000100000000004000000000000000000c0000010000802400000020010000000000828000000000000a0000000000800000000000000000000000000002000000000000080080000000002000000000000000000000000000000000000000005711000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040080000000000000000000000000000000000020000000000080040080000000000000000000000080080000000000000000000000080000800800000000000000f42040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000000000002000000000000080000000000000000000000000000000200000000020005000000040008000000000000000001040000001000000001000000000000000820800000000400400804014110800000000010000000020802410a00020010420020004000000440000010000000000400800000040000000000000820002420000800010020000010800000001000820000000000000000400800040020400020000400810415040400800510020000020800400400400820440000000000008000000000020000020000000840000000400001000020010000000800000000200000000000040400001000008020010020000000800000000000000c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000000000000000000020000000000000000000000000000000000000000000008000000c000202300000000000080000000000002080800000000094003000000100080000000000080000000000002000000000000000002000000000200000000000008010000000200000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000006df10000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000008000000000000000000000008000000000000000000000000000000000000000800000000002020000000000000008c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000008000000000000000000000000000000000000000200000000000000000020c00000000180200000000000000000000002000006100000080002000003000000000080000084100000000102000000204200000000000004080000000000800080000000004080000200000000000001000000000000000000600000003000002000000040000000080000000000c000000c01000000800000001800021000000010000800000000400020002000000000080000000000020000400030000800000000000082000000000002800000000000000000000000000000000000000080000000000082000c00000041020004c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000050881000000000000000000000280000000000020020020000020800000000000000000100000000000000000002400000082000022000000010000900200000a000840080090010020800000000000208000081000000000a0000000080600008008000000200200200020808500400000080000800000000000002000000000000000000000000500030000000014010000000000500000000000000000000000000000000000000000b7b6000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000186000000000000000000000000000000000000000000000000000000000000000000000cc2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000c0001000000400000040001000a0000000002000000804000000014000400800000000000000000000000000000004005020980000002000000000304828000000000000000002000000080000000080200a00000000841028080080000010140000000000080000002080082140002002084085000100000082000000000001000089080000002000000000002085008442000180a02042000002080000000000082000000000000028000080000002a000020000000a80821000800800820022000020a8080000088082000000000000005000000020002b400020000040a8000000080000a000020002c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000808000000000000008000000400000600000000004000000000000c00080000000000000000000000000000000000000000000000000000000000000080000110800000001004004000002004100800000c041202000000001008000000008000000000000000002000020000040200000000000000000000000000000000000000000000040001020000000800000000104000000000000000400000000500000000000000000000080000000000000000000000000000000000000052af000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000ac2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000008000000000000000000000000000000000000000000000000000080002040000800000000000400802000000001000200200000040000c000002000000080000000100000000000000000012400000000000080000010000000000000040000000000000000000000000000000001000000000080000000002000a941000000000000000000000000000000010000000000000000000040000000000000000000000008000000000000000000010400001020000000000000000000000000000200080400000000000040000002000000000040200001000010000000280000080000000000000000000000000021008000006c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000040048800e000010000002000000280000000000040000000400480881000800000000000010000000000080812000008000000000000000000000000000000000200000000000000000000000000000000120008000000004001226208040100000000200800000200010000000008000000000000000000000a01c000000000000200000000000000000000000000000000200000004408020010000000000100000100000000000000000000008000000008000000000400205660000000000000000000000000000000000000d2a1000000000000000000000020000000200000800000000000000000000000000000000000000000000000000000ec2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080c00000800000008802020004010c22480040100010800001000080682000800410000000000040000000000000000000124800000000000040004920400000000000004000000000000000000800004000800200001040000000000000000800820000000000000000008000008000000000000400000000000000000000200000208000000000004080002000000000000380844000200000200000000000001804000200000000000000000000000080000001000000080000000000900001002040000001c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100000012100000100000004500214000008000008000460208000000000000040000400000010100004000000000000002004008004002000000100000000080000000010000000000000000000000000000000000800000000000000000000000000000000000000000000000020820012420002040008240002000000001000000000000000004080000000008000024000010000000800000000100000000000002080000000000000010a04a1080000080000900008200000000040000000000800008000080100000004002040000000100000000000000000000000000000006cad0000000000000000000000000000000000000000000000000000009c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000200000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000020000880000040110000100001044000000000100080004000000080000020000020100000000040400000000000020000000000000000001040000000400000002000004020000000000000000000000020800000001040001000000000040808080000000000000000000000000000000020000401000000000000040000000000100000000000000080002000000080000002144000440000000000000000002004000000000200000000000000000600005005c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0080000810000009000000000000240000c04000201080000800000000400a000010010080000000000800000000000002000000204101480000008100010000200000202402300102000002004480000000040000000400010000000000000000000000000000000000010000000000000000000000800000888000020040040000010910811084000005110a00000000811028000000008000000000000020000000804000000200000100000000000000000000000020020000000003020400200000000000228400410000000010001000420041020400000c000400000000300000000000000000000000000000000000000000f5af000000000000000000dc2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000008cbb0000000000000000000000080000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000010000022080020802200082404002081001080824105220040010c00000800000000008000000000000000000000400200000000000000000000000081000000000400080000000000000000000000000044000010020a0100800000000000c00000800000000000000008400a040000000400200000000000000000000000a00000a200000000000200000000102000004000100c000880000200000000000001003c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (104810122080000000000000000000000000400000000400000000000000000001000001400000024000000000000000250000000000800000000000012000000000000030c0011001010000010000000000000280001004000040004000000000000000000400000000000080002000000000000000000000000000000000000000000000000000000020020000c2410000010000040640002004c00040100480000080041010400400000000000000000000113000200000000400120000000008000000000000001000000000000000000028000000000000000080000000001100000000001001000000000000000000000000000000000000000000000000bc2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02000000004040000000100000000000000000000000000000000cc1000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000021402900000001950094142001004000340000001902005000000000490040410200100000020000000000000000000000124000000000000000000000000000002010800040000000000000000008000040000120800800000800000000000004100000000000000000000420100020000000000000000000000000000000000000000000000000000000000000400007c2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000020000000000401040000000120000000000000000000000020100000001000000800000000000020102100000200d00000000000000900000000000800000000020100300000000800400000000014031000000000000800060008010020004800000000400280000000000100000000000808000200000000000000000000000000001000000000000000000000000002002000400000000000010041000020200000001000000010000000000000000000000000000000000000000200000000000000000000000000000000000000004000000000000001000000000000000740000000000000000080004000040000000101000fc2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000e000040000000000001000000000080000000000001004000000000000000000000000000004000000003e7100000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019120040001000441000008040220900400000000400200000000010141000000004000000000000000000000000001004002000000000000000000000008000000000001000000000000000000100400000201000030010008000000000000101010000000000000000000002100002000000004000000000000000000000022040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (280120080000100008000002000000000000000186000000002002200100000000000000000000080004000080000010000100000000006000000000000000014000000000100001000040000000040040800020000000000204000004000000082500000000000102080000000021010101000c000000204000081100000000400100010200000000000000000102000000000000002000000000000000000000000000000000000000000000000000000000000000000002000044002200004020000000000000000000000000000002000000000000000000010000000000000000000000080000002000000000000000004000000000000200000000000000822040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000080000004010400000000004000000000100000100100000000100000000000000000000000000400000000000000000000000000000000000000000e759000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000081000000000000004100000000004000000000000000028000000080000000000010000000000400000010000020000000000000800000000100000000000800001c0000400800000000000080180008000000000000000400000000000045140004000000000040000200100422040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000408000100000000000200008a00000008000220000000000010000000000000000000000000000000000408000000000000000000000000000004100000004000000000000100000040100000000000004000040009000000000200200000000000c010000000080040040000800840110001000000000000000000004000400800000110000108000000200000010000000000000000000008000000001030000020400000000000000000000000000000000000000000000000000000000000000000000040050000000080002080000800000010000000000002001000002002000000000000000000412000000000000000000000080000002000800000c22040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000040000420000002000000000000000080000000000040000001041041040000041001010011020000000000000000000000000040010000000055a800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000002084100000000004000000000000000100000000000000000000000000100000008000000080100010000000000000000000000000000000000000000000000002000040000000100040000000000010020080080000000220000000000000100000000000080010020032400800222040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000001000004000800000900000000010011206400200000000004000040011400041000000000000000040000000002000000000000000040040000000000000000000000001000000801000040200000000000800000401002000000000000010100104000004000400000000400100804001100081040000000800880084820000000020004021000050200004800004000080004000002100004010000100000004000000004800004000830000020400000000000000000000000000000002000000000000000000000000000000000000000012000000104000500002020000012040000800081082000004000080000080000000000404000a22040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00101400000000000000000001000000800000000000090040000000041002000001401001000000000040000002000000000080000000000000090000010001482582000000102002000000001100000000000000000000000000004000000000005a5300000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000104000000004400001100204008001000410000400200000100000008000000000000008000004200020108008048021000000008000000100000000000000000622040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000900000002000000000000001100000000000000000000000080000002002006088006140000004800200002000000100000002409820000000000080000000000001000800000008008000001000200800000001000100000000004001000000008400000800080000001000000880001008100000000480a04000000002104200000004900000804020802002000024000120000000004020110000000020488000000000100025141408000880810000000000100000400000000200000000000000000000000002000000000000000000000000800000000200000000000000000000480080000044014000080000000410010000004110000000000e22040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00840000000000000088000000000000200100004000000000100000100002000000000012000000000080000000041000000001001040000040040000000002000000000080000000000000010000014000480484104104082006100104000000000000000000000000000000000000000000006cd900000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000040000000000040000000000000000000000002080000000000000002000000000080000000000040000000000000000000880504000002000000000000400002400000010000800000000008000000000008000008100122040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000240000000000000000420200090800000000c0020000000000000000000000000000000000000000008000000008000000020a008002214092000480182000000000000000004000000000000800200000000000000000000000208008000001000200000000001100000080000000040040000000000000000040000000000000080200008000012000000004208000000004082000000202580400000000002040004000000000000000008100800008010000200000800001009049000000000001000000000000000000000000a00010000001000008000000000000000000000000041000000000000000000000000001202000080002091000000000922040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000000000012020001004820141000000103000000000004202800000000100c0000000000400000000a0500000000000002840000c00000005000000000000000100000000010200050010000000000000000010000000000400000400400000000000000100000004000000000000000000000000000000000000000000000000000000772d0000000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000000000004000000000000100100000000000000000000000000200000000000200000410011c0040840800843000000060480c200000040009430008008041001c480000001000800000522040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000200000200200000000200000000000000000000800000020000000001010002000c008000300000000000000000010000000120000000000000000020000080520500000200002800010028a0002002100000c04910000003000400000000000000000000000000200000000020000000000804100000000000040020002000000404202000000420000000000000c002000000000402000000000800000100410000800200140800500001220004040014014022800000000010000004008000000008010384200400500009000010000000000200800000000000000000000000000000000400000010000000000000000000000000041000000000000000d22040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000400010000c100e8040000140200004e40020015000000000000400a00000002038000000000000000000a000100000280000001c040000000000000000000000000000000800200000000000008020000003000000000000000000020040200000000014014000000000002800000000000000000000000000000000000040600000000000000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000040000000000001081000000000001048200000002089000000000001000210400400290050040050080000410830000800000000322040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000010004000000000100a0010000002800302002000010010000000004004000000000001003000000000000002000000000000000002000000000000000000000000000000000000008085002000028005000000a000050000000400000000000000000000000004000000000000300040000000000000000000000000000000000000000000004000200000000800000100000000000000000000000000000000000000000000000004030804000000000900000000010000c00000050000804000800000001c2a0000040001000230611000022209000000014040000800020408000000080002000402000400008040000400000020000000b22040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010080000000808000000000000000000000000000000000000000000000000000000000000000000000040011000441000090422500000002908cb4801000000000000040000000000000000000000000000000010001000500000000000000000000000000000000000000000002200896800000084012d900800008028b6001100000008c00800200000000000400000000000000000000000000000000000000000000000000ef2d00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000722040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000408084202000000000000000010005015000a0004000000000000000000000002002000000000000084000000000000008000000000000000000000000000000000000000a00000000080a000000000000000280100001000400000000000000000000002000800000000100000000000000000000000000000000000000000000000000000080021402000000100000000000000000000000000000000000000000002000800000d0000005000010401000000000100008000000000c0000000000000000000040001000300027002000108000000000000036004202800800000020000f22040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (080000000000000000a0010200540000002000000000000000008000000200000000000000000000000000000000000000000000000000000000000000000404080002010000001000000800200000004020000000000000400000000000000000000000000000000000010000000000000000000000000000000000000000020000000000000020000100080000000001004008020000a00000800002000000002020000000000a082040000000000000000000000000000000000049b9000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000040000080200000004000000000000a000000000000000000000000000000000040000000000000000000000000500000000010000000000000000000000000001000000100000000000014000000001500000000000000000000000000000040000000020000000000000000000000000000000000000000000000000000000000000020040000c000000000000000000040200020001000000000000000408080004000600000000000400000000000000600000000000000000000018000000080800000000400000000400008a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40002000040010000000000088050002040800000200010000028828226100c400100800008002010004000000008002000000400000000000000000000000000000000000000000000000000000000000010400020000103015010614218890a484c8448500040000800204001000000000000000000000000802800000010080020000000000000000000000000000000502020220080618498403004212a14a100202184c84a8402001218a11200000000244924800000002a22890000000000010000000000000000000000027ef000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010020000000142008140204820004020000801000a0120008403000000001008400000000000400000000000081010000000000000002000000000000010040000000000000000000000041000200011021000100010040000a01100050050000000000000000000000000010010040000000400000000000000000000000000000000000000000008000002000424040000c00000000000000000008080000000000000000000000040804000000800800200000020200800000000041000200000000000800ca2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000010000000000000000004000002000000004000800000100000808800000000000020000000000a0040020190200080020010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000808000000008410610a00210910908628408500000000810204000000000000000000000000000800000000010000060000000000000000000000000000004408420200118518018400400a102146102200284284684080008058196000000000c2802800000001420a000000000000000000000000000000000000f890000000000000000000000000000000000000000000000000000000000000002a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000008000804200200010020020008000000000000800800000000000200200000000001004200000000000000000000000000000020001000000000000000000040010200001001000100000040002200100064078000000000000000000000000008010000000000200000000000000000000000000000000000000000008000002000000040000000000000000000000004000000000100000000000000000004200108000000200000aa2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000100000000000000000000000000000000002000000000000005080000000000000000002000008040084200400000200000020080000000004000004000000800000000000000022000000000000000000000000000000000000000000000000000000000000000000000000020800000100000800000000100001001000008000040080000000000000000000000000000000080000000000000001000000000000000000000000000000000802000020000000000000000000100004000000000000000000020a00000000020000800000000002040000000000000000000000000000000000006295000000000000000000000000006a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000c4ac0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000280010000020000000000000000000000000000000000000000000000000000000000000000000000000800000000000000002000000000000008080002000000000000000000000004000000800000000000000000000000080080000000000000000000000000004000000000000200000000000000000000000000000000000000000008000000000100000000000000000000000000000040000000000ea2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000000000000000000000800000000000000000000000000000004000200080000001200020100000000000000000001000001100000000040001000000000000010003100100080020000008000000800000000001000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000020010000c00c84002000030032000400008000800010000400000000000000000008000000000000000000000020000000000000000000000010820200100400430c300200c0000c40c000001002300300000040044008000000000810000000000002100000000000004000000000000000001a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000440a000000000000000000000000000000000000042e500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010020000000000000000000800000080000000000800000004000000000010030000000000000000000000000200001000000000000000000000000000000000000000000000000000000000000002020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080200000000000009a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000c00000004100000200000000000000000000000200a0800000000000000000020000000000842800000004820200000000010041000200000000008820021008000000020000000240200800c40c0b00000001004004002030040242000004000000000100050000802100020000000000000000000000000000000000000000000000000000000000000000040000800441009000024002022140040400084c840005080001420000140003010000000000000000000200110000008000000080c00000000000000000000000848040004001001809840200400221061000010011848840000000011062000000014408400000005a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (94520306148e4000010c1828200000043060a080000000c0000000000000000000000000000000008cae0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000802000100020280000001000000000100000000080100001003000000000000000000000000000000000020002004000000000000000800400000000008020080000000000000000000001008000414020000000010000000001000000000000000000000000000000040000000000000800000000000000000000000000da2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000008000001000000000000000000000000000000000000000000000008000001000000000000000000000000000000000000000000000000000000000028000000000000008000001000028000000000000000000000000028000000000000008000001000000200000040004000000000010028000000000000008000001000028000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000400014864251480000521909452000054864000000001000000000000000000000000100000000000000040000000000000000000000030600080000010c18521909452030614864251480c1852190003a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (55554c0ddd36455555383774d9155554e0ddd364555553837044215555188421108555546210a100000000000000000000000000000000000000c4ec000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000001000028000000000000108000001000028200000043060000000000000c180000000000300000800000100000000000000000000000000000000000000000000000000000000012800000000000400000000000002820000004000000000000000000020000000ba2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (038048110040000000000000000000000112200000000021021000000000000000000000000000000000000000000000000000820f10000400000000000000000000000000000000000000000000000f0ff11a2000000fcc000004642100001811800001c54c0000000000000432b400000000000001ab5f57c800001faaddfebc000000000103e54b76000000000000036ae600000010000003883000000000000000000000000000000000000000000000000000000000000000000cccc000004010b3011303774d91cc044e0ddd364428293837000000a0a00000000000000000000000f0000000000000c0c0000000000000000000000015554000004421007a2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000001a9a80000044216a6a480e3dc639a9a92638f718e6a6a498e3dc639a9a92638844216a6a1884211085a9a86210a1000000000000000000000000000000000000003e53000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002110110000080000000001e000000000000281cc370055554010000000005555000000000000000000189ff000000000000033c30000000000000000400000000000000000000022a3804800000800000000000000000fa2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000002200894200002a228000000000000008942150840000000000000000000000112200000000023021000000000000000000000000000000000000000000000000015405010000400000000000000000000000000400000000000000000000f8f40ba20000007c4000004642100000891800003fd4c0000000000000436b400000000000003bbd757cb000007ab40bebc000000000f0324ab70000000000000037a6e000062228000038830000000000000000000000000000000000000000000000000000000000000000000808000004210820012038f718e0800498e3dc6380221263880000008800000000000000000000000f000004000000002a800062040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000000000000000000aa000000000000000000040000000000000000001a800000842a6a6a64308031c9a9a998c200c726a6a66308031c9a9a998c20842a6a6a00c52210a9a9a80314910006a6a000000000000000000000000000000081aa0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d0000000000000001e000000040000291485511da9a8010000000006a6a000000000000000000189ff000000000000033c3000000000000000040000000000000000862040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000200304000000000000000000000000000002c52100000000000004000000002c52012a800000000000000000000002123000000000510220000000000000000000000000000000000000000000000000080a8570c00000000000000000000000030000000000000000000000000000005a3080000000000006a62a0000009100000000000000000008c241c18800000000000004087cbbdc00001660c80000000004000fa001cb4a00000000000004b4d200000c4000000000000000000000000000000000000000000000000000000000000000000000000000000000000081800000190c200c72000066308031c8000198c20400000000000000462040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040461b221c990000186c88020000000000000800000000000000030300000010000000000000020000000000000003015400000852b5555603320c191555586c883064555561b220c191555586c88852b555500856214ad55540215910095555000000000000000000000000000000002c1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000200000000000008000001018000000000000000008000022c9a422b001a8000000000006a6a0000000001a9a80000008ee00000000000000c62040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (5000000000155540000009ee000000000000000000000004000304000000000000000000000000000000816008000000000000200000000816604b4000000000000000000000021614000000001102b00000000000000000000000000000000000000000000000001054f570c0000010800000000000000003ab00000000000000000000200000023a3010000000000004e6230000009100000000000000040000c241c1980000000000000519f08b1c00000269440000000000000c8002ab4010000000000004945f0000022340000000000000042000000000000000000000000000000000000000000000000000000000000000000130824000180cc8726400262040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000080000000000002000000000000280000000000000000000000000000800000000000000000000000500000000000014000100000000000000000000000000000000000080010000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000006252000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000040000000040001000000010108000000000008041000013816407b701540000000000055500a62040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000001000000000008000000000000000000000000000000000000000000100000400414200800000000080008000000014880000000000000000000000000800200000000800000010000002080000800000088200000002002a800801000000800100000000024800800800000802000000800140004800800400820900000820000800000000800004000000000000800000004805010800000000940000c00004800020084820120940000000800805000000000004000000000000000120820800000000000000000805880000000004340000400000805000100020000000000000000000000000000000140000000000000000000000000000662040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000180000000000000000000000000400004000000000000100000000000004400001000040002000000000000000060000000000000000000000000000000000000000000000000000000000000002000000000004000000000000000000000000000000000000000002000000000000000000000000102000000000000000000000000000000000000000035bd0040000000000000000000000000000000000000000000000000000000000000020000000020000000000000000000000020000800000000200000000000000000000000000000800000000000000800000000000800000000000160000820000025000000000240140000e62040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000000000000000000000000000000000000000000080000000000000000c00000000006c01860000000000800000000000000000000004000100000040006000410001000000000000000002000000000000200200010000100000000000004100000000000100000000000004000000006200104000000000004200000000200002004000000404000100000000000001000000004804200000000012800000004804800a00000000000000800004000320104000100120008410800004800000000004012000000000000120820000002002000000480004100000000444042002000000000000100000040002002000000000000000162040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004000000000400100080080000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000040001000800000000000000000000000000000000000000000000000000000000100000000000000000000000800000000000000010000000000000000000000000000000000000800000000000000000000000000800000000000000000000000000000000000000007a190020000000000000000000000000000000000000000000000000000000300000000003000100040000000000000000000020000000000000000200000000000000000000400004010000000000000000000000004000000000962040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004000000000000080000000000000000000000000000042000004000000000004000000000000000000010000000000000000000000000000000000000000000000000000000000002002008000000000000000000000040000401040000400000000000000008008000000002200200210000000400000000000008000000020008800400400000000100000200000800400400000208000000600008000800400400020400000420000400400000400000200000000048000000000000000200000001000000000000800000001010040400003040000800000000000000048000000000000000001000008008000000480800000000000440008002000000562040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00800800a10800910108000000100041000004000000000000000000400800000000010000000000000804400000010000100000000000008800080008008001000021000200c4890000002800010000100000404800000020010000000000000400800000010000000000000000400000000000010000000000000400000000000a000000000000000000000000200000000000000000000000000000000000000000200000000000000000000000000000000000000000f83d0000000000000000000000000000000000000000000000000000000000000000010003000000040000000000000000000000000400000000000200000000000000000001000000d62040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000020000000000000000000000200080080000000000000000000000020082000000000002000000000000000000000008000000000000080000000000000000000008000000000000010000000000001000000000000000000000000002000814120804001000000008000000000000000000000000008400020000000000000000000820804418040090810000800000028000400000000800000000000020800400000000a00000000000800400820000410800000800000000400800000000400200000000040400800000000440000000000800401000010000000080800081010402000000000400000001000040400800000000000000000000000362040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (06000000200000000000000000000800000000000001091000880082000000020000000000c00900000000000000400000000000010000000000020000000000000000000000000000000000000200000000000020000000c0010000008000000000000000000000000000044000000000000000000000000800000000000020000000000000000000000c00000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095990000000000000000000000000000000000000100000000000000000000000000000000000420000000000000000000200000000000b62040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000020000000000000000000000000000000000000000800100000000000000000000000000000004000000000002000000000030080000000000002000000000000000000000000000000000000000000000000000000001800030000000000000000000c208300010420c0022000000000020800000800000000100800000000000800000004000000000004000002000000000040180000000000004000000000000000000000000000000000000200000000000020000004000000000000000000000000000000000000200000000200000000000000800000000000020180000000000000020000200020008000000000800000762040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (29000000120808000a8080000000000a4000000008000008008000000000000808010000008008000800014200800000002d0020000004000100000000000000000800000000000000000000000804800010020000100000400000004c0004020800000110000100000014d00000000000420000100000804800000020000000000400000800802208020000000008200000800000000000020000000000000800000000001400080000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000002000000000010dc0000000000000000000000000000000000000000000000000000000000000000000000f62040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000000000000000000000085020040004000000000000000000000000000000000000000000000000000000000140800000000000000100000210000000000208000001000004000e00100000024028000200000080000040000000000000010000000000000020000000000000800000000000000008000280800000000001428010808000280809000800000000100800000000880820080000000400000004850a0182002012140020080000005000480000000000000000008005088080000800000000000000080080082400002000000080000000080080000000140200000000000080080200200a000000000000a808000000000e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000080080083000800000000000000100000000000020000008000008020000200008000500000000000000000000000000000004000000100200002008000100008040000001020000000010000000000000000000000000000000001000000000000000000000000000000000000000000000002000004080000000800120000002820002000000020000080000001040000000000000008080004000000242000000000000000000000000000000000000000000000000010004140000000000000000000000000000000080000000000000000000000000082000000000000000000000000000000000000019ff00000000000000000000000000000000008e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (73a50000000000000000000000000000000000000000000000400000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000400000140041202104040000000000000020040044000000080000000000081000000000000000000000000000000000000000008000002000000000008000000006000000000000000000004000443200000000010108400450000000000000004000000000000400000000000000000000000000000000000000000000040000000001002200000000000808000000000020800000000000000000000000000800000000004e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (6000001000000040000800080c310000001000208004000004801a100010010000800000040000000000020000002430000014208010000000008000010000120000020000004000000900000000248118100034200010c00000000040100000002800002000000100000002400000061000000000000000000000000000000000000020000040000000000001000000000000000c981000000000000000000000000000004000000000000070000000000000000200000800000000000000000000000000000000000806100000000000000000000000000000000000000000000000000000000000000020164000000000000000000000000000000000000000ce2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000040000000000128800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000600041004012000841a40000400400000218000000400000000000000000000000000000000000000400000000000008000009040000000000040000000000000080080000000065000004000000001000100000000000000800000000000020100000000100080000400000090000000000000000000080080620000000000010c8000004409080010060101000080408880008445002e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000208000905400011000810402000008200000000000000000000000008000000000104000010008028448000000211010000804000008000000000021000001248000050004808840001000000010000020000020800090100000804030c3004892080404900000520002000084010080000200000000000000000000040080000100000000000000000000000000000400000000000000120004020800000010000c80004000410020000000400000800000010100000000000000080800040000000020000000000000000000000000000000000000000000008000000020c0000000000000000000000000000000200000000000000000000000028000000ae2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000100000000000000000000000000000000000000000d89400000000000000000000000000000000000000000000000000000000000000000000000c0000000000020000000000000000000000000000000000000000000000000000000000000000000000000001000002000800200000001023228640000200022620008400000248440042000002080000000000201000000000000000000000000000800000800000008000000000000000004000008000000000200000410000000100028900000000002024001430100080008000000008000000000000000000000000000000000000008000000000800000000000006e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000000000000400000000000020008000003000404110000040200002400008000400000800010000000400002000c0208100000000008200000004c400000000000100000000002000000080000000104100880001004100000800010000000000041000000000081000000040000041028c8000100080052000001000000800000000114000008000001000000220000000020000000002001000200080080080000080000200010000000003040000000000000000000000000000000000000000000000000001000000000008840004040001210000001000000000000000000000000000000000000000c00000000000000000000000000000000000000ee2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0082000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000002fa1000000000000000000000000000000000000000000000000010000000000000000000000002000000000000000000000000000000000000000000000000002000000000000000080008000000000000000000000040000000100000001002080000404900002040010040100000000000040000000000000000000000000000000000000000004000041000000000001100100100000040020c022005009211000c90000010000101000000000000a84000000000025100000004200400000000008000010000000001e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000020000104800000000004100400000000104000000c00000100000000400001000000000000090040001000000001000000000800400000000000000000000010020400000000000008000000004120240080000000000000c00000000004000004000000400040900000000091000000000000000000c0010000000000000104101021002100004000080000210008000000000040000000000000000000000000002000000000000002000000080000080100000020000020840821000000020020800800001c048000000000000000000000000000000000000000000009040000100004041000008000000000000000000000000000000000000000009e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000010108000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000791f00000000000000000000000000000000000000000000000000000000000000000000000c0000120800000000000000000000000000000000000000000000010000000000000000014200000000000000000000010000000000000040102042120000002400110500000480000000000000000000000000000000200000000000000000000000000000000000000000040000000008000050100008209040004000000000000000000000000000000020000000400000005e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000090042000000000a0200000100400248000020210050800000000401040000010000100000000008400000000000000100000800004000008000000000100000000000000000000000010300000000400000000040000120100001000000800000000020000000000000000f000080080000301008000000000000000000080000000000200000000000001241103200000000008080000000001000000000001000000000000000000400008000040000000000000000400000000000000000000000000000800008410000000000802000000000000000000000000000000000000002000000000000000008000000000000100001000de2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000002000000018000000000600010000000200000000000002000000000000000080000000000000000000000000000010000000000000000000000000000000000600000000000000000000000000000000000000000003cfc0000000000000000000000000000000000000000000000800100000000000000000000000040020000000020000000000000000000000000000000000000000000000000000001020000000000000000000000020010000300000382401000020012004080103000080001420000000002000000000000000000000000000020000000000000080000000000000000000000802004000280010100000000000802208000003e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0400000000000018000000000000200040524000000000000000000000240200400000800000200000000000100010008000400200000200010000400000000010408000000002000080090000800008000800000000000010480000000000000a0000020000001000000000000000040000048800840000100001008010001001900000000010001014000040108800024000400000001000001800100000000810001000000101040000800000440000001c000001400041000000000000000000000000800000000000000000000000000000000020000800000000000000082800000100000200040000000004000000000000000000000000000006000000be2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000008080000100000000000000000000020004004020020000000000000000000000000000000020000000000000000000000000000004000000000000000000000000000000000000000100000004000040000000000000000000000000000000000000000021cc0000000000000000000000000000100000004002000000000000000000000000000000000000000000000000000000000020000000040000000000000000040000000060000000001800000000000001860000010001000000000020083000102080001000000080000000000800100000800000000000000000000000000800000000000000000000000001001000000000007e2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000020000800000000000015000000000000000204000040080020000004000004104400000024014120000040400000000c00001000020000000000020000000000020000000000000000000000080000000000040800012000080014000000000010060200000100000000200000000000000000000080010000000000000000400000000040400000000400400000c82000040000020020c10800000008802000000000000040000080000000000000000040000000000001000300000008021000300008000200020000000000800000000000000080800020010000000000000000000000000000000000000000000000000002000004040000000000800fe2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000040088048402040004040842612240821242000000008810a000001000200100000000000000001040040420440000000000000008080000000000000000000000000020000800000000000040084000000000000000000000000000000000001000800040000110000000000000000000000000000002000000000f23100000000000000000000080000001000000040004000000000000080000002000000000000000c000000000000000000000000000000000800000000000020000000008800001000004000000000000000000000000000000000000000000000000410010220000040008000000000000000000000000000400000000000000000012040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000041000800800000000000200000000000005001000000000010000000000000008040000000400000000040004020820840000020120800000004002004000000200200004041000008000400000100000004002004000000000000400000000200008000100400000020000000080200004000044400800008000000000004900004000400000000000000000000008000108100001100004408008a44410000800100243004809100000080214002008024001000040528000002204002080400000004128000a430c00000c000000304820000000001000000000000000000000000044100000020000000000000000000000000000001000000812040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010824000100000000200008100000000000008010020000000208010080802008020800000000030480000000000000400000000000000000200040028000000001000000000000000000000000000000000000000010000000000000000008000000000000000000000000000000000000000800000000000000000000000000000000000000000800000000372a00000000000000000000000000000000000000080000000000000100000800000000000000000c00000000000000000000000000000200000000100000000200000000800000000000100000000000000000000008008000000000020828820280880828a40000a000010400800800412040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000820400080020400000400000020000040000000000000000000000000020000010000000002000b00100000000001000000082000240020000040040020000000000000000020020000000000400040040080000800008010000800002400a004000180a280020000020000000802020000000000880004260000010004001000040000000040100000020000a200000000000000108000080040000002000000000800000a0060020000010105018890220c80900114004800826110020800120090020000020020014000c00d24100120824020000008004020c008288000000000001000000000000000000000000040000000800001000804500012000c12040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000008800000008000000000000800000000800820824000000020000000000140000200004400000410000c000000402b0422c0041042000000000001000000000040100000000000000020090000000402000000000080001000000000000000000000000000002000880000000000000003800000000000080000000000000000000000000000000000001000000000000000000000000000000000000000028ed000000000000000000000400000000000000000000000800000004400008010000000000000000000000000000820000004000000000001800000000000010000000000000000000000000000080000000000000102001002000020000212040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000080000000000000000001000040004200000008040000000000010030000000300608000100000104000200000020000000000000000010000000000004000000184000000100000108418010008000600008300000000400a0000000000000000000000000000000008000004900000000400850022800800000002000840041000000000000201000000001040000100010080002000001080004000102100000000000000000860861000000021040000000400000000900002000008020080402000002000000000004040000020820800080010000000000000000000040000000000000000008000080200144084000001210000000282000000000a12040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040c40000800000040000000001040040001140300004004000000c00010000000800010001000800000000200020c00000000000c0020001000800000000000020484020000000800000000000000280000000000000100000280000000020000004000000000000100000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000031be0000000000000000000000004000000000000000000000000000000004000000000000000020000200000000008200000000800000000020000040000000000000000000000000c0000000612040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000020000400000000000000000000000000200100000110001004000002808040000000800810000000000000000000000000000000000000020000020000000010c00140140000400000010400a4102004000032c204080200110000400005b00080080008a00008828a0004000000000000442001080020180081000028004001020000000200030012400000000000080400100000410004002001008000200010808000000003000000000000000020030820c080000010080a00a000000008000000840000000400001400000000300000400080024003082092040401481000000c0000000001001000140040000100040045100e12040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000280850000880040848006003c05000412000580000000000000000000000000800000000000000000000000000c04400000000230030000000000002c000001000000e0020008060000000002a038000e8000000000000000000000000000000000000000000048054002802f02800200008040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f530000000000000000000000000400000000000000080000800000000000400000000000000001000008000000000000000000080000000000000112040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000000000000000000000000000000000000000000000000008000001000100080000000000000000000000000000000044048000000002002000000001080084014000001000000000000000000000000000000000000000000000000000000000000000000000000000000400005005000100400280c00080400002020000000000800880000000000000000000000140600000005000000000200080000000000002000000000000000000000000000026020000000000100000800000010000020040a00000000000000018030000140140000000000000000000028028000005000000e00000000000000010000000020002800080000d00680000000912040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000880000104000000000000000000000000000000000000004020000000000820508800080800400002000000000000400000000000008008000000000000000000000008000000000000a00200000000080000000000028008000080000000000002002005100000a000000000000000000000000000000000000000000800000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006f3000000000000000000000000000000000000000000000000000400000000000010000140000400512040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000800200000000020000000000000210000000000004000000000000040000000000001001000000000100000001000000200100000000000000000000000000000000025000000000105b4000000020052d00000000000020000000000000000000000000000000000000000000000000000000000000028000000000200008008000400110800425100000021001b4000000040002d00000002400430000000000000000000000000000080014000000002800500000000000040000000000000000900894000000020012c000a00028005000008000000000000000000000000000400000000000000408000005000200000000000000000000000000d12040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40a00000005000000000000000000000000000008000000000000020004000000080000000000000000000000000000000000010a0200000800000000000000000080200000000100000000000000000000000000000000000000080000000000000002800000000020000000008000020000000000800008000002000000140040000000000000000000000000000000000000000080000000000000002000000000000000000000000000000000000000000000600200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004c48000000000000000000000000800000000020000000312040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000800000000000008008000000000200000000000008020000000000000005000000000001000000000000140000000004000000000000000040000010000040080000000000000008000000040000a00100000000a09080000020028080000000a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000400a80080000000200000000000000000040080000000000000000000000000400000000000000000000000000000000000000000000000000000000020001000004000000000000200000000000000000020000000000200000000000000400800000000000000500b12040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0024004000200200030030000000000000024888201109421000200008000000000000000000000240001040002000240008000000000000000000000000000000800440000820202120c0208000500024000000020000000040210000000008009000000000000000000000000000400000000200200000000004808000000a008022012900000000420084010001880000300000000000000000000000000000000000000000000080012010008000000000000000000000000000000000000000000000000280280000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007006000000712040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000341200000000000000000000000020000000001001000000000044004000000001100000008040000000100000000102100000000010084000000002102200000000000008000000000020030000000000000002000000000040010000102102140c0618448488409024610612210000008000008000000000000000000000000000000000000000000000000000000000800200000000001200a000240050202081001001010014840040040500221001001014004840040040080000010001000000000800000000000010000010000000080200080200010004020014040840840840321061861000004021111800000000f12040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0084000002006146000000000904100000000000004000200a00000000000000000000004098201109001800200008000000000000000000000400000060042110100040000000000000000000000000000000000000010000000042080048048000000002000400000000102200000000080000000000000000000000000088028000000002201200000000080008000001000000084080000000000142010001800080000000000000000000000000000000000000000000200280012010000000000000000000000000000000000000000000000000000080480000000000000000000000000000000000000000000000000000000000000000000000000000092040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000a8db0000000000000000000000000000000000010000000000008004400000000010100000804000000410000000020220000000008008800000000000000000000000400400000010000402000000000000000000000000400001402610200214040aa8408408409028a10610210000000000408000000000000000000000000000000000000000000000000000000000000400000000000200200008000000056100000102c0088400400404009a1001001020000000040000080000018000000000000000000000000000000000002000000000080000000000022001840800892040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800100000000008040000000000000000000000000004000000000000000010000000000000000002200200020000000000000000000004200008082000000010000000000000000000000020000000200002220000000000000000000000000000000000010002004000009101000080000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000004080000004000001008000100000200000000000280000000000000000000000000000000000000000000000800800002000000000000100000000000000000000000000000000000000000080080000000000000000000000000000000000000000492040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c45700000000000000000000000000000000000000000000000000040000000000000000000020000000000000000000000000000010000000000000000400000000000010000000000000000000000000000000000000000000000040000000000000000000000000400000000000800100000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000100200000000008001000000000000000020000000000000000000000000000000000c92040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000c080008040000800400000000030030080000010c10c00000000400400000000010010000200200000000000000000000000000200008000000000004000000000000000000000000000000401000000024090000000000000000000000000000000000800000010000090000024000000000000000000000000d00000000020024000000000000000000000000090000000000000000000000008010000000000002060000000000000001000000040000100000000000000000000000000000000000000000000000002000000000000040200000000000000000000000000000000000000080080000292040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000002008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000056a900000000000000000000000020000000000000000000000010010000000000400800000080000000000000000100c00000000000020000000000800800000000000000000800000000000000000000000000000000000020000000000c00c00000000430830000100000c00c00000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000040000102000004004000004000100100000000004004000000000100100000000a92040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40040100000001001000004000040000000200000004000000000200080000000008002000000000100400000200008004000011000800840400100261060010004009009200000000c00040010010000300300000000000000228000100004200000000000400000000000000028003000008004000108000080480000000000000000000000000008104c0009020210c0040000000281024001002020000000000200000000008000800000000000000000000000002000000000000000000000001004000000000d00c40b040140200028040002010400400300000000000000000000000000000000000000000480400100002008002000080c00000000000692040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001010000000000000400000000000000000000000000000000000000002820000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bcc800000000000000000000020040000000001102800000000000004000000001100000000000002804000000000002000000000088080000000000200200000000004000000401000020010000000000000000000300000000020044002002100a0000058488501000000212210000040000408000000000000000000000000000000000000000000000000000000001000400000000001000800020050028004000000100400c000000e92040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000282000000400014864251480000521909452000014864251480000521909452000000080000010000002000000400000080000010000280000000000000080000010000521909452030614864251480c18280000000030600000000000000282000000400000000000000101280000000000040000000000000000000000000000080000010000282000000400000000000000000000000000000040080000010000282000000400000080000010c18000000000030600000000000000000000000030600000000000c1800000000003060000000000000c1808200000043000008000001000028200000040000000000000000000000000000000000000000192040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000030300000000000c0c00000000000000000000000000000000000000000188421108400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079870000000000000030600000000000c18000000000030600000000000c18000000000030000080000010c18000000000030600000000000c180000000000306000000000000000820000004000000000000000000800000000000148642514800005219094520000548642514800005219000000000000000000000000000000000000000000000000000000000000000000000000000000992040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000001c030000000000000038048110044c01203774d9100004e0ddd36440001383774d9100004e0ddd3644000000000440100000000011084000000000442100001008400000000000000082000004c0ddd36455555383774d9155552888a00001555400000000000006a01c202000000000000000f0f06a01c0000000000000000000000000000000080d4000010b10f0c06294011aa00000000000000000000000000015430000053b30000002bf7eaec0c0c4000075ec6eaea0040000003aba800000000000000000000001555401000000055550000000001555400000000000555501001425580000000050842000010280408100000592040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (006a810000000001a80000000088242080000000000000000000000000000000000000000000aa004000000002a800000000000000000000000000000000000000001884211084000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fc9700000000002a01555400000000055550000000001555400000000055550000000000000000002008855550000000001555400000000055550000000001555400000000000000000084e600000000000000000000000000000001303774d9111114e4ddd36444001383774d9100004e0dc00000000000000000000000000000000000000000d92040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000001c030000000000000008942150848c013038f718e0000498e3dc63800012638f718e0000498e3dc638000000000542100000000011084000000000442100004a8840000000000000154050000480e3dc639a9a92738f718e6a6a1014000001a9a80000000000000011409512c000000000000080f0011400000103000000000000000000000000080d4000010b10f0c01500a117f800000000000000000000000000157f000005377600000267fe6ee4c0f4000075e4e15150040000000545400000000000000000000001a9a80100000006a6a0000000001a9a8000000000006a6a00000392040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (6a6a0000000001a9a8000000000006a6a1000100161a9a800004000000002145001128000000000000000000000000000000000000000000aa00000100000000000004000000000000000000000000000000000000c52210a80000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000001df900040000000001a9a80000000006a6a0000000001a9a80000000006a6a000000000000000000222886a6a0000000001a9a80000000006a6a0000000001a9a800000000000000100084e6000000000000000000000000000000012038f718e1d1d49ce3dc63800012638f718e0000498e200000b92040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (066308839c8000198c204c7200006630800000000000000000000000000000000000000000000000000000000000000000000000000000002c52012a8000180c200c72000066308031c8000198c200c72000066308031c800000000004aa000000000210a8000000000842a0000004980000000000000080a8000064308031c801a998c200c726a6a22c1a00001a9a8000000000000002c92022a00000000000000ffff02c9210000000000000400000000000000000000000000001800002005021218000000000000000000000000000000000004b812470306beb49040000000001b4d00015000000000054540000000000000000000000001a800000000000792040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000030154000000000555500000000015554000000000005555000000a525555400000280900002801d205240000000000000000000000000000000000000000303000000008000000000000200000000000000000000000000000000000856214ac000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eb870000000000000001a80000000006a6a0000000001a9a80000000006a6a0000000001a9a8000041018006a0000000001a9a80000000006a6a0000000001a9a800000000000000000044240000000000000000000000000000000190c600c7200000f92040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000c01400000000180cc83264000061b221c990000186c883264000061b2200000000000000000000000000000000000000000000000000000000000000000000004200000000816604b4000190c883264000061b220c190000186c883064000061b220c190000000001812d000000000214ac000000000852b00000088c00000000000001054f0000603320c193015586c883064555501054000015554000000000000010114444340000000000000c2fc1011400800000000000020000000000000000000000000421100004d2323135c000000000000000000000000000000000004b4524703023f34505c000000001f455c0ea0000000003aba800052040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800000000000000000220100000000000020000000008000800200000008000000000000000800000800000000000000002000001000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000200000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ceb6000000000000030154000000000555500000000015554000000000555500000000015554000001109c0550000000001555400000000055550000000001555400000000000001000044074000000000852040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00008008200000000000002200000000080008000000200000a00208000208000202000000000000000000000000000000000000400000000008210000000000000080010880000016000000000000590400000001002400004400028080000a10000002020420010029000000c0001000008000008000350400000000000208002000802008480000800900020020026020044a40a40a002000280080080804080080080000002000500108400004008002002002a8008008008045200200200a011080080000000000080000000002008000022008004c000a1002211a42082030080000000480005011000100c000002220100008000110000400b020000800452040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000c014cad018c02212d200092001040000020060020000000000000000200003000000001080000000010440800000000000000000010000040c0040000000000000000000000001000000000000000000000000000020000000000000000100000000000104000000000000000000000000004020021000010000000000000000001020000000000000000000000000020000000000000000800000020000000800000000000800000000020000000000000000000000000000000000000000000dba500000000000040000000000000000000008000000000010200000000000008800000000000200000000000000200040000080002000000000008000000c52040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000400000000000010000000000000002000180000000000000c020000000000000020000000000000000000000001801800000000000000020000000000900800000000000143300000000885000002100000040003060018001000000000001040000040000001000000000001000000010000000000000000000000200000000021000800085000040200000000000002006000000001000040000000000000008000a40000808000021180048c8804000222100000002104000082000004800302000002000000000000000080088c0000010010820000816482181c00c024004f00a0c0082448800c0a020821200883000252040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000402400890a02001222080c80002030020000402004c20080c80000028808000002080008080000000000000000000800000000000080000000008202000000000000000000008000001200108000000000000000000000000000000000000000000000000000800000000000000001000000000001040000000000000000000000000040800800000080000000000000000000800000000000000000000000000800000000000000020000000800000020000000000020000000000800000000000000000000000000000000000000000003eb200000000000000000000000000000000440000000000009080000000000040000000000001000000000000a52040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000000000000200000000000000000000000000010004000000000000000000000000000000400800000000000000000000000000000800000000000220010800000800010000000000000000000000000000000000000000000000000000000000000000400000810001030000000c0000000084000000000002000018000000000000200000000004000200000000004400100000400000800020000000000008000480008400000000000200200008208608008000012220210020008400800000200000600000008028000218200000208000010024000800904400800090028010228000400800000000200a080000000000082000480000020408000000652040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00104084088202000080000806100400c0400003041040040020441041000449010228210000202410020800008810005000000000001040000010000000400000010200000008800420000020000000a104100010008000c0000020000800020000000400000000000000002000200084008000000200000000200200000088000008000201100100000000008000000000000000100000004040206100000000002100000000008004040000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000daed00000000000080000000000000000000200000000000000000e52040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000800000000004020000000000000801000000404020000000200200000000000008000200004000000800100000000020000000000000240000000008400000000000000000000000000000000200000200000000000000008000000000200000008000000020000000000000008000880000030200008c00008208810008001000220000000048408800000000208200040000000100000000004008000108200004100100204004008204002240000208002000008004000000010900000020400004080006108000000008102088084088200100004000000100000088008200000000000004110000008084002204200000002200152040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000004000000000080100800018000300800000000020000b01021000200c4c00c0000081004704010cdc00410410000020100820840008081000400040020101020001000000000000008000000000000001000000300020000000000000040000c01000010040000c080004000000000000000000000c00000100000000000000000004000c000000000000000000020008000000000000000000000000000000000000001000000000000000001800000000800200000000000000000000000000000000000000000000000000000000000000040000000000000060800000000000000000000000000000000000000000000000000c24000001000000000952040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000e7940000000000000000000000000000000000000000000000000000000000000000000001000000000000200200000000000000000000002000000000080000000000000000000000000000000000000000000000000000000000000000000000000200000000000000008000000000200000008000100000000000000000003000000000084200052100010408063310000a080000082000310000402400084100010210400010000000400000c0000000000010008400000001000000000020009000048a0000021000000000000000400000c00002c010800200040000008a00020022400000000000000000000020010040000000552040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0850022000800000020000000c0005800000001300a823800008a00a80060820008000020020804800850001100002120400020002800800001000029000001240001e00800069220002900428000801000800100400000000000820000820000200800000020100000000800850080420000000000820000000800000800000000000020000000800000000000000001004200048408040000200000000200a0000000800800800028120020000000000800200400000000020000000804000b210000000000200200000008008040000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000d52040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000b2480000100000000000000000000000001001408000000004000000000000001400800000004050008000000000000000000000000000000008001400040000000050000000000000020000000000800000000000000000000000000000000000000000000000000000000000000000000000000000100050001000000000014021800000102d00060000000015028100000008540c882000002150402000080005000200400000000000000080080002082009000a000020800900850ac8020000820000820000800000000000020000004020000800000020c200000014208e48008000352040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000040002001000000401100800000000000020000000000002001000001100000800820001200000154000002080000080000080000000000200800000040000002000000040404100800000008100420000000002000044000000050040100000000000000000000000000002000000200000000000010000000000000100000000000001000000000002400000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000800000020000020000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b52040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000841a0000000000000000000000000000000000000840000000000000000000000000010000000000200000000000000000000000000000000000000000000000000000000800000000002080040000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000100000010400400000012d844008804000010000200040000100004004000a0000440800000400001000000000000010000000000000000000000010010004000000000020400000010000100000000000004000000752040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000008002600002000000000040000140000000000100000000000000008041200000000001040000000000040000000200002000000040600004908008200000020000000000000000000000000008010008000000000986100800000000000000049200128d02101328010000000004d0018890a10083000000000000400000000000000000000000000000000000000100000080000813960000000000200000000000804000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000010000000000000008000000000008000000000000000001000000000000000000000000000000000000f52040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000609d00000000000000000000000000000000008008300010004200000000000008084000000010000000002010000000010000000000008000000008082200002000000008000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000100010008000180000080c92000000000100480010001400410000000000012000100000000000000120000040400000000000200000005000000000000080006100000000000012040000d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000800000050008008000000000004440008000000000800000000000000940000000000000000000000000008000000000100000010000000000000400000000000080000010000889000000000000944000c20000020800002000001000004020000008001121102000090000010000000010141200000040204020000042208122000001248000840000040000001000000000000088000000000000000000000000800008420000000000000008000000008000000000000000000000000000000400000012000000000000000000210000000000000000000000000000000000000000084008000000401000200000000000000000000000000008d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080800000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000538c00000000000000000000000000000008008000000010008200000000000008000000000008000000000010000000004000000000000000000008000000000000000000001040000020800200000000000000000000000000010000000000000000000000000000000000000000000000000000000000004000000000000080000000000000092000000002400000000210000000440044000000400000290000054000008000000800000082004d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (3000040200020000020002000000800000040000000000000004000000410000420001000080040400000000120000000000001008002000000010000001000100010c000000000004208000000000000000000008000209000010400040012000000001011484401420000000800000000280000000000000800000000000000000000030200800021000200000208200404001008408940110020200200000000004000000000000a0000000000000200000000020041000080000400000001001000100000040040400000000000000002000000000000008000000000000000000000000000000000000000000000020000020000000000002490000020000cd2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000004000000001002100000001010000000000000000000000000000000000000000000000000000000000000000000010000010000000080000000000000000000000000000000000000000000000000000000000000001ec20000000000000000000000000000000000c00000040000010041000000000c00000000080020080000204000004000000000000000000002000c0000000008002000004000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000042512042000000020020020c0000042100012052482000001880302000012042000002040004080002d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00040000000000002100000240104000000000000000000000248100000000200000000000009000000218000020010100000001040000000000041000000800000000000000800000000000000000000000000000008200000000000208000000000000000000000004208001040000000200041000000000100000000002000000000040000000000000000000049a0000000800000000104920000900120104020000400a04001500001520000800000000000000000000000010000001000000000000000000000000000000400120000000400000000000010000800000000000000000200000000020000000000000000000000000000000000000000000ad2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00800000000000000000000000000000000000000000000000000000000000180000040000242500000000200000000000000000000000800000000000000000000000000000000000000000000002000002000000004000000000000000000000000000000000000000000000000000000000000000d5840000000000000000000000000000000c000048200200000000000000000000049200000000000040000080000080000000000000000000000000041000000000001000100020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004104008000000002000001000400040402000000100006d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40000000000000010100000048000c00000000000110048000000800400220000000010008000000000400a4800004000020800000000000a000000008020000000000000400000002400000180008000000000000020000100040000000000000000002000010108208000400400208000000000020000000400440208001040020102000000000800998001000000000000000000400000000010018000000000004000004000008018048282000000c41001000200010000000000000c8000000002000002000000080000000000000000000000000000000000000100000800120000400000000000020000010000000000000004000000000000000000000ed2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000400000000002000000000000000000110000000040200000010000000000000000000010000000000000600000000000810200000000001040000000600000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000004e2d00000000000000000000000000000000010108000000000004204000000010101000001000400000000000000000000000000000010000000010100000000000401000000800000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000002000001d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000020000000000008000000400400000002010400004004818004800000010000000c00000420000000000010000000010000000000000200000000020008001800008861200800020000000020800000000000040040000008001e01000000002000000000000000022810000000000000000000000000000001060000000000019a00000060020000000160800000800882000000000800000010000018000100040000020100804800000000001000000240040041008808800061020000010080801800020000000800001024040004140000000400000001840001000000000000000000000040001800000000000000000000010000100401800000009d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000080008000000000000000000000000008000000000004000200000020000000000400000000200010000000000000000000000000000000000000000000000800008000000000008020000800800000000000000000000000000000000000000000010000000000000000000000000000000000000000400000000000000008000000000400000000000000000000000000000000000000005b81000000000000000000000000000000000000000000000000000000000000002020100000000b0000008408000400000000400000880000000000004000010000000000004100000300000000000000000000000c00c00000000010000000000200000000005d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002000000000000010000000000000000000000000000000000000000000000000000000000000000000010000000002c608000a18000000020800000002000000000000000010040000208010000000804040000840020004000000104000408000100000008004001008800a0010008000000000200001000000001000000000400010000000000008800020000000040000004000000800080000000840000000020080208000000000000000000010010000000020040000000000021010810000010400400410080000008010000412200000280c080410008218000000008208200000010008300080000000408000000000000000000000000000100dd2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00008008000000000004000000080000002100001040400040000000400000020000000420020000000000010000002000800080088000040080081000080000090450000000000000082001000000000080000001000020000001082040004000000000000000000000000000000000000000000001000000000000000000000000000000000000000040000000000002002000000000040000000000000000000000000000000000000000ef1100000000000000000100000000000000000000000000000000000000000000000000000100000000108008102002000000000004010008000000000100000000000000000000000040004000000000000000003d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000004000000000000000000000220220000000000801004000004000000100000000000000000000000000000000000008002040010002002402040000430010010c00000282412400010084088080028020000200400005000000044120880400001404001040040021080024800001000000000000010020404008050800000080021000000000081044000000040001000020820808800000000800000080000000800002044000000001000000800804c41000001000000008000002001040000000040002000800011401050040002001004000220820802000020040c3008603004203200209205200002000003000208200128100200000bd2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (11003010800120000412002090180900010010004410000104420212400000004010102500400000810000000000004004000000000000000000000400200000000840800020000801020004000000020800030430000000001000821800800000000020000000040800000002020128000000200000000000000000000000000000000000000000000000000000000000000000000000100000000000000800000000800000000000000000000000000000000000000000000000000000b3b800000000000000000000000000000000004000000000000104000000000004000008000000088000000200000200400000200001004004000004000000008400007d2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40000200000008000010001600400000000010000000000000050000000000000000000000000100000000000000002000002000000080000000000000000000000020000000004020002000000000008200020000000050000040000008080400014000280100020001008500000400800000000020800000000008800048000120080010000105204004220200042040008000124000002264000004000008000120000040088000000082040019041200000140204000001001a0014000000000810400000008008200000000000a001004204080001020040008004100004000080d0823012004850401220042011000400000004804229020820010000900fd2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000a4100200108048240128200000010804820000809a421200300008000010200000012600608200010442022081000008600010090000164002024000020000000400000000004000000000000000000020000000000000000000000000000000000000000000000000100000100000000100000000000000000000000000080001000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000093810000000000000000000000000000000100400000000004040000000000001600200000010018000000000000100000032040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (084102404004002000100084000000000000000001200000000002082001080080002400100000000000000000000000000000000000000000000000000000000000000400000000000000400000000000005000200000000040000000402100000044801000020012000040000820018809800001840b00a20000a4004000000010104200090400080000000014000048000100200000040101204000200000000022408110194000000240000804000004000000000040088040000026862801101200800a40000020000001100008800000008000000000048000c0000000000404104000004000100006000804000000000005000420020004810084810000832040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (84000000000000d00004000000000403200000013040aa004080004010080041401b0402155440100a5004134100000000004400010104000014c000000000000200000000200000004050808000800001000080400000000000000000000000014000002010800000000000020000000000000000000000000000000000000000000000010000000200000000000000020008000400402000000000000000000000c00000000c00000000000000000000000000000000000000000000000000c000000000000000000000000000000000000000000000000000000000000000000086b80000000000000000000000000008200101400010200004001400000400432040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000a002080000000040080000001000001003040401001000100000003040000040000080000020000a80000092080402022000080000000000820000000000800000000000000000000000000000000000000000000000000000000000000000000002900001001000000010040800010010002952c00000830200010c00021004802c2000443010014080003200000000000145000002000004000000000000000000000028000b0000c40028040201c00820008012000200000000040000002000000010145000000000400000900010044000010000001000000020000001080000a03000400000c00110000028a000000104004410401450020000000000c32040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000201403000800000000010000000001000000000000000000000000000000000000000000000000040a8002000028005000000000a00080000800068000000000000000000000000000000000000000000000000000000000002010000011200000a0000000100800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000004004000000000000400008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e870000000000000000040000232040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000347c0000000000000001004000000000000000000000000000000040200000000006000000808000000000010000004000000000000000000100000008000000800000a0000000000002000000000000080080000000002002000000000000000000000000000000000000000000000000001000000000000080044000000000000430000010000080000400300000000000000000000002000a0000408020000200000a00000080000028000004000000a00200000000a000000800000500020200000010040000000000000000000000020000000000000400000150100008001001400000000000000000000000000800000000000001400000a32040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000040000000480502494000000800006d08000000000000000000000040000800000000000020010000000004000000000000400004000000000000000000000000002000400000040200000000000000000000000000000000000000000000000000000000200000001000000000002800400000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000900a25000000020009b400000000004000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000632040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000070900000000000000000004000100020000000002008008001000000080000000008008000c000001000000001000000000000000000000000000200020020008000010800000000000100000000000010014000000000400100000000000000000000000000000000000000000000000000400000000000004008000000000080000000004000000000100a000000000800000000000000040000000000100040000000000000000000000080000000000000000000000000400802010000000080050040000000000001000000000000000010000000000000000280280000000000000000000000e32040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000100000000000280280000a00020006000000000000000000000000000020000000020000400000080800000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000800002000010000100000000200000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000132040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1c3000000000000000000000000000000000000000140000000000000028000000140140000000000000000000000a00000000000000000000002000140140080000000040000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000010200010040280000000000040000000000000000000000000040000080048001400010000280000000000000000000010000000004051400000000000400000000010000000000000000000000000400000000000000000000932040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10a420000000088090000000000002100000000008010000200200030130008040000800400000000000000000020001000220c089044848848302261021221000000000000800100200010002002008000400080000000100840000010021424020000200020204000008000800020001000008402000000000000000000000000000000000000000000080400110804010000011402300000400820044010000000100800000000000000000000000000000000000000000000000000000000000000000000000000000000000003003010210210090098408408400800000200040000000000000000000000000000000000000000000000000000000000000532040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000917700000000000000008000000800400000000028024000004000400802200a00008048000040000800200201000000010000000000000000400a000480280000200010844000000000022000000000800800000000000000000000000000040000000000000000000000000000000000004021000000000810901000040100223205200012000200040422000004001000802000080014020200020101100814001084042000000040100080040001004008020500002001000004001008400080020200d32040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00020500008000000800001008040000020211200000000008008000000000020020000000000000800020060008000000804000000000000000000000001000000080002090918448008400060a10210210000000000408000000000100050040000000000000000000008800200180204000a0000000020000000000000800108000000040002000000000000000000000000000000000000000000100200800880000000001415000000400020040010000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000404610200210180008408408400000200000000000000000000000000000000332040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8d00000000000000000000000000000000000000802408000000020000220020000800800400000000000010000000000000000000000000000020000800800000000a0880000000020026000000000000040000000002020000000000000000000000000000000000000000000000000001020000000000890800000020280215204200010000100020020100004000000800000000000000100008000100800000004000000800000100000000000004000b32040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800080004800140002000020000000080000000008000000100000802000000000000000001200000000040100000000001000000000000000040000001000100000000000008000000000000000000000020020002000008001000000001800000000000000000000000000000000000000008000000000000000100040010020000000000004400000400000010000000040000000000001000000000000000000000000000000000000000000000000100040000028008400000000000000000020000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000200000000000732040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000020000000c00c00100000030030008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000af5e00000000000000000000000000000000000010000000000000000000400c00000020000020002000500402000000010000000000000000800800000080000020004000200000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000010800100000000004a002800002000000010040080002000001008000000000011000002000001000f32040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (080004004020000800000000000000000004000008000120000000200000000000008000000002000000000000000002834000000000804880000000020020000000000400c00000000010000000000000000400000000000000000000000000000000000800000000000000030830020000000c20c0000000000002000000280200000000000000000000000000003000000000082090800014000004000000100000000000000000000000000000000000000000000000000000000000000000000000102040100000044200000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000040004002002100200a000840840000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006bc800000000000000000000000000000000000004000000000000000000102100000000000000000000000000000000004000000000000002402000000000000080000030200000000400800000000024020000000000000400000000000010000000000000000000000000000000000000000c0000000002202000000200010800888000000002000000100000008b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000020122080000000000000100200a00000100000400028005004000000000080002400108002400000004000010004000100000200000000000080000200110904010000020124200000000880900000000000000000000000080000010010000100b000000000100040000000000000000000000100022100010048088482804000a12210000020000408000000000000000000000000000000000000808000000000208040000022000002040000080000000880054000084000000000000000000000000000000000000000000000000008c00000020080110c0140000000000044000000000000a000000000000000000000000000000000000000004b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000148642514800005219094520000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e3de000000000000000000000000000000000000a00200000000001008000008000200200000200010002000008000400100000000000000015008000400200080200000804000000022020000000000080000000000000022000000000000000000000000000000000000000000000000000024000000000800882000cb2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000c1800000000003060008000001000c18282000000400000080000010000002000000400000080000010000002000000400000080000010000000000000000000000000000000002000000430600080000010c18280000000030600000000000c18000000000030600000000000c00282000000400000080000010000000000000000000080000010002521909452000014864251480000521900000000000080000010000002000000032600000000000c18002000008400000090000210000002000008400000090000210000000000000000000000000000000000000000030600080000000c18082000000430000080000010000280000000000002b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00601180000000014c2500004614e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001303774d9100004e0ddd364400000000210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000095e6000000000000000000008000000000028200000040000a000000000000282000000400000080000010000002000000400000000000000000282000000430600080000010c18000000000030600000000000c1800000000003000000000000000000000000000000000ab2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000eaea0000000003aba800000442100eaea188439555c0c0c000004421000000400110040000000004401220000000110a08888000004401222200000000008888000000000030300000820a3aba8000004400eaea3804800003aba800000000055550040000001555400000000000002888a02080000000000082000000000000000000000004888800004c0ddd36440001383774d9100004e0dc0000000000000254ce000000001d5003aba8000000000eaea0000ce22334f6c00004f64600000000157a3212300000421b900000000000000000000000000000000000000001555400007dc0055555b8006b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000001a9a800005fc006a6a5b801225480000000014c2500004614e000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012038f718e0000498e3dc6380000000030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b1d000000000000000000000002000000018842110840000620000000000042010802200000000020200000000000114400000000000000000042010802215554000020088555500000000015554000000000555500000000eb2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a6a0000000001a9a80000000006a6a000000000000000000000000000000000000000000000000001515000000000054540000044210015151884280b980c0c0000044210000004001508400000000054210a00000001529028280000054210a0a000000000028280000000000303000004029054540000054001515089420000054540000000006a6a0040000001a9a800000000000001014055014000000001540500000000000000000000004a8883535480e3dc638d4d52638f718e0000498e20000000000000014ce000000001a6000545401000000015150000ce22334f6c00004f64600000000157a3212f00000421b90000000000000000000000000001b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000420a60000000000000000000000000000000000000000001a8000053c006a6a318000a121a9a80000084620000404d20000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000190c200c72000066308031c8000000001900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075600000000000000000000000000000001884211084000062000000000004223088a20000000002200000000000000000000000000000000004223088a21a9a80000222886009b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000c5110406001a80000410186a6a0000000001a9a80000000006a6a0000000001a9a800000000000000000000000000000000000000150000000000545400000842a00151500c52651580000000020222030300000012a800000000004aa0000000000100800000000004aa000000000000000000000000000000000000a58080054000000400151502c52000005454000000000006a0000000001a9a80000000006a6a22c1a202a000000000080a800000000000000000000000088c000064308839c8000198c220e720000663080000000000000104c40000000004d000005400000000015150002206120000000005ac580000000006914000005b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2206104000000005ae510000000006914400000000422a700000000000000000000000000000000000000003015400001a8095555318040242555540000084620000400d60000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000180c883064000061b220c19000000000400090000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094b3000000000000000000000000000000000c52210a8000002000000000000c511040600000000041000000000000000000000000db2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (44240000000001019000000000000000000000000000000000114044270154000001109555500000000015554000000000555500000000015554000000000000000000000000000000000000c0ea0000000003aba800000852b00eaea008562d3a4000000000422b030300000604b4000000001812d0000000006012c000000001812d0000000000000000000000000000000000003190b03a8000018019eaea0081600003aba8000000000c055000000000155540000000005555010544153c000000001054f0000000000000000000000029850000603321c990000186c887264000061b220000000000000084c50000000006e00703a8000000000eaea000003b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (82002000020000000000000000000080000002000080000200000400000000000000000008000000000000000020000000000000400000000000000000000001014000000004000584800000000002000000000000000000000000082000000000000000100000000000000408000000000000000000020004000000000000910000000800020000004000000820010000000004004000004000100100000000000008100000000100000000000800000000000000000000000000000000000000000000000000000000000000000000000000001000000080000000000033ad000000000000000000000040000000000856214ac0000028d00000000000114000bb2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000200000000000000000000000000000000200000008008000000000000000000020000000000000000000000000008000000000000000000800000008800800800000000000000000000000000000005000000000000000800000000000008000010800001408010008000008000000000000200000000000008002080000080020000000000002200000000000000000000000000200000000001400004000010008c00020000200000001000000058200000000000200008000000050200a0004080000c02020000820020830800000000000002000204400020000000110000020400804410020000002000020007b2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2005200000000000000c002000600400c000a000031c48000c300000000818c0008000000200000000040000003030000048c000000010000000000000200000000000000000400000000000000000000000000000000000000400100180000010000000000000000000000000010000020000000000000080000000000080000200000008000000020000000000000004000000180040d0000000000000402000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000003000000008000000000000000000000000000000000000005d14000000000000400000002000000000fb2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002202000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000004000000800000000000800800004000000000000108000000000004000000000040000000000000000000000000080000000000000000000000000000000008000008804020000000020000c00003a020040020c800c21010820c18000000002000100010000000400180000000000000000000000018000200480000000000072040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0104208000000000000080080000000100002010000000400004000c00000000000000402400448200001248000000080000000000000000010000000000020048000001200000000000000000000080000000000000000000000000000000000000000000000000000400000408000000000000000000000000000000000004000000800000000008020000000000020000008000000200000000000200000000000020000000044000000000200000000000000000000800400000800010020000000000000008000000020000000000040000000000020000000000000000000000000000000000000000000020000000000000000000100000008000000000872040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000800000000000007c2d0000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000800000000400400800000000000000000000000000000000000000000000000000000000000000000000800000010000000000000000000000000080000000000000000000000100080000000000000100000000800000000000000000200000000000000080000080002000080000000000000840840000141280000c000820100000000000021100400000040002000082000472040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8400000200000000000008084104000000000000100000008080008000000104000200080000184008210100200401000004090004008000008204000208000008000008400000000000200000000084008200004104000000000004084000000000000000200080000082082000000000000200000c40080180141002009020000081008200000000000000001200000200200000000000801000001000000400000000000000001000000020080000000000000080010000000402000000000002081000000000000080040000000020000000000080000000000000000000000000000040000000000002000000000000000000000000000000000000000000c72040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000020000000000000be90000000000000000000002000000000000000000000000000000000400000000020000000000000000000000000000000010000000800800000010000000000002000000000000000000000000000800000000000000000000000000800000000000020000000000000000000000000020000000000200000000000000000900000000000001080000008040800000802102028000004808000900000200000000000000000000000100000000008400800000020000000000000408801000000010800000000000400800400040800a0102000000002844400272040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000011000a004400000000080020000000008000300000000020100000000000000000000000020000000001004000000080000120040000403004000000000020000040003013401200410019000000040000008300000008000000020000000000000200000000000020008000000001600000080000082022000200000200000000000220020120800808800000000800000008000000000000000000400000000600000000000000000000000080400000000004000000000000000000000000002000000000000000000000000000002000000000000000000000008000000000000003400000000000000000000000100000000000000000000a72040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000200000000400000000000000000000400000000000010000000000000000000000000000000000000f5d50000000000000000000000000000000000000000000000000000000000000000000000c00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000a000000000000000000000000000000000000000002000786018818000000100188000080006100000000012480080400080000000080010000000000000200000000000000000000000002200000000004000000000000672040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000010a8080000008000000000000000080080080000000140349000100005082082804002a00000000000080000080000000000000000004080000080020042a000220008000290805820000024000100000800800804c00008001428000000100800004820000800000020800000000801820000820020000000000800800800000000000020000000000000000020000020020000104280020000000000000000004000850298c000000000001200000000502004000000402000002000008400000000000000000000000010080000000000000000210000000400020100000002002248000000000080080000000000000000000080000000000000e72040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0a40000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000ee63000000000000000000005000040000200000200000000000000100400000000000000000000000000000000000044000000000020000000000010200000000005004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200a0000000000040000000000000000010000000000010090000000002140a01000400405480800400400010002090080000080000000280000010000200000080280000002000172040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0200000000000000000108000000200020000000000040400000000000000000040000000000000100000000000200000001000000200000090600000000000000000000000000000000000000000002000000848000004000031000000000000000020010c10000400000040000000000009200000000000008000880000000000000000002000000000000080000240000000000000000000000000000000000000000000000000002000008000000000500200002400010010010040000000000000000000000000900000000000000000000000000000000000000000000000000000000000000200000080000414100012004000000000884100000000000972040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000013080100004000482000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001002000000000000000000000000000000000000000000000004a1200000000000000000000000000000500000000800000000000020000000000000800004000010000000000000400000002000000008000010000004000001000002008400000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001804000108004001010028140000001000000000000000000000002000000000000000000000800572040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000800000400800010001000000000020030000000000000000000000000000000000000004000000000000020000800180000000000000000000004804900000040000010400220000001000000000000000400000000000010000000000000801014800808011000000001a00804196c10000000400000000000000004000002d20000020000000000002000000000000000000000000000000807df00000800000000000004000020000000000000000000000000000800004000002000001a98040078210100400001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c87000d72040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000020c00000000000000008080004000000030c00000000008000204001010000000000c200000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000002000000000000080004000000000000000000000000000000003ac900000000000000000000000000000000000080000000000000000000000000000000000010000000400000100028000000000000000400040600000000000000000208000000000000000000000000000000000000002000000000000000000000000000000000000000000000040000000000000000000000000000000080097000000000000800000000000000000000372040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000000800000002010000000000020000000c00000000000200008000000008000000000000040000000000040010000040400080000000000000400000000001000009020000000000000000000000048200000010c00000400000004200010000000000000000000000000000000000400000000004800008000010030800000000000000100006104000100000020000000000080000000000000008002080000001000000000000010001000008000000120800000000000200000020000000000000000000000000002000000008000000000000488000004210200000020000000000000000000000001000000000000000000000008000000000000000b72040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000004000000000000000000001000100000000080000000000001000000080104000004004004100000000100000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001000000000000004000000000000000000000000000000000009dad00000000000000000000000000000420000081000000000000844000040000002000000010000000400000200042100000000000404100010000080810000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000772040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000400000000000000000000000048020400000010040000083000000040800000000000020000000000400440000000000000002000044000004000000020000000000000000000000000000100000000000000400000000000000040000000008c40001000000820020408108044000000000000000001000100000000010000820000080001010044c000000000401081000000000000000000000400000010000020008004000000000000000001020000000000001000000800000200004020000000000000000000810000000000000000000000000000000000000808201002000000000000000000000010208000000000000010400020000200200f72040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000012480000000000000000000000010080020000000000000000000000000000000020000000000000400000001000021c04820800410020100000000001c0480100000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000005aca000000000000000000002000001004000000400000000000020400000000000000000100000080080000000001080000020000008200000000000081000000002008001000000000000000020000000000000000000008000000000000000000000000000000000000000000000f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000020000000000020080000000000000000000004820000000000004000000000020020000000000000000000000000000004000000000000000000000000000020000000000000000080000000000000000000000000024928400000400000000000000000000000000000000000000000000000000410000001000904820004920004100004000000021800000000000000000000000000c0000402000004000000400000000000000000020000000000001000000082000000000000000024000000000000000000000000000000000000000000000000000002400100010000008f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000020080000000000000000000000000040000000000000000820004000040000000000000000000200000000000000000000000024c00000000000000000000000008000010008100000000208000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000800000000000000a0f7000000000000000000000000081000000000000002000000008800000200000000000000000000000000000000008000000000004800000000000009100000000000000010000000000000000000000000000000000000000000004f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000100000000004000000000000010008000000c00400010000000000100000000000000000000440000040000080000000000000000000000000000000800000000400000100000000000000000000000110141040000000400000000000020000000000000000000002000000000000000000000000000040037100000001200e00000020000100000008000200000000000020010000200000000000080001000000000800000000000000000800000100000000000000000000000000000000000000000000000000000cf2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01800002000000000001820000000200200000000000000000000800100000000000000000020000001000020000000060000420100010800000000008000001000000200000008010010300000000000000000000000000000021010100000800000000002000000000000200180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000004a23000000000000000000004000000000000000000002000000010000000000000000000000000000080000000000100000000000000000000200000000000000004000000020000000002f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01800000800004000000020000000080000000000000000010000000000000000000000200000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000040000000000200c000004c804010000000042400000000090080002000000000000000010018018000000000001002040000000810810800c00000004020001000000034001811000400041000400090400400000000000000460000010000160a0000001c000000000000000200000040000000000020001060800000000800000018000000004600001001000060000000000000200000000060000001800000010000000000080000000af2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000004000000000012100300100000000000000100000000000100000002000000000020004900800000000000080000080000002000002000000000000000000000042000000000000000000081000000000000000000010000000008000000c0040000000000020000800000000000000000000000000000000200000000400000000000000010000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000100080000000051c5000000000000000000000000000000000000820000000000000800000000000000000008000000000008004000000000000800900000006f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000000020104800000000000824000020000220000000000000000000008000000000000000000000000000000000000004000800000000000000000000010000000000000000000000000000000000000000000000000000020000100000000000000000000000000805000001008000200240000081000020000000000040000a0000000000000000001000010000020000400000000000020000400000000000050000040032400010100000400000000000020004000041000000000000000034000000000000000000000c2008040000000000100040000040000403040000000040000000000002001001000400002010020022003000020000ef2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01001430000180000004080081002005080000004000000030000004c40002001040002080000081001105000004040045001000000000001104000088002000200400049430000000c2008208040208000208200008023000008480000000001080000000000080000040800000230000000000000284000004408200408c1040400402423218440a022420000080080040008000000200000000000000000000000000000000000000000000000000000000000000000000004000000000000400000000000000000000000000000000000000800800000000276d000000000000000000000000001020000000000120020000000000000000000400000000001f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800040000000000000000008000200080000080000080040000820000000000800020000000084000000041002008000000200000000000000000800000000000000000000000000000000000000000000000200000000000000000000000000010002000080000100004800020400002004004000004200000000000024010000000880004800100002290000100008000000100006000000000008002000000002000800000000000004889004801280000004080000000220084c20010004108000020200008100204100000000040200000008002101008000000040040000420004040100001000000028040084001401084002080040800000030c009f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10002000000002000000040000800000000404000100001044002000080186800100800000000048004100001200020000000880040000000102000410200050048020800400400200000400100012040000400000000000000000040260060480000000a00800000010102022000000000000040040010000000022220000000000000000000084000000100086000100110002180004000100084000000000000000000000000000000010000000000000000000002000000000000000000000000000042000000000080080000000000004000000080400000000000000000000000020000000000000007208000000000000000004000000000000000000005f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000000000000000000000000000410000004000000400000000001000048000000009000000000020000840000800400000000020000000080000001000000000000000000000000000000000000000010000000000000400000000000000000001000000000000000000000000000005000a00008000040000000002000000000405400001040400000000400018408202416400000000004208000000008108200200000208008004000000010000000004088088200a041008020100241040000210008000000404004000000000010000060008000041010000004188048000000000200008610008000000108282000280500400000802048000df2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0400002002410050410a00000802004824804000a010802200010000060080000000034900800634000824004000000000000410000000014048000130001200c0000080000004082000000000000020004004005400000000020000001020000004020800020000062800800ad40140240a0008000020820800000000200800200140000000000001000000000080000000c000000000000000200001044000004000018000000300b0820400820c20000020000020010000000400000000000000000000000000200000000000000000000000000004200000000008008000000000000000000008000000000000000000000000000000000000000000bf5f003f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000100000000000000097e000000000000000000400300000000000000000000000000000000000004000100004000000000100000000000000008000000000000000000000000000002410000020000000000001000000000000000000000000000000000000000000000000001000000000000000000000000041000000000104040000002001000108000000000040140040000061020001040001000000820800000009000000200a0000004000000000002000800000040000000a0000000004000000000800101800000010104200010000804000002000000a100001000340840004000000000000000044064000000001200000100000bf2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000030000000000000050e80100120400000030800c1000824308489000a800003100002001000c00140000000000004c00000c012c0100001000208000800009418400110000000000800000400000c000000000000000000000000000001500000000004048000000000000000000000001000210400200000408008008c0000020028004000000820800000000030a3020024000000530420000001400e142043000000000000014004000300210008100000c005002040200200000080000000000000000000000000000000000000000080000000000000002000000000000000000000000000000000000000000000000000000000000000800000000007f2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c00000000000032008000000000a00100000000000000000000000000000000000001192040000000000000000000000004008000000000008008c00000000c00080000000000000100000000000000000a280000000000002080000050000080000080010000000004000000100000000000000000000000200000000000000000000000000100000000000000000000000004100000030000800000000000400000000000000008000080000010c010004100044002040000201000014010000800000000080020020000010000830800000000028c02000005030810800020800c0000101080001000008000048000000001010c00001000040000000020000ff2040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000b021000080024000000000000200000000000000000000000000000000000000000000000000000000a0000008800800004000800000000000000000000000000000000020100002000c000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000002800200010240000400000000000000000000000000000000000100000000000000000000000080000000001002002800000000080080010011021003010082e000204000020020809400000000000000000000000000000000000000002000000000280080000000004008000000000080000000000000000a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000c00000000000000000000000000400200000000010000000000000000a00000000000000000000000000000000000001709000000000000000000000008000006018000000000a00680000000000000000000000040200020002008020000000000280300000000014000000000000140000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400050100000010001000000000020000030000800200000000000000000000000000080000000000000000000000000000000000000000000000000800000000000000080a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000040000000000000000150002000000000000000000000a00000001000000000000000000000000000000000000000000000204145000000208000200000001000000000000000000000000000000010000000080000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000028002000000000000002010042a001000000080040000000000000000000000000000000000000000000000000000000000000000810000000000088008000000040c40214008000000800202a0120000001400000000000000000000000000000000008008000000000000000040a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000001000000000000000000000001000000000000010040000000000001000000000000000000000000000000000000000000000000000058b00000000000000000000000000002000494000000000006c00000000000000000000010000000000002000094000000088006d000000020000b4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000a00040040000000004010000000100010000000000000000000000000020002000000a0000000000000001000c0a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000001000000000000000000000000005000000000028005000100000000000000000002811000200000000000008004000000000000000000000000000000000000000000000000000000010000800008000100400000200000200000000000000000000000000000000000000000000000000000000000000000000000000000000000021000000000000800100000000000000000000000000000000000000000000000000000a00140002000002000000a0000000100000000000000000020002800000000000000000000000000800800008000000008000000000000a000050000008080000800000000020020120002008000000000000000000020a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020041020010800300240000000000000000000000000000000000040400000000011011000000000080440000000010012000000000100240000000000011000000000480300000000000001000000000000000000000009e53000000000000000080000000004001000000000000000100000000000000000000000000400008002004008000000000000400000000008014000000000000a000200000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000004000000000000000000000000100000000020002000000000400000080000000000000000000000a0a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (04000800000000020800400010040000000000000002000200010040000000000000001000100000000002000400000020000000000000000420220088088000000002000080008000000000000000000000000000000000000000000000000022008c004208408082000010202100800000000000000000000000000000000400000000000000000000000000000000000000000000010000002008000000000280240000000000001000000000000000000000000000020004000000800088400008100020101400008402000000000000000000400010004000000000000000000000000004000100000201202000000004008000010008242104400000000060a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400000000080080001002820002040000020020001020010800800040000000000000000000000000000000000040440000000021001000000000100440000000002006000000000400040000000010000000000000940880000000000000000000000000000000000007ebe00000000000000000000002000200800204084084030002102102100000000000000004080000800000c00c04084084080052102102100100c8408408400804000200240000000000000000000000000000000000000000000000000000000000000000000000000000000008001000000000000000000000000000000000004040000000010084000200000480408008080000800e0a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000100000002000000800000000400020000010001000080820002000000400000000000000020000000000400000000000000000001000000000020000000000600000000000000000001800880080000000000000000100000010000000000000000000000000000000000000000000000090804000580006000008006100000000000000000000000000000010000400000000000000000000000000000000000000000000008000001001200000000000040000000000000000000000000000000000000000020000000000800020400000000008000800000000000000000000000000000000006000000000000000000000008804000000020120920010a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000080200000000002081000000000280040008008280000008000022000000000000280000000000000000000000000000000000000000000000000000000000000000000000200000000001029000000000000000000000000000000000000000040000000000000000000000000000000000001b1a000000000000000080400000000010001840800840400060021021000000000000000040000010004020021840800840000021021021020008840840840080400001020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000090a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000028004000100000000000000000000000000000001000080200000000000000000000000080000000000000000000000000000000000000000000800000000000000000000000040100000000000000000000000000000000000000000000000000000000000000000000001008001020040041010020000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000004028000000000300a00000000000000000000000000000000000000000000001000000000000400000000000000000000200000000000000000000000000000000000050a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000001000000000000240244000000000000000000200400202000040010003000000000c0000200000000000000000000000000000000000100000000000004004000000000000100000000000000000000000000100000000004004000000000000000000000000004000000000000000000000007c9a0000000000000000000000000000080000000000000000000000000000000000000000000000000000010000000000000000000000000010000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000d0a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000200000000040300000000000004000000800008101020000000040200004000080800000000000000000000000080000000000000000020000000000000000000000000000000000000000004008400080800000000000000000000000020000000000000000000000000000000000000000000000020000500000000020100800000000000000000000000000000002000000800000000000000000000000000000000000000000000000000000040000000000000000000000000004000000000000000000000000000000000000000000000400000000000000000020030a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004000000000100002a28082400000000008002000000000000000000000010000000000000000000000000000000c003000000000000000000040040000001000234800008040000000000200240010020000000000000000000000000000000000024004000000000101100000000020004000000000800800000000000024000000000000800000000004000000000000000000000000000000000000000fdbe00000000000000000080000000100000000030030014000000c00c00000000000000000000000000000000400030030000000000c00c00000100030030000004000000a0000000000000000000000000000000000000000000000000000000b0a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080800000000080100000008004004080080000000004000000000000000000000100000000000000000000004000100000000000000000008000000000000000004000080000000000000000094210e00000400000000000000200140004000000000000000000000000000000000000000000000a0c0040042d08281002000c8400000000000000000000000000000000000000000100000000000000000000000000000000000000000000000010111000000000540400000000000000000000000000000000000000000000070a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000028000000000000008000001000000000000000000008000001000000000000000030600000000000c18280000000030600000000000c18082000000430000080000010000282000000400000000000000000000000000030600000000000c18000000000030600000000000c18000000000030600000000000c18000000000030600000000000c000000000000000000000000400000000e59200000000000000000000002800400202900080084010000002102100000000000000000020000000200400100080084034050002102100400c0008408400001000090240000000000000000000f0a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (094520000148e400001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000280000000030600000000000c18002000000430000080000010000280000000000000000000000000000000000000000000000000000000000000000000000000000000280000000000000000000000000282000000400000080000000000000000000000000000000000000000000000000000000000000000282000008400000080000010080000000000000000000000000000002000000400000000000000000000000000000000000000000c18080000000030600000000000c0000008a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000555529000000015554000000000000000000000000000000000000000000000000002c2c000000000000001404000002c0000003002500000000000000000000000d4460000000000000001555400000000055550100200001555400000000055554000084aa200000000212a800004038084aa0000000000000000000000000001555400000000055550000000001555400000000055550000000001555400000000055550000000001555400000000000000000000000000000040040000000000e118000000000000000000008000001000052190945200001486425148000000000000000000008000001000052190945200001486425148000052190088a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (100004c0ddd36440001383774d9100004e0ddd3644000138372008800000000000000000000000000000000000000000000000000000000000000000000000000000000003000000000000000000000000000000018842000015554000000000555500000110040000000004428000038082000008888000000000000000000000008888000000000000000000000000c0c000000000000010882000000000000000000000024541e4aa00000000042000c0000000000000000000000000000000000000000000000000000000006a01c9577c00000000255df0000000000000000000000000000000000011111c0000000000000000000000000000000000000048a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000006a6a2900000001a9a8000000000000000000000000000000000000000000000000002c2c000000000000005484000002c0000000082500000000000000000000000d4460000000000000001a9a80000000006a6a0800200001a9a80000000006a6a72000c02020000000030080000072018c0200000000000000000000000000001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a800000000000000000000000000002006200000000000007000000000000000000000000448000004c0ddd36440001383774d910000000000000000000000044000c8a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (12638f718e0000000000000000000000000000000480e3dc63800012638f718e0000498e3dc63800012638a22880000000000000000000000000000000000000000000000000000000000000000000000000000000000300000000000000000000000000000001884200001a9a80100000006a6a000001508400000000054a4000008812000002828000000000000000000000002828000000000000000000000000c0c00000000000005281200000000000000000000002040df0a340000000042000c0b000000000000000000000000000000000000000000000000000353501140056e0d4d40000015b80000004000000000000000000000000000010011c0028a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000093b00000000000000000000000000000000000000000006a3380000001a9a80000000006a6a000000000000000000000000000000000000000000000000004444116b0000000000000009462000000000000000000000018c40000000000000000001a80000000006a6a1104000001a9a80000000006a6a2000064031a9a800001900c0000205106403000000000000000000000000000001a80000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000006a6a00000000000000400000400000000008be10000000000000000000000044080000480e3dc63800000a8a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000008400000064308031c8000198c200c72000000000000000000000000000000064308031c8000198c200c72000066308031c8000198c24101800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c520000001a80000000006a6a00000012a9a9a8000000402000002948000000000000000000000000000000000000000000000000000000000000000000020200000020148000000000000000000030300411602f00000000042000000000000000000000000000000000000000000000000000000000000002c92c1b1800000000306c6300000068a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000001011431a94000000000c6a5300000000000000000000000000000000000287b40000000000000000000000000000000000000000c055338140000155540000000005555000000000000000000000000000000000000000000000002000c0c7009c00000000000000846b000000000000000000000018c490000000000000003015400000000055552084000001555400000000055550a0150072555540000401c900000a15500724000000000000000000000000003015400000000055550000000001555400000000055550000000001555400000000055550000000001555400000000055550000000000000000100000000000000ebb80000000000e8a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000005a700000000000000000000000084090000603220c190000186c8830640000000000000000000000000200000603220c190000186c883064000061b220c190000186c88110900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010800000000000000000000000856000030154000000000555500000604b5555400001804b0000008540000000000000000000000000000000000000000000000000000000000000000000042000000010500000000000000000000303020976a37c0000000042009000000000008000000000000000000000000000000000000000018a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00890940002404022004600020000800000000002080084400080000000110000600400080000000000800000000000000024620020000040910000000000800000000000000000000000000000000000000000000000000000000010030002000910000000000800020000000000114200400000000100004000000008004000000000020100000b009440080000200000590000000000002000001000000000000000000080000082000000000000000020014000000000000880000000000014000800000000000000000000000000000000000080000800000000000000000200000000000000000000000000040000000000000016000000000000000000098a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000001000000000000000000000000000000000000000000d0cb000000000000400000000800000000000500000000000414000000000400000000000000c00000010000030000000000000000080000000000080000000000000000000100000000000000000000000002000002080000000000002000080000000000000000000000022000080000000000000000000080004000000000000000000000020800000000000000000000000000000000000000000000000100000000000000200800018000120000000800000000000020000010940000400200024420004000000140000000002000800080004000020000000000014c0000000058a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0400c10000001010000048000308400004200000000000000000100000000000008012000000410010480010000000000000000000010000600000080012000000000000482000000002000000000000000480000000000012000000000000000000000000000000000820000480800000000012000000000000480000000000012000000006000000180580000012000400000000002010000000000400000000400004140000000000100000200000000000400000000800000820c000000000000000000000000c1800000180000000010000000000000000000000000200000000000000004006006000000000000000004000000000000000000000000000d8a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075c4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000400000000000000000000080180000000000000180000000000000400000000000010000000000000000000000000000002000080000000000000000000080002000400060000000000040100001040000000000000000000000000000000000000000000000000000000002004000000000000000000000000000000000180c0000000000000000000000000030000000000600400038a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000040010002000000000000000000000000000008040000001100003080000042000881000002008013000000020000600000000000000000000000000000000000000000000000000000000000000000000040000020000000800000000000800000000000000000000000000000000000000000000000002080000002010008000800000000000400020000000000002000000000000080000000000000000000000000000000001081000000000024000000200000000000000000800000000004000000000000000000000000000000000000000000c0000000000000000010000000000000000000000000080000000000000000000000000000000b8a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (008000400000010080000008000010000000000000000000000000008000000000002000008000000400000000200400000000000000000000000000000000000000b32f00000000000040000000000000000000000000000000080000000000040000000000000080000002000002000000000000020004000000000000000000000000000000000000000000000000000000000200000200000000000000000004000000000000000000000000000000000000000000000000000000000100000000000000002000100082000000000000000000000000000000000000000000008000000000000400000000000012000000080000000000002000000040000078a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (080000084008000000000000000000480004010002080000080000002004000080000000008000000000020284008000800408000000110410008010104020400004030000080100000000000204000100000000084010804080400000000000000108004400010204008008000000000000000000004000000000020108000000000000000000000000000000030c080040040080002001000002000002040000000010201200108000000000000000000001048000880041000000000008000000200008801010a03100400000020000000000000010004400000000000008400000000000000080000000008008000808000800000000002020000000000000f8a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020001020000000060200000001800000000000000100000044020000000000040000000000008000000000000000000000040000800000000000100000000200100000000000000000000000000000000000000315100000000000000000000080000000000000000000000000000000000000000000000000080000000000002000000000000000000000000000008000000000000000000000000000000000000000000000000001008008000000000200000000000002000000000000000000000000002000080000000000020000200000008000000000402000000004000004000000000000010000000000000000000000100000000000000080000000004a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000800000060000000900000024000004008000000000180000100000002020000000008100400000000230020008000000020000000000008002000000200000400100c000000200000104020405004030000028000000000000004000100000000120000000088001000000000008000000000000005001800000068100000000000000000208000008040000040001800003000000000000300086100003203200000400100000409200400208000000020101000800000000008300000000050000023000000000000000000200000000000100088840000000000000002030000000000000000000000080200000000000000000002000000200084a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000008008000000000000006102800000000000001000008004502800000200000000000008000800000040000000014000008000000000018000000000000408000000040400000000000002100000002d00800000000000000000000000000000000000000783b000000000000000000000000000000000080000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000100000000000000000000000020000000000000010000000010020000800000000c0000000800000020010000000000000780000010000000400000680400c86000000044a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4800002010002000400000080410080000000000000000080080000000004080140040000400400080080000000000010000841028080000800810a004000000400a8000000008002000000000804005080880000000a000102022840a80800000008200000000000000808000400000020000000200210000800000000820100000000000800810c200128200008008004008000000000000000010208000048048000040000000000000000800000000000008014008008000002800400009200014208000001002d40000000000000008000000000501000008008200000002092c028000000004800020000100800000050200000000000020004800000000c4a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000009001010000000000000000000000000000000000200000308000008000900000000000000020000000000000000000000000000000000804000000002100000010000000000000000000000000000000041200000000000040000000000000484000000000000000000000000000000000007cd5000000000000000000000000000000000a0000000080802800000000000000000000000000000000000000000080000000000000000000000014010000000000000000000000000000000000000000100000000014084100000000502000000000000000000000000000000000001000000000000000000040000000000000010000000405020024a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000001000000000000000000000004000050000000000000000000400000000000000000000000000000000000000000000040000000000000010000000000000100000000000000000010000000012002400000000000000001000000000000080010000da40004864000000000000400030000000000000040001000002108242000000400208800000000000000000000000000000800000000000801000181024000000000000001000003000000001000002000000000010000000000000000040000080001200000000808000000000000000000800000000001000000000000000008040000200000000000000000000100028004000000000000000a4a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000920000000000040618248180020000000000000000020000000100000c0000000000004000000000000000000000000000400000000000020000009000008000000000000000000002400000000800860000000000000000000000002000000000000000000040020002040001000000044800000000000000000000000000000000000055af00000000000000000000000000000010000400000800000002000000200000000000000800000000000000000000000000400001000000000000000010010000000000000000000000000000000000000000000000009000000000000008000400000010000000004000000000000000080000000064a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00040000000000000040000000000000000000000000000000000000000800000000000024000000000000000000000000000000000000000000000000000000000000000004000000000000000000000400002000001000c000000000300000002000000100000020000020009004100300000002c2000201000800030004000000000000111008000010000000000008000808008108064808000000c0040000000000001000000100020000000c411188000800000001010000092801700e2100000000021002000000000000000001000001040000000000040400042000043200021001080001000000000000000000040000041000000000000000000000e4a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000042000000080000000000000000000000000800000000000481000300000000010000008200000000000022000000000000000000200000490000008000000000000800000000000000100000000000000000008000000400000000081000000008000000100000000000201000000000001800004000000204000100000024000000000000000000000000000000000000000e0a0000000000000000000000000000060804000001002101000000040000000000000000000000000000010400000000002080000008000000000000800000000000000000000000000000000000000000000000000806b000000000000000000000000014a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000800000000000000001000010000000400000000000000000000000000000000000000000400000000000000000000000000004000000000000000000100000000000000000000000000000000000000200000000000000000000010000000000020000010000000000000008100040000000100000080000880008000008000400001248000a48008010088000400000020000008000000000000000000000100820408040000020800000000000000000000000000004000000000000204000000000400004000000820004000004000000000000000000000000800000800000000000000008820c00000000011040000000208000000000000000094a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040420128020880244800c0480000400012014200000040000041000000082000000000000000084020000090008001000000008400000000000020020020000000000010000000000000000000000000000000000100000005040400002000000105100008040008000000000000000000004820000000c000008000000000000000000000000000000000004a8400000000048a408420001200800100000000000000000000000000000000000348300000000000000000000000000000000040000010820010000000400400000000000001000000000000000000000000020c00000800000020000000000010000000000000000000000000000000000000054a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000040000080040c0000100010002000000000000000040000000080010480000200000800000000000000000020000000000000000100020000000004000000800000000000000000000000000000000100000000000004000800000000020000040000001000000020000000100000002140004000200a002409000000000000004000800020000221430041288844482000000001000010040c01000000100010000040041030050000420808040280000004000000000000100440000201000000028a00120808a01021000400010100100828200010200020900000000000000000000100000104008000008020c000d4a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c000000000000000000000000000000828800200500000005000084100084200000000000000000000000000000000000000008000000000004000041000000000002000004000400140000000010000000000000000000000000000000000000000000000092000000000000000000000000482440000001000000000000000000000000000000000000002080000000000000000000000000000000000020001000004001000041000000020000000000000000000000000000000000000007887000000000000000000000000000000000c0000000000001000800000000000000000000000000000000410000020000000800001020000000008000010000034a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002000000000040001000000000000000010000000000000000000000000000000000000000001000492040000000010400000000000000000000000000000000000000000000000000000000020000000001000000020000104000000800000000000000000000000000800000000000200000000000008000004900000000000000000000000000000004820000000000044040000000000800400000000000000000a21000000000000004000000001821000000000000000004004000000000000000100a0500000501000140010020000000000400000000002800000002080802011000020020082800010000040100081810800000000800000000000b4a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2000000000010b00040008200600000000000000000000000000000000000000010182400000000d00000000000210100000000000c0124020000000000000002000040000800000000000020000000080000000020000100100008000000400000000000000000000000000000000000020000000000000000800000000200000060000040000800000000000000000000000000000000000000010100200000000000000000000000000000000000000044200000000080000040000c00000000000000000000000000000000000000000329c00000000000000000000000000000000000000000048000000000000000000000000000000000000000000000074a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000100001000009000200020010000000002000000000000000000000000000000000000001000010100000002000400040000000000000000000000002080000040000000000000000000000000000000000000000011084000000000440000080000000000000000000040000000000000000000000000000100410000002000002000000000000000000000008000000010000200200000000008000000000000001000000000004002080000020201000000000008000080800000200000000000006010000000000209220010000018000000000800000000000000005400000400000601000000002028000f4a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010000000000200000400000206000400000000000040000000000000000000000000000000000010000000002080000800000000080000000408000000a06000000008200000000000400002000000020000008200000000000000000200000000000010081048000141000420100200000001000000040000080000080008008800000000000006000008108004000000040000202000000000000000000000000810000000000000000000000000000000000000000000001880000000000081800000000081800000002102000000000000000000000000000000000000000fd710000000000000000000000000000000012020000000800080000000ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000004000000000000000000001001000000000000000000000000000000000000060000000000000000000000000000000000000000000000000000000000000000001000000800000000000000001000000800000000000000800000000800000020000000000800000020010001000400000000004000000000020000000020000014000018000040400001000000400000000000000000000800000000000030000000000000000000020000018000040100000000020208000000200060008000008000c1000000004400000840000410000000000001804000040000000040000000000007000880000000008000100000000000210000008ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000010000000000200010000000000000000000008000000000004000800080000000200000000000000800100000200000000000001000010000080000000000000410000a18400000001000000000000000000000200000000000000008000000008000108000000004000000000200000020000104800000001031240041000004000200140000000000040002000000000800008000000000200030000000c0800000000000000022000000000000200000010000000000000400000000800000000000000000000200410001040008010000000000010000200400000200000008a000000000000000000000000000000000000daba0000000000000000004ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000bcb800000000000000000000000000041041000000000800040004000000000000000000000000000000000000000000000000000000020020000000000000000000000000080000000000002000000000000080082000002080000000000000000000000000000000004000000008000000000002000000000000000800000000000000000000000000000000000020000000000000000000441000050000000000000400000000000000010020000000000000000000041000001040000000000400000000000000000000002000000000000200000000000000000008000000108010000000400000100000004400200040000000000000cca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (012800001000120043008090000000040000800222108000000000808420000000000000800000000000000002000440200000820000000000000000520100004004004400000000400000000200008004010002080000040000000080400000040000000200000000000000008000100000204008010200000004008000000000000000040000203000008000000c40000000220000000084000000000000000000000002000022000080000100030000000c0000000000100000008000000001000000000000000081000002000000000400080000000000000000000000020820001000000000000040000000000000000000003000000000000000000000002ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a088001000001040000000000000000000000000000000000000c2cb0000000000000080002000000002082080000000100002000000000800800000000004010000000000000000000000000000000002002000000000080004000000000000000000000000000000000000000800000000000000041000000840400000000000000000000000000000400000000010000000010000010000000400000000410004010400020000000020000008000000040000200000001002100000080000000000042002000000001048000000000000000440020000000000008000000000040000000000002008200001080000c100000100000048001040120808000000aca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (42000802000000040100000100001080080004100040002000040101002000040000001000000048280040000041200000082021042081080001002000040080000042082104800040002000010042000000002a00020080080400021001081801880084082000082000000080000081800842800000021002080082000080002028040000000244800001800a20080080002042080020010020080000000000004000000000000000005000000000000000000000000201406820002000010000200000004000820004084100000200000001008200020010000000000002000000000400000000000000020000000000040004001000000004000040000004006ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000002080000000000080000002088000001200020000000000000000000000000000000000000fb310000000000000080002000000000000000000000000000000400000000000000000002040000000000000000000000000000000800000000000000000002000000000004000000000000200000000000004008200000208000000000000801001000000000000001000000000001000040000240001000040040000000800000000080004202040000000000001000004004000000020000000000000880800000000080000004020004001000000800000200001004000420000000000000210100000000000412000000000a18400000a100eca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80c00000000010000000000040090100002041012001000100200080d02002000202030080082000211c08000002008003080024000080d04212000002090188104000042000001180040000001040000042c040000010000500000010000100090000002010023108800804000100010400006802800828200420840018004228908100140008401c88020800010120802600000000080000008050008000000800800020020a0000000020400020000000104400000210020008400000480000000000000000000000004820000000000210000001800000020004006000100000004800008000020000000000000000000410400000080000000800000000001ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000001001041000800000000000800010000081040000000002144c00001400044000080000000000000000100000000000000000000000000000000000042ae000000000000000000000000000000000e000000000000100000820000000000000000000000000000000000000000000000000000000000000c00080000000000000000000000000000000000000000000200001e1400040005902000024000000000000000000000000000000420000000000000000000000020000000000000000049001001440000000000000000000000000000000000010000000000000000000008010000200000000000000000020000100000000000100000800008009ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000003000034000004090000100001480000000140008c100000001010100000000000128000000000000800020041000440400801020400080030400c00011000000c800110000404c0400423000000000000000000400010302c000010004000c003001040008880000a000000000800000030088020c020000000000000000180000000000030c02808c30424040c2120108110005000012c00100402020001090204000000f0440004402000000a000280000500100000200002400200020000810400000c1000005048000a800000000001320000022004000000000000101210000010480002800000002000d0000003000000000000000000000005ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000010000002800000000000020080000000000000000302000000000048060000000001800a000000010c020000000000000000000000000000000000000000000076db00000000000000000000000000000000000000000000001000010400000000000000000000000000000000003000000000000004000000000000000000000000000000000000000000000000000000000000800000c400100004202000050000000000000000000100000000000410000a0000000000000000000200000028000000800201020880000000000000000040000000030000082002080000830000000000800204080008040000000000dca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000090000000020002000000000000010000000000400008000000000200000400000000800140000000210000000000000400000002008000080000000002008100000180000004000100000000000000000000000400000001a10000000048410005000080200008020000800340000200000004000000000000000000000000000000000000a000000000000102000100000001000c8002400050000000000000000000000000000004000000000000028000000140000003400000000400000000000100000000000000000000010000408000000000000000000000000000000000000050003ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000800000000000000000000000002000000000020000000000000000004000000000000000000014040000000000000000000494000000080012d000000023001b4000000000004c000000000000000000000000000000000000000004cd0000000000000000000000000000c00200000000020000000000000000000000000000000000000000000000000000000001000040000000400000200000000000000000000000000000000000000000000002002000200000000000000000000000000000000000a0000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000bca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000c001000000000000000000000000000000000000000000000280000000800000000000000020200008000001020000800048000000000000000000000000000000000000400000002000000040000000000c0010000000000000200040004000000100000000000000004000008200000000000200000000000000000100200000000000000000000000000000100000000000480200000000000000000000000000000000000000000000000000000040100000000010000028000000040400000a00010000000000000000000000400028000000000000000000004000000000000004000000002000000000000050000000000000000000000002000007ca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010000000000000000000000000000000000000000000010000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000080000000000000010000000000000000000000000000000000000000000000000000000002aa000000000000000000000000000000000000000000a028000a0000000000000000000000000000000000000000000002000000000000008402000080204000000000000000000000000000000000000000000200200090088008040002800100000000000000000000002800000000000000000000000000000000000000000040400000000000000000000fca040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000a00028001005028000000040000000000000000000000000000000000000000000000000a00000000000000000001000000000000080000008201000100000008000005000000a000000000000000000800000080000080000000000000000000000000000000000000000000000000000200000000000000000000008000000000000000000004000000000000400040200000000000004000010000000000000000000000000000000000000000000000000000000000001002000000000100000000280000004000000000100000000000000000000004000000010000000000000000000000000000000050000000000000080002a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010002000040400004504800080944000002000000020000000000000100040000004000000000000000100020000002004001000040080100020000802000000000000000000804000200020000000009003000000000000000100120408408400000a1021021004020840840840000121009022000000000000000000000000000000000007a440000000000000000000000000002008000000000020000000001400000000040010000000001000000000000000000000040000008000002000000000000000000000000000000000000000000000000000020020000000400804000000000000000000000000000000000000000000000000000000000000082a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0802000200020000000000000000000000000000000000000000020000080001000400202000020000000000000000000000000000000000000000000000401000020010000000000000000400800020000004220011080040004000002000000200008000002000000000040000000002000421004000010040000200000000000008000000800000020001000040804140000881000200010040000000000000000004000001000240008000401000000200000040000c0100008004800002000080040000000000000000000000000000100080002804900020000008020000100003004100000000002020000000000000000004000200040000000000000042a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000004000200020000000000000100000000404000004040000014840000040000800000000000000001000000008040000000000000001000200000020060010000000000800400000000000000000000000000060002000600000000040090000000000000000800984080084020002102102102200684084084000004000102600000000000000000000000000000000000231300000000000000000000000000008088000000002401200040010000000000202100000000088008000000000000000800200010020010201001080110000000000000000000000000000000000000000001001000090030010020001000400000000000000000c2a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080020000000000000400000000000000008000002000600000000000000000000000000000000000000000000000800010004002020000400080000000000000000000000000000000000000000000000000000000000000000000002000800000080000400000002800000001010000002000080000000002000000000080000010000a000000000004000040000000004000800000000000800000180002100002000800080020000004000000000000000000400000100024080800000400000020000800000040000000000800000000000000000000000000000000000000000000000000004880040000000060000100002404100020000000040000022a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000001000000000800000000000000001000000000000000000000000000000000000000000002000000400000080000100028000002000000000000000000000080000000000000000000000000000060000000008000400000100000010000400000000000000000000008000000010000000000000400000000000000040000000000001008400000000000000000000080000000280010000000000000000000000000000000000085ed00000000000000000000000000088008000000002001200040000000000000200200000000004010000000000000001800100014040000000000000000000000000000000000000000000000000000000001001000a2a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000008008000000000000000000000000000000000000100000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000080000200000000000400020100080000000800000000000000000000008000000010000000000008000000000000008001000000000000408330200000000010000404100010000000000000000000000000800100100000000000000000000000000000000000080000000000000000000000000000000000000000000000000000100000004400000000062a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000100100000000000000000000000000000000001200050000002000000000000000000000000000000000000000000000000000004000000000101000200000000000000000000000000002000400000000000000000000000000000000000000000000001000000000008000000000000000000000000000000000000000080000000000000000000000000030030000000000c00c000000000300300404100004008000000000000000000000000000000000000fdb00000000000000000000000000010010000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e2a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000020000001000800008000000000000000000000000000000000000000002002000004000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000010800400100000a080000004000000000000200000000800000000010000000000000000000000000010000000000000000000000000000000000000002000000040000000000000000000000000000000000000000000000000080020000800000002080000000400000000003000400000000000100000000000000000012a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (008000280000000000000000000000000000000000000000000000008000280000000000010000010000000200100000400110c02000000000000000000000000000000000000000000002000000000000000041080040000000000100040000000000000000020000000000000000000000000000000000000001000040080100020001004000000000000000000800000000000000000001001000000000000000320110008008403002800210210000080008408404000000110200000000000000000000000000000000000085e000000000000000000000000000004004000000000000100000000000000000000c0000000002000000000000000000000092a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0010000000000000400c0000000000000000000000000000005008000400080000000000000000000000000000000000000000002002000100300100200008004000000000000000000200000000000000000000000000000000000000000000001000000000000000040000000000000000000000000000000000000000000000000000000040080002001400000000000000000100004000401000000080000000800000000100000000004000000000001000000002000200020301040000800000000000000000000000000000000002000000030000020000002080000000000000000000000000000004100000000000000000100300000000002000040052a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000210002080400000000000010000000002082000008400000080000200000000000000000000000000000002282000000400000080000210000282000000400000080000010000000000000000000080000010000000000000000040000000000001002800000000000000800000100000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000800000100002820000004000000000000000005219094520000148642514800005219094520000148e40000100000000000000000000000000000000000b08a000000000000000000000000000000200a0000000400000000010000000000d2a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000004000000000000c1800000000003060000000000000000000000000000000000000000000200000040000000000000000000000000000000000000000000028200000040000008000001000000000000000000008000001000000000000000000000000000000000080000000000000080000010000002000000400000000000000000000000000000000000000000000002000000400000000000000000002000000400000080000010000000000000000040000000000000080000000000000080000010000280000000000000000000000000000400000000000080000210002280400000000000010000000000000000000000000080032a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00e8b800000000000000000000000000000005a95205e2290000000014e8000000000000056800ebb1c000000003380000000000000000000000000000000000008420080080000002131000000100220108101000000802000000000000000000000000804200000000000003d7f40000000000031002011800000000000000d40100000000000000408800000000000000000000001fc3000000000005000000000001740000000000000000000000000000000002000800001884211084000000000000000004c0ddd36440001383774d9100004e0ddd36440c013837044210000000000000000100000000000000000068b900000000000000000000000000b2a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000855b000000000000000000000000000030300400000000c0c00000000055550000000001555400000000000000000000000020000000000000000000080004000000000000000000000000000000000000000000002888a0208000000000008200000000000000000000000046000000000000000000000000000000000001880000000000000005eca9000000000820a000000000000000000000000000000000000000000000000001100400000000000000000000000080000000000000284c0000000000035454000000000000067000000000000000020046030c2000400000c00000000000000030000000000000000005b9561d00429580000072a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (30000000000000000007f9501d001119e00003e8b800000000000000000000000000000005a44245e2290000000117e8000000000000056800e7b7c000000003380000000000000000000000000000000000008420080080000002131000000100220108100000000802000000000000000000000000804200000000000003fff40000000000031000151800000000000000d40100000000000000428800000000000000000000001fc3000000000005fd000000000157ec0000000000000000000000000000000000800000188421108400000000000000000480e3dc63800012638f718e0000498e3dc6380c0126388442100000000000000000008200000000f2a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (98c20842a00000000000000000000000000000000000d75d000000000000000000000000000030300400000000c0c0000000006a6a0000000001a9a80000000000000000000000200000000000000000000008800000000000000000000000000000000000000000000000101405501400000000154050000000000000000000000000000000000000000000000000000000000001880000000000000005eca90000000004029000000000000000000000000000000000000000000000000001508400000000000000000000000800114000000000a44cfb0000000003fffc000000000000025000000000000000020157030c0000400000c000000000000570000aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0010e800000209000800000000000000000000000000800000000004b01800002037000000000000000020000000000000000000000004180400003380000800000000000020000004c0010b128000000005100000000000000000000000000000000002109802028000000001101800001045002020000000000080a00000000000000000000000080800000000000000000000000400000000022110000000000000018c20000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000001000000000c52210a80000000000000000064308031c8000198c200c72000066308031c80001008aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0c190000186c883064000061b220c190000186c88c72b000000000000000000008000000000000000262000000000000000000000000000030300000808000000000020200006a0000000001a9a8000000000000000000000000000000000000000000001040000000000000000000000000000000000000000000000022c1a202a000000000080a80000000000000000000000000000000000000000000000000000000000000080000000000000004282a000000000250080000000000000000000000000000000000000000000000000012a80000000000000000000000000000000000000002000000000000000000000004000000073000000000000000004aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000007f01000000000000000114500000009400800000000000420000000000000800000000005301100000d3ba00800000000000020000000000000000000000004148000003381000800000000000020000004c0110715c00000000510010000000000000000000000000000000210980242c0000000015210000010054024240000000004b0b00000000000000000000000090900000000000000000000000000000200011114000000000000018c29000000000000000000000000000000000000000000000000004200000000000000000000000004200000000000000000000000000000000000856214ac000000000000000006032200caa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000580004000000014100000000000580000000000016000040000000000000000000000000000000000005636000000000000000000000000000030300000108000010000004200c05500000000015554000000000000000000000000000000000000010000000040a400000000000000000000000000000000000000000000010544153c000000001054f0000000000000000000000000100000000000000000000000000000000000080000000000000004292a000000000211080000000000000000000000000000000000000000000000000604b40000000000000000000000000400000000006242000000000008002aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000040040000000000000000000000000012138000000000800000400080000020000000000005000080000200140010010000000000000000000008c00200008004420200000000080200000400000000000000000110010010000044400410418000110401004000404500224000000004000000000004400000000000110000000000004408000000000110000000000008800020000000000008000000804400000000008118010000000005000000000000000000400000080000000000000000008000000000050000000000000000001000000000001040000000000000000000450000430040101400000000000050000000000000000000000aaa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000004000000000000100000000000000000000000000000000000000000086c100000000000000000000000000000000000000000000001400001000000002000040000008000001000041008200001000000002000000000000000000000000000000000000000200000000010000000000000010200200000000000208000000000000000800000000000000000008000200000000200000000000001004000000000140000105000000001041002020000040000000021001010000022000810800200001000000000000000000000000006aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000000800120000000000020000000000000000002012c0020084000048900000400c4100002000000804800000100000100000000001800000100000000120000000000004802000000000000000000000004800010000000010000000000004800000000000120000000000024800000000000000000800000004800000000000120000000000000000000000200120000000000000000000000000000000000000000000000000000000000000000800000000000000120000000000000000000000000000000000000000000000600000000008000000000000000400000000000001000000000001040000000000000000000000000000040000eaa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000400000430000000000000000000000000000000000000000000000000000000000000000000000000000000400000000010000000000000000000000000000000000000000000000000000000000000000000db73000000000000000000000000000000000000000000000000000000000000000000000000000000000c0000040000000002000000000000000000400000000000010000000000000000000000008000000000000004000000000000000000000000000000000000000000000000000040000200000011000000000000000002000000000080006082000000000000000000000000000000000000000000000000001aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000000000000000000001000000200008800040000000020006000000000000800000000000000100000000080030000001400000101400000040000000000000000000000000000000000000000000000000000000000000000040000000000004000000000000100100000000000000000000000000000000000000000000000000000000000000000000040000002000280000000080000000000000000000000800000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000009aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000080000000200084040000000002200004000004000000000000200200000000408002000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000008000000000000200010000000000000000000000000000000000000287200000000000000000000000000000000000000000000000000002000000000000080000008000002000022000100002001000000000000000000100000000000004000000000000100000000000000000000000000200100000000000108000000000000002000000000000000000000000000000008000000000000000000000000000000000000000000000000005aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100000000020020001000000080000000000002000000004040000000000080002000000000000100000000000004008000100200100002200104004008188004208004206000000000400280008400200204100200084008200002200000102100208084c88184110100010204210100000000000000000002006000a00004000800000204402206100000106404108108100032206104c1080000000000000000020412000008801010810000400040200000020010418008800400800040000010011008000000048000800000008000001000400000000000100000020010400808200200210440002401001002040000000102101000000004000000000daa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000881000004000000030000000000000100000000800000000000000000000000000080000000000000000800000000800000000000020000000000000800000000000000000000000000000000000000000000000000000800000000000020000000000000800000000000020000000000000000000000000000000000000000050f100002000000000000000000000000000000000000000000080000000000002000000000000000000000000008000000000000002000000000000000000000000000000000000000000000000000040020000000002000000000000000000000000000000000000000000000000002008000000000000200000000000003aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000020010000000000000400000000000000000000000000800000020008060020820000000800800400000120020100000000004004000000020000030000000000010000000020000000000000002000041060400020000000000010001040040000000900002000000000080000000880000002412022000400000400000406000000004800100004080480000000021a049000000000800800000000c00100000000030804800800240300108018000008404081000020260040008004000004800000000000120020000000004040618000000100008000018600201e0002800000004000000000400000000004014020002000000880000c20000400baa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000004202d08008003481080208200248000008000000000002012010000000080000210000000000420000002000480400000000002000080000080008080008102a022000003240a8010000028140a00000000000000000000000000000000000000000000000000000a0000000000002800000000000014000400010002800000000000000000000000000000000000000000123e000008000000000000000000000000000000000000000002800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0000000080080000000088000000000000040000000000001000000000000000007aa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000004000000000000100010000000000000000000001501210000000054240000000000000000000040040001000000000000000000000008000000040800000001040020000000000000200000020000008008000020200200201200308028808508008000000201a00000020002d0002400000020020120000840850002020000020020020800000a8080000000002082002000800000000000004940a802020000820004800020220020a20002020a10800810c0004042002000010040000000100009000002000000082080482080000802a000000028020a9000080080080a020000020020a8400080002400002000000080000080080000000a000100faa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000400002000000000000000000000008000000000000028000000010040000000000000000000000000000020004100000000002000000000000000000000000000000000000010300000000010080000000020000400000000000000400000000000000000000000000000000000000000000014004040000000000000900000010010001010010400400000000000000000000000000000000000b98f000000000000000000000000000000000000000000000000000000000000000000000000000000000000040140244000000000000000000000000200000000000000000000000000000000000000000000000000010008000006a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000001001000000040800001101800082000001000000000000040000000000000000000020040000000000800000000000000000000000000800000000000000000000000000000000000000000004400000000200000100000008000000000000008000000000000000008000080800400000000000002080004000000000000000000000010000000000000000000000000000000000000000000000002010004000000000000000110b011000000000004000000004040000000040000004000040002000400000110020004000100002000004000010000010100000000000000000000000020000000042000000004000000000000040086a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002000000000008000000080000000000000000000200000000000000000000000000000000200000000000020400000000020000000008400000004000000000000000000004010d20040000000010400000000000000000000000000000000100001208000000000440000000400001008000000000010000000004000020000040000000000000000000000008008718001801001000401060048068200009001201a1800000000000000000000000000000000000017ec000000000000000000000000000000000000000001200000000000000000000000000008000000000000000000101000400000000000000000000000000000000000000000000046a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000000000000000000800000000000000000000000000010000000018000000000000000000000000000000000000000004000000004000108000008200000000000208000000200000000000000000000000000000000000000000000000000000000001000000000000000000040000000000000000000000000000000000000000000000000000000000100798000000800000400008400080000000001000000400000180400014000000000021040000000100058400020000000000102080000510880000000008004000000000180081000120000004129600041404100030000000040050a400800020000000000100000000414000010000000000c6a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0480008100000080000001400000000000000000400000004000000000020000000000000000000800000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000002003124004000000000820000000000000000000000000000000080000000000004000041020000024020020000000000001040000000000002000000000000000000020000000000804000002000100000040000004800000000000120000000000000000000000000000000000000000041bc00000000000000000000000000000000000000000040001000000000000000000000000000000000000000008049a0000100c0000026a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000000000000000800000002400000004000004000004000000200000000000000000000000000000800000800008000002600001081000082000000400000020000040000000000000020000000000020000000000000080000000000000000000800000000000000000000000000000000800000100000020000000100008000000046000000000000084000000000020800028800001000000000004800400040000000000002000008800020010400000000040400040000400000000000000000000001020008000000000000008000002408000000100000c0010000040080002010000800020022540044010820400800000041000808040500000a6a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2010409000210014200000040480840488100200204002200008000040c0000100000001042000000010040080000100401000000004000000002000001000000010000000040000000002001200000080004000000800021000000a484000080400000000000000000000400000828000080000100000000000000000000000000000000010001040004001000004001100000000000004000000000000000000400000000000000000000000000000000004400000400000300000000040008c00000000001310000000000000000000000000000000000000000068f7000000000000000000000000000000000000000000000010000000000000000000000066a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000040000200000000000000000000000000000000000000800c00000008400000000000040000000000000000000000000000040000000000000000008000000000041010000000000848400000040020010001020400000420010040800040840000020000000200000000000000000000000000000008000000000000004000000200000000000208100000000200000400000000000000000000000000000000000100000000200011200000000000000840045200000000000004000000000100200000000000080000000000001021208000000100900024032000000000020000142400220000400000000000800201000000810a10200000a0900e6a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00004000000041000001100000810820910004a02a20004000804100000000020008180431000001014000100004000000000004100020000000100000000000000000000100000000000000000000200000000000000000000000000800000100000124004000000000200000000000200000000000000000000000000000200000000000000000000000000000000000000000000000000001000000000000001004000000401008000000000000000000000000000000000000000000000400000000000028200000000000000000000000000000000000000000000000000000000000000000000000000000ed79000000000000000000000000000000000016a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (e0f4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000082010840000000000000000000000000000000000000000402000000000000000000800000000000000000000000081802000002002004000001040000001000006000410040004000010000020000000000000000000000000000000000000000000000800000020020000000010000000000010000000000000000000000000000000000000002000000000000000100000000000000000020000000800000000080002000000804000002000000000000000000034000000800010aa090700003000000000000480050000100000000096a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000080000038100000000600000080000000018900000000001cc80000e00401b00100020002008000000800000341000a0040200400000000000120000000001000c80000001000020000000000200802000000000000020000000000000000000000020000000000000c010000001000000010000000000010000000100000000000000000000000000000010000000000000000000000000000000000000000000000000100002000800800000080000000000002000000000000000000000000000002000000000000000000000002010000000000480080000000011010000800000480c0002000000000000000000000000000000000000056a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000009ed30000000000000000000000000000000000000000000000400000000000000000000000000000000000000001010000101080000000000022000000000000000000000000008000000000000000000000000802000002410000000800000420000000000000000000000000000001001004000000000040000000000000000000000000000000000000008000000000000000000000000100000000000000000000000000000000000800000000000000000000000000800000000440008000000000100400000200c00000000020000100000000008440000000400100000800000000c0000000800001412000d6a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000020000000000000000000008000408000000000000080000a00100000010200000000000010000000008010000000000000000604105000002080000104000000002000008000400000000000000000000040000000000000000098000000000080000000202000000000000000000001a00000000000000000002000000000000000000000000000000000002000000040000000008020008220000000000000820800000000000000400080000080400000000000080000000000010800800000000000020000000000000000000000000000000400000000010000000020000000800008000980000000000000000000000000000008000000006000000036a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0410002400000000482080010400010400010000000000000000000000000000000000002f500000000000000000000000000000000000000000000000100000000000000000000000000000000000000000800000100110000001081804000000060000000000000000000000000000000000000200200002000000000000000000450000000000000000000000008200000000c00000800000000000000000000000000200600000008000000000000001000000800020000020030000002880080400a10000800020040800100000024a00004000001000002000000000804000000038884008060200202086004000000008008408a0000800000000000000b6a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000110000100040001040001008200008000120808000210000400401004200000000000000000000000300008810200000200000200008c002000002000002000000000000022000000a001000000040000000800000000800020000040000800000028000000000000000000000020000010000000000100000000031000000001000000040040000a08001001200000000240200800080028008000000800201c0100001000000000000000000000000000200000000000000000108c08080000000010404080000000000000000020000000000000000400000080000012000000000000400000800010000400000000000000000410010000080090076a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000880000000000820002020802000010010822020c26120820884c310208200020200008000000000000000000000000000000000008df8000000000000000000000000000000000020000010400000c000001000000000000000100000000000000000a0000000004000100000000000000000000004000000000000000000000000800000000000000020000008000800040000040040000000800000000000000000820000000020000000000000000000000000000008000000400000014000000100000000010000000000000600000000000000000001490408000000202200000000002080000000002010000000000000000000000000010040000000f6a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000800000000020804000000000000004000000009000802201000000100004100000004080c1000000000000010000004020000000000100800400a081040004844048000040001024004000000010000000000008000000020042000c2400000000000008040000114840400000000401000000000200000000040000000000000000000100000000004400000000100000000000000000000000008080000002020000008008000001000200200010100008000000000001000001040000000000040000020040002000000000002042000000000001040980000000000000002000000080001000000020000010000000c00000000000000000000000000ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000800000000890000000000000000011808080020080008a000000028020000010000a02480002000000482000000000200000000000000000000000000000000000000000057b60000000000000000000000000000000000000000082100002000000400000000000000200002000080000000082002008028000600888000800000000200410000000000000000000000000000000000000002000000100000000008020000000000000000000800000820440000040020041000041000011040000000000000000000000000000180000000000002000020000020048000001000000200810000809020000800000040020800000041000000000040008ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (06000214000000000000410000000000228200010000010000000000020028040000000220000001601490005800000000818000000001210124010000000200440020624010220000020010001401012010110506000808814000a22000400820100400010000021804000200004120012010010004000400220000021000000408801400400000100000000000020800008800004820108004200808204004000004000100000050104000400410000028210010060000000400008004804000000114680000010810000008000000282080000000128100000020000800002020049008000020000000000a64040008009000800a00200020000802000001004ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040008009000000240000000001100000008000040000000000081000000000002000001280008000008000000000000200200000200008008010c0082080000002000000000000000000000000000000000000000000000000084c40000000000000000000000000000000000100000000080004000000000000000000000000002000080000400108000002020008200000001000000000000000000000000000000200000000000000100100000000000010000000000820000000000008a0000100000926004000000004820000000000004000000000000000004000000008000000000000020820800800000010808820000020800010060000000000000cea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000400410000010400000000000000008000420000000000040000000000080000020100010010000000000401021020000000001000000000200021010000200000800040800000200110000020000230008020820011e20000000081000000050002114180043400816800480000200411d0001002000071040481010808ad90821000200104000402440615cd201100000883000100000010e02080000005033000080001482c110024100160806004000004000100000000104000000010000820000000420010b30000000004800000000150400000000800282008000000080080100000008000000000000000002000049008000000000000000204002ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000300000040000000000000000080300000000000040001100000000a0000001200282004000000300430000000c001054000000000000000000000000000000000000000001000000000000008000000000001000000000000000000000000000000000000000000450a0000000000000000000000000000000000000000000000080000000000000000000000000000000000400810882002080082000080002002000000000081000000000000800800000000000000000000000000800000010000000002000000000000000200000000000001000009040c0904100004103000104020000000040000000001000000040000000010410400000000aea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000080800002000000030000000042000c01000800090010405401001000000082480082020808a081000000010c000000000080400000408200000010048003083200000b3010800000420400048400100000028002880004c100080140200c000000300020808000003001001a00440000148000084810c0081008000100320800800304c0000c810000010410430d00008820001009008000010150c4000042000480000000404001400141000000000400000000020100020040000549000000000000d2003000000003000c000000005004000000800041000000000000004100000008002000002000241200001000100000200000100120820000006ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000080440000000000001000040000000000000000000000000000000000000000010000080800000400000000000000000000000000000000000000000000000000000000c000000000000350050000000001400000001401600220000000000000000000000000000000000000000000078a8000000000000000000000000000000000000000000000000000000000000000000000000000000000b00004080800000000000820000000000000000000000000000000080080020000000200000000a000000880000000002001000001001000c0030040140000000001000208300030000000000000000000000000000000000eea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000003024001400000100010000000000000000000000000000000000000000000000000002000000000000400100048040008010000000000300000080008000010000200000000000000000000800000000040008080000000000000400000000000000000040000000204000001000000800200000000000a010000280480000000000000a110810050280000000000000000100100000005000400000004000450900010040000020000804000090000004000000400000000004004000000000100800000000000000000000000000020000000000000000000000000000000000002000000000000000000000280020000000000380000004000100000001ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000040000000000000000000000800500000000000000000000000000000840a00030025000000000000000000000000000000000000000000400140002010000000000000004200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000004ee10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000008000380020000000000000000000000000000000000000000000001000400000100010100000000004800000800100000010000000000001000c00250009ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40000000000204000000000000040080000000000040900000a0000000000000000000000000000000000000000000000000000000000008001000000000000000200225000000001020b4000100044012d000000004000300000000000000020000000000200100000000000000000000000000000000080000028002000000000000000004000000000004000400000080000000000000004150000200000000000000000008005080940010000000100000000100000000040002000100000000001000040800080000020001500400000000010000200000004a000000000000000010000000000000000000000000000000000000000000000000000040005ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000400000000000000000000000a004001400000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000040000000201000000200001020040004000400000000000000000000000000000000000000000000020000000000000802000000000000000000080080800a00000002000000000000000000000000000000000000117e000000000000000000000000000000000000000002020000000000000000000000000000000000000002000000200010140410000002000000000000000000000000000000000005000000280a25000100000000b4000100020046d000dea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008000000000001c02802200400010000060000000000001800000000000020000000002901000200000000000000000000000000000000000000000000000000000000000000000000004000000000000000100800000000008006000000000100880000000010001000000000040a000000040000000000402080000001002000000000000000000400000000020008000000000000000000000000000204000004000000000000000000248800000000000000000000000100002008401000000080000004280084020000020000000000040200000000000008000000000004000000000100000000000000000800000000000000000000000000000000003ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800000080080000000002000000000000000000000000000004001000000100100024000104004000800040000000000000000010000000000000000000000000000040010000801101000400000040000000000000000000000000000020004000400001000440009000120010000400800000000000000000000000000000000000000000000008000008040200a00000000008020000028028a00800000200800000000000000000000000000000000000fe18000000000000000000000000000000000000000002008000000000000000000000000000000000000002000000140810000000140a00000000000000000000000000000000000000000000bea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000010210008804818a192100400c84484c8408400212a142100000082102480000000084020000a00a211240100080800000004000000000000000000000000000000000000000000000804000200020000000010010000001010211210140128408428404804210210a101000284084084008080002000200800200000022000220005040200000000000000010000000800010040000000001000000000800202000220040000000000000000040400a90489028000000000000000200430030008810220011000248420000840408800000000000002200c0000803000804000080020401000100100000042000104028007ea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000020000000100000000000000006008001800000000000010000000000000000000000000000000000000000000000000180024000104044000800000000000002000000000000000000000000000000000000008008000100902000200000020000000000000000000000000000000008000000000800221000840000000000000000000000000000000000000000000000000000000080018000018002200200000000008000000008008602000000600000000000000000000000000000000000000b101000000000000000000000000000000000000000002008000000000000000000000000000000000000014012000080290042400100200000000fea040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000100120004804900824200000020000000000000000000000000000000000200220000000618a08a10000018488418400001210619a100800000206480000000004088000a004000042000080800000004000000000000000000000000000000000000000000000804000200000000000020010000004610a00a100000a8428458400004a102106100000200084080008040000000201000000004001000000000000000000000000000000000002000018000000000000000000000000400000400048008000000000000041000180009048000000000000000600008080044004000000000208108001001000000000008000000201000000098000000001a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001000000000020001000000040008000020000000000010001000000000000000080000000000001001000000000020000000000000000000000000000000010000000002000240000000000000000200000000000002000000000000000000000000000000000200000002000008004000000000000000000000000000000000000000000000000000044000040800000100000000000000000000000000000000000000000000000000000040000040000008000000000000a0000020020100000000100800000000000000000000000000000000000b87f00000000000000000000000000000000000000000202000000000000000000000000000000000081a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000001001400000000000400000000000000000000000000000000000000000000000200000000000008000000400000800004080000020000000200000000000000000000000000000800404000000002000000000000000000000000000000000000000000000000100200000000000000001000000800100100040024000000000000000000000000008004000000000100000000001000004000000020006200008000000000000000000000031000000000000000000000000000000000010001000940000000000000000000000200480880000000000000001000f00000200000a0000000280008002020041a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00008000000000002028000202480400a0002009000000004080000001400028040000000001000200000001000800010400001000000000000001001000400000080000000000000000000000000000000000000001000000040000000000000000200000000000000000000000000000000000000000000000100100000000000000000000800000000000000000000000000000000000000000000100000100001000000000010000000000000000000000000000000000000000000000000000000a0000000000000000000000000000000000000000000000000000000000000000000000000000f815000000000000000000000000000000000000000000c1a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000001001100000030000100000000000000000000000000000000000000000000000c00000000028c20c00000000430030000000008c00c0000000000092000000000002000000004040002000000000080000000000000000000000000000000000000000000000004080000000000000000000400000000000c00c00000000430030000040000c00c00000000030030000000000000002800100000000000000000000000000000000000000020400000000040000800000000000001000000000820000044000000000000002800000008048000000000000000021a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000040880042000000000000000000300140001000000004000300004002080044021080020000002000100020003000001002000080000c0400a0000001000300000000000000000000800800000000020000000000000000000000000000040014000000000000000000000300000000401000000000000800200000000000000000000000000000400400008008000000000100200000000000000000000000000000200000004010028100210108004200080000000000000000000000000000000000000000000000000000000000000400010028000000000400a0040020800202800001000000000000000000000000000000000000921e000000a1a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000082c8000000000000000000000000000000000000000000000028000000000000000000000000000000000004000000800040000000108201000000000000000000000000000000000024020000a80240820821015010012840840a8030022186100000400806280000000000080000800a008c00300000000008004000000000000000000000000000000000000000000000000000000020000000000000002c004006002100a010000840840280000021061008000000840800000000010000000004000000200004000000000000000000000000100c0000000400020080000000000000000000001001200000040000000061a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000800002000022820000084000000000000000032824000084000000000000000022820000084000000900002100800024000084000000100000000022824000084000000800002100000000000000000000800002000000000000000000000000000000000000000000000000000000000000000000000000000800000100010000000000000000800000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000001000000000000000000000000000000000000000000000000000000000028000000000000000000000000028200000040000a00000000000000000e1a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000018c42110840c0c63108000000000000000000000000000000000000000853d0000000000000000000000000000000000000000000000000000000000000000000000000000000000000282000000400040080000010000000000000000000000000000c18000000000030614864251480c18521909452030614864251480c18521900000030600000000000c1828200000040000008000001000000000000000000000000000000000000000000000000080000010c18000000000030614864251480c185219094520300148642514800005219094520000000800000100022800000000000000800000000000000000000000000800000100000000000011a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000bc6000000400000000c00000004400000002bbb6eee0000000000000000ab6e2b6cacc0000000000000000000010114ea7a8000000029560c750000117cc0e8e800000000000007298c312a4000000004aaac02000040000000080800001540004020000000000100800000000000000000000000000000000000004030000000000101000000804200000000000000000000000104600000000000000000000000000000081d00000000000400000000000000000000000000000000000000cd230000000003f83000007cc4351c000000000000000000000000000000000000000000000000000030318842000000c0c01000000091a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000030318842000000c0c010000000000018c42110840c0c63108000000000000000000000000000000000000000e1a1000000000000000000000000000000000000000000000010000000000000000000000000000000000000042010802200004000004200000000000000000000000000000555500000000015555303774d9155554e0ddd36455555383774d9155554e0dc000015554000000000555573a2002080000000000082000000000000000000000000000000000000000000000000000020828555500000000015555303774d9155554e0ddd36440001383774d9100004e0ddd36440000000020a0000006008200003130000006b00000051a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001000000004001200000130000006b000000000000000000000000000346000000400000000c0000000440000000319bfeee00000000000000ffab160002fdd8000000000000000002201820f3400000000322460c00004011bddbebe8000000000000076bad312a400000000521bc02000040000000080800000880004020000000000100800000000000000000000000000000000000004030000000000101000000804201ce00000000000000000001046000000000000000000000000000000800004000000005d4000000000000000000000000000000000000000000000000033a3000001cc0101c000000000000000000000000000000000000000000d1a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000c52808000c0c000020200030300c52210a80c0c0314a020000000000000000000000000000000000000210000000000000000000000000000000000000000000000001000000000000000000000000000000000000004223088a2000000000000000000000000000000000000000006a6a0000000001a9a92038f718e6a6a498e3dc639a9a92638f718e6a6a498e200001a9a80000000006a6a77800550140000000015405000000000000000000000000000000000000000000000000000100a46a6a0000000001a9a92038f718e6a6a498e3dc63800012638f718e0000498e3dc638000000031a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (31c9a9a998c200c72000066308031c80000000009408000048148000000000000053a0000000001000000000000000104208030000000000000000000840000007cb792c068000000000000000007f0091e04800000000000000000400104429800000000080dcce00000006706800000000002000000230980a2a8000000004acce020200000000000000000030200000000000808000000000020200000000000000000000000000000000000000000000000000020a0800000000010000000000001004000000000000000000000000000000aa0000000000000000000000000000000000000000000000000000000000000808000000000050420000000000b1a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000010800000000001c420000000000108000000000000000000000000000000000000000000000000856108000c0c000004200030300856214ac0c0c021584200000000000000000000000000000000000002e42000000000000000000000000000000000000000000c0c00000000000000000000000000000000000000000c511040600000000000000000000000000000000000000000006a0000000001a9a990c200c726a6a66308031c9a9a998c200c726a6a6630800001a9a80000000006a6a7b800202a000000000080a800000000000000000000000000000000000000000000000000009402006a0000000001a9a990c200c726a6a6630800071a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0550000000001555580c883064555561b220c191555586c883064000061b220c1900000000008411000048050000000000000053a0800000001000000000000000104308030000000000000000000c60100007d1594c04c000000000000000007f1500794c00000000000000000022100035c00000000416c5c2ea000006b948000000000020000006f2b80289c000000004a4d7020200000108000000000004a01000000000108000000000004200000000000000000000000000000000000000108000000000004b0900000000000800000000001004000000000000000000000000000000a21d00000000000000000000000000000000000000000000000000f1a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000200000000010000080000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e6a000000000000000000000000000000000000000000c0c000000000000000000000000000000000000000000114044240000000000010000000000000000000000000000c0550000000001555580c883064555561b220c191555586c883064555561b2200001555400000000055557f8004153c000000001054f00000000000000000000000000000000000000000000000000008442c0009a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000001400010000000000000400000000000021000000010400000400000000000000000000000000000000000000100000100000000000000004000220000100000000000800000000000000000000000000000000000000000000000000000500004000020000000000000000000800000010000004000000000400010400000000000000000000400000040000000000000000000000800000200000000000000000000000000000000000000000140000000000005000000000000140000800000005010000000000000000000000005001000000000140001000000005000000000000140000000000000000000000000000028000000200000848002000089a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000003000000000000000080000000000000000000000000000000080000000000000000000000000000000000000000000000000000010000010000000000000000000000000000000000000000000000000000c000000000000000000001000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200200080000008808002000000200080000000002082000000000c020000000000000c9a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000020820000000000020000000000000000000000000000000004000000200000000000001000041008000000000000000800000000000001000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009f880000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000029a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000080000200001000000000004000000000000000000000000000000000004000000000000000002000000000100000000000000000008000000000000040000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000800800800000020020020000000804800a9a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000040000000000001000000001080240001000000001080000010000000000000002004040080000000000000000000000080041000000000002000000000000000000000000001000000080004000000000000000000000000000000000000001000000000040000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000a9860000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000400400000000069a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004008000000100000200000004000000000002000100208000008000000000000000000000000000084000004000200000200000008004004000000002104200020108000000000000900000000000000024004104000000100000000008004000010000000180000000080000000000000000000000000000040100000000000000000000100000010400000000000410000000020010000001200400400000000e9a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001040000002000100000080090004180000000000000000000084000000000002100000000040084000040000002100000000000000020000000001000000c000000000000001000000000000000000000000000000060000000000000088000000000020000000000000000060000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000a6860000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000008000000000000000000000000000000000000000000000000000000019a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300000004000000000800020000000030000800000000000000000000020800000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000400000000000000000000006400800000090000000010000000800000000000000000000000000400000000000000000000000000000000000002000000002000000000000160000000000004000010000000000000000000010020000410000000900099a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000021000000000400040000000009221000000000000000000000000000000000000000800000000001081000000000000801000000080000002000000010000400400020200000000000000000400410000000000010000000000000000000000000010000000000080000000000000000000000000000000000000010000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009c4b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000059a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000002000000000000080000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000020000000000000000000000000000000000000008008000000200000200000008000000000000000200208000008000000000000000000000000800008000000000200000200000008000000008000000008200040008000008000021000000000000000040000000020000200000000008000000008000000200000000000000000000000000000000000040040000000d9a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000004000001000020000000000000802000000000000000000000082000000000000040020000000008040000000000004000040800000000000000000001000000000000000000000000000000000040000000000000000000000000000000000000000000000080000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000093dc0000000000000000000000000000000000000000000000000000000000000000000000000000000000000039a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000080000000000000000000000000000000000000000080000000000000000000040000000000000000000000000080000000000000000000000000000000000000020800000000000800000000000000000000000000002000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000800000000000000000000040000000000000000020000000000000000000000000000c0000000000002000b9a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000008000000000000000000828000000000020000000200000200000008000000000008000000800000000012010000000000480000004000032000000040080480000000024000000000000000484001001000012000000040000480800001000072000000000000000000800000000000000000000000000100001040000000000000000000000000000000000000001000000000000000000000000000000000000000000000080000082000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000087050000000000000000000000000000000000000000000000000079a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000004000000000000000000000000001000002080000000000082000001000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000804000000400000000000000000000000082000000000000000000880000022800000400000800000000000000f9a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (008400000820000004000020000000400000400000020000000000000200000020000000000000000000800000800000020000000000008000000000000000012000000000000480000002002012000000080004480000000004000000000042004484000102000112000000088000480208004004112000000000000000000000000400000000000004000000000001040000040000000000000000000000000000000001000000000000080000000000080000000000000000000080000082000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060cf0000000000000005a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000002242000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000010000000200000000000000000010000008000000100000208000000000008200000100000208000000000008000000000000000000000000000020000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000080000000000080000000040000000000000000001000000000000000000000000085a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000208000200000000000000200000108000000000000000008000000000000000000000080000200000208000008000008000000000000000000000000000000000200000200000000020000200010002800404100210020004100008400c00084000020000000000002000c00404100100020010080004300800800000000020040200000000000000800000000000000000084000000000000100000004000000000000000000000000000001008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000081160000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000002000000000000000000000000000000000000000000000002000000000000000000000000000000000000002000000000000000000000000000000000000000001200000000000000000000000000040000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000c5a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0000000000000000000040000000000000000000000000000000000000000000000000000080000000000000000000030000000000000401080040000000090440000080800401000000000000000001004800800140000110020040000000400202000000000000000000000000001000000000000000000000000000000000000000000000004800000000000100000000000408000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000025a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008cc20000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000001000000000000000000000000000000000000000000000000000001000001000000000000000000040000000000000000000000000000000000000000000000000000000a5a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000400004000000000000000400088000100018024400008000500a1800020141000880000000000000000000001000000000000040000000002401000009000000050000000000000000000800000000000000000004000000080000100000004000008400000000000200000000000000000000000000000000000400000000000000000000000000000000000000000000000000000065a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000086320000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000002000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000001200000000000002000000000000040000000000000000000000000020000000000002000002000000000000000000080000000000000000000e5a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000800000000000000018000000400000000200008010200010000600000080000000000410000000000000000010000010018010000000000000000018000000000000000000000000000000000000000820a200000004208208001820009e60000c0000021800011006000a0020018600042e209000000000200000104100000080000000000600080000000000180040800000800100000000000000000000001004002000000000000800100020000000000000000000000000000000000000000000000000000015a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000813c000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000006000000880000000000000000000000800000000000000000000010000000000010010000000000000000000000000000000000000000100000000000000000000000000000000000000000100000200000000000000000000000008000000000000000000000000000000000000000000000000000000000000000095a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000800000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000400400000008000000000000000400000010000008000000000c00410000000000000000000010040000000000401040000020000000005000000000020800000000010820000000200024200010000820a000000000000a8000000000008008000000000000000000000000100000000000000000000000004000000004000000804000020000000000000000055a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000040000000440000000000000000040000010000001000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e2270000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000200000008008001000000000000000000008000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d5a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000010000000000000020000000000000000000000000000080000000000000000000000000000010000000000000000000000000000020000000000000000000000000010000800000400000020010000000000000000000000800808020400800002400080402400400010010000000800000400400800020000400000000000400000010000020400010000400410000400000000000000020000400000000000000010000090010901000001400000002000000210200000000008409300010010200200082040400020410040010008008002040040000410000000000000002000000000000410000401000035a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001008000002000000000005040000001000000000000000040080000000000000202000101008000080000000000000000000000080000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000019080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000b5a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000808010000000000000800000000000010000000000000000000000000000000008000000400000008000000000000000000000000000001020000000000000000000000000000000001000000000000000008010008000000000000000000000010000000000000080000008000010000080000000000000a0001800004840080800041000248001000200000040008000008000060000200000000200000000000000000000002001000000002000000101002000004101000000008000040000000000511082234014080442088200d02100084200000000042100010000001001004000080040002020811001001001000a040140001001000075a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2000000000008000100020000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000098480000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000200080004004080000000000000000000008000000000008000000000000280000100000008000008000000000000000000000000100000000000000000000000000000000000000000f5a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000100000000000080000000000000000000000000008000000000800020000024008000000801200204000000020000040000000020080000420050020534021000900a20800024000008000008800200a20000a00000000000000000000020000804000000000020101000000204100000200008000000000000800000800808000000020000000000200000000000000000000000000000800008000000020000da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (30c000540101400000001040540002883040400000002001002002000800000000000000000000800000000000000000800000000000000000000000000000000000000000020000020000800030000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a8a00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000008da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (080000080000000000000000000000002000000000000000000000000000000000000000000000000000800020010000010000800000000000020400000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000400030020000000030c00000000080000020000000000a000004800000000020020000000000c0000000020010040000805000020000800000030002000800c00000000000880000002000030000000000000000000000020020c8040002000500000002000400001030c208c0014040c308200009d50101c04005800404051400020cc004141004da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000080000008000000000000008000280080100080006006022002400000e80000000000000008000a0028020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002786000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000400000000000000000000000400000000800000000000020000020000c000cda040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000000c808d000402000040002da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000800800000000004022800804900020000010000000000400008020000000000010000000000000800c0044001001002002000000000040200001001400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000329e0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ada040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000004000000100100000000022000000000000000000010000000080800000000000000000000008000002140400a000401001000080080000040008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000db820000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000eda040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000100200044024000220002100c41102204002021101000400211020400800022000144040002002002004800030000846044002402280910c4002003100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000842800000000000000000000000000000000000000000000000000000000009da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200200008408400828800000000218200000608210000020020108040000000200818009000210210000420004020808008010210610000104000000880000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c0000000000000000000000dda040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000009fef0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000200000104000000000008004000002000000002004008000000000000080200200000000000001000041000000000000004000088000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bda040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000053c40000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007da040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200201100000004204008140008214000000001020000000000108004000000000000000010000000010008000002000200080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fda040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000001dd600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002002000084084040001001411202182008006482101000000008000000000002000180080002102101203040010020080080102106100510000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000072b300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000043a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c3a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006000000000000f0a000000000000007000000000000f0a000000000000008000000000000f0a000000000000009000000000000f0a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a3a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000289a00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000040000871a00000000000000700000040000871a00000000000000800000040000871a00000000000000900000040000871a0000000000000000000000000000000000000000000000000000000000000000000000000000e3a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000008008008000000200040000000000000000001000000000000000008000040000c01400000040000000000000000000000000000000000001000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000e7a600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000013a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000400000000000208000000000108000000000004204000000000008000000000000000000000000000000000000080000000000000008000100003204000000000000100000002000400040011040002058001000080008200000000040051000000000200040001040020044240000200004000000100020244001000009089108100000000246002002000201100009000040000000400000000000000000000044000000000004004000004000044000000000101100000004100044000000000001100000080000044000000000000080000000000000000000000000000000000000000000000000001400000000c00000501040000000000000093a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000500000000000000000000030000000000420c040000000100001000008000300000000100000c000030800040420000000000080000040000000000000000000000010400000000400400000060000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000be4500000000000000000000000000000000008000000000000200000000000000000000000000000000000000008000000000000200000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000008000000000000200000000000008001000000000000000000053a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000000840000400000000000000000000000001800020000000300100000000000004000000000000100000000000004000000000000000000000000000000000000000000000000000004000000000020000000000002004800000000020000000800000004000000000080110000000040004800000000000000000000004004800000000c001200000000040248000000800000008004000000048000000000a000000080000000480002000004012000000000000000000000000000000000000000480000000000000000000000000480000000000012000000000000480000000000012000000000000480000000000000000000000000480000000000d3a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000004000000000000000000000000000000002010210000000000028000080000000000000000000000050800000420040000c00080000000000000000000000000000010400000000401400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e1cb00000000000000000000000000000000040000000000001000000000000000000000000000000000000000040000000000001000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000440000000000400033a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000100000000000100000000030000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000800000000000000000800010800000000010000010084000000002400020000000002000800010400000001800001000000000000000000000010020110100000040000004000000000020000000020000800000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b3a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (008020000400000800000010000000000000400020000000000004000020010600120000000000004000080400002000002000000000000000000008000202000000280000002002200100000000020000000020000008a00000000000000080000000000000000000800000000010400201410000000000000000000000202000000000000000000000000000000000000000000000000000000100000000000000000000000000abab00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000073a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000800000000000000000000200000000000000000000000000000000800000000100020000000000000a000000000000000000000000000000000000002002100000080000080000000000002000000000100080000000000000000800000000000000000002800000840000002080000000020000080040022000040000020000000400800000020080000001802006040000000000040122000002080040000040022040000000000041000001300000060000000000300801044000000049008000000880840000200004060000000000001000000000000000000040001000000000000000041002000004000008000000001044000000000001000000f3a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000010000c008240104000600000060100000000400004001810000040040000000008000000000000000000000000000000000000000000200000000018000082080000000000000000000000000000000000000000000008008000000000000000000000200002008000000000002000800000000000000000008000000000104000004100000000000000000000000008000000000000010000000000000000000000000000000000000001000000000000000000000000003e7a0000000000000000000000000000000000800100000000020000000000000000000000000000000000000000800000000000020000000000000000000000000000000000000ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300000000000000000000000000000000002000000000000000000000000000000c000000040004000001000020000000000000800860000001000000000000000000000000000000000000000000000000000000000000020000020800000000040020000000000000000000000800000800000000000200000000000000860400000100000000000400080500000000000000000003000000400000000031012000440000f00400020100022012400030000000000100000000000030000000000400001000014800800180800000410000000008ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000400020900000200a00202000000028010000000400b4200000000802d008000000000b4000000000040500004000008014000a00000000000040000200201001a00084000000044000002000410000010000000000000000000000806010000000428100000002002200000100400000040000002002000000040028000000000000000000000000000000000000002010000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000006cef0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000140040000000005000200000000000000000000000000000000000140800000000000000000010000000000000000000000000000000140805000010005009240000000140004000000000000000000000000000000000000054811400000001400200000000050001000000000000000002000000004000000000000000000020000004800000021400000000060000800800100000000000000000004004000a4000b40a41002002005880000000000000012000013080080000020002010200000000005000040000000430000000000000000200021900a020020008020a8000100400002010810800000000008000020000000cba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010304000000000008000000000008000000000000000000000000000000048000000000000000000010000100408000400000c000000100000100000000000040000040000000000001000000000008000000004000101008000040000400200000000000000000000000040000000048000000000100404008200000100000000000000000080800004000000000000040000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b3e0000000000000000000000000000000000000100000000050000000000000000002ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000080000000000002000000000000000000000000000000000000400000000040000000000000000000000000000000000000000000000002000008000000000000000000000000000100000000000000000000000000000000208000000100030000000000000000000000000000040000000000020000000004000080100000000000040000001010000000000000000000000000000000000000000000000000000000000000000000000000000000010000200000000000000000000000000000000100000080000100014200400000000000000000000828000080000000800100100001200001020b01800002000800004100000120024000000000aba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2002000000031800140000000000100000000000004404040800000000101004000000000080004000000000000001e442200c000000000000000000180044806100c1010000010080040200080200000000000000400008000000011000040000000200000000080001000000080000080000260004000000000000000000001000400000020000000000124800000000000000000000000020030200040809b810000000000000080000000000000020000000c00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049f0000000000000000000000000000006ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000e94800000000000000000000000000000000008000000000000200000200000000000000000200000000000000000000000000000000040000000000000000000000000000000000200000000000000000080000000000000000000000000000000000008061a00000000001248000000008004300000000000000000001000000a00000000000000080000001080607000000000000080002000080006000000000000000000000000000000080000000000000001000000000000000000000000080080000000000000000000102000000400000000100000000419001404598440002000000080081000000d38000000000000000000600100818180000eba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (6010004000000000004040c001050000000480000002400280102450000000001000000100000002088014100000000000000000000000000040000000000100400100800002000000000000000000402480000001000000000000080800080210000000000000000020200000000000008000000800080000080008000308000000200004008000000000000000000000000400000000200400000000000000208000004400001000000000001041010802040800000000000000010000000000004000000120400082000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000d9540000000000000000000000000000000000800000000000020000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000010800000000000000000000000000804481000000000000000000000000040000000000000000000000108010000400000000000000000009000000020000000000000000000010000000000000000000000100000000000400000000000000009000020000200000000008000000000008200104000008000004244c0000400000000000000000000009ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000840480201408000a00000000020240402020800010000220000008c20208880a000412800000000800081c0021006012101000000000004002001010000000000004840000000021400000000000820000000448c200000000010000000000002cc00000004000520001000000014c00040000800020000000020000800010000400000000000020020400000140020100000800000000000000000000000000000000004200008400000000004000200000000000000000000000010001050004400000000001008000080000000000000000000000000000c1000000000000000000000000120000004000000000000000000000000000000000000000005ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000003b000000000000000000000000000000000000400001000000030000000000000000000000000000000000000040800000000000020000000000000000000000000000000001000000820100000000000102000004000000000000840000000000000000c20040000000020801000000040c0200000000000000000020010000002800000000020100800000020c0000080000002000080000000040000000000000000000000000000000000000000000000000000080000000000000000000000000040000000000000000000080000480000002000042404000dba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000900000004821050000000000800028021000010400040000001c0910001140000000003000000080221804049000000080000080000012400000002000400000000000000000102400180010002000020010000000000000002000003000200086051080000080000000000000480000000000000000000000000000000000000040000000080001000000000000003000000000001001000082010780000000100020100000000000000000000000000100010c04011400000030104000000000000000000000000000000041020006140000800800000000000800000000000000000000000010400000800000000000000000210000008000003ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000067bd00000000000000000000000000000000000040004000000001200400000000000000000000000000000000000008200000000000008000000000000000000000000000004000400240000000000000000000000000000000000000000000000000400248000000000004200000000000088210000000000000002000000000000000003000002000000000000012004003000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000100000000000000bba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000100000000000000000000000030000000000400400204021000100101000001000000000000040078100000008000400000000c001103020010080018080000000081209821000080008000000000002183014400020004400000800000600012000001000000000000101300040400080008000000000a4130100008000000c000000000000301008000000004000000000000100000000000000000000000000001000000002020000000000000000000000000000000000000a00000000000800000000044000000000000000000000000040000000420010000000000880000000040400000000000000000000000282007ba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800040000000000040000000040061800001040000000000000000000000000000018000000700000000020000000000020000000000000000000000000000000000000000000006eff00000000000000000000000000000000000100000000000404200000000000000000000400000000000000010000200000000400008000000000000000000000000000000000010000000000000001000000040000000000008000000000000000010108000000000400000000000010100800000000000000000000000000000000000004000000000000101000000000004000000004002001000000000000000000000000000100000000000000000000000100fba040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008020000020000000000000000000008800000000000000000000000018008c1800004000400000400010000000000000003801001100160806810000000000000001000001800000104800080000000008210024a01090000008c00000a0200000080000010000020000000c00000080018700032000000080000000018000000000000400000000000400000000400000000000000600a860000000008400000000008000a00000000000000400004104000402082006000004000184000000800000000180000000400000000000003000004000002008080080001000000001000000180000000002004040014000000000080400002000040000102000007a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00001040880040008000080200400000200000040081000000000000000000000000000100008004000000000000100000000000000000808800020000200000008008000000a000000000000000000000000000000000000000000019ad0000000000000000000000000000000000800000000000020000000000000000000800000000000800000000000000000000000000000000040000000000040000000000000000000000000100000000000001000000000000002000000000000000800000000000000000002800000840000100000001800000018008000600000000000000000000000008000000000400000000010000000008000000400000010087a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000008800a00000000000000000010080000400000000002001000000000000000000000000000000010000000004040000000000004000000000008000008000002900200000000200000000000000000400818100800000000000000400020010000000000800000810000080100000000042000002000000200080000000044000009204000040000010000000000002000408000000000010000000080000000000004000000000000000000000000000000000000000000000000000000000000100000000000000000000000002020000000000008000042101000000000000110000000001004000000010000000000000000000000047a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000430000000c00020000202100004020004000030c0400442000008002000000000400000010000000000000000000801000080040000000000001000000000000000000200000800008000000200200000008000000000000000000000000000000000000000000065a4000000000000000000000000000000000000000000000000000000000000000000080002000000080000000000000000000000000000000000000000000000000000000800000000000000000000000000000001020000000010000000000000000000040000000000001000840000000000000000000000000000000010000000000210000000000000010000000c0000c7a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000010010000400004100200000000010000008000004000200000008000020002120000004000000080010000800000400000000000000000200002200000000100008040000020800000000000020088010090000000401002000200020008041001205120000000800000000020041001404a0800000000000002000224100100000218000608000004000204001008004000000004204010008100000000000008000100100000000000000000200008080408002082000000000000000000000000000000000000000000000000004104000100000000000008000000041002040000048000010008040000000000000000000000030027a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0500000014001080000000080000100080080008000002000084280100100221202400c2020406008a000001010100040000100102000000080084000401000004000000000010001001000000000208080000000000100000100000200000000000002000000000002000000000000000000000000000000000000000000000c99d00000000000000000000000000000000000000000000000000000000200000010000000100000400000020800000000000820000002000000200080000000200000000000020000000000040000080000002008000180000002080000000800020400800100000430000088820024000400200000000000000000000000000a7a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (100100000004000040000000082008000000200000000210000408800000800000000040000000000200000001000000000000000000001000000140000000020000000000001000000000000000000000000040000000000020000404000000810008400000000000004800000001120010000080040006800020000028442000020420010000002010000040010010000004a000000000641200000804a420109000a000420000000400080000400008080208012010000110000010000080880110000012820a00400420400028010002200400220428010010000010004810000000400022810000420010000000000000402902000000041000000100040067a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000002000400900001000000000000000002000204000000000000000000000000000034000002100000ca0000000d0020020000000010000000400003500000044000002000000000000004000000100000000000000000000100100000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000057ce000000000000000000000000000000000000000000000000000000004000000120000000000004000000000000000000000000000000000000000000000000000400000400010010000000200000a2000000800001420000000000000000800000000800400000004100010800e7a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000002041c00000000043800002000002001c1000008000000000000024001000100000800000030008401001401e400000000000300002000000000200000000000000008000000000000000010200000000000000008000400000000000000004000010000000000000010020004006904000004000000320000800008211400800200000008000120800d00800020008100000000000024a3c8004120002030460480080081b010080000114000020820402821c02020802008030000820002000220080800120402000800000a2e900000000020800000822081821c200a0800410000020010410a2dc00014000810030000400882000020010000017a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (011004041084000000101001000000000000000000000000c00c00000000a0002801000002002c80040002810c3008080001000000010008310c020030042800200000020003080000002900020b0030000100800000100000000008000200000000000000000000010010c2000041000000010400000000c00010030010004014c001000000000000000000000040000000000000000000000000000000000000000000a21d0000000000000000000000000008000001000000200200078008200000000000200000000000000000002080c00000000082020000080000000002000000000000000000002400c00000000080000000000000000000000100000097a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000820000000002000000010000000000000005003000100000000001002000300000004000000040000000041000000040030000800000000400280000040080000800000000000000000000022000d000000000008000000402000008000000000000000000008000000000000000000010000200000000100000080008000010c40000010040000004000002b08000800001200000080000014010048420000102800200000030810200c00001103430000028a100080020000000048000000d0210001000000200001020004028a8000e0410a0008000008000108008520c0810000000400100400000401000000021200023110408001005140057a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00050004000044048000040000000040010000008000000000080080300000003000208000000020028000000000805040000000008000000000000000000000000000000000010010000200a100868000508000000000000000000c04000100030881000000308100040000004004000000050000000000000080004800000100000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083e900000000000000000000000000020000000000000800800020020800000000000000000000000000000000000000000000000200000000000000000000000000080000000012002000d7a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000200000000000000000000000000000000000000000000000000000200700088000008000000000100402000048010000000000000000000000000000080080000000c00000000408288880000000000000000000408040400000000000000010000000080000000000000000000400040000080000000000000000000000000000000000000000004000002000000080400000001150002010005000000000000000210000000250a00000400000002060c0800014001000400000000041000202d092210000000140a00003000000040140000000010007000000000000000000000000000a00240000c000900000000000037a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000404010000000000000000100000400400000a0000000440000000004010000000000020000000001000008000000000000000000002002042800200020000000100000000000000000000000000010004000140040000000010005000000000000000000210000000800041000050200000000000800a0008000001000000000000000020000002800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f77400000000000000000000000000000000200000000044000000500200000000000000000000000000000000000000000000000001000000b7a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000a00000000000008000000000000000000000000000000001020000800140000000000000000000000000000000000000000020000000100100000400020000020000000a00000000000000000000000000000000c0000000028004020000000000200000000000202000000200000a00000000000000000000000100800000000000000001408800c00080000000000000000000000000000000000000000200108004408100000800030000000404028140200000000000000020000000000000000020000002005004020a008080000000002000284000000820100050000000000040000008000000800000100000000000000000000077a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000200000200020000000000000000000000000000000004008000000150002000000a000000000004005a00040000002004000a8000000040000800110000000008000020000000000800000000000001008400000000140000000000000280000000000000000000040220000000200000001100000000000000000000000000000001002000001000000020000002000000800000100101060000000000001000000000000040000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000012e900000000000000000000000000000000100000000000014000000200000000000000000000f7a040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (140a000000000280020000000000000000000000000000050280000000001400000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000004000080000080040000000400000000000000000000000000000000000040000000000041012004000040000040000800009010000000000000000000100500004030000000000000000402000800400000000000000000000000000000000000000000000000000000008004002000000000040130000040000000000000000000920010810010000000000000001088000020000000000000014040040002a010000000000000000029000fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20010050020a000400002000100200008010000200280080200000000000000000000000000000000000482888010012000002000000400050308008090010004000010401010090000408440000200110400000010004410000000000500400010000014082020002000200480001002000100020000000000000000040010008405000002000802020000000000000000000000000002204800100848000010001000000001000020080100824000080020004800000020000020000804000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000061a8000000000000000000000000000028000000008fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000200000000408001005000220100000000000000000000000000000020200008001001004000000040000000000000000000000000000000100002000800000000000000000000000000000000000000000100100002004800002000100020110141000003000000000000000000000000040000000040005004401000a0102112000000002108040100041110800000000000000000040120002005000000000000000410100202020000000000000000000000000000000000000000002010a000022008000000000800204040048004440000000000000040008880024030010000000800008c021300900280002000080004fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000010840020000008000000000000002050400208000000200000000000902000084008000040000000200000000000000000000000000040011000001000000400000040001808000015009800000001800001001000078060000040040800200000001422000000000090000001800000402402000000000054000000000010002000000000000000010010080040560100000080600000000000000000040000008002a0048200004041000000000000000000000200001800020000000400060000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e72700cfa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000585c00000000000000000000000000002000400004080004048002201000000000000000000000000000000202000000000000040001000000000000000000000000000000000502000040000000000000000000000000000000000000000000002401100020008010000000000000000110090048000000000000000000000000000000080420050440020009000420000000400010002010000000000400000000000000006002000080000000000000000101000400000000000000000000000000000000000000000000000000010000000000080820020004058402000040000000000000000000102000000400002fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000002000000000000000000000900000000000000000420000804000000000000000000000000000000004000000000000000000000000000000000000010000080100000000000000000204100100100000000000200000100000008108000000000000400000000000080000000000008000200000000000000020000002000008000000000000000000000000001100800080000004100000000000000000000000010001000000006040000800002000000000000000000000000000000000000000000080000000000000000010000000000000000000000000000000000000000000000000000000000000000afa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000001eeb00000000000000000000000000000000000000000020020000000800000000000000000000000000000000000000010000020000000400000000000000000000000000000000800000000000000000000000000000000000000000000000000900800000040004000000000000000a00000040000000000000000000000000200000000600000200008022000800000000000820000000000000000000000000000000008018000400000000000000000000000080000000000000000000000000000000000000000000000000000000000000100000000000000000006fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000200008000000002000000000000000000000000000000000000080000000000000000080100000002002000000800010001000002000000000000000000000000000000000004000000000000000000000000000000000000000000000800200000100000000000000002404100100100000000000000000100000000100000004000400040000000010050000000000401400000000000800000000000008000000020000000400000000000000000000000000000800020000000000000000000000000000000000400000000000200800000010000000000000000000000000000000010000000000400800000000000000000000000000000000000efa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d2c100000000000000000000000000000000000000000090080000002000000000000000000000000000000000000000004000080000000100000000000000000000000000000000000020000000000000000000000000000000000000000000000002000004000000000000000400000000000040000000000000000000000000800000140000100100000002000044100000000210001020004004000000000000000000020000000200000000000000000000000000000000000000000000000000000000000000000000001fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000020010000000000000402000011000420000000000000001000000010000000000000000008c00d010300408002000000000d001021080122100000001002000000040000000000c0000008000000000000000000000000000000004100000200090002000000000d00208a0840040000340000000340008000000808000000011048000000000400400000000010030000000000c10540000200008004000080a00100001000000000000000004004080400000102200010004000000000000000000c000300000880000000080000020000004004001000000080000020000000000c0000010001009fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0c20000000000000000000000000000000040000000004000000000020000000000000000000000000000000000004001001000000000040000000000000000000000000000000000000001000000000000000000000000000000000000000000020000003004400802000100040130080000c0000000000000000000000000002000800000104400430000100101003000000004004000000030101000000000000000000100080002004c00000000000000000080004000c0005fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2000000400000000000000000002000000400000000000000000000000000000000000000000000002000000400000080000010102280000000000000000000000002282400008000000080000000082282000008400000010000000183280400000000040010000000002082000008400000080000210000000400000000000000000000080002000008400000000000000000282000000400000080000010000282000000430600080000010c18002000000030600000000000c18280000000030040000000000001000000000000000000000000000002820000004000000800000100000000000000000000800000100002800000000000000000000000000dfa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (07562002b0190040000332a00000000008c8c000000000033000000010000c000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a4a1000000000000000000000000000000028000000000000a08000001000000000000000000000000000000000200000040000008000001000000000000000000000000000000000200000040000000000000000000000000000000000000000000028200000040000008000001000028200000040000000000000000000002000000430600080000010c18282000000430600080000010c1828000000000000000000000000028003fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (28855550414a000000000000000000000010882828000000000000000000000001040000000000000000000000000000000000000000000870000000623bc000000003ff98000002ab60000000000000000001d006e15c7700000000000174000000029414ebb950300000000004f4f050400000017340000000000000250012aaa4000000003395b0000000000000000000000000000202000012a5581008000000000040210c020008010c000000002004040100420109555400000002055550000000001555400000000055550100400000a8880000000000000000000000000000000000000000005281c31eb7888800000c77300000000000000000000000bfa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (83cca800004555700000000000000000000000a15702b0098040000012a00000000000c8c000000000033000000000000c000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dbbf000000000000000000000000000000001000000000000040000042000000000000000000000000000000000000802200000000020088000000000000000000000000000000000000028000000000000000000000000000000000000000000000028800020800000000000820000000bbe0200400000000000000000000000062085555400000828c55550aaa0204415554000021007fa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (9a80000742ac6a6a0d2a020441a9a80000212886a6a0504a000000000000000000000052812400000000000000000000000000000000000000000000000000000000000000000000000b70000000e63bc000000003d7980000032b00000000000000000001d001615c77000000000000b8000000034192fb3c103000000000044ee014c400003d7f4000000000000021001486e40000000071880000000000000000000000000000020200401489181008000000000040210c020008010c000000002004040100420109a9a80000000206a6a0000000001a9a80000000006a6a010040000028000000000000000000040000000000000000000000005294115e00ffa040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000202a22b3c8000000000ac280000000000000000000000514a0000331880000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e4500000000000000000000000000000000000400000000000010800000000000000000000000000000000000000088a2000000000222880000000000000000000000000000000000005500000000000000000000000000000000000000000000000100105501400000000154050000103fe5500000000000000000000000000062085a00006040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a200000000000000000000000000000208801a80000088526a6a5a80802001a9a80000110946a6a20142000000000000000000000020148250000000000000000000000000400400000000000000000000010000000000000000000000000000231a8000000001a814ffbc7ca9a00000000000000000000007f1824200000000000114000c357c8004e1c0000000000020044ee5500210000000000000400000007f0012b0a8000000001b40c000000000000000000000000000e30000001abb700000000020200040200450a1828000000000840a0000104908282001a800000840a6a6a0000021001a9a80000000006a6a1049000001a9a8000004000000a000806040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000555510094000015554000000200002a2200000000000000000000000000001100613a4000000001857b00000000000000000000000a856400331894000000000000004200000000000000000000000000000100800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006c53000000000000000000000000000000010410000000000410400008000000000000000000000000000000000001040600000000041018000000000000000000000000000000000000200000000000000000000000000000000000000000000000022900202a000000000080a80000003800406040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000010144153c000000001054f0000003de410a40000000000000000000000000208b015400005005955555d23c02025555400001109d555511052000000000000000000000001040210400000000000000100000000480240000000000000000000010000000000000000000000000000775ac000000001bc9100007d29000000000000000000000007f1924200400000000198010c357d2904f14c00000000002004f4f5109a008000000000000200000033011290cc00000000594a100000000000800000000000000023000000139b14000000000420004020005431c2c000000000c70b00001009412c27015400000850b5555000002102555540000000c06040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000400000000000000000080000008000000000800000000000000000000000000000000000000000000000000000008000000000000000010000000000000000040000000000000000000000000000000000000000000058000000000000000000000000000000000000000000000000000050000010000001600000000000008000000000001400000000000000000000000000000000000000000c2040000000000000000000000000000000000940000000000025009090000000000000000000000000000000000000442400000000011090000000000000000000000000000000000004106400000000000000000000000000000000000000000206040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0802400000000002080000000020014400000000001000000000000000000000000000000000000000080000000000000020800000000000020000000000000000000000000004002000004000000000000000028028000000000a0000000010080000000000008001000000000000000000000200000000000000002808000000000080000000000093000000000000501000010c000110000000008100000000000000000000010000400004104400004800000008000004610000000110110000100004000004404000000110010010000000004010000000910000004000000000000000000000000400000000000000000000110000000000000000000000a06040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000012000000000000480000000000000000000000000000000000010012000000000000420004100000000000000000000000000000001000000c0000000000400000000000000000080c0000004000000300000000000300000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000001000000000000040000000000000000000000000000000000000000000000000000000ab920000000004000000008000000000000000000000000000000000000000000000000000000140000000000000000004000000140008000000000800000000000160000000000000800000000000606040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000100000002002004000080000000100002000002004000000000000000000000000000000000000000000000000000000000000000000800000000000000040400000000011000000000000000080000000000000042000040000010000000801000020000000c4000003000100000180000000100000000000000000000040004000000000000000100100000002004040000000000100003000000000000000000000120000000000004800000000000000000000000000000000000000120000000000004800000000000120000002000000000000000000120180000000004800002000000120000080000004800000000000000000000000000e06040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00202000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000200020800000000000000000000000000000004000000000000000000000000000000000000000000008000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000bcf80000000004000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000004000106040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000800000040000000000000000000000000000000000400400000010000000000200400000402000000000000000200000000000000000000000000000000000000000000000000000000000000000040010000000000400000000000000008000000000008000200000000000400000100000044000000120000004800000800000000000000000000000000000000010000000000000000000000000000008000040000000000800009000000000000000108000000000000000100000000000000000000000000000008084000008800000000000000000000000200000000208004000008008000000000000000000000004008000000800000906040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000018410010000810410000000000010000610000100400200000424400400000000000200000000000810000000401000410020004000000400000000000100000000020810408040000000800000000000000000000000000002000200000000008088000000008000000000084000000202000000000000000000000000000000000100000080000004000100000008002000000080080002000000000000000000000000000000000000000000000000200000000000008000000000000000000000000000000000000000000000000000000e87f0000000000000000000000000000000000020000000000000000000000000000000000000000000000506040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800000000000000000000800000000000000000000000000000000000220000000080000000000002000000000000080000000000802000000000000080000000008000020000020001000000000000000000800000010000800420000000000000000000000a001200080044202001000000002101100000000004002002000000000040000450201001000000208080000000000000000000000000010000000000088004000000100100000000004200000000100008a00200000a40200022000000000480000004084184010000000206000000000088004000100000802000204080040101000020021004c0012008402018900800100100010408400d06040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8040000200102001200100000000004000040000181300000000004000002000000001180104000002000008000100000003080000006008000000000001000000000002004000000000600000080000000000000000000000000001000000000000000000000000000000000000080000000000000000000000000000000000003000000000000009000000000000000000000000000040000000000000000040000000800000000002000000080000000000000000000000000000000000800060000000020000000000000000000000000020000000000000000000000000000000000000000032e30000100000000000008000000000000000000000008000306040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000020000000000000000000000000200000000000000000000000000200000000000000000000000000200000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000c0400000010002000000000000400400000000010202000000000000200008120040040800008401200000000200000008000000000200000000000080000000000400000000000000040000000000000800400000c2010002000000000800000005001012000400804000080000000000001000000000800080000000000000000030002000b06040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000010000202000400400034200000040140802000c00400090a000300100000004008200290002000018800022000000000000010100000120488000000024800800000000000000000000000ad00000008008214000600040000008000000000001000000000208508000000000000080000000000000000000000000000002000000000081480000000000000000000000000102010000000000000000000000000000000000000000400000080000021000000010000000000400000000000000000000000000000000000800a001000008000280000000000000000000000000000000000000000000000000000000000000000000034c10000000000706040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000974500001000000000000000000000000000000000100040000002000000000000000000040402800000000000000000000002002800101000000014010000080002d00904000000014002000000000500420000000014004100000100001000001000000000000000000000040000001000040041000000000000000000000150210000400405004b100000000100100000000000020000100000000024000800850100000000801426010000020000000800010000000800000000000800800000000020000000000850000000060001420000000000050001100000000004000000014000840000882020801000000004800000f06040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4000020811042000000104404000008000000000008800000100000800000000000b080020004001002000000000000000400000000200001000010040000000000000008801800000020000020a4404400000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000100000000000800000000000000080000000000000010000000000000000802401008000000102000000000000000000000000000000040000008000000000000000000000000800000000001000000000200000000000000000000000000000000000010000020000201000000000000200000000000000000000000000000086040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000080180000806010020000000000000000000000000000000000000000ab000000000000000000000000000000000000000000005000000000000000000000000408000000000000000000000000080000000000000000000000500008200000200010100000024b000110000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000008000000000000000000210000000000000000000000000000000000000000000000000000000800000000000020000000000000000000000000000000000000040000000000000000000000000108000100000000050000001000000000000000040000200886040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000100000010406000008420080040040000400000105200000000004049aa800000000000000002000000000000000000030400251024004000001000210004040004000000000040000000044000400000404210000c1080000102000502004580000000000020000000000000200000000000000000040000084402000000000000000000000000000000000000010000000004000410000000000000400000000000000000000400000000000000000001a10000200000000000200000008040001000000040000008000000000000000000000000000000000200000040000000000000000000000000000000000000000000020000000020020060800000486040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000001000000000020000000000000800000000000100000000000000000000000000000000000000000052be0000000000000000000000000000000000002000001000000800060000000000080000820000204000008000008000000000000000020000000808c0000082100110000000000080c12000000000022400000000000000000000020000000000200000080000000000000000000000000000000000000000000000000000004000000020000024800000000000000000000000000000000000000000000000000040c00000000004020000000000000000000000000000000000000000000001000000010000000000100000000000c86040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (100000010000000000200000000000000c10000100400008208000000180000040000000100000004000401040001000040002000000000000880000050000000000001020090a0804000000002800000020010000000000000010000000020000400000000000000000000000800001000a1002300000000000000000000000200000000000000000040000082000000000000000000000000000000000000000000000000444000000000010000000000000080000000000000000000000000000000802000000000000083000000400000040001000000040000040000000000000000000000000000000800000800020000000000000000000000000000000286040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000004000000000800000000000000000000000000000040400400020001110000000000004000000020002000800000000000000000000000000000000000000abc2000000000000000000000000000000000000400004108000020040000000000008000000000000000000000000000000000000000000000000080002000000080044000000000080000000108000000000000000000000000000000040500000800000000000000000000000000000000000000000000000000000000000000000000000000800020000000000100000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000a86040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000100002000000000000000000000000000000000004000000002080900000200080004010000042000000000000804000021000000404080000000010208000004000000000000200000000000280000409080042020c8000005000010020800400810000000002000001040200400a20000800a11050c2824400080000040020002000000000080000000000000000000000120000000000000c0000000000000000000000080000000000000002000000000000080000000200000000000000000000000000020820000040001081000002901004100000000000080000042000000000000000000002000002000000000000000001000004003000686040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000052400001010100000000000000000000000000000000000000000010400005000000010000050000000000000010001000000000001000000000000000000000000000000000009f990000000000000000000000000001000000042240001000000202000000000000000820080900080000002000002000004080100044000080000c00000000000120001001040000c0000100000002008000000001080000000000800000000000000000000000000000000000000000000000000000000000000020008000800000400000020120000000000000000000000000000000000000000000000000020000800000000800000000e86040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000100000000000000020000000000000000000000000000000000000000000000000000000040000000420000008000000000000000100000000004000000000000020020000100000c00a8800100000000000000000000000000000000001000000110090000402000400050484401000400000003000410002000000000000011000040000421842010080001080400540000000000000000000000000000002000000000000080000000000010000000000000040000000000000000000000040200040410000008000000000020000000000000010000000000000600000000020000000000000000000000010000000000000000000000186040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000001000000000000000000000000000000000000000000000000000004008028400000000000000000000000000000000000000000000100002000000000100080400000000000010000020000400000020000000000000000000000000000000000015d2000000000000000000000000000040000001000044000000148000000000000000040080040040000000000000000000000000000004000002000482040410000002000000000000492040000000000000000001000082000092410100000000000000000000000000000000000000000000000000000000000020000000000000400040001004040000000000000000000000000000000c00986040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000800000000000000000000000000000000000401000000000010000000000000000008000000000000000000000000000000000000000000000000400208000010010000002000000c00000000000100020000000001c000010000000103020400002000000000000000000000000080006808000400001b0000202000000e090000000a0000000000000008c80000001000018200002001001c00000008020011100008000000000000000000000000000000200c000000000040101000000020000000000000000000000000000004008000080000000218000000000000200000000000000000000000000000000000400008000000000000586040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000040000000000000000000000100000000100000000000000000000000000080000002000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000002800000000000100820000000000000000000000000000000000000000000000000003f9c0000000000000000000000000000000000008100800000000809000000000000000000a000808020000000000000000000000800080001000210100008001000c000000000000101000000000004000000000000100000030090008000200000000000100000000000000000000000000000000000000000000000000001000000000000040000d86040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080000000000000080420008000000c0000022000180023021008000000000000080020000400000006001800000000000000000000000000000000000600000000000000000000000000000000040000000000000000000400020000000000840021000000000402020000000000000000400014080000000000000000082000400000000000000000000000000800001000000004001000000001000000000000000000040000020001000190000000940001000040100088100000000840600000001400000000000000000000000000000018000020000080000410000040001000000000001000000000000000000000008000000180000000000200000386040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000002000000000000004000000040000000000000000008001000000080008400000000000000000000000800000000000000000000000001000000000000000000000000080000000000000000000000000000000000000000000000000800000000000802000000000020000000000000080010000800000000000000000000000000000000000006604000000000000000000000000000000000000000800008000020008000000001000000000000000000000000000000000000000000000000080000000000000000000004000000002000000000400180180000000004000002000100000000080020000000000000080000000080020002000000000b86040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800000000000000000000000000000000000000000000000000000400004000090000000400000000000000000000000000008000000000000002000000000000000002000000000000000000000000800000800000000000000000000000100000000000000000010001004c000040000000000500000000400000040000801000140000040000000000000000081082000000000020000000000000020000200040000000000000000020000000000000000000000802010000020000000804004000000000000000140000000000000000000000000000000000000000000400000000000000000008080000410000000000000000000000000000000000786040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000008002000002000000000000000000200000000000000004400000000000010000800010002008000880000024004040104000400200011440000040400000040000000100000000000000000000008000000000000000008000000000000000000000000000000000000000000000400000000000400004000000010002000000000000000000000000000000000000000000d593000000000000000000000000000000020000008000000000800000040000000000000000000000080000020000000000000000000000000880000040000002000000000000000004000000000000000001100001020000000000800000000000008000f86040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000402000020000000000800000000000200000510000000000000000000000000100000000000000000000001000000000000800040000000000000004202100000000000000000000000800000000000020000000800000000000000000000000002000002000000000000000000000000000000000000004000010001000c010000000000000300000000000008000000000000040010404020000000000000040000021050000820000014000000000000210400801000014000000000400000000010040000000001110000000000000001004100000000000120008120020000000000000000000000000000000200808200220200080400020020000000046040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (810000212880200000100802000280000000800420000000000000000002010000008000100a002002000040002000000080114000000000000100040000000000000800000010200400a0080000402482010c200000204000010200011010060000000400000000000400000000000000000100000040000000000000000000000000800811000000800000080010020000000000000000000000000000000000000000000000000000000000009ba2000000000000000000000000000000000000010000008000000008000000000000000000000000100000080000000000000000000000000000040000000004000000004200008048010000008000400000846040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000008200000001680080400000012000000000000900000000004200000009200000200080000001000000000000000040080000001000000000000000000200000000040060000000000200000400404000004000000104000020800000000180000000000004000000000040000000000100000000000000200008000000000100000000000000110000000000000100800000000040000008200000100804000082008204022021801800000000040000100009a85a0102490000614000000800020100402000014424014200012000100000881800404a2000000000860091000000020000080040000008001000008000000880800000241020021000446040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (200820280000000000800000000010000020810012000800002082111400000000000000800820000000000000002000000002000000100000008000004000000000208001000002000000000000100050000800000000001000050080440000001001000000000000000010000000400404000000040002080000202001000000000000001000004100000000000000000000000000001101002004005408041000400002000000000000041000000000000000000000000000000000000000c0e1000000000000000000000000000000000000000400000000010000000000002000000000000000000000110000000000000000000000000800140040000000c46040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010030000000020040000822000020033000820200049020000040008201000000000240000000004000000000000820000012004000000000000000100000000000000000000000000020000000800000000080030000400000020041000000000000000010000800000000000018000002400000090000010000004000000000020000000000000000000800000000000000100000010000000010002010810000000100320008000410000160000000000020410000280101d000000000240000000004434101004100009d043000841001048e00024082428490420002000010000042040080441000540000440040088000022033000020020000246040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80300010002021080200004480042048088010000010000000480830830002040023d60c00004c12c00020000004030c30c00000c00000c000000800020000000000000000008000000a000022000000002008002000080010010000000000002002400000000800000000000000000000000000000000000000000000020000020020c20000000010010200004408008000000000000010000002000000000000000000a00028000400008a0808009040020000002800841000000000020840000000000000000000000000000000000000af64000000000000000000000000000000000000000000000000000040000000000000000000030000000000000000a46040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80100000000000000000000000000000000000005000008000000000a0810004020a00000800000000000010404000000000000000000400010404000000000002000000000001000200000000000000000000001000300000000000000000000000000001028500000080805110000000012012000040000040002001010003a0000000c200000100000004090004000000000000000000000028000000001000000000140001002090000004a02000004000002008000100008482812200000000008010000000010000000000100000000000002000ac00c0021820000010000a0088000520a000320002008100051090140008002000000002000000010400646040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10004000110400000000000000000000020160400000000000c000900c2000000400011000000200000000000000000000000000000028002000028002000008000080140000000000000000000000000000000000000000002000000c0000000000000000000000000000000000000000080000020000004080000000000000000000000000000000000000000000000000000000000000000000000008040006000008000000000400000000000000000000000000000400000000000000000000002000000000000000802010000000000000000000000000000000000000000000003134000000000000000000000000000000008000000000000000200000e46040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000024004000000040100000040000000000000028005000080080000000000000028000000000000008000040240080000200000004000000000040040000000010000000020000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000001000000000040000000000000000000000000000000000000000000000000000030020100000000400000000000000000000000000000000000000000000000000000000000000c0100000010000000100100000000402000a00000000000000400000000000021000400200000000000000000000000000000040000000000200100011005000146040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000c00020000005a1004000000004080002000000000000000000000000000800500200000000002000000008820100400040014000000000000000000000000000000000200000000100000000008000000000000000000000000000000000040002000000500084000014000000000000000000000000000000000000000000000020000202000001000040800000000000000000000000000000000000000000000000000000000000100000000a000040001000000000000000000000000000000000000000000000000000000000080000000000002000200000000000000000000000000000000000000000000003f6000000000000000000946040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000276d00000000000000000000000000001100094000100020006d100100010000200000000000000000a00000000000000000002000040000000000000100248045800008001000005000000100000000008000001000000800080000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000080010000000000000000000000000000000000000000000008000000000000100000000000000000000000000000000000000000000c0000000000004004000080000080004000020000400008000000000000000000028000000000210000004000000000100040000000000000000000546040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002008008400000100000000000000000000000000000100000000000400010000200140000000000200000000000000000000800000000000018000000040000800000004000026000000140000000000000000000000000000001000000a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040004000800000280000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000200000000000000000000000000000000000000000000000000005000000000000000000000000000000000000000000000000000d46040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80400000000000000000000000000000000000000000000000007b9900000000000000000000000000000000800000000000080000000000000000200000000000000010000000000000000000200000000000001000040010000000000000000002800000000000060000000400000800020000000000000000000000000000000000000000000000000000000000000000000000000000008000800140000200000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000002000000000000000080001000040000080000200000004000000000005000000400000346040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2004440001000010080000800400010000000800102000a40008030000000000000000000000000000010040001000248151000040404000240004000200000000000001008240012000400400800000000000020012000400100c00084028000000000000000000000000001000020001040000801000020044000000000000000000000000000000040001000200001000000008000000000000000000000000000000000000000840014012821224910004000080200000000000000000000000000000000000000000000000000000000220080000088208002000100000000000000000000000000000000000080000000008004000000008000000000000b46040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0018000000000000000000000000000000018000002800000000000000000000000000000000000000000000c3f700000000000000000000000000000c00904186184030026192106100800082402281000100000040000000000000002000200000000001000000088020800240001040101401100050050008040000000400201000020010000000000000000000000000000000000000000000000000000000000000000000000004008000400080040200008001000000000000000000000000000000000000000000000000010000000000000200100000000000000000000000000000000000100040000000024022000080400808081000000000201100746040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000002000800000020000004000000000000000021008000000000000000000000000000010006800800000000000000000000000000000800000000021814108010100000000000000020000000000000180026000200000000000008000080406000000020090024000400000000000000000000000000000100010000104060000100004006000000000000000000000000000000004000080040000100000000000000000000000000000000000000000000008084000201c220080010002000180400000000000000000000000000000000000000000000000000000000000040000108400000000000000000000000000000000000000000600f46040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000004000000002000000000002000000000004000000000000000000000000000000000000000000000000000e89c0000000000000000000000000000000018408028400400a102186100000002404081000100008044000000000000001000000000040000000000000008004200000040001001100004040000040000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000002010000a000800800000100000000000000000000000000000000000000000000000000000180020000000000000000000000000000000000000000000000000008800000000c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000080000000000001000040800000002000000000800000000010000000040000000000000100010008000020004000840000000000000000000000000000000000000000001040000880820008000000000005000000000000020104000000000000000000000000000000010000000008000400400000000000000000000000000000000400000000010020000800800000000000000000000000000000000400000000000010000200000000000000000000000000000000000000001000000090004008018080000000000000000000000000000000000000000000000000000000000000000000000000000200000000008c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000022000000000000000000000000000000000000000000000000000000000000000000800400000000000000000000000400000000000000000000000000000000000000000000000577d00000000000000000000000000000400000000000010020000000000000100000000000000010000000000000000000000000000000000000000000080000000000000000c000000100400100000020001004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000100100000000000000000000000000000000000000000000000000000000000000000006000000000000004c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000004004000000000080000000000000000000000000000000000000100000000008008000000000228000000008100004000004020008201000000000000000000000020000000000000000000000000000000000000000000000000000010004000000008000000000200008000000000000000000001008000200000000000200100105028000000000000000000400000000000000000000000000000000400000000010000000400000000000000000000000000000000000000000000000010300000000000000000000000000000000000000000000403000000010080c80a0004000000400000000000000000000000000000000000000000cc6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000a0800000010800000000000000000000000000000000000000000080000000000001000500000200800000000000040300002800000000000000000000000000000000000000000db3600000000000000000000000000000000000130c30000000024c00c00000000800d200000000000000000000000000000000000000000000000100000000000000020200021000000200200000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000040200000000000408200000000000000000000000000000000000000000000000002c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000020000000000000000020010000000000000000000000000000000000010080000000000200400008020000808200001000000010000000000000010000010800400000020001000400d008000000c000000000000000000000000000000002000100002000c01302041000804000080000000000000000000c0000100c04000010000000108004000008a000280100002002800000000000000000000000000000002000000000080000000c008000000000000000000000000000000000001000300200000040010000000000000000000000000000000000000000800008002020404500000000000000000ac6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000c1828200000040000000000000000000000000000000000000000000000000000000000000000000000028000000000000000000000000000000000000000000000000000000000000000000a00000000000028000000000000000000000000000000000000000000000000000000002ec200000000000000000000000000002c011002800840a00200121821000002024044800000000040040000000000000000002000100800005008000280228000200008804004000000a00100000000008002004010000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000040000006c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000002000000400000080000010000000000000000000000000000000000000000000000080000010000002000000400000000000000000000000000030600000000000c18000000000030600080000010c000020000004000000900000101000000000000000000900002100022820000084000000000000000000000000000000000800002101800024000084000000900002100000000000000000400900002100000020000084000000900002100022820000084000000000000000000000000000000000800000100002820000004000000000000000000000000000000000800000100000020000004000000000000000000000000000003060000ec6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (3000000000000000000000000000003aba8000000000eaea78a3b1aee0c0880000000000000000000000000000000000000000000000000000000000000003e2e5b8c2000000400000000000000000000000000000000000000030300000000000c0c62108000000001884200000000001000000000000000000000000000000000000000000774a0000000000000000000000000000c18521909452030614864251480c1852190000003000000000000000000000000000000000000000000028200000040000008000001000028200000040000008000001000000200000040000000000000000000000000000000000000000000000000000000000000000001c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000120adc000000000c4880000000000000000000000000000000000000000000000000045b900000000037084000000000000000000000000001555400000000055550000000001555400002559c00000000011afc100000004039800000000000000000000005abb800001515877d480000000000000000000000000000000000023952c0ea0000171ee0e80000006200900000000000000000000007e95b0000000012a11f7314000030752000014aa6c1cc00000000000000000000000000001008000008020000010802041080000000000000000000000000000000000008352000000000820009c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000083520000000000229000000000000000000000000000000545400000000015157937315ee4c4a80000000000000000000000000000000000000000000000000000000000000000a2e5b8c2000000000000000000000000000000000000000000000030300000000000c0c62108000000001884200000000001000000000000000000000000000000000000000000a8fa00000000000000000000000000055554c0ddd36455555383774d9155554e0dc000001010000000000000000000000000c00000000000000039842110007c7c00001dc2000002888a020800000000000804000000000020000000000000000000000000000000005c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000554400000000000000000000000000000000000000000000000000000000000000000000000000000011d55c000000006c5980000000000000000000000000000000000000000000000000045b900000000055084000000000000000000000000001a9a80000000006a6a0000000001a9a800002119c00000000011ae0100000004179800000040000000000000005a7b8000073108774400000000000000000000000000000000000071042c00000401e2f4be800000062081000000000000008ebc00007d4800000000014811c7314000000110000015a2200dd8000000000000000000000000000100800000802000001080204108000000000000000000dc6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020a0a00000045040020000000000000000000000000000000000000081000000000005028000000000000000000000000000000054000000000151520b624a2c8000000000000000000000000000000000000000000000000000000000000000000000003184a8080000000000000000000000000000000000000000000000000008080000000314a0200000000c52000000c0c00000000000000000000000000000000000000000000de1d0000000000000000000000000006a6a480e3dc639a9a92638f718e6a6a498e2000000000000000000000000000000000e00000000000000039842110007c7c00001dc00000010140550140000000015404000000003c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (e00000022c1a202a00000000008040000000000200000000000000200000000000000000000000000000000000000000000000000000000000000000010a2d800000000004840000000000000000000000000000000000000000000000000084ae000000000620a800000000000000000000000000001a80000000006a6a0000000001a9a800001104c6a6a00000003d8000000000009c1fff0000000000000000004181a00007c01042020000000000000000000000000000000000001b404f5fd000002b860000000004b4a400000000000000000000004e8040000000012b180000000004160800006c2e905068000000000000000000000000000000000000bc6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4c0000000000000000000000000000000000004b0b0000000544042400000000000000000000000000000000000008190000000002142c0000000000000000000000000000303a8000000000eaea1937445058000000000000000000000000000000000000000000000000000000000000000000000003185e108000000000000000000000000000000000000000000000000000108000000021584200000000856000000c0c00000000000000000000000000000000000000000000306d000000000000000000000000000006a64308031c9a9a998c200c726a6a6630800001a9a8000020200000000000000000000000000000000033c52210100000000038007c6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000420000003385621024000000001ce0b0000010544153c0000000010449000000000410240000000000200000000000000000000000000000000000000000000000000000000000000000004817c000000005048d0000000000000000000000000000000000000000000000000085af000000000414ac00000000000000000000000000301540000000005555000000000155540000111c9555500000003f4000000000179d0fff0000000000000000004161300003211242044000000000000000000000000000000000005948105cd000012ad24000000004b6a40000000000000000000000496a0000000001291800000000008a1100005d27022100fc6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (041440000040000011010040000000100000000008000000000000080001000000000011000000800000501000000000000800000000000000000000000000000000080000500200000000000000000000000205000000000000140000000000000880000000000160000003080005803100000000160000000000025800000000000000004000000000800000000000000000000000000800100000000020000000000000000000000000140000000410005000000000000140010400000000000000000000000000000000000069a4000000000000000000000000000c055603220c191555586c883064555561b2200001555400000420000000000000000000026040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000000020000000000000800000000000140000000000005000000000000028000000000005000000000000020000000000000020000000000140000000000000000000000000540800000800005020400000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000001400000000000000000000000001180000000000008800002000000000000000000000000000000000000000040004044000000020041148144004000001001000244800040045000001000000000000001100040000004000000800000000000000000048045001000000001100000000000826040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001000000000000000000040000000000000004800001000000000000000000004c0000000010012000001000000480000000000000000000000008480000000000000000c000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000040000000000001000000000000040000000000c0100001000000024210000000000010000008400014210000400000000000000000004000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000021f300000000040000000000000000000000050000000000001400000004000000426040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000004000000000000100000000000004000000000000000000000000000000000000000100000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000001000000000000000000000000000010000010000000400000000000000000000000004000000000000000000000000000000000000000000000000000041000000000800000000000000600000000000001200000000000000000000040001200000000000000000000001000000000000001004000000000001200000100000000001000000001200c26040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000008010000000000000000000000000400008800200100000010000000000000000000000800000000080000000000000000000000000000040000400000000000000000000000000100000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000002000000000000000000030800000031000001400000010000000000c00000000000400040030000400c000100000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006eec00000000040000000000000000226040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000049da0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000800000800000020000000000000000000000000000100000000000000000000000000000000000000004000004000000100000000000000000000000010000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000080000000000000000040084040000000001002000180000080041000000010000000a26040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000440040000000100000000002841800001040054001001000000041800080020008011000100000040800000000114040000500000000000100000000040002000000041400080000002050000080000080800004200000040000000800200000002000001001000000040000000080000000002041000000080000000008000200020010008000800000000000200a000002001004204008000000008101000000040200002000000108100000000080400000000000808000020000080000004000000008000000000000200000000000002000000000000000000008200400000000000000000410000000000000000000000000000000626040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (002000000000000000000000000000000000000000009ebc0000000000000000000000000000000000000000000000000000000410000800000000020020000800000000800000000000008000000000000000000000000028000000000010000000000020020000000000000000000000000000000000000000100000000001000000000000000100400000024000000000000000000000000000000280048002000000000010080000000000000000002000000000200000000000000011000000000000044000000000000000000000000080000000000008000002000000000000000000000000000000000100000000004000000000000204104400004000e26040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000400c00c0004041100080000000000000000080000040000000c068000000000040410000010400000010040000001002000000000060410000000000010000000000080500002000000011830031800008800000000c20400030000000000020000000000010000000000000820000000001804800000000040000000001000000000000000000800040000000000000000000200008000000000000200000000000800800000000800200000000000008000000000000200002000000008000000000022000003000002000000080000020000010000000000000000000000000000000000000800000000000200000000000108000000000000126040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000800028000000000000a00800000100028008000000000000000000000000000000000000006674000000000000000000000000000000000080000000000002000000001000000000000004000000d000000000000000000000020000000000000800000000000000000000000000800000000000000000000000000000000000000020000000000000000000000000020000000000000800000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000008000000000000080000000000000200000000000000000000000000100000000000000000000000000000000000300000000000000000000926040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000800000000000000000000001500180000000000000000000000040000000000000000000080042840000000001200000000000000000008001081001000008000008040100000000015084000000002000020000080000000a0000020004002800000020180000800400a8400002000000140040000400400080002000000002000000860000000080000000402180000040080000000004032008020020004480800000000000000000000100400ad08008000000040201000010042d029300024102b4200000000000000000000000000004000000000000000000000014010000000000502000000000000000526040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000010000200000000000008000000000040100001020400000000000000004020001000000000000000000000000000000000000000012d0000000000000000000000000000008000a0000000090002800000000000014010d00000000500590002020014000000080802840000000020000020000000000500c200024002a000000000020050090000000000000000000018000000000000000108000001440280000000000000100000000024000000000000000000000000000800542cf4001000000000008040000000000000000001000000000208000000000000001000000000002848000000000000000000012802800000000c00000020000d26040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000010000000002000020000040000000000000000000000000000000000000000000002000001000000000080000020041000000000000000000000000000000000000200000000a8800008000000200000000001000000020000000000000200000040000020000800210000400000000004100000040000000000100810000040000080a4020000000000000000000000001000002000000000000000000000000000000000000020000000080800000000000000000a0000000000002000000010000008004000220002000410010000410c34401000000004000000204010000400024000000000000000000020004022c00001000000200000326040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000001000000000000000000000000000000c00000000800000000000000000000040000001000000000010000000000000001008a2110000002000000000000000000000000000000000005b570000000000000000000000000000802060020001000100000000000000000000400000000000080000010000004000000000000000c01800040000000004301000001040400800040080000000000000000100000000020000000000000000000000000000008200000000040240040000000000000000000000000000000004000010400000000400000000000000000000000000000000000000000002000000800000000000000000000000000000000000b26040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02000000000000000002000000000000000100000002000080000000000002040208089a0000000000000000000000000000000000001900000008000000010102014001000020000400008000000200000000000004400000000000010000002800000000000000000000008018000080000000000000010200002001800000805b118000500000800000000002001010000004011050000000000040f4000000000000000080004000000000000000000000000000000000000000000000000268004000041800000000000400002640040000010001000000000000000008004000000000000000003288029060002020800001048004208400000000000000726040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10c00051008000400008020200050408000108000010000020000030a10000800000400000000000000000000000000000000000100000008000800002120400000000000008020009002000000000000000000000000000000000000000f9c60000000000000000000000000000104004000000006900100100000000000000920000000000020840000000004400000101000040000060014000000000000000020000020800000000400000000100000000000000800000000000800000000000000200000020000000000028004000000000000000000000000040000000000000000001248400000000000000000100000000000000000002000000000000f26040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000800000000200000000000000000000000000000000000010800008000082100008040000000000000000000000000000000000000000000000020000004000020010004000000450000000000000000000000000000400000000000000010880000800000020000001000001000400800000000000020000000080000000008000000020200000840000080000000004000004008008000000008802000000000000000002000040000800000000000000000000000000000000000000000020000000004a00000000000000000200000800000080000000000000080400082800100001000000001040802080000a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010104120008800005208000208408104230012008401200008108000248008000000000000000000000000021400000000000000000200008000404002004200000200080000001100400001008a08200000040026404000003004000000000000000000000000000000000000000da8d00000000000000000000000000008000240200000000009008000000000200000000000000001000200020000000000200008000204408040240080808020800000830000000000000804000000000000000800000000400000000000000000000000000000010000000000000000040000000000000000000000000000000000100114000000002000000000080008a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000800000000020000000000000000000000010000000000000000000080000200000080000008000000000200000100000000040000000080084120100400001100040400000000000000000000000000000000000000800000002004000000040000010020000001001000002000001200000000000009000000000200040102084000000000000000000000000048005080004000000080040000440802080020c020101000100000020000020002000020000000200000c08000000000000000001000000000010088000000002000000800000000000000000030800000000000020000040010010000002008200208000000000088000000080000004a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000102002000400000040080000000000000201002080140080000000004110404002140040000100012001010200000500100000000000000000000080080100000000000000000000000010080000040010401000000000001000410000028205010000000021040410000000004000000000000000000000000000000000002af7000000000000000000000000000000000c0000000020003000000200000008008000000000200000200c0000801000000000100088800840018001010000080820000020400004020000000000020000000000000000000000004000000000000000002080004100100000020000018040001000000000000000200000ca6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000001040000100004000000000000002000000000000100000000010480000000000100000000000000000000c00000000000000000000000003804000000000000000000000000000000003000000000140000040001000400000000000000000000000000000000000041400000400000c0000000000030000240008020000000000000000000000000380400000000040000100010000000000000000000000000008408040000000002001000000000084202140009000000001000000000000000000040000000100000100000000048200008000000000000004000008000000000000000000000000000000000000000000001000000000004000000002a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000100000000000000000000000003000000000000000080000000000c00000000200000180c00000200c00000000000030080400000400000000000000000090100000000000000000200010001000000000400040000000000002000001000800000001000020004000000004800000000000000000000000000000000000000000d9940000000000000000000000000000000000000000020001001000010000040000020000000000024010000000000000044000000008040000000010481000000000100000104000000000000000000020800000000001000000820301000000000000000000000800000000aa6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00800080000000000000000000000000080000000000010000000000000000000000000020000000000000000400000200000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000002000000800000000020000110000000000000000000000000000000000000640000000000020000000800004400000000000000000000004000000000000020000000000000000e800000000000000000000008006408040800000a0000000002001800008008201030100002000000800040208020018000000000008440002000000000100000000000800000000000010000000000000001000000000000000006a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8618400000000000800800800000000000000600002000000000209006000000e000002008000400008000000000000000000000080020000000001000000024040004600400108020204204000140000010000800200010000420000000028000400520000001040000000000000000000000000000000000000000400010400004000000004000000000000000420001002000000000000000000000000080000000000000ff200000000000000000000000000000000032000000820000480080000000001000000000000040000000000001000000000000080200000010010020020000000040100000004002000000000000040000800000000000000300ea6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004000000000000800000000010000000000000000080000000100000000000000140000000000000400000000000080000000000000000000000000000010204480000800100100000010000000004000000002000020000008000000000000000200000000000400000000180000000000000008400008400001000000000040000000000000000200000000000008008000000008000000000100002028004001020000004000180000b001800003c000400000000000c00000000400000000000004040000800000600000480600010000e00000010000140000400000000e0000001000000000000000060004000000000011960060000004000000001001a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000020000000000000000004000000000000000040000000001040040000001000000000c0000004000000004122000208000000010880040002040300200000000000008001002108001100000000040000046000441200020000c0005000802000040000002400000000000000000200000080000000000000000000000000000000000000000000000000082001000020002000000200c000006200000088080000000000000000000000000000000000000000e9ef00000000000000000000000000000000000000000000003800000008000000000200000000000008000000000400000000004000000008100800200124000000024000010000009a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000810004000432000000000000000000000200000000000000000000000000000000000400000010000000000000002000000020002008000000040008000000010000000000000000000001000000000000000000100004000000008000000000000000000100004000000000000000800000000000002000000000001000000000420000000000000100000000000000000000000000000000000000000001001000000000000000000000000010002000000002000000400000000080000008a0000080000000106000080000000000040100020000000000840000000008000000100000000100000000000000001040000000000041000800000000000005a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000114000208004004100204102004000000002000008000400000000000000008000000000000004000000008104004010000204000000200008008004080004244100000002000000500080000040400400000200000010052048008000000000828000828088400440c28028008c00004230030090c02008c90400180000008020040402422000000000000000000000000000000000000000000000000401050408000400040000000010000002484240010000002400000000000000000000000000000000000ca050000000000000000000000000000000100100104100300000100001000000000048000000000000800000000000000000000001000da6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000c0400202000000000020020400000000800100000204203082000201002001000800040020100000000000002000000000000008010000000000000000400000000000002400001000000800001000000000000400000000000000810020000800002010800000000180080002100000001000002001084080000000000400000000000000000000400000000000000000000040000000000000008000004412000000100000000000000100000000000000000000000048002000040000042080040000008002282000080000000000002080101000000001400001001080001001041041081400001022040000002001000000040001040000002406040003a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0820011002041001420880081008010459200040000080048002288000002008000200082000000000000000000000000020000000000000040000000001800200000004000000200000000000200000001012000008400000000420080001000104000200000040100800000003100010000010881010083001000010021841061000010840000000008461008050000000801000002000880000000002000000000000000100000000020000000000000020020000000400000000800000008000900000004000104040000000000000000000000000000000000065f10000000000000000000000000002000084080082080080002080080001000020800000ba6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000002000060000800000004410000000000100000000000004000410100001000000000000000800a08000000108000000000000000800000000100000000000000000000004000000000080002001002100000002082000000010200000000000000010000000000800008120200020000008200000000008208200004080040008200000008000200020000804000000800010000011000000000000001000000000020000020000000480000000008000000000010000000000001000000000000000000000001808080202000001000840020040000240020a0200004008000080000822008002104004800820000000808122801800044988002007a6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (320008200020800008800001200200025008001040828900001820008824082089c80282a6000060900026820800000c12022000000800002000400000000000000000000002000000002000000000020000000000000000000000000000000000000000120000000000000000000000200000000000000000000008000010040000100000102103000000000000010208000000103000021000034000a01e0000000000000001000400000000000080008000000000410d00000000000430000400000020000000000000300000100000000000087004000380004080000000000000000000000000000000000056750000000000000000000000000002000000fa6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (d6f7000000000000000000000000000000000a0000000000001000000000018000000100002d101008200000040000000001000020000000400000210000000008101000900000000c0000000000004000020000000800000020004001000040080002000000200001000040000041002201200000000000080000002000000000000000019002000900000000000000000000080000000000008000000000000000000000000000000000000000050000000000000020000000010400000000020000004100020000000000000000004002000000000042000040000781000050081009a0008028022008002c08800080100000804000000000200004001c0100066040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0020000000048000c30010002420a001400004453020000000000000200020828410100a594042108004100895000000020830002020c4400040104422800000c00000020c0000001080000100000002000000000d100800000000000800000000000004004000000000000000000000000000000000000000000082000000220000200000040402000000001000040000040400000400004a102000100108000000000101104000040010c001004b000c901000000040000000108082000000000000400a00000d040000000000011000001000000000010000000000000000080081004000002002000002000000000000000000000000004000000000000000866040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000b8100000000000000000000000000000000000000000000000080000000008004000420000c000000000000100040000000000100000000204100008a10000000000000200000000000000000000101400000000000000000000000010000200000a0002000000000812000000020801000c00000000000040000000028800000024a00004000010280000000000000000002000040000000000000000000023000000000000000020010021000090080000000a0001000000000841048000000800000000001000000002000000000001000000000408040048000028000000d0800044011000000050000100000466040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000400800a000000000300000000000004000000000000000000000000000880020000000000000000000000000000000000000000000000000000000140100000000800000001000000000000000000000804000000040000000000000000020000000000000100000021000000000000000000000000000000000000000001280000000020008005c000000000b000000020020100000000800000080040000c01000808000400000000000020c20000804000080002520000200006000000000000000040000000004000000000000000000000008000000000000080050040000000000080004000000002000920000000028001000000000c66040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (016d00000000a142b4000000820004c000000000000000000000000000000000000000004e52000000000000000000000000000400400001028010000000400a00000000000000000000000008002000000000000148804200000000014810000000000000000020005c00040000008000000000010000000000000000000000000000000000000000000000000000040600000c0000000200000000000000000001010000000080140000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000a00010e0002a00a0000000000000000000000000000000800000000024000266040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000100000000000200000000008000080000010000000000000000000000000400000000000000000000000010140a00000000000000000000000000000000000000000000000000000000000020000240a0000000000000000000000000000000000000000000000000000000000000000000000000000000404000000000000000000000000000000000000000000400894000500008002d00000000000080005005000002000000000000000000400200000001100000200500000008230002000020000009c0400000c0000000000000000000000000000000000000000000000000000001400000000200000010009400000000000a66040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000000000000000002000000000000014080000000042000100000002001d00000000000000000000000000000000000000000000580300000000000000000000000000054040000400001502a000000000001000000000000000000020001000000000000000300125000000040000b48000000400008008000000100000000000000400008000000000000000000000000000000000000000000008003000100000040000000000000000000000000000020000000000800004000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080020000400002000850021000000000000666040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000200000000000000030000500000000000000000000000000000000000000000400000000000000000020000000000000000000000000000000000000000000000000014080000000000000000000000000020000000400000000000000000000000000002000800000004000000000000000000000000000000080001000200000000000002000400000020010022800800000000000000000000000000000000000000000000000000400000000004080000000000000000000028000000000000a000050010004000400002000208004404400001040000000000000040041600044008000000000000000100280002000400000000000000000000000e66040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000100800030010000000000000000000000080004000000002000400900a04084086030206102102180c00084084086020a06100102000000000000000000000000000000000000e607000000000000000000000000000400400000001010002000040040000000000400000000600000000000000000800000080000040800009024000001000000000000000000000000000000000400020002000000000000000000000000000000000000000000000000000000000000028005000000000000000000000000002000000000010000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000166040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000080000001002009000844880902000000000000000000000000000000002000080000000800020100001000000082420000000010100000000000000400000000000000080822000084000000000000000000002000100040000000000000000000000000000010048009004080040000404000000000000000000000000100010000000000000080000000004000404000102000800000000000000000000000000000000000000001128140508408403000210210210090028000801080000200000080002200900020085000240006020290028002001080800200002000288050a00c2511000000000000000966040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (24018000020118000021000000000000000000100108004804800000000000000000000008000400000000200000090058408008402062a1021021400008840840840822000001020000000000000000000000000000000000008e930000000000000000000000000000400800110240010220001009000000000000000800002000200000000000004000a0882281021021041204848840840200020020022000040000010000080200000004000000000000000000000000000000000000000010002000100000100000020000000000000000000000040000002000000402000080020000000000000000000000000000000000000000000000000000000000566040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000001808000000000000000000000000000000000000000000000000200000000000000040000000000004400400000000110090000000000000400000000000000000064000004040000000000000000000000080000000000000000000000000000000100002004004080000000000000000000000000000002000080000000000000000100000000000000000000000000800000000000000000000000000000000000000000208018508008400006a1021021008000000000508080000000008000020020000404100028020584004000000040420200000d66040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010040000000204000000000000000001a0040000010000000021014000000000000000000000054090000000000000000000000000000000000000000000000800000002000100000000000000000000000000000000000000000000000000000000000000000000000386b000000000000000000000000000040080011020001022000200800001000000000000000402000002000000000000080002061020021040820840840840000000021022a00080000000000080000010000000000000000000000000000000000000000000000002000040000000a00020000000000000000000000010108004000000804200000000000000000000000000000366040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000200000000000000000000000000000000200008000000100000000000000000000000000000008000000000000000000000000000000000001200020001000000000000000000000000000000000000000000000000000000001004000900000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000080220010000000000000000000000800810080000200020000000000000100000b66040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000020002000020000000010000002001000008081008400000000110000003000080010000000000082000801000000000000000000000000000000020000000000000000000000000000000000000000000000000030030000000000c00c0000200003003040000000040080000000000000000000000000000000000084ca000000000000000000000000000000100008000000000000900000000000000000080040000000004000000000000010001000000000000009000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000766040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000002800080004000082403000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010800000004080000000000000000000000000000000000000000000000000000000000000000010200000000400000000000000010000000000000000800000800000000000000000000000000000000000000000000000000000000000000800000000010000400000020000000000000000008000000000000000000000001000000000000000000000040000000000000000000000000000000000000000000000080001030030020000000c00c000f66040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000008501110080284050000002102100080a8210a0428100020000c0000008008000200080101000000002100300a100012001400020100015001080092c8500000000000000000000400000000000000000000000000000000000000000000004008031000800850a8020002102101509200084084b00012800102000000000000000000000000000000000000b96d00000000000000000000000000000004002000400000000000010000002000000010000000000000000000000020000000080000c00c0a02000203003000000400000080000000000000000400000000040000000000000000000000000000000000000000000000000000001000000e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000030000000000200100000a00002000000000000000000000004000001000000000080020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100040000000001704040080822000000000000000000000000000000000100000000000000000000000000000404400000000010310000000000000400000000000000281000000880020000000000000000000000000000000000000000000000000000000040150000801000000000000000000000000000000002000100040000000000000000030000000000000102002000000000000000000000000000000000000008e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000400000000000000000000000000000000000000000100521909452000014864251480001015219000000000400000000000002820000004000000800000100002800000000000000800000100002820000004000000000000000002820000004000000000000000000020000004000000800000100005219094520000148642514800005219094520000148640000000000000000000000000000000000000000c942000000000000000000000000000400400a0000401000002848010000001000040008010000200800000000000020000830024012022100c0042108428400001000010200000000000000000002000000040000000000000000000000004e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000008000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000400000080000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100280000000000000000000000000000000000000000080000200000000400000032600080000200c1800000000003000000000000000000000000000004009000021000000000000000000008000020000000040000000000001000000000228240000840000001000000000000000000800000008000021000200000000000000000000000000000200000ce6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000b0000000000000000000000080000000000000000000000000000000000000000000004c0ddd36440001383774d91002a224e0dc00000a888000000000000018b7884221fdfc00007555f220c18c8400003000c00007a84100f008040046500000000000000000018909c1108000000000000000000000011084000000000442100004c0ddd36440c0d383774d9103034e0ddd36440c0d393700000000000000000000000000000000000000001f8200000000000000000000000000000000000000000000000000000000000020000004000000800000100000020000004000148642514800005219094520000148e4000010000000000000002e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4e0ddd364400013837044211f03000000000000000000008200000000000000000000000000000000000000000001000000000000000004000000000000000000000000000000051e40000000007d42400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000020001800000000000000000000000000000000000000000005a8000000000000000155540100164005555000000000000000000000000000000000000283b0000045d1c00000000000000000000006200000000000000000000000000000000004a9cc6a57f700000000000000000000000000000000004abb8000ae6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000523b8000000000000000b000000000000000000000008000000000000000000000000000000000000000000000484e3dc63800012638f718e000a0049ce2000002800000000000000019bb895224000000000cca72a0c18c8400003000c00007a8211310080c695c700000000000000000018908e010800000000000000000000001108400000000044210000480e3dc6380c0d2638f718e0303498e3dc6380c0d27388000000000000000000000000000000000000000a2510000000000000000000000000000404004000000010100100000000000000018c108000000003cc00000000000110840d01303774d910000006e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (3cc00000000000110840c012038f718e000049ce3dc63800012638844211f0300000000000000000015405000000000000000000000000000000000000000006c000000000000000004000000000000000000000000000000063c60000000006fc0400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000001004000000000000000000000000000000000000000005a400ea000000000001a9a801000a8006a6a0000000000000000000000000000000000002bfbc000046ea00000000000000000000000620000000000000000000000000000000000103fee2fdc7000000ee6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000020ffa023f8000000000000000000000000020000000004ac1a0000000000000000000000000003300000002102800000000000000000000000000000000000000000a0064308031c8000198c200c72000a006630810000000000000400000002db2044290000000001144657570088800000015400004b840eec800842601500000000000000000000801610000000000000000000000000210a8000000000842a000064308031c8000198c220e72000066308839c80c0d98c2202000000000000000000000000000000000000039580000000000000000000000000000000004000000000000100000000000000018c00000000000001e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000202000000000014c0000000000009c00000000000210a8000190c200c721f0066308031c8000198c20842a0000000008080000000000080a80000000000000000000000002000000000000000000000000202001b1b000000000000000000000000000000000021250000000005bc400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004500000000000000000000000000000000000000000418000000000000000001a80000404006a6a0000000001a9a800000000000000000000000000000001dc5200000000000000000000004b4000000000000009e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000004b4010000000000080000000000002000000182bf06fb4000000000020000000000000004000000004a4130000000100000000000000042005f00000002142c00000000000000000000000000000000000000002a22603220c190000186c883064002a2261b2200800000000000020000003191e44210000000000aaab030300898000000154000043e28e0c80088a55b240000000000000000000801200240000000000000000000000214ac000000000852b0000603220c190000186c887264000061b221c9900c0d86c88420000000000000000000000000000000000000e9610000000000000000000000000000000000008080005e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000404000001080010100000042000000000014c0240000000009c89000000000214ac000180c8872641f4061b220c190000186c88852b00000000010800000000001054f0000000000000000000000002000000000000000000000000042000000000000000000000000000000000000000023250000000005a84900000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000020000010005400000000000000000000000000000000000000004140100000000000803015400004880955550000000001555400000000000000000000000000000001ae00000de6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1100000004000044000020000141100021040000000040200000001140001000020044000801000081100000000000045000040040005100000000000045000220000001120000000020000000800000000000000080000000000000000001400000000000000000200000001400000000000050020000000001400000000001000504000000000000000000000000500004000000000000000000000000000000000000000000000000d00000000000016000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000003f2a0000003e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0800000000000000000000000000bbac00502000010040000000200000000000008000000020000200000000040000000000000000000040000200050000000000000000000000000000000000000000008000000100000000000000000000000000000208000000000080080000000000158000000000000000008000000200000000000000000000000002000000000400000080080000000000000000000000000000000000000080000000000002000000000002080000000008014000000000000080000000000000000000000000880000000000002000000000000000000008000000000000000000002000010000004000000400004441000000000000be6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010000001000000400208488000200000000000000000020498001400000412c00050400200480008200200012018010000000480000000000012000208000000480000000008012600200200000480000400000000400000000418000010000000012000000000000000000000208000000000000000000000000000000000000000000000400000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000060000000100000040000000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000007e6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000800000000000000000000000000d276000000000000000000010000000000000400100000400010000000000000000000c0020000000840000800400000000000000000000000000000000000000000000000000000000000000010000000400000000040000000000000000000000000040000000000000100000000000204000000000000000000000000001000000040000000000000000008000000000000000000000000000408200000000010000200000000400000000110000000100000000400000000000000000000000000000000000000010000000000000000000010000612000000000200480000fe6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000040000100000000000000000000081402000040000000000000000000800000100000000000024000040000021240080000020000000020000000800800000000041000000000800020021000000040080000000800200000000000000000000000000000000000000000000000000000000022000000000000000000000200000000000000000000000000000000000000000000040000004000000000000000000000000000004000000000000000000000000000000000000000000000000200000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000016040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000045bf00100000004040000000000000000000000008000000000000000000080000000000080000002000002100100000000000000000000000000000000000000000004000000000000000000010000000400000000100000000000000000000000000000000000000000400010000000008000000000000000000000001004000000300000040040000000020000000000000000000000000000010400000000000000400000004000000000040000000100000000000000000000000000000000000000000000000000000000000816040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400000000400a008100000000200200008000000000000000000008100000004004006000000104084000400410000005000004000004000000000000404000100000408100000484000c04100010200000100020000001004105100000200100008200000004100000000200100008000080006000000000000000000000182000000200000200100000080000000000000001020004000800000000000000000000040000000080100100000100200000000000000000011000000000000000040000000000800000002000000000000000000000800000000000000400000000020000000202000088000000000000000000000000000400000000000000000416040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006fa10010200000000000000024000000000000800000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000800800000000008008000000000010900000000000040000000000100100000000000008000000000000002000000000000080000000000000000000000000084000000010008000c00000c002000110020000080000000800040000000000001080000000000000c16040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000001020000000000040000000000001000000000000000000000000000000000000000000000000000000000000000400400000000010402620000000400000420001001821010000000800010400010000000010000000000e100400004000000100028000000804400800000040101810400000004000000000408100010000020004800000000200100000000400000000000000000000000008000000000000000020210300801800000000000000000200000000000008000000000000200000000002000084000000000000000000000000080000000001000000000000000000000800000000000000000000480000000000202000008000000000216040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00401900a0001000020402d0000c000000000000000000000000000040000000000000000000000000000000000000000000000000000000020000000000000000500c0000000000000000000000000000000000000039cd00000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000008000000000002000000000000090000000000000000000000000003000000000000000000000000000010010000000000100000000050000401000021400000048000000000000a16040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010140451800000405000200011000140a0000050002800000000000014000000000000000000008009000200000000200500088000000000000000000008580000000800001000000020000000200200004003014900004200000080002000008020000000008000080248000000000100204400500d0800090001400a3000002000024200001000142300000000000009200000000a0000000000201000000000041000000200000200000084008000000000000001002800000000000000000800014002040000000140240200000204a00000000000000000410000000000000000080020000a00400020000000000000000000000000000000000000000616040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000020000000000010000000000080000000000100002000000400400000000000000000000000000000000000000000010000000000000200000000000000800008000000800000000010020010000010100000000000000000000000000000000000b426000000000000000000000400040000000000000000000000000008000000000000000008000000000001000a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000001000000000000000000000001001010000000000040400000000000010000000000000400000000000010010000000000400300000e16040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000001000000000000001004108202000000012080000000000080204c000000000840000000044000000000000200801000000000000000000000000800000000000000000000000000000008000400000800000000008000800000808200000228200000020010001000214222010000200800000000202a8000400000000001000000800000000020000800020980120800000000000040000000050000004000000000008000000000000000000000000000000020000000000000000801000000000000800000000004800000000000a0000040000002000000010000000000000400000100000000000000800000000000000000116040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000040000000000000000100000000000000000000000008000000000060000000000104c03000000100000000000080000000000000000000000000000000000000000000000000000002000000000000080000000000000006000002012680000000000000000000000000000000000002ea400000000000000000000080000000000008080020080000200800400000000000000000000000000000040000000000000000000000000000000000000000000000000400000000000100000000000000000000000000000000000000000000000000030000080800003000010820000000000000000000000000000000000908000000000916040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (080000000000040000000000000000000000000000000000000000000020000000000000040000886140000040000124000000010944810844840000800000050000804190002001000000040082000008000000000800000800002400000000000000000c000000000000041008000000000004008040184069002080200000100200404181900000086c001000404000000040080000033120012c40810001080e0000005002000044000000000040804000102101442000000408004041880900000020200000000000000000000080000000000000000000000000000000000000000000002008000000004000060000000018001000000000000418184000516040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (200000000000000000000000000000000020000000000000000000000800000000000000001000000000002000000000001200000000000801000008001020000000020800000000000000000000000000000000000000000001000000000000020000000000000080000400000082000000000002000020000000000000000000000000000000000000000041f1000000000000000000000000000000000010020000000000430002000000000000000000000000080000400000000000000000000000100200000000000000000000000000000000000000000000000000000000000000000000000000000800840000c4020000008000400000000000002000d16040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000480a188000800000a044008200000040000000000004000000000000000900000000000000000000000000000000000000003000040020a008490100400000010408000208200080100200000010000100008210000020004000004200820400080008000000000000000080000000000000000000000001000000000000020100000000000000205000030000000000000000200200240828421200000008400000000041200020010000000000040208400010000000000408404008000012008000000000200000800205000400002000000080000000000000000000000000000000000000000000000000000000000000000000800000000000000000316040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0100000000008000000000022000000000402000000000000880000001000000000000000000008000000000000080000040000001000000000000000000000000000000000000000080800040000400021201240000200020000020000000000000000000000000000000000000000000000000000000000000000000000108000000000010000000300000200000000000000000000000000000000000157700000000000000000000000000000000004000090000000200000800000000000000001000000000000000000000004000000000000010020000000000000000000000000000000000000000000000000000000000000000000000000000000000b16040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000500000200004220000011800100800004210000000000000100020000000004000000000000000000000000000000040110000000000000020e22004002000020000010440040c40000845001100000020440020c23080002000000108001000000004a100000000200880000004000000000000000220000000020002000000400000000024000001000801021041010000c2002021120101120204940004100000040800200105100910020008428000820c000000804c00080810004000008000209010430000002004000040120000000100000008000008000000200000000080000000000000000000040a00716040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000010124800000000000000000000000000000000000000000000800100000000020000000000400800000000000200000000000000000000000000001000000000000000000000000000000000000000000000000000000240000000000000000040008000000000010000000000000000000000000000000000000000000000000000000400000000000010104000000000000000000000000000000000000000000000000000000000000cd6900000000000000000000080000000020000000000420000000000200000000000000000000000000000000040000000000000000000000000000040000000000000000400000000000400000000000f16040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000d0000000000000000000010000d00088101020100000004000800001000100000000000000020000000000000000000000000010000010000000050000000000000400040108821000020008100051400010014029400100401000000400010041020000000000400000000040000601000001000200000000000000000000000000000000000000104034020000000000004000a20824825000800400000c14104010620481400000120004800000400800868a00000000820000020410044921a000000104250400200000001106000041004208000000000888400040000000000400004000000096040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000201000200000040000080000000000002000000006012010000000000000000020000000000000000000000010000000000000000000c000000000000300000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000020020000000000c0000000004000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000840400000000000000000000000000000000000000004a800000000000000000000300008000000000041010100000001000400000000000000000000000000000208000000010000200000000000040000000000896040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08020000000000100000000000080000040000000000000000000000000000000000000000000000000011000000000000000000040000020900400000000000290000000000080000000000000000000000000000000000000000000002000002000000000020000000000080000101000000401004410000000000139000400050c08000000000000101860000400000080800000000000201000000004000000000000000000000000004000000000000180a0840000400000000040020270b00020000041801000200042078300008000002c80024000200010008000000801c08020000020070108008000a01e08281040001070001000008000ec8008000496040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000010000010040800018000000400001004000420100018000000000000000040000010018000000001000000000600000000100000800020021000800002080000000000401080002100000000000021000000080000000000000020000000000000000000000000000000010000000000420000020000000000000000009c06000068000000088000000200200000000000000060000000400000000000000400000000000000000000000000000000000400030000000000000800000070200040000000000000000000000000000000000006bd00000000000000000000000000000040000800000000000020000000000000000000000000000010000000c96040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (100000000000000000000000800000400000000000000000000000000000000000000401000010000000000000000000000000000000000000000000000000000000400000000000200082100008118400800010002002000800000000000000000000000040000080000000000000000000000010000000000000000000002000000000000000000000000000000800000000188000808000080000800000001000000000002800080028000000000000000000000000000000000000000400000000000400180000000004004000000000882100000000000000000000080800002180051808008c000000802001140000020000061000064000002008000000296040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000041000001200000000001940010080002000000820000010040000080000000000210000010000000000008010001000000200000000008000000200400000000000000000010000000200000000002080000000000400000004000410010000000000004500000000004000240000008000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000040000000000001040000000000000000000000000000000000000059d200000000000000000000000000000000000000000000000000a96040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000080000020800002000000000000000000000000000000000000000000000000000000000000000040000400000000000000000000000000000000000000000000000000000000000000400000000000000008200000000400000010000000020008000000000000000000000000000000000000000000000400400000000400000000000000000000800010000000000002000000100010000000000001000820200000a006000000000010090002000000800404000000000000000000000400000000000100000000180000100000000100000044044004000005008000000000000000202100202000000820000008002084100900696040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00120801180020080c80080880080000a02000002082420081000000000004000800080c0000000880000100200001004200000009140240100600000000200200008000008000010000200002008044000000000048200400100001008000000000000000000000000000008005004080080002024000012000000008040000000000000000000000000000001000000000000000008044000001000000008000000000000000000820000a00000000000000000001000000000000000000000000000000000000000200100000000008000001000000040000000000100000400000004100900000000000000000000000000000000000012c02000000000000e96040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000007e840000000004000000000000000000000000800000000000020800000000000000000200000000000000000000000000200108000004014000140000000000000000000000000000000000000000000000000000000000000000000000080000002000105000081000000000800000000220100000000000000000080000400000800000000004000000000000000010000000000000000020004030000000410000090000001000000010410000000010400808000000000010100048008020042001040100000810041030800000000100000080080080000000000002000000001000000002042020802080004000000044400000196040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000200042009001050000000000040346080000800008200000220010248000a8280000000120028888101a0600400010600a000008048100810040a00284940000020828000000000100001000040100000004000200000000a40000000000100400000004000400000000008010000008082000000000000001000010001020040080000020421000004000080100000010000000000000000000800420008400002000000000100b1002602800200210004000001000041000820000401000000000000000000800000000040000000000000000000000000000400000000000010000000800000028000000000200004000000002000000000000000000000996040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000014400000200000800000000000000000000000000000000000be9701000000000000000000200000000000000000000000000001000000000000000000800000001020000000000000000000800000020020004c0000010000000000000400000000000000000000000000000000000000000000000000880000000000040000000000004001000020240044000000000000000000020000000000000000000040000104004000100014000000008000000000004000000000000008010002000000000000410000008000000010001002000000000028000000028002460000000000120800000000000000000020020060000000101106900000000000596040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000402000040000092000001040008000000008000208d000200000200b0080000800a005c200100002002200020008000408000800800403080208a8808004200028802084b00800084008210000208000010b204014200c280c080004000000000002010000000064000000002000000400000000002080000000900000800000200000008000000000000002100000008000000000000000400208000000000000000000000004000040001000000000000000000000401001200000200200004000001040081000100000002300000000000000000000000000000000000000000000000000000000000400000000000000000000000008400000000d96040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000008200200000000100000000000000000000000000000000000000000000000000000c718000000000200000020000000000800000000000000040000010000020000000000000000000000000000000c000000080002000000040100000000000000080000000400000000000000000000000000000000400c0000000000000000000000480d20000000000000000000006012008000000000000000000020000000000000000000001000810000000000000000000000000008010410003000408249020000008610201c082010000003000000000000108000100000400008000014008000000000000810000030800000000000396040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08800002000010000000200000000000000000000000040088010000048002000210000214000000110110106310b0000100000010432e800c40200a000c04002440300811134052028102040840560022205300000042280040002c802c800130800180820000400208410400111302000000100000004200008000000000000000000000010000004000000000000041001010a0400000000004000000100020000000004000000000120100000000200000000000000000040000008000000040000000000000000000008080000002000000000000000048020000040200000040000000801000000000000000000080008000000000000008000000000000b96040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000010000000000000000000000000002000000000800880000000008000000000000002010000000000000000000000000000000000007eae000000000000000008002000000200000000005008300000000000010000000000000000400020000000000000000000000000000000010000000000000000000000000000000000000000000000000000000100000000000000000040000000300008a28000000000000a00000002008000000000000a00000000000000000000000000008000800000050300050000000000400c32041340a800410040840204000030400800420b00000040004020000800408010400000000000020000796040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000500400010000400000100300200000000031018000000000000a000100030000000000000000000000000000000000000000000000000000000300000000000a0000000000000c020400004408d0042020008000000000000800000000c00000002010100000a10200000400000404800080004c00000080000008000020000000100c00000000080200000000002014000000000000300000000000020000000000000000000000000000000000000000000a000100004000100000000800000000040000000000000000000000000000000200000000000000000000000000000000000000000000000000000001001800000000860300000000000000000f96040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002800000000000000400000000000000000000000080000000000000000000000000000000000000002000000000000010000000000101000000000000020000000000000000000000000000000000000b3f2000000000000000000000000000000000000000000800100000008000000000000000000000000000800000000000000000000000000000000004000000000000040080000000000000000000000000100000000000000000000000000000001010000000000200000000000026000000000000000000000000000020100000000c000000080040000000000000000000000040000000300202000000000000080060200000200000000800000056040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (350000000000000800020000020010200003000000800000000a40100000800825000000004004b4000000028006900000000000000000000000000000000000000000000000000000000000000800000008020000000000020000c0010018000100808000000010000004004000080000000000040010000000001000000000100010010a880000800000040080000020010100000000000000010000000000000401000000000000004000000000100900000100020000000000000000000000400000000000008000000000000200014000000000000000000000000000000000000000005028028000000000000000000000000000000000000000a0008000856040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000020000400000000000000000000000000000800000000000020020000000000200a00000000025008000000000140200000000000004000000000820025000000000000000000000000000000000000263000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000001000000000000100000000000000000000000000000000000000000000000000000000220100940000000040aad00000000800db0000000000000000000000000000000000100000000000800000000028008000000000000a0000802100000456040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000010000000000000000000000000000280000800208000000000000100010000000000200000000000a00880000000000000008001000000000080000028000000000000000000000000000000000000000000000000000000000000020200000500004000040800010008000110200000000000000000000000000000004000000000004002004008000000400000000004000000000000000000000004000000000008000000000840440000000011021000000000500400000000024004008004000000100000000000000000000000140000000a0000500500000000000000000100000000005000000000000000a0000000000000000500014000c56040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000080010000002002000100008040000000000000000000000000000040008000200000000200002000000000000000000000000004020000000000900100000000020048000000001200800000000048080000000002100a00000000048890200000000000100000000000000000000000eacc0000000000000000000000000000000000000000000000000020000000000000000000000000000002001400000000000000000000000000000010000000000001000400000000050000000000000000000000000000000000000000000000080080000000000000000000000000000000000000000000000000000000000000000000000000000000256040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000040000000000000000000000001001000000000000040001002002024828000020021000001000080810880800200004004000202000044044090090102102100100484084084088022000002000000000000000000000000000000000000000000000000000000000000080050020800100000040002011020011040008020000820200200800020012000200000800040408800480030808400002000220402000102010000040001000480808440009000000000000044000000001000400000000048050000000001200a0100040004000800000000000000080010000404009002800120120800020000004000010000001000200000a56040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (22120080000000004000000020001000200000000000000080000000002002000100008060000000000000000000000000000040000000600001008600001040000000000000000000000084004000000002100100000000000094000000000200000000000088084000000000000000000000014080a0000000000000000000000000000000000098f20000000000000000000000000000000000000000002000800040100000000000000000000000000002000400000000000000000000000000000040210000000009000000000000240220000000000001000000000000000000000000000002140820448488409008a10210210080248408408400000000656040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0840000421021021020002800840800000000000000000000000004000000000008000000000000200000000000000008000150010080a018000000081080202000500000000000100008084000a020480400000800461020021001000840840840080080001024000000000000000000000000000000000000000000000000000000020000000680410000000080000020800201048900040000010002000000000800180000a000000002010000000000801004100000024020000000000800000008200000080010000806000000008800800000000020220000000000000000000000200100000000000004400000000000000080000000404009000080100e56040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000020002000000400080080010010120002000000400000808000100000000000000000000001000000000000000000008000000000000000000000000000000000800010000000400000204000000000000000000000000002000000000000080000000000000000000000080000000000002000000000000000000000000000089000000000000000000000000000000000000063070000000000000000000000000000000000000000004000000000000000000000000000000000000008000400000000000000000000000000000000010000000000408800000000220020000000000000400000000000000000000000000000010058408000156040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000401000400000000000000000000000000000000000000000000000000000000400000000000000200000000000000000000000a000000200000004200000002000000010000022080000000000000000000140100000002000400000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000008800000010000000000009100000000000002000200000000000000000400000000080000000200000000000040000002000000004010200800008120200000000002000000000000000000000000000080000000000002000000000000080000200000000000000956040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000008000000000000000000000000004000000000100100000000000004000000000001000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000010000000000000c00400000000000000000000000000400000000000000000000002400000000000020400000000000000400000000000000000000000a5610000000000000000000000000000000000000000000000400040200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000556040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000000000000800c00000000000000000000000000000000000000000000000000030830090004000c00c0000000003003000000000000000000400800020000000000000000000000000000000000000000000000001400000000000000002000400800000006000000000040010000101100004000000010000c00c00000000030030000000c0000080000000000000000000000000000000000000000000000000000000000000000000100000000000002000000002000000040080002020020082000000000000000000000080080000400100002000000004000000002001001000000000010000040000400000000000001000000000000000000000d56040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000004000000000100000000000004c048000000000200200800200000004000000000000000800200000000008028010000001000200008000000080400100000000000000000000000100002000000000000000000000000000000000000000000000000080000010000000200000004000000000000000000000040440000000001009000000000a000400000000080100000000000000400000000120280000000002530d0000000000000000000000000000000000001fee00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0000000000356040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000200000000000000080000000002000000000000000004000000000000000000000000000001001100080084050010002102100000000084080000000000000000000000000000100000000000200000000000008000000000400000000008008400c00000200000000000000008090c0800000004004001000400008030010004002002101000c00084084000020001102400000000000000000000000000000000000000000000000000000000000d0000000c000200000040040010a00020810000040000000000000000000000000000000000000000c0003000400c00100300000001480044100000c02120000040080000000b56040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000002400008400000090000210002280000000032600000000000c18000000000030600000000200c1800000000003000000000000000000000000000004000000000010100200000000004000000000000100000000000000000000000000001000000000000040000000000000000000000000000000000000001000000000000000080000010000000000000030600000000000c18000000000030600000000000c18000000000030600000000000c1800000000003060a080000010c00000000000000000000000000000000034e10000000000000000000000000000000000000000000000800020080000000000000000000000000000000000000000756040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000c18000000000030600000000000c1800000000003000000000000000000000000000000000000000000052190945200001486425148000052190945200000000000000000000002000000430600000000000c18000000000030600000000000c18282000000430600080000010c182800000000300000000000000002820000004000148642514800005219094520000148e4000010000000000000000000000000000000000000008000000000000000002282400008400000010000000002282400008400000090000210000002000008400000090000200002082400008400000090000200f56040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000610133a003d0004257c7400000053804c22200000206e0000000003040b0200112a600001555400000000055550000000001555400000000055550000000000fec000000000000000000000000a8880000000002a22000008c000a8880000000000000000000000000000000000000004fa00000000009c000000000000000000000000000000000000003e3000000000000404000042066000000000000015554000000000555500000000015554000000000555500000000015554000000000555500000000015554621084421000000000000000000000000000000000009ed9000000000000000000000000000000000000000000000a0000000000000d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000003030000000000000000000000055550000000001555400000000055550000000000000000000000000000000000000000000000000000004c0ddd36440001383774d9100004e0ddd3644000000000000000000000000df085555400000000055550000000001555400000000055550004011005555400000555655550004000000a804000000000000018080000800001303774d9100004e0ddd364400013837000200000000000000000000000000000000000000000000000000000000000029cc62ee388440000000001d316aa32ea1983400000045c09000000000940870c0008d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2fb1983400000046c81000000000000870c00000061013fa006f800d7fdc740000004be46ce0300000d177c00000000002a0020042a2200001a9a80100000006a6a0000000001a9a80000000006a6a0000000000fec00000000000000000000000028000000000000a00004008c00028000000000000000000040000000000000000000000fe000000000000000000000000000000000000000000000000003ff00000000000040400004202000000000000001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a862108442100000000000000000000000000000000000c1ea00000000000000000000004d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000067b40000000000000000000000000000000000000000000001088000000000000000000000000000000000303000000000000000000000006a6a0000000001a9a80000000006a6a000000000000000000000000000000000000000000000000004000480e3dc63800012638f718e0000498e3dc638000000000000000000000000ce085a9a80000000006a6a0000000001a9a80000000006a6a0800000001a9a80000055566a6a0800000000fc000000000000000100801008000012038f718e0000498e3dc63800012638840200000000000000000000000000000000000000000000000000000000000031cc62ee388c00000000001d1172a300cd6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000007c88a02868000000000020000336ab61269080000000019ca4000000000400a8000000001300400007f800213f8000000001385800000000020ab0015400004164a0000082e80000001a80000000006a6a0000000001a9a80000000086a6a0000000001a9a80000000000000000000000000000000040000a0000001540000000000004000000a00000000000000000000000000000000001000000000000000000000000000000000000000000000000000001000000000000420420000000000000001a80000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000006a6a0000000001a9a803148842a6a6a0000000000000000000002d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (555402158852b555500000000000000000000000000000005bb2000000000000000000000000000000000010000000000000400000000000000000000000000000000000000000808000000000000000006a0000000001a9a80000000006a6a0000000001a9a8000000000000000000000000000000000000000064318031c8000198c200c72000066308031c80000000000000000000000014508801a80000000006a6a0000000001a9a80000000006a6a0001000021a9a80000184406a6a0001000021a9a8000000200000000008200a0000190c200c72000066308031c8000198c2080280000000000000000000000000000000000000002000000000000000ad6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000100000000000004000000000000000007d09a0284c000000000020000335fb610790c000000001aea50000000002808c000000001320d00007381465fb40000000013e4100000000105f3c0154000008a01000020a601080301540000000005555000000000155540000000015555000000000155540000042000000000000000000000000002002a2200001448000000000000200002a220000000000000000000000000000000000800000000000000000000000000000000000000000000000000000800000000004620300000000000003015400000000055550000000001555400000000055550000000001555400000000055550000000001006d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000006fc7000000000000000000000000001000000010000000001000400000000000000000000000000000000000000000108000000000000000c055000000000155540000000005555000000000155540000000000000000000000400000000000000000603320c990000186c883064000061b220c1900000000000000000000000016408b015400000000055550000000001555400000000055550081200085555400001854155550001200005555400000420000000001c20424000180c883064000061b220c190000186c8881090000000000000000000ed6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000020000000000000800000000000000000000000000900000000000110100100000000000000000000800000000000004400000000004114000000000000000000000000000100000000000100084000000110000000000000000080000000000000000000000020000000080000000000000000000000000000004000000000000800000000000000000400000005000000000000140000000000005000000000000140000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000050000000000001400000000000000000000000000200000100000008000000000000000000000000001d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d0290010000001400000000000000000008000800000000000140080000000400002000008008408000000808800000000000100008000000000800000000020020000800800000800000000000801020800000800800020020000000040000000000000900000000000060000000000800800000000800800020000000000000400000000000200000000000058100800000002000000000800058801000000000000000000000000000000000001400000000000008000001000000200000000000008009d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000400000000000010000200000000400000000000010000000000000400000000000012000000000000410000000000000000000000000480000000008213000308000200480000200000000018000200c08000000000000600600018000000000210000000180000000200000488210000000000000c000000004800000000100000000000000004800000000000000000000000004000000000002130001000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000010000000000010000000000000000000000000000000000000000000000018018000000000000000000000000001000005d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003e0c0000000000000000000000000001000004000001800000000100000000000004000000c00c000800000800000000000000000000000000028000000800000000000000000000000000000000009000000008000000000000000000110000004000041100000000101100004000000040000000000000010000000000120002004100000010000000000000408200200000004000c003000004002001000000000000000000000400000000000000000000dd6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000800000000000000000000000000000000100000000004000000000000000000000000000000000000000000000000000000000000000000000000000000080080000000000000000104840004900004000000004000002002000008000200000000000000000080000000000088002000000000000004000000104000000000000000000000000040000000000000000000000000000000000000008000000000000000000000004040001000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000004000000000004000000000000000000000000000000000000000000000003d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000020000000000000000000000010000000204000020000008000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000a4c9000000000040000000000000000080000000000000000000000000000000000000000000000020000060080000000000020000000000000200000008001002000040080000080000000000040000080000000080001002000000000040000100000004000000004000000100000040000000000100100044000000001080000041000000000000000000000104084000000000000004480000084200400000bd6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000100000000200000a00000000000008400000000000210000000000000000000000000800000000000020000000000000800000000000024000000000000800000000008010200100400000900000000008404002040000000400400400040050000000000010500000040000000401000000000000000000000800000020000410000010810000000000000000a00400000004000400000000000000400000000000000010000000020410000800000000400000000000a00000000008050001040000000000000000000000400000000000100400800000008000000000000002000000000000000000000000000000000000000000004002002007d6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00800000000000000000000000000000200200000000000000000000000000000b000000000000200000000000000000010003300000000200000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000cc910010000000400000000000000000008000800000200200004000000000400100000008008408000000008000000000000000008100000000000000000000000000000000000800000000000400020000000000000010000000000000000002200000900000000200020008000400100900000000000004000000000020400200c0000100020004000000000800fd6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000020400000c000008000000200000000082600600000000000000000000080000000000000100000000000908010000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040003000006000000101006200000002000040100001020000000000004040000000180001043003000000000180000000000006080000104000004004000001080000000108000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000020000001000000080000000000002100000000000080000000000002200000000000000000000000000000000036040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4800000000000000000010000000000000000000000000000000000000000000080000000000000000000000000000809040a000000005000280000000000000000000000000000a0800400000080004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001e69000000000000000000000002000000000000000020020002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000022000000820000000000000020022000800030000000000000c00000000000000836040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (008240200800101501010001040004000000000000000200000000000500da40004200b4804000000000000000001000001800000000000040100000000000201000010802800000000000014020000000000500800000820014000000000000540030000000014000000000040001801000010015000100010d4004000420000021c0261000000000008100021800a10245002300028000080000000000000000000080000082000200000000080229028080000000000000001000400000008000000000000200000000000002000000002002000080000000001000000000010300000000429004800000000000000000040020000000001000010080080000436040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000040000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000020000000400400100000000000000000001000000000008000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b6630000000000000000080000020000000000800000000000004001000000000100000000000000000000000000000000000000000100000000000000000000000000000000208c0000000000080005000100000000000000000000000000000008000018000800000000c36040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000008000408288100241400000010401000000000010020010000088000004000000008000000000000001000000002209c00000000000100028008000208440000000100280000000004200000400000004000000040000000004400000000040040000000010000004000012000000000000002000004001000000000000000800000000020000000000002000000000000001000442800004002020100000000000040000100000020000000000000000000000000008000080000000804002004148008400010000000000000000004000000000000000000000000008000000004000000000000000000000000000000800500200000200236040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010004900001610400324400208000000000000000000000008000000000000000901000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000031000000002000008000000000000004000000000000000001000000000000088000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e092000000000000000000000000000100000100202400000000108000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000a36040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000020800000000000000000000000000000000000006802001001000ca80000000008068600000000010000000020b000000040000000000d20800024000904100000000000000002160014905850400000001000000000060000201004908001000000000000004000000000000100001800000806100000000000124800000400000020000000000100800200000000000000b20000000000000001104181000001000104800000800005806000c0000000000000200000410000020000008200000000000040000480000000006000000000250000000000000400000000040420180000000000000000000110020000000000000400636040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000400000000040000000000000020000000800800400001008000008000000000000000000000000000000000000001000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000090000000000000040000000400010000000000000000000000000000000000000210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa09000000000000000000000000000000000008401008200010020000000000000000000000000000100000000000000000000000000000008200000000000000000000000000e36040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000001040000000000000000000000000000000000000000000000000000000000000000000000000000004800005100c30130c0800100800080000800000005040000401000000448000001200000000000020000000008100080000000000104040042248002288000000006044000080000022010000000004400000000000000000020000000000000820008000000000100000000000000000000000000100000000400010000000000000000000000200000200000410002004000000200040108c00a040400000000000000300000000000000000020800000400000008000010000000000002000060400200008000010000000000000000000000136040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (104000000000000000000000000090100000000000000000000000000000000000000040000000000800000000920108100880008000000000000000000000020000000000000820000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080100040000800000001000000200248000010000010000000400400000000000400000000000000000000000000000000000000000000200000000000000000000020000000000000000000000000000000000000b3620000000000000000080000000000000000100098a0200010008040000000000100000000000000100000000000000000000000936040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (120000080000000000000000000000000000000000000000000000000000000000000000082800000000000000020000000000000000000010010000000000000040204084410010002004090000000c0000040000040000800020104000000000000000020000040000214c00004001000000801000000008409000400000000810000000000001090000008100000000001000800000010000020001001000000c00000000000820000020000800800000000000008000000080000808000080100000001000000010810000020000008040a0804004410000300100010000104000000000008000020000002000010000000042000000010000204000000000536040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000004000000010000920000000000100000800920000000000000000000000000000000000000000000000000000100000000000000000000000404801000000020004100100000000000100800100000020020000000000601800000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000001008000000000000000000000010000000004000000000001048100000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000e15d0000000000000000000000000001000000000400002000a0050000000000000000d36040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000a1000100400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000010010000000800000000900aa181001003012000000000000082000000000000000020000000000000000000000025800020120000820000000000400000100000000020000000000080000000000000000000000000000000000000000820000000000000000000000000000000000400000c10000000000000000000004001040004000000120100020000000040000010020920010000004000100104041d809a5004000000000020000c0000003000000000001000336040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000080000000000000002080000000000000000108000000000000800080000000200021214200000000000002000000001a0000000000000000000000000001000000000000000200000000000488000000004008000000000000000010000000000000400000c000000100000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000020000000000000800000000040000000000008000300208000000000010100000000000000000000000000000000000000000000200000000000000000000040000000000000000000000002000000000000f858000000000000000000000000000000b36040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000fdd200000000000000000000000000000000000004000042004000000008000000011200001000000000000000000000000000000000000000000000000000000000000000000000000000000000000401000000000000000000000000000004000000014108400000000400200000000010108000000000000000000000000000000000000004000000c02000331000000080000004080000201001840000000000000000000200002049030000008000000000000100082000000004000000000000101000000000004000000000000100000000000006000000000800100020000000018000000000000109004000008006002000000300301000000400736040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000000000008500202001021201012000007208800000005a003002000000000000000000002003800000080000000000020000000020000000000004000000000006101000000000081000010000000080000000004000000000004000000000002000020080000000000012000000000000020006000002000000008000000008000000000000002000000000000000000000000000000000000080000000000020000000000000000000000000000000000000000001000000000000000000000000000000000000020000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000f36040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000202900002000000000000000000000001001002000000800000012090000010000000000000000000000000010000000000000800000000000004000000100000000000040000008000000000000000000000000010000000000000000080000010000008000801001000008000000008200018000008000008000200000b04006000218980a0000020e0000008800000002020000000060002044000000040040000040002002000000402000000000000000000000000000000010001c00800000000020000000000000000800000000060010000061800001800000000310100000228000008000000000000b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400000000000310000440600005000000400c00000000000000008000000008000000000200000800400008010010010400000000010008000000000000000000000284000000001408000000000000100000080000000000000000000000080200000a0000000000000400000000000020000000001000800400000000402000000000000800080000000000022800100000000500000000000000040000000000000000000000000000000000001000000010000000200000000000000000000000000000000020000000088600000210080020000000000000001000800000000000000000000000000000000000000000000000000000000000000000000008b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000001000000000000000000001000000000000000000000000000000000000b39a000000000000000000000000000010830080008000c20800c0000800080000000000002400000000000000002003000000000080004080030802000c000000000000000000200000008000000000000000000000020020820001000000000800000160000000000000000000000000004000000000000000000000000000000000000000410000000000000810020800040000000004100004845040000000000002100000000080000000000800000020000000000000000000000000001000000800000000008000000000000000100000000000000000004b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0820004000000010001000400000000000000021000000400000000000080031040022006041220001024000022025030805444020000004080088100000000100080080000000000081001000001200000000042020020808004820800080000001002002484000000000000000000002010000004000000004000044000000000000000820000810080088000000040408000000000000090080008000000400002200000020000000080000000000000000000040000000000000000000000000000000000000000000000000000000200000000000000804000000008000000000008001000800000000000040080000000000000000000000000000100000cb6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00020000000000000000020000000020100000000000000000000008000000400010000000018000000000000000000000000000000000005ab000000000048000000000000000000000008001001080001030029000008000020000410100000000000008000002000002000000000000030800000c00000000000000000080000002000000000000000000008000000000000000000000210440000000800000020000024000c2000490003000000000000800000030400000020000020000092020020800820c30880000000220020c80404a2920040040000444a02002000100022000101000200040000000000080000082000200000482080482080000002b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0200000000108000000000000004000000100040118010000000000000000000080100000020800000c02100000006024000020000004c248240008001008200008000048600000020040200240041200004421a0066048085100022802900101100000002008080080012004100000028000000208200430004044100100040000800002009002000001010004008000000000009000800004048000010080002000000080000001041000000011040000000000401000000000020100020000000000000000110020000000000000000000000000000000000080080000000000000201001400000000000000000000000000000000000000002000000000000ab6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000240000800000020000000000000000000020000000000000000000000000000000000000000400010000000010000000000000000000000000000000000002c15000000000000000000000000040000000010000010010008410610000400000200004120000000000000000010010000000000400000400000010000000000000000000000100000000000000000000000000000010010420000000080005000a00000000001000002100000000104140000000180000000104000000000000000000000000000000000008200000084000008042000000000000080000000000001000000100000840000080000000000000000006b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000100000000000000100080000010000c200800000820300810000820800c2080000082000800000001000c000400000080000000000000008000000000000000000800020a00004408002030000000912028d44401000000245008051400000000800082000240001000000000000000e00000000024081000902000800808008000000200a02000000040a0010004000000000000900000100100000001800000000000000202000485b300000080082001000080000000001000020001000000000000800000000002000000000000000000000000010000000000000000000000000000000000000080080000000000000001000800002000200010000eb6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000003000000103000400000001000200030800000c00000000010200020000001000300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b56900000000030000000000000008000000000004001000000000001000000000000000000000000000000000000000000000000000000000000000000001000000000060000000000000000002000300000000040000000000000000000000204444008100104900820100070100c2010080403000800001000000200000000000000000000200010024028a0a820924000000040000004400000a0400000000001000001b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000800000041000000000000000000000000000000000000100000000020000000000000000400800000000000800000010000020000000000000000020000000020001000000050920000000884000402000000820050030000100014b0414c0810201080a000a04200485208041412012800090862040840030423a01011020000428c10c10008804c00001400080000000080040010000012040000000000400000000000000410000000000000000a0008008000800000c000400200000400008010000000010000000090000410010400000010000000020200000200300000000000000000200300000000000000000000000020000100100009b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000001201200000200000000042800200000040008000000800000800100000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bca700001000000000000000000000000020800010000020020000000000000000000000000000000000000000000000000000000000008000010000000401000000000040000000000000000000800000000000040000000000000200044002830010000c004100000000000404000004040100000000000000000000002000280000004004800000001001040820041008005b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000008000000002000000000000000000000000000000000901000000000040004000000000400a00000000000000000000000000000000000000000000000001000048008000000040091000000001002000414000040000000000000000000000000200000000001000000000000008000001000240200000542840800000000000000000000000000000000000000000000000000000800000010080001000200000060000000000000000400000000010000000000000000000000000000000000000000000000000000000000200001000008000000000200000000014000000000000500001000000008000000000000000000000000000000000000000db6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000400400000028000000000000000000000000008400080400000000020004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ac9000000000000000000000000000010000000000000580180000000000000000000000000000000000000000000000000000000000000400100000000000000000000000000000000000000000000030000000000000000000000000000000004000000a00c000004000401400000120041000000000000000c0004000000003b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01200500000008000000000000000a0000000000010010000000000000000000000000000000000000002002094000000008002d000000008000b40000000000000000000000000000000000000a21000000000005b4040000000000002840000000001000000000000000000000000000000000800400000000000c000000200000000000000002004000000100060000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000000008000000000000000000000010000000000000000000000000002000000000100000000000000000a0000000000000200000000040008000000002800200014000bb6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040040002800000800000000000060004000010040008000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000557600000000000000000000000000001102894000000004022d000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000002801000100040000000000007b6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000002002000000100000040002800601202800084280000000010010000000008000028040000800000004000000000000000000000000000000000000000000240800000000010011000000000000000000000000028840000000140000000004005000000580040140021080881000000000002000000200000000000000000000000000000000200000001000000000040200000001a00000000400000004000000000000000000000000000000000000000000000000000002000000000020000200000100000000000000000000000000000000000000000000000000080000000000000000002000000a0000000400002800500000002800002800fb6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080010800000000000200020000800000800200004040020008000101000000200000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000300500000000008000000100200010080000120000000200020002020004000040200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003a6a00000000000000000000000000000000400000000000080000000000000000000000000000000000000000000000000000000000000020004000100800000000000000000000000000000000000000000500000000000000000000076040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000100000000000000000000000000000100a00492104000000009084100a0000213223000000000800000000011000041000010040000800100000000000000000000000000000a00404084084008032102102102102084084084000000000000000200800040008008080001000400200900020050008000008024400000000940408008000000800200400800040008800000000040000100800080048000020000000000809000104808800400000020000000000000000000000000000000000000000002000200004020000401020044010000000000000000101000020008000000000000001000000000040000000000000000400800876040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000200000000000000000008880800008000000000002000000000004000000000040400000000001010000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000001004000000000000040001002004100000000000000800000000020000000000802000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047a10000000000000000000000000000040240408408420104214210a100000000000080000000000000000000000000000000000000000000008000001000000000000000000000000000476040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000020100000000000000000000000000000000000000000010000000000000000000000000000100184010222000400008408000020000010040800000000400400000010000041008000040002000000000000000000000000000000002501984080084040006102102100000284084084000000000000000200048040000008080001000000200148008040008001280000000000001040008010000000000000400000000010000000000000000000100000020008000001000000808280108010000000000000000000000000000000000000000000000000000000000600000000002000000028000000000000000000000000000000000000000000c76040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000002000000000000000000000000000000000000000000000000200000000400000000000001000000000010000020000004000000800000080000020000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000004010000000000000200000000000010000004000000080000000200000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a4860000000000000000000000000000000018408008422900214211a100000100004080000000000000000000000000000000000000000000276040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000010000801800000002000000000000000012000000000000000000000004000040000000020000800200000000000000000000000000000000000000000000020000000000000400000000000000000000000400000020000000000000800000000000000000000000000000000002800020000000003000800000000800000000000000000000000000000000000000003002800000009000008000000000000020000000000000000000000000000000000000000000000000008000000400800004080000a76040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000002000080040000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000400000000000000000000004000000000000200000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000400402000000000000000000400000000000000002000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000264000000000000000000000000000002000000000000400800040004000000000000000000000676040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (30030102000040c00c00000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004400c0000000001002000000000080082000000000000000000000000040000000000000000000000000000000000000000000000000400030030000010000c00c00100000030030000000000000000100000080014000000c02000000800800000030000020000010400000000480000000000000000200000000040000000000000000000000800004008010080500000002009080020020000100000080000000000000000000000000000000000000e76040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000000000000000000000000000000000000000003000000010020000000200000020000000000000000000000000000000000000000000000000010000000000000000000400808000010000000001000008020010800200800200000000020008000000001000200008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300100013013010002000000000000100000080400000200008000008004000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005dd300000000000000000000000000000400000000176040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000c009000800840a00344021021000000000040800000000000000000000000000000000000000000200100000020000000000000000000000000000000000000008000000000000000000000000000000004000000320340000200808904008012000504240000000040000004001000000000000c000000000400000000000000000000000000000000100080084090040002102100c008000840840000000000000000008000000100000000000005030028000200900000c00090484000008000002000000000000000000000000000000000000000000000000000100000000200000004408011000408c8800400000000976040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000080000210003282400008400000010000000000000000000000000000000000000000000000000000010000000002282000008000000000000000000002000008000000000000000002080000000000000000000000000002000000400000080000210100000000000000040000000000001000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000000000000000002800000000000000800000100002800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000898000576040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000069050000000000000000000000000000000521909452004014864251480000521900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000010000000000000000000000000000c18282000000430600080000010c1828200000043060000000000000000002000000400000080000010000000000000000000000000000000521909452000014864251480000521909452000000000000000000002000000400000080000010000282000000430600080000010c180020000004000000800002000000020000000000000100000000020820000080000d76040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002a0011c0000000000000000500059000000000005aba9a0ec72a33e411dc1c000000000000000000000000000000000000000000000000001c3fc000000000000027884800000000000000000000000000c0000000000000000000005680000000000000000000000000000160518300000002131000000000000000a8880000000002a220000000000a8880000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c00000000003f700000000000010c0100200000000000004557300001d88000000000000000000000000000000000000000000000000000000000000000000000000000000376040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000c40000000000000893800000000000000000000000000000004c0ddd36440001383774d9100004e0dc00000000000000000000000000000000000000000000020200000000000000000000000000000000000000000000000442100000000000000000000000000055550122010041555400000440055552888a0208155540000000000004060000100220000000001088800000000000000000000000000000004c4ddd36440001383774d9100004e0ddd364400000000000000000000000008000000000000200000180000008155540000000205555000007711c000000005a80000000000b76040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0206a6a000007711c000000005a400000000001dd0011c000000000000000040002a000000000005a7cdafef76a326811dc1c000000000000000000000000000000000000000000000000001fd740000000000000272a01100000000000000000000000002a00000000000000000000568000000000000000000000000000012250030000000213100000004000000028000000000000a000000000000280000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000300000000000010c0122000000000000000c42100003880000000000000000000000000000000000000000000776040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000008510000000000000025610000000400000000000000000000000480e3dc63800012738f718e0000498e20000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000044210000000000000000000000000006a6a0100000001a9a80000044426a6a1014055015a9a800000000000040600001002200000000035ca80000000000000000000000000000000484e3dc63800012638f718e0000498e3dc638000000000000000000000010080000000000402000001004010081a9a800000400f76040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000008028000000450200a001a80000080286a6a00000423b000000000418000000000012a00000000000000000000500010100000000000418ae000023371763b0000000002020000000000000000000000000000000000000000000000000002020000005789825000000000000000000000000104000000000000000000004c00000000000000000000000000000000120000000001101000550000000000000000000400000000000010000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00f0000010000000000000000000001000000000000000001842e000050808000000f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01004000000000000000adab000002814000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080040000000000006b61000000002000000000000000000000064318031c8004198c200c7200006630800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000842a000000000000000000000000000006a3101000021a9a80000000086a6a22c1a202a1a9a800000000000000000000082100000000008402000000010008200000000000000000064318031c8000198c200c72000066308031c80000000000200000000000200a00008f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (b220c1900000000000200000000000204240000000008109000000054204270154000008109555500000427b4000000004140100000000145024000000000020000004c0112202400000000414d700006f3702ab94000000000420000000000000000000000000000000000000000000000000000420000006701821004000000000000000000000002004000000000000000004c01000000000000000000000000000002424000000001121110100000000000000000000020000000000000800000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000ceff00000008000000000004000000004f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000080000000000000800000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000002000000000000000000000000000000000000000001d350000000000000000000000000000000603320c1900c4186c883064000061b2200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000852b000000000000000000000000000c055310100000555540000000015555010544153d5554000000000000000000000821000000000194090000000100080400000000000000000603320c190000186c88306400006100cf6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000800000800000000000000000000000000000000000800000004000000100000000000000000000000000000000000000800000000404c000140000001130001000000000000000000000000000200000880040040000001100000040000045101000000001140000020000044124020000001180000000000044000030000000000800000000044000800000001100000000000000000000800000001000000000000000000000000080000000000058002000000000000040000000000000000000000000000000000000080000000000000000000000000580000000000014000000000000580000000000000002f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000040000000000000000000000018040000000000000000000000000000000000000000000000000000000000000000000000000000000044000000000000000000000000000000000000001000000000000000000000000000000000000000000e33d0000000000000000000000000000000000000000000000140000000202205000000000000160000000000000000000800000000000000000020000000000000000000000020020800000000000000000000020020000000800000000000000000020000000000000000000000020000000000000000000000000008000000000008000000000000000000000000000000000000000af6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000006006000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000080000000200400008000000600030000003024480000800000000600002000010018000000020852600848000200480000000008212000000000000488000400000000000000000000000000480008000010c0000020000000000000060000000400000000000001000000000000000000048000000000000000000000000040000410000000000000000000000000000000000000000000000000400000000000000000000000000400000006f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000005f140000000000000000000000000000000000000000000000000000000180000000000000000100002000000000000000000000000000000000000000000c00000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000018600400000000ef6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000010000000100008000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000008000000080002002000000000000000000000000000000000000000000000040000001020000000030000800002200000020000000000000000000020020020000830000030820080000800800001040020000020000001020000000000000000000000000000000002000000000000080000000800000000000000400000000000000000000001000000000000000000000000000000000000000000208000000000080000000000000000000000000000000000001f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000020001000000000000000000000000800020000000008000800000000800000000000008000000000000a10100000000400000000000000a001230000004004000000000000000000000000000000000000000000000000080000000000000018100000000000000000000000000000000000000200000000000000000000000000000000000000000cbc000000000000000000000000000000000000000000000000000000000020000000000000000000020000000000000008000000000000000000200000000000000000000000200100000000000000000000000100200000008000000000000000000400000000000000000000000000000009f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000002200220000000000000200008000000000000080000000800801000000040000000000800000000000000000000000000000000000000000000000000000000000008400000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000040000000011008000400024010000000004000005000010000004000404000000100100100000430104010400000004410200000004100008200000004450000000000004000000000000000100000000004000004000000000000000000000000000000000102000000000000000000000004040200000000010004000000008000800000000000005f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000040000000000008000000000000000000000000000800000000000000000000000000000000000000000000000000000080000000000002000000000010080000000000100000000000000000008840000100400000000000000000000000000000000000000000000000000200000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000008f650000000000000010000000000000000000000010000040000000000200200000000000000020000000000000000000000000000000000000000000000008028000000000000000800000000000000000000000000000000000000000000000df6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000020020000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400000000400010000000400000001800400000401800400800044000010000013011001010000c00400000000000010001040000000400000000000014000000000000400000000000001000000000000400000000000010000000000000040000000000000000c000000000080000003f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000000000080102000000000081180000000a0010400000000000000000000000000200000000000000000000000140002000000000400080000000a00000000824028420800004110b5201400000000000000000000015000a00000000008000000000000000000000000000000000000000000000080000000000000000000200000000000000000000020000000000000000000000000000000000000000000000000000000000daa40000000000000010000000000000000000000010000040020000000000000800000000000020000000000000000000000000000000000000000000000008008000000000000000000000000000bf6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000002200000000000000000000000000000000000000000000000000000000000000000000000000040000200000000000001000000000000000001000000010010010000000400000000010000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000400000021240b40a40000400080000000000000010001800000000002000080000002000000124000000000000200000082020020080000000200000408400000800000080000004000a0000200000000000000008004000080000000400000000000000007f6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000080000080000000000000000000000000000000000000000000000000000001180000002000000000000800404400000000000000000000000000000000000000000000000000800000000000020000000000000000000100000080000000000000006000880100000000000000000000000801000000000008000000000000000000001000000000000000000a0000000000000000000000000004400000000000000000000000000000000000000000000000000000000000000000000000000000b889000000000000000000000000000000000000200000008010000000020800a0000000020802d0208000000000000000000000000000000000000000ff6040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000080000000000000000002000000002000000000002000000000000000000000000000000000000000000000000400000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000010500000000000040000040452080000000000000008000000000000a00000888a40000100010800304000020132080081108000000000020000040000200400400420100000000000000e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000020000040c02000004040000000000000000000200000020100822040000000000800000000000000000000000000002100008100010000004800000000004082000000000000000000800000000000000000000000000000000000000000000000000000008000808800000c20000000000020800800821000000000000000000000800300000000000000000000000000000000000000000000280000000200000600000000000000000809aa10000000000080000000000000000000000200078000000000000000000000000000000000000858a000000000000000000000000000000000000000001400000100000000004000000000080000000080080e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (722818000000104000000000049000000008400000000000000000000000000000000000000000000000000000000000008000600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000080018000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000218400400400010004008000200010000000c120000040000000000000400000080200ca0000011010034444000201008050011122a200068120001e120040e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (14a00004800010000402003000220a00000400000000000010002008022000000000000000000004000000000800000801000000000000000000000000000000000000000088505000000400040400080000012000800000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000108000004000000000000000000008000000000000002000000000000000000000000000000000800000020000000000000000000000404000804000000000000000020000000000000000200000000000000000000000000000000000000000101000000000000000000000000000000820000000000a4700c0e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000820000020002000080000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000400000800000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000200000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000400000000282020000200000000000000100004000000000008400000820040210100110482000100020e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000040000000000480202802480200084800108052501100090008008000000014008012100040104200400400448080000000000000000000000208008408410000004000200000480000000000010000000000001420000008000024500000004404000000000000000000000800000000000000000000000000008000800000002200000004000008004400100003080100082000100014c08000800000000000000000000c00020000080000000000000000000000000040000000000080000002080003080000000000008000000000000000000002000000000000000000000010000000000000000000000000000000000000000063f80000000000a0e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000176700000000000000000000000000000000000000000429210010000280430440000000000001200000000020000000000000000000000000000000080000000800000000000800004000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800004c80010000100000000000088000020480000200000000060e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000002010002000800000000000000000000000100012121000000046001900400000010042000004082000102001000401040002005000000000000000000000000000003080000000010000020100001000000000000000000000000000000004000220200000100040000000400080080100000000000000000000000000000000000000000020000000000900000000000000000100000014000000000000000000004000000100000000000000000000000004100000000000000000000000000000000000000000000000000000000000000000000000008040004900000000000000000000000000000000000000000000000000000000e0e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000004000000000000000000000000000000000000000770f00000000000000000000000000000000000000000400004000000241000000000000008000001048000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000012082000480000010e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000130002000008004000000002800218000040000000000000000020000020001000281c00000088000160108000008001cc000000a00010030100000000180010000004012004000000000000000004000006000000000008080000000000000008800000000000200000000000010000000080000a004000080000028000000000000000000000000000000000000000000000000000100090000400000000800010000203020000000008000000020400301010000000000000000000000101000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000090e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000a65700000000000000000000000000000000000000003080001000000000000020000000008000c00008000040000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000050e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000200000000000000000000000000000000000004004000002000000104000004008000100000000000080200020100004000000000020080000002004002404001080020180800000000000000010000004000b0004000018040000e4080003e210018400000040400000000000018000000000000000010000100000000000000000000490000001000000100000100001040000040000000000000000080000001000000000000000000000000000000000000000000200400c00000000000000000000000008000000000000800000000000000000060000020000020800000000000000000860000009800000001000000000000210000000008000d0e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000020000000000000000000000000000000000080000000000000000000000000000000000000002000000000000000000000000000800000000000008e7b00000000000000000100000000000000000000000000000004000000000000000000000000000000000000002000200000000008000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000400000000000000000000000000000000000000000000000000000000000040040000000000000001001041000000048000000014104040a1000010000000100000000000080000000a0008224002400001050008000000208041400800080000400000000830000408000800100408008480000000000400000208000000000000402000000011000400000000000490060020080000000000000800000000000000000000000000000000000000020000000000000000000000000000200000000000001000000000800800000208230400000420000000800010800000000000000000200800048400000000000000000800000000b0e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400004400000000000000000040100000000000000000004040000000000000000000000000000000000008000000000000000008000000000000000000000100000000000000000000000000000000000000000d44e00000000000080000000000004000002000000000040041001040000080000000000001040000448000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000001000000000000000000000000080000000070e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000004000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000040002000000800800800080090000082030902286030010000084082020802001032085000030001030c8004004200102204082008102083010004000014000000000100004200408011000a0020480000000000200000860000000000000804000040010400840000000020000100000040108040000100001000000004000000000000000000080000000000000000000000000000000000000000000000000000000000001000400000000040000000041041000000001000000000000000000f0e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000004000000000002000000000000000000000400000010000000002000000000000000080000000000020002004000000000000000000000000000000000000000040040010000000000000000000000000000000000000000000000000040000000000000f2d700000000000000000000000000000000000000001022021000820000008000000000000c20000130000008000000000000000000000000000000000000000000000000000000004400000000000000000000000000204000000000000000000000000001004000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000400008e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000004000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000080080000000000000088000000480040481000401010401000812480010003400002000000000000024802080102002802800020009442000004000010020000a082000100000000200001200000008040040000008000000002000000880000000020000000000000800000002001000800000000000208000000049000000000000000010000100000000000000000000000000000001060000000000040400000000000800000020820060088e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000400000800000020810400000000000000124100ca10100000000000000000040000c400000000000000000024400200000000000000000000002000000000000000000000000002000000000000000040040000000000000000000000000000000000000000000000000000000000000000000f80c00000000000040000100000004000001000000000800801000000000090040000000000000100000000010000000000000000000000000000000000000000000000000001000010000000000000000000000000001010000000000000000000000000000840000000000000000000000000000000000000000000000010010000000000000410048e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000002004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080080ec200200000020080000220020000400124800028020020008400100800110a0020132000416404005000110000090b200020806000020a48000000003008002000010040e012100012000200080000400c00180000000000000000400000000000100000000000000100000000100000000000044000000004000020000000000100000000000001000000000000000000020008400000000c8e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000a00000000000000000002000301083000000010000080a00200a2841020820000201040000500800008a00214000300000000000000800000030000000002000008000200000000000000000001000004301200000000040000002d008000000000000000000080000000000000000000000000000000000000000000000000000000000000000003ded00000000000000000000000000000000000000000000000040000000000000000200000483000000000000000000400000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000010000000000000000000000000040000028e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000000000000000000000400000000000000000000200200000000000008200000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000008000000000000000000000000001281000041420002000000050020401040080040000000001430410001400050420020041000c010a3010434041020000440010c010481340500c100029001080400100201c100040c80000000800000008000000000000000000100000000000000020c0000000000000a00088002020a000000000002800300c01008a0010000000000000000000000a8e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000009100000014000000000000000000000000000000000000000000000000000800000000000000000010000000010000000000000000a0000000020080000000000000000200000020000000000000000000000000000000000000000000000000000000000000000000000002800200000000000000000000000000000000000000000000000000000000000000000000000000000000000ba3e03000000000000000000000000000000000000000000001030000000000080000400000020100000000000001000000000000000000000000000000000000000000000002000000000000000000000000000000002000000000000000000000000000068e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000140000000000000402000000000000000000000000000000102a00040a020080020121004100001200900000a8000400081028000000100400000280000000000000000000000200000004010030000000100200000000000000000000000000000004000000000000200200000e8e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000900894000000094082d00000000002800000000000000000000000000000004000000000000000000000000000200000000000000000200000000028220000000000000028000000800200000000000000004010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000009eaa00000000000000000000000000000000000000001001000000040000000000000002800200000800000000000000000000000000000000000000000000000000000000000000000000080000000000000018e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800020004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040014002800010000000000000000102000040100000000000010000000000000002000001008000102000400004040000000000840108040020000000000000000000000000000000100000000000000000000000000001000000000000000000000000000098e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000200000000000000000000000000000000000001002000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000140000000000000028140000140000000000000a00000168000148140000000000000028000000400100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000006cc500000000000000000000000000000000000000000900400090004000010000000000000000000000000000000000000000000000000000000000000000000058e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000014000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400028000a28040000000000000000000000004000000000000000000000000000000042000000000200100000000800000000020000040002008044800002000040a00180400005004000000000000000000000d8e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4000050020001100a000000000000000400080002000000002000040800000000000000000000000000000011012040840840500921021021204000000408900000000000000010000000000200000000000000000000100004000800000000000004000800000802080040000008002200a00008a048000000000000002001000050030000000000000000000000000000000000000000000000000000000000000000000000800000008020000000000000000000000000000000000000000800000000000000000000000000000000000a06e00000000000000000000000000000000000000002000200020020000000000002800000200004000000000000038e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8020008000200802000000008840200000000000000000000000000000000000000000000000000000000000000004040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000280520022202080000000080840000000022020040000000800080000000000000008040440108400920280000050000082300000204020802010002410002000000b8e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08000000000000080001000000a20000000000000600100001008000000000000000000000000000000002000000000000000000000000000000000000001001840800840880521021021200001880440840000000000000008000000000000000000000000000000100000000800000000000000000800000800000000000008008200a0000880080000000000000020010000000280000000000000000000000000000000000000000000000000000000000000000000020002000080600000000000000000000000000000000000000000000000000000000000000000000000000003fff00000000000000000000000000000000000000000400100090000078e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000601a00000014000000000200002000200010000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400022802000000000000880002020024020000000000000000000000000000000000500000400000002000088400f8e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000002010080000000000101000000000040101000000000000000008000400100200000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000002000000000000000000001000000000000000000000080000000000080000200000000000000000000000000000000000000000000010004000000000000000000000000000000000000000000000000000000000000000000000000100008000000000000000000000000000000000000000000000000000000000000000000000000000000cc5900000000000000000004e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000fa500000000000000000000000000000000000000000000200000000004000800000000000000000204020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008220000400400000000000008000000000000004000000000000000000084e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0030000000000800808000000020000000000000000001000400800800410000000400000010240000000280000000000000000200000000000000001000000000000000000000008000000000000200000080000000000000000000000000000000000200030030000000000c00c0011008002102000000000000000000000000000000000000000000000001000000000000000000000000000000000000800200000000000000000000000000000000000000002000004000000000000000000000000000000000000000000000000000000000000000000000000000400008000000000000000000000000000000000000000000000000000000000000000044e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000002000000000000000000000000000140000000004fad00000000000000000000000000000000000000000000000000000040000000400000000200000040400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080800001001000000000000c4e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000202108100010100000000100800000000023c24100000000000000000000000000010082000130004010000200000000000000008002408c0000810200000200010020008048001000a00000000000000000000000000000800000000040000000000000000000000000000001000900080084000008002102100401008084080000000000000000000000008000000000000000000000000000400000000000000000410000000010208004000000000000000000000400000000000000000000000500c0000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000024e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002800000000000000000000000000000000000000020000000000000000000000000000000000000000000873a00000000000000000000000000000000000000001000000040000020008000100800000000010820400000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a4e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000181002400000432600000000000c18002000008430000000000000000000000000000000092000210082280400000000000092000210082280000000000000010000000081000400000000000000000000000000400000000000010000000000000000000000000000000000002521909452000014864251480000523900000400000000000000000080000000000000000000000000000020000004000000000000000002800000000000000000000000002820000004000000000000000002820000004000000000000000000000000000000000000000000000000000000000000000000000064e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000001d942000000000000000000000000000000000000620000000000000000000000000000000000000000005bc100000000000000000000000000000000000000000000000000000000010000000000000000800000100000000000000000000000000000000000000000000000000000000002800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000e4e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000005af00000d754faba8000000000eaea00000118000000000000000000000000000010040005000042690014a6e000008c0000500273100335ceb400000e8b00000000000055000000000000000000000003a000000000003087400000000000000000000000000000000000000004c0ddd36440001383774d91f4004e0dd605180000000000000000029000000000000000000000000000000005309400000000000000b0b188c2000002c2c0000000000b03188c25309400000000000000000188c262000000000000000000000000000000000000014e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a000000000000000000000000000000000000000000000000000000000000000000000000003884e00000000000000000000000000000000000062000000000000000000000000003400000000000000a4090000000000000000000000000000000000000000004c0010000000ffff0000000000007c0000044210000000000000000000000000000000000000000000000000000000000188420000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007b80000000000000000094e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000018800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000272700400d7d4c545401000000015150000011000000000000000000000000000000000000a000000960015d90000038c0000a07db3100332349400003ebb0000000000545500400000000000000000000fa00000000000338740000000000000000000000000000000000000000480e3dc63800012638f718ef400498e3225000000000000000000029000000000000000000000000000000005309400000000000000b0b188c2000002c2c0000000000b03188c25309400000000000000000188c260054e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00021c5aa19a80000000000000000021c5b022100000000000000000000000000000000000000000000000000000000000000000000000050c520000000000000000000000000000000000000200000000000000000000000001450008000000000031550000000000000000000000000000000000000000000c001000000014150000000002ac0000000442100000000000000000000000000000000000000000000000000000000001884200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d4e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000272700000752f00054000000000151500000210205454000000000000000000000000000005010200f4006c19000000000000505183ac1963b3a800000000000000000096ec00000100000000000000000000000000000000000000000200000000000000000000000000000000064318031c8000198c200c7200006630800120000000000000000003380000000000000000000000000000000211a80000000000000000021c5a80800000000002020000034e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000002185e10800000000000420000002185e31dac000000000000000002185e022340000000000000000000000000000000000000000000000000000000000000000000000002af600000000000000000000000000000000000002050000000000000000000000000000800000000000262700000000000000000000000000000000000000000020000002020000000000010000000000002862a000000000000000000000000000000000000000000000000000000000000c5200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b4e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007081400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005af0000065eb703a8000000000eaea0000021047aba800000000000000000000000000000a000201f4005d27a00800000000a00a633cd6944998000000000000000200692c000000080000000000000000000000000080000000000002000000000000000000000000000000000603320c190000186c883064000061b2212424000000000000000003380000000000000000000000000000000215ac000000074e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000008000000000002000000000000000000000000000000000000000000000000000001400000000000000000000000000000000400000000000000000000000000000000050001000000001400000000000058000000000001600000000000000000000000001410004100000000000000000000000000000000000c07f00000000000000000000000000000000000000000400000000020000000000000800000000000c52b00000000000000000000000000000000000000000000000000000000000085600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f4e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000088000010000000000000800000000000800000000000160002000000000000000000000000000000000000200000000010000000000000000000000000000000000000000000000000000100000000000000000020000000000942004104204005001100000000000000000004020000100004004110004004100100104020000004000000100000104500000000000004080080000014500100000080110000004002014400082000000114000000000004400000000000000000000000004400008000000118000000000014400000000000140000000000005800000000000140000040000000800000000000000000000000004e0000000ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00040820000000000000000000000040000000000000000000000000000400000004000004000000000000000000004000000100000000000000000008000000200000000000000000c00000000000002000000000000000000000000000000000000010000000100000000000000400000000000010000000000000000000001000000000000000000000000000000000000000000000000079000000580000000000000000000000000500000000100014000000000000000000000000000000000000000080000000000002000080000000080000000000000000000000800000000000000080000000000000080000000000002100000000000000000000008ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40000000000001008000000000000000000000000000000000009000400000000000000000000000000400000000000010000000000c000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000040000000000000000006004004800100184004000004184000000000006000204120c0010000810484020c0002001201081002001c480010000010012008008400400484210000000012400000000200480008200000000000000000000480000000000012000004000000480000000000000000000000000400000000000000000002000004ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000104000000000000000000000000000000000000000000000000000000000000100000000000000000000000000100000004000000000000000000800000020000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000200000008000000000000000000000000000000000000000de7e00000040000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000001000000000000040100000000000000000000000000000000000000000000000000000cce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000102000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000020000000000000000001000000000100800410500800004120000000000000000000004000000000000000000000008008008201000008000000000000200009008000008000200200008001008000000000000020010000000001800200000000000000000800000020800000000000000000000000000000000000000004000000000000000000000002ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000010000000020000400000000000000000000000000a000000000010040000000000808000000000000000000000000108800000000000000000000000002080000000000090000000000000000000000000000000000000022000000800000400000000000020000000000000080000000000000020000000000000000000000000000000000000000000000000000090000000000002000000000000000000000000000000104000000000000000000000000000000000002fea00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000004000000000400000000000000000ace040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000020000000000000800000000000000000000008000000000000000000000000010000800020000000820000000000000000000000100000000000000000000000000000000008000000040108100000001010200000000000000000000000000000000000000002000000000000000000000002000000000000000080000004000000000000000000000000000100000000000002080000040000800000000000000080000000000000006008000000000000400400000100010010000400100000400010004000400400400100410000401004000000000000100100800100404000120000020100000a000080041001202000000040000000000040000006ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000400012000000000000000000000400004000000014000000000020400000000000020000000000020800000006006020000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000200000000000000000000000000000080000000200000000000800000000000000000000000000000800000000000000000000000008000000000000200000000000008000000000000200000000000000000000000000200000000000000000000000000000000000000000be4e00000008000000000000000000000000000001000000000000000000000000000000000000000000000000008000000000ece040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000010000000006000000000000000000000000000000000000000000000080000000000000000000000000000000000004000000004000000100000000000000000000c0000000000000000000000000000000000000000000c00200000000000008102000000000080010000000000000000000000000000000000002000000000000008000000000000000000000000000000000000000000000000004000000000000000802000000000000080000000000000000000000000000110000010001000400000000000000000081000000001000040040001080001000000046001002040003000000001000008000000040004200000201000020000001ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00300000f240080000000200000000002000080142801002040000080000208000a000000000010000000200020004000000000400000010000010020101000002480804010000000100000000000000000000000000021400000000000000000000002000214000000000008000400000000000200000000000000100000411200004000010442800010000000000000000000008000000000000000000100000000000000002400000000000004902000000002400085000800000001200000000000000000000000002800000000000000000000000000000000000000000a65d0000000800000000000000000000000c0080000000000002000000000000009ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000080408000100000000000000000000000001000000100000200000000001401050000000050001000208001400400008000800008000000000001000000000000001400000001402410000000050001400000000000000000100000000000000000000000000000000000000000400214204000004002d009800004080010000000000000000000004000000000000000000000000000000000000000000000400000080000000000000000000000000000000000000000070028000400000000000000000000400000000000000010210000050028002402000002000080080080000000000008000000000082000000806000000110000100000008000005ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800100000010020001000000000004000006010010200000000000000100000000000000000000000000000000018000000000000001000100210000010033000ca0100000000000400200084040000008100000000000200000020010000000000000048000000000004000000000000000000000000003000000100100041084000004040104414000000400000000000010000000000000000000000000000000000000000000000000000000000000000000000010000004000000000000090004000000000300104884040000000000000000000008000000000000000000000000000000000000000000000006f5f00000000000000000000000000dce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000e5c200000000000000000000000000000042000000000000000010000000000000020000000000000000010000000000000400000000000000000000000000000000000408000000000000000010000000000200000000000000400000000200000000100000000000000000000000000000000000000000000000000000000000482000b2404010200040000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000042a000000000000000000000000008000000800000000000000000002200000010000000000000500000000000000003ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000001000000d40000000000034900000300000b5460000c0000000000010001000400010c208103800405018208000411000010002000000000000000000161844000010000500400420011026840031824400000000000000000400004800400120000000800000000805800000000000000000001804000000000000000000000000200008004200000010200000400000400000800000000000000000000000000000008204000000100000000020000000000000008000000000000000000000000000001200080000800001000000000000200000401000004005200660000000000000000000000000000000000000000000000000000000000bce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000016e90000000000000000000000000000104030000000106000c000000000000000000000000000000000000400000000200000100000008000000400100000000100000100000000000000100000000000000000408000000200000000000008000000000000000000000000008000000000000000000000000000000000000000482003000000010000400000000000100000000000100000000000000000000000000000000000000001000000000000000000000000001000000000000100002000000000000000000000100010000400004000000000000000000000080198000002000001400000007ce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000800008040010000000000000000480000040800000000001210000800000049000000800001008000040004808820000010000000010410100080008008000000000108008200080000000000000000088000448800800000008008008130000a0480200800000000000000040000000000803000000000000040000400000000000000000004800004000000000000000400000000000008000000000004200110204400400081000020c04000880000410000002000000008000008100000000080000000000000000000000000000000000000000000000000000001000000000006080200000000228400010408000008000000000000002000000fce040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00008100004000000400000000001000000001000000000000000000000000000000000000000000314100000000000000000000000000000000000000000000802000000000000000046100000000000000100400000008000000000000000000000100400c000000000002040000000000040000100000000084004000000800100000000004000000000000004000000000000000000000000000000000000000000000020000000000004820000040000010000001000800000000000800020000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001002041004000040000000000002e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0210000100000000002008000000000000000000000000000420000200000100040000000000000800000000002020004000080080820000010008020805000880000000100045104000a0200420000080008001200802080200302480000000100000000000100004c00100088084410280000008004080000024000010004004800040000000020004000004000000000000000100000000000000000000880000000000000000002000080010c00000800001011201000000000000811000000000011000000000000400002000100800000000000000000000000000000000000000000020000000000000001000000040200021000000801000001000000082e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (090000000000002002000040044012000480000000480000000002003000000000000000000000000000000000000000000000000000000000007400000000000000000000000000000000008000000000000000100000000000000008000000000020040080000080000002001002000000008200080080040201000042840100000004262000200000001240008000080002002000002000000000001000000000000000000000000000000000000000000000000020000000810040004100520800000004000000000000000000000000000000000000000000000000000000000000040000000000000000000000000040000200000000000000000000000042e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000110900000000c00108000000000000030000000000000000024c31100840000000c0000000000040000000002400010000000cd00000000c4000000000002010500000200080922002000102081109040000000000080000400102800402000000000003000013001108002050000020440000200009040000010080000000000402000400000010084000000100000000000000000000000000000000000000000000000000100001020000010000820400000000001000000000002010000001000000000000000000000000000000400000000000000000000000000000c000000000000000000000000000000c2e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000100000000000000000000000000000000000400010000000010000202002080000004000000000000100000000000010000000008000000000000000000000000000000000000000000d3b0000000000000000c0000000000802080000080000000008000000000000000008000000000000044000000000082000000000000000000000000000040000000040040080000002800000000000000800000100000480100000000002080010000000000000000000000100000000000000000000000000000020000000020900000800000024000008000000000000000000000000000000000000000000000000000000c00000000000030000000000000022e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000004000000000000000008000000000101000000000000000000000000000001000000000008000200000000000200000008005000010800020300000000000006000200802000a0100802008200c80020088000260300002000001e08200000048030000000000000000000001000120108800000080e0000100240011110004000000200000000000000800000000000300000000000000000000000000000000000000010000000800000000000000000400010100000000000001000200000000200000200000000804000000000000000040000800000000000000000000000000a2e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000020000000000000022000000000000000000000000001000808400000200002000000001000000000000040001000000000000000100000000000000000000000000000000000001000000000000000000000000000000000005a2d00000120000000000000000000040200040004000800800000000000000000002400000000000000000000010008000000000400000000000010000c0000000000000000000000000500004000000010000100001004040000000040020000200000000040000000000000000000000000000000000000000000000000010001100000000c0000000000000000000000000000000000000000000000000000000062e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000100002000000000000180000002180000002000000000000000000800000000000000004004080020000100102000000000800000000000c080100800200000000800000004000000000040800000000000000004000000010000104000000004180000001000006400000080404400420086000a20110000002c0040010800000082000002000000000000000004000c32000000600000020000000a800300000000000001001048004980000000008400000008000000000000040009800084060000000000000440000000000000000004410000000000000000000080000000002000000010600090020000000010008000020000000100200100200e2e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000400420000000100000020002000000100000000008000000200000000400000000000000000000000000000000000000000000000000000880820000104000100400000200000000200001208200000000000002080000000000000000000000000000000000000000000000000c8ea000000400000000000000000100000000000000000000000000000000000000800000000100001020000000000000000000000000000000000000000000000000000000000028004022000000000020040000000000000000000000000800000000000000080000000000000000000000000000000000000000000000400000000000009000800000000000000800012e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (100001000000000000100000000000000080000000000002000000020000000000002000000002800000010000000000000000000000000000000000000000000000000000000000020002000000480082000034080080000000000000000000000000000040000000000000000000000000001000000048000440000020400000000000202001000000040000000080000840000213003051002020440000000040000000040000000000010400081082000802000020000010000800041144000000000000000400000000000010820010000000000000000080000000000000800000000000000000000000000000000000000000914000800000000000040092e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010000006090404000010000010220000100250000000020000040000000100002084000010000000400000000004100000000000000080000000000081000000040000000000001001040000000000000400020400200400410001210400000008000000000000000000000000000000000000000000000000000000000a2e9000000000000000000000000000010000000000000400010000000000000000020001820800000000040000000004000000040000000800401000040000000000020104020000000000000820040000000040000000004000002000000000000000000000000000000000000000000000000000800040000040000000052e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000204000000400000010000008100000000000000004010000010000400000000000000000000000000000001000000000000000000000000000100100000000004004000000000400108000400002430200400080c12080000000000000000000202001002000040000000084000000a00008000800000086000030002100820020840008080000801402020100106080040020080080c00000882001020000020080000401000000000000001040030010480000400000000021030010420000400000000000000024080020800008c2220080008200000000000801000020000000000000000000000000000000000d2e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004000000040002000001000100000000000000000000000000040020000000000000400000000000000000000000000002000000000000000000020000000000000000000000000400000020200001001000840200000802004001012400061000000010080002000000484000000000080000000000100000810400000020000001000000000000000000000000000000000003b07000000000000000000000000880010000000000020210010000000000400001000000000080000000000000000001100000000000002000400000000000000000000042000008002060800000000020000000000000001000001000000008000000020000000000000000032e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000008000008000000200000000000000000000000000000008000000800000000404004000000000000200010400000000000000010000000010000400000000000000000000000040000000000000000000000000000000000002010000000000080400000002400410001000020400c00000021000800000000028000000000000800800804000000020200080000900118000000000010000000080504000120024030004204000c00c00c081001001000200000400400000001008021000080a40011081a4840204008004208201100280202a000001000240000000000020002000000010000020000000481102810000010a000000000000000000b2e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02080000062080000000002000000000001000000000000000000000102900010000000000000000210000100010500000000080000000000000100010000000000000000400400400830000080000000000000000010404000000000001000001200000028000000000000000001200000200000000000008000120000000408000008000000000000000000000000000000000000000000000000000000000000000000000651d000000000000000000000000200001000420000020009400800000000200004400000001000042050001040000020800001000800024040800040000000020000000000002020000014020000000010080000000000800000072e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00001082000000000080000000210c0800000000003000008000000008000100000000000000000000000000000000000000000020000010400240000000310000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000100100000004104000000000100000000100300004000000000004002000000000000000000001000400000002300400803004000060092000080032002000000000c8008000002003000000080000d0120000410803020000824004090000020800000004020000088044a0060820010000000822104021000020000000330006000002002800024000000000001102000f2e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040200400482020000400000490000000400000481a00000000410800000000000000000000000a0000002000000000800400000000000000002400004082004000000000200000000000002000000004000000000008002004000000000400000000000000010000080000800000000c3001000000000002800080100000100040226000000411000410000200048000010000000000000000000000080000003001000000000000000000000000000000000000000000ebd7000000e0000000000000000000000200001000000800200000000000000000000000000204044008000108008000090002200380002008004000002000000000000000000000000ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000200904040108000020000008000a090000000c0020208100000000105014000000000020000000030c008000000200000000000000000050000001400000001000401000002802c004008000000200000100000000000000000000000c00000000010000000000000000000000000000000000000000400000000000010000000010010000410000000000000200010000a00400200000010000200000000c0004000000000000010000000000008010100014200000004000400000010000010040100d0010020000800010040c00141020410010820802834838820041020010080920800408002a140000c880042a400410100c02c00012c00c001100008ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000000000000410000015080018005800000804088a00020000400002000080000000090000010000000000000400000002000140000000000000000000000000000080000000200800000100000002000003005000000800000300000000000000000004000100000000000200050000004000000000000000000000000000000000000000000000000000000000101400000000000824000800002021400020080070000004050800000000000000080100004000800000000000000000000000000800000000095f7000000000000000000000000000000000400000020000800828a000000000000080042082804000001000000b002000000810000004ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0a000800000000000000004000800400000100000000000003401008003000000000020140000000001000c000000000a0000004000800000000100030100000000002000000000000000000000000000000404000300000000000c0000808b0000000010200140a000000000000808000100010000000000000000000000000000000000040000000000001001000000000040040000000000001400000000000020000000000804000800000000000000000000000000100050800400000050000800000000000000000000000000100020000080000001000804000000046100000000802000024000004028000820020408080024000000010020880004000cae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0084000100000042200080800002040004a00000000000000000a1014002800800000020200040002000400010100000000000000000000004200000000000000000000000510000000000000000000000000002000800000000000040000028000020800400040425040000001000b5000800088012d400000010000320010008000000000a0000000000000000000000000000000000000000000000000000000020402494000000040212d000c0000002000000000023010080008000000000000000000000000008000000000000000000000000000000000000a89c00000000000000000000000000000000000000000002800020008001400000000000002ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000001000100149400000000002ad000000000000000000000000000000000008000000000000400025000000000011b400000004000ad0000000000002000001000000000200040000000000400000000000000000000000000000000804000100000000a020000000000100200040000000000000002000100010010000000000000000000000000000000000000000000000000000200040000000008000000000000200200000000008002010005000080000080a000200000000000000000000100000001000100000000800000000000000000000000000080040000000004000001004000000000000400010200000420000d00032200aae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000400001000008010102800020200008040004008000002800060004200000000000000000000000000140000400095820000000008000000000408040800000000000a00005140002a00100005000140000000000000000a00000000000000000000000220000000000000000000000280081681400000008003400200080000200000408408008000200010080010000000000000000000000000000000000000000000000000000000000000000000008190080000180008020000000004000000012100400000800000880000000000000100050000000800000000000000000000000000000000000036db00000000000000000000000000000000006ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c08e00000000000000000000000000000000000000000400000000000000000000000000008040000000000000000000000000000000000000002000080008008040000000000500000000000040000000000000000000000004008000000000000000100000000000000000000000000000000000000080000000200002002000a0000004540000800000000002800200000000000000400000000000000000000000000000000000000a000000000080200000000002012000000000880000000000000000010000000080000000000000002000000000000000010000000000a100000000800000000000000000000008000000010040000000000000000000eae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000020100002000800000000080020001000020084100800001200008100000001104101000001104024000080010081000000000000000404402010242000822000882020084042081040100000000008004020000044001100040001000000100008800404000000000000000000000012200000000008402400000002000c88928044010122122100c00484c86184030026132106100000486204c82000100000004000000000000000000000000000000000000000000000000000000020408904284884820006102122120008800022088081004000400800000000000000c00200000000000000000000000000000000000000000000001ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000093fa0000000000020000000000000000000000000000020200002000000020140408408405002210210210000000000008000000000000020200020009004405009010210210080028408408402404210210210200088000008000000000000000000000000002000000000000000000000000000001000000000020000c02200040040010120010020204040002000400000040000000100000000000000000000000000000000000202100000000030090000000000c00a00000000030030000000000800001000100000000000040000000000000000000000000000140010021000400000040000000000000009ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001200000810000000000400000000000000000000400010002000000000000000000000000000400040004000000000000010400800080000010400000400080000402000802010000000000000000040480002100000002820000002000400000081010004000100800402000800400010000000000200010000200000400000000000000000000001021000000000040840000000200008a10800400610600210090208508418408008210218210000040050528200010000000000000000000000000000000000000000000000000000000000000000000818468208481802a102102100009004244090081000080100000000000000000000200000000005ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000002000000000000000001000040000000000000000000000000000000000000000d32b0000000000060000000000000000000000000000000000000000000000018408008408000210210210000000000408000800000100020000040008800005004610200210000018408408400000a1021021000000800040840000000000000000002000040000000000000000000000000000000080800010000000000008004004180410200404020404000200000000004000000020000000000000000000000000000000000120100000000004004000000000100080000000008000800000000000010100010000000000000000000000000000000000000000dae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00002000000000000000000000000000000000000000000000000000002000000000000000000000000200000000000000000000000000000000181000000400080000000008000000000000002201000000000008000008000000000000000000000004000000000000000020400000000000000000080010000400004000080800080080000000008000100000000000000000000000000000000000000000000000000000000000000400000000000000000000400100400000020020010020000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000100000000080003ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (030030000080010c00c0050080040002000000002000000000000000000040100004000000000000000000000000000001000000000089d7000000000001000000000000000000000000000001000000000000001000000000000000040000000000001000a00100000000028005000000000000600000000000000020020000000000000a00000000000001000000000000800008000000000000000000000000000000000000000000000000000000000000000000800001000000000008060000000000000000002000000000000000000000000000000000000000000020000000000000000000000000000000000000000008000000000000000000000000bae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000001000000000000000000000000000008000400000000000000000000000000000000800000000000000008000000000000000000000000000000000000000000000000000100000000000001008000002000000000000000010000000000000102000011200000280800000000000000004000000002001000201000011000000000044200000000000004000208000200200000000000000100000000000000000000000000000000040001000000001001000000000000000480000000020c80c00000402030430000000000c10c00000000012020000000000010000000000000000000000000000000000000000000000000000000000000000007ae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000002140110008008682444400214212020020808489020000a800009000000000000001501000040008000000000000000000000000000000000000439100000000000000000000000000000000000000000000000000000000002000030030010000000c00c00000000000024000000000000000000000000000000000000c00c00800000030030000000000c00c004010000a00200000000000000008000000000000000000000000000000000000000000000000004000000000401402400000001200000000000000000000000080000000000000000000000000000000000000000200240000000008008000000000200000fae040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000200000000008010000000000200a00000000008020000000000000100000000008040010020080800200000000000000001000000010000000400008000000000000000000000000000000000000000000000000000000000000800400211020808220008000201000000212000808200001040200008800120008000000000000040000311008c4080c00001282000d0003008000400002000080000000090004010140004000100400000002000100000000000000000000000009001000000000a4004000010000008001400a00a402202a1008002000849840100100221021008004009040800000000000400000000000000000000000000000006e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000052190945200001486425148000052390000040000a00000000000000000000000400000000000000000000000000000000000000000000003eba000000000000000000000000000000000000000004008020000000034009000800840100300021021000004000440880000c000000000350080000002800800400200210140080008408405402000210210000044002408000802000080040000000000000000000000000000000000000000000000000000040003400a400100080000410008000000000000004000000000028000000000000000000000000000000000086e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000010000000000000000000000000000c18000000000030600000000000c18000000000030600000000000c00000000000000040000000000000000000000000000000000000002280000000000040010000000000000000000000000080000210000002400008000000080000200002280400000000000090000210002280400000000000090000210000002400008400000000000000182280400000000000090000210082280000008000040000000000001002000000400040000000000000280000000000000000000000c9800200000003060000000000000c18282000000430614864251480c18521909452030614864251480c1852190000003000046e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (dd36455555383774d9155554e0dc000002c2c00000000000000000000000000000000000000000000000000000000000000057574c0ddd36455c05383774d9157574e0dd150000000770000000000000000000000c0c0000000000000000000000000251400000000000000061ac000000000000000000000000000000000000000000000000000000000052190945200001486425148000052390000040000008000001000028200000040001486425148000052190945200001486425148000052390000040000008000001000008000000000000000000000000000000000000000008000001000000282000000400000080000010100000000000000000000c6e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (f0004100000581fe0000000000000000000000714880000000000000000000000000005555000000000155540000000005555000000000155540000000000000000000000007fc00000000000000040000000000000000000000005b8560000016bc000000000000000000000000000000018a8c000000000040000000000004400c5314208000000b3340000564c2cd966626000000b33400007e757696900001f5b380000000000000ffff1426200003088c00002500b00001118c0000031300000000000c4c00001605183130000000000000001000000000000000000000555500000f70015554000000000005555188c2530955555303774d9155554e0d0026e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (06a6a188c253095a9a92038f718e6a6a498e3dc639a9a92638f718e6a6a498e2000002c2c0000000000000000000000000000000000000000000000000000000000000000303480e3dc6380c052638f718e0303498e2310000000e30100000000000000000000c0c000000000000000000000000000020010100000000003bf7000000028a51a0000000000000000000000000000000001000000000004c0ddd36440001383774d9100004e0dc110840000000004400000072800118000001303774d9100004e0ddd36440001383774d9100004e0dc710840000000004401000000000000000000000000000000000000000000000000040004000000010016000a6e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000001f1d04000000007c7ff00000000000000000000000a8880000000000000000000000000006a6a0000000001a9a80000000006a6a0000000001a9a80000000000000000000000005500000000000000004000000000000000000000000592c4000009c9c000000000000000000000000000000018a8c00000000000000000000000000000f54608000003b30400004ef3dc169662e400003b304000001b119696000016e77800000000000005d5d68662000033b8c0000002a0000042fac0000001100000000000044000012250001100000000000000000840000000000000000006a6a00000f7001a9a800000000000066e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000006a0000067001a9a8000000000006a6a21c5a211a9a9a990c200c726a6a66308031c9a9a998c200c726a6a6630800001a9a8000020200000000000000000000000000000000000000000000000000000000000064308839c8000198c200c72000066308e18000c0d42000000000000000000000001c000020200000000000000000000400000000000000003b030090a23000000000000000000000000000000000000000100000000000480e3dc63800012638f718e0000498e21108400000000044420000728101100000012038f718e0000498e3dc63800012638f718e0000498e2500840000000004400000020000000000000000000000000000e6e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0840800000000000000000000000000000000000000000000000000004000000010221003a000000000400f6800100000000000000000051400000000000000000000000000000006a0000000001a9a80000000006a6a0000000001a9a80000000006a6a000000000000000000040000c1400000000000000000000000000018dd200000000000000400000000000000000000000000085800000000040800000000000000000000001800800000000004223e000042222008000000000009a700000000014d100000000000000005cd0026280800000000001024acece0809800020000000000400000000000010120000000000400000005169000000000000016e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2c24000000000020000007029c000000000000000000c055000006702555540000000000055552185e215ad555580cc83064555561b220c191555586c883064555561b220000155540000042000000000000000000000000000000000000000000000000000000000000603221c990000186c887264000061b223ba255d5c0a250000000000000000000003c00000420000000000000000000002000800000000000ce750000508a10000000000000000000000000000080200c0000000000000064308031c8000198c200c72000066308210a8000000000840000000210021000000190c200c72000066308031c8000198c200c72000066308210a8000000000096e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000186c883064000061b22204ac0000000008529000002000000000000000000000000000000000000000000002000000000000014052400000000542cf00000000000000000000000a800000000000000000000000000000c055000000000155540000000005555000000000155540000000005555000000000000000000002000c1f000000000000000000000000000309d600000000000000020000000000000000000000000085100000000000804000000000000100004c018008000000000042ac10000422ba0080000000000526310000000016a9640000000000000ffff0227210800000000000a201c2c220ab800004000000000020000000000000056e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f2520c1200510000000000000000000000000000080000c00000000000000603220c190000186c883064000061b22214ac000000000840900000200021064000180c883064000061b220c1900d6e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (020000200000020000800800008000020000000000000000020000000220000000000800000001000100000020000040000001000000800020000000000000020000000000000000000000000000000000000000000000000000000040080000000000000000000000000000000200000000000080000200000000000000000080001400400000000050000000000001400000002400050000000000008000000001000000000000000040001000001001000040040000000000000020020800000020020800040000000008200000000000000000000000020000000040000020000000000000000000040000000000000000000000000000000000000000000036e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008171000000000000000000000000000000020000000000000000000000000000020000000000000000020000000020000000000000000000000000b6e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084010000000000002000000080000084002000004000000002000000000000040000001001000000000000000030000000000000004000000000000000000001000000000000000000000000000000020000c0000000000001044040040041100104001100100000100100100040006004044040000000000030600000000000018000000600000000000000000000000000000018400410000600400510100000c0000800a00000000800800000800000040000020100000040000800800000000020040000000076e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01200000000020020000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000063aa000000000000000000000000000000000000000000000000000000000000000000000000000000f6e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000800000000000000000000001000000000002000040080000000002000000000000000001000000002000000000040000000001000000001000000000000000000001000000001000000000000000000000010000000400400000000000000000000000000000000000000000000000000000400000000000010000000000000000000000000000000000041041001041041001040041001000001001001001040000041041000000400000000080000000000000002000080000080080002002000000000000000000000000000000400404000000201200000000200200000200000000000008000ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (410820000000008408000400600000200008000000000000400000000000000000000000800200000000100000000000000000400040000000010000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000004004000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b0f00000000000000000000000000000000000000000008ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000040000000000000000000020000000000040000000000000000020000000040000000020000000020000000000000020000000000000020000000040000000000800000000000080000000000000000020000000000000000000000000000000000000800800000000000000800000800000000000000000000200000000000400000100000000210000000008000000008010000008000200000008500008002200010400200408800000000000000020000082002002082202482010082000000000000808000080000000002400408800200000001000000000000040000401008001000110000000014008000000000000000000808000800000000004ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (002030030000000000c0000202000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000001000000000000000000000000000000000000000000000000000c000001000000000000000000000210000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e2ac000000cee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000002031000000000040000000000000000000000000000000100000000000c00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000200000000000000000100000000001801000000000000000040000000008000000000040c0000000020000000100000830020004d00020000000000000c000300300000080008022208208082000882000000000020000000000000800008000002000000000030030000000060000c01030032030030040c00000010002ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000200000008000808001000000000040000000000000000000008000a08000000008208200000000048040008009000001000050000000000000000000020000000000000008001000000001000000000000000008800200000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000020000000000000000000000000000000000000000000000000006d2f000010000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000010000000000000800000000080000000000000000000000080000000000000000000000000000000000000000000000000000000000400000000200000400000000000000000000000100100000000000000080100000000100000000000000080000002000004000000000004100000004000000000000800800202000001000020000000000200002000a0002a00020000000020080400000200a000000800800800100000000800000006ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000400000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000010000020000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000eee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000020800000000000000000000000000000000000000000000080100000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000002080000000000080400000000000040000082000080100000000002000000000000000000000000002000000000000000000000000000000000002000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000020000028100008800004200000200000000000001a000001ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (12004000000000480000000000012120000000000480c00000000000000000008200000004000208000000000020200000009000000000000000000000000240000000000000000000000000000000000000000400000200000000000000000000000000000000000000020000000000000000000001000000000000000000200000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000010000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000400000000000000000009ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000008000000000000010000000000000000000000000000000000000000000000000000208000000000000000000000000000000000000000000003bda000000000000000000000000800000000000000000000000020000000000000200000008000000000000100000200000000000000000000200000000000000000000040000800000000000000000000000000200000200000028000000000000000000000000000000000000000000000008000000000000000000080000000000000000000000000000000000000000000000020000000000000000000000000000000080000000000000000000000000080000008000008000005ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000009100000048000850000040000052401202220000180048080000030001210450000840048010400000000000000000880000000400020800000000001020000002000000000000000000000000020000000800000000000080000000100000000000000000020000008000000000000000000040000020000000000000000000000000000000000000001000000080000020000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000008000000000000000000000000000000000000000200000000000000000000100000000000000000000000000000000000000dee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000e95a000000000000000000000000000000000000000000000000000000000000000800000108000008000000100000200000000000000000000200000000000004000000000000200000000000010000000000000200000200000008000000000000000000000000000000000000000400000008000000000000000000080000004000002000000100800000000000000000000000100000004000000000000000000000000080000000003ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000840000000000022000040011001080000800040000800020001000c40011020040040000000000000000001000000000000040000000000000800000000400000000000010000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000040000002000000000000000000000100000000000000000000000000000000000000000001000000040000000000000040000000000000000000000000000000000000000000000000000000000008000000004000000000008000000000000000000000000000000000000000000000200000000000bee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e2ef000000000000000000000000200000000000410000000000008000000000000000000000000000000000000000000000000000000000008200000200000200000000100000200000208000204000000000008000000200000020000000000008000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000004800000000000007ee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000084000000400000000000000000000000000000000000000000000010800000010000020000020000031000000000000000000000000020000000000008800000010000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000020000000000000000000000000000200000000000000000000000000000000000000000fee040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000fe4e0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000020000000000001e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000040400200000000010000000009000400041000008010002000000000000000000100000000000004000000000000000000008000000000000000800000000000000000000000000000000000000000000000000002000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000100000004000000000000204000000000000000000000000000000000000000000000000000000000000000000081e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000180000008000000000000000000000200000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000046f20000012000000000000000000000000000008200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000041e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000180022006000040080002180000000000000000000000000002000000000000020000000800002000000000000000000000000000000000010010004004880480400000822400800800104010004100900500000080000000000000000000204000000000000800800000000000020008000000e000000000000000200000006106000204008000000000006000084008000000000920100020180000000000100000300000000000000000000000000000100a0000000c0000000000000002000000000000000000000000000000061081000000000000000002000000000000000000000c1e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000400000000000000000000000000000000000008000000000004000000000000000000000000000000000000000000000000000000000000000000000000067a20000000000000000000800000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000200000000021e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000002000000000080000000000000000000000000000000000000000000000000000080002000000000020004020800000000024040000000000080000820000820000820820020800800000000000004020020000000000000000000000000000010010000920000c0452480000002000000000010800000000000400200400000080000000000000000000100000000000000000000000100000000000000000000000000000000000000000000001000000001000000000000000000148400000200001000000000000800000000020000000000000041000000000000040000040000000000000000000000000000000000800000000000000000a1e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000100200000200000000004000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000040000000000041000000000000000000000000000000000000000000000000000000000000000000000000870d0000000000000000001000000000000000010000000200008008000000000000000000000000000000000000000000000008000000008000000000000000000000000000000200000000000000000061e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000100000000400000000000000000000000000000000000000000000000000000000000000000000000004000000000000000100000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000410401000410400000000108100410410008410210010480400400000000000000400041200001000040080040000040001001041000000000000000080000000000000000000040000001000000002000002000020000041040000080000001040000000082000000080080000000000000041040000000002040000040001000040000000e1e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000280008000008000200000008000200000000000000000400008000000008000000008280000000000000000000000000000400000000000010020000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000200000102000000000000000400000000008000000004400200000000000004000000000000000000002000000000000080000000000000000000000000000800000000000000000000000000200000000000000099e70000008000000000000000000000000000000000100000000000000000000000000400000000000000000000000000000000000000000000000000000011e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000400000000400000000000000000000000000000010000000000000000000000000000010008000000400000000000000000000000000000000000000000010800000000400420000000000200000208010014000100000100000000000014100004500044004100104004200000008000000100100000000200000008208204000000200000000001180000000000044041040040000101000040002006100200004004800000040000080100090002002002000002000180012000000000000000002000000000000000004800000000000000000000000002002000000090090182200000002000000002100280202014000004000000000091e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000008000000000002400000400000000000080000100000000000000000000000000000000000000400000000000000000008000080000000000020000000000000000400000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000008a60000008000000000000000000000000000010000080100004004000000000000000000000000000000000051e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000010000100110000000480000000000000000000000000000000000000000000000000000040040000041041000000041041000001001001001000000011000000000020000000000000000000000008001012000040008000000000002001000000000000000000000001000800000000000000000000008000000200000848020020000002000000000000000000000020000101000008000100d1e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000400000000000000020080002000000c30c2000002000000000000000000000000000001000000040000000000500001000000000000000000014000000000000040000000000000001001000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000400000000000000000000810c00000000420000000000000800000000000000000000400000000000000000000000000000000000000000000000000000000000000000000010000000000000004053000000a000000000000000000000000000000000000000000031e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000001000040000000000000000000000000000000002080000000000080000000000000010a0000008080000008042000000000000100000004000001000000000000000000000000040040000041040000000000000080001000001001020821021000820020840820020000001000000020008040000000000000000000000001000000000000540040000000000001000000000340000000000008001000200000000001000040001000000b1e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084200000000000000071e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000042560000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000500000000000000000008000000000000201000000000000000000000000000000000000000000000000000000000000000000000000f1e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010009e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000010000000000000d8a1800000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000280000000000000000000080000000000000000000000000000000000000000000000089e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000002d5f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030010000000000000000000000000000000000000000c9e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (842848021021809221040020211020001000040801020000840840000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000029e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000082a40000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101100020024000a9e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000020020000840840042800021001021a20000161821020001000040801020000800040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000069e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d3f90000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e9e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000008000000000200000000000000000000040000200000000004008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000019e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024d4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000099e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400400000000030030000c00c20c00c100008004008004001120204008000300300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000059e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001d820000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d9e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020020000840840040808021001021820100061821020001002050801020000800040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000039e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f99e4000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b9e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000079e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000004001c510000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f9e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005000000000000f08000000000000004000000000000f080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010d1405014000000000000000000000000000940081c0000000008ff58a3800200000071020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000050000004000087180000000000000040000004000087180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000080110000000000005000000000000140002000000005000000000000140000000000000000000000000000000000000000000000000000000000000000000050000000000000000000000000000000000000000002000000000000000000000001400000000000000000000000101400034000020050000000000000000000000000050000800000000000000000000000000000000000000000000000008000000000001400000000000000000000000000000000000000000308103810029b0281a3c200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c5e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000005000000a00000140000000000005820000000000148000000020005800000000000160000000000000000000840000000000000000000804000000000020800000000400000000000000000000080000000000000008000000080000000000000000000000000000000000000050000000000001400000000000050000000000000000000000002000000000000001680000200000058000000000001108000040024244040101000101100024044000244d010000000011080200000000000008008008040200000008008440008000008000000000000000000000000008000000000000000000000000000000000000000000000025e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000004800000000000000000000002004882000000100000000000000004800000000000000000000000180000000000000000000000000000000000000000120000000000000000000000000000000000010000000000000010000000000000000000000000400000000000000000000002000000000000000000000000000000000000000000000000c00000010000400000000000000000001000000000000000000000000060000000000000000000000040000000000000000000000000000000000000000000000000000000169e0000000000000000000020000000000000800000000000160000000000000000000000000140000000200000800000a5e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000040000000000000000000000000000000000000000010000000000040000000000000000000000000040000000000001000000000018000400000200000000000000000040400000000011008000000002000000000000000000000000000000000000080001000000000000000000000000000000000000000000000000000000000006180000000000000000000000100100000000000000000006010006000000000400000000004000000000000000480008000600612000008000000000010000030600000418000000480010610010112500000004214000010000010000000200244000480008000010200108200065e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000080084100000002000000080006080000000000000000000000000000000080002080000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000040000000000000000000000001000000000000000000000020000000000000000000000000000000000000000300000209000000040004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006b9d0000000000000210000100000000000004000300000000100000002000e5e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000800000000400000000000020000000000000000000020000000000000000000000000000000010000800000000000000000000012000000000400000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000004010000000000000000000000000000400000000000000000400008000020020200021000800000000021020000100c00000000000008000000000000000000000004004000000c801000000000000015e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (100000001000104000000800000100200000208080080000008104200000000208000100000008004000000000000008000000000004000000000000000000000000004000000000200000000000000000000000080000040000000000000000000000000100010000000000000000000200000000000000000000100000000000000000000001001000000000000000080000000000000000002000000000000000000000000004040000100000004000000000000000000080000000000000001000000000000000000000000000000000000000004000080000000000000000000000000000000000000000000000000000007f1100000000000000c000000095e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000d2ea00000000000000000000200000000000008000000000200200000000000000000000000000000000002000008000000000000000000000000000000002000000000000000400008000000000000080000000000008000000000000200000000000000000000000000000000000000208020000000200200000000000000000000000000000800800001000000000000040000800000000000001800000000000000000000000001000000000000040000000001000008000002040040080000020002000000020002800000000000080001000000000000040000102040004000024101040100100000004000000004100044004000004040055e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (30000c0040002000004001100080000080000000000008080000000008080040080000000600200000000004000000000000000000000180003000000000000000000000000000000000000000001000000000000080000000000002000000000000080000000000002000000000000000000000000000000040000000000000000000000000000000000000801000000000000000000000040040000000000000100000000000000000000000020000000000000000000000001020000000000000800000000020000000000000020800000800000000000000000000000000000000000000000040000000000000000020000000000000000000000000000000d5e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010802800000000000000000000000000000000000000000e10200000000000000000000000000000000000000000000400200000000000000000000000000200000000000000000000000000000000000000008000000000000200000000100008000000000000200000000000008000000000000200000000000000000000000000000000000000400000000000400000000000000000000000000000000000000004000000000000106000080080000000004800000000000000000000000084000000000002100000000000080000000000000000000000000000000000000002000000000000080000000000001000000000000040000000008001000000035e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0808000080009242a000000002480a808000000000000000202000008000208200088200a00000000000508000000008000208200000608000040000028000200000000a08000200000008004000100000000008000000000000000000010000000020000420000000000010300000020000d00080000000050800040000000000000000000000000580400000000000000000000200000000000001200a00000000000000000000000000000000000000000000080000000000000000206028000000000000000008000149028000000020002a000000000020000000800000024000000820000000000000000000000000000000000001000000001400010000b5e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000004000000000000000000000000040200000000000000000000000000000000000000000000211c000000000000000000005200000000000000000000200005000000000000000000000008028000000000000140204000000000000000001200a00000000201028000040000000000000000004028000040001200b4024100010002d00010000000000000000000000000000000000014062100000000502880000000000000000000000000400000000000000000000000000080080004000000000000000000000000001840a0000000080402800000000010200005000000208008008000000000200000025802d008000000000000022000000075e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02800000040000000002000000000040009000000004000000000a0000200080001010402002000000010000000000000000000000100000000000000000080200000400004000000000000000000002020000000000000000000000000000000100000000000000040000000080000002000000000040000080200200000000000000000000000004000000000000000000000000020000000000020080000000000000000000000000000000500000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040400000001000000000000040240004000000000000000000000000000f5e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (420000300000000000000000000004000080000000100000100000000004100008000600049200000000400000000000000000000000000000000000a9f8000000000000000000000000000000000000000001000000060000000000000000000040000000000000000000000000000000000004000000000000000000000002000802000000000100000000000000000100000002004008000002000000000000000000000000000000000000000090000000000001100000100000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000200800000000400c004000000100010000000410100000000000de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02390004000000008440000000040000000000020004100000500000211004800000060000000000000104000400000004100000000222186c04001010000000000002400000000106280000010000000800000000000000000000000000000040020000090000000000000000000000000000000000000008000000040000001200828400000800024010004004000800000000000120000000000200900000000000208000008000000000000028800000000000800000000000000000001044040000000000000000208000000000000000000000000000000000000000000040200000000000000000008000009000000000010080000000000002000000008de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000820000000000000000000848000000000000000000000000000000000000000000000000000001000400000800000000000000000010000000000000000000000000000000000050cb00004000000000000000200060000000008000100040000201800000000000000200001004000000000000008041a0000000000010000004004000000004000000000000401834800060000820000000040064804004020000800001820810000000000000000000000000000000000004900000000000100000000000000000000000000000000000000000000000000000000000000008000080000000000002000003800040000000000000000000004de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000080000040000000010400000000024010240030004008200000404200200000088000000100010000080010048000400008000000020000000005000040010000000820080400040010800000000000080000000204012040000010000000080c110800001000002000000000004400000020000010000000000000000000000000000000000000000001088080040000100000200000004088000000000000000200000000000004000000000000000000000000000000000000000000000000000000000000000000000000000004000000001000000000000000000000000000000000000000000000000000000000000000000000000000080000cde040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000001000000000000000000000800001000000000c2804000001000100000000020000000000000000000000000400004000000040002820800000010020000c000000000001000000000000000000000000000000000000000000935b0000000000000000000028000000000000800000000000020000040000000000000000001000000000000000800000000000000000000000004000000000000000020000822004800000000000000000020000004000000000100000000040000000000000000000000000000000000000000000000000020400000800000008000000000000000000100000000000000000000000000200000000000000002de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010000000000000000000000200000000000008000800002c0000002000001000004009008480008210048000000000200000000008000000001200000000000084000805040040000000080000045000002000001080000800400080000100000400000004000020000010400000400200000400830000000000000000000400000000100000100000000000010000000000801000000200000040000000000000000800021000000030000040100000800000000000020400000000002000000000000000820000022000000000251020000000000000000000000000000000100001c000000000000000000000000000000000000000000000000020000ade040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (410000000000000000000000000000000000000000000000000000000000000000010002008200000000000000000000000000000010000001200000000000000000000000000000000000000000004000000100000000000200000000000000000000000000000000000000000000000000bb970000400000000000000032040000000000400000040000131000000000000000000020820100400800040000c0000000000000002001000000c00000000004010000100200000840000080080010002100004080c801040010000120000000000000000000000000000000000000000800000000000020020000200000000000000000000000000040000000006de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000c000011000000000000000080000000000002000000000000000000000000000000000000000041248100000000040300000000000200500110018000000000000000400000000000148200000000001200000000004008003000000040208008800001008300040000000048000000000000003000000000000400005020000010000000102884000008000000000000000000000204000000000000000000000000209002200000100000000000000010800000000002000010080000080a000020002000000000800000400000000000000000000000000000000000000000042020000000000100000000000000000020020820000000000000000000ede040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000012000000000000000000000000000000000000000000000000020000000000000000080000000000000000000000000080000000020002000000000000000000000000000000000000000000000000000000000000008000000000000000001010000000000080000000000000000000000000000000000000000078ed0000000000000000000004010000000000000020000000000100040000000000040010000000400000000000000000000000000000000020800000000000800000000000002000000000001020000000000000000000000000000000000000000000000000000000000000000000000004920000000000144000001de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000001004800000000040000000000000000002000000000000000000400000000000000000000000000010000000000000000000000000000120000000000000800000000000100220000000000000000000000000008400240200c00000000000100100002008000800000000000030100000000000e0000000029010000000100020080000000000000011010000000000000000041090000400000000000020000000001900000000000000000800000021000000800000000000000800000010000000000080000000000000010000000000300000000000000000000000000300000000000000000000000000040020100000000000000000009de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000001000000010040000000000000000000000000000000000000000000000000000400000010000000000000000000000000000000004000000000000000000000000000000000202000180000084002080000080000060000001800000060000000000160000100004000060080001800000000000004020000000000000000000000000000000000000000000000069500000100000000000000404000000000000100000000002404000000000000000000000200800008000200010100000000000000000000008120000000008000800000000000100100000008200800200000008130000000000000c0000000000000000000000000005de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000600080000000000000000000180000000000000000000020000000000200000000000004100020000000000000c004000040000000000000000000c0000000000260000000001000000000800000000002000040000000000000040004100000040800004440800040001004000000002000800800004800004000a0000400000008000140000000180080108000100000400084080000000800000000c1000009901800048060060080000022080000040000000005000001002000a000000000600800400604050100000000000600000004018108600018018600440402000010110000000000000800000100000000180000140000000000000000000dde040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000010040000080000002100000000000000000000000000000000000000000000400000400000400000000000000000000000000000000000000000000000000000000000000000010000000000000040000000000404000c880000202000042000001004100004020000000000000000000000000000000000000000004002000000800000000000000000000000000000000100000000000000000000069c60000000000000080000002000000000000000001000000001000004100000040000000004000000000006000000000000080800800000000000000010000000000000000000024000010000003000000000800000020003de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000400000000002000800410000000000010200010001000000100100000004000000000000800000000000000000000000000000000044000000080000008001000000008000000000000000000000000000000000000800000000000000004000000000008310008000000000000000010040100000001000000200000000000021200004000008000020000000148004001040004000000100000000000004000000004100800000300002000008200000a100000000000000000050000000c310080000000000400400080000002040000000040000010900000209000000000000001000100000010000000000000000000400000000000000000000000bde040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000002004000400000000000000000040800000000000000800000402000000000000000000040000000400000000010021000000000000000020000080000022000080000000000000200000008000000000000000800000000000000000000000800000000000000000000000020000030800000020080420000010020800040400000000200000000000000000000000000000000040020010004010010040000000002000000000000001000000000000000000000b1200000002000000000000000000000000000000000000000400000000000000000000000100001004000000000000000480040001000005000000204004000000000000004007de040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000024000082020022080000000000020080804800000020c8800008080000048000482000082000001000400400000010000000000000000000000000040100002008200000002100000002410800080000410100000000010000000820002180002000000010004000004000000400020082000080000a00002000400200280000048102400002010480204200104004000404082021021108000c00100000c00000010401024004820800080880006020088000000c00100000890080002000804005000004008400000200432080082431004200090081050042004000000801000080002000002004400086000000000000000020c040048010000000fde040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (190810000000800800000080000010020020000802000040800024080000020000100000040000004000000000000100800004008000000200008000014000000000010110041000000000000000000000080000000000000000000000000000000000000000000000000800000000000000000000000008000000000000282002040000042281001282080000000000000000000000000000000400000000000000000000000000008000000000000004000000000002000008000000000000000000000000000000000000176900000080000000800400120000000800004800008000800108000000000000200002000800004020010004004030002000900003e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01009000020000000000100040000000000000000000000800a1000100000002000000000000810000100020802040000010000080010000000000000000040000001000000000000008080000000004000000800000100000000028008010004108000000004104000200000100000008200000200828000000100000000000000004000000a08000000891800488004004000220208300010000088200b040200040002000000010081080289200100002001004104800000001000400000000001814000000020010060001000201a008002002034000918110010030280400000021000104200400030020814800800800000000800028040a80020000200083e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000008000100000008040200000000209200000000008008000020000000000200000009000020020000a0000000000000000000000000000000000000000000800000000000000000000048000008000000000000000000000000000000200000000000000800020000000000000000000000000000000000000000000000000000003000000000140000000000001200000008000001041200200020000080000000000000000000000000000000000000000000000000008000000000010000010010000000000008800000000000000000000000000000000000cd7e00000000000000000000500000000000010000000000001140000000000100000043e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08000008040001049005000000208002000002000000200000000100000140300000000100000000080000008080008200000000080000204008000000000000000000002004a8400000000031200010000000000000000000000000000000000000000500000000020800002000000004000000000200000000000000000000000000000000000400000000000000000000000000180000000000000000430000080400000000000000000100080000800500000020100001010000000724020308004000000020480000000080408202000208290400080280002002000000000200000018008008000800000004040800004048010000002000200000000000c3e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (28082000000285000009240000000000000000000c00093144100000000080000000200000c701400000000000040000000010000c1000010080000040000400000001000010400000000000400000000080010000000800000028a02000800202800200000000021000000000000000000020000004000000000000000000000000000000000000000000000000000000000000000000800000000424000000000818040108001008010040008041000084004002c00000000000000000000000000000040000020001000000002000000000000800001000000100000000000000000000000000000000000000000080fc00000000000000000400000000000023e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000ac99000000000000000000001000000000000000100004104110800000000000000000001c000e000000000000000000010000000000000010080080010000000002000010000000000000000000002000000000400008000000000001000000080000002000000000000004000000000005000400000000100000000020030020000000000400080080000400000000000000000000000020030010000000000000000000100000800000000040000040100228028020034000020000c0010002840003001000000400200000020000002000000000b0000000000001004000040000030121401001010c0000003000000050440000200440008240140000a3e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000050000000000000000080000000400000000000280000000000000000000000000000000000200000000000000000000000000000008000800000000000020200000001000000000000000000001400000100000000000004000000000020100000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000001000000014040040000000000000800200000080008000001000000000000000000000000000000000000000010004000000000088002800000000000000000000000000000000000000000000063e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000059c6000000000000000000000001000000000000000010042000010000000000000000000000000000000000000000200c001004200080020000000000000000000000000000400000200a8008000000000000000800001400028001000020802000000000000000000000000000000000000000000080000000000000000000000000000000000000000001c00000000000000000000000000000000000000000000000000005c0000010000000000000400011406004215008100c00150200000000000000018001000000c00000400000002000002000000000000000000000000000000140400080000000e3e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000140000000000002000000000080000000000000000000000000020000000000000140000000000080200000000000000000000000000000000800080000000000000000000800000100000420000004010005000000400000000000000000000000028000000000000a0000000000502800000000000000000000000000000000000002000400000000000000000000000000000000140008000000000000000000000000000000000000000000000000000000000000002000000000000000000000000002000000a00200140000008000000000000000000c0000800000000000000000000000000400000000000004010000000000014120000000000013e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000020041400050000000000000000000000000000000000000000000012390000000000000000000000000000000000000000000040000080100000000000000080020000000000000000008002000000000000040000000000000000000000000004200800000008000000000000000000000002000000000000000050000000000000000000000000000000008000000001004000000000000000000000000000000000000000000000002802800000000000000000000000000000000000000000000002a000000005000080000822a0905001000000240000000000000000000000000200008840014000002800202800300000000093e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000000000000000002000000000000000a00000005028028002000000000080a00028000000000000000000000000000000200000000000000000000010000000000000000000001000000200080000000000000001008000000040000000000001000000000000800000000000000000000005000028000000000000a00140000000028005000140a0000000000000000000040000800000000000000000000000000000000700400000029000000000000000000000000000000000000000000000000000000008002000000a0000000000000002800200000000080000000000001000100004000000000002000500000000000000000000000100200053e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000200000000000000000000000402100000000084090000000002422290800200000000000000000000000000000000008000000000e05700000000000400000000000000800000000014020000000000002000000000000000000000000040000000000014010000000000000080074000000001800500000000040028000504022000000000000020020000000000000400000800000000000000000000000000000000501000000014000000000000400000000000000000000000000000000000000000000005000140a00000000000000000000000000000a00a00002028000000000080000000050810820240002000008404000000000000020100d3e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (149043201040001002040000000000000000824001100040800000080000100000000000002001000010200080040000800000002000200020000020000000000100000000808000402000100040802000000000000000000000000020100008000800000000000000040080002000001002000100000080012001002000000000000004000400020000200040000800004001000000000100040000802000000000000000000000000100000000000000000000000000000000028024002002000000000000000000000000000000000000000000000000000000000800400000080000000000000000000200008000000010000002000800000000000000040033e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000400000000000000006000080800000400000002000000000000000000000001020000000000840800000000020220020002000000000000000000000000000000000100000000009d4a00000000000100000000000000800000000008020000000000200c0000000000000200020000000000000000002800801000000200003002800000000080020000000002802810040082200040000000002802800000000a000200000800000000000000000000000000000000100800040004000020001000100000000000000000000000000000200000002010008001000080800000000000000000000000000000500000024004010004000100000504120000b3e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004000000200000100000000000008190100928000400020000400000000000000000200000000004000802000000000100000000000000000000010200000000000800000000000200020000040000000000200000000800000400000100060804000000000000000000000000060000008000800000000000000020100000000001000000080010200012000004000000000000004000400020000200040000800004000000000000100000000800000000000000000000000000000000000000000000000000000000000000024001002200000000000000000000000000000000000000000000000000000000000000000080000000000000000000200000073e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000713b00000000000000000000000000000000000008000804000000001000000000000000000200000000000000000008008000000000000020008000000000000200000000002008000004280000000000000088000000000008000000000000000000000000000000000000000000100800040004000002000000200000000000000000000000000000000000002010000001000080800000000000000000000000000000f3e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000002008000000000200200000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000200000000000000000000000000000000000000100400000800000000080000000000000000000000000000008000000000000000000000004000000200000000000000000000000000000000000000000000200000000000000001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000200000000000000000000000000000000000000000000000000000000000000be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000c00000000020020000000000c00800000000000000000000000000000000000000000000000000e0a7000000000000000000000000000000000000000000000000024004000000000000020000000000000000000000000040000010000000100000000000000000000000000100800000001000002000000000900100000810100000000000000000000000000000000000000000000000480400000000020000000000000000000000000000000000000000000040000000008be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000002000000010000000000000000000000000000000000000000000001000000000020200000000008001000802000c08a0000000000000000000000000000000000040004000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000200000001000800000000000000000000000000000000000000000000000000000020200000000000008000000000000000000000000000000000800000000000000000000040000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000004be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000003002002000000000000000000000000000000000000000000000000000000000000080040000000000000000000000100000000004000000800000000080000000000000c0000a100000000000000000000000000000240000000008009000000000242a2d000000000000000000000000000000000000000000000000070de00000000000000000000000000000000000000000000000000100000000000000000000100004000000000000000000000020000000004000000000000000000000000000000200010000000200000000004000000000004000000004000000000000000000000000000000000000004040000000000003000000000000000cbe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000000000000800100000000000000000000000000000a000800000000080000000000000000000000000000000000000001404801040140000040001004001405041011142080c0200028205000000000000000004000080000000400108002000002000000000200100000000008004000000400080200100000000000000000000000003000000200000400000000000000008000000000000000000000008000000000000000000000000000000400080000a000300000000000000c00000000000000000000000000100000040000004000001000020100000040000002000000000000000000c0200008002000000000000000000000000002be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000008000021000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000c18000000000030600000000000c182820000004000000000000000000000000000000000000000000000000915e000000000000000000000004000000000000000a00000a00014005000000000000010000000080200000000000200200000000000000300200a0000000800000000000030040020c008008004000000000000340a0421000800400008820200000000000000000000000000000abe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00800000100000000000000000000000000000000020000004000000800000100000000000000000000000000000000100000000000004000000000000000000000000000000000000010100000000000004000000000010028200000040000008000001000000000000000000008000000010000000000000000001000000000300040000800004001000020018000000000000000001000000000228000000000000008000001008000000000000000000000000000000200000840000000000000000000200000840000008000001000228000000000000001000000000300000000000004000000000000100000000000004000000000000000000000000006be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000003130000000000000000000000000000000067600000000000000000000000000000000b0b00000000000000000000000000000000000000000000000000000000000000002c2c0000000000000000000000007cc0000000007f300000000000f000000000000000000400000000000000000000eaea0000000003aba8000000000eaea18842110840c0c0000000000000000000000000080000c0000000000002ac6000000000000000000200000000000028000000000000a0800000100000000000000000000000000000002820000004000000800000000000000000000000000000000000012800000000000000000000000000020000004000000ebe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000c0c000000000030000400110840c8000000442100000000000000000000000000000000000160f00000000005831000000000000000000000000000000fffe00000000000000000000000000000000000000000000000000035700000000000d5c00000000009012026510008382400001660900000000000000d47c00002dc00000000000000000c0c00000000005af000000000016bc00000000000000000000003c0000000000000000102b4000000000000014405000000400000000000000000000000000000ead5c000000000000000000000009b3800000000025730000141400000000000000000000c4c000000000031300000000000c4c00001be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000004400000000000110000000000004400000000000110000000000000000000000000000000067400000000000000000000000000000000b0b00400000000000000000000000000000000000000000000000000000000000002c2c0000000000000000000000007fc0000000007f300000000000f200000000000000000400000000000000000000151500000000005454000000000151518842110840c0c00000000000000000000000000000000000000000000de5c000a3001050000000188000000000001884200000c000621084600000000000000000c00000000000000018842110840000000004000030300400000000c0c000000000010018800009be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (030300400000000c0c000000000000018c00000000c0c000000000031000400110840c00000004421000000000000000000000000000000000001f1d04000000007c710000000000000000000000000000007fff0000000001fffc000000000000000000000000000000000000005500400000000154000000000900008410082003e400000018c2000000000000001c44000055400000000400000000c0c000000000272700000000009c9c00000000000000040000003c000000000000000000ab4000000000000002a20000000400000000000000000000000000001e2c440000000000000000000001f6778000000007d97300006800a000000000000000005be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000005182200000004000000000000000020000000001010000000000000400000000000010000000000000400000000000000000000000005b400000000000000000000000000000000bef00000808000000000000000000000000000000000000000000000000000000000000000020200000000000000000000000004000000000000000000000000000000030300000000000000000000000001500000000005454000000000151500c52210a800000000202000000000000000000000000000000000000084f300000000000000000188000000000001884200000c000621084400000000000000000e0000000000000001884211084000000000000000dbe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000c52210880000000000000030300000808000000000020200030100800000000000000020200030300000210a8000000000842a000000000000000000000000000000000001003a000000000400100000000000000000000000000000000000000000000000000000000000000000000000000000000000000550000010000000000000400000550318001040000000000000000000000000000000000003be0001540000000000000000000020000000001010000000000000400827270000000000000000000000000000019800000000000004045a0c04000000000000000000000000000000000e1c00000000000000000000001461000003be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001060c4000000000000000000000029144000000000a42200000223200000000000000020000000001000800000000000020000000000000800000000000020000000000000000000000005b410000000000000000000000000000000b2f00000108000000000000000000000000000000000000000000000000000000000000000004200000000000000000000000000200000000000108000000000000000575700000000000000000000000c0ea0000000003aba8000000000eaea00856214ac000000000420000000000000000002068500000000000000cf89000000000000000000080000000000000c5200000000003148840000000000000000000000bbe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000002158c619000000000000000000000004200000000856210ac0000000000000030300000108000000000004200030000a3400000000000000420003030000031cac000000000c72b0000000000000000000000000000000000014052400000000500190000000000000000000000000000000000000000000000000000000000000000000000000000000000003570000000800000000000020003572c80200080000000005003000000000000000000000001c60901ff0001000000000000000020000000001000804000000000020105af000000000000000000002000000001980000000000000081290c0400000000000000000000000000000007be040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0080000044400000000804000000000000000000000100000110000000000004400002400000110000000000000000000000200110008080000000000000000000000000000000000000000000041110001040000004400000800000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000050000000000001600000000000000000000000000000000000000050000000000000000000000000000000000000000000000000000000000000000000000000000000000d71f010000a1244000000008040000100000085600fbe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010000000400404000000000000000000000000000000002000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000020000000000000000080000000000002000000000000080000000000580000000000000000000000002080000000000000000000000000000800000000000000000000000000000000000000000000000000020800000000000020000000000000000020000000020000000000000000000000000000000000000020000000000000220000000000005000000000000140000000800000000000000040000001000000004400000000000110000000000000000000000080110000007e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000004810000000000120000001000320000000000000120000000000004d8001010000000000000000208480008000000000000000000000000000000000000000010000000480000000000012000000000000000000000000000000000000000480000000000012000000000000480000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084e30087e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000005b0d0000000000000000000000000000000000000000000000100000002000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000001000000000000084000000000000000000000000004000000000000001000000000000040400000000000010002000000000080000000000000c00000000040600010000811000010800000003000000000001000000000000000000000000000000000000000000000000000000000000080000048100020000000000000000000048000000000a0120000800000064800000000047e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000100000000000000000000000000000000000000000000040000000080000000080400000000000001002000000000000001000010000000000000000004100000102000000000000000000000000000000000000000000000000000000000000000000000000000000000000041000001040000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000b9400200000008004010000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000800000000000020000000000400800000000080000000000000000000000000020000000000000000400000000000000100000000000004002000000000020000000000000c0000000020000000800100800000900000000000010000000000000000000000000000000000000000000000020000000000000000000002000000010002000000000000000800000027e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000010400000000000400000000000000400000000000410400000000020411000000000000000000000020400000000000810000000000000000000000000010000000000001400000000000000000000000820400021000000800000000000000010000000080000002000008000400008000000010000000000000000000000000000000000000000400000000000010400000000000400000000000000000000000000000100000000000000000000000000000000000000000004000000000080000000000000000004000008202000080040002001000000000000000000000204000000000000000000000000000000000000000000000000000000a7e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000001223000000000000000000000000000000000000000000000002000000000040000000000000000000000000000000000000000800000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000082000000000000000000000000080000000000000000000000000000800000000000000000000000000200010000000000400000000010800000000000020000000010000000000000400020000000000000010000000000000000400000020000000000000020000067e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000100000000000000000000000000000800000000000020000000000000000000000c0100000000000000044000000000001000000000000000000000000001000000000000040000000000000000000000000800000000000001000000000104040004000003001000000030000004000000000001000000000800000c008000000000000000000000000000000000010000000000000400000000000011000000000000000000000000000000000000000000400200000000000000000000000000000000000000000000000000000000000000000000010000000000800000000000000000000008000000000000200000000000000000000e7e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (840a0014100014402d084100000000000000000000000000000000200a00000000000000000000000000000000000000000000000000000000000000000000000000000000008535000000000000000000000000000000000000000000000000000000003040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000084000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000004040000000000000000000000040000000000001000000000000000000000000000017e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000005001200000200002000000000000004080000012000000000040000000200021802a000000000400a800000000000000000000000400008020000000240028000000c0000000000000020000000000000a00090000011000000000000040010008000000000000000008010280000008090000000080000240a8000000000000000000000025028000000000000000004000000005000200000000000000000140028000040008020b4800000000002d824040000000160048200000000000000000000000000020000000000000000000000000000000000000000800000000004000000000000000000000001420410004404000100500010097e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000080000000000000208011020000000000001000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f490000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000a00000000000000000000000000140101000000000000100000208000000080000000000080000000000100420002000000008000004001403080000000050082000000000057e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000000000000000002001008200000000000200000002040000000004082000800000001000000000000000000800000000040208300000200200000000000000000000090200000000001010000000202000020400000000000000080040140a10404800800000080410000001002100000000010400000000040010800000000000000100c000400000000800000000040000000000000000000000000000000011600000000000000000000000000000000000000000000000000000002600000008001100840000000003028000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d7e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000016404400200000092100022084000000000000000000000000000050400000000000000000000200000000000000000000000000000000000000000000000000000000000000008e5b000000000000000000000000000000000000000000000080008802000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a2000000000000000008404000404000040004000800000000100000a010000000000400000002000000000000000000000037e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (04000000400000000000000000000000000100000400000449000000000005240100000000000000000000002240000000400020810010000000010000400000080000000000000000050600048840102000000000000000000000001800000000001040040040020018000000200000000000000000e4110001220000e0a0000068480000000000800001000000010200021300040000000100005056008007084008200000000000000000000000000200000000000000001008200004000000040000000000000000008000000000050620248400100010c1000122200000000904920000000000000000000000000000000000000000000000000000000000b7e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040024104000001400240080000040000002000000000000000000000000000080000000000000000000000200000000000000000000000000000000000000000000000000000000000000008a90000000000000000000000000000000000000000000000082011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000080440000000000000000000000000080000000000000000000000000805860000077e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000020000000a1000000010108000804008000002224000080400000900020408000000100400000100008000000004000200880000000000020000009000000020200030904010000000108000400000000000000000000020010848048800840000000000000000000006080000000200000000400001405020020000800000000008000005000420008000000830020800240040400000c00000020200010000020010000000000000008010408000008000000000000000000000000000000000000000000000004000000000000000008000000000000000000000000000010850049450450208c0800005010000000800008800000000000000000000f7e040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01220000000c800080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000080400000100000001042100101c02924100000012008204000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000009e0e00000000000000000000000000000000000000000000000200000400000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000008000000000000000000004400000000fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010000044000008000000000000200010008208000000000000000002008200040800000100000040000000002000080000200000022881000000080200000000002000001000000000400000000002008100000000002224000200000022800000000000208002300000001100100002c400000200080100000000000000000000000000000000880000048013040120080100040000001000201080124104424104004000000010000800000001000000008000080040000000100041010804a0440202200000010004002000000000000000000110000000000001000000000100002000000000000000000000102010080100000012cc000008100081228008fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0400000040000a005060205921650800000124040000000000801000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000004000000008200000010000800500240100100014048004000080100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000580c00000000000000000000000000000000000000000000000100000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000800000004900400000000000010000000000020000000000040000200000400000210110000000020000000600000000000410004000600000000088010000000000000000000000000000040000010a00000000000002000000000000000000000000002000100000000100005240100000a0000800000000000000000000000000000800000540000091090110010000000000000000000904224200000900020910020002002000000000028804240008c40000001404820000000010020040a00910000120000000000000000000100000120800000000000000880000000000000001000000000000000000cfe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0111100000000004000000000000000000000401000000000400401311404e1008000c0024000000001090000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000200000000120081000040008c00000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000e56a00000000000000000000000000000000000000000000000000240100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000002010000000000000000000000001000080000000800000000000000000100000200000000010000000000000c000800000090000000000100080000000004000000000000000400000800004000000000000000802000000000010800000000000000000000000000000000001201000000010008000000000000001000000000086c0000020000100184002001002800200000000010104440000400d8000928000016000000000000044000100000001a0004480280008000080400000b114000000020080020000000000000200000000080000000000000afe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000001001860000002000002008000000000000000000000000000000000000100000000000000048000000000010040000000080008600100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000140800000000000000400020000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d2f00000000000000000000000000000000000000000000000004000000000000000000000000000000000020000000000000000000000000000000006fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000004000600000000200000a002000000000000000000001800000a00000000001008000000001100200108000000000614410000000000820000000000000020000000000000000000000000000001140000008000000001048000000200000000000000006000000000000880000000000000000000000040a00040002000004000000000004800080000000000000800800000820800000090000000000000304220800001220000000000000100000000000000000000000000100800001000000000000efe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00010400400010004000c0011000000800000800000000010000000000000040000000000000000000000000000000000000000010000010000000002000000004001100002000000404000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400008008a200340008300000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000156f00002000000000000000080000000000000000000000000000000000000000000000000000010000001fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000010000000000000000000000000000200000000000008800000000000000000000000000000000000000000000000000000000000000000200000000000008000000000080000000000000000000020800040040000000000000000000000004000000000002100000400400003000521002014000000840010000000010400000000000000400001000000000000000000000080004002400000002000000000040010000010000000000000000048040802000000000000000000000000000000000000000040000002000000204000000000000000000080100002000000080108010008000000000008000208000000100004000000284009fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000000400402400002020000000105014000000000000000002000009083000000000000000000000200000000000000080000000000040000000000000000000000000000100000100000000040000000040001000041000002841040800080021000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000010400400010400000204010010000048000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000f55c00000000000000000000000000000000000000000000005fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000010004000000000000020000000000800400000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400000000000000000800400080000040000000000000000000100000410410000010000a0020101020025000005000000090000401080020001000043000000800000200000000000080000000102005040024000010000001040008000400004400002000000000003002088080000200010000000000000820000010004000000402000080000040100000000000020000012000080000000080000409001000400dfe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (41800840000201200000000000400004100200000000000a008040000400001801938020008102004000000001844020000000040000040046000000006000000000000800002000000000000000000000000008008000000000000009008000000000001000000000002000010000010000000500000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000010010000004000500000000300000000000000000000000400000410000000000000000000000000000000000000000400000000000000000000000000000000000000005f3b00000000003fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000009d3e000000000000000000000000000000000000000000000004000200000001000004000000000000100000000010000000000000400000000000010000000000000000000001080000000000000000000000040001010000000000000400000000000900000000000000080100000000000000000080000082000000040000000041008200000080208088040001004002008000048a2800000016820800000001000100041000022000000000000800008600240020a00420020000000400000000000220000200000000000000000a100000000000000000000001000000000000000001002000400100000000000400000400bfe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000430000000080103010000000000300024001102601ec000000020072000a8200010ce041008000802834002000800100d20810000000000000100000918009002800000300000000200000000200080000300000000200001c4000400000003000000000000000000000000080000000000850fd20100000000032004001040001c8000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c000000000000000000000001040000000000013300011000000000000000000000000000040000081000000400000000000000000000000000000000040000000000000000007fe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000b4f8000000000000000000000000000000000000000020800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002080000000000000000000000000000000000000000000000000000000000810000000000000000000000080004000000000000000020400001045000000000000000004000000000000000000000000000201080800001000043000000000410000000000000090420000010400080004000040000000000000000000000200000000000000000200001000000080040300004000000801010000000ffe040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (080000000000000000020500008001400000000010000014004814000410000004014004224005030c0000c000001430004030482000000d00054000000000000208010500000428504009000000a000104000204100000000000000840003000040000000000080008000010000000400000000000000040040000000000002a1004000000030800400c0000000100002000004000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010050004020020800c4200040000002008000080800000000000000000000000000000000000000000000000000000000001040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a1b90000100000000000000004000000000000000000082000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000400010000000000000000000000000008102081000000000400000000000800000000400000410000210008001040000080200040002000080801200000813080008c8208100300a1820800000002000000030c00021000c00004102970034080000000028020c00000c00030c05015030000c000000000000000080000801040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000001000000000000000000000488a80002020000000000000e000000000000000000000000000000000004000008000000000000000080000402000000000000b04000004000000000000000000000000000000008000900050000404000000900000a8000005000140200000000000000008000000040400000000000000000000000000000000000000000030005000000400010000001102830002000050000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000004000001004000000005088360020000081808001800040000000000000000000000401040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (502000300006000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000389a000000000000000000000000000000000000000000200000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001040000000000040000000000000c000000000000000400002000200100200040008018000000500000000000010014020018000202000000014000000000000500000000000000000000000000402001c0000000000008000000c01040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000802094000000088022d000000000000000000000000000000000000000028040200002000140000000000000000000000000000000000000000000200000000000000000000000840140004000008004000000008000000000000000000000028000000000000000080200c20040000400028000000000000000000000000000003000000000000000000000000000000000000000000000000008000000000000062005400460100000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000c04408250000008220c1b6d0000201040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000080000000000000000000100000000000000000000000000000000000000000000000000040014000000000000000000000000000000000000000000000000000000000000000000000000000000000000b8e70000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001040000080000000000000000000300002001000000008c000000008005120003000100225000140028010b4400000024002d0000000050014000000000000100000000000000000000000a01040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000140000028000000000000000000000000028002000000000000000080080000000000000000000000000000000000340000000008800000000000000000000000000000000000000000008000400100000000000000000000000400000408082000000202000000000000000000000000000000000000200040000000000800008002000000100000000000800000000000000010000000000600000000000000000000000000000000000000000000000000000000200040000000040006000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000601040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000800000010024010102102112428086084c86000220001022400000000000000000000000000020008000000000000000000000000000000000000000000000000000000000000000000000000000000000000936900000000000000000000000000000000000000000000014000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020008000000000000000000000000000000100408000000000010000000000004000a000801000000000000100080040004008000000000000000e01040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (192102401286185184044046182102100000800040084008040001000100000000000000008020001000102200104084084028052102102100000000000080000000000000000820002004c80800200008000000000000000000000000000000002000000004020000000000000001201020048032000200000000210000000800000000000000000000001000080000000200010000021000248020851000200004020000000000000001000400000000000000000000000000000000000400000000000000000100000000028428a011250240100200080202000000000000000000000000000000000000000000000000000000000000000000000000000000101040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000200000080008006026102002180006a86084086000200102902000000000000000000000000000060008000000000000000000000000000000000000000000000000000000000000000000000000000000000000db29000000000000000000000000000000000000000000800080004010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000410041000120400000000100840002008022021040000000900900000200004a11004001008018200901040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000800000000200002020204000800618200a10020048428508400408210210610000028806408400800200100010000000000000000800200100000240018408008400000a1021021000000000040800000000000000010000020040400000000080000000000000000000000000000000000002000080000000000000000006012080080240002001020000000200000000000000000000000000010000800180002000040400800006000000010002000000000000000000000000000000080000000000000000000000000000000000000000000010002000000000122408404000028000600050000000000000000000000000000000000000000000000501040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800020000000000000000024000000000800000024000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ff2f000000000000000000000000000000000000000000800080001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018080002040000000000840800000000021022000000d01040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001200000000000000000050004040000000000000000000000000000008000080000008000000000002000a00000020000000000000000080000000080200000000000000000000010020200000000000000000000000000000000000000000000000000000000000001008000400200000200000000000000000000000000000000000000000100004000000000000000002100940010000000000000080010000000000000000000000000000000000000000000000000000000010000080004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020080090000080c200000800008204000000301040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000112200080000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000082010000c00c00020000032030000000100080800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bd67000000000000000000000000000000000000000000000000004008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b01040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000020000000000c000000001003400000008080090000000002002000000000000808000020000020c20c00000100132030000000000c00c00000800000020000020100000000000000000000004080100000000000000030030020010000c00c000000000000200000000000000000100000082008000000000000000000000000000000000000000000000000000000000000000000000020000000000000801100000000000000000000000000000000000000000000008000000000000000008480100c00000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000701040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000030010c004308500004000020a040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000040024002002110c200a0284a84014028008122400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e83d000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f01040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000a0000300000840000000080090000200802042010000000008008000000002010122000400a40920021010014010844840200100021061002008080040800000400000000000000000000000000210000004003009000800840300400021021000002000040800000000000000c8030010000c0280020000004000000000000000000000000000000000000000004000000000000000080004002002300804000002040000000000000000000000000000000000000000300000000000000100b00002c8280000000100200000000000000010004000000400000000000000000081040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000010000000002000000008000000080000000000000000000000000000000000082282400008400000090000210002000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000004000148642514800005219094520000148e400001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000794000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000881040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000280000000030600000000000c1800200000043060000000000000c18280000000030614864251480c1852190945203001486425148000052390000040000008000001000000000000000000008000001000052190945200001486425148000052190000000000000000000010228000000000004000000000000200000000000000000000020008228000000000000001000000000228200000840000009000021008000040000000000000000020000000200000840000001000000000228240000840000001000000000000481040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000d8d8702014ec50040800000000000000000000003bc04000000000000000000000000000000063000000000000000037c0c00000000001010022000004010000000440100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b58000001303774d9137374e4ddd3644dcdd38372d440000000000000000000000000000030300000000000000000000000000000000000000000000000000000000000000000000000000000000000008c13600000000000000000000000000000000000000000000a00000000000000000000000000000000000000000000c81040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000073e02d88a00001555400000000055550000160801555400000000000555568280000015555303774d9155554e0ddd36440001383774d9100004e0dd60f0000000000583c000000000000000000000004c54100004c0ddd36440001383774d9100004e0dc00000000000000000007020804000000780000000000000000000000000000000000000000000444200000000000000000000005bab58ec6022b00000213180000000000000000000000000000000000014ec500804000000281040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000014ec503834000000000d8d8101014ec50343800000000000000000000003bc00000000000000000000000000000000063000000000000000037c0c000000000000000000080020000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003100000012038f718e050549ce3dc638141526388c400000000000000000000000000000030300000000000000000000000000000000000000000000000000000000000000000000000000000000000001f87000000000000000000000000000000000000000000000541000000a81040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000022018000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000073f01514000001a9a80000000006a6a00001f1001a9a8000000000006a6a003c000001a9a92038f718e6a6a498e3dc63800012638f718e0000498e3f1d04000000007c74100000000000000000000004c1600000480e3dc63800012638f718e0000498e2000000000000000000ff020844000000000000000000000000000000000000000000000000006744200000000000000000000005fab44da5c02b0000021297000000400000000681040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (3f9994e070000000001121cac00000000000000000000000080000000014837000000000202000000106d148b7000000000202000000000000000000000000000000000000000000000000000530000000000000000000000000202000fc000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004700000cd90c200c72050566308839c8000198c231e00000000000000000000000000000000000000808000000000000000000000000000000000000000000000000000000000000000000000000000002c54000000000000000000e81040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000a4000000000000000000000000000000000000000000000141140000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007fc1a0000001a80000000006a6a0000100001a9a8000000000006a6a78e9200001a9a990c200c726a6a66308031c9a9a998c200c72000066309003a000000000400e80000000000000000000000104aa000064308031c8000198c200c72000066308000000000000000000ffff0081200000000000000400000000000000000000000000000800006e852000000000000000000000000181040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000100000f05200000000000000020000007f9990835400000000112d5ac00000000080000000000000010000000014835400000000042000000581d548b5400000000042000000000000000000000000042000000000100000400000000530090000000000000000000000042000ec00c000000800000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002206400cd80c883064373761b221c990000186c88ca09000000000000000000000000000000000000108000000000000000000000000000000000000000000000000000000000000000981040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000c16200000000000000000000000000000000000000000000002ad8000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007d0441080301540000000005555000014006555540000000000055557839400001555580c883064555561b220c191555586c883064000061b234052400000000501490000000000000000000000181a90000603220c190000186c883064000061b22000000000000000000f36f00812100000000000000200000000010000000000000000581040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000001400000000000020000000000001100000800000044000800000001100010000010044000000008000000000000000044008000200000000000200010044000020000001140000000000000000000000000000000000000044000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000500000000000000000000000000000000000000000000000000000000000000000002000000000000580000000000016000000000000000000000000000000000000000500000000000000000000000000000000d81040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000815f0100000004000010000000000000000000000000000000000000000004005000000000000000000000000020000000000000000000000000000820000000000000000000800820000000000000820020000800020000000000000000000000000000000000000000000000000000800000000000000000000000000000208000000000000000000000000000000000000000400000000000009000000000000000000000000000000000000000200000000000408000001010010a004000104000584100000000000000000000000000000100381040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040208010000000000000000020048000008000001200000000000004000000000001200010000000000000000000801200000000020048000800008001200080000100048300000200000100000000180048000c00000001200000000000048000000000000000000000000000000000000000000000000000000000000000001200080000000000000000000000000000000000048000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000010000000000000400000000000010000000000000000000000000000000000000b81040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000282f00000000000000000000000000000000000000000000000000000000040000000000000060000000000000000000000800000010000000000040000000000000000000000000000000000000001000200000000000000000000000000000000400000400000000000000000000408400400000010000010000000000100400000000000000000000000000000000000000001000000000000410100000000000000000000000000000000000010000000000002400000010080091002000082000781040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000010000000000000000040000000000000000000000000000000000000000000000006000000000002000001000000010000030000000800000000000080000400000010000000000400000400130000001220000000020000000000000000000000000000000000000000000000000000800000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000f81040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000200000000000008000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ed5a02000000080000000000000000000000000000000000000000000000000000000000000000000000000000200000002000000004000000000000200000000000000000004008200000000000004000000004000200000000000000000000000100000100000000000000000000100100100000004000004000000000044000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000041040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000004000000000002100000000000200000000000008000000000000a00000000000108200100000000008000000000004000000000204100109100000020110000000004100000000000000100400000000100000000000004000000100000104200000000004000000000000400000000000004000000000000100000000000004200000000000000000000000000000000000000000000000000000000800000000100000000000000000000000000000000000000004000000000000000000000000000100000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000841040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000008000000000000200000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000cf2800000000000000100000000000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000008040000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000001000081000000441040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000002200000000400000400000000000010000000000000400000000000000000000000000000000000002000000000000008000000000000000000000000000000000000410200410400000080400000000010100000000000004000400000000100000000000004000000000000000000000000004000000000002000000000000004000000000600100000000000000400000000000000000000000004000000000001000000000000000002000000000000000000000200000000000000000000000000000200000000000100000000000000400000000000010000000000000000000000000000000000000000080000000000000000000000c41040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00020000000800a00000000000000000000000000000000000000000000000000000000001000000005004100028000b4006100004102d00430000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000829200000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000241040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000140804000000000000200000800000000000008000001000000000140104000000000000000000000010000000000005009000000000140000000000005009000001202b4220200000000008000000100014000000014802d80025000000000008000000100800004000c000002000000100028000800000800a8020000204000008a800028000a0000000000800000400000ca00f400480000080000010000000001c0000000000000000000000000a0000000000000000000000000000000000000000500800000000200000000000000000004000000016210400004802800000000000000000000000000000000000000000000000000000000a41040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000080000000000000000000010000000000000000000000000000000000000000000000000000100000000000000000001000410304000000210400c00011000000008000000000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000e606000000000000000000000000000000000000000000000000000000000000a0000000040000000000000000000000000000000000000000000014004000000000000000000000000000400000000500080000000000000000000000000000000000000000000000000000000000000000000000000000000000641040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000200000000000000000000000000003000004000000020000002000001000000000000001400000000004001000000000020000000000000000008000000024000000000008501005100000020000000000000900000000000000044000000000450000000000001040000000000000800000000000008000400000000000000008010000223031100000000011008005000422060940411000000000000003000800040000004000218000000001001000000000000000000001b0800002000000080000010000000000000040000000000000084000000000000000000000000100000204004a0010000000000828000000000001000e41040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000008a80001000000000000000000000000080000000000000000000000000000000000000000000082400000000000000000000000000000000000000000000000000000000000000000000012080002006000000000000000112484000000000000000000000000000101800400820000000000002000000000000000000000000000000000000000000000000000000000000000001a9800000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000040000000000000200000000000000000000000000008400000000000000000000000000000004000080000000141040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000200000220000000000000000000000000000000000000000000000000000804da0000020000280000040000000080000000000000000000000804c21000000000000000000000000000000000000124001000000847960000000000120040004000004100000000000000000000000001000000b0000000400000000000000020008000008000021800800000000888000000004803040010038100000000000440112580404f880000400000201000124802003151a001000000000400080100000410000000000000001104040202000002000002000400000000000000000000001008000000000000000000400000000000800941040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000040000001000082000002101000000000083000000000000080000000000000000000000000000000000000000000000000040000010000000000000000000000000000000000000000000000000000000000000000000000800000030c0000140000400020001000000000000000000000001000004000000000000000002000000000000000000000000000000000000000000000000000000000000000031b5000000000000000000000000800000000000000000000000000000000400000000000000000000000000000000000000000000000800000000080c0008010400000000000000000000000000000000008000000000541040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000040000000000000000000000000000000000000000000002000002000000000000000000000000008000000000000000000000000008000010020000000c2000048000000480000080000001000000000800000400000000040000000000000000000000000000001000000840001003090000000010000000001000800000000000004000000000840000000000000400000000000000800200000100000120000000100000200000000040009040003001000820000080801000024a400848000910000410080000000048200020000000000200010200800c08000000000000010000040000000010000000900200000000000000000000000d41040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000100000080000000000000800000000020000010000000000000000000000001000000040a240091000001000000000000000000000020000000000000000000000800000000000008000000000c0000000000000000000000000000000000000000000000000400000000400010000200000408410448000404100001210000000000000000000000000000000000020080020800000000000000000000000000000000000001000000000000000000000000000000000000000743e00000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000008000000010400000400341040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000002000000000c0000000210000000000000000000000000000002000001000000000000000000000000000000100000208000000000000000000000000000000000000000000020000000c00000800100000080000002000000000010010000041000000000c00000800000000000000000000000000008000020040000000000c0000000000002000000010000480000000100000000002004000010084080008112800001000800000000000000000000000412500002000001500052404200424284400308000104100400110040002c02208040100000008000084002482002020000000000000000200080000000000000000000100000c0040800b41040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000080000000030000000000124800008000000000000000000000c00000000000000000000000000000000000000000000000000000000000021100800000000000000000000000000000000000000200000000000000000000000000001040400000014000000000000000000000000000000000000000000000000000000000000000008001000100029800008200000000000000000000000000000000000000200000000000000000000400000000000000000000000000000000000000000000000000000000000000000902300000000000000000000000020000000000000000000000000000000000040000000000000000000000000000000000000741040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000490100000000000000000000000000000000000010400000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000004801400000000000000000000000000010010000000000000000000800000000000000000000000000000000000000000800000000004821000000000020000020000000801000000000000000000000000000404800400000800008000000000000020324000800000000020080020030800000c00000000001400001040000104200100000000a230000010000000000048100048000000000000200000000f41040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000208110040000000001e4000000000001010080000000000000000000012000000000000000040000000000000000000000040000000000000000000000000000000000000001000020000000080000000000000000000000000000000000000000000000000000000000000001000120000008000000000000000000000000000000000000000000000000000000008000400008000000030010000000000c00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000d5e30000000000000000000000000000000000000000000000000000000000c0000c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000200200000000000000000000000000000000000000000000000000000101010000420000000000000000000000000000004010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000240000000000000000000000000000000000000000001010000000000000000000000000000000000000040000800000001010020800040040000000200003000800000800000000000000001a000000040000c00000000000000000001000000d40000000000060000000008000d000000000000201800000000007010000000000201000000004000008c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40241008010068c00400018000000000020008000800000040000800400840000000000002000000010080000000000000000000000000000000060000200000000000000000000008000000000000500000000004000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000002002000000000000000000000000000000000000880080000000004000000008000400480010000040000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000b01000000000000000000000000004c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000063ee00000800000000000000000000000080000000002002000080000000000002000000001008080000010088000000000000000002000000000008000000008000000000000010000000400000000000000000010000000000000000000000000000002000000000000000000000000000000000000000000000000000088080000000420000010080000000000040048000180208000000000000000200000000000000006006000008000000000000000180010002000006000000000180000000006000000002000080008006000000000300200c4000008000000000821000000004080028800400080002500000000000000040000002000000cc1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (400000000000024800000000400202094000080430000800000280080400000480000000080000000c9240000308000400000000000000810000001000000000000000000000000000000000000000000000000800004000000008000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000402000000000000000000004004000000000000000000000020020000000000100000000000001410000040000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000078b00000000000000000000008000000000000200000000000000000008008300000100200001000000000000000000000000000000000000001000000000000800000000000208000200000008200008000000008000000000000000008000000000000000000000000000000000000000004000000000000000000000010008000000000000001010000020000100000000000000000080000008080000000000000080000000000000082000000000000000000000000000000000010000000010000000000000000010020020010100000004000400000001200000000001000000100000010000000ac1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000c0000800104000000080008002100222200010228000040800010000802040610001000408008400219041004010809023008800002a100024c00000c30180c00080002020022004802005000000000000000000040000000000004000000000000002008000000000000004400200000208000000000004000000020800001040000000000000000000000000000000000000000000000000000000000000000000000000000804000000000000000000000000000000000000000000000000000000008000000000200200004208000020000010000000900000080000000000000000000000000000400000000000000000000000000000000000000006c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000005c8f000010000000000000000400000000000000000000000000000000000008000008000000000000000080000000000000000000000000000040000000000000000000000040080000001000004100000000000080000000000000000104000000000001000000000000000000000000000800000000000000008000002080041000000000000002000008000000040a000000082000810c3080441004000000000000000000000000210000080000401080002000802098400082000402080402480000082000000000002a050004400000430040100000ec1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000400008010010100405000400000000000000000010000002000000002020000000000a8020882000409a04a4000920002801000204001501a8084200000001418000630018008230000000041001000000002000008000000000000000004080041002000000041080004000000000000400000000010000000000000010000400000010000000000008000000000000000820000002000000000000000000000000000000000000000002000000000000000000000000000810000000000000000000000000012000000000000080000020020000008002000001200000000000000000000008000000000000100000000000000000000000000000010001c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000bc3e00000000000000000000060000000000001000000000000001000040041080000002000000000000000010001000000000000040000000000000000000002000000000011080001000000042000040000000040001000000000000090400000000000000000080000040000000000001000000000000008000800000000000000000000000000200000000010004100000000000049420820040400000000000800800000000002014420010000100008000000086000020000001000000100000042000009c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (a0814020c34000820000020800020844200a200000000000000001000010000000001233200100000000000010000018003000000009002006000000480003480040850400001010000101640000942000000c104800000000800000040000820d20106802002032000082002400c9048000040400410010000010a0040204000010000080000000100000000000080300000400000000000000000000000000000020808000000000000000010000000000000000000000000000000000002000000000000000000000400000010410000000000400000000000002000000000000880000000000000000000000100000201000002cc0001000200333008200005c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00200000400400400010200000000000000008000000000000000000000000000000002000000000000000000000000000000000000000040000000000000000000000000000000000000000a7de0000000000000000000000000000000000000000000000000000000000808000000000080000000000000000000000100000000000008208011c08000000108000000000000000000000000041030008000000000000000000000000000000000000040000008000000000000000000000000000000000000000200124008410000020000000000000000000000000000000000104111c31800410000000040040000001001000040000040804340010000000dc1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000010010001420000420d0040000000020000100012000000100000000014040000400000000004000000000408000010003448000000000000000000000001409040000000200000004c000408050020b0010320141000b0000080820400000001400002000010000000410000003044040c4280000010000040000110004080000400000000000000008023004000000000000400000002000a0010000020000000000000000200000000008004000000000008000000000001000000000000000000000000000000000002000000000000000000000000000200000400208000000000400000000000020000000000000400000000000000000001400003c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000008000000800400a00040080000800100008800400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fe210000000000000000000000000000004000000000100100004200000001000100000000000004000000004000200000100000008100002082040002000000004000280000000000000001400000000002000000000200000000000000000000000000100000000000008000000000000200000000000000400000000410008000000001000000000000000002208008000000000200000080008000000000040000bc1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000a0020004805400000000000000000000000000000800000000000020020800401000000000000004000800020000000020001800000000000002000880010001004000000000000000000000000000020000000000000001060000084002100c00000806000800000080000c048002004120000000000000000100000001004000000000000000000000040008000000000000040000001502d0100060000000000000000000000c000080002800000000000000000000000000000000400000080000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000007c1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8002000000000000000000000000000000000000000000000000000000000000000001000000000000041400014009000020000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000049ee000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022000000000000000000000000000000000000000000c000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200200028000000000000000000000000000000fc1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0250008000000000000000000000000000000000000000000000050050400000000000000000000000000000000001400100000000050050000000000000000000002001004020000000000000004000000200000000000000000000000000000000000000000000000024000800000000000000000000000080800040900000000100000008000000080008000000000000000001000040000080004000100000080000000400000000000000000c00c00100000100000000000000000000000000001002000000050000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000021040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000140140000000000000000000000000000000000000000000000000000000000000000000a00020002800008400068080000a000802000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000044d30000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000401002000000000000000000000000000000000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000400821040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000008008000140100000000000000000000000000000000000000000020008000000000000000000000000000000000000000a00000000000000000a00a00140000028001005068000a08048000000000000000000000000080000000000a00000000000000000000000000000000000000000000000200000200000000200000000000a000000040081000000000000000000000000000200000281000000000000040000080000000000000000000002000000100000000000000000000000000008000000000000000000000000000000000000000000000000088000000400000000000000000000000000000000000421040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00800000000000000000000000000000000000000000000000000000000000000000000084024000000000000000000000000000000000000000000000000000000000000000000040002000420809000425092008240000840400000000000000000000000000008020000000000000000000000000000000000000000000000000000000000000000000000000000000000000866a0000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000020004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c21040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000080088808004400000000000000000000000000000000000000000200088400001000000000000000000000000000000004000100020100108005004401004000100040020100004101080000000002001004100108040080040000400000000000000000000000000080002000800000000100804000100024000002010100000004000100012100004201122000000000000002000600048000500044000080020240100000002000000000000001005000040220000000000804000000000004000001004000080040000000000000000000000000000010080008000221040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000840040000000000000000000000000000000000000000000000000000000000000000000400010000000040000810080080400000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000009e3d0000000000000000000000000000000000000000000000000000004000800000000000000000000000000000000000000000000000000100148003002800000000000000000000000000001000000100040000000000000000a21040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000020001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500400480000000000000000000000000000000000000000000000900100000000000000000000000000000000000420010000010010a404404000004200100004020508804100000040000000001006000100000000000000000000000000000000000000000000000000000000000000000100000000000000000100000004100000029400000001198000000000000002010980002000800040000000000040000000000000000000000000002400000220000000000000000000000008000800004200200020000621040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01002000000000002000000000000000000000000000000000000000000000010200000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000020000000400002000000012080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000303c0000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000200108000004800000000000000000000e21040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000c008280080100000000000000000000000000000080000008001000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000200800400000000000000000000000000000000000020080000080088000000000002020000040000000000001000000000000000408080008021000000000000000000000000000000000000000000000000000000080000000000040000000000208000000000200010000000000200000000000000008000400000000000000000000000000000000000000000000000000004000000000000000000121040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (03000000000000008000000000000000000000000000000000000001000400200000000000000000000000000000000000000002000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000100008040010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000023b0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000921040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000102200020084000000000000000000000000000008000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000240000000000000000000000000000000000000000000000c002002000000000000000000000000000000000010200050200200801000400008010000008000000000200000000000000000000000080020200040000000000000000000000000000000080000000000000000000000000000000000000000000001000050000002002404000040000000000000000000000000000000000000000000000000002000521040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000c10000000000000000000000000080000000000000000500200a1400000000000000000000000000000000008000000000000000000000000000000000000000200800000010000000000000000000000000000000000000000000000000000000000000000000000000400a0000000000000000000000000000000000000000000000000000000000000008000000000440000200210041004400010840500000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000b1d50000000000000000000000000000000000000000000000000000004000400000000000d21040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000002000000000000000000000000000000000000000000000000000000020024003000000000000000000000000000000001004000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000d00a400080800000000000000000000000000000000000000000012012000c80d00000000000000000000000000000080000000002002002080000100100010000004000000080000100000000000000100010020204110004000000400000000000000000000000000000000000000000000000010000000a001050000c02000c0000008000000c83a080800000000000000002000321040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (800002100022804000000000000000000000800020000084000000900002000020820000080000000000000000800004000000000000000000000000020000004000000800002100000000000000000000000000000000020000084000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000001000028200000040000008000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006dc50000000000000000000000000000000000b21040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1ced000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000028200000040000000000000000000000000000000008000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000282000000400000000000000000000000000000000000000000000282000000400000000000000000000000000000000080000010000282000000400000080000010000002000000400000000000000100002000008400000000000200000000000000000000090000200000000400000000000090000200002280400000000000000721040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001000000006380000b104262000000000000063b18b1b1046620000000000000000001e060000011080c0000000538000000240002200000000000000003b3b004000000004000000000000000000019d1180000000003cef0000000000000000000000000000000000001000400000000000000000000000000000000000000000000000000000000000000000000003030040000000000000000000000000000000000000000000000000000000000000000000002d44b373700118b5220dc8000002d44b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f21040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000607e0000000000000000000000000000000000000000000000000000000303000000000000000000000000000000000000000000000000000000280402000000000000000000000000000000000000000445530000000000000000000000000000000000000000000000000000000000000000000000000000000000000006828160000000000000000000000000000000000000000000000006828160f00000000000000000000000000000000000004c54100003814131504000000004c5410a800000131505d0000000000000000000001110980200000000000000000000000000000000044000c000000000000a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000044000c000000000001000000001340010b167262000000000000013697b1b16766200000000000000000000060040011198c0000000538000000240004000000000000000000a0a004000000000000000000000000000019d11800000000038ad0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003030040000000000000000000000000000000000000000000000000000000000000000000000c4e305052011831220140000000c4e300000000000000000000000000000000040000000000000000000000000000000000000000000000008a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000e2a5000000000000000000000000000000000000000000000000000000030300000000000000000000000000000000000000000000000000000000006141000000000000000000000000000000000000008020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003c1f144000000000000000000000000000000000000000000000003c1f1d04000000000000000000000000000000000004c16000002894330580000000004c1603b800000130581900000000000000000000011108002000000000000004a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000002020000000000000000000000000840000000000000000000000005380000006ea6280800000000005381c00456ea7280800000000000000000000000080828000000005200000006f0002300000000000000000a0a000008080000000000000000000000016d1000000000003ce600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030300000808000000000000000000000000000000000000000000000000000000000000000011c2e000000100c7a100000000011c2e0000000000000000000000000000300000000000000000ca1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000030000000000000000000000000000000000000000000000000000000000000000000000000000000000000004356000000000000000000000000000000000000000000000000000000000000000808000000000000000000000000000000000000000000000002450002a0000000000000000000000000000000000000040a00000000000000000000000000000000000000000000000000000000000000000000000000000000000000078e93000000000000000000000000000000000000000000000000078e93003a000000000000000000000000000000000000104aa0000506d0412a800000000104aa000000000412a8000000002a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (6a400000000181a900000000070ea400000000000000fac0000000004000000000420100000000000000000000000860100000000000800000000004620100000f2720080000000000420d58b010f27210800000000000000000000000010d2c000000005220100006f0102102400000000000003b3b000001080000000000000000000000016d1000000000003dee000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000303000001080000000000000000000000000000000000000000000000000000000000000000089a900000010032a34000000000cba90000000000aa1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (04800000000000000000000000000000000000000000000000000020000000800000000000000000000000000000000000000020000000000000000000000000000000000000000002120000000000000000000000000000000000000000000000000000000000000001080000000000000000000000000000000000000000000000102b640434000000000000000000000000000000000000a929000000000000000000000000000000000000000000000000000000000000000000000000000000000000000783954002400000000000000000000000000000000000000000000783954052400000000000000000000000000000000000181a9000050a9660006a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000800000000000000000000000000000000000000000000000000000440000000000011000000000000000000000000011000000000000440400000000011000000000000000000010001011000000000000440000002000111000100200104444008100000000000000000004440000200000000000000000000000000000000000000000000000001000000000000008000000000000000000000000000000000000000000000000000000000000000080000000000016002000000800800020000000000000000008000000000000000000000000000000000000020000000000000020800800020020000000000000000ea1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000010040000400000000000000000000000000000000001000000000000000000000000000000000000000000558500000008000000000000200000000000000000000400000000000000002000000000000000000000000000008000000000000200000000000010000000000000000000000200200000008000000200000000000008008000000000a0000000000000800000000000020000000000020800000000000000000000000000000000000000000210000000000008000000000000000000000000000000000000000000000000001a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000020000000000000000000060018001800000000000000000000000000000000000000000000000000048400000000000000000010000001c0000000000000000000000004b00000100000000000008000004800000020000120000000000004800010030000000000000000000000000000000000000000000004800000000000010000000000000000000000000000000000000000000000010000000400000000000000000000000008000000000004000000000000100000000000000000000000000000000000000000000000000000000000000000000000000200000009a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000204008000100200000000000000020000000000000000000000000000000000000000000000000000400008000000200000000000000000000000000000000000000000000000000000000000000000000000000000c5830000004000000000000100000000000000000000000000000000000040040000000000000000000000000004000000000000100000000000000400000000000000000000000000000000800041100000001000004000000000000110001000000004000000000000100000000000024000000000000000000000000000000000000000001008000000000040000000000000005a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000010000000420000000000000000000000000000000000000000000080000000000000000010000010020010400400c100000000000000000004000000200000000000000000000000000000000002000000000000000000000000000020000000000000000004000000100000000000000000000000000800000000000000000000000000001000000400800010000000000000000000000000000da1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000080000000000000000000000000000000000100200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000200000000000000000000000000000000000000000551e0000000000000000000000000000000000000000020000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000040020000000000020800000000800000001000000000000000800000000000000000000000000000000000000000000000000000000000000000000003a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008000000000000000000000000000000000000040002000000000000080000000000000000000000000000000000000000000000000000000000000020040000000000000000000000000000000000000000000000000000000000000000000000000000000080040000000000040000000000000000000000000000000000000000000000000000040000000001000080000000000040000000000001000000000000040000000000000000000000000000000000004000000000000000040000000000000000000000000001001000200200000000000000000000000000000240000000000000000000000000000000000000080002000000002000000000ba1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f400000008000000000000200000000000000000000000000000000000001000020000000000000000000000008000000080000200000000000000000000800000000000000000000000000000000200000000000008000000000000a0000001000000800000000000020000000000007a1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000004000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000200000000000000000000000000000000000000000000000000000040000000000001100000000000000000000000001000000003000040000000000001000000000000000000000000001000000000000040000000000001000080000000040000000000000000000000000040000000000000000000000000000000000000024000000000000000004000200800000000000000000000000000000900000000000000000000000000fa1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000100000000000000000000000000000000000140003000020028000000000000000000000000000000000000008000000200000000000001000000000028020000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000002001400040000000000000000000000000400000000050009000000000000000000000000000000000000055bd000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000800000000000000000880000020000000000000000000000000000000000000000000000000000c00000020000061040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000502010000000000000000000000500db4002020000806000000000020400000000008800000000000000000000001200000000000000005009100000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000020200a002000000000800000000000000800008000200000000000000000000200001000280000000040001600280002400280a0000800200a00000000300000008080020000400000000041000000000020000a00000000002000000000000000140800000000000000000000000000000000000000000000004000000000861040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (200000000000040000000400400000000000000000000000000000000000000000000000000000000000010000000002400000040440000000000000000000000000000010000000400400000000000000000000000204000000000000000000000000000000000000000000000000000000800000000000000000000000002000000000000000000000000400000000000000008000000000000000000000000200400000000000000000000000000000000000cc85000000000000000000005000200000000000040000000000000000000000000800000000000000000000000000000000040005020800004000000000000100000008000000000000001000461040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000020000002000000004000400000010000010400000820000000000404000000000000000000000002080090000000292880800000000084030000000000000000000000000200000000100082000000000000202000000000000000000080000000000000000000000000000000000100000000000100000000000000001000000000000000000000000000000000000000010000000000008000000000000000000030800300000000000000400000000001000000000000000000101000204000081080000104002100002108400012000020000012000000002100000000000000002100000000000000000000000008000000050000020000108000000c61040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000008000000008061100000000000080000184000000002000000010020000000000000000000000002000000c0000008100008200000200000000000000000004000121221800000000000000000000000000000000400000000000010000008000000204000008000002000000000000000000000400000000002000000000000000000000000000000000080000000000000000000000000000008066b000000000020004000000000000000100000002080000000000000000000000000000000000006664000040000000000000000010800000000004000000000000000000000000000000000000000000000000000004a00000000000008440100000261040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (2210000000008044600000000201040000000000000010000000000090000000000080000000000000008000000008060600000000001248008400400318f4020001000121000000000801a0000002000000000000000000000000000000000120800400030805980000820000000000020000000000000000000000000c000000000000002000010000000000400000000100200000000000000000000000000000000000001040000000000001f010000000000000140000000000020020100020000000000000084000020000000400080c100004a000000200000a4040808100c4492060810820102b04a00040000000000001000002690402000000040000a61040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040000000000000000080004000000000000000000000080000800000000010000100000000000000000005000000804040020000000000000020000042820120000000000000000000000000000000000000000000120800000000000000000000000000000000000400000420400010000000004000000000180010000000000010000000000000400000000000000000000000000800000000000000000000000000000000000000000000020008001010000000000004100000000004008010000010000000000000000000000000000000000000000b69e001000000000000000002001400000004000100000000000000000000000000000000100000000661040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000001000000001000000000800000000000020000004018000002210801000000203000010000000620401010000082000000000800000000000000000020042010482101000000412000a400000000820488000000000000000000200000800000000000040000100000080002000000000000000000080000000000000000000000000000000000000000000100100000004000800004000000000000008000004000000000000000000000000000200010000010000000000000020000500002000000100200002400000000004000000000004040080004000000100000040010042054242202000100000000088904000000e61040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000240000810000008231040000000208c080000104000001080004002c000000001100000000000000000c010000002000004020101448000010c002908000040080002200000008000000000020200000000000200000208000008000000004080000000000031000002000000000000080000000000000021002000008200010000000242000081000008890040200000243000082000004000001000000200000000000000000000000000000000002000000200000000000000000000040c429208020004001084400020000084c0040080021088020000000000000000000000000000000000090cf000000000000000000002008001000002000081100161040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (800000000000000030000000000000018800000000000018401002000008090000000000080000000000420000801000030400000080000010000020080000214800402000025210000000020000000000000420000820010020821000880000205008440080008500100080000000000400000000000000200200000000000000010200400000000004000000000000000000000000000040000000000000000000000000000000000800000000400000000000000040000000000000000000000000000000000000000000040000000000402000008010000401110051000000000800000420000000c0000000900080010000040d000880010c010048004400961040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40000001000000000400400000000040000002001008404040000081082080010401042000000000000000000018009004000000000000000100040000000402000000000003001000000002061000a200000000050010000000000000000000408040000000000080000000000000000004000000820004900000500800200000000000000000000000000100000000420004200000014080000000000022110100000000000000000000080000004000000000000000000000000000000000000000000000000000000000000000000000100000014000008000004100000000012014100000016000000000000000000000000000000000000000af7d001000561040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000afd90000000000000000000000124840000000000001014000000008000400000000210000000000000000000000004800400000000524800000000010080010000000002000400000010441000000000104000000000000800410010000504041400001c121210500000200242400000000049410000000000000002000000000000000000000000000000000000000000104000000000004002000000000000000000000000400000000000000080000002000000000000000004000000000018000004000000000000000000012000000000000000000000040040001002410100014010000000050804200000000010000d61040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (5002000000800000008100100000000001000800000000020010100000000000800400000200020122000000001c0020900000017200000800000000000800010010000000000100000000000800001010000000040000000000000000020000101400000000020004000000100000040000842000000000000000000000000000000008001000800004000480c000000000000000010000000000000000000000002400080000000091000014000000100000000000012880010400000000000000000000000000000000000000000000000000000000000000000000000000000000000101800000400000000800000400000401080010004000000000000000361040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080000000020000000100000000000000000000000000000000000000000006fec00000020000000000000405008000000000040400280000000204000040000000000000000000400000000000100000000000404200029020000000400000000001100000040000002800000000400040000000000100000000000401000000000010300020001000504200001000000120000000400000000000000000000000000000004000000000000001000000000000000000000002000400000000000000000000800000000080000080000000000000000200002400000000000020000000000000000000000000002000000000000000000000000000000181000b61040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000200800000040002001003000002084058041004002000000004021040010023007160004100102060c08800000000004002000000000000000400000000000000000000004100000000000000000000000000800000084204002000001208000118000001000008400000000000000000001000000000000000000000000000000000000000000000210000000000140000000010010000400400000000004000000000800002a000000000080801000020001801000000800800020000100002105000000000804000000000000000000000000000000000000000000000000800000000000000080000000000000800000761040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000008400000010008008000000000000200000010000000000200001000000000000000000000000000000000019f700000000000000000000200000000400002000090000020000020000000000080000000000004000000000008000000000000200000000414000000020088208000080011080000005000010050014000000000008000000000000010000028000008c00100400200010000030002000400000000000008000000800802002000000000000180001000010080000000000000000000000000000180000000000040000000000000080000000000000000000000000000000000000000000020000000040000000000010000000f61040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000200000000000001001000000000000000000000000000000000100000000000400200008000008000000200000000205100000010200000004000000808000000100804000920000000800204820314000000820c008800201008000a00000000000001000000048001100000000000000000000000001100004000000100001400010000c840000000000000000000000010000880000000000000004000000000000000000000000001000000028000000000000000200000000000000000000000000000002000010401000000000000000600000000000400000008000040000000000000000000000000000000000000000000000000000000000000000e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000040000000000000000000000000000100000004000000000000080000000000000000000040004100100000000000000000000000000000000000018000000000000000000000000000000000000000020800000000000000040000000801000000000000000000000000000020000000800000000004100000100100000020001001000010001000000000000000000000000000000000000000840000000000000004000000000040000020000020000000000000000000040040000000000000000000000000000000000000000040000000000000001000000000000000000000040001000000000000000000000000000000000008e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000400000000000000000000000100000000000020000000000001000400000000000000000000000000000120100000000000000000000010004000404840024100029210810028800000000001220480a090004010008110484800000124190100a00080010410032042400c10a02100000000000000c00000030001200000000000000000000002002000080001010000000400010406200000084000200200000008c110000040000000000000014000000000000000000000000000000000001000000000800800020020000000000000000000080001084000000000000000000000000010041000000000000000440000420040001000010000004000004e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (200004040000000040001000000000002000000000000000000000001000000110100000000000000000000000000000000000004a018010000000001000000000000480000000000000000000000000000000000000f03000000000000000400000000400000400000000010000020000020000000000000000000000000000000400000000000000000040008000410000208020000000008100204000100400004004404004000410400000210008000400008008020000002400400400000110000030200004400000000000000008000000000008010300000000000000200000004280000000000001000000000000000040000000000000000000001000ce1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000800000000002000000000000000000000000000000000000040000000000c08000000000000000000000000042000082400500001000000020512002200200400804190c00100008014c0800881028040a404202501004000004000160800500c00000000008000000440908000000500040000000000010000000024000004100008100000000000480000000018000400000000210c000000000000000000000008000000000000000000000080001000010000020800000000000108000000000004000000000000001100000000000004420000000004040041008004000002e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000001001e000404002000002080000000000000000000000300090000000000000000000000000000000000000c4230000000000000000000000000004000000100004000000000000000000000104200000000000800200000000000000000200000005000000000000204000040001044240088040040a01000000010800000000000040001000000000001001000000200010000000050000000040401000010000000009401000080080000a008300000000000000000000000002000800000080000000ae1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (430000002000081043010000000000400000000000000000000000000000000000000201000000000000000000000000000000000000000040000000000000000000000004080000000000000000100000804000000008001c00000000200000008000010002000010040000000110000000000080000000020900404501000000013400800004830000800006010c0021400000000000000000000200010000000000400000020001080040000080200002008400000000000000800000000240000004000001000000000000000000000000000010010000000000000800000000810000090020880020000200008200000000004004000000000000040000006e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0001000000000008040000000000000000000410000004000001000210a000000000100000000000000002000000000400000000000000003000000000000000000000001000000000400000000000300008004100210200040440000008000004000000000008000000000000000000000000000000000000009eab000000c00000004021807805000400000000000000000000000000000000000020000020000000020804000100000021000007a600400004100200200100000000100000000000000200008042000200041040001001000000240430000010008211e084402000000002002180000000000200000000048000002000000000000000000000ee1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010000000000000000000000010030000001000c000200000000000000080000000000000000000000000000000010000000000001000000000000000000000000000000000000000000000000800000010000000000040000500000040000001000000040000000031000800020001001000000000000000220200000000000000100014008000300100401002b4100401010040000010003200401000002c0800090200000000000040000000401a4800000000000000000800404010000000c140000000448200004205000000300300000000000028000000000000200000000000000000010010000000000000200052a28208020100000100020000100001e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000010010000010000000000000000000000000020000002002002000800080080040080001c02002002000080000020060000000000002000000000000000000000000000000000000000000000000000000000000000000000000800200004000084018000004001c00600100000000004008804000000000000000000000000000000000000ce840000000000c000000c20020400000000000000000820000000000000010002000020401000000000020000000000000c000000308100000510010000810400000010000004004000000004400001010000000000028000a00008100000a0430020c00030000800000100800c300050008000009e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02c180b40a0028031801002002000000010000000000000000000000000000000000080000080005000000001000400000000000400000000000001000000000000000000000023000000000000500c00000000010002000000000100080000000000004000000000000000400000000028000000000a00000000017000000900000000000000000000000000000000000100000010010000000400004000000400810000400048420005000080000280400002202000000000000000c00c0000a00000000000000000003d000000400000042800000003490c400200284030a0000140005000000000008000e00150000000000000008000000000000000000005e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040050280000000000000000000000000000000000000001140140000040000000000000000000000000000040000800c94002000000056d000200020001b4801000000010c000800000000008008000000000000000000000000000000000000000000000000000000000000000000000000002000200800100225040000001009b440040002000080400000000000000000000000000000000000000015b2000000000000000c0000001201000800400000000020010000000002000000000000040000000000000000000004040048000000000008800800001800010028000000000800000000000048020000000000000000010000000000000000200a00de1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010100000000004000008000080020220010000001008800000000140000000000400000000000000000000000000000000014001002880000800011000800000000000020000000000400000000000000000000000000200800000000024030000000000c002000000000040a80000000000000000000000000000200100005000000028000000000000000080240200000000000000000a0000000001000000004000000000000024000800000000000002810400000001000000000820088000000803000000000000000044010000000000000000000000000002a000080000000000000004888000008800200085200800a00000000020000000000003e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (04100000000000000000000000000000000000000000000000001000000000000000000000000000000001001000000000000000000020000000000000000000001000000000000100000000000000004000000000000040000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000008000800040000000100000010010000002000000100000000000000000000000000000000000000000004113000000000000000000400010010004020940000000840a6d000000002011b4000000000000800000001000000000040008000000100040440094000200000082d000000004004b4000000000000800be1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00060018000000000200000000000014000000000000000000000040000000000000000000040000004000040000000200000000000080000000000000000000000000000000000200800000010005020160000000000480880000000008028000000000000000000000000012000000000800000000000010008000000000200000000000008000000000000000000000080000000000000000000140005000000000080000000000000180000000000020000000000200001020000100850000000000000000040000000600000000010002000140000000100000000000000000000020020000000000000000000002000000240100200018000080000000007e1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040220001005100402000084000000400120140100148002482040000000010110000000442444480000000110010000000000000000000000004001120140000020100000000000100800000000084024001400904a8618402402a10a1221001011850849840400121241060000000012012000000000000040000000000000000000000000000000000000000000000000000000022008000880300300401061061001010864862840400120821062000000000001000000000000000000000002e7500000000000000000000001001400000000000000010000000000000201000000000000000000000000000000000040004020000002901152000000200fe1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00400010000000090001402422444c0548448402804210210210240098408408400002200100240100040000402000004000080000200148005002408005000040090000000000404000000000000000000000000000000000040002044102000288a1220000000002801000000000210220000000000000400000000000210000000000400800000000040200000000004808000000000100010000000000000000000800020100040100004000400090008408803000000000000000404000000000080040000402000020000005000a000100000000020010200012001008240000880440004000882004000000000000008008000800a00000000000000000011040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000100080000000000000000000000000022000400100084020000000600080002415012020000240001000000010011000000040040640000000000000000000000000000000000000400010011000001010000000000210010000000000800400040218608128400808211218210000008408618400000400014a0000000005002000000000000000000000000000000000000000000000000000000000000000000000000000000140300800061060821000000841840840000040011166000000000000000000000000000000000002d7a00000000000000010030000000402100c04084084048092102102100c00c84084084000002000002001000811040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (021021000005840840840000000001020000000000040000240020010020110401854800840000821021021000000840840840000000011024000000000000000000800000000020001000800000800040002010020000000000a000000000000000000000000000000000002012008100000222202620000000000050000000001201600000000000000000000002200000000000044080000000000001200000000000008000000000000100000000000000000008000201000401000040004000900850000000000000000000008080000000002000600004000000000000044004000000000000040000200015041018240000000000004000082000000000411040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (02000004042200080000020000080000000000000000000004000000200000000000000000000000080000800000000020000030000000000800003000000000000000002000000000080000000000000000000000000000000000000000020004000000000000000000000000020000000000000000000000000000000000000200000000008000000000200000000040000000020001000000000000000000000000000000000000000000000000000000000000000000000024000000000000000800000000000000000000000000000120001000000000000000000000000000000000001a1f00000000000000080000000400000000184080084040042100c11040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002808800010010010000000000000000000000000000000000000002000400000000200040001000000008a000400004000000800000000000000000002000900000000020004000000002000400000000004020000000100000000000000000008001e0000000000000000000000000000000000000000000000000080204008000000000000280000000000000000000000000000000000000000000000000000000000000000004000000000101200000000000008000000000000000000000000000000000000000000200000000000002002028000000000000000000000000000000000000000000000000400800000000000100000000000000100000211040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0080000008005000000000002002000004000000000004081000040000000040040000000000000000002000040140000000000000000000000002400000000200000000000000040000240088000080000000000040040000000105001000000000040040000000000000000000000008000000000000000080000000000400800000000014010000000000c30530024000000c00c00000000030430000000090410800000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000020000000c10c00000000830830000000020400800000000000400000000000000000000000f18900000000000000a11040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000762800000000000000008008000000000000800030030000000000c00c00800000030030000000000000800000100000000080008002800200000402030030000000000c00c0000200003003000000000080080000010000400000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000100050000000000400000000000028000000000002000000000000000010000000000000400000000000000000000000000000000000080000000000000000000000000000000000000000000000000000000000000000000090000000000000000000000000000000000100000080000611040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000200032008000000210002000000c000081000000000000000020c8204200000203000000000000000000300200208012000000000000000014000000100b0000040001000408020001108000000440023020000000000000100040000024484800000001000000000000000000000000000000010200002800002000000000001009000000000a00a40014001000800840400100a2102100d0140108418404000004010200000000110100000000000000000000000000000000000000000000000000000000000000000000000100000002003000804400208a100c00c00084484000000010102000000000000000000e11040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (19094520306148e4000010c000000000000000000000000000000000f4c400000000000000010030001401402a009000800840080100021021012010000840840000100001020010004000000400400300004004082009000804840540080021021014014000840840080b000210240100040001002000800000280040000080001003000802000100020000000001000000000000000000000000000000000008020030040000800000010040000000028008000000000100000000000000000000000000000a00000000000010000000000a000000000000500400000000000001000000000000000a0000000000000200000400000000801240050050000000111040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000004000000000000002282000008400000010000000080000000000000000010000000002282000008400000010000000002280400000000000090000210080002400008000000000000000080000000000000000000000000002282000008400000080000010000080000001000040080000010c1800000000003060a000000000c1800000000000000000000000000000200000040000a00000000000c18000000000030600000000000c18521909452030614864251480c18521909452030614864000000c18000000000030000000000000000000000000000000000000000000000000000000000000000000000282000000430614864251480c185200911040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000006201c400855555303774d9155554e0ddd3645555538370442100000000000000000000000000000000000d860000000000000000000a08000001000052190945200001486425148000052190945200001486400000000028000000000000a0800000101005219094520000148642514800005219094520000148e400001000028000000000000008000001000028200000040000a08000001000028000000000000000000000000000000000000030600080000010c18280000000030600000000000c18000000000030000000000000c18000000000030600000000000c18000000000030600000000000c000000000000000000000000000000000000511040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000404000000000000000000000000000252a80f87c000000000000000000000000001a5a400000000000006a37806cf6c6c400000000040b10419000003d7d4000063b18f5f5000006202400000000000001b09004000000000000000000000000109c2d70b40400000002001000001000002820000000008801555500000000015554000000000555500000000000000000000000000000000110840c0c6310800000055550000000001555400000000055554c0ddd36455555383774d9155554e0ddd3645555538370000055550000000000000000000000000000000000000000000000000000000000000000000000000000d11040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000006215402085a9a92038f718e6a6a498e3dc639a9a926388442100000000000000000000000000000000000e61200000000000000000054104455300004c0ddd36440001383774d9100004e0ddd3644000138370000000001504000000000054100815340004c0ddd36440001383774d9100004e0ddd3644000138374455300001504000000000000000d420000000003000040000000400004000018810000000000000000000000000000000000155540000583c055556828000001555400000000055550000000000000000000000055550000000001555400000000055550000000001555400000000000311040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000006a6a0000000001a9a800000000000000000000000000000000000015150000000000000001000000000000693f4e4500000000000000000000400000025a5800000000000006a379f930ac6c400000000040b16726e00003cfcc000013697f3f30000062024000000000000000090040000000000000000000000007a89a4229004000000020000420010000028000000000104016a6a0000000001a9a80002000006a6a00000000000000000000000000000000110840c0c631080000006a6a0000000001a9a80000000006a6a480e3dc639a9a92638f718e6a6a498e3dc639a9a92638800006a6a0000000000000000000000000000000000000000b11040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000001a9a800000000000000000000000000000000000000000000000000000000000000000000e3a2000a801a990c200c726a6a66308031c9a9a998c20842a6a6a000000000000000000000000000000018b60031004100000000002201880200000480e3dc63800012638f718e0000498e3dc63800012638800000000088060000000002201850200000480e3dc63800012638f718e0000498e3dc638000126388802000000880600000000000000d4050000000000000400000000000000000188100000000000000000000000000000000001a9a800007c7416a6a003c000001a9a80000000006a6a000000000000000000000006a6a0000000001a9a800711040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00001a9a8000000000006a0000000001a9a80000000006a6a0000000001a9a80000000006a6a000000000000000000000000000000008080014540000000000000272380d278000000000000003030000000000000000002020000000ed1349320000000002020000006ea7a80800000000007381cf3000000082018000000000000000a800000808000000000000000000021558651380000000000000800010000002800404000008820006a0000000001a9a80000000006a6a00000000000000000000000000000000210a80c0c0314a020000006a0000000001a9a80000000006a6a64308031c9a9a998c200c726a6a66308031c9a9a998c2000006a6a0000f11040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (064555561b220c191555586c88000055550000000001555400000000000000000000000000000000000000000000000000000000000000000000e3a4004af015580c883064555561b220c191555586c88852b5555000000000000000000000000000000057fc00009004000000000141140040a000064308031c8000198c200c72000066308031c8000198c20000000005045000000000141140000a000064308031c8000198c200c72000066308031c8000198c20040a0000504500000000000000108a8000040010000a00000000408048000000910000000000000000000000000000000000001a80000400e86a6a78e9200001a9a80000000006a6a0000000091040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (555578394000015554000000000555500000000015554000000000c0550000000001555400000000055550000000001555400000000055550000000000000000000000000000000010800141000000000000004f83b4a154000000000020003030000000000000000000420000000e916260dc000000000420000000f1900080000000000460d5f500000001201c000000000000004000000010800000000000000000002385e217ac0000000040020000110000002800404000000420c05500000000015554080000000555500000000000000000000000000000000214ac0c0c02158420000c055000000000155540000000005555603220c191555586c88300891040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000200000000000008000000000000200000000000008008008000001610000000000050000000000001400400400000000000000000000000000002000052080000000001402000000000008000000000001400000000000058000000000001600000000000000000000000000000000000000000a25500000000000000000002ad8a9290000603220c190000186c883064000061b220c190000186c880000000000ab600000000002ad901294000603220c190000186c883064000061b220c190000186c88a929000000ab600000000000001094f0000000100808400000844004010000009100000000000000000000000000000000003015400005014900491040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000100000000000000000000000000000000000000010000020000000000000000800020000000000000000000000000000000000020000000000000000000000000000000000000000005020000000000000004000000000800000040000110000000000004400000000000110000000000000000000000000000000000000000000800010040110008000000000000000000100200000002000000000120000000000001000000004500000000000110000000000000000000200010110408000000000000000000000000000000000200000000000000000000000000000800000200200140000000000000000000000000000000000000000008000000000c91040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000400000000000010000000000000400000000000010000000000000400000000000010000000000000000000000000000002002000000000000000000000000000000000000000180000000000000040000400000000000000000000000000400000000000010000000000000000000000000000000000000000002c660000000000000000000020000000000000800000000000020000000000005800000000000020000000000000000000000000060000000000000000000000000000000000000000800000000000020000000000000000000000000000000000000002800000000000000000000000000080000000000000291040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000020000000000000000000000000000000000000000000000000000000000000000000000020000000000000000800000000010000000400000000400000000000000000000000000000000000200060000000000001800020000000041120000303000004080000000001120000000008004840040000008120400000000004a00000000001120180010000034800000000000000000000000000001800000000086000005840004800000000000000000000000000000000c00000120000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000004000000000000000000000000000000a91040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040080000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000004b600000000000000000000100000000000004400000000000100000000002004000000000000100000000000000000000000000110000030000000000000000000000000000000004000000001000100000040000000000000000000010060000000004400000691040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000004000000000000000000000000000000008000000020000000000000000040000000000000000000000000000000000000000000000000000000000000000020000040000001000000001000000000000010000000000000000000000200000000000000000000000000000010400002004800000100000010000400000000002000010010000008001000000000000080000000000800000040000000000400000040000000000000000000000000200000000000020000000240000000000000400000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000e91040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000008000000000000000000040000040000000001080000008010000000000000000000000000000000000000000000000820000000000420000000000000800000000000020000000000020800000000000420000000000010000000000000800000000000000000000200000000000000080000082000000000000080002004000800000000000000000000000000800000000000020000000000000000000000000000000000000000033c40000000000000000000000000000000001000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000020000191040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000080400000000402010000000000000000000000004000000000000290000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000010000000000000000000000000000020000080000000000000000000000000000000010000000000000900000000000010000000001000400040000000010000000080000400000000044010000000000000400000012000000002000000000000000000000000000000000000400000000000000000000000000080000000001010001040000000000000480040001002000000000000000000000991040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00001000000810000000060000000000000000000200000000100000000001000001000000000040000000000000020000000000060000000000000000000000000200000100000000000000000000000000000000000000000000000000000000000000010200000000000008000000000000200000000000000000002000000000000000000008000000000000200000080020000000000000000200000000000008000000000000200000000000000000000000000000000000000000418e0000000000000000000020000004004001900000000000024000000005000800000000000020000000000000000000000002020000000000000000000000000000591040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000822000000000000000000000000000000000000000000200000000200008000000000000000000000020000000000000808000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000002000000000000000000000040000000000000000000000000000000000200000000000000000000800000000000000000000000000080000000000010000000000400400010000000010000000a00000000020000012000000000000000000000002000010000000000000000000000000080000000000000000000000000000000000000000480000000001010000440000000000d91040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800000000000004002d0000000000000000000000490a800000000400000020000000800000000000000000000000000000000000000000014000000082802800000000000000000500000000000800000002000140904000000080000000000000140200000000000000000004002140008000008028000000004002a00000000000080000000000000000000000000000000000001000000000000000000000040000000140008000008028000000000200b4000000000000500c00000000000000000000000000000000000000b0870000000000000000000000000002002008080000000000002000000003000800000000000000000000000000000000391040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000b401010000000050080000000000000000000400050210400040000000000000080000011000080000000400000000050041000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000010000000000000000000000000000000000000000000000020000200000000800000000000000000000000000000000000000020000000000000002a00000800102000020000004002a0080080800000800020000000050000400000000000200000000280000000050000000000000080000000000000001400000000000000000000b91040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10000000000082040000040000000000000002000000000000002010008020040010000002000000000800200000001000000040030020801010000020000000000000140000000000010000004000004000001200800000000042801040000000200000000000000002000000000002010100000000000010001000000400000000400000110040000000004400000000100000020000004000000000000000000000000000000008020000000010010004000000000000000440200000000010000001100000010000000800010020000000000000000000000000000000000000170d0000000000000000000050010000000001401000001000000010000000791040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008040000000000000000000000000000100000000a040000000000021000040000000800040000000088040100400000000020400000008000010400040040000000000482000000000000000000400000080000001000042044000100001000801040000000000000000000000000000000000000000000000000000000000000000000000000000000000080000100000000000000000000004000000000000800000000000000000000000000000000000010800000420000000000200000000000000000000000000020110000040000000910228005040000400210010c0200000040000024000041000001000001000800200002080000000001000400f91040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00c60180e229000008000000000020000000018000000000000008061a84000000002000002020040000000000000002a0000000000000000040100900000000000000000800000000800000000000000000000000000000000000000000804400004100100090040000040000081800000000000400000000000000000000000200688000000008041800000000201a00000000008061000059019201900001a600400000000418010000800000000000000000041000000000020c004008200008a0010000000000000000412000610010000000010406080686100010012012400000000000000000000000000000000000009b670000000000000000001000051040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000072f9000000000001000000000000000000004080680180000002018180024c000804c20004000020310000000000000000000000000c00002200000000000000000000000000000000807820000000021a288000000000000000000010000000000000000880200000000010400000000000000400000000000080000000000000008000000000000000000000000000000000000010000001000000000000000000000000001000000100000020000008800000000000000001000000000000000180400000000000000200600001800080186000000002080e100004040a445000848020541000600024000000640000000200a4000080000800851040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (800490001030810000100201000002410008000000200841000000082140000020000000800002000008820008000010000000000000040820840000000040000001000000000000020000100001000020400210000040400221200000c20000400000000400020c000000200000000082000000000110010042000004000451000000040020042000000000005040000000020000000000000800000000080020004000144000800000000000120000000000004000000000000100000000000000000000000000000000000800004000000020000100000000000000000000000000100000000000000800001000000120000000000000000000000000000000451040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000023000000000000000000000000000000000000000000af5000000000000000000000008000000802080000000100002000000002004081000100000002004080004000000100000020000008000409000001000002288000000100008000080000000000002008200000080000000000020100008000000900050420880008000042840004200000122000000000000000000000000000080000000000000000000000000000000000000000000001000001000000000000041000000000000840000100000080000004000000000010100000040000200004008000000000022000000002000800000000000004000400000040810000110008200002000c51040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00100002000440200c00000020000900400040000400040040000000034000000000000400080020000300080040010000000000801040000000000000040c000040000000000800000000080000000000201220a00200408000020002000013005000000000000000000110410004a3000000000000040000081000000000440000c000004420803005400000000000024c104000000008080000000000800080000000010000020000000c00001000000010000000000000c0004100000031000000000000c010000000000200802000000000000000001040000100000040008042081040000600001000000040840000000000301000000040004c00000000251040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1000000000000000000000000000000000000000000000000000000000000000000000000000000000000a050000000000010000000020040820000040c00000000000010840000904004c240200200000300800000000000000000410000200040411008000040000010000000c200004100042100000000003080000000000000000000100000000000080000000421000000000008200080000000009000008000000200020000000000100000000000000000000000000000000000000080000024040000000000000001080000020800000000002100400082000000000000000000800000082000000008020000820000000000000042000400000100000a51040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000042000000000000000000000000020000000102000880000c000820020800008400000000000000101000020008000800004000000800054960000000010000000000000000000000000001000000000000000000000000000100000000000000800000000000000000000000120820800802040000000000c0000041080008800000000000005000200080000000040000004080041000100000000000000000800000000100000104020000000006800000000000104000000000000020000000000002000082000000800000000000020800000000000000000000000000000000000000000000000000000000104000010000054100000000000000000651040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000010000000000000400000000000001000000000000480000000000003010000000000440c0000000000000000000000000000000000000001796000000000000000000000000001000001000000000000000040000000004005080101000000002000000000000000000000000012080040400004000000100000000000000000000000000000000010400000100000000000000000000000040000100000100000000020200000000000120000000000000000020000000000200000000000000000000000000000000c00000000000000010000000000000000600000000000000000008000800000000000000000000000400000208000000000000e51040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000400008000100000000000000004000000000000100000000000804000040000035100008000004e44020000000000130920000100404000000080000100000040a048000100000200000000000000000008000000000131000000000000000000000009000000000000004002000000080000400002000048000000000000000100000200000024240000000000000000010000000200000000101000000000048000000000000002060000000000000000000000001000800000000000400000000001010020000000000400000000021010800000000480400020000012000000000000400000000000000000000000000000200151040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (01801880060000000000200000000000000000000800006000000000000080000001000000050000000080000000000080080000000000000020000000000000000000000000000000000000000030ae00000000000000000008400000000020010100000000000004000000020030100000020000404000000000000000000000800400000000080000040000020000001000000000000100000000000404000000000000000000000800000000000020000302a00000000008080000020000000a000010000000000000000000000000000000000000000000000000000000000000080000001000020000000000000041000000000000040000000000100000951040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000001000000040000400008000000000000000040100000000000000000066000000000020000000800000000902000020000020000000002100c000020000000a000100008400008288010018000002704000200080000200400010001682800600000002000100000220000000000080010000000000000000000000400800000008840000000208000008210000046c000011800805800105981808020000820080040000190000002000400900000000000000000001000000000000000000001001082000000000400000000000000000000000200000000000009000000000000000000000000100018008000002a0000080000010080000000551040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000100000000002002002402400400080000000090000000000000000000000000000800000000000000000000000802000000000000000000400410000000000400080000400000010410000000000000000000000000000000000000001487000000000000000000000000000000000080020008308002000000200040080000000020002004000080000000000000000000000000010000000000400000000000000000800080000000000002000000000000000000080000000000000000002081204012400000000000000000022000004000000000800001001000000000000080000000000000000000000000000000000000000800280000040000d51040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000200208000000000008000000200000008000000000000000200000340000008c0000000000010200000000000000100000000010000000014004000000000050800011010002000440012000400080000000000002000000000801000804000402000102000100000000100400008000000000000000000000002000000000000000000000400000000000000040000000000000000201010400000000000000000800400000000000000800000040004100000204000000000080000000000010100004000000000008000000000008001000000000018000000000020000000000000100000000000028100000000000351040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000208000000108200208001020000008008088208008200020004824004204820220900000020108000000000000000000000000000000000040000001000000020004000100200004010000220220000208020320040008208100320208000000000000000000000000000000000000001d96000000000000000000000000000000000000040004000000000000000400000000000000000000000000000000000000020001000000010000000000400000000004000000000000000000000000000100000100000000000000000000000000000000000000000000100100880800008000060020000800000000008000000010000000000000000000000000b51040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004008000000000001000000000000000000000000000000000000000000001000008400000000000000110000000400000000000040000100000000200100008004000000000000820000000000100000010040000440000000900010000020080002000886004402030432404900104a2100019000413000842048100092814400040008440000800800000508000600008000029002000020001010000000000000004000102000000080000000002480800082000002000a020000082200000000000085000000080a004000000000004304000204004000000040000000100020080002000000000090088200000810000000000040000040000000000000751040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000002080000000000400000000000000808000000100000080000080000000000000101800000080000200000000000008000000000000000000008008000000000000000800008001001020000040000000808000000000020400480410000a000020900000084000800000000000000000000000000000000000000000000000000f48f00000000000000000400000010000000000000902192000000000092430000400000400000010400000000000000000000000000000000001000000000100000000400030000000008000430430020004000004000000000000000004100100800000c311000000000280489040000010040002000000000100000f51040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0020020880040002000001002000040010000010400010001000000000000000000800001000840000000400000400100000060100010400000000000000000000000000400000000004000010000000000100000000000000000000000004004000000000210000000000002000102000000000142000000000010040200040000004000004000000200000202811004900100001000000004400120000408020000000020004690000000008100002000000000410200000000000000010010000100100000000000000b2000000002504000a00000000c0001042040100000000204000044000100040000000400004000000200000000010000000000000000d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00041400000000000000001000001000000000000200000020000040000040000000008808002080101c010020020000000000000801800824800020000404020000000000000820000000000000040040000000001000004000000000000200100000000008000000000024200004004100008000104100010000000000810030700000000000000000000000000000000000000000954104000000000000000000000000000000000040000200000000000100800000001004000000000000000000000000000000000000000000000800000000408000000000080000000010000000000000000000000000000000000000000000000000000a5080000000008d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0010000000010400404904410484000d2000000000040000000041000000000000000000242000000000000000000000000040040001000048000000080000080000000001000000000000000000400000000000000000000020000000000000000000000000000000000001000000000000000000014001010400000400003000100020000040a0001001000071040001040040001000083001031040000050281082000000024386001800000200008040200000000000009a02001c40000000010000000008200002080010000000020204200010000000080100000004800803192400006200001400400000000000000000200000004001080000000000004d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000204280021008000000800200000000000801040050000100000000000000020000000000000010040200000008420000000000040000000000000000000000000040000000000204008000000000008000000000240000000000000000000000000001000001000000000000000000000200000000000000000000008008200000000001000208000000048000000000000000000000000000000000000000000000000000000fd520000000000000000050030401000000001c080c000000004000001104100dc4000044000007100000100000000000000000002000000000000000000000040000000000b00000100800004304307200000000000000000cd1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040000020000000000000000000000000000000000000000000010408000010000200000000000000000000000010000000000040000400000020000000000000000000400000011000000000000000a00000000010040a08000000a000000002000000080001000004000000000000000280080000003000000000000080000000000000000001000000000001400010001400000c01050000040000000200000000400000000000000000000000000000000000000000282002041000000000000000000000000000000000000000000000000000001400000000002020000003120003080020000000000081040103041000000000015504052800800000002d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00004021000000000000000002088818804020010000000040e04038080004018000000000100100a0090000000000100c00000000010000000000000008003000000100000000003000000000000200000000000000000000000000200000000000000000080880000000002020000000000000000000000000000000000000000a000080000010000000000000170280000004d000000000000020000000008008002000000200000000000000000000000000000000000000780e040000000000000004000080000000000000110001000000000000000100000020000010000000000000000000000000010000000000c00000000000000000000140000000ad1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800000040000000d0000000004000000100010001800004800410260080000000000000000000000000000010140000020000009800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000002002300020010000000000008000003001101000000054000000000000000000000000000008000000000000000000000000000000000000020000000000000001000000004040020010001000e0180010000000004004000000000000000001008000100004000000004000280000000000000000000280000001004000000000000000000000180000000802000882020000010000800101006d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000028002020100005000000000100002228000000020000000000000002a202d0020008000000000000000000000a01020000000000000004001225000000034001b4000000004046d00000000000002200000000000000000000000000000000000000000000000000000000000020000000000000140140000000005000000000000000000000000000000000000000100000000005004028000a00140000000000a0000000000000000080000000000000000000000000000000000000000000000000000000000000945c00000000000000000040000800400800000000030000010000201020002000214804000000000f011000000000000000000000ed1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000080000002000000000000000000000000000008010002800000000000080010000800000000000020000008004000000000000000000000008008000402094000000044046d040000020005b000000000000000000000000000000000000000000000000000000000000000000000000000020004000100a000800008000010800100004010008028000240400000000000000000200000000008040a000000000000000000000000000000000400000000000000000200000000000280000000024200000000000800002802000110020000000000000090050000002000000000000050000000000000000000000000008000000000000000002000001d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000001000020000008000000040800440020200a0d000000000000001100000000001000000400000000000040000000000000000a00a800440000000000000000000000008000000000000000000000000000000000000000000000000094034000000000500800000000080020500500000500880020000000000000800000000000000000000000000000000000000000000000000000000000000000000000000002502800000000000000000020020000800002000800000000000000000000000000000000000cf7e0000000000000000000000200000030000009400400000000050100050051008009d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00009000000000800040000010028008000200000300080000000000000000000000100000020001280a00000010000028000000000000000000000800800b00001025000000001000000000000040000020008004000000000000000000004008000000000000000000000000000000000000000000000000000000000000000000000000000009003000000000000000000060202000000020002040040008008000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000004002080000000000000000400000000400000080280000000800200000001000000000000000000000000000000005d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (040001008001000000080040000000000000000200000001000000000000000000804000000020100024000204000200000000004028642a42a481400000000000000080888000a02200000020008000240001080200000000000084084990c9010210210110248408408402403210210210001000080024090000000000000800000000084024000000000200800000000090030900900000100820020000000000000800000000000000000000000000000000000010080000800100402000020004000002000080000400c00000000080008000020020200800000800a00000000000000000000000000000000000a451000000000000000080000000001000dd1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00006e340000000000000000800000100040240140802404802000400000008141118802a03004803200100040000000000000000802000200043000400140090040100000000400000028000002000004a01088610000000020240000000009009000120010618608405004211218a100c0098408418400000000000000000000000000000000000000000000000000000000000000000000008028000a01000020004800200880000000420048200200028008000000000000000020000000002000020000000000000000000000000000000000040000000000000000000000050011020451000420800000000010040010000000c0240100000001002240003d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0004040000000001000201000000000022000100000000000020000000000000000000000002000000000080000000000000008000000000000000140000000001000000004080885042008680000000000000000185001000201500000200010000020000000001000000000080080010086102002101100084084084024006102102100000002000040800000000001000000000000040040000000002000000000000400029001000001000200800000000000020000000000000000000000000000000000000000800000001000020000800040000020000800008000000000000800180000000006020000008006000000000000000000000000000000000bd1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000100000000000000000000000000000000000eeca0000000000000000802000200000020029000808000000800020000111218004800800008800020080000000000000000000000000044000000100010040200002000800000012000008000004600890210000000010060000000008800000000018408208405008a18a10210020028008408400000000000000000000000000000000000000000000000000000000000000000000080040001d0020000000400000100000000000100100100000800000000000000000000000800000001808000000000000000000000000000000000800000000000000000100000000400100000400020200000000007d1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800000030000000508000880000000000000020000000000000000000000000000002800000000000080000000000000000000000000000000004000000000000000014000000000000000000000000001000000000002200434010000000000000000000008000000100000000100000000040000800000000000000000000800800000000000002000000000000090000000000000000000200040000000000008000000000000000000000000000000000000080080020000000000000000000000000000000000000000000000000000000000000000040000020000000000000000000000000000000000004000000000000040000000801000000000fd1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8000100000000000000000010010000000000402000000000000000000000000000000000000a33d000000000000000100000000000000020000200400200000000000000000000000a0040020000000000000000000000000020000000000000000500000000000000000002000400008020000000800000000000000400000000000000000000800000000600000000000014000800000000000000000000000000000000000000000000000000000000000000000000000000000000040400000000000000080000000000080000200100002000100000000000000000000000000000000000000020000000000000000000000000000000000000000000000031040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000028000000000100000000000000000080000002202100000000000000200000040000010000000000000000000000000000000000000040000000000000000000000000400008080800000000000000000020000181005000000000000000000000000000800000800000000000000010000000000000000004002000000000c00c00000000030030000000000c00c00000000000900200000000004020000000000000000000000000000000000000080080008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000040400831040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00a080000040000280000000020000001001140140280000000000000000c040000002800b0080000000000000000000000000000000000052f3000000000000000000800000000020004800000000000000000000000000c0400008000011000000400000000000000000000000000080004000000000100000000004000000000000000010002404030000000000000900000000020024000000000930830000000010c20c00100000030430000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000040000000000000000000000000431040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000002000000000208000000000000000000000000000000000000000000000000000000000c0020200000020000000200000080040010000201000000000010020401000000000014040000800400000000000000000000000010000000000000000000000000000001000000000800200000400000001200410800800a00000000000000000050040800000000000010020321010020400000000000008010830404802002100001400084084020020002102100000000000240880000000000008000000000200a00000000000028000000000100b00010028000028280080a00000002000028000000000000000000000000000000000100000c31040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000008200000040000000000000000028200000000000a0800000100000000000000000000000000000000000186500000000000000000020000000401000800020010020000000000800000000000040040000002800a0000000000000000000000100041005000040080040000004000000080000001000004c000000810000000000000000000000080010000c0090028248408800008210a1008000000840840000000000000000000000000000000000000000000000000000000000000000000000800800000100002000000020004001000020c0004004000200480000000000231040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000008200000000000000000000000000000000000000200000000000000000000000008000000000000008000000000008001000000000228240000800208a09000020000228000000000008a08000021000228000000000200001000000010000000000000000000000000000228000000800000000000000008000000000000000008000021000028000000000204a09000001000000000000000000a08000001000028000000000000a0000000000002820000004000148642514800005219094520000148642514800000052390000040000a00000000000028200000040000a00000000000028200000040000a00000000000000000000000000000000a31040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (40c0c631080000030300400000000000010000000000000000000000000000000000000000400000000000010000000000001001840100c0c01000000003031884211000000063108442100000000000000000000000000000000000bd26000000000000000000008000001000028200000040000a00000000000028200000040000a08000001000000000000000000008000001010000000000000000000000000000028000000003060a080000010c18000000000030600000000000c18521909452030614864251480c005219094520000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a00000000631040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000bb210000000000000010d90000021216300011000848400000000000000000000000000044000000000000000000000000000000000000006300000000000000000000000002c3686200347440599010000000468420000000016ccbfe42100006a37800002a8c001000000000000000000000000000000000000006a378000000000000000000000000400000006c0c0000600880000043a800002fffc00100200000000000000000000000101fbde0000382200000000011ead80000000018842110840c0d303774d9100004e0ddd36440001383774d910000004e0dc110840000621080000000018842110840000621080000000018842110800e31040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (18842110840000621080000000018842110840c0c631080000030300400000000000010000000000000000000000000000000000000000400000000000010000000000001001800100c0c0100000000303188421100000006310844210000000000000000000000000000000000044b5000000000000000000000044600000015000208000000540000000010028008204400000a000c4600000000000000000000000044710002000000000000000000000000000028040000015554a0100800055550000000001555400000000055554c0ddd36455555383774d9100004e0ddd3644000000000000000000000000000000000000000000000000000000000000131040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000b08400000000000000008f0000084846300011002121000000000000000000000000000002000000000000040000000000000000000000006300000000000000000000000002c36862003474521040100000005704200000000092cb8182100006a3780000008c001000000000000000000000000000000000000006a37800000000000000000000000000000000000c0000200880000623a800002fefc21000000000000000000000000088007fbb8000028a200000000015e1000000000018842110840c0d2138f718e0000498e3dc63800012638f718e000000498e2110840000621080000000000931040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c7200000066308210a80000031480000000000c52210a80000031480000000000c52210a80c0c0314a0200030300000808000c0c0000000000000000000000000000000000000000000000000000000000000000000100004c3200c0c000020200000000c52a18000c0c03148842a00000000000000000000000000000000000842400000000000000000000000800000000880814000000022040000000000014014000000000000820000000000000000000000000831008000000000000000000000000000000000600001a9a80001850406a6a0000000001a9a80000000006a6a480e3dc639a9a92638f718e0000498e3dc638000000000000000000000000531040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (6a6a66308031c800000000000000000000000000000000000000000000000000000000000000000000084900000000000000040e80000000003300021002400000000000000000000000000000044000000003320000000000000000000000000003300000000000000040000000004ee3202800000010643020000006c052000000000f3340982a00000ed12000015300000020200977f0000000000000000000000000000ed1200020000000000000010f00000000000000000001000800004122800002af0000000600400000000000003020100000bc52000000220000020011b4aa80000000000c52210a80c0190c220e72000066308031c8000198c20000d31040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (c0180c887264000061b220c190000186c88306400000061b22214ac0000021580000000000856214ac0000021580000000000856214ac0c0c021584200030300000108000c0c0000000000000000000000000000000000001d1d000000000074740000000000000100000c5340c0c000004200000000856318240c0c02158852b000000000000000000000000000000000009db80000000000000000000000004000000500000000000014040000000000024900000000000800004100000000000000000000000004100000000000000000800000000000000024500000001a80914000a86a6a0000000001a9a80000000006a6a64318031c9a9a998c200c7200331040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000005555603320c191555586c883064555561b220c19000000000000000000000000000000000000000000000000000000000000000000000021090000000000000000a88000000003300021000240400000000000000000000000000080000000003320000000000000000040000000003301400000000000040020000004ea3602804000000049420100005d0520000000010c355252300000e9160000153000000042007fff0000000000000000000000000000e91600004000000000000055f00000000000000000001430100002222800002af000000402800000000000000302000800dbc10000000a20000020011745000000000000856214ac000b31040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000140000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000200000000000000000000000080000000000000008000000000001400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ea1e00000000000000000000000a81900000081440064000002050000000001001450824000040150a81900000000000000000000000a8190080000000000100000000000000000102b600003015440ad9010d55550000000001555400731040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000020000000000000000000000000000000800000000000000000000000405000000000000160400000000000058000100000000000000000000000200000010000080000000000008000000000000000000000000000000000000001600000000000000000000000000000000000000000000000000001400000000000050000000000001400000000000000000000000008000000000000000000000000000000000000000000000200000000000000000200044008000000009100000020010044000020000001100280002000046000000000000000000000000000000000000000000000000000000000000000000000000000000000f31040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000480000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000004000000000000000000000000000000000000000100040000000000000000000000000000000000004000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032f6000000000000000000000000000000000080020000000000000000000000000000000000002000000000000000000000000000000000000000080000000000002000000000000000000b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000040000400080001000000000010000000000000000000000000000000000000000000000000000000040000000000000010000000000000010000000001000000000000004404000000000000000000000000002000000000000000000000000401000000000000000000000100000000000000110000000000000000000000000000000000000000000000000000000000000004000480000000000012000000000000480000000000000000000000000020000000000000000000000000480000000000012840000002000480080000100000cc000050c004480104500000012000000100000484000000000012000000000000000000000000000000008b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f387000000000000000000000000000100000444000000000000000000000000000000000000010000000000000000000000000000003003004b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000010002000000000000000400000000000000000000000010000000000000000000000000000000000000000000000400000000000000400000000000000000000000100200000000000000000000000000000000008000000000000000000400000000000000000000004000000000000004000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000004000000000000002000000000000000000000000000000100000000030000000000000000000004010000000009210400008410000000000400008000000200000000cb1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0500000000100010002004080000400000000000010100000000000000020000000000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000200000000000000000000000040000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000775f000000000000000000000000000080000082000000000000000000000000000000000000002b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4200000000000000000000000000000000000020000000000000000000000000000000000000000800000002000020000000000000000000000000000000000000000000000000000000000000000000804000000000400000000001000000000000400021004000002000008000400000000000000000000000000000000008040000020000008004000000004004100000000000000000400000200040000000000000000000000000000000000000000000000000000004008000004400000800004100800000000004400000000000000000004000000000000000004000008000801004000000c00000100010000000004020102000000000400041000000ab1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (003000000040800020000001084000208000048000000008001000000200000050000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007c2000000000000000000000000000000000080006b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000009002000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000002000000001000000000000000800000001000c20002000002000008000000008000000000000000000000000000000000000080000000210000000000010400000000000000000400000200020000000000000000000000000000000000000000000000000200010010000008100002000010202000000000000100000000000000000010000000000000000010000000300000800000002100000000000eb1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000080010200140000800000000000880028000a8000a000000000084040000000a0004000090002d000000004000a0000000000000000000000000000000200000000000000000000014080c00000000000000000400000000000000000000000000000000000000000102800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005000240000000000001000000000008000000000140008000044028000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009ef1001b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000087f3000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200140800000000005004040000000000000000000000000000000000000000000000000000000000000140001000000000004000008000a0000100800102d00020000000040a0000000008000000080002480000000000090008000000000000014214000000008000000000000000000000084802d020000000000000021000000000000000000000000000000000028000000000000a00000000000000000008000000080000000000000008000000000000000000009b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (110000080002000000000000100000000020000000000000080004000201000200100c0001090000411000008000000000000010800008020c00002000082014100030010000010000000000000400000000000000000000000000000000000004000040000000080000000000000000030000000000000000000000000005000000800000000400040000000000000000000001000000000000040000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000008000000502100280000000100000000000000000000000000000000000000000000000000000000000005b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000005a720000000000000000000000000000000000000080000800000000000080000000400000000000040000000000000000000400000080000000000240000000000000200010000000000820000000000080000000000000000000000000000000400000002100001040000000808000400000000020000001920840000400000000400000000000000000000000000201004000000000018000400000000050000000000000000000000000000000000000000000000008000000000000080000000000400000000000000000000000000000000000000040020000050100db1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000020600488019000800012000580000000004000000000000000000000040000000000021000000000000000000000000004000538000110a010000000009e20100080000019000005b200008000201f8801a248040001e10000000201800000000000000000000000000100000000000001200000000000000002014000000000000c00000000000000000000000061001000000000000000400000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000400000000000120100800000000842000000000412000082000100000000000000000000000000003b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (08021000008010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d4e900000000000000000000000000000000008001000000000000000000000000002000000000201a6000000000000000000000000002000000000000000000000020030000001010000000000000000000000000000000000000000000000000000000804160000000000000000000000000800100001100124800080000008061800000000000000000000000000100000000000400000000000008010000000000000000120000000000001000201814000100400000010020000002000000000000000000002000000000bb1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000000404000000000020000000000000000000000049020000000001280c02000024002100008000200000800000010000000000000000000000004020000080000020408210011410028102020808000001002408001208004000000200010204000000000044000004000000200000400000000000000000000000020010000000000000021000000800000408000000000049200000030000000000000000000001000800100000000220000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000000000000000000000000000000004081080000080020200008000001100007b1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (20000424900020804000828200000008000408000c01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d4e50000000000000000000000000000008000800000000800000000000080000000000000000020000000000000000000000000000082000002000000000000000020481040001020001040000000000084000000000004000000000000000000000000800000001040000041000080000000000020001100400000000100008000100000000000000000400000000101004000000210104000000000408030000000000000020000000000000004210030000000200004108000fb1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000002200093080001004000000224000008000110400000000004000000210010000000100000c4020000000002100010000000000000000000000000000000004000000001000c000000000000000091002800000002404102840801400100000000020000100041802400100080010013002281000200c000000800000010000000000000000000000000000040000100000800800000001000083000101000000000000000000002000000000000000000000300000020000010000000000000000000000000408000000000010000000000000000000040000000000000000000000004000000000000000000000000000000000000000200010000000071040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000004000000000000000000000000000000050040000001400000050000000040011004a100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f7b100000000000000001000000000000000004200000000000000000000000000050a0000000010000000000000000000001000000000000000000910000000000030100040000000000000000000000000000000000000000000000000000001000000c20000000000000000004001024000040000000321000040240000244000004000000000020000820000082100488000002000008000208020800000000000000000400000871040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (1040000000008a40000000000000000000000000000020801401922810000000000000000000000440010000000000000000020000000000504000000020004000000080000000000000000000000000000000000000000000000000000000000000000110000000001050104050101000000000004940000001000040010000100444001001500000100000000000000000000000040000000000000000000000000001000000004000010080400000000000000004000000000400000010000000000000000820000000050000000000000000800000000000200000000000000000000000000000000000080000000000000008000000000000000000000000471040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000400000020010000000000000000000008000000000000000040000000004000008800000100000202000000001000000004080080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000078d200000000000000002000000000000000000100000000000000000000000000000000000000000000000000000000000000000000200000000000040000000000010a1840000000000000000000000002000000000002000000000000000000000000020820000000000000000000020001800000020000000000200008100000004000000000000004000000002000100000000000c71040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000008000000080000000000002000000000010000000000000000000000000000000000000000c042000000000000804000010000000102000000000200000802008000000000401201a0000000004004404000000200100000000000000000000000000000000000000000000000000210000000000008404114000000020128000000004000000000000020100000000000c480000000400201000000000000000002000000000000000000000000200010000100000002000000028040000000000800000000080000b020000000000000000000480000000000000000000000400000000000000008000000000000000000000000000000000000271040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000a0040000000009000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009b7100000000000000000000000000000020000100000000000000000000000000040200000000004000000000000000000000000000100000000010000000000000404000000000000000000000000000000000000000000000000000000000000000010108000000000000000000000020004003000004c0000000000000020100000000a71040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000038000000000000001a00000020001000000020001040230000010010008000400800000040000020000000000000840000000800210000020000000001040020000001001008a0022600080000000000000000000000000000a0000000000000020900000000008000001820020060040820410800100c10042000007410400000001410410c80000031000040008081040061000004000200100002198807800000800100010000800019800000000000002000000002000000000020800020800000824000000000c00c4002000000000000000000000000402000000000000000000000000000000000000000000000000000000000000000000671040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000400000000000000000000080000001000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047f80000020000000000000000080080000200000000000000000000000081000020000000000000000200000000021002000000000200002000000000000001000021000000080000021000000000000000000000000200000000000000000100000000000000004104004800000002000000e71040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000050001000000000401000000000040000000000000000010000000000000004800000000800024000040000000900400000000004000000400000100000000100000001002000408000000004000120000000100004000100000000000000000000000040000081000000400012000000000000108000000000000000400000000000000000400000010000000041010000020000002050060000000000442010000010400000010104000004000000002000045082000400c8008000000200000000000000000001000040000000000000100000000000000000000000010400000c0000001000002080000000002000000000100000171040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000900200208000000010800010010020000000800000000001040000000000000000000000000000000000000000000000000000000000000000000002000000880000000000000000000000000000000000000000000000000000000000021000000000000021040220840080400001021000a04a000000000000000000000000000000000000000000000000000000000000000000000000000000000000e0000000040000000000000000000000000000000000100000000800000000000040000000000008000000000000040000004000000000000000400000400400000050000000000000000400000000000000000000000040000000000000000000971040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (04000110000000000010000000000000080022082000501080000000000008a000080000100800000c0002000040026104000100800000108000200008010401000100200000002001000044800408830000000040000000200001040020001020020020804010400000048204008040105000000000000000000000000000000000085000800080002130800020000002100000084040000002041209000001208000088000104100820800104104924810124440000100008400c0002081208800002a410402010410000c00210210412440040230210810000200000000000000000002022080020840002090000040800c3211008100000081040040242000571040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0040200000300100040040008010004000200000000000000000000008010000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000100001000009100800000000020000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000061b600000000000000000000001001040040005020001000000048000002049001001004010000120801000000000004080080000000400480000000800000c5082000800000080000004800000000d71040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (80000002002000000000000000040000000000000000000000000000000400000000080040000000400000000000000001000000000000000000000000000000014610080400000408400004404090000001c0040020000004000880001000000000000000000000000000000082002000090200000001000000000002000000806104180000000020800000004a008200000002080000800000000000000000004000400000010000000000000000000000000001000000000000a0000400000001801810060000441019000480002091001040001808008020001400004a00044000002008000040000000000000000000000010000020000000002800000400371040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000001000001000000000040000100000009000000200008040000020000000000000200000000000000000010008008080082000200000000004100000000000000020000000000400000000000000000000000000000000000000000002000000080000000000000000000000000000000000000030000400000000100000040000008000000041040c41040001000300040001082080000000000000000000000000000000000000000000000000000000000000000000000000000000000026c300000000000000000000000000000000010000000000000000000000000800a0081000000008000080000000000000000000800050040400000400b71040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000004000100004000004000000d00800200000000000000020000000020000c000000000000000000000000000008209241148108000208200000200000080c0000000200c01308008402208000800002000000000400000000000000000000000000008000000008080108300000000000000000000000000000000a0220004000000000000000400008000410000000000208000000048008200200042000840000000000010000020000000000000000000000000000800000000000000030000000000020800000000124808000020020008000c0000000800000020002848000001000000044821404000000000040000081000000000771040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000010100104000000400400000000000010000000010000000000000000000000000004080c040000000000400000000000001400000000800000000000000000000000001101040000000000000000000000000000000200000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000001000020000010000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000345d0000000000000000000000000002002000082000000000002000000002000000000001000042080000f71040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000010000000000000000100000000000000000000000100000001000000801040000000000000000000001000000000000000000000000100000400000000000000041040000000000000000000000001000300000041400001001000004100001000400304000044004014500000220000800410000000020000008000000000000000000000000000000001400022200010000000002800000800000000080000000000000000000001000000410020000420000000000000200000004000000000000000000000000000000200000000000008800000110408000000c40000210110d0401010000000001010800c400200001200108804000f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000200008000400080200002000030200804240000200040801030006000a00080003000000000000000000000000000018000000000c0000000000000000000000000000000000000000001800000000000000000200000000000000002000800000000040000000000000010000000000000200000000000000020000000000000000000000000000200000000000000000000000000000000000000000005038000001000c00000100040000000000001000000000000a0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000bf1f00000000000000000000000000000001000000000000008f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000080000000000000000000000000000000000140000030000000000000000000000000000002008000000000c00400012000000000000000200000000000000000000000000000000000000000010000000080000000000000000000000000010000028a00008001000000000000100000000000000000000000000000026401804000000080000000004000000000000000000000000000000010000208000250200000000002408c00000000000010000000000000000000000200000020020000000000020800000000000004000000000000000000000000000000000001c0000000008000400080900400010030e0008004f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0a0000000000080004000080000a000008005002010000020000000000800100000000010280000010004b00140000068200000000000000000000000000000000000001000000020000000040200040001000000000000010008004000001a000000000000000000000000000000000000000000000000008000000000000000800000000000000000000000002000800000000000000000000000000000000000000000000000000000000000040000000000800494000000010012d04010001000020200200000300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ef230000000000cf1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000008c2000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000020400000040200000009003030001000000000000000000000000000000000000000000000000000015000000080000000000000000000000000005000000000a8000000000000000000000000000000008024940000010080c6d00008000002c00000080000000000000000000000000000800410020801000800494000000010022d00000000000000000000000000010004000000400000040000000000000000000000004000000000000000000000000000000000000000002f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000800800000000020020028005000000000000000000200000000000020008010140202050002000000800000020000000148810000000010000000000000000000000000004000000000000000000000000000010006008000200000400000004020800000000000000000000004000000000000000029028000000000000000000020000000000000800000000000000280000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000010000000408800000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000af1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000001d54000000000000000000000000000018000000100a000000000000000000000000000000000100050000000000000000000000000000000000000008001000801020200080000040000400000000000000000000000000000000000000000000050100005408000000000000000000000000280001400000200840000800100002820000000000000000200000000000002a00000008000000000014020000000000000000000000000001080800000112000000000000000000000000000000000000000000000000000000000000000010000000000000002000000000000020006f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (102012020000000080001000000000000000000000000044000000001001002000100040040000402000000000004000000400402000180204820400800000000020804000004021088421000a8115083000000108008000000000080000000000000000000000040000020200000000804000000020102000800000080102020000844000000000000000140100000000000000000000200000000000402400000000000001100000000024024000000000901100000000000004000000000000020000000000000000000000000000008020001000401100404284184004032186192100a0088244049080020001002400000000000000000000000000000000ef1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006dfc00000000000000000000000000001000200000080000000000000000000000000000040012200100000000000000000000000000000000000800020008010012200000c0100020000402000000000000000000000000000000000000000000020090002003000000000000002001000020000090a42003089040021010000200020000000000000001200904084085008c2210a152100c02400024010000000000000000000000000002400908022210a02100a04084084028042102102100000000000080000000010084000000001f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10210000010000408000000000008800000000200200000000000020000000000000800000000008408400000000200200200010000004400040000008000408006000020200000000021000020100000000800000000000404000020480060004400000000100008000000010000000000000000000000000020000020008000000400000400000080001000000000000000001810100000000000000140160000000000000000010000000000000004000000000000000000000000004004000000000900100000000000000000000000000000000000000000000000000000000000000000000000002184182184084022106102100200200044180000200009f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000020000000000000402000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000372a00000000000000000000000000000000200008080000000000000000000000000000040000400100000000000000000000000000000000400080020000088024002400002000000000000000000000000000000000000000000000000000000a0010000800800000000000000000000020000010a0000000800000000020020000000000000000000060118408008500428213a122100002040000080000000000000000000000000001480100002182200000184080084000016102005f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000040004000000000000000000000000000000000000000000000000080000000000002002800000000000000000000000000000000000000200000000008008000000000200000000000000000000000000001002000000000000804000000000140008040000000000001000000020008000000000000000000000000000000000000000000000004000000000000000100000000000000000000000020000001000040020000000000000000000000000000000000000000000000000000000000000000200000000000008000000000000000000000000000000000000000000800000000000000000000000000000001000000080000000000040000df1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000002000000030430000000020c20c001008008200208000000040100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000b170000000000000000000000000000000040000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000800000200000000000000000000000000000000000000000000000000000000200000000000000000000000002001000040000080040000800000020010000400000000000000000000000000000000400000084040001400004000010000000000000000000000000000003f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010020004000000000000000000000000000000000000400100000800030030000000000c00c00000000000020000000000030000000000a00a000000000204090000000000000000000000000100000000000000000000000000000000020000000080000000000004000000000000000000000200000000004000000000000000000808000200008000000000100000028000000000000000000000000000000000900000000000000000000200000000000000200000000000000000000000000000000000000000000000000000000000300300000000000000040000000001009000000000040040000000000001000000000000000000000000000000000bf1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000001000000000000000000000000000000000000000000000120010008208400003000210a100001100584096800000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000838b0000000000000000000000000000000010000000000000000000000000000000000004000000000000000000000000000000000000000010000000000000800100000000000000000800000000000000000000000000000000000000000000000000002002000000000000008000400010000200010002800000080004000104000000000000000000001000030032100200000c00c00100007f1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000030001000800842c0810042132100c000400b00100000000000000000000000000000000000100000014009000800840a80400021021000000000040800000000080800010000a220e240000000800100800000000000000000000004004000000000000000000000008004000000800000000000000000800440808400008840000002840000021010300001000820000000940d000302a100830000000c0000008000000000000000000000000008000008080400000200000004010400140000010028002000000200000000000000004001028000000000000009010000000000400000000000000080080000000002402400000000090110000000000ff1040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00030600000000000c18000000000030000000000000000080000000000000000000000000000000000000000080000000c18521909452030614864251480c185239000004300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000363a000000000000000000000000000008000000040000000000000000000000000000000000100000008000000000000000000000000000004008000200080000c00002012000004000080c00000000000000000000000000000000000000000010008000200240000000000000200100000010008004204b08104002001000001100000000000000009040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0400800000100000108000000000000000000000000052190945200401486425148000028200000040000000000000000000000000000000a080000010000521909452000014864251480000521900000030600000000000c1a28000000003008a000000000002080000000030600000000000c1800000000003004000000000000000200000840008a08000021000328040000000200000000000000228040000000000a09000021000208040000000000a00000000000000000000000000a00000000000000200000840000a00000000000000000000000000a000000000000000000000000000000000000c1800000000003060000000000000c18000000000809040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000155540000000000055550000000001555400000000055550000000000000000000000000001880000000000000000000000000000000000000000001540055554c0ddd36455555383774d9155554e0dc5511c74740000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000036e1000000000000000000000000000000028000000000000000000000000000000000000000a00000000000000000000000000000000000000000200000040000a08000001000028000000000000000000000000000000000000000000000000000028200000040000000000000000100000000000400409040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (8a020800000000000000000e0000000000003800000082000000e2880000000000000000000000004c0ddd3646ec8d383774d91000008264601800000000000000000000000000000c2462990442100004c0ddd36440001383774d9100004e0dc00003aba8000000000eaea014000000000018821000000000010000000155540000000005555000000000008000000000000000000006a004000004100295200001980000000000001000000010086fb7a0000082b036307102110080dc00000000000445000000000000000000000001884600000000000001ff0000000400100000018000000000020000048800000000000000000000c0c010000000555500c09040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000c0c0100000006a6a0000000001a9a8000000000006a6a0000000001a9a80000000006a6a000000000000000000000000000188000000000000000000000000000000000000000000088006a6a480e3dc639a9a92638f718e6a6a498e222000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f375000000000000000000000000000000015040000000000000000000000000000000000000a00200000000000000000000000000000000000000000000000000a00044400000000040000000000000000000000000000000000000000000000000028800209040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000010140550140000000000000000f0000000000003c01001540500000f100000000000000000000000000480e3dc63ac2bd2638f718e000008010701800000000000000000000000000000e406204044210000480e3dc63800012638f718e0000498e200000545400000000015150140400000000189210000000000100000001a9a80000000006a6a000000000200000000000000000000015b00400000410301520c5d1988000000000000000000010087e37c0000082b076300082110083d4000000000012a2280000000000000000000001884600000000000000ff0040000020100000018000000000000100048800a09040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000002000000000000000000000000408800000000000000000000c0c000020200006a0000000001a9a8000000000006a6a0000000001a9a80000000006a6a0000000001a9a8000000000000000800000000000000000000000000000000000000000010000006a64308031c9a9a998c200c726a6a6630840131a9a800002020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa93000000000000000000000000000000008806000000000000000000000000000000000000005000000000000000000000000000000000000000000080800000000208000000004000000000000000000000609040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00080000404000000000000000000000000000000000000000000000000000000000022c1a202a0000000000000000000000010000003c00000c0a800000022800100000000000000000000064308031c8000198c200c72000000980201a0000000000000000000000000000000002600842a000064308031c8000198c200c720000663080000000540000202001515310008080054540826000000000310000000001a80000000006a6a0000000001a9a80000000000000000012b0a00000c4048008400003080010003fc3c00000000000005ef22000000001f7069102210337d800808000000411400000000000000000000000084000000000000001670000e09040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000084000000000000001671240000002000000000000000000000000408800000000000000000000c0c000004200c0550000000001555400000000000555500000000015554000000000555500000000015554000000000000000814000000000000000000000000000000000000000000809c055603220c191555586c883064555561b22026a5555400000420000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000aa54000000000000000000000000000000050450000000000000000000000000000000000000092400000000000000000000000000000000000000000000080000109040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000004000040050a8890000400020000000000000000000000000000000000000000000000000010544153c000000000000000000000000800003800001074f000000010140080000000000000000000603220c190400586c88306400000080220524000000000000000000000000000040002058c72b0000603220c190000186c883064000061b220000303a8000000000eaea3109010803aba8082600000000031010000030154000000000555500000000015554000000000000000001210840000c404c108500003181800801fc3800000000000004ebe6108000001f6078622300317f804108000000020780000000000909040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000044000002000001100000000000000000000000000000000000000000000000000001100080000000044002000000001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500000000000000000000000000500000000000000000000000000000000000000000000000000000080000020000016000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007104000000000000000000000000000000000ab6000000000000000000000000000000000000400500000000000000509040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000008000000000000200000000000000000008000000200000000000000000000000000000000000000008008000000000000000000000000000000000000000000000000000000000000000000000000000008000000000001400004000000000000000000000000000400000000580028000000016c00000000000000000000000014002042000000000000000000014000000000000080000000000016024304000000000000000000014000000000000520000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000440904100100011104104100000444000000000000000d09040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (030000000000000000004800000000000120000000000000000000000000000000000000000000000000000000000000000004800000000000000000000000014800000400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000252e000000000000000000000000000000000000000000000000000000309040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000040000000000001000000000000000000000000001010000000000000000000000000000000000000040000000000000010000000000000000000000000000000000000000000000000000003000000000040010000000000000000000000000000000000000000000000000000400010000000010000000000000000000000000000000000000000000000000000000000000000000400008000000010000000000004000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000000000012000000000000000000000b09040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000800000000000000000000000000001041001000001041041000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ded0000000000000000000709040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000033c200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000008000000000000000000000000000000000000000008000000000004000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000200000000000000000000000200000000000000000000000000004004000000000000000000000000000000000000010000000000004304000001000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f09040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000400000c00000000000010010001200100048000000000000000000200000004000000004000000000000100000000000000002000800000000000000000000000000000000000002000000005000000000000000020000000804000800004000004000000000000000000000000000000000000000000000000000000000000000000000000000000040080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400408000002000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000089040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000c5d400000000000000000000000000000000000000000000000000000000000008000040000000201000000000000000000000000240000000000000000000000000000000000000008040000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000000010000000000000000000000000000000000000080488000000002200000000000000000000000000000100000000000000000000000000000000000080000000000002008000000000000000000000000040000000000010000000000000000000000000000000000001000000889040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000400000000000000000000000000100002100000000090000300000c00000030000000004040000000008100010000000004000000000000000000000000004000800000000100000000000000000000000008000002000000000800000000000100000000002004000000010000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000000000000000000000080000000000000000000000000000000000000000000000000000000200200000002000008000000000000000000000000000000000000000000000000000000000000000000489040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000094c700000000000000000000000000000000000000000000000000000000000000000020000000000800000000000000000000000020000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000080300000000002000000000000000000000000002000000000000000000000000002000000000000000000000000002000000000000000000000000002000000000000080000000c89040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000041028080000800800a00000000000000000000000000000000000040000000000000040000000000000000000000000000000080080100005008240000000a000000000020a8000000008000000001000040005204100004000a0000000000000000000000000000000000000008000004000000000000000004c028000000001140b4024d00000902800000000000000000000000000000000000000000000000000000000000000000000000000000000080080000000200a00000000000000000000000000a00000000000000000000000000000000000000000000000000000140208000000005008200000000000000000000000000000000289040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0010000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f71b00000000000000000000000000000000000000000000000000000000020014020800000000000000000000000000100000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000802800000000000000000000000000000000000809200b4020000800000000000000000000000000004002800000000000000020800020002800000000000014030c000000028000000000000a89040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000400800010800400000000000000001000000000000000400000000000000000000000000000000000000000000000000000200000000410410008010200000000000400000504000010008c48000000000000800000004008004000000010000000000800000900400400000808010000000400000000000000000100000000000400000034904008000000400000020000000000000000000040000000000040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100208000689040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000008041018059001001040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a20400000000000000000000000000000000000000000000000000000000000000000004000000010030000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000100000000000000000000000000000000100000000000100000000340001100000002000000040000000002000000000000002100000e89040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (010000000000000000800000020005c201000000000000000048000019001201078600000000000000001000000000020000000000000000000000000000000000000000000000000000040000000000100000810000004000000000000000600000001040600208040000000001001000000000600048000000000000200208020200000020001000001000000000000000000000100800000000000100008009602001000000000000008100041200001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000000000000000000000000189040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000008000000000001000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000884d00000000080000000000000000000000000000000000000000000000000000041000000010200648000000000000000000000218678000000000000000000000000000000000008079600000000000000000000000000000000000000000000000000000000000000000000000000008000600001000000000000000000000000000000000000000010400086580004000012019400000000000200000989040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0008000002410001200010000010000080200200000000000000440000020800000801000000100000000000c00000001200000000000000000000000000000000040000000000000000000000000000000000000000000000000000008100100000000805210004224200204000000100011100000204008820040040000000001000000008800048000800000000280820080800000080000010001000000000000000000000401000000000000400008020000008400000100010040100000000000000000020000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000589040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000004000000000000000000000000004000000000000000100000000000000000000000000000000000000c00001000000220000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000025db00000000000000000000000000000000000000000000000000000000020000000000000004200000000000000000000000000200000000000000040000000800000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000100d89040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (004000000000000000000000000000008040004c00000020000a1000000004000000000020000110000000000000000000002000030000002000000080000004000031000004000000000000000000010000002800001400000000000000000000000000000000000100000000000200100000002002000040084080000000002000000004002000000000000c000000000000b000010008210084000410010000300000000200240000000000006000000200000000000000000200000010000200204000402000401000000000000048000008800001000000000000000001000000000000000000000000000000000000000000000000000000000000000000389040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000200000000000000000000000200000000000000000000000000200000000000000000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000930400000000080000000000000000000000000000000000000000000000000008000010000000104000000000000000400000000100000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000b89040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000100000000000000200000000000000000000000000000000000008000100008000208000000000000001008000000000000030000000400208a00000000500000000000200000000000000000000000000000008200000000100040000000000000000000000000000000000000000000000000090000000000000800000008420000400000200000000800000408000000000020000000004000000004100000000800000000000000000000000000000000000000000000000000000000000000000000000000100008000008000000000010208000008204000200000000000000000000000000000000000000000000000000789040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000001000000000000000000000000000000000000000000000000000000000000000000001000000000200000000000000001000000000200000000000000000000000000000000000000000000000000000101000000000044080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005e9f00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f89040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000000000000000000000001000010000008000000000000000000000000000000000000000003010800000000400400000000000000000000000080000000000000000000000020c80000000000001000020000000480c000000000000000000000000800000000000020000000000000000000000000000000000000000000000020400000000000000000000100000010000000000000008400000000000120000000000004800000000000100000000000000004020000000000200000000000000000000000000000000000000000000000000000100008000100800000000000020000002000000800000000000049040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (4000000000040000000000000001800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000008000000000000000000000000000000000000000008000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d1c300000000000000000000000000000000000002000000000000000000000010000000000000004000000000000000000000000004000000000000000000000000000000000000000100000000000000000000000000849040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000000002000180000000000000000000000000000000000000000000000000000000000020000000000000000020000000000000800000000000000000000004000800000800040000000000040000180000000000004104000000100000000000000000000000000000800000000020000000000000000800000000000000000000000000000000000000180000000000000000000400000000000000000000104120000800104124100002004000000000000026000000000000400000806000001182000000000000002000190000000000000400000000000000000000000004400000000000011a000001140020000449040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0002104000000000080000000000000520400000000000080000000000100000002800000000000000000000000000000000000000000000000000000000040041000000000000000000000000008200001040000000000000000008000000200000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000603500000000000000000000030000000000000000000000000000001000000001000000000000210000000200000000000000000200000000000000000000200000000000c49040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000040000000000000000000050000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000000000000800000000010000000000000041040001000000000000000000000000401040040000000000400000000000000010040020000000001000000000000000000000000000000104000000000000000100000002404000001041000000001041041000000040002000208200000208000208008208200000008200002001000201000010000000041040201001000040000000000000000249040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000040840401001000040000000000000000022000020000820800000830000000c80000084004000c0000000200088008009200000000000000000000000000000000000000000000000000000000080082000000000000000000000004010400002020000000000000000010000000400000000000000000100000000000000000000000020800800800000000002000004800000000000000001004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000694600000000000000000000000000000000000001000000000000001000000101004000000000240000000400000000000000a49040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000009208000000880000000000002200080000000100000000000000001000000000200400000000040100000000000000000000000000000000000000000000000000000000000000000000000200000040000000000000000000000000000000000000800000000012082000400002082000a220000000000202102084008200004000000000000000000000800020040802080c00000104920822120002000000000000000000000000020042000000000900100000000000000000000000000000000000000000000000000000200000000000008100200204008204928004124102410440000410201411010410400004048410080905000101000488000649040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000001001000000000000420020000000000004000008000000400000000000000000000000000402000080000000000000000000200000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000008008000020000000000000000000100010000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000295600000000000000000000050000000000000002000000000000000000020800e49040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000004000c0000000000000000000000042001000000000000000000000000000000000002002000000001000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000010000000000000000084000000100010400000000000000000000010001000000000000000000000000000020020800000000000000000002400000000000000000000000000000000000000000000000000000000000000000000000000208000000000008000000000000000000000000410410400410410410414210410400100040400000400905800149040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (001008001000200009000a0000000000004000000084004020100000c10200000002400000000000200000000000000000000000000000000000000000024100000930000820000020038010040040002000800023020000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c00000000000000000000000000c000000000000000000000040000000000000000800800000080081e8000000000000000008000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002e2800000000000000000000000000949040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000051210000000000000000000000000000000000000000000000000000000002080400002080000008000000000000000000000000001000000000000000040000000000000000000000201000000000000000000000000040000000000000000000000000000000000000000000002000000000000000000100000000200000000400000000000010000420820114100120120020820000010000000c00030000000000000000000000000000000003840000000820c0c0004108200028100008000000000000000000090000000008000c0001400400000000000000000000000000000000000000000000000000000000000000000000000000000000549040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00400000000810000000000000000000000000200004000000800000000000000000102008000030008000400000804000200000800000440000480000000000000000000000000000000000000000010400400c0000040800900001000002004800080000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000000000000000000000000000800000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d49040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000f1f30000000000000000000000000000000000000000000000000000000000020000800000000002000000000000000000000000000000000000000000000020000000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000480400400000000000000000000000000000000002000000000000000000000000000020000000000000000000000000000000000000000000000000011000000000000000000800000000000000000000000000000000000000000000000349040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000000000000000000080000000000080200000014088000000000000000100000018000000000002000000000000080080000002000002a000000000380042000400000000000100004000800000000000000000000000000000000000001040000000000000008000800002000100020000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000010000000000000000000000000000000000000000000000000002000000000000000080000000000000000000000000000000000000000000000000000000000000000000000000000000000b49040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000026a500000000000000000000000000000000000000000000000000000000001000000000040000000001000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002180000400000000000080000000000000000002000000000000000000000008010000000000000000000000020022000000000000000000000000002000000000a0008001000200000000000749040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000280000000000000000000000000000000000000000000000800000050008105000004000000000000000000000000200000000000000000000000000000000080000000000001000000000000000000280000000000000000000000000000000000000000000400300020040000100000000000002001000008000400000001400000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000f49040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000dad400000000000000000000000000000000000000000000000000000000000000000000080000000100000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000680010a00000144000000000000000000000005000000a00000000000000000005000800040000000000000000008000000000000000000000000c9040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000145000000005020000000000000008000000000000000140028005000000000000000000000000000000000000000000a0108080020004d01100000a154000000000000000000200000001000000000000000000000000000000001000100000000000000001000000000000000000000a00140000000000000000000000000000000002002041010000000000a80000040000008000000000000a000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000020000000000000000000000000000000000000000000000000000000500d000000101168200200144008c9040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (00000000000a00a0002805020a0200210084000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004bbe000000000000000000000001000000000000000000000000000000005020000000100000140000000000000000000000000040000000000000000000000000000000000018005000000a00000000000000000000000000000000000000000000000000000000000000000000000000000000028005000000a0000000000000000000000000000000a00140000a10005a00008a00028000000000000028000000000000000000000000020000000000000000004c9040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (10080000000000000002200100000000000000000040008a02000000200800000000000000800000000000030020000201000000000000000000000000000000000000000000080231000c81102191284030422100000000000000004040000000400000000002100000000080080001000002010020010040000000c30028002400a0020000000000000000000000000000000001008400080048211244100040008802808000080002101000000000002000000000000000000000000000000000000000000000000000000000000000000000000000000000000040010000000000000000000000080010000000000000000000000000000000000000000000cc9040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
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+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (000000000000000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff55170000200000ef00000000da564c65055280140800c2001000000da5b00000300a0000080002000080002017cbe4a000004c65055280140800c2001000000da5b00000300a0000080002000080002017cbe4a000004c65055280140800c2001000000da5b00000300a0000080002000080002017cbe4a000004c65055280140800c2001000000da5b00000300a0000080002000080002017cbe4a000004c65055280140800c2001000000da5b00000300a0000080002000080002017cbe4a000004c65055280140800c2001000000da5b00000300a0000b99040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000799040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f99040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000059040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000859040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000459040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c59040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000259040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a59040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000659040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000e59040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000159040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000959040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000559040) ;
+RUNTEST 5000 TCK ;
+SDR 8 TDI (60) ;
+SDR 2080 TDI (ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000d59040) ;
+RUNTEST 5000 TCK ;
+SIR 8 TDI (FF) ;
+SIR 8 TDI (01) ;
+RUNTEST 20 TCK ;
+SIR 8 TDI (FF) ;
+RUNTEST 20 TCK ;
+SIR 8 TDI (FF) ;
+RUNTEST 20 TCK ;
+SIR 8 TDI (FF) ;
+RUNTEST 20 TCK ;
+SIR 8 TDI (FF) ;
+RUNTEST 20 TCK ;
+SIR 8 TDI (FF) ;
+RUNTEST 10000 TCK ;
+SIR 8 TDI (20) ;
+SDR 32 TDI (00000000) TDO (00000000) MASK (00000000) ;
diff --git a/src/prj/td_project/hg_anlogic.adc b/src/prj/td_project/hg_anlogic.adc
index c449a69..223992b 100644
--- a/src/prj/td_project/hg_anlogic.adc
+++ b/src/prj/td_project/hg_anlogic.adc
@@ -62,10 +62,12 @@ set_inst_assignment {u_pll/pll_inst} {location = x40y0z0;}
 
 
 create_bound { bound2 } -mode fixed -width 25 -height 25 -origin { 0 0 }
-create_bound { bound3 } -mode fixed -width 18 -height 20 -origin { 23 0 }
+create_bound { bound3 } -mode fixed -width 18 -height 30 -origin { 23 0 }
 add_cells_to_bound -bound { bound2 } -cells { u_mipi_dphy_tx_wrapper }
 add_cells_to_bound -bound { bound2 } -cells { U_rgb_to_csi_pakage }
 #add_cells_to_bound -bound { bound2 } -cells { exdev_ctl_a }
 #add_cells_to_bound -bound { bound2 } -cells { exdev_ctl_b }
 add_cells_to_bound -bound { bound3 } -cells { u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper }
-
+add_cells_to_bound -bound { bound3 } -cells { u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper }
+#add_cells_to_bound -bound { bound3 } -cells {sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert }
+#add_cells_to_bound -bound { bound3 } -cells {sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert }
diff --git a/src/prj/td_project/hg_anlogic.al b/src/prj/td_project/hg_anlogic.al
index e741ec9..a4b8b9c 100644
--- a/src/prj/td_project/hg_anlogic.al
+++ b/src/prj/td_project/hg_anlogic.al
@@ -572,6 +572,9 @@
                 <BitgenProperty::GeneralOption>
                     <bin>on</bin>
                 </BitgenProperty::GeneralOption>
+                <PlaceProperty>
+                    <opt_timing>high</opt_timing>
+                </PlaceProperty>
             </Strategy>
         </Run>
     </Runs>
diff --git a/src/prj/td_project/hg_anlogic.sdc b/src/prj/td_project/hg_anlogic.sdc
index 20b9fdf..caf27f7 100644
--- a/src/prj/td_project/hg_anlogic.sdc
+++ b/src/prj/td_project/hg_anlogic.sdc
@@ -10,7 +10,13 @@ create_generated_clock -name S_clk_x4 -source [get_pins {u_pll/pll_inst.clkc[0]}
 create_generated_clock -name S_clk_x4_90d -source [get_pins {u_pll/pll_inst.clkc[0]}] -master_clock {S_clk} -phase 90 -multiply_by 4 -duty_cycle 0.5 [get_pins {u_pll/pll_inst.clkc[3]}]
 create_generated_clock -name a_sclk -source [get_ports {a_lvds_clk_p}] -master_clock {a_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {u_pll_lvds/pll_inst.clkc[1]}]
 create_generated_clock -name b_sclk -source [get_ports {b_lvds_clk_p}] -master_clock {b_lvds_clk_p} -edges {1 2 3} -edge_shift {0 -7.441 -14.881} [get_pins {uu_pll_lvds/pll_inst.clkc[1]}]
-set_false_path -from [get_regs {u_pixel_cdc/multipy_xy[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]}]
+set_false_path -from [get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]}]
+set_false_path -from [get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]}]
+set_false_path -from [get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]}]
+set_false_path -from [get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]}]
+set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]}]
+set_false_path -from [get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]}]
+set_false_path -from [get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]}] -to [get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]}]
 #set_input_delay -clock [get_clocks {clock_source}] 12.5 [get_ports {a_ad_sdi b_ad_sdi clock_source global_reset_n gpio_trigger onoff_in paper_in rxd_dsp scan_in}]
 #set_input_delay -clock [get_clocks {a_lvds_clk_p}] 6.25 [get_ports {a_lvds_clk_p a_lvds_data_p a_lvds_data_p[0] a_lvds_data_p[1] a_lvds_data_p[2] a_lvds_data_p[3] a_lvds_data_p[4]}]
 #set_input_delay -clock [get_clocks {b_lvds_clk_p}] 6.25 [get_ports {b_lvds_clk_p b_lvds_data_p b_lvds_data_p[0] b_lvds_data_p[1] b_lvds_data_p[2] b_lvds_data_p[3] b_lvds_data_p[4]}]
@@ -22,3 +28,7 @@ create_generated_clock -name clk_adc -source [get_ports {clock_source}] -master_
 set_false_path -from [get_regs {BUSY_MIPI}] -to [get_regs {BUSY_MIPI_sync_d0}]
 set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {a_pclk_rstn}]
 set_false_path -from [get_regs {clkubus_rstn}] -to [get_nets {b_pclk_rstn}]
+#set_false_path -from [get_nets {u_bus_top/start_sp_a_tmp[*]}] -to [get_regs {u_bus_top/start_sp_a_sync1d_48m[*]}]
+#set_false_path -from [get_nets {u_bus_top/start_sp_b_tmp[*]}] -to [get_regs {u_bus_top/start_sp_b_sync1d_48m[*]}]
+set_false_path -from [get_nets {u_O_clk_lp_p/signal_from[*]}] -to [get_regs {u_O_clk_lp_p/temp[*]}]
+set_false_path -from [get_nets {u_O_clk_lp_n/signal_from[*]}] -to [get_regs {u_O_clk_lp_n/temp[*]}]
\ No newline at end of file
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_094627.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_094627.log
new file mode 100644
index 0000000..68458ce
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_094627.log
@@ -0,0 +1,1854 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 09:46:27 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.132704s wall, 2.046875s user + 0.078125s system = 2.125000s CPU (99.6%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 314 MB, peak memory is 339 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.128490s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.7%)
+
+RUN-1004 : used memory is 527 MB, reserved memory is 513 MB, peak memory is 527 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.904536s wall, 1.859375s user + 0.046875s system = 1.906250s CPU (100.1%)
+
+PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.129571s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (96.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28668e+06, overlap = 484.094
+PHY-3002 : Step(2): len = 1.18318e+06, overlap = 557.375
+PHY-3002 : Step(3): len = 843931, overlap = 601.625
+PHY-3002 : Step(4): len = 791874, overlap = 624.344
+PHY-3002 : Step(5): len = 609615, overlap = 754.969
+PHY-3002 : Step(6): len = 529112, overlap = 805.719
+PHY-3002 : Step(7): len = 456874, overlap = 912.031
+PHY-3002 : Step(8): len = 425331, overlap = 995.844
+PHY-3002 : Step(9): len = 378282, overlap = 1057.66
+PHY-3002 : Step(10): len = 340965, overlap = 1115.97
+PHY-3002 : Step(11): len = 297218, overlap = 1185.28
+PHY-3002 : Step(12): len = 272422, overlap = 1214.28
+PHY-3002 : Step(13): len = 251103, overlap = 1252.66
+PHY-3002 : Step(14): len = 233830, overlap = 1297.31
+PHY-3002 : Step(15): len = 207240, overlap = 1327.09
+PHY-3002 : Step(16): len = 192315, overlap = 1358.84
+PHY-3002 : Step(17): len = 174239, overlap = 1404.44
+PHY-3002 : Step(18): len = 162009, overlap = 1423.03
+PHY-3002 : Step(19): len = 147685, overlap = 1465.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2036e-06
+PHY-3002 : Step(20): len = 148424, overlap = 1423.66
+PHY-3002 : Step(21): len = 179191, overlap = 1304.53
+PHY-3002 : Step(22): len = 190294, overlap = 1232.22
+PHY-3002 : Step(23): len = 199319, overlap = 1189.78
+PHY-3002 : Step(24): len = 198566, overlap = 1179.34
+PHY-3002 : Step(25): len = 198247, overlap = 1163.12
+PHY-3002 : Step(26): len = 195020, overlap = 1157.25
+PHY-3002 : Step(27): len = 194648, overlap = 1158.09
+PHY-3002 : Step(28): len = 193918, overlap = 1142.66
+PHY-3002 : Step(29): len = 192851, overlap = 1149.03
+PHY-3002 : Step(30): len = 191764, overlap = 1148.06
+PHY-3002 : Step(31): len = 190566, overlap = 1168.28
+PHY-3002 : Step(32): len = 188829, overlap = 1145.56
+PHY-3002 : Step(33): len = 188125, overlap = 1149.47
+PHY-3002 : Step(34): len = 187128, overlap = 1136
+PHY-3002 : Step(35): len = 186806, overlap = 1099.56
+PHY-3002 : Step(36): len = 184419, overlap = 1073.5
+PHY-3002 : Step(37): len = 183688, overlap = 1074.06
+PHY-3002 : Step(38): len = 181963, overlap = 1075.84
+PHY-3002 : Step(39): len = 180821, overlap = 1100.16
+PHY-3002 : Step(40): len = 180049, overlap = 1107.62
+PHY-3002 : Step(41): len = 178563, overlap = 1115.78
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.40721e-06
+PHY-3002 : Step(42): len = 182212, overlap = 1088.72
+PHY-3002 : Step(43): len = 192003, overlap = 1041.94
+PHY-3002 : Step(44): len = 195313, overlap = 996.5
+PHY-3002 : Step(45): len = 200502, overlap = 971.938
+PHY-3002 : Step(46): len = 203704, overlap = 964.062
+PHY-3002 : Step(47): len = 207043, overlap = 946.125
+PHY-3002 : Step(48): len = 207363, overlap = 916.281
+PHY-3002 : Step(49): len = 207868, overlap = 907.031
+PHY-3002 : Step(50): len = 206820, overlap = 918.844
+PHY-3002 : Step(51): len = 206254, overlap = 931.125
+PHY-3002 : Step(52): len = 204603, overlap = 938.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.81441e-06
+PHY-3002 : Step(53): len = 211487, overlap = 931
+PHY-3002 : Step(54): len = 228174, overlap = 895.562
+PHY-3002 : Step(55): len = 237150, overlap = 803.812
+PHY-3002 : Step(56): len = 242854, overlap = 767.344
+PHY-3002 : Step(57): len = 244809, overlap = 750.625
+PHY-3002 : Step(58): len = 247200, overlap = 746.219
+PHY-3002 : Step(59): len = 246762, overlap = 749.906
+PHY-3002 : Step(60): len = 246476, overlap = 758.188
+PHY-3002 : Step(61): len = 245504, overlap = 776.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.62883e-06
+PHY-3002 : Step(62): len = 259270, overlap = 736.844
+PHY-3002 : Step(63): len = 280310, overlap = 622.125
+PHY-3002 : Step(64): len = 289452, overlap = 594.688
+PHY-3002 : Step(65): len = 292950, overlap = 596.625
+PHY-3002 : Step(66): len = 291834, overlap = 562.719
+PHY-3002 : Step(67): len = 289272, overlap = 547.375
+PHY-3002 : Step(68): len = 287091, overlap = 546.344
+PHY-3002 : Step(69): len = 287110, overlap = 528.281
+PHY-3002 : Step(70): len = 287591, overlap = 509.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.92577e-05
+PHY-3002 : Step(71): len = 306070, overlap = 487.531
+PHY-3002 : Step(72): len = 321535, overlap = 471.406
+PHY-3002 : Step(73): len = 327807, overlap = 437.219
+PHY-3002 : Step(74): len = 332649, overlap = 431.281
+PHY-3002 : Step(75): len = 331947, overlap = 424.094
+PHY-3002 : Step(76): len = 332519, overlap = 428.656
+PHY-3002 : Step(77): len = 332226, overlap = 415.594
+PHY-3002 : Step(78): len = 331189, overlap = 397.969
+PHY-3002 : Step(79): len = 330580, overlap = 386.438
+PHY-3002 : Step(80): len = 331430, overlap = 383.438
+PHY-3002 : Step(81): len = 332546, overlap = 365.906
+PHY-3002 : Step(82): len = 332833, overlap = 367.281
+PHY-3002 : Step(83): len = 331822, overlap = 367.219
+PHY-3002 : Step(84): len = 332233, overlap = 356.375
+PHY-3002 : Step(85): len = 331344, overlap = 344.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.85153e-05
+PHY-3002 : Step(86): len = 350518, overlap = 322.5
+PHY-3002 : Step(87): len = 360328, overlap = 306.594
+PHY-3002 : Step(88): len = 357880, overlap = 317.406
+PHY-3002 : Step(89): len = 358822, overlap = 305.344
+PHY-3002 : Step(90): len = 363911, overlap = 302.406
+PHY-3002 : Step(91): len = 367835, overlap = 304.938
+PHY-3002 : Step(92): len = 363522, overlap = 317.188
+PHY-3002 : Step(93): len = 365018, overlap = 310.875
+PHY-3002 : Step(94): len = 367761, overlap = 310.25
+PHY-3002 : Step(95): len = 369860, overlap = 319.094
+PHY-3002 : Step(96): len = 365177, overlap = 314.25
+PHY-3002 : Step(97): len = 363436, overlap = 316.188
+PHY-3002 : Step(98): len = 364963, overlap = 322.094
+PHY-3002 : Step(99): len = 366885, overlap = 314
+PHY-3002 : Step(100): len = 363632, overlap = 313.844
+PHY-3002 : Step(101): len = 363549, overlap = 310.25
+PHY-3002 : Step(102): len = 364192, overlap = 304.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.70306e-05
+PHY-3002 : Step(103): len = 382186, overlap = 300.719
+PHY-3002 : Step(104): len = 393320, overlap = 290.438
+PHY-3002 : Step(105): len = 390061, overlap = 265.469
+PHY-3002 : Step(106): len = 389428, overlap = 253.938
+PHY-3002 : Step(107): len = 394384, overlap = 237.344
+PHY-3002 : Step(108): len = 399627, overlap = 227.5
+PHY-3002 : Step(109): len = 397812, overlap = 236.219
+PHY-3002 : Step(110): len = 399415, overlap = 243.656
+PHY-3002 : Step(111): len = 402607, overlap = 242.125
+PHY-3002 : Step(112): len = 404322, overlap = 239.312
+PHY-3002 : Step(113): len = 400761, overlap = 240.844
+PHY-3002 : Step(114): len = 399368, overlap = 243.125
+PHY-3002 : Step(115): len = 401595, overlap = 233.938
+PHY-3002 : Step(116): len = 404676, overlap = 239.812
+PHY-3002 : Step(117): len = 400962, overlap = 247.219
+PHY-3002 : Step(118): len = 400739, overlap = 247.281
+PHY-3002 : Step(119): len = 402377, overlap = 239.938
+PHY-3002 : Step(120): len = 404242, overlap = 244.781
+PHY-3002 : Step(121): len = 401723, overlap = 248.594
+PHY-3002 : Step(122): len = 401871, overlap = 252.375
+PHY-3002 : Step(123): len = 404195, overlap = 251.375
+PHY-3002 : Step(124): len = 406140, overlap = 257.312
+PHY-3002 : Step(125): len = 403540, overlap = 259.656
+PHY-3002 : Step(126): len = 403245, overlap = 259.188
+PHY-3002 : Step(127): len = 403984, overlap = 258
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154061
+PHY-3002 : Step(128): len = 419164, overlap = 244.906
+PHY-3002 : Step(129): len = 428463, overlap = 233.125
+PHY-3002 : Step(130): len = 426829, overlap = 217.812
+PHY-3002 : Step(131): len = 427102, overlap = 211.844
+PHY-3002 : Step(132): len = 429947, overlap = 210.938
+PHY-3002 : Step(133): len = 431921, overlap = 206.281
+PHY-3002 : Step(134): len = 429822, overlap = 204.156
+PHY-3002 : Step(135): len = 430225, overlap = 212.344
+PHY-3002 : Step(136): len = 432285, overlap = 210.5
+PHY-3002 : Step(137): len = 434226, overlap = 207.281
+PHY-3002 : Step(138): len = 433644, overlap = 199.531
+PHY-3002 : Step(139): len = 434785, overlap = 208.406
+PHY-3002 : Step(140): len = 436011, overlap = 203.75
+PHY-3002 : Step(141): len = 437222, overlap = 200.469
+PHY-3002 : Step(142): len = 436221, overlap = 201.188
+PHY-3002 : Step(143): len = 436724, overlap = 207.406
+PHY-3002 : Step(144): len = 437985, overlap = 207.875
+PHY-3002 : Step(145): len = 439045, overlap = 207.375
+PHY-3002 : Step(146): len = 437923, overlap = 207.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000297449
+PHY-3002 : Step(147): len = 447213, overlap = 201.406
+PHY-3002 : Step(148): len = 454452, overlap = 203.656
+PHY-3002 : Step(149): len = 454959, overlap = 198.281
+PHY-3002 : Step(150): len = 455780, overlap = 191
+PHY-3002 : Step(151): len = 458270, overlap = 186.562
+PHY-3002 : Step(152): len = 459849, overlap = 184
+PHY-3002 : Step(153): len = 458838, overlap = 186.688
+PHY-3002 : Step(154): len = 459485, overlap = 181.969
+PHY-3002 : Step(155): len = 461789, overlap = 184.562
+PHY-3002 : Step(156): len = 463496, overlap = 173.094
+PHY-3002 : Step(157): len = 462326, overlap = 171.438
+PHY-3002 : Step(158): len = 462656, overlap = 170.656
+PHY-3002 : Step(159): len = 464690, overlap = 167.469
+PHY-3002 : Step(160): len = 466201, overlap = 171.656
+PHY-3002 : Step(161): len = 465166, overlap = 165.188
+PHY-3002 : Step(162): len = 465218, overlap = 167.594
+PHY-3002 : Step(163): len = 466623, overlap = 165.719
+PHY-3002 : Step(164): len = 467287, overlap = 162.25
+PHY-3002 : Step(165): len = 466412, overlap = 161.688
+PHY-3002 : Step(166): len = 466327, overlap = 158.469
+PHY-3002 : Step(167): len = 467295, overlap = 161.75
+PHY-3002 : Step(168): len = 468354, overlap = 160.594
+PHY-3002 : Step(169): len = 468124, overlap = 155.656
+PHY-3002 : Step(170): len = 468614, overlap = 159.062
+PHY-3002 : Step(171): len = 469394, overlap = 153.281
+PHY-3002 : Step(172): len = 469789, overlap = 151.75
+PHY-3002 : Step(173): len = 470169, overlap = 135.656
+PHY-3002 : Step(174): len = 471663, overlap = 137.594
+PHY-3002 : Step(175): len = 472466, overlap = 133.844
+PHY-3002 : Step(176): len = 473025, overlap = 132.812
+PHY-3002 : Step(177): len = 472951, overlap = 135.25
+PHY-3002 : Step(178): len = 473084, overlap = 136.938
+PHY-3002 : Step(179): len = 473356, overlap = 135.25
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000566962
+PHY-3002 : Step(180): len = 479949, overlap = 132.312
+PHY-3002 : Step(181): len = 485650, overlap = 134
+PHY-3002 : Step(182): len = 486958, overlap = 125.781
+PHY-3002 : Step(183): len = 488201, overlap = 126
+PHY-3002 : Step(184): len = 490404, overlap = 126.844
+PHY-3002 : Step(185): len = 492125, overlap = 131.5
+PHY-3002 : Step(186): len = 492854, overlap = 128.094
+PHY-3002 : Step(187): len = 494116, overlap = 125.406
+PHY-3002 : Step(188): len = 496340, overlap = 126.312
+PHY-3002 : Step(189): len = 497988, overlap = 123.688
+PHY-3002 : Step(190): len = 498041, overlap = 122.812
+PHY-3002 : Step(191): len = 498102, overlap = 120.5
+PHY-3002 : Step(192): len = 498689, overlap = 124.594
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109183
+PHY-3002 : Step(193): len = 502699, overlap = 120.406
+PHY-3002 : Step(194): len = 508726, overlap = 117.844
+PHY-3002 : Step(195): len = 511069, overlap = 114.281
+PHY-3002 : Step(196): len = 512644, overlap = 114.906
+PHY-3002 : Step(197): len = 513979, overlap = 114.875
+PHY-3002 : Step(198): len = 515197, overlap = 112.781
+PHY-3002 : Step(199): len = 515367, overlap = 112.906
+PHY-3002 : Step(200): len = 515820, overlap = 108.875
+PHY-3002 : Step(201): len = 516704, overlap = 111.188
+PHY-3002 : Step(202): len = 517142, overlap = 112.75
+PHY-3002 : Step(203): len = 517073, overlap = 107.688
+PHY-3002 : Step(204): len = 517115, overlap = 107.688
+PHY-3002 : Step(205): len = 517492, overlap = 112
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00191502
+PHY-3002 : Step(206): len = 520575, overlap = 107.125
+PHY-3002 : Step(207): len = 525493, overlap = 102.531
+PHY-3002 : Step(208): len = 526615, overlap = 100.969
+PHY-3002 : Step(209): len = 527208, overlap = 101.75
+PHY-3002 : Step(210): len = 528067, overlap = 102.562
+PHY-3002 : Step(211): len = 529197, overlap = 104.125
+PHY-3002 : Step(212): len = 530271, overlap = 102.125
+PHY-3002 : Step(213): len = 532302, overlap = 102.125
+PHY-3002 : Step(214): len = 533399, overlap = 103.219
+PHY-3002 : Step(215): len = 533896, overlap = 100.969
+PHY-3002 : Step(216): len = 534380, overlap = 98.9375
+PHY-3002 : Step(217): len = 534814, overlap = 96.5
+PHY-3002 : Step(218): len = 535308, overlap = 96.6875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.011669s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 705016, over cnt = 1536(4%), over = 7270, worst = 58
+PHY-1001 : End global iterations;  0.682636s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (130.5%)
+
+PHY-1001 : Congestion index: top1 = 78.64, top5 = 60.55, top10 = 51.46, top15 = 45.82.
+PHY-3001 : End congestion estimation;  0.905364s wall, 1.093750s user + 0.031250s system = 1.125000s CPU (124.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.834783s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143207
+PHY-3002 : Step(219): len = 646213, overlap = 36.1875
+PHY-3002 : Step(220): len = 644319, overlap = 34.0938
+PHY-3002 : Step(221): len = 639708, overlap = 39.3438
+PHY-3002 : Step(222): len = 639697, overlap = 46.5312
+PHY-3002 : Step(223): len = 642009, overlap = 48.0312
+PHY-3002 : Step(224): len = 641422, overlap = 47.8125
+PHY-3002 : Step(225): len = 640251, overlap = 44.2188
+PHY-3002 : Step(226): len = 638069, overlap = 35.5625
+PHY-3002 : Step(227): len = 635262, overlap = 23.5
+PHY-3002 : Step(228): len = 631544, overlap = 27.6875
+PHY-3002 : Step(229): len = 628555, overlap = 28.2812
+PHY-3002 : Step(230): len = 626551, overlap = 29.0312
+PHY-3002 : Step(231): len = 624331, overlap = 32.0312
+PHY-3002 : Step(232): len = 622629, overlap = 37.5625
+PHY-3002 : Step(233): len = 620279, overlap = 34.2812
+PHY-3002 : Step(234): len = 620152, overlap = 34.7812
+PHY-3002 : Step(235): len = 617309, overlap = 36.5625
+PHY-3002 : Step(236): len = 615563, overlap = 38.2188
+PHY-3002 : Step(237): len = 614250, overlap = 37.7812
+PHY-3002 : Step(238): len = 613568, overlap = 37.75
+PHY-3002 : Step(239): len = 611804, overlap = 36.5
+PHY-3002 : Step(240): len = 610938, overlap = 38.875
+PHY-3002 : Step(241): len = 609379, overlap = 39.9062
+PHY-3002 : Step(242): len = 608310, overlap = 39.2812
+PHY-3002 : Step(243): len = 607656, overlap = 40.0312
+PHY-3002 : Step(244): len = 605710, overlap = 41.8438
+PHY-3002 : Step(245): len = 605011, overlap = 44.0625
+PHY-3002 : Step(246): len = 603058, overlap = 43.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000286414
+PHY-3002 : Step(247): len = 605841, overlap = 43.4688
+PHY-3002 : Step(248): len = 609140, overlap = 42.8438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000469768
+PHY-3002 : Step(249): len = 613099, overlap = 42.2188
+PHY-3002 : Step(250): len = 620558, overlap = 41.125
+PHY-3002 : Step(251): len = 635556, overlap = 34.5938
+PHY-3002 : Step(252): len = 638311, overlap = 33.125
+PHY-3002 : Step(253): len = 640895, overlap = 31.9375
+PHY-3002 : Step(254): len = 642045, overlap = 32.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731656, over cnt = 2654(7%), over = 12250, worst = 64
+PHY-1001 : End global iterations;  1.686468s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (133.4%)
+
+PHY-1001 : Congestion index: top1 = 85.02, top5 = 66.04, top10 = 57.79, top15 = 52.68.
+PHY-3001 : End congestion estimation;  1.941448s wall, 2.484375s user + 0.015625s system = 2.500000s CPU (128.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.266385s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012412
+PHY-3002 : Step(255): len = 634493, overlap = 218.594
+PHY-3002 : Step(256): len = 633945, overlap = 186.656
+PHY-3002 : Step(257): len = 624281, overlap = 182.938
+PHY-3002 : Step(258): len = 620956, overlap = 176.469
+PHY-3002 : Step(259): len = 616979, overlap = 157.156
+PHY-3002 : Step(260): len = 613520, overlap = 135.344
+PHY-3002 : Step(261): len = 609779, overlap = 127.906
+PHY-3002 : Step(262): len = 608368, overlap = 127.469
+PHY-3002 : Step(263): len = 603987, overlap = 124.812
+PHY-3002 : Step(264): len = 601816, overlap = 126.906
+PHY-3002 : Step(265): len = 599563, overlap = 125.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00024824
+PHY-3002 : Step(266): len = 599695, overlap = 121.312
+PHY-3002 : Step(267): len = 601392, overlap = 118.5
+PHY-3002 : Step(268): len = 603887, overlap = 117.031
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000496481
+PHY-3002 : Step(269): len = 610653, overlap = 103.031
+PHY-3002 : Step(270): len = 617658, overlap = 96.375
+PHY-3002 : Step(271): len = 621957, overlap = 93.625
+PHY-3002 : Step(272): len = 624159, overlap = 89.5625
+PHY-3002 : Step(273): len = 623537, overlap = 89.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.400125s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (100.4%)
+
+RUN-1004 : used memory is 569 MB, reserved memory is 560 MB, peak memory is 706 MB
+OPT-1001 : Total overflow 402.84 peak overflow 2.69
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 966/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725272, over cnt = 2983(8%), over = 10954, worst = 26
+PHY-1001 : End global iterations;  1.156194s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (151.4%)
+
+PHY-1001 : Congestion index: top1 = 65.78, top5 = 55.57, top10 = 50.32, top15 = 46.98.
+PHY-1001 : End incremental global routing;  1.476210s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (139.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.886001s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.5%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 332 needs to be replaced
+PHY-3001 : design contains 17952 instances, 7503 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6004 pins
+PHY-3001 : Found 1238 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 648311
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16555/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741400, over cnt = 3040(8%), over = 11005, worst = 23
+PHY-1001 : End global iterations;  0.235303s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (152.7%)
+
+PHY-1001 : Congestion index: top1 = 66.03, top5 = 56.05, top10 = 50.69, top15 = 47.27.
+PHY-3001 : End congestion estimation;  0.487897s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (124.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85749, tnet num: 20354, tinst num: 17952, tnode num: 116398, tedge num: 137520.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.429176s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.6%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 628 MB, peak memory is 710 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.390328s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(274): len = 647207, overlap = 0.4375
+PHY-3002 : Step(275): len = 646813, overlap = 0.4375
+PHY-3002 : Step(276): len = 646562, overlap = 0.4375
+PHY-3002 : Step(277): len = 646329, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16669/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738224, over cnt = 3040(8%), over = 11020, worst = 23
+PHY-1001 : End global iterations;  0.187494s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (125.0%)
+
+PHY-1001 : Congestion index: top1 = 66.44, top5 = 56.30, top10 = 50.96, top15 = 47.56.
+PHY-3001 : End congestion estimation;  0.434127s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (111.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.906176s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000327438
+PHY-3002 : Step(278): len = 646336, overlap = 91.7812
+PHY-3002 : Step(279): len = 646431, overlap = 91.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000654876
+PHY-3002 : Step(280): len = 646360, overlap = 90.7812
+PHY-3002 : Step(281): len = 646751, overlap = 91.4375
+PHY-3001 : Final: Len = 646751, Over = 91.4375
+PHY-3001 : End incremental placement;  4.857263s wall, 5.046875s user + 0.203125s system = 5.250000s CPU (108.1%)
+
+OPT-1001 : Total overflow 409.66 peak overflow 2.69
+OPT-1001 : End high-fanout net optimization;  7.738956s wall, 8.609375s user + 0.218750s system = 8.828125s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 708, peak = 730.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16602/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740224, over cnt = 2991(8%), over = 9937, worst = 20
+PHY-1002 : len = 794184, over cnt = 2008(5%), over = 4860, worst = 18
+PHY-1002 : len = 828048, over cnt = 869(2%), over = 1996, worst = 17
+PHY-1002 : len = 852104, over cnt = 293(0%), over = 560, worst = 11
+PHY-1002 : len = 861664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.850138s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (136.8%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.28, top10 = 45.86, top15 = 43.68.
+OPT-1001 : End congestion update;  2.107112s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (132.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.796110s wall, 0.765625s user + 0.031250s system = 0.796875s CPU (100.1%)
+
+OPT-0007 : Start: WNS -1018 TNS -1565 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 96 cells processed and 6778 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 7 cells processed and 350 slack improved
+OPT-1001 : End global optimization;  2.948401s wall, 3.578125s user + 0.046875s system = 3.625000s CPU (122.9%)
+
+OPT-1001 : Current memory(MB): used = 690, reserve = 692, peak = 730.
+OPT-1001 : End physical optimization;  12.597660s wall, 14.187500s user + 0.281250s system = 14.468750s CPU (114.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7503 LUT to BLE ...
+SYN-4008 : Packed 7503 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6095 remaining SEQ's ...
+SYN-4005 : Packed 3693 SEQ with LUT/SLICE
+SYN-4006 : 969 single LUT's are left
+SYN-4006 : 2402 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9905/13636 primitive instances ...
+PHY-3001 : End packing;  1.641518s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6890 instances
+RUN-1001 : 3371 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17530 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5758 nets have [3 - 5] pins
+RUN-1001 : 1123 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6888 instances, 6742 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3560 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 657912, Over = 251
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7593/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 813888, over cnt = 1952(5%), over = 3148, worst = 7
+PHY-1002 : len = 821784, over cnt = 1230(3%), over = 1767, worst = 6
+PHY-1002 : len = 830520, over cnt = 722(2%), over = 1019, worst = 6
+PHY-1002 : len = 837008, over cnt = 475(1%), over = 681, worst = 6
+PHY-1002 : len = 845584, over cnt = 109(0%), over = 150, worst = 6
+PHY-1001 : End global iterations;  1.489145s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (145.8%)
+
+PHY-1001 : Congestion index: top1 = 57.65, top5 = 50.04, top10 = 45.96, top15 = 43.38.
+PHY-3001 : End congestion estimation;  1.877146s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (135.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6888, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.651109s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.4%)
+
+RUN-1004 : used memory is 607 MB, reserved memory is 606 MB, peak memory is 730 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.545102s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.75783e-05
+PHY-3002 : Step(282): len = 645888, overlap = 249.75
+PHY-3002 : Step(283): len = 639979, overlap = 245.5
+PHY-3002 : Step(284): len = 636462, overlap = 252.5
+PHY-3002 : Step(285): len = 633658, overlap = 252.5
+PHY-3002 : Step(286): len = 630887, overlap = 260.75
+PHY-3002 : Step(287): len = 627447, overlap = 264
+PHY-3002 : Step(288): len = 624149, overlap = 268
+PHY-3002 : Step(289): len = 621609, overlap = 270.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.51567e-05
+PHY-3002 : Step(290): len = 624770, overlap = 262
+PHY-3002 : Step(291): len = 629314, overlap = 250.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000190313
+PHY-3002 : Step(292): len = 633723, overlap = 244
+PHY-3002 : Step(293): len = 645927, overlap = 215.75
+PHY-3002 : Step(294): len = 648474, overlap = 213.5
+PHY-3002 : Step(295): len = 649771, overlap = 210.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.384293s wall, 0.250000s user + 0.546875s system = 0.796875s CPU (207.4%)
+
+PHY-3001 : Trial Legalized: Len = 725964
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 759/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840944, over cnt = 2673(7%), over = 4537, worst = 8
+PHY-1002 : len = 859824, over cnt = 1524(4%), over = 2187, worst = 7
+PHY-1002 : len = 878400, over cnt = 481(1%), over = 720, worst = 7
+PHY-1002 : len = 886200, over cnt = 114(0%), over = 174, worst = 7
+PHY-1002 : len = 888632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.342450s wall, 3.312500s user + 0.046875s system = 3.359375s CPU (143.4%)
+
+PHY-1001 : Congestion index: top1 = 53.23, top5 = 48.36, top10 = 45.74, top15 = 43.97.
+PHY-3001 : End congestion estimation;  2.792795s wall, 3.765625s user + 0.046875s system = 3.812500s CPU (136.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.883659s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160038
+PHY-3002 : Step(296): len = 699842, overlap = 38.5
+PHY-3002 : Step(297): len = 685178, overlap = 66.25
+PHY-3002 : Step(298): len = 673051, overlap = 91.75
+PHY-3002 : Step(299): len = 666043, overlap = 117.25
+PHY-3002 : Step(300): len = 661142, overlap = 139.5
+PHY-3002 : Step(301): len = 658978, overlap = 146.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320077
+PHY-3002 : Step(302): len = 665134, overlap = 141.75
+PHY-3002 : Step(303): len = 670968, overlap = 139.75
+PHY-3002 : Step(304): len = 671541, overlap = 147.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00063987
+PHY-3002 : Step(305): len = 676138, overlap = 148.5
+PHY-3002 : Step(306): len = 686491, overlap = 145
+PHY-3002 : Step(307): len = 691560, overlap = 146.25
+PHY-3002 : Step(308): len = 692892, overlap = 151.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.033670s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (92.8%)
+
+PHY-3001 : Legalized: Len = 721430, Over = 0
+PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.101764s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (107.5%)
+
+PHY-3001 : 612 instances has been re-located, deltaX = 269, deltaY = 342, maxDist = 3.
+PHY-3001 : Final: Len = 732202, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6891, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.838147s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (99.5%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 643 MB, peak memory is 730 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3456/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859832, over cnt = 2564(7%), over = 4193, worst = 8
+PHY-1002 : len = 875568, over cnt = 1522(4%), over = 2156, worst = 6
+PHY-1002 : len = 887848, over cnt = 801(2%), over = 1128, worst = 6
+PHY-1002 : len = 899448, over cnt = 263(0%), over = 372, worst = 5
+PHY-1002 : len = 905456, over cnt = 12(0%), over = 15, worst = 2
+PHY-1001 : End global iterations;  1.898895s wall, 3.000000s user + 0.000000s system = 3.000000s CPU (158.0%)
+
+PHY-1001 : Congestion index: top1 = 53.38, top5 = 48.42, top10 = 45.65, top15 = 43.88.
+PHY-1001 : End incremental global routing;  2.278653s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (148.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.853883s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (98.8%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6798 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735387
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15975/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909520, over cnt = 90(0%), over = 105, worst = 5
+PHY-1002 : len = 909704, over cnt = 43(0%), over = 44, worst = 2
+PHY-1002 : len = 910104, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 910456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.606926s wall, 0.640625s user + 0.031250s system = 0.671875s CPU (110.7%)
+
+PHY-1001 : Congestion index: top1 = 53.36, top5 = 48.44, top10 = 45.71, top15 = 43.96.
+PHY-3001 : End congestion estimation;  0.906467s wall, 0.921875s user + 0.046875s system = 0.968750s CPU (106.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.825465s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.1%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 657 MB, peak memory is 730 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.724727s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(309): len = 734474, overlap = 0
+PHY-3002 : Step(310): len = 734081, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15963/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908160, over cnt = 75(0%), over = 95, worst = 4
+PHY-1002 : len = 908296, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 908824, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 908920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.579257s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.44, top10 = 45.71, top15 = 43.95.
+PHY-3001 : End congestion estimation;  0.903977s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (105.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.857724s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333503
+PHY-3002 : Step(311): len = 734109, overlap = 1.5
+PHY-3002 : Step(312): len = 734482, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005654s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (276.4%)
+
+PHY-3001 : Legalized: Len = 734542, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058476s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.9%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 734724, Over = 0
+PHY-3001 : End incremental placement;  5.862522s wall, 6.125000s user + 0.093750s system = 6.218750s CPU (106.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.572296s wall, 10.906250s user + 0.109375s system = 11.015625s CPU (115.1%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 740, peak = 740.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15926/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909344, over cnt = 69(0%), over = 91, worst = 7
+PHY-1002 : len = 909360, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 909488, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 909728, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 909752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.825851s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (107.8%)
+
+PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.37, top10 = 45.65, top15 = 43.90.
+OPT-1001 : End congestion update;  1.136542s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (105.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.710160s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.2%)
+
+OPT-0007 : Start: WNS -1040 TNS -1754 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 739128, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060601s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.1%)
+
+PHY-3001 : 29 instances has been re-located, deltaX = 25, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 739360, Over = 0
+PHY-3001 : End incremental legalization;  0.380118s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.7%)
+
+OPT-0007 : Iter 1: improved WNS -990 TNS -1625 NUM_FEPS 2 with 35 cells processed and 11554 slack improved
+OPT-0007 : Iter 2: improved WNS -990 TNS -1625 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.370516s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (105.5%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 740, peak = 740.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.717246s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15842/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913768, over cnt = 81(0%), over = 92, worst = 4
+PHY-1002 : len = 913880, over cnt = 38(0%), over = 40, worst = 2
+PHY-1002 : len = 914048, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 914240, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 914256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.828398s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 53.56, top5 = 48.50, top10 = 45.71, top15 = 43.94.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.705181s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1040 TNS -1725 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.103448
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1040ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17552 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17552 nets
+OPT-1001 : End physical optimization;  16.693550s wall, 18.281250s user + 0.109375s system = 18.390625s CPU (110.2%)
+
+RUN-1003 : finish command "place" in  59.292799s wall, 87.812500s user + 5.906250s system = 93.718750s CPU (158.1%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 647 MB, peak memory is 740 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.678123s wall, 2.890625s user + 0.031250s system = 2.921875s CPU (174.1%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 647 MB, peak memory is 740 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6915 instances
+RUN-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17552 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5757 nets have [3 - 5] pins
+RUN-1001 : 1125 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.566751s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.7%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 622 MB, peak memory is 740 MB
+PHY-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847752, over cnt = 2759(7%), over = 4572, worst = 8
+PHY-1002 : len = 866784, over cnt = 1589(4%), over = 2268, worst = 8
+PHY-1002 : len = 884376, over cnt = 660(1%), over = 927, worst = 6
+PHY-1002 : len = 898472, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 898536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.811408s wall, 3.875000s user + 0.062500s system = 3.937500s CPU (140.1%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.37, top10 = 45.59, top15 = 43.67.
+PHY-1001 : End global routing;  3.130373s wall, 4.187500s user + 0.062500s system = 4.250000s CPU (135.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 705, reserve = 712, peak = 740.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 981, reserve = 987, peak = 981.
+PHY-1001 : End build detailed router design. 4.037322s wall, 4.031250s user + 0.015625s system = 4.046875s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.055823s wall, 5.046875s user + 0.000000s system = 5.046875s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.405393s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1024, peak = 1018.
+PHY-1001 : End phase 1; 5.473249s wall, 5.468750s user + 0.000000s system = 5.468750s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.31459e+06, over cnt = 1958(0%), over = 1962, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1035, reserve = 1040, peak = 1035.
+PHY-1001 : End initial routed; 21.312394s wall, 54.171875s user + 0.265625s system = 54.437500s CPU (255.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.084   |  -4.275   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.181891s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1053, peak = 1047.
+PHY-1001 : End phase 2; 24.494358s wall, 57.343750s user + 0.265625s system = 57.609375s CPU (235.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.235728s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.4%)
+
+PHY-1022 : len = 2.31459e+06, over cnt = 1960(0%), over = 1964, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.494742s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (101.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.28119e+06, over cnt = 722(0%), over = 722, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.230700s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (184.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.27972e+06, over cnt = 191(0%), over = 191, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.578101s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (181.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28086e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.446764s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (118.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28087e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.230835s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.203896s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (107.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.257216s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.189281s wall, 2.171875s user + 0.015625s system = 2.187500s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1149, reserve = 1159, peak = 1149.
+PHY-1001 : End phase 3; 9.037253s wall, 10.609375s user + 0.015625s system = 10.625000s CPU (117.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.177166s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.0%)
+
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.512961s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (79.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.945ns, -4.090ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.192721s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.298443s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1168, peak = 1158.
+PHY-1001 : End phase 4; 6.031518s wall, 5.921875s user + 0.000000s system = 5.921875s CPU (98.2%)
+
+PHY-1003 : Routed, final wirelength = 2.28094e+06
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1170, peak = 1160.
+PHY-1001 : End export database. 0.138576s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.5%)
+
+PHY-1001 : End detail routing;  49.597829s wall, 83.890625s user + 0.296875s system = 84.187500s CPU (169.7%)
+
+RUN-1003 : finish command "route" in  55.343928s wall, 90.687500s user + 0.375000s system = 91.062500s CPU (164.5%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1099 MB, peak memory is 1160 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10273   out of  19600   52.41%
+#reg                     9368   out of  19600   47.80%
+#le                     12618
+  #lut only              3250   out of  12618   25.76%
+  #reg only              2345   out of  12618   18.58%
+  #lut&reg               7023   out of  12618   55.66%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1810
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1425
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1358
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               942
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    143
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_277.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/reg10_syn_122.f1                         3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12618  |9246    |1027    |9400    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |561    |454     |23      |449     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |110    |93      |4       |93      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |32     |32      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |9       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |781    |337     |96      |583     |0       |0       |
+|    u_ADconfig                |AD_config            |191    |118     |25      |142     |0       |0       |
+|    u_gen_sp                  |gen_sp               |269    |158     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |379     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |129     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |259    |144     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3071   |2501    |306     |2076    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |137     |17      |133     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2855   |2346    |289     |1907    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |1       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |9      |4       |0       |9       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2407   |1999    |253     |1544    |22      |0       |
+|        channelPart           |channel_part_8478    |143    |136     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |41      |0       |0       |
+|        ram_switch            |ram_switch           |1870   |1532    |197     |1149    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |247    |220     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |31     |28      |3       |17      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |965    |654     |170     |661     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |658    |658     |0       |365     |0       |0       |
+|        read_ram_i            |read_ram             |300    |255     |44      |195     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |240    |200     |40      |155     |0       |0       |
+|          read_ram_data       |read_ram_data        |56     |51      |4       |36      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |337    |245     |36      |283     |3       |0       |
+|        u0_soft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3397   |2743    |349     |2088    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |189    |127     |17      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |3178   |2597    |332     |1911    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2741   |2251    |290     |1561    |22      |1       |
+|        channelPart           |channel_part_8478    |243    |238     |3       |137     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |2023   |1671    |197     |1132    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |219    |192     |27      |98      |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |6       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |6       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|          insert              |insert               |982    |658     |170     |674     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |822    |821     |0       |360     |0       |0       |
+|        read_ram_i            |read_ram_rev         |378    |263     |81      |214     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |311    |226     |73      |165     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |67     |37      |8       |49      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9907  
+    #2         2       3801  
+    #3         3       1374  
+    #4         4       579   
+    #5        5-10     1189  
+    #6       11-50     584   
+    #7       51-100     22   
+    #8        >500      1    
+  Average     2.92           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.070200s wall, 3.515625s user + 0.031250s system = 3.546875s CPU (171.3%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1101 MB, peak memory is 1160 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.596267s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.8%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1103 MB, peak memory is 1160 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.429763s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (99.4%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1108 MB, peak memory is 1160 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6913
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17552, pip num: 172527
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 589
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 479670 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.245918s wall, 64.453125s user + 0.140625s system = 64.593750s CPU (630.4%)
+
+RUN-1004 : used memory is 1262 MB, reserved memory is 1267 MB, peak memory is 1378 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_094627.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_101346.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_101346.log
new file mode 100644
index 0000000..c87fe9c
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_101346.log
@@ -0,0 +1,1854 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:13:46 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.166014s wall, 2.031250s user + 0.140625s system = 2.171875s CPU (100.3%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.134371s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.2%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 513 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.909639s wall, 1.859375s user + 0.046875s system = 1.906250s CPU (99.8%)
+
+PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.250363s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (124.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28668e+06, overlap = 484.094
+PHY-3002 : Step(2): len = 1.18318e+06, overlap = 557.375
+PHY-3002 : Step(3): len = 843931, overlap = 601.625
+PHY-3002 : Step(4): len = 791874, overlap = 624.344
+PHY-3002 : Step(5): len = 609615, overlap = 754.969
+PHY-3002 : Step(6): len = 529112, overlap = 805.719
+PHY-3002 : Step(7): len = 456874, overlap = 912.031
+PHY-3002 : Step(8): len = 425331, overlap = 995.844
+PHY-3002 : Step(9): len = 378282, overlap = 1057.66
+PHY-3002 : Step(10): len = 340965, overlap = 1115.97
+PHY-3002 : Step(11): len = 297218, overlap = 1185.28
+PHY-3002 : Step(12): len = 272422, overlap = 1214.28
+PHY-3002 : Step(13): len = 251103, overlap = 1252.66
+PHY-3002 : Step(14): len = 233830, overlap = 1297.31
+PHY-3002 : Step(15): len = 207240, overlap = 1327.09
+PHY-3002 : Step(16): len = 192315, overlap = 1358.84
+PHY-3002 : Step(17): len = 174239, overlap = 1404.44
+PHY-3002 : Step(18): len = 162009, overlap = 1423.03
+PHY-3002 : Step(19): len = 147685, overlap = 1465.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2036e-06
+PHY-3002 : Step(20): len = 148424, overlap = 1423.66
+PHY-3002 : Step(21): len = 179191, overlap = 1304.53
+PHY-3002 : Step(22): len = 190294, overlap = 1232.22
+PHY-3002 : Step(23): len = 199319, overlap = 1189.78
+PHY-3002 : Step(24): len = 198566, overlap = 1179.34
+PHY-3002 : Step(25): len = 198247, overlap = 1163.12
+PHY-3002 : Step(26): len = 195020, overlap = 1157.25
+PHY-3002 : Step(27): len = 194648, overlap = 1158.09
+PHY-3002 : Step(28): len = 193918, overlap = 1142.66
+PHY-3002 : Step(29): len = 192851, overlap = 1149.03
+PHY-3002 : Step(30): len = 191764, overlap = 1148.06
+PHY-3002 : Step(31): len = 190566, overlap = 1168.28
+PHY-3002 : Step(32): len = 188829, overlap = 1145.56
+PHY-3002 : Step(33): len = 188125, overlap = 1149.47
+PHY-3002 : Step(34): len = 187128, overlap = 1136
+PHY-3002 : Step(35): len = 186806, overlap = 1099.56
+PHY-3002 : Step(36): len = 184419, overlap = 1073.5
+PHY-3002 : Step(37): len = 183688, overlap = 1074.06
+PHY-3002 : Step(38): len = 181963, overlap = 1075.84
+PHY-3002 : Step(39): len = 180821, overlap = 1100.16
+PHY-3002 : Step(40): len = 180049, overlap = 1107.62
+PHY-3002 : Step(41): len = 178563, overlap = 1115.78
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.40721e-06
+PHY-3002 : Step(42): len = 182212, overlap = 1088.72
+PHY-3002 : Step(43): len = 192003, overlap = 1041.94
+PHY-3002 : Step(44): len = 195313, overlap = 996.5
+PHY-3002 : Step(45): len = 200502, overlap = 971.938
+PHY-3002 : Step(46): len = 203704, overlap = 964.062
+PHY-3002 : Step(47): len = 207043, overlap = 946.125
+PHY-3002 : Step(48): len = 207363, overlap = 916.281
+PHY-3002 : Step(49): len = 207868, overlap = 907.031
+PHY-3002 : Step(50): len = 206820, overlap = 918.844
+PHY-3002 : Step(51): len = 206254, overlap = 931.125
+PHY-3002 : Step(52): len = 204603, overlap = 938.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.81441e-06
+PHY-3002 : Step(53): len = 211487, overlap = 931
+PHY-3002 : Step(54): len = 228174, overlap = 895.562
+PHY-3002 : Step(55): len = 237150, overlap = 803.812
+PHY-3002 : Step(56): len = 242854, overlap = 767.344
+PHY-3002 : Step(57): len = 244809, overlap = 750.625
+PHY-3002 : Step(58): len = 247200, overlap = 746.219
+PHY-3002 : Step(59): len = 246762, overlap = 749.906
+PHY-3002 : Step(60): len = 246476, overlap = 758.188
+PHY-3002 : Step(61): len = 245504, overlap = 776.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.62883e-06
+PHY-3002 : Step(62): len = 259270, overlap = 736.844
+PHY-3002 : Step(63): len = 280310, overlap = 622.125
+PHY-3002 : Step(64): len = 289452, overlap = 594.688
+PHY-3002 : Step(65): len = 292950, overlap = 596.625
+PHY-3002 : Step(66): len = 291834, overlap = 562.719
+PHY-3002 : Step(67): len = 289272, overlap = 547.375
+PHY-3002 : Step(68): len = 287091, overlap = 546.344
+PHY-3002 : Step(69): len = 287110, overlap = 528.281
+PHY-3002 : Step(70): len = 287591, overlap = 509.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.92577e-05
+PHY-3002 : Step(71): len = 306070, overlap = 487.531
+PHY-3002 : Step(72): len = 321535, overlap = 471.406
+PHY-3002 : Step(73): len = 327807, overlap = 437.219
+PHY-3002 : Step(74): len = 332649, overlap = 431.281
+PHY-3002 : Step(75): len = 331947, overlap = 424.094
+PHY-3002 : Step(76): len = 332519, overlap = 428.656
+PHY-3002 : Step(77): len = 332226, overlap = 415.594
+PHY-3002 : Step(78): len = 331189, overlap = 397.969
+PHY-3002 : Step(79): len = 330580, overlap = 386.438
+PHY-3002 : Step(80): len = 331430, overlap = 383.438
+PHY-3002 : Step(81): len = 332546, overlap = 365.906
+PHY-3002 : Step(82): len = 332833, overlap = 367.281
+PHY-3002 : Step(83): len = 331822, overlap = 367.219
+PHY-3002 : Step(84): len = 332233, overlap = 356.375
+PHY-3002 : Step(85): len = 331344, overlap = 344.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.85153e-05
+PHY-3002 : Step(86): len = 350518, overlap = 322.5
+PHY-3002 : Step(87): len = 360328, overlap = 306.594
+PHY-3002 : Step(88): len = 357880, overlap = 317.406
+PHY-3002 : Step(89): len = 358822, overlap = 305.344
+PHY-3002 : Step(90): len = 363911, overlap = 302.406
+PHY-3002 : Step(91): len = 367835, overlap = 304.938
+PHY-3002 : Step(92): len = 363522, overlap = 317.188
+PHY-3002 : Step(93): len = 365018, overlap = 310.875
+PHY-3002 : Step(94): len = 367761, overlap = 310.25
+PHY-3002 : Step(95): len = 369860, overlap = 319.094
+PHY-3002 : Step(96): len = 365177, overlap = 314.25
+PHY-3002 : Step(97): len = 363436, overlap = 316.188
+PHY-3002 : Step(98): len = 364963, overlap = 322.094
+PHY-3002 : Step(99): len = 366885, overlap = 314
+PHY-3002 : Step(100): len = 363632, overlap = 313.844
+PHY-3002 : Step(101): len = 363549, overlap = 310.25
+PHY-3002 : Step(102): len = 364192, overlap = 304.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.70306e-05
+PHY-3002 : Step(103): len = 382186, overlap = 300.719
+PHY-3002 : Step(104): len = 393320, overlap = 290.438
+PHY-3002 : Step(105): len = 390061, overlap = 265.469
+PHY-3002 : Step(106): len = 389428, overlap = 253.938
+PHY-3002 : Step(107): len = 394384, overlap = 237.344
+PHY-3002 : Step(108): len = 399627, overlap = 227.5
+PHY-3002 : Step(109): len = 397812, overlap = 236.219
+PHY-3002 : Step(110): len = 399415, overlap = 243.656
+PHY-3002 : Step(111): len = 402607, overlap = 242.125
+PHY-3002 : Step(112): len = 404322, overlap = 239.312
+PHY-3002 : Step(113): len = 400761, overlap = 240.844
+PHY-3002 : Step(114): len = 399368, overlap = 243.125
+PHY-3002 : Step(115): len = 401595, overlap = 233.938
+PHY-3002 : Step(116): len = 404676, overlap = 239.812
+PHY-3002 : Step(117): len = 400962, overlap = 247.219
+PHY-3002 : Step(118): len = 400739, overlap = 247.281
+PHY-3002 : Step(119): len = 402377, overlap = 239.938
+PHY-3002 : Step(120): len = 404242, overlap = 244.781
+PHY-3002 : Step(121): len = 401723, overlap = 248.594
+PHY-3002 : Step(122): len = 401871, overlap = 252.375
+PHY-3002 : Step(123): len = 404195, overlap = 251.375
+PHY-3002 : Step(124): len = 406140, overlap = 257.312
+PHY-3002 : Step(125): len = 403540, overlap = 259.656
+PHY-3002 : Step(126): len = 403245, overlap = 259.188
+PHY-3002 : Step(127): len = 403984, overlap = 258
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154061
+PHY-3002 : Step(128): len = 419164, overlap = 244.906
+PHY-3002 : Step(129): len = 428463, overlap = 233.125
+PHY-3002 : Step(130): len = 426829, overlap = 217.812
+PHY-3002 : Step(131): len = 427102, overlap = 211.844
+PHY-3002 : Step(132): len = 429947, overlap = 210.938
+PHY-3002 : Step(133): len = 431921, overlap = 206.281
+PHY-3002 : Step(134): len = 429822, overlap = 204.156
+PHY-3002 : Step(135): len = 430225, overlap = 212.344
+PHY-3002 : Step(136): len = 432285, overlap = 210.5
+PHY-3002 : Step(137): len = 434226, overlap = 207.281
+PHY-3002 : Step(138): len = 433644, overlap = 199.531
+PHY-3002 : Step(139): len = 434785, overlap = 208.406
+PHY-3002 : Step(140): len = 436011, overlap = 203.75
+PHY-3002 : Step(141): len = 437222, overlap = 200.469
+PHY-3002 : Step(142): len = 436221, overlap = 201.188
+PHY-3002 : Step(143): len = 436724, overlap = 207.406
+PHY-3002 : Step(144): len = 437985, overlap = 207.875
+PHY-3002 : Step(145): len = 439045, overlap = 207.375
+PHY-3002 : Step(146): len = 437923, overlap = 207.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000297449
+PHY-3002 : Step(147): len = 447213, overlap = 201.406
+PHY-3002 : Step(148): len = 454452, overlap = 203.656
+PHY-3002 : Step(149): len = 454959, overlap = 198.281
+PHY-3002 : Step(150): len = 455780, overlap = 191
+PHY-3002 : Step(151): len = 458270, overlap = 186.562
+PHY-3002 : Step(152): len = 459849, overlap = 184
+PHY-3002 : Step(153): len = 458838, overlap = 186.688
+PHY-3002 : Step(154): len = 459485, overlap = 181.969
+PHY-3002 : Step(155): len = 461789, overlap = 184.562
+PHY-3002 : Step(156): len = 463496, overlap = 173.094
+PHY-3002 : Step(157): len = 462326, overlap = 171.438
+PHY-3002 : Step(158): len = 462656, overlap = 170.656
+PHY-3002 : Step(159): len = 464690, overlap = 167.469
+PHY-3002 : Step(160): len = 466201, overlap = 171.656
+PHY-3002 : Step(161): len = 465166, overlap = 165.188
+PHY-3002 : Step(162): len = 465218, overlap = 167.594
+PHY-3002 : Step(163): len = 466623, overlap = 165.719
+PHY-3002 : Step(164): len = 467287, overlap = 162.25
+PHY-3002 : Step(165): len = 466412, overlap = 161.688
+PHY-3002 : Step(166): len = 466327, overlap = 158.469
+PHY-3002 : Step(167): len = 467295, overlap = 161.75
+PHY-3002 : Step(168): len = 468354, overlap = 160.594
+PHY-3002 : Step(169): len = 468124, overlap = 155.656
+PHY-3002 : Step(170): len = 468614, overlap = 159.062
+PHY-3002 : Step(171): len = 469394, overlap = 153.281
+PHY-3002 : Step(172): len = 469789, overlap = 151.75
+PHY-3002 : Step(173): len = 470169, overlap = 135.656
+PHY-3002 : Step(174): len = 471663, overlap = 137.594
+PHY-3002 : Step(175): len = 472466, overlap = 133.844
+PHY-3002 : Step(176): len = 473025, overlap = 132.812
+PHY-3002 : Step(177): len = 472951, overlap = 135.25
+PHY-3002 : Step(178): len = 473084, overlap = 136.938
+PHY-3002 : Step(179): len = 473356, overlap = 135.25
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000566962
+PHY-3002 : Step(180): len = 479949, overlap = 132.312
+PHY-3002 : Step(181): len = 485650, overlap = 134
+PHY-3002 : Step(182): len = 486958, overlap = 125.781
+PHY-3002 : Step(183): len = 488201, overlap = 126
+PHY-3002 : Step(184): len = 490404, overlap = 126.844
+PHY-3002 : Step(185): len = 492125, overlap = 131.5
+PHY-3002 : Step(186): len = 492854, overlap = 128.094
+PHY-3002 : Step(187): len = 494116, overlap = 125.406
+PHY-3002 : Step(188): len = 496340, overlap = 126.312
+PHY-3002 : Step(189): len = 497988, overlap = 123.688
+PHY-3002 : Step(190): len = 498041, overlap = 122.812
+PHY-3002 : Step(191): len = 498102, overlap = 120.5
+PHY-3002 : Step(192): len = 498689, overlap = 124.594
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109183
+PHY-3002 : Step(193): len = 502699, overlap = 120.406
+PHY-3002 : Step(194): len = 508726, overlap = 117.844
+PHY-3002 : Step(195): len = 511069, overlap = 114.281
+PHY-3002 : Step(196): len = 512644, overlap = 114.906
+PHY-3002 : Step(197): len = 513979, overlap = 114.875
+PHY-3002 : Step(198): len = 515197, overlap = 112.781
+PHY-3002 : Step(199): len = 515367, overlap = 112.906
+PHY-3002 : Step(200): len = 515820, overlap = 108.875
+PHY-3002 : Step(201): len = 516704, overlap = 111.188
+PHY-3002 : Step(202): len = 517142, overlap = 112.75
+PHY-3002 : Step(203): len = 517073, overlap = 107.688
+PHY-3002 : Step(204): len = 517115, overlap = 107.688
+PHY-3002 : Step(205): len = 517492, overlap = 112
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00191502
+PHY-3002 : Step(206): len = 520575, overlap = 107.125
+PHY-3002 : Step(207): len = 525493, overlap = 102.531
+PHY-3002 : Step(208): len = 526615, overlap = 100.969
+PHY-3002 : Step(209): len = 527208, overlap = 101.75
+PHY-3002 : Step(210): len = 528067, overlap = 102.562
+PHY-3002 : Step(211): len = 529197, overlap = 104.125
+PHY-3002 : Step(212): len = 530271, overlap = 102.125
+PHY-3002 : Step(213): len = 532302, overlap = 102.125
+PHY-3002 : Step(214): len = 533399, overlap = 103.219
+PHY-3002 : Step(215): len = 533896, overlap = 100.969
+PHY-3002 : Step(216): len = 534380, overlap = 98.9375
+PHY-3002 : Step(217): len = 534814, overlap = 96.5
+PHY-3002 : Step(218): len = 535308, overlap = 96.6875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.010808s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (144.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 705016, over cnt = 1536(4%), over = 7270, worst = 58
+PHY-1001 : End global iterations;  0.711680s wall, 0.937500s user + 0.046875s system = 0.984375s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 78.64, top5 = 60.55, top10 = 51.46, top15 = 45.82.
+PHY-3001 : End congestion estimation;  0.943588s wall, 1.171875s user + 0.062500s system = 1.234375s CPU (130.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.843555s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143207
+PHY-3002 : Step(219): len = 646213, overlap = 36.1875
+PHY-3002 : Step(220): len = 644319, overlap = 34.0938
+PHY-3002 : Step(221): len = 639708, overlap = 39.3438
+PHY-3002 : Step(222): len = 639697, overlap = 46.5312
+PHY-3002 : Step(223): len = 642009, overlap = 48.0312
+PHY-3002 : Step(224): len = 641422, overlap = 47.8125
+PHY-3002 : Step(225): len = 640251, overlap = 44.2188
+PHY-3002 : Step(226): len = 638069, overlap = 35.5625
+PHY-3002 : Step(227): len = 635262, overlap = 23.5
+PHY-3002 : Step(228): len = 631544, overlap = 27.6875
+PHY-3002 : Step(229): len = 628555, overlap = 28.2812
+PHY-3002 : Step(230): len = 626551, overlap = 29.0312
+PHY-3002 : Step(231): len = 624331, overlap = 32.0312
+PHY-3002 : Step(232): len = 622629, overlap = 37.5625
+PHY-3002 : Step(233): len = 620279, overlap = 34.2812
+PHY-3002 : Step(234): len = 620152, overlap = 34.7812
+PHY-3002 : Step(235): len = 617309, overlap = 36.5625
+PHY-3002 : Step(236): len = 615563, overlap = 38.2188
+PHY-3002 : Step(237): len = 614250, overlap = 37.7812
+PHY-3002 : Step(238): len = 613568, overlap = 37.75
+PHY-3002 : Step(239): len = 611804, overlap = 36.5
+PHY-3002 : Step(240): len = 610938, overlap = 38.875
+PHY-3002 : Step(241): len = 609379, overlap = 39.9062
+PHY-3002 : Step(242): len = 608310, overlap = 39.2812
+PHY-3002 : Step(243): len = 607656, overlap = 40.0312
+PHY-3002 : Step(244): len = 605710, overlap = 41.8438
+PHY-3002 : Step(245): len = 605011, overlap = 44.0625
+PHY-3002 : Step(246): len = 603058, overlap = 43.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000286414
+PHY-3002 : Step(247): len = 605841, overlap = 43.4688
+PHY-3002 : Step(248): len = 609140, overlap = 42.8438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000469768
+PHY-3002 : Step(249): len = 613099, overlap = 42.2188
+PHY-3002 : Step(250): len = 620558, overlap = 41.125
+PHY-3002 : Step(251): len = 635556, overlap = 34.5938
+PHY-3002 : Step(252): len = 638311, overlap = 33.125
+PHY-3002 : Step(253): len = 640895, overlap = 31.9375
+PHY-3002 : Step(254): len = 642045, overlap = 32.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731656, over cnt = 2654(7%), over = 12250, worst = 64
+PHY-1001 : End global iterations;  1.699224s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 85.02, top5 = 66.04, top10 = 57.79, top15 = 52.68.
+PHY-3001 : End congestion estimation;  1.957687s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (129.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868584s wall, 0.828125s user + 0.046875s system = 0.875000s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012412
+PHY-3002 : Step(255): len = 634493, overlap = 218.594
+PHY-3002 : Step(256): len = 633945, overlap = 186.656
+PHY-3002 : Step(257): len = 624281, overlap = 182.938
+PHY-3002 : Step(258): len = 620956, overlap = 176.469
+PHY-3002 : Step(259): len = 616979, overlap = 157.156
+PHY-3002 : Step(260): len = 613520, overlap = 135.344
+PHY-3002 : Step(261): len = 609779, overlap = 127.906
+PHY-3002 : Step(262): len = 608368, overlap = 127.469
+PHY-3002 : Step(263): len = 603987, overlap = 124.812
+PHY-3002 : Step(264): len = 601816, overlap = 126.906
+PHY-3002 : Step(265): len = 599563, overlap = 125.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00024824
+PHY-3002 : Step(266): len = 599695, overlap = 121.312
+PHY-3002 : Step(267): len = 601392, overlap = 118.5
+PHY-3002 : Step(268): len = 603887, overlap = 117.031
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000496481
+PHY-3002 : Step(269): len = 610653, overlap = 103.031
+PHY-3002 : Step(270): len = 617658, overlap = 96.375
+PHY-3002 : Step(271): len = 621957, overlap = 93.625
+PHY-3002 : Step(272): len = 624159, overlap = 89.5625
+PHY-3002 : Step(273): len = 623537, overlap = 89.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.438621s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (99.9%)
+
+RUN-1004 : used memory is 572 MB, reserved memory is 562 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 402.84 peak overflow 2.69
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 966/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725272, over cnt = 2983(8%), over = 10954, worst = 26
+PHY-1001 : End global iterations;  1.136247s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (147.1%)
+
+PHY-1001 : Congestion index: top1 = 65.78, top5 = 55.57, top10 = 50.32, top15 = 46.98.
+PHY-1001 : End incremental global routing;  1.461568s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (137.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.896043s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.4%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 332 needs to be replaced
+PHY-3001 : design contains 17952 instances, 7503 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6004 pins
+PHY-3001 : Found 1238 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 648311
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16555/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741400, over cnt = 3040(8%), over = 11005, worst = 23
+PHY-1001 : End global iterations;  0.229839s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 66.03, top5 = 56.05, top10 = 50.69, top15 = 47.27.
+PHY-3001 : End congestion estimation;  0.495635s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (116.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85749, tnet num: 20354, tinst num: 17952, tnode num: 116398, tedge num: 137520.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.464309s wall, 1.421875s user + 0.046875s system = 1.468750s CPU (100.3%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 613 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.413103s wall, 2.281250s user + 0.125000s system = 2.406250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(274): len = 647207, overlap = 0.4375
+PHY-3002 : Step(275): len = 646813, overlap = 0.4375
+PHY-3002 : Step(276): len = 646562, overlap = 0.4375
+PHY-3002 : Step(277): len = 646329, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16669/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738224, over cnt = 3040(8%), over = 11020, worst = 23
+PHY-1001 : End global iterations;  0.202072s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (123.7%)
+
+PHY-1001 : Congestion index: top1 = 66.44, top5 = 56.30, top10 = 50.96, top15 = 47.56.
+PHY-3001 : End congestion estimation;  0.461944s wall, 0.500000s user + 0.015625s system = 0.515625s CPU (111.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.929000s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000327438
+PHY-3002 : Step(278): len = 646336, overlap = 91.7812
+PHY-3002 : Step(279): len = 646431, overlap = 91.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000654876
+PHY-3002 : Step(280): len = 646360, overlap = 90.7812
+PHY-3002 : Step(281): len = 646751, overlap = 91.4375
+PHY-3001 : Final: Len = 646751, Over = 91.4375
+PHY-3001 : End incremental placement;  4.949409s wall, 5.312500s user + 0.281250s system = 5.593750s CPU (113.0%)
+
+OPT-1001 : Total overflow 409.66 peak overflow 2.69
+OPT-1001 : End high-fanout net optimization;  7.847362s wall, 8.890625s user + 0.281250s system = 9.171875s CPU (116.9%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 711, peak = 733.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16602/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740224, over cnt = 2991(8%), over = 9937, worst = 20
+PHY-1002 : len = 794184, over cnt = 2008(5%), over = 4860, worst = 18
+PHY-1002 : len = 828048, over cnt = 869(2%), over = 1996, worst = 17
+PHY-1002 : len = 852104, over cnt = 293(0%), over = 560, worst = 11
+PHY-1002 : len = 861664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.840112s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (140.1%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.28, top10 = 45.86, top15 = 43.68.
+OPT-1001 : End congestion update;  2.102260s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (134.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.792407s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.6%)
+
+OPT-0007 : Start: WNS -1018 TNS -1565 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 96 cells processed and 6778 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 7 cells processed and 350 slack improved
+OPT-1001 : End global optimization;  2.939430s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (124.9%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 689, peak = 733.
+OPT-1001 : End physical optimization;  12.718807s wall, 14.406250s user + 0.343750s system = 14.750000s CPU (116.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7503 LUT to BLE ...
+SYN-4008 : Packed 7503 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6095 remaining SEQ's ...
+SYN-4005 : Packed 3693 SEQ with LUT/SLICE
+SYN-4006 : 969 single LUT's are left
+SYN-4006 : 2402 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9905/13636 primitive instances ...
+PHY-3001 : End packing;  1.594259s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6890 instances
+RUN-1001 : 3371 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17530 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5758 nets have [3 - 5] pins
+RUN-1001 : 1123 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6888 instances, 6742 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3560 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 657912, Over = 251
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7593/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 813888, over cnt = 1952(5%), over = 3148, worst = 7
+PHY-1002 : len = 821784, over cnt = 1230(3%), over = 1767, worst = 6
+PHY-1002 : len = 830520, over cnt = 722(2%), over = 1019, worst = 6
+PHY-1002 : len = 837008, over cnt = 475(1%), over = 681, worst = 6
+PHY-1002 : len = 845584, over cnt = 109(0%), over = 150, worst = 6
+PHY-1001 : End global iterations;  1.480725s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (148.8%)
+
+PHY-1001 : Congestion index: top1 = 57.65, top5 = 50.04, top10 = 45.96, top15 = 43.38.
+PHY-3001 : End congestion estimation;  1.864224s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (139.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6888, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.589775s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.3%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 607 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.440174s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.75783e-05
+PHY-3002 : Step(282): len = 645888, overlap = 249.75
+PHY-3002 : Step(283): len = 639979, overlap = 245.5
+PHY-3002 : Step(284): len = 636462, overlap = 252.5
+PHY-3002 : Step(285): len = 633658, overlap = 252.5
+PHY-3002 : Step(286): len = 630887, overlap = 260.75
+PHY-3002 : Step(287): len = 627447, overlap = 264
+PHY-3002 : Step(288): len = 624149, overlap = 268
+PHY-3002 : Step(289): len = 621609, overlap = 270.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.51567e-05
+PHY-3002 : Step(290): len = 624770, overlap = 262
+PHY-3002 : Step(291): len = 629314, overlap = 250.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000190313
+PHY-3002 : Step(292): len = 633723, overlap = 244
+PHY-3002 : Step(293): len = 645927, overlap = 215.75
+PHY-3002 : Step(294): len = 648474, overlap = 213.5
+PHY-3002 : Step(295): len = 649771, overlap = 210.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.387720s wall, 0.390625s user + 0.531250s system = 0.921875s CPU (237.8%)
+
+PHY-3001 : Trial Legalized: Len = 725964
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 759/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840944, over cnt = 2673(7%), over = 4537, worst = 8
+PHY-1002 : len = 859824, over cnt = 1524(4%), over = 2187, worst = 7
+PHY-1002 : len = 878400, over cnt = 481(1%), over = 720, worst = 7
+PHY-1002 : len = 886200, over cnt = 114(0%), over = 174, worst = 7
+PHY-1002 : len = 888632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.361613s wall, 3.468750s user + 0.031250s system = 3.500000s CPU (148.2%)
+
+PHY-1001 : Congestion index: top1 = 53.23, top5 = 48.36, top10 = 45.74, top15 = 43.97.
+PHY-3001 : End congestion estimation;  2.812142s wall, 3.906250s user + 0.031250s system = 3.937500s CPU (140.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.856794s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160038
+PHY-3002 : Step(296): len = 699842, overlap = 38.5
+PHY-3002 : Step(297): len = 685178, overlap = 66.25
+PHY-3002 : Step(298): len = 673051, overlap = 91.75
+PHY-3002 : Step(299): len = 666043, overlap = 117.25
+PHY-3002 : Step(300): len = 661142, overlap = 139.5
+PHY-3002 : Step(301): len = 658978, overlap = 146.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320077
+PHY-3002 : Step(302): len = 665134, overlap = 141.75
+PHY-3002 : Step(303): len = 670968, overlap = 139.75
+PHY-3002 : Step(304): len = 671541, overlap = 147.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00063987
+PHY-3002 : Step(305): len = 676138, overlap = 148.5
+PHY-3002 : Step(306): len = 686491, overlap = 145
+PHY-3002 : Step(307): len = 691560, overlap = 146.25
+PHY-3002 : Step(308): len = 692892, overlap = 151.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.031834s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (147.2%)
+
+PHY-3001 : Legalized: Len = 721430, Over = 0
+PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.102043s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (107.2%)
+
+PHY-3001 : 612 instances has been re-located, deltaX = 269, deltaY = 342, maxDist = 3.
+PHY-3001 : Final: Len = 732202, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6891, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.808366s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (100.2%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 639 MB, peak memory is 733 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3456/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859832, over cnt = 2564(7%), over = 4193, worst = 8
+PHY-1002 : len = 875568, over cnt = 1522(4%), over = 2156, worst = 6
+PHY-1002 : len = 887848, over cnt = 801(2%), over = 1128, worst = 6
+PHY-1002 : len = 899448, over cnt = 263(0%), over = 372, worst = 5
+PHY-1002 : len = 905456, over cnt = 12(0%), over = 15, worst = 2
+PHY-1001 : End global iterations;  1.810662s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (157.1%)
+
+PHY-1001 : Congestion index: top1 = 53.38, top5 = 48.42, top10 = 45.65, top15 = 43.88.
+PHY-1001 : End incremental global routing;  2.168099s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (148.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.849406s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.3%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6798 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735387
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15975/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909520, over cnt = 90(0%), over = 105, worst = 5
+PHY-1002 : len = 909704, over cnt = 43(0%), over = 44, worst = 2
+PHY-1002 : len = 910104, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 910456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.602310s wall, 0.609375s user + 0.031250s system = 0.640625s CPU (106.4%)
+
+PHY-1001 : Congestion index: top1 = 53.36, top5 = 48.44, top10 = 45.71, top15 = 43.96.
+PHY-3001 : End congestion estimation;  0.913209s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (104.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.853489s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (100.3%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 657 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.811511s wall, 2.781250s user + 0.031250s system = 2.812500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(309): len = 734474, overlap = 0
+PHY-3002 : Step(310): len = 734081, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15963/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908160, over cnt = 75(0%), over = 95, worst = 4
+PHY-1002 : len = 908296, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 908824, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 908920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.561995s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (40.0%)
+
+PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.44, top10 = 45.71, top15 = 43.95.
+PHY-3001 : End congestion estimation;  1.870989s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (49.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.852195s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333503
+PHY-3002 : Step(311): len = 734109, overlap = 1.5
+PHY-3002 : Step(312): len = 734482, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005621s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (278.0%)
+
+PHY-3001 : Legalized: Len = 734542, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060887s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.6%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 734724, Over = 0
+PHY-3001 : End incremental placement;  6.910587s wall, 6.140625s user + 0.156250s system = 6.296875s CPU (91.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.508764s wall, 10.765625s user + 0.187500s system = 10.953125s CPU (104.2%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 739, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15926/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909344, over cnt = 69(0%), over = 91, worst = 7
+PHY-1002 : len = 909360, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 909488, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 909728, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 909752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.768854s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.6%)
+
+PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.37, top10 = 45.65, top15 = 43.90.
+OPT-1001 : End congestion update;  1.078340s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (101.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.719111s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1040 TNS -1754 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 739128, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061223s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (76.6%)
+
+PHY-3001 : 29 instances has been re-located, deltaX = 25, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 739360, Over = 0
+PHY-3001 : End incremental legalization;  0.376444s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.6%)
+
+OPT-0007 : Iter 1: improved WNS -990 TNS -1625 NUM_FEPS 2 with 35 cells processed and 11554 slack improved
+OPT-0007 : Iter 2: improved WNS -990 TNS -1625 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.310855s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 739, peak = 742.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.715623s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15842/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913768, over cnt = 81(0%), over = 92, worst = 4
+PHY-1002 : len = 913880, over cnt = 38(0%), over = 40, worst = 2
+PHY-1002 : len = 914048, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 914240, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 914256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.759288s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 53.56, top5 = 48.50, top10 = 45.71, top15 = 43.94.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.744197s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1040 TNS -1725 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.103448
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1040ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17552 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17552 nets
+OPT-1001 : End physical optimization;  17.517753s wall, 17.781250s user + 0.218750s system = 18.000000s CPU (102.8%)
+
+RUN-1003 : finish command "place" in  58.108534s wall, 85.328125s user + 6.484375s system = 91.812500s CPU (158.0%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 608 MB, peak memory is 742 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.694098s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (173.4%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 609 MB, peak memory is 742 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6915 instances
+RUN-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17552 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5757 nets have [3 - 5] pins
+RUN-1001 : 1125 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.571304s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.4%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 634 MB, peak memory is 742 MB
+PHY-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847752, over cnt = 2759(7%), over = 4572, worst = 8
+PHY-1002 : len = 866784, over cnt = 1589(4%), over = 2268, worst = 8
+PHY-1002 : len = 884376, over cnt = 660(1%), over = 927, worst = 6
+PHY-1002 : len = 898472, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 898536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.786165s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.37, top10 = 45.59, top15 = 43.67.
+PHY-1001 : End global routing;  3.102727s wall, 4.031250s user + 0.031250s system = 4.062500s CPU (130.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 714, reserve = 719, peak = 742.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 987, reserve = 991, peak = 987.
+PHY-1001 : End build detailed router design. 3.955857s wall, 3.875000s user + 0.093750s system = 3.968750s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.820234s wall, 4.812500s user + 0.000000s system = 4.812500s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.401733s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.1%)
+
+PHY-1001 : Current memory(MB): used = 1023, reserve = 1028, peak = 1023.
+PHY-1001 : End phase 1; 5.233667s wall, 5.234375s user + 0.000000s system = 5.234375s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.31459e+06, over cnt = 1958(0%), over = 1962, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1037, reserve = 1040, peak = 1037.
+PHY-1001 : End initial routed; 21.038035s wall, 54.015625s user + 0.328125s system = 54.343750s CPU (258.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.084   |  -4.275   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.257336s wall, 3.250000s user + 0.015625s system = 3.265625s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1048, peak = 1044.
+PHY-1001 : End phase 2; 24.295442s wall, 57.265625s user + 0.343750s system = 57.609375s CPU (237.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.141703s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.2%)
+
+PHY-1022 : len = 2.31459e+06, over cnt = 1960(0%), over = 1964, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.395659s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.28119e+06, over cnt = 722(0%), over = 722, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.277288s wall, 2.281250s user + 0.015625s system = 2.296875s CPU (179.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.27972e+06, over cnt = 191(0%), over = 191, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.597151s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (185.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28086e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.443774s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (116.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28087e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.233645s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (93.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.210436s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (96.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.244542s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.228109s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1158, peak = 1151.
+PHY-1001 : End phase 3; 9.030322s wall, 10.593750s user + 0.046875s system = 10.640625s CPU (117.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.145104s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.9%)
+
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.388057s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.945ns, -4.090ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.248707s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.295070s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1168, peak = 1160.
+PHY-1001 : End phase 4; 5.959596s wall, 5.953125s user + 0.000000s system = 5.953125s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.28094e+06
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1170, peak = 1162.
+PHY-1001 : End export database. 0.138856s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.3%)
+
+PHY-1001 : End detail routing;  49.000489s wall, 83.437500s user + 0.484375s system = 83.921875s CPU (171.3%)
+
+RUN-1003 : finish command "route" in  54.715682s wall, 90.078125s user + 0.531250s system = 90.609375s CPU (165.6%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1100 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10273   out of  19600   52.41%
+#reg                     9368   out of  19600   47.80%
+#le                     12618
+  #lut only              3250   out of  12618   25.76%
+  #reg only              2345   out of  12618   18.58%
+  #lut&reg               7023   out of  12618   55.66%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1810
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1425
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1358
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               942
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    143
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_277.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/reg10_syn_122.f1                         3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12618  |9246    |1027    |9400    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |561    |454     |23      |449     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |110    |93      |4       |93      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |32     |32      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |9       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |781    |337     |96      |583     |0       |0       |
+|    u_ADconfig                |AD_config            |191    |118     |25      |142     |0       |0       |
+|    u_gen_sp                  |gen_sp               |269    |158     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |379     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |129     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |259    |144     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3071   |2501    |306     |2076    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |137     |17      |133     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2855   |2346    |289     |1907    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |1       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |9      |4       |0       |9       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2407   |1999    |253     |1544    |22      |0       |
+|        channelPart           |channel_part_8478    |143    |136     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |41      |0       |0       |
+|        ram_switch            |ram_switch           |1870   |1532    |197     |1149    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |247    |220     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |31     |28      |3       |17      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |965    |654     |170     |661     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |658    |658     |0       |365     |0       |0       |
+|        read_ram_i            |read_ram             |300    |255     |44      |195     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |240    |200     |40      |155     |0       |0       |
+|          read_ram_data       |read_ram_data        |56     |51      |4       |36      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |337    |245     |36      |283     |3       |0       |
+|        u0_soft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3397   |2743    |349     |2088    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |189    |127     |17      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |3178   |2597    |332     |1911    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2741   |2251    |290     |1561    |22      |1       |
+|        channelPart           |channel_part_8478    |243    |238     |3       |137     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |2023   |1671    |197     |1132    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |219    |192     |27      |98      |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |6       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |6       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|          insert              |insert               |982    |658     |170     |674     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |822    |821     |0       |360     |0       |0       |
+|        read_ram_i            |read_ram_rev         |378    |263     |81      |214     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |311    |226     |73      |165     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |67     |37      |8       |49      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9907  
+    #2         2       3801  
+    #3         3       1374  
+    #4         4       579   
+    #5        5-10     1189  
+    #6       11-50     584   
+    #7       51-100     22   
+    #8        >500      1    
+  Average     2.92           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.074691s wall, 3.515625s user + 0.015625s system = 3.531250s CPU (170.2%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1101 MB, peak memory is 1162 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.609631s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.0%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1105 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.624386s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (98.1%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1107 MB, peak memory is 1162 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6913
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17552, pip num: 172527
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 589
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 479670 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.403554s wall, 59.765625s user + 0.187500s system = 59.953125s CPU (637.6%)
+
+RUN-1004 : used memory is 1261 MB, reserved memory is 1265 MB, peak memory is 1377 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_101346.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102305.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102305.log
new file mode 100644
index 0000000..51b9bc8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102305.log
@@ -0,0 +1,1927 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:23:05 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.130906s wall, 2.015625s user + 0.109375s system = 2.125000s CPU (99.7%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.130210s wall, 1.093750s user + 0.031250s system = 1.125000s CPU (99.5%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 513 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.909113s wall, 1.875000s user + 0.031250s system = 1.906250s CPU (99.9%)
+
+PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09942e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.130244s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28632e+06, overlap = 485.281
+PHY-3002 : Step(2): len = 1.18266e+06, overlap = 557.375
+PHY-3002 : Step(3): len = 843127, overlap = 600.25
+PHY-3002 : Step(4): len = 790805, overlap = 624.094
+PHY-3002 : Step(5): len = 608450, overlap = 755.875
+PHY-3002 : Step(6): len = 528193, overlap = 805.094
+PHY-3002 : Step(7): len = 455855, overlap = 910.219
+PHY-3002 : Step(8): len = 424140, overlap = 996.562
+PHY-3002 : Step(9): len = 378064, overlap = 1058.25
+PHY-3002 : Step(10): len = 343837, overlap = 1105.38
+PHY-3002 : Step(11): len = 297304, overlap = 1186.62
+PHY-3002 : Step(12): len = 274141, overlap = 1211.5
+PHY-3002 : Step(13): len = 246465, overlap = 1252.81
+PHY-3002 : Step(14): len = 236341, overlap = 1285.16
+PHY-3002 : Step(15): len = 207644, overlap = 1329.84
+PHY-3002 : Step(16): len = 196819, overlap = 1344.47
+PHY-3002 : Step(17): len = 173985, overlap = 1401.88
+PHY-3002 : Step(18): len = 169394, overlap = 1435.94
+PHY-3002 : Step(19): len = 151327, overlap = 1462.91
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.16723e-06
+PHY-3002 : Step(20): len = 152530, overlap = 1432.44
+PHY-3002 : Step(21): len = 180620, overlap = 1291.78
+PHY-3002 : Step(22): len = 191900, overlap = 1209
+PHY-3002 : Step(23): len = 199393, overlap = 1167.41
+PHY-3002 : Step(24): len = 198645, overlap = 1143.94
+PHY-3002 : Step(25): len = 196864, overlap = 1131.94
+PHY-3002 : Step(26): len = 195075, overlap = 1095.47
+PHY-3002 : Step(27): len = 193218, overlap = 1105.47
+PHY-3002 : Step(28): len = 190778, overlap = 1139.38
+PHY-3002 : Step(29): len = 189927, overlap = 1147.38
+PHY-3002 : Step(30): len = 187244, overlap = 1137
+PHY-3002 : Step(31): len = 185602, overlap = 1131.91
+PHY-3002 : Step(32): len = 183873, overlap = 1131.41
+PHY-3002 : Step(33): len = 182640, overlap = 1131.16
+PHY-3002 : Step(34): len = 180797, overlap = 1131.5
+PHY-3002 : Step(35): len = 179462, overlap = 1119.81
+PHY-3002 : Step(36): len = 178319, overlap = 1116.03
+PHY-3002 : Step(37): len = 177180, overlap = 1116.28
+PHY-3002 : Step(38): len = 177033, overlap = 1112.03
+PHY-3002 : Step(39): len = 176532, overlap = 1097.44
+PHY-3002 : Step(40): len = 176493, overlap = 1085.81
+PHY-3002 : Step(41): len = 176336, overlap = 1108.59
+PHY-3002 : Step(42): len = 175946, overlap = 1130.56
+PHY-3002 : Step(43): len = 174367, overlap = 1144.34
+PHY-3002 : Step(44): len = 172779, overlap = 1143.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.33446e-06
+PHY-3002 : Step(45): len = 176556, overlap = 1137.53
+PHY-3002 : Step(46): len = 185757, overlap = 1110.88
+PHY-3002 : Step(47): len = 189446, overlap = 1035.25
+PHY-3002 : Step(48): len = 194150, overlap = 996.594
+PHY-3002 : Step(49): len = 197202, overlap = 985.938
+PHY-3002 : Step(50): len = 199539, overlap = 983.312
+PHY-3002 : Step(51): len = 200452, overlap = 983.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.66892e-06
+PHY-3002 : Step(52): len = 206091, overlap = 965.094
+PHY-3002 : Step(53): len = 222252, overlap = 890.438
+PHY-3002 : Step(54): len = 234225, overlap = 847.875
+PHY-3002 : Step(55): len = 242752, overlap = 818.062
+PHY-3002 : Step(56): len = 246287, overlap = 773.25
+PHY-3002 : Step(57): len = 246843, overlap = 771.844
+PHY-3002 : Step(58): len = 245393, overlap = 758.625
+PHY-3002 : Step(59): len = 244621, overlap = 763.438
+PHY-3002 : Step(60): len = 243455, overlap = 768.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.33783e-06
+PHY-3002 : Step(61): len = 255306, overlap = 731
+PHY-3002 : Step(62): len = 273834, overlap = 634.375
+PHY-3002 : Step(63): len = 283289, overlap = 564.219
+PHY-3002 : Step(64): len = 288526, overlap = 559.094
+PHY-3002 : Step(65): len = 289137, overlap = 551.375
+PHY-3002 : Step(66): len = 289743, overlap = 557.969
+PHY-3002 : Step(67): len = 287238, overlap = 576.906
+PHY-3002 : Step(68): len = 287052, overlap = 560.969
+PHY-3002 : Step(69): len = 287226, overlap = 538.031
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.86757e-05
+PHY-3002 : Step(70): len = 305564, overlap = 504.281
+PHY-3002 : Step(71): len = 325591, overlap = 491.375
+PHY-3002 : Step(72): len = 334999, overlap = 464.656
+PHY-3002 : Step(73): len = 337376, overlap = 450.375
+PHY-3002 : Step(74): len = 334659, overlap = 460.438
+PHY-3002 : Step(75): len = 333350, overlap = 436.844
+PHY-3002 : Step(76): len = 331343, overlap = 436.656
+PHY-3002 : Step(77): len = 331735, overlap = 437.812
+PHY-3002 : Step(78): len = 331873, overlap = 429.656
+PHY-3002 : Step(79): len = 332365, overlap = 433
+PHY-3002 : Step(80): len = 332065, overlap = 414.812
+PHY-3002 : Step(81): len = 331880, overlap = 404.594
+PHY-3002 : Step(82): len = 331498, overlap = 381.562
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.73513e-05
+PHY-3002 : Step(83): len = 350133, overlap = 345.438
+PHY-3002 : Step(84): len = 361710, overlap = 321.344
+PHY-3002 : Step(85): len = 362901, overlap = 329.938
+PHY-3002 : Step(86): len = 365350, overlap = 325.688
+PHY-3002 : Step(87): len = 365175, overlap = 337.094
+PHY-3002 : Step(88): len = 366497, overlap = 323.844
+PHY-3002 : Step(89): len = 365824, overlap = 318.688
+PHY-3002 : Step(90): len = 368372, overlap = 307.094
+PHY-3002 : Step(91): len = 370195, overlap = 301.625
+PHY-3002 : Step(92): len = 371442, overlap = 276.906
+PHY-3002 : Step(93): len = 368800, overlap = 284.719
+PHY-3002 : Step(94): len = 369009, overlap = 277.594
+PHY-3002 : Step(95): len = 370367, overlap = 277.469
+PHY-3002 : Step(96): len = 371804, overlap = 273.344
+PHY-3002 : Step(97): len = 369949, overlap = 271.531
+PHY-3002 : Step(98): len = 370922, overlap = 270.219
+PHY-3002 : Step(99): len = 370684, overlap = 273.812
+PHY-3002 : Step(100): len = 372227, overlap = 281.562
+PHY-3002 : Step(101): len = 369318, overlap = 281.531
+PHY-3002 : Step(102): len = 369023, overlap = 286.125
+PHY-3002 : Step(103): len = 368420, overlap = 285.062
+PHY-3002 : Step(104): len = 369994, overlap = 286.531
+PHY-3002 : Step(105): len = 368789, overlap = 290.625
+PHY-3002 : Step(106): len = 369057, overlap = 293.5
+PHY-3002 : Step(107): len = 368088, overlap = 290.875
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.47027e-05
+PHY-3002 : Step(108): len = 387580, overlap = 270.219
+PHY-3002 : Step(109): len = 396382, overlap = 253.469
+PHY-3002 : Step(110): len = 392732, overlap = 268.656
+PHY-3002 : Step(111): len = 393339, overlap = 264.031
+PHY-3002 : Step(112): len = 396621, overlap = 258.75
+PHY-3002 : Step(113): len = 399538, overlap = 253.156
+PHY-3002 : Step(114): len = 398774, overlap = 266.344
+PHY-3002 : Step(115): len = 401438, overlap = 263.812
+PHY-3002 : Step(116): len = 404361, overlap = 246.562
+PHY-3002 : Step(117): len = 407015, overlap = 242.281
+PHY-3002 : Step(118): len = 404192, overlap = 239.406
+PHY-3002 : Step(119): len = 404317, overlap = 235.438
+PHY-3002 : Step(120): len = 405579, overlap = 233.062
+PHY-3002 : Step(121): len = 406698, overlap = 239.719
+PHY-3002 : Step(122): len = 405342, overlap = 239.594
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000149269
+PHY-3002 : Step(123): len = 420184, overlap = 225.219
+PHY-3002 : Step(124): len = 428398, overlap = 220.875
+PHY-3002 : Step(125): len = 426033, overlap = 223.438
+PHY-3002 : Step(126): len = 426598, overlap = 212.688
+PHY-3002 : Step(127): len = 431052, overlap = 207.094
+PHY-3002 : Step(128): len = 434536, overlap = 200.594
+PHY-3002 : Step(129): len = 431557, overlap = 196.938
+PHY-3002 : Step(130): len = 431615, overlap = 201.75
+PHY-3002 : Step(131): len = 434002, overlap = 197.875
+PHY-3002 : Step(132): len = 436195, overlap = 201.75
+PHY-3002 : Step(133): len = 433765, overlap = 198.125
+PHY-3002 : Step(134): len = 433322, overlap = 175.062
+PHY-3002 : Step(135): len = 435217, overlap = 179.125
+PHY-3002 : Step(136): len = 437154, overlap = 179.906
+PHY-3002 : Step(137): len = 434607, overlap = 179.062
+PHY-3002 : Step(138): len = 434552, overlap = 178.031
+PHY-3002 : Step(139): len = 436309, overlap = 183.562
+PHY-3002 : Step(140): len = 437086, overlap = 185.469
+PHY-3002 : Step(141): len = 434987, overlap = 180.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000270013
+PHY-3002 : Step(142): len = 443383, overlap = 195.312
+PHY-3002 : Step(143): len = 450596, overlap = 191
+PHY-3002 : Step(144): len = 451232, overlap = 188.438
+PHY-3002 : Step(145): len = 453286, overlap = 194.094
+PHY-3002 : Step(146): len = 456914, overlap = 188.344
+PHY-3002 : Step(147): len = 458871, overlap = 188.562
+PHY-3002 : Step(148): len = 458359, overlap = 183.344
+PHY-3002 : Step(149): len = 459245, overlap = 180.562
+PHY-3002 : Step(150): len = 461115, overlap = 182.281
+PHY-3002 : Step(151): len = 462488, overlap = 173.719
+PHY-3002 : Step(152): len = 461372, overlap = 174.656
+PHY-3002 : Step(153): len = 461355, overlap = 173.125
+PHY-3002 : Step(154): len = 462222, overlap = 170.281
+PHY-3002 : Step(155): len = 462880, overlap = 168.312
+PHY-3002 : Step(156): len = 461794, overlap = 165.094
+PHY-3002 : Step(157): len = 461846, overlap = 166.406
+PHY-3002 : Step(158): len = 463099, overlap = 167.562
+PHY-3002 : Step(159): len = 463796, overlap = 171.656
+PHY-3002 : Step(160): len = 462976, overlap = 164.625
+PHY-3002 : Step(161): len = 463205, overlap = 162.5
+PHY-3002 : Step(162): len = 464188, overlap = 164.312
+PHY-3002 : Step(163): len = 464336, overlap = 164.5
+PHY-3002 : Step(164): len = 463702, overlap = 165.438
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000500351
+PHY-3002 : Step(165): len = 470023, overlap = 164.281
+PHY-3002 : Step(166): len = 478426, overlap = 149.875
+PHY-3002 : Step(167): len = 480733, overlap = 147.594
+PHY-3002 : Step(168): len = 483162, overlap = 142.344
+PHY-3002 : Step(169): len = 485865, overlap = 138.906
+PHY-3002 : Step(170): len = 487087, overlap = 136.781
+PHY-3002 : Step(171): len = 486716, overlap = 135.312
+PHY-3002 : Step(172): len = 487084, overlap = 132.281
+PHY-3002 : Step(173): len = 488753, overlap = 134.875
+PHY-3002 : Step(174): len = 489656, overlap = 136.875
+PHY-3002 : Step(175): len = 488994, overlap = 136.906
+PHY-3002 : Step(176): len = 489036, overlap = 135.094
+PHY-3002 : Step(177): len = 489984, overlap = 131.531
+PHY-3002 : Step(178): len = 490650, overlap = 132.719
+PHY-3002 : Step(179): len = 489958, overlap = 130.5
+PHY-3002 : Step(180): len = 489958, overlap = 128.375
+PHY-3002 : Step(181): len = 490694, overlap = 129.125
+PHY-3002 : Step(182): len = 490952, overlap = 127.406
+PHY-3002 : Step(183): len = 490717, overlap = 126.375
+PHY-3002 : Step(184): len = 492116, overlap = 117.344
+PHY-3002 : Step(185): len = 493545, overlap = 120.062
+PHY-3002 : Step(186): len = 493932, overlap = 120.875
+PHY-3002 : Step(187): len = 493306, overlap = 118.125
+PHY-3002 : Step(188): len = 493368, overlap = 114
+PHY-3002 : Step(189): len = 493910, overlap = 119.969
+PHY-3002 : Step(190): len = 494180, overlap = 119.625
+PHY-3002 : Step(191): len = 493453, overlap = 113.188
+PHY-3002 : Step(192): len = 493304, overlap = 116.875
+PHY-3002 : Step(193): len = 495330, overlap = 111.469
+PHY-3002 : Step(194): len = 497509, overlap = 106.812
+PHY-3002 : Step(195): len = 496089, overlap = 107.719
+PHY-3002 : Step(196): len = 495648, overlap = 102.844
+PHY-3002 : Step(197): len = 495620, overlap = 113.531
+PHY-3002 : Step(198): len = 495684, overlap = 115.656
+PHY-3002 : Step(199): len = 495165, overlap = 113.344
+PHY-3002 : Step(200): len = 495130, overlap = 113.344
+PHY-3002 : Step(201): len = 495305, overlap = 114.156
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00094834
+PHY-3002 : Step(202): len = 499652, overlap = 118.688
+PHY-3002 : Step(203): len = 506272, overlap = 109.594
+PHY-3002 : Step(204): len = 509023, overlap = 105.094
+PHY-3002 : Step(205): len = 510956, overlap = 107.875
+PHY-3002 : Step(206): len = 512456, overlap = 105.969
+PHY-3002 : Step(207): len = 513932, overlap = 109.906
+PHY-3002 : Step(208): len = 514642, overlap = 111
+PHY-3002 : Step(209): len = 515151, overlap = 109.812
+PHY-3002 : Step(210): len = 515738, overlap = 117.469
+PHY-3002 : Step(211): len = 516612, overlap = 120.875
+PHY-3002 : Step(212): len = 517216, overlap = 120.781
+PHY-3002 : Step(213): len = 517566, overlap = 116.781
+PHY-3002 : Step(214): len = 517565, overlap = 117.344
+PHY-3002 : Step(215): len = 517715, overlap = 114.562
+PHY-3002 : Step(216): len = 517772, overlap = 114
+PHY-3002 : Step(217): len = 517758, overlap = 114.312
+PHY-3002 : Step(218): len = 517466, overlap = 116.875
+PHY-3002 : Step(219): len = 517368, overlap = 116.094
+PHY-3002 : Step(220): len = 517353, overlap = 113.844
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00177633
+PHY-3002 : Step(221): len = 519735, overlap = 112.656
+PHY-3002 : Step(222): len = 522404, overlap = 111.844
+PHY-3002 : Step(223): len = 523222, overlap = 107.781
+PHY-3002 : Step(224): len = 523864, overlap = 104.719
+PHY-3002 : Step(225): len = 525091, overlap = 103.875
+PHY-3002 : Step(226): len = 525980, overlap = 104.188
+PHY-3002 : Step(227): len = 526269, overlap = 102.469
+PHY-3002 : Step(228): len = 526419, overlap = 101.812
+PHY-3002 : Step(229): len = 526727, overlap = 102.062
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00287579
+PHY-3002 : Step(230): len = 528973, overlap = 102.062
+PHY-3002 : Step(231): len = 535225, overlap = 95.6562
+PHY-3002 : Step(232): len = 537340, overlap = 93.6562
+PHY-3002 : Step(233): len = 539016, overlap = 90.2812
+PHY-3002 : Step(234): len = 540400, overlap = 92
+PHY-3002 : Step(235): len = 541128, overlap = 94.25
+PHY-3002 : Step(236): len = 541018, overlap = 92
+PHY-3002 : Step(237): len = 541086, overlap = 91.9375
+PHY-3002 : Step(238): len = 541783, overlap = 91.1875
+PHY-3002 : Step(239): len = 542223, overlap = 89.7812
+PHY-3002 : Step(240): len = 542146, overlap = 89.7812
+PHY-3002 : Step(241): len = 542200, overlap = 89.7812
+PHY-3002 : Step(242): len = 542841, overlap = 89.7812
+PHY-3002 : Step(243): len = 543081, overlap = 89.7812
+PHY-3002 : Step(244): len = 542845, overlap = 88.5312
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.012595s wall, 0.031250s user + 0.031250s system = 0.062500s CPU (496.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715072, over cnt = 1569(4%), over = 7254, worst = 41
+PHY-1001 : End global iterations;  0.672361s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (146.4%)
+
+PHY-1001 : Congestion index: top1 = 72.31, top5 = 58.11, top10 = 50.26, top15 = 45.42.
+PHY-3001 : End congestion estimation;  0.892362s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (134.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.873663s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000135405
+PHY-3002 : Step(245): len = 647330, overlap = 35.3125
+PHY-3002 : Step(246): len = 645544, overlap = 31.6562
+PHY-3002 : Step(247): len = 642361, overlap = 29.0625
+PHY-3002 : Step(248): len = 642147, overlap = 35.4688
+PHY-3002 : Step(249): len = 645045, overlap = 38.625
+PHY-3002 : Step(250): len = 640881, overlap = 36.4062
+PHY-3002 : Step(251): len = 636744, overlap = 35.3125
+PHY-3002 : Step(252): len = 634323, overlap = 34.75
+PHY-3002 : Step(253): len = 631973, overlap = 36.2812
+PHY-3002 : Step(254): len = 628947, overlap = 29.2812
+PHY-3002 : Step(255): len = 626358, overlap = 24.2188
+PHY-3002 : Step(256): len = 625558, overlap = 23.5625
+PHY-3002 : Step(257): len = 623859, overlap = 27.2188
+PHY-3002 : Step(258): len = 622742, overlap = 27.4062
+PHY-3002 : Step(259): len = 621778, overlap = 28.6875
+PHY-3002 : Step(260): len = 620455, overlap = 27.1875
+PHY-3002 : Step(261): len = 620051, overlap = 31.875
+PHY-3002 : Step(262): len = 619857, overlap = 37.2188
+PHY-3002 : Step(263): len = 618471, overlap = 42.0625
+PHY-3002 : Step(264): len = 616900, overlap = 41.9688
+PHY-3002 : Step(265): len = 616820, overlap = 41.1562
+PHY-3002 : Step(266): len = 615024, overlap = 41.0625
+PHY-3002 : Step(267): len = 613746, overlap = 37.0938
+PHY-3002 : Step(268): len = 612186, overlap = 34.5938
+PHY-3002 : Step(269): len = 611627, overlap = 35.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000270811
+PHY-3002 : Step(270): len = 612355, overlap = 33.5625
+PHY-3002 : Step(271): len = 614595, overlap = 33.5312
+PHY-3002 : Step(272): len = 619235, overlap = 34.2812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000541621
+PHY-3002 : Step(273): len = 627014, overlap = 37.7188
+PHY-3002 : Step(274): len = 640209, overlap = 38.125
+PHY-3002 : Step(275): len = 654007, overlap = 41.5
+PHY-3002 : Step(276): len = 655415, overlap = 42.1562
+PHY-3002 : Step(277): len = 656222, overlap = 43.625
+PHY-3002 : Step(278): len = 654931, overlap = 39.4688
+PHY-3002 : Step(279): len = 654269, overlap = 35.0625
+PHY-3002 : Step(280): len = 653527, overlap = 32.4375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00105112
+PHY-3002 : Step(281): len = 659681, overlap = 32.4062
+PHY-3002 : Step(282): len = 666757, overlap = 33.0625
+PHY-3002 : Step(283): len = 669570, overlap = 33.9062
+PHY-3002 : Step(284): len = 674560, overlap = 31.6875
+PHY-3002 : Step(285): len = 679438, overlap = 31.25
+PHY-3002 : Step(286): len = 682500, overlap = 32.8125
+PHY-3002 : Step(287): len = 684056, overlap = 33.7188
+PHY-3002 : Step(288): len = 683442, overlap = 35.625
+PHY-3002 : Step(289): len = 683043, overlap = 34.9375
+PHY-3002 : Step(290): len = 682605, overlap = 35.4688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00182141
+PHY-3002 : Step(291): len = 685655, overlap = 35.625
+PHY-3002 : Step(292): len = 692673, overlap = 34.375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 57/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 779800, over cnt = 2761(7%), over = 12663, worst = 41
+PHY-1001 : End global iterations;  1.613666s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (143.3%)
+
+PHY-1001 : Congestion index: top1 = 85.37, top5 = 69.16, top10 = 60.86, top15 = 55.44.
+PHY-3001 : End congestion estimation;  1.870796s wall, 2.546875s user + 0.015625s system = 2.562500s CPU (137.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.870821s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126338
+PHY-3002 : Step(293): len = 679169, overlap = 218.594
+PHY-3002 : Step(294): len = 676584, overlap = 178.281
+PHY-3002 : Step(295): len = 658441, overlap = 167.781
+PHY-3002 : Step(296): len = 649766, overlap = 158.594
+PHY-3002 : Step(297): len = 641422, overlap = 144.438
+PHY-3002 : Step(298): len = 635219, overlap = 134.938
+PHY-3002 : Step(299): len = 627754, overlap = 132.188
+PHY-3002 : Step(300): len = 622948, overlap = 124.75
+PHY-3002 : Step(301): len = 617931, overlap = 115.719
+PHY-3002 : Step(302): len = 612951, overlap = 117.562
+PHY-3002 : Step(303): len = 611101, overlap = 126.781
+PHY-3002 : Step(304): len = 606535, overlap = 121.281
+PHY-3002 : Step(305): len = 603971, overlap = 120.5
+PHY-3002 : Step(306): len = 599876, overlap = 116.188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000252677
+PHY-3002 : Step(307): len = 600766, overlap = 110.719
+PHY-3002 : Step(308): len = 601951, overlap = 109.688
+PHY-3002 : Step(309): len = 604820, overlap = 105.344
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000505353
+PHY-3002 : Step(310): len = 610053, overlap = 99.0312
+PHY-3002 : Step(311): len = 615941, overlap = 95.75
+PHY-3002 : Step(312): len = 619105, overlap = 91.8125
+PHY-3002 : Step(313): len = 619171, overlap = 92.25
+PHY-3002 : Step(314): len = 619269, overlap = 89.0938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00101071
+PHY-3002 : Step(315): len = 622165, overlap = 85.5
+PHY-3002 : Step(316): len = 626321, overlap = 82.2812
+PHY-3002 : Step(317): len = 628926, overlap = 76.3438
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.442105s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.8%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 563 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 384.25 peak overflow 3.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 608/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730336, over cnt = 3081(8%), over = 11182, worst = 28
+PHY-1001 : End global iterations;  1.387109s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (147.6%)
+
+PHY-1001 : Congestion index: top1 = 68.88, top5 = 56.00, top10 = 50.34, top15 = 46.94.
+PHY-1001 : End incremental global routing;  1.717651s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (138.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.902055s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.7%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 326 needs to be replaced
+PHY-3001 : design contains 17946 instances, 7496 luts, 9229 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6011 pins
+PHY-3001 : Found 1237 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 653450
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16692/20526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 745144, over cnt = 3100(8%), over = 11183, worst = 28
+PHY-1001 : End global iterations;  0.248699s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (150.8%)
+
+PHY-1001 : Congestion index: top1 = 68.36, top5 = 55.93, top10 = 50.45, top15 = 47.10.
+PHY-3001 : End congestion estimation;  0.497614s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (125.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85732, tnet num: 20348, tinst num: 17946, tnode num: 116397, tedge num: 137498.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.471328s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.8%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 618 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.757884s wall, 2.703125s user + 0.046875s system = 2.750000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(318): len = 652491, overlap = 1.15625
+PHY-3002 : Step(319): len = 652003, overlap = 1.15625
+PHY-3002 : Step(320): len = 651731, overlap = 1.15625
+PHY-3002 : Step(321): len = 651544, overlap = 1.15625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16784/20526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 742104, over cnt = 3099(8%), over = 11252, worst = 28
+PHY-1001 : End global iterations;  0.199276s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 69.05, top5 = 56.22, top10 = 50.68, top15 = 47.30.
+PHY-3001 : End congestion estimation;  0.440974s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (120.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.984479s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000525728
+PHY-3002 : Step(322): len = 651394, overlap = 78.8438
+PHY-3002 : Step(323): len = 651319, overlap = 78.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00105146
+PHY-3002 : Step(324): len = 651806, overlap = 77.9375
+PHY-3002 : Step(325): len = 652508, overlap = 77.7812
+PHY-3001 : Final: Len = 652508, Over = 77.7812
+PHY-3001 : End incremental placement;  5.330097s wall, 5.750000s user + 0.250000s system = 6.000000s CPU (112.6%)
+
+OPT-1001 : Total overflow 388.78 peak overflow 3.00
+OPT-1001 : End high-fanout net optimization;  8.481058s wall, 9.562500s user + 0.250000s system = 9.812500s CPU (115.7%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 732.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16751/20526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 746216, over cnt = 3051(8%), over = 10070, worst = 28
+PHY-1002 : len = 799424, over cnt = 2035(5%), over = 4957, worst = 19
+PHY-1002 : len = 832528, over cnt = 1038(2%), over = 2356, worst = 17
+PHY-1002 : len = 856960, over cnt = 316(0%), over = 759, worst = 13
+PHY-1002 : len = 869744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.860481s wall, 2.593750s user + 0.015625s system = 2.609375s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 56.19, top5 = 49.70, top10 = 46.41, top15 = 44.30.
+OPT-1001 : End congestion update;  2.115335s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (135.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.781218s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (100.0%)
+
+OPT-0007 : Start: WNS -968 TNS -1428 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1428 NUM_FEPS 2 with 60 cells processed and 3300 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1428 NUM_FEPS 2 with 29 cells processed and 1250 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1428 NUM_FEPS 2 with 19 cells processed and 250 slack improved
+OPT-1001 : End global optimization;  2.939153s wall, 3.656250s user + 0.031250s system = 3.687500s CPU (125.5%)
+
+OPT-1001 : Current memory(MB): used = 690, reserve = 687, peak = 732.
+OPT-1001 : End physical optimization;  13.482191s wall, 15.234375s user + 0.328125s system = 15.562500s CPU (115.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7496 LUT to BLE ...
+SYN-4008 : Packed 7496 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6096 remaining SEQ's ...
+SYN-4005 : Packed 3930 SEQ with LUT/SLICE
+SYN-4006 : 747 single LUT's are left
+SYN-4006 : 2166 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9662/13393 primitive instances ...
+PHY-3001 : End packing;  1.528995s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6757 instances
+RUN-1001 : 3305 mslices, 3304 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17524 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9973 nets have 2 pins
+RUN-1001 : 5758 nets have [3 - 5] pins
+RUN-1001 : 1099 nets have [6 - 10] pins
+RUN-1001 : 324 nets have [11 - 20] pins
+RUN-1001 : 339 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6755 instances, 6609 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3537 pins
+PHY-3001 : Found 483 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 662646, Over = 251
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7385/17524.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 819392, over cnt = 2011(5%), over = 3265, worst = 7
+PHY-1002 : len = 827768, over cnt = 1274(3%), over = 1810, worst = 7
+PHY-1002 : len = 840728, over cnt = 538(1%), over = 732, worst = 7
+PHY-1002 : len = 847344, over cnt = 251(0%), over = 347, worst = 7
+PHY-1002 : len = 852456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.470423s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 56.59, top5 = 49.52, top10 = 45.88, top15 = 43.57.
+PHY-3001 : End congestion estimation;  1.852186s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (136.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73583, tnet num: 17346, tinst num: 6755, tnode num: 95970, tedge num: 123551.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.580464s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.8%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 609 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17346 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.436426s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.03146e-05
+PHY-3002 : Step(326): len = 650065, overlap = 247.25
+PHY-3002 : Step(327): len = 643489, overlap = 251.25
+PHY-3002 : Step(328): len = 639900, overlap = 254
+PHY-3002 : Step(329): len = 637466, overlap = 256.75
+PHY-3002 : Step(330): len = 635418, overlap = 256.5
+PHY-3002 : Step(331): len = 634221, overlap = 260.75
+PHY-3002 : Step(332): len = 631922, overlap = 257.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000100629
+PHY-3002 : Step(333): len = 634909, overlap = 256.5
+PHY-3002 : Step(334): len = 638638, overlap = 254.5
+PHY-3002 : Step(335): len = 638912, overlap = 248
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000201258
+PHY-3002 : Step(336): len = 647882, overlap = 229.75
+PHY-3002 : Step(337): len = 655417, overlap = 212.25
+PHY-3002 : Step(338): len = 654441, overlap = 213.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.407200s wall, 0.375000s user + 0.625000s system = 1.000000s CPU (245.6%)
+
+PHY-3001 : Trial Legalized: Len = 734375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 913/17524.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853872, over cnt = 2636(7%), over = 4414, worst = 7
+PHY-1002 : len = 866992, over cnt = 1785(5%), over = 2701, worst = 7
+PHY-1002 : len = 887368, over cnt = 796(2%), over = 1147, worst = 6
+PHY-1002 : len = 903000, over cnt = 167(0%), over = 244, worst = 5
+PHY-1002 : len = 906288, over cnt = 20(0%), over = 28, worst = 5
+PHY-1001 : End global iterations;  2.417823s wall, 3.468750s user + 0.015625s system = 3.484375s CPU (144.1%)
+
+PHY-1001 : Congestion index: top1 = 54.42, top5 = 49.43, top10 = 46.68, top15 = 44.75.
+PHY-3001 : End congestion estimation;  2.892117s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (136.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17346 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.851836s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155538
+PHY-3002 : Step(339): len = 707166, overlap = 41
+PHY-3002 : Step(340): len = 691624, overlap = 63.5
+PHY-3002 : Step(341): len = 678450, overlap = 97.5
+PHY-3002 : Step(342): len = 670113, overlap = 119.75
+PHY-3002 : Step(343): len = 665854, overlap = 130.25
+PHY-3002 : Step(344): len = 663089, overlap = 144.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000311076
+PHY-3002 : Step(345): len = 668659, overlap = 141.5
+PHY-3002 : Step(346): len = 674428, overlap = 144.75
+PHY-3002 : Step(347): len = 675540, overlap = 149
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000622152
+PHY-3002 : Step(348): len = 679835, overlap = 146.5
+PHY-3002 : Step(349): len = 690044, overlap = 141.75
+PHY-3002 : Step(350): len = 693056, overlap = 144.75
+PHY-3002 : Step(351): len = 693919, overlap = 144.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.032217s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (97.0%)
+
+PHY-3001 : Legalized: Len = 722758, Over = 0
+PHY-3001 : Spreading special nets. 415 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.097978s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (95.7%)
+
+PHY-3001 : 603 instances has been re-located, deltaX = 195, deltaY = 348, maxDist = 2.
+PHY-3001 : Final: Len = 731230, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73583, tnet num: 17346, tinst num: 6758, tnode num: 95970, tedge num: 123551.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.838932s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (100.3%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 602 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3592/17524.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862664, over cnt = 2545(7%), over = 4018, worst = 8
+PHY-1002 : len = 876088, over cnt = 1450(4%), over = 2031, worst = 7
+PHY-1002 : len = 891184, over cnt = 551(1%), over = 771, worst = 6
+PHY-1002 : len = 898656, over cnt = 178(0%), over = 237, worst = 3
+PHY-1002 : len = 902616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.078923s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (144.3%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.83, top10 = 45.19, top15 = 43.50.
+PHY-1001 : End incremental global routing;  2.444184s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (138.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17346 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.166716s wall, 1.109375s user + 0.046875s system = 1.156250s CPU (99.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6666 has valid locations, 20 needs to be replaced
+PHY-3001 : design contains 6774 instances, 6625 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3611 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 733332
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16006/17540.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905080, over cnt = 73(0%), over = 84, worst = 3
+PHY-1002 : len = 905272, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 905416, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 905488, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.587339s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (101.1%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.83, top10 = 45.20, top15 = 43.51.
+PHY-3001 : End congestion estimation;  0.899018s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73736, tnet num: 17362, tinst num: 6774, tnode num: 96162, tedge num: 123752.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.813649s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (99.9%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 665 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.680109s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(352): len = 732327, overlap = 0.25
+PHY-3002 : Step(353): len = 732127, overlap = 1
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15989/17540.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 903320, over cnt = 52(0%), over = 61, worst = 3
+PHY-1002 : len = 903392, over cnt = 29(0%), over = 29, worst = 1
+PHY-1002 : len = 903712, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 903864, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.544917s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (106.1%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.76, top10 = 45.16, top15 = 43.50.
+PHY-3001 : End congestion estimation;  0.902369s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (102.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.973210s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000133736
+PHY-3002 : Step(354): len = 732417, overlap = 0.75
+PHY-3002 : Step(355): len = 732417, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005705s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 732504, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.103720s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (105.5%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 2, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 732644, Over = 0
+PHY-3001 : End incremental placement;  5.993353s wall, 6.093750s user + 0.093750s system = 6.187500s CPU (103.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.109022s wall, 11.062500s user + 0.156250s system = 11.218750s CPU (111.0%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 738, peak = 745.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15972/17540.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 904328, over cnt = 41(0%), over = 47, worst = 3
+PHY-1002 : len = 904496, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 904568, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 904584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.603266s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (103.6%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.75, top10 = 45.17, top15 = 43.51.
+OPT-1001 : End congestion update;  0.971973s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (102.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.719451s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1233 TNS -1918 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6774 instances, 6625 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3611 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 735708, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058137s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.5%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 14, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 735798, Over = 0
+PHY-3001 : End incremental legalization;  0.373179s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (96.3%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 27 cells processed and 8300 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6774 instances, 6625 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3611 pins
+PHY-3001 : Found 486 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 737482, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.098478s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (95.2%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 9, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 737574, Over = 0
+PHY-3001 : End incremental legalization;  0.413882s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.9%)
+
+OPT-0007 : Iter 2: improved WNS -933 TNS -1418 NUM_FEPS 2 with 15 cells processed and 2900 slack improved
+OPT-0007 : Iter 3: improved WNS -933 TNS -1418 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.884912s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (104.5%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 738, peak = 745.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.789100s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15842/17540.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909232, over cnt = 109(0%), over = 124, worst = 4
+PHY-1002 : len = 909240, over cnt = 60(0%), over = 65, worst = 2
+PHY-1002 : len = 909696, over cnt = 21(0%), over = 22, worst = 2
+PHY-1002 : len = 909888, over cnt = 13(0%), over = 14, worst = 2
+PHY-1002 : len = 910056, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.760581s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (110.9%)
+
+PHY-1001 : Congestion index: top1 = 52.33, top5 = 47.75, top10 = 45.19, top15 = 43.52.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.769513s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1133 TNS -1718 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 51.931034
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1133ps with logic level 2 
+RUN-1001 :       #2 path slack -1047ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17540 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17540 nets
+OPT-1001 : End physical optimization;  18.037825s wall, 19.203125s user + 0.156250s system = 19.359375s CPU (107.3%)
+
+RUN-1003 : finish command "place" in  60.717251s wall, 94.984375s user + 6.265625s system = 101.250000s CPU (166.8%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 653 MB, peak memory is 745 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.665080s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (174.5%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 653 MB, peak memory is 745 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6776 instances
+RUN-1001 : 3310 mslices, 3315 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17540 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9970 nets have 2 pins
+RUN-1001 : 5759 nets have [3 - 5] pins
+RUN-1001 : 1102 nets have [6 - 10] pins
+RUN-1001 : 330 nets have [11 - 20] pins
+RUN-1001 : 351 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73736, tnet num: 17362, tinst num: 6774, tnode num: 96162, tedge num: 123752.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.578368s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.0%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 668 MB, peak memory is 745 MB
+PHY-1001 : 3310 mslices, 3315 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 848384, over cnt = 2654(7%), over = 4346, worst = 8
+PHY-1002 : len = 866472, over cnt = 1506(4%), over = 2141, worst = 6
+PHY-1002 : len = 884232, over cnt = 552(1%), over = 761, worst = 6
+PHY-1002 : len = 895936, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 896376, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.829556s wall, 4.000000s user + 0.031250s system = 4.031250s CPU (142.5%)
+
+PHY-1001 : Congestion index: top1 = 52.69, top5 = 47.79, top10 = 45.18, top15 = 43.37.
+PHY-1001 : End global routing;  3.151243s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (138.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 716, reserve = 718, peak = 745.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 990, peak = 988.
+PHY-1001 : End build detailed router design. 3.951487s wall, 3.859375s user + 0.078125s system = 3.937500s CPU (99.6%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 265576, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.831832s wall, 4.843750s user + 0.000000s system = 4.843750s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 265488, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.861044s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1023, reserve = 1026, peak = 1023.
+PHY-1001 : End phase 1; 5.705998s wall, 5.718750s user + 0.000000s system = 5.718750s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.35062e+06, over cnt = 1770(0%), over = 1780, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1041, peak = 1038.
+PHY-1001 : End initial routed; 23.761919s wall, 57.484375s user + 0.203125s system = 57.687500s CPU (242.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16463(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.070   |  -4.233   |   3   
+RUN-1001 :   Hold   |   0.080   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.166545s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1053, peak = 1050.
+PHY-1001 : End phase 2; 26.928528s wall, 60.656250s user + 0.203125s system = 60.859375s CPU (226.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.947ns STNS -4.104ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.136574s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1022 : len = 2.35063e+06, over cnt = 1773(0%), over = 1783, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.391817s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.31799e+06, over cnt = 616(0%), over = 618, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.449995s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (197.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.31779e+06, over cnt = 121(0%), over = 121, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.738337s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (137.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.31914e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.306701s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (117.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.31929e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.206499s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.31937e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.253491s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.31937e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.285199s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (104.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.31935e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 7; 0.341807s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16463(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.947   |  -4.104   |   3   
+RUN-1001 :   Hold   |   0.080   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.174070s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 564 feed throughs used by 411 nets
+PHY-1001 : End commit to database; 2.189967s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (100.6%)
+
+PHY-1001 : Current memory(MB): used = 1152, reserve = 1159, peak = 1152.
+PHY-1001 : End phase 3; 9.735852s wall, 11.453125s user + 0.015625s system = 11.468750s CPU (117.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.947ns STNS -4.104ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.136197s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.3%)
+
+PHY-1022 : len = 2.31935e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.368320s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.947ns, -4.104ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16463(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.947   |  -4.104   |   3   
+RUN-1001 :   Hold   |   0.080   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.178600s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 564 feed throughs used by 411 nets
+PHY-1001 : End commit to database; 2.319958s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1168, peak = 1161.
+PHY-1001 : End phase 4; 5.891238s wall, 5.890625s user + 0.000000s system = 5.890625s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.31935e+06
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1170, peak = 1163.
+PHY-1001 : End export database. 0.059983s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.2%)
+
+PHY-1001 : End detail routing;  52.664796s wall, 88.015625s user + 0.296875s system = 88.312500s CPU (167.7%)
+
+RUN-1003 : finish command "route" in  58.431426s wall, 94.953125s user + 0.328125s system = 95.281250s CPU (163.1%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1094 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10238   out of  19600   52.23%
+#reg                     9365   out of  19600   47.78%
+#le                     12335
+  #lut only              2970   out of  12335   24.08%
+  #reg only              2097   out of  12335   17.00%
+  #lut&reg               7268   out of  12335   58.92%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1815
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1402
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1341
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               933
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    136
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         71
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             u_mipi_sot_min/reg1_syn_308.f0                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_183.f1    3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GeneralRouting     io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12335  |9211    |1027    |9397    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |519    |436     |23      |433     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |96     |79      |4       |85      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |26     |26      |0       |18      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |6      |6       |0       |5       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |784    |392     |96      |572     |0       |0       |
+|    u_ADconfig                |AD_config            |189    |119     |25      |140     |0       |0       |
+|    u_gen_sp                  |gen_sp               |278    |171     |71      |115     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |742    |425     |96      |556     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |127     |25      |128     |0       |0       |
+|    u_gen_sp                  |gen_sp               |254    |173     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2987   |2416    |306     |2084    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |166    |123     |17      |130     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2786   |2283    |289     |1919    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2364   |1944    |253     |1580    |22      |0       |
+|        channelPart           |channel_part_8478    |140    |136     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |0       |
+|        ram_switch            |ram_switch           |1841   |1492    |197     |1182    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |236    |209     |27      |124     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |10      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |16      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |32     |29      |3       |18      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |10      |0       |0       |
+|          insert              |insert               |994    |677     |170     |691     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |611    |606     |0       |367     |0       |0       |
+|        read_ram_i            |read_ram             |290    |235     |44      |199     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |223    |183     |40      |154     |0       |0       |
+|          read_ram_data       |read_ram_data        |65     |50      |4       |43      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |329    |246     |36      |273     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3259   |2609    |349     |2103    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |183    |116     |17      |149     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |3045   |2490    |332     |1923    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2595   |2148    |290     |1562    |22      |1       |
+|        channelPart           |channel_part_8478    |232    |217     |3       |137     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |1909   |1596    |197     |1144    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |229    |202     |27      |113     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |18      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|          insert              |insert               |989    |706     |170     |681     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |691    |688     |0       |350     |0       |0       |
+|        read_ram_i            |read_ram_rev         |364    |259     |81      |209     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |296    |211     |73      |163     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |68     |48      |8       |46      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9908  
+    #2         2       3787  
+    #3         3       1373  
+    #4         4       596   
+    #5        5-10     1167  
+    #6       11-50     588   
+    #7       51-100     25   
+    #8        >500      1    
+  Average     2.91           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.057600s wall, 3.500000s user + 0.015625s system = 3.515625s CPU (170.9%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1096 MB, peak memory is 1163 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73736, tnet num: 17362, tinst num: 6774, tnode num: 96162, tedge num: 123752.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.559380s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.2%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1101 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.447704s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.3%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1103 MB, peak memory is 1163 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6774
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17540, pip num: 172918
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 564
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3276 valid insts, and 479661 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.340373s wall, 58.515625s user + 0.187500s system = 58.703125s CPU (628.5%)
+
+RUN-1004 : used memory is 1259 MB, reserved memory is 1262 MB, peak memory is 1374 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_102305.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102726.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102726.log
new file mode 100644
index 0000000..ea80304
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_102726.log
@@ -0,0 +1,1889 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:27:26 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.143665s wall, 2.078125s user + 0.062500s system = 2.140625s CPU (99.9%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.117009s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (100.7%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 513 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.881016s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (100.5%)
+
+PHY-3001 : Found 811 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09942e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.123155s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (114.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28602e+06, overlap = 485.469
+PHY-3002 : Step(2): len = 1.18176e+06, overlap = 556.281
+PHY-3002 : Step(3): len = 845108, overlap = 602.688
+PHY-3002 : Step(4): len = 793971, overlap = 624.094
+PHY-3002 : Step(5): len = 610586, overlap = 759.688
+PHY-3002 : Step(6): len = 530601, overlap = 795.219
+PHY-3002 : Step(7): len = 451300, overlap = 927.281
+PHY-3002 : Step(8): len = 420840, overlap = 995.906
+PHY-3002 : Step(9): len = 371319, overlap = 1076.5
+PHY-3002 : Step(10): len = 344394, overlap = 1105.34
+PHY-3002 : Step(11): len = 299023, overlap = 1167.34
+PHY-3002 : Step(12): len = 279849, overlap = 1200.25
+PHY-3002 : Step(13): len = 251854, overlap = 1240
+PHY-3002 : Step(14): len = 234199, overlap = 1279.66
+PHY-3002 : Step(15): len = 210524, overlap = 1306.72
+PHY-3002 : Step(16): len = 195088, overlap = 1348.47
+PHY-3002 : Step(17): len = 175003, overlap = 1420.22
+PHY-3002 : Step(18): len = 164135, overlap = 1445.38
+PHY-3002 : Step(19): len = 150913, overlap = 1471.66
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.24448e-06
+PHY-3002 : Step(20): len = 149071, overlap = 1437.66
+PHY-3002 : Step(21): len = 179910, overlap = 1299.75
+PHY-3002 : Step(22): len = 190918, overlap = 1237.5
+PHY-3002 : Step(23): len = 199440, overlap = 1198.25
+PHY-3002 : Step(24): len = 196540, overlap = 1173.97
+PHY-3002 : Step(25): len = 194698, overlap = 1164.06
+PHY-3002 : Step(26): len = 191690, overlap = 1152.34
+PHY-3002 : Step(27): len = 190937, overlap = 1147.22
+PHY-3002 : Step(28): len = 189425, overlap = 1137.41
+PHY-3002 : Step(29): len = 188943, overlap = 1114.81
+PHY-3002 : Step(30): len = 188968, overlap = 1115.72
+PHY-3002 : Step(31): len = 188346, overlap = 1124
+PHY-3002 : Step(32): len = 188404, overlap = 1112.09
+PHY-3002 : Step(33): len = 186707, overlap = 1088.16
+PHY-3002 : Step(34): len = 185925, overlap = 1069.69
+PHY-3002 : Step(35): len = 185577, overlap = 1063.03
+PHY-3002 : Step(36): len = 184774, overlap = 1074.06
+PHY-3002 : Step(37): len = 184473, overlap = 1087.62
+PHY-3002 : Step(38): len = 183020, overlap = 1109.69
+PHY-3002 : Step(39): len = 182194, overlap = 1116
+PHY-3002 : Step(40): len = 179450, overlap = 1118.88
+PHY-3002 : Step(41): len = 178621, overlap = 1117.28
+PHY-3002 : Step(42): len = 177021, overlap = 1123.28
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.48896e-06
+PHY-3002 : Step(43): len = 182202, overlap = 1106.44
+PHY-3002 : Step(44): len = 195888, overlap = 1006.41
+PHY-3002 : Step(45): len = 201050, overlap = 971.844
+PHY-3002 : Step(46): len = 207217, overlap = 910.906
+PHY-3002 : Step(47): len = 210682, overlap = 905.469
+PHY-3002 : Step(48): len = 211783, overlap = 913.062
+PHY-3002 : Step(49): len = 212950, overlap = 915.375
+PHY-3002 : Step(50): len = 213008, overlap = 906.594
+PHY-3002 : Step(51): len = 213380, overlap = 916.719
+PHY-3002 : Step(52): len = 211909, overlap = 918.469
+PHY-3002 : Step(53): len = 210641, overlap = 917.844
+PHY-3002 : Step(54): len = 208882, overlap = 925.281
+PHY-3002 : Step(55): len = 206463, overlap = 940.469
+PHY-3002 : Step(56): len = 204546, overlap = 942.781
+PHY-3002 : Step(57): len = 203128, overlap = 936.906
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.97793e-06
+PHY-3002 : Step(58): len = 210709, overlap = 912.625
+PHY-3002 : Step(59): len = 225038, overlap = 895.125
+PHY-3002 : Step(60): len = 233621, overlap = 828.125
+PHY-3002 : Step(61): len = 241735, overlap = 783.625
+PHY-3002 : Step(62): len = 244962, overlap = 766.875
+PHY-3002 : Step(63): len = 247192, overlap = 779.781
+PHY-3002 : Step(64): len = 246086, overlap = 787.75
+PHY-3002 : Step(65): len = 244838, overlap = 781.844
+PHY-3002 : Step(66): len = 243663, overlap = 789
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.95586e-06
+PHY-3002 : Step(67): len = 255950, overlap = 753.875
+PHY-3002 : Step(68): len = 273776, overlap = 687.25
+PHY-3002 : Step(69): len = 281594, overlap = 616.844
+PHY-3002 : Step(70): len = 286142, overlap = 595
+PHY-3002 : Step(71): len = 287247, overlap = 583.25
+PHY-3002 : Step(72): len = 289116, overlap = 556.906
+PHY-3002 : Step(73): len = 288231, overlap = 559.625
+PHY-3002 : Step(74): len = 289593, overlap = 559.844
+PHY-3002 : Step(75): len = 289893, overlap = 547.719
+PHY-3002 : Step(76): len = 290889, overlap = 564.656
+PHY-3002 : Step(77): len = 290438, overlap = 577.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.99117e-05
+PHY-3002 : Step(78): len = 307350, overlap = 533.812
+PHY-3002 : Step(79): len = 322006, overlap = 495.188
+PHY-3002 : Step(80): len = 326793, overlap = 453.062
+PHY-3002 : Step(81): len = 330186, overlap = 440.719
+PHY-3002 : Step(82): len = 330188, overlap = 433.281
+PHY-3002 : Step(83): len = 331863, overlap = 439.656
+PHY-3002 : Step(84): len = 330034, overlap = 425.969
+PHY-3002 : Step(85): len = 331333, overlap = 421.438
+PHY-3002 : Step(86): len = 332648, overlap = 414.594
+PHY-3002 : Step(87): len = 333331, overlap = 403.406
+PHY-3002 : Step(88): len = 333848, overlap = 404.531
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.98234e-05
+PHY-3002 : Step(89): len = 352325, overlap = 380.469
+PHY-3002 : Step(90): len = 364025, overlap = 349.906
+PHY-3002 : Step(91): len = 364769, overlap = 363.125
+PHY-3002 : Step(92): len = 365840, overlap = 347.406
+PHY-3002 : Step(93): len = 367324, overlap = 338.594
+PHY-3002 : Step(94): len = 370918, overlap = 348.062
+PHY-3002 : Step(95): len = 369342, overlap = 329.969
+PHY-3002 : Step(96): len = 370399, overlap = 307.375
+PHY-3002 : Step(97): len = 372123, overlap = 301.656
+PHY-3002 : Step(98): len = 372623, overlap = 298.125
+PHY-3002 : Step(99): len = 371169, overlap = 309.844
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.96469e-05
+PHY-3002 : Step(100): len = 387250, overlap = 298.156
+PHY-3002 : Step(101): len = 399404, overlap = 278.906
+PHY-3002 : Step(102): len = 399934, overlap = 279.5
+PHY-3002 : Step(103): len = 401837, overlap = 275.75
+PHY-3002 : Step(104): len = 404196, overlap = 267.344
+PHY-3002 : Step(105): len = 407106, overlap = 260.75
+PHY-3002 : Step(106): len = 402762, overlap = 265.688
+PHY-3002 : Step(107): len = 403184, overlap = 265.469
+PHY-3002 : Step(108): len = 406014, overlap = 256.031
+PHY-3002 : Step(109): len = 409209, overlap = 245.031
+PHY-3002 : Step(110): len = 405376, overlap = 238.062
+PHY-3002 : Step(111): len = 405386, overlap = 240.688
+PHY-3002 : Step(112): len = 406270, overlap = 247.594
+PHY-3002 : Step(113): len = 407380, overlap = 244.375
+PHY-3002 : Step(114): len = 405222, overlap = 240.625
+PHY-3002 : Step(115): len = 406068, overlap = 231.594
+PHY-3002 : Step(116): len = 407697, overlap = 230.656
+PHY-3002 : Step(117): len = 409528, overlap = 237.094
+PHY-3002 : Step(118): len = 407242, overlap = 233.031
+PHY-3002 : Step(119): len = 407337, overlap = 234.719
+PHY-3002 : Step(120): len = 409528, overlap = 237.219
+PHY-3002 : Step(121): len = 412569, overlap = 234.719
+PHY-3002 : Step(122): len = 410367, overlap = 240.312
+PHY-3002 : Step(123): len = 411372, overlap = 235.531
+PHY-3002 : Step(124): len = 413601, overlap = 231.469
+PHY-3002 : Step(125): len = 416196, overlap = 228.281
+PHY-3002 : Step(126): len = 414003, overlap = 234.625
+PHY-3002 : Step(127): len = 414661, overlap = 229.75
+PHY-3002 : Step(128): len = 416071, overlap = 234.188
+PHY-3002 : Step(129): len = 417262, overlap = 237.875
+PHY-3002 : Step(130): len = 415454, overlap = 232.156
+PHY-3002 : Step(131): len = 416248, overlap = 226.219
+PHY-3002 : Step(132): len = 417212, overlap = 234.406
+PHY-3002 : Step(133): len = 417874, overlap = 233.594
+PHY-3002 : Step(134): len = 416116, overlap = 230.156
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000152415
+PHY-3002 : Step(135): len = 431003, overlap = 232.531
+PHY-3002 : Step(136): len = 441362, overlap = 225.062
+PHY-3002 : Step(137): len = 438253, overlap = 219.625
+PHY-3002 : Step(138): len = 438100, overlap = 214.719
+PHY-3002 : Step(139): len = 440975, overlap = 214.594
+PHY-3002 : Step(140): len = 443675, overlap = 213.625
+PHY-3002 : Step(141): len = 441607, overlap = 214.406
+PHY-3002 : Step(142): len = 442191, overlap = 218.75
+PHY-3002 : Step(143): len = 444940, overlap = 205.531
+PHY-3002 : Step(144): len = 447989, overlap = 211.312
+PHY-3002 : Step(145): len = 445403, overlap = 217.656
+PHY-3002 : Step(146): len = 445287, overlap = 218.75
+PHY-3002 : Step(147): len = 446664, overlap = 222.156
+PHY-3002 : Step(148): len = 447820, overlap = 212.781
+PHY-3002 : Step(149): len = 446535, overlap = 203.125
+PHY-3002 : Step(150): len = 446754, overlap = 200.469
+PHY-3002 : Step(151): len = 448181, overlap = 198.219
+PHY-3002 : Step(152): len = 448813, overlap = 199.562
+PHY-3002 : Step(153): len = 447376, overlap = 201.969
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000295598
+PHY-3002 : Step(154): len = 457307, overlap = 197.844
+PHY-3002 : Step(155): len = 464739, overlap = 191.125
+PHY-3002 : Step(156): len = 464715, overlap = 185.719
+PHY-3002 : Step(157): len = 465542, overlap = 181.281
+PHY-3002 : Step(158): len = 468449, overlap = 179.562
+PHY-3002 : Step(159): len = 471492, overlap = 175.312
+PHY-3002 : Step(160): len = 471044, overlap = 166.281
+PHY-3002 : Step(161): len = 471790, overlap = 164.469
+PHY-3002 : Step(162): len = 474206, overlap = 165.969
+PHY-3002 : Step(163): len = 476170, overlap = 163.906
+PHY-3002 : Step(164): len = 475126, overlap = 162.25
+PHY-3002 : Step(165): len = 475340, overlap = 154.844
+PHY-3002 : Step(166): len = 477044, overlap = 159.656
+PHY-3002 : Step(167): len = 477467, overlap = 156.719
+PHY-3002 : Step(168): len = 476632, overlap = 157.625
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000521868
+PHY-3002 : Step(169): len = 482351, overlap = 155.812
+PHY-3002 : Step(170): len = 487621, overlap = 149.531
+PHY-3002 : Step(171): len = 488498, overlap = 140.812
+PHY-3002 : Step(172): len = 489333, overlap = 138.875
+PHY-3002 : Step(173): len = 491241, overlap = 134.438
+PHY-3002 : Step(174): len = 493008, overlap = 136.562
+PHY-3002 : Step(175): len = 493138, overlap = 135.719
+PHY-3002 : Step(176): len = 494156, overlap = 131.844
+PHY-3002 : Step(177): len = 497403, overlap = 130.438
+PHY-3002 : Step(178): len = 499980, overlap = 130.25
+PHY-3002 : Step(179): len = 499220, overlap = 131.312
+PHY-3002 : Step(180): len = 499192, overlap = 130.812
+PHY-3002 : Step(181): len = 500454, overlap = 127.5
+PHY-3002 : Step(182): len = 501665, overlap = 121.062
+PHY-3002 : Step(183): len = 501772, overlap = 130.719
+PHY-3002 : Step(184): len = 502723, overlap = 132.406
+PHY-3002 : Step(185): len = 503932, overlap = 129.406
+PHY-3002 : Step(186): len = 504514, overlap = 128.656
+PHY-3002 : Step(187): len = 504827, overlap = 128.781
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000946347
+PHY-3002 : Step(188): len = 508431, overlap = 126.156
+PHY-3002 : Step(189): len = 513065, overlap = 123.625
+PHY-3002 : Step(190): len = 514303, overlap = 120.188
+PHY-3002 : Step(191): len = 515234, overlap = 123.125
+PHY-3002 : Step(192): len = 516883, overlap = 124.75
+PHY-3002 : Step(193): len = 518778, overlap = 123.156
+PHY-3002 : Step(194): len = 519362, overlap = 121
+PHY-3002 : Step(195): len = 520365, overlap = 122
+PHY-3002 : Step(196): len = 521664, overlap = 121.406
+PHY-3002 : Step(197): len = 522549, overlap = 121
+PHY-3002 : Step(198): len = 522692, overlap = 124.125
+PHY-3002 : Step(199): len = 523785, overlap = 126.5
+PHY-3002 : Step(200): len = 524876, overlap = 123.969
+PHY-3002 : Step(201): len = 525318, overlap = 124.844
+PHY-3002 : Step(202): len = 525357, overlap = 128.469
+PHY-3002 : Step(203): len = 526154, overlap = 127.094
+PHY-3002 : Step(204): len = 527058, overlap = 127.031
+PHY-3002 : Step(205): len = 527556, overlap = 124.781
+PHY-3002 : Step(206): len = 528240, overlap = 123.062
+PHY-3002 : Step(207): len = 530053, overlap = 127.344
+PHY-3002 : Step(208): len = 531875, overlap = 128.812
+PHY-3002 : Step(209): len = 532415, overlap = 134.844
+PHY-3002 : Step(210): len = 531124, overlap = 120.688
+PHY-3002 : Step(211): len = 530619, overlap = 118.625
+PHY-3002 : Step(212): len = 531010, overlap = 119.75
+PHY-3002 : Step(213): len = 531117, overlap = 121.812
+PHY-3002 : Step(214): len = 530755, overlap = 119.562
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00165362
+PHY-3002 : Step(215): len = 533241, overlap = 123.188
+PHY-3002 : Step(216): len = 538189, overlap = 124.375
+PHY-3002 : Step(217): len = 540055, overlap = 121.656
+PHY-3002 : Step(218): len = 541364, overlap = 120.094
+PHY-3002 : Step(219): len = 542549, overlap = 118.906
+PHY-3002 : Step(220): len = 543239, overlap = 119.094
+PHY-3002 : Step(221): len = 543386, overlap = 123.781
+PHY-3002 : Step(222): len = 543908, overlap = 122.531
+PHY-3002 : Step(223): len = 546017, overlap = 126.25
+PHY-3002 : Step(224): len = 549191, overlap = 122.625
+PHY-3002 : Step(225): len = 550006, overlap = 119.469
+PHY-3002 : Step(226): len = 550450, overlap = 119.031
+PHY-3002 : Step(227): len = 551180, overlap = 120.188
+PHY-3002 : Step(228): len = 551432, overlap = 120.188
+PHY-3002 : Step(229): len = 551099, overlap = 120.812
+PHY-3002 : Step(230): len = 550993, overlap = 121.625
+PHY-3002 : Step(231): len = 551122, overlap = 121.625
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00302322
+PHY-3002 : Step(232): len = 553904, overlap = 122.906
+PHY-3002 : Step(233): len = 559570, overlap = 120.875
+PHY-3002 : Step(234): len = 562084, overlap = 124.281
+PHY-3002 : Step(235): len = 565202, overlap = 124.844
+PHY-3002 : Step(236): len = 567781, overlap = 124.906
+PHY-3002 : Step(237): len = 569926, overlap = 122.094
+PHY-3002 : Step(238): len = 569645, overlap = 122.438
+PHY-3002 : Step(239): len = 569725, overlap = 118.938
+PHY-3002 : Step(240): len = 570764, overlap = 115.625
+PHY-3002 : Step(241): len = 571132, overlap = 116.25
+PHY-3002 : Step(242): len = 570467, overlap = 108
+PHY-3002 : Step(243): len = 570103, overlap = 111.875
+PHY-3002 : Step(244): len = 570179, overlap = 110.812
+PHY-3002 : Step(245): len = 570187, overlap = 110.812
+PHY-3002 : Step(246): len = 570056, overlap = 114.188
+PHY-3002 : Step(247): len = 569826, overlap = 114.938
+PHY-3002 : Step(248): len = 570032, overlap = 110.375
+PHY-3002 : Step(249): len = 571281, overlap = 105.156
+PHY-3002 : Step(250): len = 571768, overlap = 102.438
+PHY-3002 : Step(251): len = 572109, overlap = 110.094
+PHY-3002 : Step(252): len = 572574, overlap = 108.031
+PHY-3002 : Step(253): len = 572834, overlap = 108.781
+PHY-3002 : Step(254): len = 572475, overlap = 107.719
+PHY-3002 : Step(255): len = 572372, overlap = 107.594
+PHY-3002 : Step(256): len = 572526, overlap = 108.594
+PHY-3002 : Step(257): len = 572542, overlap = 109.219
+PHY-3002 : Step(258): len = 572201, overlap = 107.969
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015495s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (100.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720448, over cnt = 1595(4%), over = 7284, worst = 45
+PHY-1001 : End global iterations;  0.728039s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 78.86, top5 = 59.71, top10 = 50.73, top15 = 45.49.
+PHY-3001 : End congestion estimation;  0.943184s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (129.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.857460s wall, 0.812500s user + 0.046875s system = 0.859375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000150341
+PHY-3002 : Step(259): len = 651509, overlap = 64.875
+PHY-3002 : Step(260): len = 650312, overlap = 45.625
+PHY-3002 : Step(261): len = 644878, overlap = 36.875
+PHY-3002 : Step(262): len = 642104, overlap = 31.4688
+PHY-3002 : Step(263): len = 642272, overlap = 32.3125
+PHY-3002 : Step(264): len = 640924, overlap = 31.2812
+PHY-3002 : Step(265): len = 638120, overlap = 30.6562
+PHY-3002 : Step(266): len = 634159, overlap = 29.5625
+PHY-3002 : Step(267): len = 632203, overlap = 24.625
+PHY-3002 : Step(268): len = 630708, overlap = 21.5312
+PHY-3002 : Step(269): len = 627355, overlap = 22.9062
+PHY-3002 : Step(270): len = 623692, overlap = 24.1562
+PHY-3002 : Step(271): len = 620992, overlap = 25.6875
+PHY-3002 : Step(272): len = 619033, overlap = 24.8125
+PHY-3002 : Step(273): len = 617317, overlap = 30.9688
+PHY-3002 : Step(274): len = 615491, overlap = 35.375
+PHY-3002 : Step(275): len = 614021, overlap = 38.3438
+PHY-3002 : Step(276): len = 612020, overlap = 43.9062
+PHY-3002 : Step(277): len = 610190, overlap = 45.7188
+PHY-3002 : Step(278): len = 608354, overlap = 45.9375
+PHY-3002 : Step(279): len = 607040, overlap = 47.25
+PHY-3002 : Step(280): len = 605449, overlap = 50
+PHY-3002 : Step(281): len = 604662, overlap = 50.5312
+PHY-3002 : Step(282): len = 603300, overlap = 49
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000300681
+PHY-3002 : Step(283): len = 604514, overlap = 47.1562
+PHY-3002 : Step(284): len = 606771, overlap = 45.1562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 87/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 695112, over cnt = 2590(7%), over = 11052, worst = 32
+PHY-1001 : End global iterations;  1.588816s wall, 2.046875s user + 0.015625s system = 2.062500s CPU (129.8%)
+
+PHY-1001 : Congestion index: top1 = 80.95, top5 = 63.37, top10 = 55.05, top15 = 50.18.
+PHY-3001 : End congestion estimation;  1.843512s wall, 2.296875s user + 0.031250s system = 2.328125s CPU (126.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.857208s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.6578e-05
+PHY-3002 : Step(285): len = 605503, overlap = 281.594
+PHY-3002 : Step(286): len = 610164, overlap = 235.438
+PHY-3002 : Step(287): len = 607692, overlap = 216.625
+PHY-3002 : Step(288): len = 605686, overlap = 200.031
+PHY-3002 : Step(289): len = 605649, overlap = 170.938
+PHY-3002 : Step(290): len = 604865, overlap = 156.312
+PHY-3002 : Step(291): len = 602137, overlap = 151.969
+PHY-3002 : Step(292): len = 601000, overlap = 143.844
+PHY-3002 : Step(293): len = 598808, overlap = 140.125
+PHY-3002 : Step(294): len = 596098, overlap = 130.469
+PHY-3002 : Step(295): len = 595092, overlap = 127.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000173156
+PHY-3002 : Step(296): len = 595333, overlap = 124.938
+PHY-3002 : Step(297): len = 596303, overlap = 128.156
+PHY-3002 : Step(298): len = 598082, overlap = 122.688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000346312
+PHY-3002 : Step(299): len = 605305, overlap = 106.125
+PHY-3002 : Step(300): len = 612498, overlap = 96.4062
+PHY-3002 : Step(301): len = 616504, overlap = 91.0625
+PHY-3002 : Step(302): len = 616754, overlap = 86.75
+PHY-3002 : Step(303): len = 616660, overlap = 84
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.455351s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.8%)
+
+RUN-1004 : used memory is 572 MB, reserved memory is 561 MB, peak memory is 707 MB
+OPT-1001 : Total overflow 423.81 peak overflow 3.44
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1211/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 717920, over cnt = 2979(8%), over = 10972, worst = 26
+PHY-1001 : End global iterations;  1.185364s wall, 1.703125s user + 0.031250s system = 1.734375s CPU (146.3%)
+
+PHY-1001 : Congestion index: top1 = 69.22, top5 = 56.33, top10 = 50.51, top15 = 46.89.
+PHY-1001 : End incremental global routing;  1.512573s wall, 2.031250s user + 0.031250s system = 2.062500s CPU (136.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.900609s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.6%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 328 needs to be replaced
+PHY-3001 : design contains 17948 instances, 7502 luts, 9225 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6007 pins
+PHY-3001 : Found 819 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 640059
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16451/20528.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 732496, over cnt = 2984(8%), over = 10886, worst = 27
+PHY-1001 : End global iterations;  0.214930s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 69.22, top5 = 56.74, top10 = 51.07, top15 = 47.41.
+PHY-3001 : End congestion estimation;  0.467828s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (116.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85736, tnet num: 20350, tinst num: 17948, tnode num: 116378, tedge num: 137502.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.446136s wall, 1.375000s user + 0.062500s system = 1.437500s CPU (99.4%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 610 MB, peak memory is 710 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20350 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.382035s wall, 2.281250s user + 0.093750s system = 2.375000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(304): len = 639017, overlap = 0
+PHY-3002 : Step(305): len = 638550, overlap = 0.25
+PHY-3002 : Step(306): len = 638326, overlap = 0.84375
+PHY-3002 : Step(307): len = 638064, overlap = 0.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16560/20528.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730288, over cnt = 3001(8%), over = 11016, worst = 26
+PHY-1001 : End global iterations;  0.187645s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (149.9%)
+
+PHY-1001 : Congestion index: top1 = 69.12, top5 = 57.09, top10 = 51.46, top15 = 47.67.
+PHY-3001 : End congestion estimation;  0.449545s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (121.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20350 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.910093s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000365345
+PHY-3002 : Step(308): len = 638002, overlap = 85.5938
+PHY-3002 : Step(309): len = 637951, overlap = 85.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00073069
+PHY-3002 : Step(310): len = 638133, overlap = 85.5312
+PHY-3002 : Step(311): len = 638294, overlap = 86.1875
+PHY-3001 : Final: Len = 638294, Over = 86.1875
+PHY-3001 : End incremental placement;  4.869495s wall, 5.046875s user + 0.203125s system = 5.250000s CPU (107.8%)
+
+OPT-1001 : Total overflow 429.56 peak overflow 3.44
+OPT-1001 : End high-fanout net optimization;  7.907541s wall, 8.671875s user + 0.250000s system = 8.921875s CPU (112.8%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 707, peak = 729.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16514/20528.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 734024, over cnt = 2942(8%), over = 9985, worst = 25
+PHY-1002 : len = 779152, over cnt = 2135(6%), over = 5573, worst = 18
+PHY-1002 : len = 813976, over cnt = 1159(3%), over = 2859, worst = 16
+PHY-1002 : len = 841904, over cnt = 418(1%), over = 1118, worst = 14
+PHY-1002 : len = 859272, over cnt = 2(0%), over = 4, worst = 3
+PHY-1001 : End global iterations;  1.805668s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (128.9%)
+
+PHY-1001 : Congestion index: top1 = 57.33, top5 = 50.00, top10 = 46.40, top15 = 44.16.
+OPT-1001 : End congestion update;  2.062117s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (125.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20350 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.780387s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (100.1%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 68 cells processed and 8050 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 20 cells processed and 1400 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 19 cells processed and 1150 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 25 cells processed and 900 slack improved
+OPT-1001 : End global optimization;  2.885884s wall, 3.406250s user + 0.015625s system = 3.421875s CPU (118.6%)
+
+OPT-1001 : Current memory(MB): used = 709, reserve = 703, peak = 729.
+OPT-1001 : End physical optimization;  13.021517s wall, 14.359375s user + 0.296875s system = 14.656250s CPU (112.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7502 LUT to BLE ...
+SYN-4008 : Packed 7502 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6092 remaining SEQ's ...
+SYN-4005 : Packed 3685 SEQ with LUT/SLICE
+SYN-4006 : 986 single LUT's are left
+SYN-4006 : 2407 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9909/13640 primitive instances ...
+PHY-3001 : End packing;  1.557205s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6877 instances
+RUN-1001 : 3364 mslices, 3365 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17526 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9971 nets have 2 pins
+RUN-1001 : 5757 nets have [3 - 5] pins
+RUN-1001 : 1110 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 326 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6875 instances, 6729 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3560 pins
+PHY-3001 : Found 328 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 651916, Over = 260.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7347/17526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 809152, over cnt = 1993(5%), over = 3397, worst = 8
+PHY-1002 : len = 819248, over cnt = 1243(3%), over = 1821, worst = 8
+PHY-1002 : len = 829784, over cnt = 676(1%), over = 958, worst = 8
+PHY-1002 : len = 836488, over cnt = 360(1%), over = 510, worst = 8
+PHY-1002 : len = 846064, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.595889s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 57.52, top5 = 50.01, top10 = 46.19, top15 = 43.84.
+PHY-3001 : End congestion estimation;  1.980668s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (136.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73676, tnet num: 17348, tinst num: 6875, tnode num: 96121, tedge num: 123696.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.623448s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (100.1%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 609 MB, peak memory is 729 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.474269s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.32851e-05
+PHY-3002 : Step(312): len = 641607, overlap = 264
+PHY-3002 : Step(313): len = 635690, overlap = 273
+PHY-3002 : Step(314): len = 631749, overlap = 272.75
+PHY-3002 : Step(315): len = 629322, overlap = 269.75
+PHY-3002 : Step(316): len = 627633, overlap = 271
+PHY-3002 : Step(317): len = 625492, overlap = 276.75
+PHY-3002 : Step(318): len = 623841, overlap = 271
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.65701e-05
+PHY-3002 : Step(319): len = 626494, overlap = 266.75
+PHY-3002 : Step(320): len = 630460, overlap = 258.25
+PHY-3002 : Step(321): len = 631205, overlap = 254
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00017314
+PHY-3002 : Step(322): len = 638689, overlap = 249
+PHY-3002 : Step(323): len = 649034, overlap = 231.5
+PHY-3002 : Step(324): len = 650750, overlap = 231
+PHY-3002 : Step(325): len = 651241, overlap = 228.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00034484
+PHY-3002 : Step(326): len = 657840, overlap = 219.75
+PHY-3002 : Step(327): len = 667305, overlap = 206.25
+PHY-3002 : Step(328): len = 673893, overlap = 206.75
+PHY-3002 : Step(329): len = 675404, overlap = 198.25
+PHY-3002 : Step(330): len = 675539, overlap = 187.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.398950s wall, 0.390625s user + 0.515625s system = 0.906250s CPU (227.2%)
+
+PHY-3001 : Trial Legalized: Len = 745616
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 629/17526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865328, over cnt = 2655(7%), over = 4586, worst = 8
+PHY-1002 : len = 882392, over cnt = 1701(4%), over = 2584, worst = 8
+PHY-1002 : len = 905016, over cnt = 546(1%), over = 824, worst = 8
+PHY-1002 : len = 915368, over cnt = 123(0%), over = 190, worst = 6
+PHY-1002 : len = 918112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.380308s wall, 3.453125s user + 0.015625s system = 3.468750s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 52.37, top5 = 48.06, top10 = 45.71, top15 = 44.10.
+PHY-3001 : End congestion estimation;  2.823608s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (138.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.900944s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000167688
+PHY-3002 : Step(331): len = 720005, overlap = 37
+PHY-3002 : Step(332): len = 704220, overlap = 59.25
+PHY-3002 : Step(333): len = 689975, overlap = 87
+PHY-3002 : Step(334): len = 680612, overlap = 107.5
+PHY-3002 : Step(335): len = 672605, overlap = 130.75
+PHY-3002 : Step(336): len = 669271, overlap = 142.25
+PHY-3002 : Step(337): len = 666924, overlap = 151.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000335376
+PHY-3002 : Step(338): len = 671804, overlap = 146.5
+PHY-3002 : Step(339): len = 676995, overlap = 140.75
+PHY-3002 : Step(340): len = 679226, overlap = 139.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000670753
+PHY-3002 : Step(341): len = 681733, overlap = 134.25
+PHY-3002 : Step(342): len = 688547, overlap = 129.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.033284s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (93.9%)
+
+PHY-3001 : Legalized: Len = 716306, Over = 0
+PHY-3001 : Spreading special nets. 439 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.109769s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.6%)
+
+PHY-3001 : 642 instances has been re-located, deltaX = 199, deltaY = 391, maxDist = 3.
+PHY-3001 : Final: Len = 726334, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73676, tnet num: 17348, tinst num: 6878, tnode num: 96121, tedge num: 123696.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.927069s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (97.3%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 651 MB, peak memory is 729 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4746/17526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 864200, over cnt = 2512(7%), over = 3987, worst = 7
+PHY-1002 : len = 875576, over cnt = 1601(4%), over = 2276, worst = 6
+PHY-1002 : len = 893088, over cnt = 563(1%), over = 768, worst = 6
+PHY-1002 : len = 900616, over cnt = 215(0%), over = 287, worst = 4
+PHY-1002 : len = 904872, over cnt = 7(0%), over = 7, worst = 1
+PHY-1001 : End global iterations;  1.832311s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (155.2%)
+
+PHY-1001 : Congestion index: top1 = 52.48, top5 = 47.62, top10 = 45.06, top15 = 43.37.
+PHY-1001 : End incremental global routing;  2.190999s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (146.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.906771s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.9%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6898 instances, 6749 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 331 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 729348
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15984/17550.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908112, over cnt = 90(0%), over = 101, worst = 5
+PHY-1002 : len = 908256, over cnt = 47(0%), over = 49, worst = 2
+PHY-1002 : len = 908664, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 908792, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 908832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.767703s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.8%)
+
+PHY-1001 : Congestion index: top1 = 52.48, top5 = 47.64, top10 = 45.11, top15 = 43.44.
+PHY-3001 : End congestion estimation;  1.073266s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (101.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73858, tnet num: 17372, tinst num: 6898, tnode num: 96354, tedge num: 123946.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.866886s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (99.6%)
+
+RUN-1004 : used memory is 681 MB, reserved memory is 685 MB, peak memory is 729 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17372 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.744896s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(343): len = 728743, overlap = 0
+PHY-3002 : Step(344): len = 728400, overlap = 0
+PHY-3002 : Step(345): len = 728220, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15979/17550.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906896, over cnt = 60(0%), over = 76, worst = 6
+PHY-1002 : len = 907168, over cnt = 22(0%), over = 23, worst = 2
+PHY-1002 : len = 907376, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 907464, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 907512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.733510s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.66, top10 = 45.11, top15 = 43.43.
+PHY-3001 : End congestion estimation;  1.040211s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (102.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17372 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.847246s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000203502
+PHY-3002 : Step(346): len = 728136, overlap = 1.75
+PHY-3002 : Step(347): len = 728173, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005534s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (282.3%)
+
+PHY-3001 : Legalized: Len = 728169, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063798s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.0%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 728269, Over = 0
+PHY-3001 : End incremental placement;  6.184064s wall, 6.218750s user + 0.093750s system = 6.312500s CPU (102.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.763037s wall, 10.781250s user + 0.109375s system = 10.890625s CPU (111.5%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 731, peak = 738.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15953/17550.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 907472, over cnt = 58(0%), over = 65, worst = 3
+PHY-1002 : len = 907520, over cnt = 20(0%), over = 20, worst = 1
+PHY-1002 : len = 907632, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 907680, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 907728, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.780868s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (102.0%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.64, top10 = 45.04, top15 = 43.39.
+OPT-1001 : End congestion update;  1.106509s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (101.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17372 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.707613s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.4%)
+
+OPT-0007 : Start: WNS -1036 TNS -1650 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6810 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6898 instances, 6749 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 331 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 732097, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060544s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.2%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 6, deltaY = 20, maxDist = 3.
+PHY-3001 : Final: Len = 732691, Over = 0
+PHY-3001 : End incremental legalization;  0.393100s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (123.2%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1521 NUM_FEPS 2 with 36 cells processed and 9400 slack improved
+OPT-0007 : Iter 2: improved WNS -986 TNS -1521 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.373727s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (104.7%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 732, peak = 738.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17372 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.709273s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15830/17550.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911560, over cnt = 97(0%), over = 111, worst = 3
+PHY-1002 : len = 911736, over cnt = 55(0%), over = 58, worst = 2
+PHY-1002 : len = 911960, over cnt = 33(0%), over = 34, worst = 2
+PHY-1002 : len = 912304, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 912584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.764372s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 52.44, top5 = 47.80, top10 = 45.19, top15 = 43.50.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17372 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.704787s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1086 TNS -1621 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 52.034483
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1086ps with logic level 2 
+RUN-1001 :       #2 path slack -1040ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17550 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17550 nets
+OPT-1001 : End physical optimization;  16.893004s wall, 17.968750s user + 0.125000s system = 18.093750s CPU (107.1%)
+
+RUN-1003 : finish command "place" in  57.333377s wall, 84.015625s user + 6.031250s system = 90.046875s CPU (157.1%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 646 MB, peak memory is 738 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.697502s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (173.0%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 648 MB, peak memory is 738 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6900 instances
+RUN-1001 : 3373 mslices, 3376 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17550 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9977 nets have 2 pins
+RUN-1001 : 5759 nets have [3 - 5] pins
+RUN-1001 : 1105 nets have [6 - 10] pins
+RUN-1001 : 341 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73858, tnet num: 17372, tinst num: 6898, tnode num: 96354, tedge num: 123946.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.561311s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.1%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 620 MB, peak memory is 738 MB
+PHY-1001 : 3373 mslices, 3376 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17372 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842160, over cnt = 2731(7%), over = 4635, worst = 7
+PHY-1002 : len = 859536, over cnt = 1723(4%), over = 2592, worst = 7
+PHY-1002 : len = 877344, over cnt = 765(2%), over = 1140, worst = 7
+PHY-1002 : len = 895720, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 895832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.849139s wall, 3.921875s user + 0.015625s system = 3.937500s CPU (138.2%)
+
+PHY-1001 : Congestion index: top1 = 52.61, top5 = 47.55, top10 = 44.93, top15 = 43.15.
+PHY-1001 : End global routing;  3.165431s wall, 4.250000s user + 0.015625s system = 4.265625s CPU (134.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 707, reserve = 710, peak = 738.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 985, reserve = 988, peak = 985.
+PHY-1001 : End build detailed router design. 3.946887s wall, 3.890625s user + 0.062500s system = 3.953125s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 264160, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.721628s wall, 4.718750s user + 0.000000s system = 4.718750s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 264072, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.756165s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1024, peak = 1021.
+PHY-1001 : End phase 1; 5.490274s wall, 5.484375s user + 0.000000s system = 5.484375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.35478e+06, over cnt = 1903(0%), over = 1914, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1039, peak = 1036.
+PHY-1001 : End initial routed; 21.523606s wall, 55.031250s user + 0.281250s system = 55.312500s CPU (257.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 8/16473(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.096   |  -4.228   |   6   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.233257s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1057, peak = 1052.
+PHY-1001 : End phase 2; 24.756929s wall, 58.250000s user + 0.296875s system = 58.546875s CPU (236.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -2.093ns STNS -4.209ns FEP 6.
+PHY-1001 : End OPT Iter 1; 0.146255s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.2%)
+
+PHY-1022 : len = 2.3548e+06, over cnt = 1905(0%), over = 1916, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.399951s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3243e+06, over cnt = 708(0%), over = 708, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.415416s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (194.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.32179e+06, over cnt = 124(0%), over = 124, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.804838s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (157.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.32296e+06, over cnt = 13(0%), over = 13, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.347356s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (130.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.32327e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 4; 0.262726s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 8/16473(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.093   |  -4.209   |   6   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.195563s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 564 feed throughs used by 437 nets
+PHY-1001 : End commit to database; 2.215539s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1160, peak = 1151.
+PHY-1001 : End phase 3; 9.025294s wall, 10.859375s user + 0.015625s system = 10.875000s CPU (120.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -2.093ns STNS -4.209ns FEP 6.
+PHY-1001 : End OPT Iter 1; 0.165009s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (104.2%)
+
+PHY-1022 : len = 2.32327e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.422669s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.093ns, -4.209ns, 6}
+PHY-1001 : Update timing.....
+PHY-1001 : 8/16473(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.093   |  -4.209   |   6   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.177897s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 564 feed throughs used by 437 nets
+PHY-1001 : End commit to database; 2.288585s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1169, peak = 1160.
+PHY-1001 : End phase 4; 5.916881s wall, 5.921875s user + 0.000000s system = 5.921875s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.32327e+06
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1171, peak = 1162.
+PHY-1001 : End export database. 0.143446s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (98.0%)
+
+PHY-1001 : End detail routing;  49.666646s wall, 84.921875s user + 0.390625s system = 85.312500s CPU (171.8%)
+
+RUN-1003 : finish command "route" in  55.430964s wall, 91.750000s user + 0.421875s system = 92.171875s CPU (166.3%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1100 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10250   out of  19600   52.30%
+#reg                     9369   out of  19600   47.80%
+#le                     12598
+  #lut only              3229   out of  12598   25.63%
+  #reg only              2348   out of  12598   18.64%
+  #lut&reg               7021   out of  12598   55.73%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1807
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1404
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1352
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               954
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    138
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          72
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg0_syn_175.f1             3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_mipi_sot_min/reg1_syn_316.f0                     3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GeneralRouting     io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12598  |9223    |1027    |9401    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |561    |438     |23      |457     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |99     |81      |4       |92      |4       |0       |
+|    U_ecc_gen                 |ecc_gen              |11     |11      |0       |9       |0       |0       |
+|    U_crc16_24b               |crc16_24b            |32     |32      |0       |21      |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |771    |399     |96      |579     |0       |0       |
+|    u_ADconfig                |AD_config            |201    |151     |25      |154     |0       |0       |
+|    u_gen_sp                  |gen_sp               |262    |164     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |735    |407     |96      |539     |0       |0       |
+|    u_ADconfig                |AD_config            |162    |122     |25      |111     |0       |0       |
+|    u_gen_sp                  |gen_sp               |264    |174     |71      |119     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3060   |2483    |306     |2071    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |144     |17      |138     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |2846   |2324    |289     |1899    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |3      |3       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2419   |2006    |253     |1553    |22      |0       |
+|        channelPart           |channel_part_8478    |151    |147     |3       |131     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |40      |0       |0       |
+|        ram_switch            |ram_switch           |1866   |1518    |197     |1139    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |239    |212     |27      |116     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |8       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|          insert              |insert               |953    |633     |170     |664     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |674    |673     |0       |359     |0       |0       |
+|        read_ram_i            |read_ram             |298    |252     |44      |206     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |236    |196     |40      |163     |0       |0       |
+|          read_ram_data       |read_ram_data        |59     |53      |4       |40      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |2      |2       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |347    |240     |36      |285     |3       |0       |
+|        u0_soft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3372   |2638    |349     |2068    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |187    |104     |17      |145     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |3153   |2532    |332     |1891    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2734   |2227    |290     |1561    |22      |1       |
+|        channelPart           |channel_part_8478    |253    |239     |3       |149     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |2022   |1655    |197     |1125    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |210    |183     |27      |99      |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |10     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |962    |624     |170     |653     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |850    |848     |0       |373     |0       |0       |
+|        read_ram_i            |read_ram_rev         |362    |251     |81      |207     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |292    |207     |73      |157     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |70     |44      |8       |50      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9915  
+    #2         2       3811  
+    #3         3       1372  
+    #4         4       573   
+    #5        5-10     1176  
+    #6       11-50     586   
+    #7       51-100     21   
+    #8        >500      1    
+  Average     2.91           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.064174s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (171.1%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1101 MB, peak memory is 1162 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73858, tnet num: 17372, tinst num: 6898, tnode num: 96354, tedge num: 123946.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.589325s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.3%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1104 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17372 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.533048s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (99.9%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1106 MB, peak memory is 1162 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6898
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17550, pip num: 172935
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 564
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3273 valid insts, and 479992 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.379474s wall, 62.281250s user + 0.171875s system = 62.453125s CPU (665.8%)
+
+RUN-1004 : used memory is 1258 MB, reserved memory is 1260 MB, peak memory is 1373 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_102726.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103254.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103254.log
new file mode 100644
index 0000000..0669ae8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103254.log
@@ -0,0 +1,1830 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:32:54 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.119756s wall, 2.015625s user + 0.093750s system = 2.109375s CPU (99.5%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.135435s wall, 1.078125s user + 0.046875s system = 1.125000s CPU (99.1%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 513 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.907339s wall, 1.843750s user + 0.062500s system = 1.906250s CPU (99.9%)
+
+PHY-3001 : Found 2354 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.129705s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28072e+06, overlap = 486.688
+PHY-3002 : Step(2): len = 1.17407e+06, overlap = 553.844
+PHY-3002 : Step(3): len = 841734, overlap = 587.875
+PHY-3002 : Step(4): len = 790107, overlap = 608.875
+PHY-3002 : Step(5): len = 614718, overlap = 736.969
+PHY-3002 : Step(6): len = 535694, overlap = 781.094
+PHY-3002 : Step(7): len = 456338, overlap = 892.312
+PHY-3002 : Step(8): len = 421642, overlap = 966.469
+PHY-3002 : Step(9): len = 370935, overlap = 1045.53
+PHY-3002 : Step(10): len = 343782, overlap = 1092.34
+PHY-3002 : Step(11): len = 301971, overlap = 1115.41
+PHY-3002 : Step(12): len = 283128, overlap = 1145.19
+PHY-3002 : Step(13): len = 248602, overlap = 1189.88
+PHY-3002 : Step(14): len = 229619, overlap = 1239.34
+PHY-3002 : Step(15): len = 205928, overlap = 1265.19
+PHY-3002 : Step(16): len = 189118, overlap = 1310
+PHY-3002 : Step(17): len = 176881, overlap = 1370.53
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.86508e-06
+PHY-3002 : Step(18): len = 179018, overlap = 1352.47
+PHY-3002 : Step(19): len = 218879, overlap = 1218.12
+PHY-3002 : Step(20): len = 225842, overlap = 1159.06
+PHY-3002 : Step(21): len = 230247, overlap = 1134.59
+PHY-3002 : Step(22): len = 227809, overlap = 1073
+PHY-3002 : Step(23): len = 225455, overlap = 1026.25
+PHY-3002 : Step(24): len = 220592, overlap = 1007.22
+PHY-3002 : Step(25): len = 217950, overlap = 1023.81
+PHY-3002 : Step(26): len = 215102, overlap = 1028.28
+PHY-3002 : Step(27): len = 212217, overlap = 1070.94
+PHY-3002 : Step(28): len = 210710, overlap = 1084.69
+PHY-3002 : Step(29): len = 207113, overlap = 1095.06
+PHY-3002 : Step(30): len = 204588, overlap = 1087.84
+PHY-3002 : Step(31): len = 203495, overlap = 1084.22
+PHY-3002 : Step(32): len = 201804, overlap = 1087.19
+PHY-3002 : Step(33): len = 202088, overlap = 1076.47
+PHY-3002 : Step(34): len = 200911, overlap = 1074.5
+PHY-3002 : Step(35): len = 200667, overlap = 1099.78
+PHY-3002 : Step(36): len = 200371, overlap = 1115.38
+PHY-3002 : Step(37): len = 201387, overlap = 1117.78
+PHY-3002 : Step(38): len = 200130, overlap = 1106.88
+PHY-3002 : Step(39): len = 200584, overlap = 1087.28
+PHY-3002 : Step(40): len = 198758, overlap = 1108.34
+PHY-3002 : Step(41): len = 199287, overlap = 1108.16
+PHY-3002 : Step(42): len = 198138, overlap = 1106.09
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 3.73016e-06
+PHY-3002 : Step(43): len = 204587, overlap = 1062.59
+PHY-3002 : Step(44): len = 217927, overlap = 1035.25
+PHY-3002 : Step(45): len = 226628, overlap = 974.125
+PHY-3002 : Step(46): len = 235146, overlap = 912.562
+PHY-3002 : Step(47): len = 239332, overlap = 872.969
+PHY-3002 : Step(48): len = 240805, overlap = 874.906
+PHY-3002 : Step(49): len = 239984, overlap = 866.531
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 7.46031e-06
+PHY-3002 : Step(50): len = 252025, overlap = 843
+PHY-3002 : Step(51): len = 277661, overlap = 716.5
+PHY-3002 : Step(52): len = 290494, overlap = 643.375
+PHY-3002 : Step(53): len = 297569, overlap = 589.719
+PHY-3002 : Step(54): len = 297172, overlap = 582.188
+PHY-3002 : Step(55): len = 295173, overlap = 589.156
+PHY-3002 : Step(56): len = 292148, overlap = 593.844
+PHY-3002 : Step(57): len = 290413, overlap = 597.375
+PHY-3002 : Step(58): len = 287775, overlap = 608.531
+PHY-3002 : Step(59): len = 286491, overlap = 630.312
+PHY-3002 : Step(60): len = 285640, overlap = 625.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.49206e-05
+PHY-3002 : Step(61): len = 303775, overlap = 580.094
+PHY-3002 : Step(62): len = 323788, overlap = 500.375
+PHY-3002 : Step(63): len = 332786, overlap = 458.969
+PHY-3002 : Step(64): len = 336953, overlap = 449.344
+PHY-3002 : Step(65): len = 335564, overlap = 442.969
+PHY-3002 : Step(66): len = 334411, overlap = 432.344
+PHY-3002 : Step(67): len = 331552, overlap = 439.312
+PHY-3002 : Step(68): len = 331372, overlap = 429.719
+PHY-3002 : Step(69): len = 330011, overlap = 427.625
+PHY-3002 : Step(70): len = 329856, overlap = 432.344
+PHY-3002 : Step(71): len = 329310, overlap = 441.656
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.98412e-05
+PHY-3002 : Step(72): len = 350245, overlap = 389.875
+PHY-3002 : Step(73): len = 361535, overlap = 361.844
+PHY-3002 : Step(74): len = 361142, overlap = 348.5
+PHY-3002 : Step(75): len = 362050, overlap = 350.312
+PHY-3002 : Step(76): len = 362870, overlap = 339.844
+PHY-3002 : Step(77): len = 364788, overlap = 338.094
+PHY-3002 : Step(78): len = 364761, overlap = 325.594
+PHY-3002 : Step(79): len = 366031, overlap = 304.5
+PHY-3002 : Step(80): len = 366563, overlap = 301.75
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 5.96825e-05
+PHY-3002 : Step(81): len = 384833, overlap = 277.344
+PHY-3002 : Step(82): len = 396595, overlap = 281.688
+PHY-3002 : Step(83): len = 396543, overlap = 293.094
+PHY-3002 : Step(84): len = 399101, overlap = 273.094
+PHY-3002 : Step(85): len = 402703, overlap = 257.125
+PHY-3002 : Step(86): len = 404917, overlap = 255.406
+PHY-3002 : Step(87): len = 403083, overlap = 259.875
+PHY-3002 : Step(88): len = 405003, overlap = 248.375
+PHY-3002 : Step(89): len = 406650, overlap = 235.469
+PHY-3002 : Step(90): len = 408001, overlap = 239.25
+PHY-3002 : Step(91): len = 406149, overlap = 238.375
+PHY-3002 : Step(92): len = 405938, overlap = 236.594
+PHY-3002 : Step(93): len = 406586, overlap = 233.156
+PHY-3002 : Step(94): len = 406976, overlap = 226.156
+PHY-3002 : Step(95): len = 405513, overlap = 227.062
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 0.000118842
+PHY-3002 : Step(96): len = 421248, overlap = 217.844
+PHY-3002 : Step(97): len = 429319, overlap = 205.031
+PHY-3002 : Step(98): len = 427464, overlap = 198.469
+PHY-3002 : Step(99): len = 429034, overlap = 196.094
+PHY-3002 : Step(100): len = 434105, overlap = 201.531
+PHY-3002 : Step(101): len = 437586, overlap = 195.062
+PHY-3002 : Step(102): len = 435528, overlap = 194.125
+PHY-3002 : Step(103): len = 435548, overlap = 192.094
+PHY-3002 : Step(104): len = 437020, overlap = 199.219
+PHY-3002 : Step(105): len = 438613, overlap = 206.969
+PHY-3002 : Step(106): len = 437625, overlap = 204.781
+PHY-3002 : Step(107): len = 438068, overlap = 181.406
+PHY-3002 : Step(108): len = 439671, overlap = 176.469
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000237684
+PHY-3002 : Step(109): len = 450914, overlap = 162.625
+PHY-3002 : Step(110): len = 460112, overlap = 162.875
+PHY-3002 : Step(111): len = 461891, overlap = 161.688
+PHY-3002 : Step(112): len = 464646, overlap = 159.062
+PHY-3002 : Step(113): len = 468264, overlap = 165.781
+PHY-3002 : Step(114): len = 469931, overlap = 160.656
+PHY-3002 : Step(115): len = 467248, overlap = 156.531
+PHY-3002 : Step(116): len = 466600, overlap = 161
+PHY-3002 : Step(117): len = 467545, overlap = 163.344
+PHY-3002 : Step(118): len = 468464, overlap = 161.344
+PHY-3002 : Step(119): len = 467707, overlap = 162.531
+PHY-3002 : Step(120): len = 467971, overlap = 160.594
+PHY-3002 : Step(121): len = 468918, overlap = 167.406
+PHY-3002 : Step(122): len = 469942, overlap = 168.906
+PHY-3002 : Step(123): len = 469453, overlap = 166.75
+PHY-3002 : Step(124): len = 469682, overlap = 167.469
+PHY-3002 : Step(125): len = 470737, overlap = 159.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000475368
+PHY-3002 : Step(126): len = 478080, overlap = 160.031
+PHY-3002 : Step(127): len = 484656, overlap = 157.031
+PHY-3002 : Step(128): len = 486098, overlap = 157.094
+PHY-3002 : Step(129): len = 487182, overlap = 155.188
+PHY-3002 : Step(130): len = 489476, overlap = 146.344
+PHY-3002 : Step(131): len = 491395, overlap = 146.031
+PHY-3002 : Step(132): len = 491713, overlap = 154.125
+PHY-3002 : Step(133): len = 492939, overlap = 147.625
+PHY-3002 : Step(134): len = 494576, overlap = 132.875
+PHY-3002 : Step(135): len = 496161, overlap = 137.594
+PHY-3002 : Step(136): len = 495988, overlap = 136.469
+PHY-3002 : Step(137): len = 496106, overlap = 140.25
+PHY-3002 : Step(138): len = 496266, overlap = 140.844
+PHY-3002 : Step(139): len = 496470, overlap = 137.406
+PHY-3002 : Step(140): len = 496546, overlap = 141.875
+PHY-3002 : Step(141): len = 496911, overlap = 147.312
+PHY-3002 : Step(142): len = 497266, overlap = 145.219
+PHY-3002 : Step(143): len = 497396, overlap = 142.25
+PHY-3002 : Step(144): len = 497065, overlap = 141.812
+PHY-3002 : Step(145): len = 497033, overlap = 141.844
+PHY-3002 : Step(146): len = 497338, overlap = 144.406
+PHY-3002 : Step(147): len = 497472, overlap = 144.5
+PHY-3002 : Step(148): len = 497385, overlap = 142.469
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000877422
+PHY-3002 : Step(149): len = 501184, overlap = 146.438
+PHY-3002 : Step(150): len = 504663, overlap = 147.25
+PHY-3002 : Step(151): len = 505596, overlap = 151.281
+PHY-3002 : Step(152): len = 506420, overlap = 146.594
+PHY-3002 : Step(153): len = 507917, overlap = 151.438
+PHY-3002 : Step(154): len = 508634, overlap = 149.938
+PHY-3002 : Step(155): len = 508927, overlap = 151.156
+PHY-3002 : Step(156): len = 509441, overlap = 149.938
+PHY-3002 : Step(157): len = 510216, overlap = 145.906
+PHY-3002 : Step(158): len = 510513, overlap = 147.094
+PHY-3002 : Step(159): len = 510634, overlap = 150.719
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.010935s wall, 0.015625s user + 0.062500s system = 0.078125s CPU (714.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 664512, over cnt = 1539(4%), over = 7736, worst = 41
+PHY-1001 : End global iterations;  0.616106s wall, 0.859375s user + 0.062500s system = 0.921875s CPU (149.6%)
+
+PHY-1001 : Congestion index: top1 = 84.74, top5 = 63.22, top10 = 53.23, top15 = 47.19.
+PHY-3001 : End congestion estimation;  0.829370s wall, 1.062500s user + 0.062500s system = 1.125000s CPU (135.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.833071s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124634
+PHY-3002 : Step(160): len = 608040, overlap = 88.75
+PHY-3002 : Step(161): len = 613823, overlap = 76.3125
+PHY-3002 : Step(162): len = 609425, overlap = 72.4375
+PHY-3002 : Step(163): len = 606689, overlap = 62.875
+PHY-3002 : Step(164): len = 604912, overlap = 56.0625
+PHY-3002 : Step(165): len = 607328, overlap = 51.7812
+PHY-3002 : Step(166): len = 607168, overlap = 46.9688
+PHY-3002 : Step(167): len = 607492, overlap = 43.0312
+PHY-3002 : Step(168): len = 604916, overlap = 43.9375
+PHY-3002 : Step(169): len = 603312, overlap = 39.7812
+PHY-3002 : Step(170): len = 600505, overlap = 33.4688
+PHY-3002 : Step(171): len = 599443, overlap = 33.6562
+PHY-3002 : Step(172): len = 598160, overlap = 34.5312
+PHY-3002 : Step(173): len = 596331, overlap = 35.5625
+PHY-3002 : Step(174): len = 595700, overlap = 35.7188
+PHY-3002 : Step(175): len = 594872, overlap = 33.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000249268
+PHY-3002 : Step(176): len = 595960, overlap = 32.4688
+PHY-3002 : Step(177): len = 598337, overlap = 33.25
+PHY-3002 : Step(178): len = 602408, overlap = 31.3125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00049776
+PHY-3002 : Step(179): len = 611634, overlap = 31.8438
+PHY-3002 : Step(180): len = 625542, overlap = 30.125
+PHY-3002 : Step(181): len = 635983, overlap = 27.375
+PHY-3002 : Step(182): len = 637110, overlap = 28.2188
+PHY-3002 : Step(183): len = 638403, overlap = 30.9062
+PHY-3002 : Step(184): len = 638761, overlap = 30.4688
+PHY-3002 : Step(185): len = 640101, overlap = 31.7188
+PHY-3002 : Step(186): len = 642175, overlap = 29.5
+PHY-3002 : Step(187): len = 641185, overlap = 31
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00099552
+PHY-3002 : Step(188): len = 644934, overlap = 30.1875
+PHY-3002 : Step(189): len = 650268, overlap = 27.3438
+PHY-3002 : Step(190): len = 653497, overlap = 29.5312
+PHY-3002 : Step(191): len = 657219, overlap = 29.8438
+PHY-3002 : Step(192): len = 663338, overlap = 25.9062
+PHY-3002 : Step(193): len = 669266, overlap = 23.5312
+PHY-3002 : Step(194): len = 670438, overlap = 23.7188
+PHY-3002 : Step(195): len = 669668, overlap = 23.7188
+PHY-3002 : Step(196): len = 669357, overlap = 23
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00185661
+PHY-3002 : Step(197): len = 671998, overlap = 22.5938
+PHY-3002 : Step(198): len = 677210, overlap = 21.9688
+PHY-3002 : Step(199): len = 679487, overlap = 21.7812
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 70/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765144, over cnt = 2759(7%), over = 13017, worst = 44
+PHY-1001 : End global iterations;  1.491401s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (134.1%)
+
+PHY-1001 : Congestion index: top1 = 86.68, top5 = 69.72, top10 = 61.49, top15 = 55.96.
+PHY-3001 : End congestion estimation;  1.817199s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (128.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.221137s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000140884
+PHY-3002 : Step(200): len = 668572, overlap = 217.5
+PHY-3002 : Step(201): len = 662032, overlap = 188.812
+PHY-3002 : Step(202): len = 651857, overlap = 181.156
+PHY-3002 : Step(203): len = 642621, overlap = 169.281
+PHY-3002 : Step(204): len = 635287, overlap = 160.312
+PHY-3002 : Step(205): len = 630004, overlap = 154.812
+PHY-3002 : Step(206): len = 624349, overlap = 150.75
+PHY-3002 : Step(207): len = 620699, overlap = 136.531
+PHY-3002 : Step(208): len = 615344, overlap = 136.312
+PHY-3002 : Step(209): len = 611617, overlap = 141.969
+PHY-3002 : Step(210): len = 607753, overlap = 141.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000281768
+PHY-3002 : Step(211): len = 608484, overlap = 133.125
+PHY-3002 : Step(212): len = 610978, overlap = 124.219
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000500218
+PHY-3002 : Step(213): len = 613053, overlap = 115.969
+PHY-3002 : Step(214): len = 618732, overlap = 108.875
+PHY-3002 : Step(215): len = 623533, overlap = 99.0312
+PHY-3002 : Step(216): len = 625038, overlap = 91.2812
+PHY-3002 : Step(217): len = 626570, overlap = 83.875
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.408518s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (99.8%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 562 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 411.97 peak overflow 4.06
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 761/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 726056, over cnt = 3016(8%), over = 11146, worst = 30
+PHY-1001 : End global iterations;  1.244467s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (145.6%)
+
+PHY-1001 : Congestion index: top1 = 72.31, top5 = 57.81, top10 = 51.49, top15 = 47.68.
+PHY-1001 : End incremental global routing;  1.566428s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (135.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.890866s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (98.2%)
+
+OPT-1001 : 53 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17533 has valid locations, 351 needs to be replaced
+PHY-3001 : design contains 17969 instances, 7515 luts, 9233 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6026 pins
+PHY-3001 : Found 2379 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 649869
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16613/20549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741024, over cnt = 3045(8%), over = 11241, worst = 30
+PHY-1001 : End global iterations;  0.241635s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (122.9%)
+
+PHY-1001 : Congestion index: top1 = 72.44, top5 = 58.10, top10 = 51.95, top15 = 48.20.
+PHY-3001 : End congestion estimation;  0.487399s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (109.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85826, tnet num: 20371, tinst num: 17969, tnode num: 116508, tedge num: 137640.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.411851s wall, 1.375000s user + 0.031250s system = 1.406250s CPU (99.6%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 613 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.691035s wall, 2.640625s user + 0.046875s system = 2.687500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(218): len = 648883, overlap = 0.5
+PHY-3002 : Step(219): len = 648475, overlap = 0.125
+PHY-3002 : Step(220): len = 648205, overlap = 0.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16738/20549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738384, over cnt = 3040(8%), over = 11287, worst = 30
+PHY-1001 : End global iterations;  0.193419s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (161.6%)
+
+PHY-1001 : Congestion index: top1 = 73.15, top5 = 58.56, top10 = 52.21, top15 = 48.41.
+PHY-3001 : End congestion estimation;  0.441497s wall, 0.515625s user + 0.031250s system = 0.546875s CPU (123.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.906090s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000554625
+PHY-3002 : Step(221): len = 647930, overlap = 86.0938
+PHY-3002 : Step(222): len = 648101, overlap = 86.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00109363
+PHY-3002 : Step(223): len = 648496, overlap = 86.8125
+PHY-3002 : Step(224): len = 649103, overlap = 86.9375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00217303
+PHY-3002 : Step(225): len = 649200, overlap = 87.2188
+PHY-3002 : Step(226): len = 649698, overlap = 86.125
+PHY-3001 : Final: Len = 649698, Over = 86.125
+PHY-3001 : End incremental placement;  5.216497s wall, 5.656250s user + 0.265625s system = 5.921875s CPU (113.5%)
+
+OPT-1001 : Total overflow 418.38 peak overflow 4.06
+OPT-1001 : End high-fanout net optimization;  8.325524s wall, 9.406250s user + 0.296875s system = 9.703125s CPU (116.5%)
+
+OPT-1001 : Current memory(MB): used = 714, reserve = 710, peak = 731.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16639/20549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 742368, over cnt = 2989(8%), over = 10225, worst = 30
+PHY-1002 : len = 789760, over cnt = 2161(6%), over = 5586, worst = 19
+PHY-1002 : len = 841304, over cnt = 800(2%), over = 1685, worst = 19
+PHY-1002 : len = 854616, over cnt = 448(1%), over = 803, worst = 10
+PHY-1002 : len = 867712, over cnt = 26(0%), over = 54, worst = 9
+PHY-1001 : End global iterations;  1.703631s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (142.2%)
+
+PHY-1001 : Congestion index: top1 = 59.20, top5 = 50.88, top10 = 46.96, top15 = 44.51.
+OPT-1001 : End congestion update;  1.952289s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (136.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.780835s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (100.1%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 54 cells processed and 7799 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 17 cells processed and 1950 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 27 cells processed and 650 slack improved
+OPT-1001 : End global optimization;  2.776265s wall, 3.468750s user + 0.015625s system = 3.484375s CPU (125.5%)
+
+OPT-1001 : Current memory(MB): used = 692, reserve = 689, peak = 731.
+OPT-1001 : End physical optimization;  13.132709s wall, 15.000000s user + 0.328125s system = 15.328125s CPU (116.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7515 LUT to BLE ...
+SYN-4008 : Packed 7515 LUT and 3132 SEQ to BLE.
+SYN-4003 : Packing 6101 remaining SEQ's ...
+SYN-4005 : Packed 3884 SEQ with LUT/SLICE
+SYN-4006 : 792 single LUT's are left
+SYN-4006 : 2217 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9732/13463 primitive instances ...
+PHY-3001 : End packing;  1.614203s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6779 instances
+RUN-1001 : 3316 mslices, 3315 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17547 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9991 nets have 2 pins
+RUN-1001 : 5738 nets have [3 - 5] pins
+RUN-1001 : 1126 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 330 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6777 instances, 6631 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3535 pins
+PHY-3001 : Found 1035 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 659609, Over = 259.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7288/17547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 811424, over cnt = 1899(5%), over = 3080, worst = 8
+PHY-1002 : len = 819616, over cnt = 1208(3%), over = 1687, worst = 5
+PHY-1002 : len = 831608, over cnt = 444(1%), over = 591, worst = 5
+PHY-1002 : len = 837848, over cnt = 155(0%), over = 203, worst = 5
+PHY-1002 : len = 841800, over cnt = 5(0%), over = 7, worst = 3
+PHY-1001 : End global iterations;  1.601690s wall, 2.187500s user + 0.062500s system = 2.250000s CPU (140.5%)
+
+PHY-1001 : Congestion index: top1 = 59.01, top5 = 50.72, top10 = 46.55, top15 = 43.89.
+PHY-3001 : End congestion estimation;  1.984410s wall, 2.562500s user + 0.062500s system = 2.625000s CPU (132.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73545, tnet num: 17369, tinst num: 6777, tnode num: 95935, tedge num: 123463.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.602790s wall, 1.546875s user + 0.046875s system = 1.593750s CPU (99.4%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 611 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.437992s wall, 2.359375s user + 0.078125s system = 2.437500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.79814e-05
+PHY-3002 : Step(227): len = 649249, overlap = 244.75
+PHY-3002 : Step(228): len = 643410, overlap = 240.75
+PHY-3002 : Step(229): len = 639818, overlap = 246.25
+PHY-3002 : Step(230): len = 637676, overlap = 268.75
+PHY-3002 : Step(231): len = 635073, overlap = 271.75
+PHY-3002 : Step(232): len = 632785, overlap = 273.5
+PHY-3002 : Step(233): len = 630657, overlap = 278.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.59628e-05
+PHY-3002 : Step(234): len = 633035, overlap = 279
+PHY-3002 : Step(235): len = 637910, overlap = 268.25
+PHY-3002 : Step(236): len = 638622, overlap = 267.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000191926
+PHY-3002 : Step(237): len = 646800, overlap = 248.75
+PHY-3002 : Step(238): len = 654843, overlap = 229
+PHY-3002 : Step(239): len = 653854, overlap = 227
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.339215s wall, 0.250000s user + 0.625000s system = 0.875000s CPU (257.9%)
+
+PHY-3001 : Trial Legalized: Len = 747081
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 775/17547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 866664, over cnt = 2630(7%), over = 4408, worst = 8
+PHY-1002 : len = 884288, over cnt = 1572(4%), over = 2299, worst = 7
+PHY-1002 : len = 909040, over cnt = 309(0%), over = 389, worst = 4
+PHY-1002 : len = 914176, over cnt = 27(0%), over = 31, worst = 2
+PHY-1002 : len = 915040, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.238052s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (148.7%)
+
+PHY-1001 : Congestion index: top1 = 54.74, top5 = 49.99, top10 = 47.25, top15 = 45.25.
+PHY-3001 : End congestion estimation;  2.677373s wall, 3.750000s user + 0.015625s system = 3.765625s CPU (140.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.850148s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164028
+PHY-3002 : Step(240): len = 719392, overlap = 38.5
+PHY-3002 : Step(241): len = 703168, overlap = 65.5
+PHY-3002 : Step(242): len = 689283, overlap = 93.5
+PHY-3002 : Step(243): len = 679035, overlap = 123.5
+PHY-3002 : Step(244): len = 672872, overlap = 144.5
+PHY-3002 : Step(245): len = 669474, overlap = 159.25
+PHY-3002 : Step(246): len = 667104, overlap = 163.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328055
+PHY-3002 : Step(247): len = 671898, overlap = 159.25
+PHY-3002 : Step(248): len = 677509, overlap = 154.75
+PHY-3002 : Step(249): len = 677825, overlap = 155
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000596998
+PHY-3002 : Step(250): len = 682213, overlap = 149.5
+PHY-3002 : Step(251): len = 689791, overlap = 149.75
+PHY-3002 : Step(252): len = 694503, overlap = 147.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.048143s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (97.4%)
+
+PHY-3001 : Legalized: Len = 723763, Over = 0
+PHY-3001 : Spreading special nets. 415 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.102051s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (91.9%)
+
+PHY-3001 : 605 instances has been re-located, deltaX = 186, deltaY = 380, maxDist = 3.
+PHY-3001 : Final: Len = 733675, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73545, tnet num: 17369, tinst num: 6780, tnode num: 95935, tedge num: 123463.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.827676s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.0%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 649 MB, peak memory is 731 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3465/17547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863240, over cnt = 2506(7%), over = 4093, worst = 8
+PHY-1002 : len = 879248, over cnt = 1421(4%), over = 2014, worst = 7
+PHY-1002 : len = 893064, over cnt = 625(1%), over = 874, worst = 7
+PHY-1002 : len = 899648, over cnt = 329(0%), over = 478, worst = 5
+PHY-1002 : len = 906152, over cnt = 62(0%), over = 101, worst = 5
+PHY-1001 : End global iterations;  2.013267s wall, 3.125000s user + 0.015625s system = 3.140625s CPU (156.0%)
+
+PHY-1001 : Congestion index: top1 = 55.80, top5 = 49.50, top10 = 46.22, top15 = 44.17.
+PHY-1001 : End incremental global routing;  2.380635s wall, 3.500000s user + 0.015625s system = 3.515625s CPU (147.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.181177s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (99.2%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6800 instances, 6651 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3614 pins
+PHY-3001 : Found 1039 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 737166
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15939/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910352, over cnt = 152(0%), over = 201, worst = 5
+PHY-1002 : len = 910856, over cnt = 85(0%), over = 102, worst = 5
+PHY-1002 : len = 911808, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 911904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 912064, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.784229s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (111.6%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.28, top10 = 46.20, top15 = 44.24.
+PHY-3001 : End congestion estimation;  1.086309s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (107.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73740, tnet num: 17394, tinst num: 6800, tnode num: 96180, tedge num: 123746.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.841183s wall, 1.796875s user + 0.046875s system = 1.843750s CPU (100.1%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 664 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.744779s wall, 2.687500s user + 0.062500s system = 2.750000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(253): len = 735912, overlap = 0.25
+PHY-3002 : Step(254): len = 735422, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15924/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908840, over cnt = 92(0%), over = 110, worst = 5
+PHY-1002 : len = 908696, over cnt = 59(0%), over = 64, worst = 3
+PHY-1002 : len = 909112, over cnt = 22(0%), over = 22, worst = 1
+PHY-1002 : len = 909352, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 909408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.741383s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 55.06, top5 = 49.36, top10 = 46.23, top15 = 44.26.
+PHY-3001 : End congestion estimation;  1.039481s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (103.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.842863s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000223984
+PHY-3002 : Step(255): len = 735757, overlap = 1.75
+PHY-3002 : Step(256): len = 735645, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005876s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 735524, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058817s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 2, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 735594, Over = 0
+PHY-3001 : End incremental placement;  6.172047s wall, 6.343750s user + 0.125000s system = 6.468750s CPU (104.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.213922s wall, 11.468750s user + 0.171875s system = 11.640625s CPU (114.0%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 738, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15897/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909360, over cnt = 74(0%), over = 85, worst = 3
+PHY-1002 : len = 909296, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 909376, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 909512, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 909624, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.779124s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 55.00, top5 = 49.21, top10 = 46.15, top15 = 44.19.
+OPT-1001 : End congestion update;  1.078306s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (102.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.702068s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.2%)
+
+OPT-0007 : Start: WNS -1083 TNS -1718 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6712 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6800 instances, 6651 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3614 pins
+PHY-3001 : Found 1039 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738130, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058779s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.3%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 15, deltaY = 14, maxDist = 2.
+PHY-3001 : Final: Len = 738384, Over = 0
+PHY-3001 : End incremental legalization;  0.370776s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.1%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 34 cells processed and 8950 slack improved
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.295201s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (101.4%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 738, peak = 742.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.705497s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15813/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912096, over cnt = 71(0%), over = 88, worst = 4
+PHY-1002 : len = 911880, over cnt = 47(0%), over = 51, worst = 4
+PHY-1002 : len = 912072, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 912424, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 912584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.757714s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (111.4%)
+
+PHY-1001 : Congestion index: top1 = 55.02, top5 = 49.32, top10 = 46.23, top15 = 44.21.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.711746s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.0%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1033 TNS -1618 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 54.517241
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1033ps with logic level 2 
+RUN-1001 :       #2 path slack -947ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17572 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17572 nets
+OPT-1001 : End physical optimization;  17.178715s wall, 18.546875s user + 0.171875s system = 18.718750s CPU (109.0%)
+
+RUN-1003 : finish command "place" in  57.720122s wall, 84.375000s user + 5.437500s system = 89.812500s CPU (155.6%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 606 MB, peak memory is 742 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.683641s wall, 2.875000s user + 0.015625s system = 2.890625s CPU (171.7%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 607 MB, peak memory is 742 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6802 instances
+RUN-1001 : 3324 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17572 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9995 nets have 2 pins
+RUN-1001 : 5739 nets have [3 - 5] pins
+RUN-1001 : 1131 nets have [6 - 10] pins
+RUN-1001 : 330 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73740, tnet num: 17394, tinst num: 6800, tnode num: 96180, tedge num: 123746.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.596651s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (99.8%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 632 MB, peak memory is 742 MB
+PHY-1001 : 3324 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847656, over cnt = 2689(7%), over = 4421, worst = 7
+PHY-1002 : len = 865904, over cnt = 1591(4%), over = 2267, worst = 6
+PHY-1002 : len = 880512, over cnt = 816(2%), over = 1143, worst = 6
+PHY-1002 : len = 898496, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 898696, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.039853s wall, 4.078125s user + 0.000000s system = 4.078125s CPU (134.2%)
+
+PHY-1001 : Congestion index: top1 = 55.73, top5 = 49.67, top10 = 46.33, top15 = 44.13.
+PHY-1001 : End global routing;  3.358481s wall, 4.390625s user + 0.000000s system = 4.390625s CPU (130.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 712, reserve = 716, peak = 742.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 986, reserve = 992, peak = 986.
+PHY-1001 : End build detailed router design. 3.936613s wall, 3.921875s user + 0.015625s system = 3.937500s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 272480, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.107094s wall, 5.093750s user + 0.000000s system = 5.093750s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 272536, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.402178s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.0%)
+
+PHY-1001 : Current memory(MB): used = 1022, reserve = 1028, peak = 1022.
+PHY-1001 : End phase 1; 5.521421s wall, 5.515625s user + 0.000000s system = 5.515625s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.29591e+06, over cnt = 1965(0%), over = 1977, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1041, peak = 1038.
+PHY-1001 : End initial routed; 22.960109s wall, 51.765625s user + 0.312500s system = 52.078125s CPU (226.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16494(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.923   |  -3.675   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.226051s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1050, peak = 1046.
+PHY-1001 : End phase 2; 26.186234s wall, 55.000000s user + 0.312500s system = 55.312500s CPU (211.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.800ns STNS -3.552ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.135481s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.8%)
+
+PHY-1022 : len = 2.29593e+06, over cnt = 1966(0%), over = 1978, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.395339s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2631e+06, over cnt = 734(0%), over = 735, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.501912s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (168.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.26043e+06, over cnt = 142(0%), over = 142, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.878068s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (129.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.26106e+06, over cnt = 32(0%), over = 32, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.510973s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (113.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2618e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.317840s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (98.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.220443s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.250838s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.384373s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.6%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.169679s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.26202e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.161621s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16494(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.800   |  -3.552   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.207071s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 596 feed throughs used by 432 nets
+PHY-1001 : End commit to database; 2.201411s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1149, reserve = 1157, peak = 1149.
+PHY-1001 : End phase 3; 10.582890s wall, 11.906250s user + 0.031250s system = 11.937500s CPU (112.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.800ns STNS -3.552ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.135691s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%)
+
+PHY-1022 : len = 2.26202e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.369186s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.800ns, -3.552ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16494(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.800   |  -3.552   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.170532s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 596 feed throughs used by 432 nets
+PHY-1001 : End commit to database; 2.279605s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1166, peak = 1158.
+PHY-1001 : End phase 4; 5.845892s wall, 5.859375s user + 0.000000s system = 5.859375s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.26202e+06
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1169, peak = 1161.
+PHY-1001 : End export database. 0.059894s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.4%)
+
+PHY-1001 : End detail routing;  52.521299s wall, 82.625000s user + 0.359375s system = 82.984375s CPU (158.0%)
+
+RUN-1003 : finish command "route" in  58.523001s wall, 89.625000s user + 0.390625s system = 90.015625s CPU (153.8%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1094 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10236   out of  19600   52.22%
+#reg                     9380   out of  19600   47.86%
+#le                     12373
+  #lut only              2993   out of  12373   24.19%
+  #reg only              2137   out of  12373   17.27%
+  #lut&reg               7243   out of  12373   58.54%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1814
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1377
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1321
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               967
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    132
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/reg2_syn_161.f1                        3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg3_syn_155.f1                          3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12373  |9209    |1027    |9412    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |537    |434     |23      |434     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |101    |91      |4       |86      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |35     |35      |0       |23      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |777    |435     |96      |584     |0       |0       |
+|    u_ADconfig                |AD_config            |195    |151     |25      |148     |0       |0       |
+|    u_gen_sp                  |gen_sp               |266    |162     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |723    |404     |96      |545     |0       |0       |
+|    u_ADconfig                |AD_config            |165    |113     |25      |123     |0       |0       |
+|    u_gen_sp                  |gen_sp               |257    |150     |71      |121     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3078   |2408    |306     |2107    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |182    |115     |17      |143     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2863   |2276    |289     |1931    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |6      |3       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |3       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2424   |1955    |253     |1580    |22      |0       |
+|        channelPart           |channel_part_8478    |134    |127     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |57     |48      |9       |39      |0       |0       |
+|        ram_switch            |ram_switch           |1918   |1531    |197     |1187    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |243    |216     |27      |118     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |17      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|          insert              |insert               |1011   |652     |170     |720     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |664    |663     |0       |349     |0       |0       |
+|        read_ram_i            |read_ram             |274    |215     |44      |187     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |213    |173     |40      |143     |0       |0       |
+|          read_ram_data       |read_ram_data        |58     |41      |4       |41      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |345    |246     |36      |279     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3183   |2496    |349     |2089    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |100     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2969   |2387    |332     |1909    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |5       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2517   |2038    |290     |1551    |22      |1       |
+|        channelPart           |channel_part_8478    |235    |232     |3       |141     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |46      |0       |1       |
+|        ram_switch            |ram_switch           |1832   |1484    |197     |1125    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |222    |195     |27      |109     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |6       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |8       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|          insert              |insert               |994    |679     |170     |678     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |616    |610     |0       |338     |0       |0       |
+|        read_ram_i            |read_ram_rev         |356    |241     |81      |208     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |291    |209     |73      |161     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |32      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets  
+    #1          1       9933  
+    #2          2       3795  
+    #3          3       1376  
+    #4          4       565   
+    #5        5-10      1185  
+    #6        11-50     604   
+    #7       51-100      17   
+    #8       101-500     1    
+    #9        >500       1    
+  Average     2.90            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.055370s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (172.6%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1095 MB, peak memory is 1161 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73740, tnet num: 17394, tinst num: 6800, tnode num: 96180, tedge num: 123746.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.579274s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.9%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1099 MB, peak memory is 1161 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.430525s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (99.4%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1101 MB, peak memory is 1161 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6800
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17572, pip num: 171589
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 596
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3258 valid insts, and 477073 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.160042s wall, 69.421875s user + 0.078125s system = 69.500000s CPU (684.1%)
+
+RUN-1004 : used memory is 1260 MB, reserved memory is 1263 MB, peak memory is 1376 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_103254.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103905.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103905.log
new file mode 100644
index 0000000..4461bd0
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_103905.log
@@ -0,0 +1,1830 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:39:05 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.129134s wall, 2.062500s user + 0.078125s system = 2.140625s CPU (100.5%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.121690s wall, 1.078125s user + 0.046875s system = 1.125000s CPU (100.3%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 513 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.887264s wall, 1.796875s user + 0.093750s system = 1.890625s CPU (100.2%)
+
+PHY-3001 : Found 2354 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.124365s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (113.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28072e+06, overlap = 486.688
+PHY-3002 : Step(2): len = 1.17407e+06, overlap = 553.844
+PHY-3002 : Step(3): len = 841734, overlap = 587.875
+PHY-3002 : Step(4): len = 790107, overlap = 608.875
+PHY-3002 : Step(5): len = 614718, overlap = 736.969
+PHY-3002 : Step(6): len = 535694, overlap = 781.094
+PHY-3002 : Step(7): len = 456338, overlap = 892.312
+PHY-3002 : Step(8): len = 421642, overlap = 966.469
+PHY-3002 : Step(9): len = 370935, overlap = 1045.53
+PHY-3002 : Step(10): len = 343782, overlap = 1092.34
+PHY-3002 : Step(11): len = 301971, overlap = 1115.41
+PHY-3002 : Step(12): len = 283128, overlap = 1145.19
+PHY-3002 : Step(13): len = 248602, overlap = 1189.88
+PHY-3002 : Step(14): len = 229619, overlap = 1239.34
+PHY-3002 : Step(15): len = 205928, overlap = 1265.19
+PHY-3002 : Step(16): len = 189118, overlap = 1310
+PHY-3002 : Step(17): len = 176881, overlap = 1370.53
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.86508e-06
+PHY-3002 : Step(18): len = 179018, overlap = 1352.47
+PHY-3002 : Step(19): len = 218879, overlap = 1218.12
+PHY-3002 : Step(20): len = 225842, overlap = 1159.06
+PHY-3002 : Step(21): len = 230247, overlap = 1134.59
+PHY-3002 : Step(22): len = 227809, overlap = 1073
+PHY-3002 : Step(23): len = 225455, overlap = 1026.25
+PHY-3002 : Step(24): len = 220592, overlap = 1007.22
+PHY-3002 : Step(25): len = 217950, overlap = 1023.81
+PHY-3002 : Step(26): len = 215102, overlap = 1028.28
+PHY-3002 : Step(27): len = 212217, overlap = 1070.94
+PHY-3002 : Step(28): len = 210710, overlap = 1084.69
+PHY-3002 : Step(29): len = 207113, overlap = 1095.06
+PHY-3002 : Step(30): len = 204588, overlap = 1087.84
+PHY-3002 : Step(31): len = 203495, overlap = 1084.22
+PHY-3002 : Step(32): len = 201804, overlap = 1087.19
+PHY-3002 : Step(33): len = 202088, overlap = 1076.47
+PHY-3002 : Step(34): len = 200911, overlap = 1074.5
+PHY-3002 : Step(35): len = 200667, overlap = 1099.78
+PHY-3002 : Step(36): len = 200371, overlap = 1115.38
+PHY-3002 : Step(37): len = 201387, overlap = 1117.78
+PHY-3002 : Step(38): len = 200130, overlap = 1106.88
+PHY-3002 : Step(39): len = 200584, overlap = 1087.28
+PHY-3002 : Step(40): len = 198758, overlap = 1108.34
+PHY-3002 : Step(41): len = 199287, overlap = 1108.16
+PHY-3002 : Step(42): len = 198138, overlap = 1106.09
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 3.73016e-06
+PHY-3002 : Step(43): len = 204587, overlap = 1062.59
+PHY-3002 : Step(44): len = 217927, overlap = 1035.25
+PHY-3002 : Step(45): len = 226628, overlap = 974.125
+PHY-3002 : Step(46): len = 235146, overlap = 912.562
+PHY-3002 : Step(47): len = 239332, overlap = 872.969
+PHY-3002 : Step(48): len = 240805, overlap = 874.906
+PHY-3002 : Step(49): len = 239984, overlap = 866.531
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 7.46031e-06
+PHY-3002 : Step(50): len = 252025, overlap = 843
+PHY-3002 : Step(51): len = 277661, overlap = 716.5
+PHY-3002 : Step(52): len = 290494, overlap = 643.375
+PHY-3002 : Step(53): len = 297569, overlap = 589.719
+PHY-3002 : Step(54): len = 297172, overlap = 582.188
+PHY-3002 : Step(55): len = 295173, overlap = 589.156
+PHY-3002 : Step(56): len = 292148, overlap = 593.844
+PHY-3002 : Step(57): len = 290413, overlap = 597.375
+PHY-3002 : Step(58): len = 287775, overlap = 608.531
+PHY-3002 : Step(59): len = 286491, overlap = 630.312
+PHY-3002 : Step(60): len = 285640, overlap = 625.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.49206e-05
+PHY-3002 : Step(61): len = 303775, overlap = 580.094
+PHY-3002 : Step(62): len = 323788, overlap = 500.375
+PHY-3002 : Step(63): len = 332786, overlap = 458.969
+PHY-3002 : Step(64): len = 336953, overlap = 449.344
+PHY-3002 : Step(65): len = 335564, overlap = 442.969
+PHY-3002 : Step(66): len = 334411, overlap = 432.344
+PHY-3002 : Step(67): len = 331552, overlap = 439.312
+PHY-3002 : Step(68): len = 331372, overlap = 429.719
+PHY-3002 : Step(69): len = 330011, overlap = 427.625
+PHY-3002 : Step(70): len = 329856, overlap = 432.344
+PHY-3002 : Step(71): len = 329310, overlap = 441.656
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.98412e-05
+PHY-3002 : Step(72): len = 350245, overlap = 389.875
+PHY-3002 : Step(73): len = 361535, overlap = 361.844
+PHY-3002 : Step(74): len = 361142, overlap = 348.5
+PHY-3002 : Step(75): len = 362050, overlap = 350.312
+PHY-3002 : Step(76): len = 362870, overlap = 339.844
+PHY-3002 : Step(77): len = 364788, overlap = 338.094
+PHY-3002 : Step(78): len = 364761, overlap = 325.594
+PHY-3002 : Step(79): len = 366031, overlap = 304.5
+PHY-3002 : Step(80): len = 366563, overlap = 301.75
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 5.96825e-05
+PHY-3002 : Step(81): len = 384833, overlap = 277.344
+PHY-3002 : Step(82): len = 396595, overlap = 281.688
+PHY-3002 : Step(83): len = 396543, overlap = 293.094
+PHY-3002 : Step(84): len = 399101, overlap = 273.094
+PHY-3002 : Step(85): len = 402703, overlap = 257.125
+PHY-3002 : Step(86): len = 404917, overlap = 255.406
+PHY-3002 : Step(87): len = 403083, overlap = 259.875
+PHY-3002 : Step(88): len = 405003, overlap = 248.375
+PHY-3002 : Step(89): len = 406650, overlap = 235.469
+PHY-3002 : Step(90): len = 408001, overlap = 239.25
+PHY-3002 : Step(91): len = 406149, overlap = 238.375
+PHY-3002 : Step(92): len = 405938, overlap = 236.594
+PHY-3002 : Step(93): len = 406586, overlap = 233.156
+PHY-3002 : Step(94): len = 406976, overlap = 226.156
+PHY-3002 : Step(95): len = 405513, overlap = 227.062
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 0.000118842
+PHY-3002 : Step(96): len = 421248, overlap = 217.844
+PHY-3002 : Step(97): len = 429319, overlap = 205.031
+PHY-3002 : Step(98): len = 427464, overlap = 198.469
+PHY-3002 : Step(99): len = 429034, overlap = 196.094
+PHY-3002 : Step(100): len = 434105, overlap = 201.531
+PHY-3002 : Step(101): len = 437586, overlap = 195.062
+PHY-3002 : Step(102): len = 435528, overlap = 194.125
+PHY-3002 : Step(103): len = 435548, overlap = 192.094
+PHY-3002 : Step(104): len = 437020, overlap = 199.219
+PHY-3002 : Step(105): len = 438613, overlap = 206.969
+PHY-3002 : Step(106): len = 437625, overlap = 204.781
+PHY-3002 : Step(107): len = 438068, overlap = 181.406
+PHY-3002 : Step(108): len = 439671, overlap = 176.469
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000237684
+PHY-3002 : Step(109): len = 450914, overlap = 162.625
+PHY-3002 : Step(110): len = 460112, overlap = 162.875
+PHY-3002 : Step(111): len = 461891, overlap = 161.688
+PHY-3002 : Step(112): len = 464646, overlap = 159.062
+PHY-3002 : Step(113): len = 468264, overlap = 165.781
+PHY-3002 : Step(114): len = 469931, overlap = 160.656
+PHY-3002 : Step(115): len = 467248, overlap = 156.531
+PHY-3002 : Step(116): len = 466600, overlap = 161
+PHY-3002 : Step(117): len = 467545, overlap = 163.344
+PHY-3002 : Step(118): len = 468464, overlap = 161.344
+PHY-3002 : Step(119): len = 467707, overlap = 162.531
+PHY-3002 : Step(120): len = 467971, overlap = 160.594
+PHY-3002 : Step(121): len = 468918, overlap = 167.406
+PHY-3002 : Step(122): len = 469942, overlap = 168.906
+PHY-3002 : Step(123): len = 469453, overlap = 166.75
+PHY-3002 : Step(124): len = 469682, overlap = 167.469
+PHY-3002 : Step(125): len = 470737, overlap = 159.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000475368
+PHY-3002 : Step(126): len = 478080, overlap = 160.031
+PHY-3002 : Step(127): len = 484656, overlap = 157.031
+PHY-3002 : Step(128): len = 486098, overlap = 157.094
+PHY-3002 : Step(129): len = 487182, overlap = 155.188
+PHY-3002 : Step(130): len = 489476, overlap = 146.344
+PHY-3002 : Step(131): len = 491395, overlap = 146.031
+PHY-3002 : Step(132): len = 491713, overlap = 154.125
+PHY-3002 : Step(133): len = 492939, overlap = 147.625
+PHY-3002 : Step(134): len = 494576, overlap = 132.875
+PHY-3002 : Step(135): len = 496161, overlap = 137.594
+PHY-3002 : Step(136): len = 495988, overlap = 136.469
+PHY-3002 : Step(137): len = 496106, overlap = 140.25
+PHY-3002 : Step(138): len = 496266, overlap = 140.844
+PHY-3002 : Step(139): len = 496470, overlap = 137.406
+PHY-3002 : Step(140): len = 496546, overlap = 141.875
+PHY-3002 : Step(141): len = 496911, overlap = 147.312
+PHY-3002 : Step(142): len = 497266, overlap = 145.219
+PHY-3002 : Step(143): len = 497396, overlap = 142.25
+PHY-3002 : Step(144): len = 497065, overlap = 141.812
+PHY-3002 : Step(145): len = 497033, overlap = 141.844
+PHY-3002 : Step(146): len = 497338, overlap = 144.406
+PHY-3002 : Step(147): len = 497472, overlap = 144.5
+PHY-3002 : Step(148): len = 497385, overlap = 142.469
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000877422
+PHY-3002 : Step(149): len = 501184, overlap = 146.438
+PHY-3002 : Step(150): len = 504663, overlap = 147.25
+PHY-3002 : Step(151): len = 505596, overlap = 151.281
+PHY-3002 : Step(152): len = 506420, overlap = 146.594
+PHY-3002 : Step(153): len = 507917, overlap = 151.438
+PHY-3002 : Step(154): len = 508634, overlap = 149.938
+PHY-3002 : Step(155): len = 508927, overlap = 151.156
+PHY-3002 : Step(156): len = 509441, overlap = 149.938
+PHY-3002 : Step(157): len = 510216, overlap = 145.906
+PHY-3002 : Step(158): len = 510513, overlap = 147.094
+PHY-3002 : Step(159): len = 510634, overlap = 150.719
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.011420s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (136.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 664512, over cnt = 1539(4%), over = 7736, worst = 41
+PHY-1001 : End global iterations;  0.613713s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (147.7%)
+
+PHY-1001 : Congestion index: top1 = 84.74, top5 = 63.22, top10 = 53.23, top15 = 47.19.
+PHY-3001 : End congestion estimation;  0.825393s wall, 1.093750s user + 0.031250s system = 1.125000s CPU (136.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.833361s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000124634
+PHY-3002 : Step(160): len = 608040, overlap = 88.75
+PHY-3002 : Step(161): len = 613823, overlap = 76.3125
+PHY-3002 : Step(162): len = 609425, overlap = 72.4375
+PHY-3002 : Step(163): len = 606689, overlap = 62.875
+PHY-3002 : Step(164): len = 604912, overlap = 56.0625
+PHY-3002 : Step(165): len = 607328, overlap = 51.7812
+PHY-3002 : Step(166): len = 607168, overlap = 46.9688
+PHY-3002 : Step(167): len = 607492, overlap = 43.0312
+PHY-3002 : Step(168): len = 604916, overlap = 43.9375
+PHY-3002 : Step(169): len = 603312, overlap = 39.7812
+PHY-3002 : Step(170): len = 600505, overlap = 33.4688
+PHY-3002 : Step(171): len = 599443, overlap = 33.6562
+PHY-3002 : Step(172): len = 598160, overlap = 34.5312
+PHY-3002 : Step(173): len = 596331, overlap = 35.5625
+PHY-3002 : Step(174): len = 595700, overlap = 35.7188
+PHY-3002 : Step(175): len = 594872, overlap = 33.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000249268
+PHY-3002 : Step(176): len = 595960, overlap = 32.4688
+PHY-3002 : Step(177): len = 598337, overlap = 33.25
+PHY-3002 : Step(178): len = 602408, overlap = 31.3125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00049776
+PHY-3002 : Step(179): len = 611634, overlap = 31.8438
+PHY-3002 : Step(180): len = 625542, overlap = 30.125
+PHY-3002 : Step(181): len = 635983, overlap = 27.375
+PHY-3002 : Step(182): len = 637110, overlap = 28.2188
+PHY-3002 : Step(183): len = 638403, overlap = 30.9062
+PHY-3002 : Step(184): len = 638761, overlap = 30.4688
+PHY-3002 : Step(185): len = 640101, overlap = 31.7188
+PHY-3002 : Step(186): len = 642175, overlap = 29.5
+PHY-3002 : Step(187): len = 641185, overlap = 31
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00099552
+PHY-3002 : Step(188): len = 644934, overlap = 30.1875
+PHY-3002 : Step(189): len = 650268, overlap = 27.3438
+PHY-3002 : Step(190): len = 653497, overlap = 29.5312
+PHY-3002 : Step(191): len = 657219, overlap = 29.8438
+PHY-3002 : Step(192): len = 663338, overlap = 25.9062
+PHY-3002 : Step(193): len = 669266, overlap = 23.5312
+PHY-3002 : Step(194): len = 670438, overlap = 23.7188
+PHY-3002 : Step(195): len = 669668, overlap = 23.7188
+PHY-3002 : Step(196): len = 669357, overlap = 23
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00185661
+PHY-3002 : Step(197): len = 671998, overlap = 22.5938
+PHY-3002 : Step(198): len = 677210, overlap = 21.9688
+PHY-3002 : Step(199): len = 679487, overlap = 21.7812
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 70/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 765144, over cnt = 2759(7%), over = 13017, worst = 44
+PHY-1001 : End global iterations;  1.488265s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (134.4%)
+
+PHY-1001 : Congestion index: top1 = 86.68, top5 = 69.72, top10 = 61.49, top15 = 55.96.
+PHY-3001 : End congestion estimation;  1.811421s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (128.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.863097s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000140884
+PHY-3002 : Step(200): len = 668572, overlap = 217.5
+PHY-3002 : Step(201): len = 662032, overlap = 188.812
+PHY-3002 : Step(202): len = 651857, overlap = 181.156
+PHY-3002 : Step(203): len = 642621, overlap = 169.281
+PHY-3002 : Step(204): len = 635287, overlap = 160.312
+PHY-3002 : Step(205): len = 630004, overlap = 154.812
+PHY-3002 : Step(206): len = 624349, overlap = 150.75
+PHY-3002 : Step(207): len = 620699, overlap = 136.531
+PHY-3002 : Step(208): len = 615344, overlap = 136.312
+PHY-3002 : Step(209): len = 611617, overlap = 141.969
+PHY-3002 : Step(210): len = 607753, overlap = 141.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000281768
+PHY-3002 : Step(211): len = 608484, overlap = 133.125
+PHY-3002 : Step(212): len = 610978, overlap = 124.219
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000500218
+PHY-3002 : Step(213): len = 613053, overlap = 115.969
+PHY-3002 : Step(214): len = 618732, overlap = 108.875
+PHY-3002 : Step(215): len = 623533, overlap = 99.0312
+PHY-3002 : Step(216): len = 625038, overlap = 91.2812
+PHY-3002 : Step(217): len = 626570, overlap = 83.875
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.418071s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (99.2%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 562 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 411.97 peak overflow 4.06
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 761/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 726056, over cnt = 3016(8%), over = 11146, worst = 30
+PHY-1001 : End global iterations;  1.238566s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (135.0%)
+
+PHY-1001 : Congestion index: top1 = 72.31, top5 = 57.81, top10 = 51.49, top15 = 47.68.
+PHY-1001 : End incremental global routing;  1.562907s wall, 2.000000s user + 0.000000s system = 2.000000s CPU (128.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.239909s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (100.8%)
+
+OPT-1001 : 53 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17533 has valid locations, 351 needs to be replaced
+PHY-3001 : design contains 17969 instances, 7515 luts, 9233 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6026 pins
+PHY-3001 : Found 2379 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 649869
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16613/20549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741024, over cnt = 3045(8%), over = 11241, worst = 30
+PHY-1001 : End global iterations;  0.237967s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (144.5%)
+
+PHY-1001 : Congestion index: top1 = 72.44, top5 = 58.10, top10 = 51.95, top15 = 48.20.
+PHY-3001 : End congestion estimation;  0.480665s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (123.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85826, tnet num: 20371, tinst num: 17969, tnode num: 116508, tedge num: 137640.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.417974s wall, 1.359375s user + 0.062500s system = 1.421875s CPU (100.3%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 612 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.343093s wall, 2.281250s user + 0.062500s system = 2.343750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(218): len = 648883, overlap = 0.5
+PHY-3002 : Step(219): len = 648475, overlap = 0.125
+PHY-3002 : Step(220): len = 648205, overlap = 0.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16738/20549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738384, over cnt = 3040(8%), over = 11287, worst = 30
+PHY-1001 : End global iterations;  0.189947s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (131.6%)
+
+PHY-1001 : Congestion index: top1 = 73.15, top5 = 58.56, top10 = 52.21, top15 = 48.41.
+PHY-3001 : End congestion estimation;  0.434172s wall, 0.468750s user + 0.031250s system = 0.500000s CPU (115.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.900514s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000554625
+PHY-3002 : Step(221): len = 647930, overlap = 86.0938
+PHY-3002 : Step(222): len = 648101, overlap = 86.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00109363
+PHY-3002 : Step(223): len = 648496, overlap = 86.8125
+PHY-3002 : Step(224): len = 649103, overlap = 86.9375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00217303
+PHY-3002 : Step(225): len = 649200, overlap = 87.2188
+PHY-3002 : Step(226): len = 649698, overlap = 86.125
+PHY-3001 : Final: Len = 649698, Over = 86.125
+PHY-3001 : End incremental placement;  4.827558s wall, 5.078125s user + 0.296875s system = 5.375000s CPU (111.3%)
+
+OPT-1001 : Total overflow 418.38 peak overflow 4.06
+OPT-1001 : End high-fanout net optimization;  8.332179s wall, 8.984375s user + 0.343750s system = 9.328125s CPU (112.0%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 711, peak = 734.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16639/20549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 742368, over cnt = 2989(8%), over = 10225, worst = 30
+PHY-1002 : len = 789760, over cnt = 2161(6%), over = 5586, worst = 19
+PHY-1002 : len = 841304, over cnt = 800(2%), over = 1685, worst = 19
+PHY-1002 : len = 854616, over cnt = 448(1%), over = 803, worst = 10
+PHY-1002 : len = 867712, over cnt = 26(0%), over = 54, worst = 9
+PHY-1001 : End global iterations;  1.711312s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (139.7%)
+
+PHY-1001 : Congestion index: top1 = 59.20, top5 = 50.88, top10 = 46.96, top15 = 44.51.
+OPT-1001 : End congestion update;  1.960165s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (133.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.777232s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.5%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 54 cells processed and 7799 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 17 cells processed and 1950 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 27 cells processed and 650 slack improved
+OPT-1001 : End global optimization;  2.780715s wall, 3.437500s user + 0.015625s system = 3.453125s CPU (124.2%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 694, peak = 734.
+OPT-1001 : End physical optimization;  13.139972s wall, 14.484375s user + 0.390625s system = 14.875000s CPU (113.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7515 LUT to BLE ...
+SYN-4008 : Packed 7515 LUT and 3132 SEQ to BLE.
+SYN-4003 : Packing 6101 remaining SEQ's ...
+SYN-4005 : Packed 3884 SEQ with LUT/SLICE
+SYN-4006 : 792 single LUT's are left
+SYN-4006 : 2217 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9732/13463 primitive instances ...
+PHY-3001 : End packing;  1.611493s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6779 instances
+RUN-1001 : 3316 mslices, 3315 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17547 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9991 nets have 2 pins
+RUN-1001 : 5738 nets have [3 - 5] pins
+RUN-1001 : 1126 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 330 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6777 instances, 6631 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3535 pins
+PHY-3001 : Found 1035 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 659609, Over = 259.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7288/17547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 811424, over cnt = 1899(5%), over = 3080, worst = 8
+PHY-1002 : len = 819616, over cnt = 1208(3%), over = 1687, worst = 5
+PHY-1002 : len = 831608, over cnt = 444(1%), over = 591, worst = 5
+PHY-1002 : len = 837848, over cnt = 155(0%), over = 203, worst = 5
+PHY-1002 : len = 841800, over cnt = 5(0%), over = 7, worst = 3
+PHY-1001 : End global iterations;  1.546364s wall, 2.125000s user + 0.046875s system = 2.171875s CPU (140.5%)
+
+PHY-1001 : Congestion index: top1 = 59.01, top5 = 50.72, top10 = 46.55, top15 = 43.89.
+PHY-3001 : End congestion estimation;  1.924536s wall, 2.500000s user + 0.046875s system = 2.546875s CPU (132.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73545, tnet num: 17369, tinst num: 6777, tnode num: 95935, tedge num: 123463.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.631970s wall, 1.593750s user + 0.031250s system = 1.625000s CPU (99.6%)
+
+RUN-1004 : used memory is 610 MB, reserved memory is 609 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.472946s wall, 2.437500s user + 0.031250s system = 2.468750s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.79814e-05
+PHY-3002 : Step(227): len = 649249, overlap = 244.75
+PHY-3002 : Step(228): len = 643410, overlap = 240.75
+PHY-3002 : Step(229): len = 639818, overlap = 246.25
+PHY-3002 : Step(230): len = 637676, overlap = 268.75
+PHY-3002 : Step(231): len = 635073, overlap = 271.75
+PHY-3002 : Step(232): len = 632785, overlap = 273.5
+PHY-3002 : Step(233): len = 630657, overlap = 278.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.59628e-05
+PHY-3002 : Step(234): len = 633035, overlap = 279
+PHY-3002 : Step(235): len = 637910, overlap = 268.25
+PHY-3002 : Step(236): len = 638622, overlap = 267.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000191926
+PHY-3002 : Step(237): len = 646800, overlap = 248.75
+PHY-3002 : Step(238): len = 654843, overlap = 229
+PHY-3002 : Step(239): len = 653854, overlap = 227
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.338879s wall, 0.265625s user + 0.562500s system = 0.828125s CPU (244.4%)
+
+PHY-3001 : Trial Legalized: Len = 747081
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 775/17547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 866664, over cnt = 2630(7%), over = 4408, worst = 8
+PHY-1002 : len = 884288, over cnt = 1572(4%), over = 2299, worst = 7
+PHY-1002 : len = 909040, over cnt = 309(0%), over = 389, worst = 4
+PHY-1002 : len = 914176, over cnt = 27(0%), over = 31, worst = 2
+PHY-1002 : len = 915040, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.213857s wall, 3.390625s user + 0.046875s system = 3.437500s CPU (155.3%)
+
+PHY-1001 : Congestion index: top1 = 54.74, top5 = 49.99, top10 = 47.25, top15 = 45.25.
+PHY-3001 : End congestion estimation;  2.649820s wall, 3.843750s user + 0.046875s system = 3.890625s CPU (146.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.831032s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164028
+PHY-3002 : Step(240): len = 719392, overlap = 38.5
+PHY-3002 : Step(241): len = 703168, overlap = 65.5
+PHY-3002 : Step(242): len = 689283, overlap = 93.5
+PHY-3002 : Step(243): len = 679035, overlap = 123.5
+PHY-3002 : Step(244): len = 672872, overlap = 144.5
+PHY-3002 : Step(245): len = 669474, overlap = 159.25
+PHY-3002 : Step(246): len = 667104, overlap = 163.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328055
+PHY-3002 : Step(247): len = 671898, overlap = 159.25
+PHY-3002 : Step(248): len = 677509, overlap = 154.75
+PHY-3002 : Step(249): len = 677825, overlap = 155
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000596998
+PHY-3002 : Step(250): len = 682213, overlap = 149.5
+PHY-3002 : Step(251): len = 689791, overlap = 149.75
+PHY-3002 : Step(252): len = 694503, overlap = 147.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.045540s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (102.9%)
+
+PHY-3001 : Legalized: Len = 723763, Over = 0
+PHY-3001 : Spreading special nets. 415 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.103100s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (90.9%)
+
+PHY-3001 : 605 instances has been re-located, deltaX = 186, deltaY = 380, maxDist = 3.
+PHY-3001 : Final: Len = 733675, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73545, tnet num: 17369, tinst num: 6780, tnode num: 95935, tedge num: 123463.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.825553s wall, 1.781250s user + 0.046875s system = 1.828125s CPU (100.1%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 644 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3465/17547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863240, over cnt = 2506(7%), over = 4093, worst = 8
+PHY-1002 : len = 879248, over cnt = 1421(4%), over = 2014, worst = 7
+PHY-1002 : len = 893064, over cnt = 625(1%), over = 874, worst = 7
+PHY-1002 : len = 899648, over cnt = 329(0%), over = 478, worst = 5
+PHY-1002 : len = 906152, over cnt = 62(0%), over = 101, worst = 5
+PHY-1001 : End global iterations;  1.977825s wall, 3.031250s user + 0.015625s system = 3.046875s CPU (154.1%)
+
+PHY-1001 : Congestion index: top1 = 55.80, top5 = 49.50, top10 = 46.22, top15 = 44.17.
+PHY-1001 : End incremental global routing;  2.349169s wall, 3.421875s user + 0.015625s system = 3.437500s CPU (146.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.841467s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.3%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6686 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6800 instances, 6651 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3614 pins
+PHY-3001 : Found 1039 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 737166
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15939/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910352, over cnt = 152(0%), over = 201, worst = 5
+PHY-1002 : len = 910856, over cnt = 85(0%), over = 102, worst = 5
+PHY-1002 : len = 911808, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 911904, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 912064, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.783950s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 49.28, top10 = 46.20, top15 = 44.24.
+PHY-3001 : End congestion estimation;  1.089977s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (104.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73740, tnet num: 17394, tinst num: 6800, tnode num: 96180, tedge num: 123746.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.824786s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.2%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 662 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.692506s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(253): len = 735912, overlap = 0.25
+PHY-3002 : Step(254): len = 735422, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15924/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908840, over cnt = 92(0%), over = 110, worst = 5
+PHY-1002 : len = 908696, over cnt = 59(0%), over = 64, worst = 3
+PHY-1002 : len = 909112, over cnt = 22(0%), over = 22, worst = 1
+PHY-1002 : len = 909352, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 909408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.777319s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (106.5%)
+
+PHY-1001 : Congestion index: top1 = 55.06, top5 = 49.36, top10 = 46.23, top15 = 44.26.
+PHY-3001 : End congestion estimation;  1.091734s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (105.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.917632s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000223984
+PHY-3002 : Step(255): len = 735757, overlap = 1.75
+PHY-3002 : Step(256): len = 735645, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005686s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 735524, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059362s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 2, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 735594, Over = 0
+PHY-3001 : End incremental placement;  6.260445s wall, 6.421875s user + 0.093750s system = 6.515625s CPU (104.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.929218s wall, 11.156250s user + 0.125000s system = 11.281250s CPU (113.6%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 737, peak = 741.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15897/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909360, over cnt = 74(0%), over = 85, worst = 3
+PHY-1002 : len = 909296, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 909376, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 909512, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 909624, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.794750s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (108.1%)
+
+PHY-1001 : Congestion index: top1 = 55.00, top5 = 49.21, top10 = 46.15, top15 = 44.19.
+OPT-1001 : End congestion update;  1.096569s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.709385s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.3%)
+
+OPT-0007 : Start: WNS -1083 TNS -1718 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6712 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6800 instances, 6651 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3614 pins
+PHY-3001 : Found 1039 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 738130, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061471s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 15, deltaY = 14, maxDist = 2.
+PHY-3001 : Final: Len = 738384, Over = 0
+PHY-3001 : End incremental legalization;  0.417178s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.1%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 34 cells processed and 8950 slack improved
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.377672s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (102.5%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 737, peak = 741.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.700204s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15813/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912096, over cnt = 71(0%), over = 88, worst = 4
+PHY-1002 : len = 911880, over cnt = 47(0%), over = 51, worst = 4
+PHY-1002 : len = 912072, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 912424, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 912584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.754215s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (105.7%)
+
+PHY-1001 : Congestion index: top1 = 55.02, top5 = 49.32, top10 = 46.23, top15 = 44.21.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.711104s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1033 TNS -1618 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 54.517241
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1033ps with logic level 2 
+RUN-1001 :       #2 path slack -947ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17572 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17572 nets
+OPT-1001 : End physical optimization;  16.963698s wall, 18.218750s user + 0.203125s system = 18.421875s CPU (108.6%)
+
+RUN-1003 : finish command "place" in  56.333337s wall, 82.531250s user + 5.031250s system = 87.562500s CPU (155.4%)
+
+RUN-1004 : used memory is 607 MB, reserved memory is 613 MB, peak memory is 741 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.665760s wall, 2.875000s user + 0.015625s system = 2.890625s CPU (173.5%)
+
+RUN-1004 : used memory is 607 MB, reserved memory is 614 MB, peak memory is 741 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6802 instances
+RUN-1001 : 3324 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17572 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9995 nets have 2 pins
+RUN-1001 : 5739 nets have [3 - 5] pins
+RUN-1001 : 1131 nets have [6 - 10] pins
+RUN-1001 : 330 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73740, tnet num: 17394, tinst num: 6800, tnode num: 96180, tedge num: 123746.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.603025s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (100.4%)
+
+RUN-1004 : used memory is 604 MB, reserved memory is 602 MB, peak memory is 741 MB
+PHY-1001 : 3324 mslices, 3327 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847656, over cnt = 2689(7%), over = 4421, worst = 7
+PHY-1002 : len = 865904, over cnt = 1591(4%), over = 2267, worst = 6
+PHY-1002 : len = 880512, over cnt = 816(2%), over = 1143, worst = 6
+PHY-1002 : len = 898496, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 898696, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.958838s wall, 4.156250s user + 0.015625s system = 4.171875s CPU (141.0%)
+
+PHY-1001 : Congestion index: top1 = 55.73, top5 = 49.67, top10 = 46.33, top15 = 44.13.
+PHY-1001 : End global routing;  3.282095s wall, 4.453125s user + 0.031250s system = 4.484375s CPU (136.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 714, peak = 741.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 983, reserve = 986, peak = 983.
+PHY-1001 : End build detailed router design. 3.938069s wall, 3.859375s user + 0.078125s system = 3.937500s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 272480, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.052307s wall, 5.062500s user + 0.000000s system = 5.062500s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 272536, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.423225s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1019, reserve = 1024, peak = 1019.
+PHY-1001 : End phase 1; 5.487741s wall, 5.484375s user + 0.000000s system = 5.484375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.29591e+06, over cnt = 1965(0%), over = 1977, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1042, peak = 1038.
+PHY-1001 : End initial routed; 22.900949s wall, 52.296875s user + 0.515625s system = 52.812500s CPU (230.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16494(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.923   |  -3.675   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.286618s wall, 3.250000s user + 0.031250s system = 3.281250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1057, peak = 1047.
+PHY-1001 : End phase 2; 26.187642s wall, 55.546875s user + 0.546875s system = 56.093750s CPU (214.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.800ns STNS -3.552ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.144138s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.6%)
+
+PHY-1022 : len = 2.29593e+06, over cnt = 1966(0%), over = 1978, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.423880s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.2631e+06, over cnt = 734(0%), over = 735, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.641333s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (163.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.26043e+06, over cnt = 142(0%), over = 142, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.917513s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (131.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.26106e+06, over cnt = 32(0%), over = 32, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.550060s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (107.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.2618e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.361163s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.245280s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (101.9%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.263493s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.383813s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.8%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.262e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.170235s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (110.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.26202e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.161460s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16494(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.800   |  -3.552   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.315988s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 596 feed throughs used by 432 nets
+PHY-1001 : End commit to database; 2.211738s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1149, reserve = 1163, peak = 1149.
+PHY-1001 : End phase 3; 11.037053s wall, 12.406250s user + 0.031250s system = 12.437500s CPU (112.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.800ns STNS -3.552ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.135704s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%)
+
+PHY-1022 : len = 2.26202e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.373015s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.800ns, -3.552ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16494(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.800   |  -3.552   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.203921s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 596 feed throughs used by 432 nets
+PHY-1001 : End commit to database; 2.278510s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1172, peak = 1158.
+PHY-1001 : End phase 4; 5.881849s wall, 5.890625s user + 0.000000s system = 5.890625s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.26202e+06
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1177, peak = 1163.
+PHY-1001 : End export database. 0.061940s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.9%)
+
+PHY-1001 : End detail routing;  52.991805s wall, 83.640625s user + 0.656250s system = 84.296875s CPU (159.1%)
+
+RUN-1003 : finish command "route" in  58.956089s wall, 90.750000s user + 0.718750s system = 91.468750s CPU (155.1%)
+
+RUN-1004 : used memory is 1026 MB, reserved memory is 1051 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10236   out of  19600   52.22%
+#reg                     9380   out of  19600   47.86%
+#le                     12373
+  #lut only              2993   out of  12373   24.19%
+  #reg only              2137   out of  12373   17.27%
+  #lut&reg               7243   out of  12373   58.54%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1814
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1377
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1321
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               967
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    132
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/reg2_syn_161.f1                        3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg3_syn_155.f1                          3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12373  |9209    |1027    |9412    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |537    |434     |23      |434     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |101    |91      |4       |86      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |35     |35      |0       |23      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |777    |435     |96      |584     |0       |0       |
+|    u_ADconfig                |AD_config            |195    |151     |25      |148     |0       |0       |
+|    u_gen_sp                  |gen_sp               |266    |162     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |723    |404     |96      |545     |0       |0       |
+|    u_ADconfig                |AD_config            |165    |113     |25      |123     |0       |0       |
+|    u_gen_sp                  |gen_sp               |257    |150     |71      |121     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3078   |2408    |306     |2107    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |182    |115     |17      |143     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2863   |2276    |289     |1931    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |6      |3       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |3       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2424   |1955    |253     |1580    |22      |0       |
+|        channelPart           |channel_part_8478    |134    |127     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |57     |48      |9       |39      |0       |0       |
+|        ram_switch            |ram_switch           |1918   |1531    |197     |1187    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |243    |216     |27      |118     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |17      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|          insert              |insert               |1011   |652     |170     |720     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |664    |663     |0       |349     |0       |0       |
+|        read_ram_i            |read_ram             |274    |215     |44      |187     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |213    |173     |40      |143     |0       |0       |
+|          read_ram_data       |read_ram_data        |58     |41      |4       |41      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |345    |246     |36      |279     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3183   |2496    |349     |2089    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |100     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2969   |2387    |332     |1909    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |5       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2517   |2038    |290     |1551    |22      |1       |
+|        channelPart           |channel_part_8478    |235    |232     |3       |141     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |46      |0       |1       |
+|        ram_switch            |ram_switch           |1832   |1484    |197     |1125    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |222    |195     |27      |109     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |6       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |8       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|          insert              |insert               |994    |679     |170     |678     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |616    |610     |0       |338     |0       |0       |
+|        read_ram_i            |read_ram_rev         |356    |241     |81      |208     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |291    |209     |73      |161     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |32      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets  
+    #1          1       9933  
+    #2          2       3795  
+    #3          3       1376  
+    #4          4       565   
+    #5        5-10      1185  
+    #6        11-50     604   
+    #7       51-100      17   
+    #8       101-500     1    
+    #9        >500       1    
+  Average     2.90            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.121534s wall, 3.546875s user + 0.015625s system = 3.562500s CPU (167.9%)
+
+RUN-1004 : used memory is 1028 MB, reserved memory is 1053 MB, peak memory is 1163 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73740, tnet num: 17394, tinst num: 6800, tnode num: 96180, tedge num: 123746.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.649398s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.4%)
+
+RUN-1004 : used memory is 1031 MB, reserved memory is 1056 MB, peak memory is 1163 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.476537s wall, 1.421875s user + 0.046875s system = 1.468750s CPU (99.5%)
+
+RUN-1004 : used memory is 1084 MB, reserved memory is 1109 MB, peak memory is 1163 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6800
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17572, pip num: 171589
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 596
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3258 valid insts, and 477073 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.953446s wall, 68.953125s user + 0.140625s system = 69.093750s CPU (694.2%)
+
+RUN-1004 : used memory is 1262 MB, reserved memory is 1264 MB, peak memory is 1378 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_103905.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_104647.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_104647.log
new file mode 100644
index 0000000..a442d73
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_104647.log
@@ -0,0 +1,1854 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:46:47 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.141890s wall, 2.062500s user + 0.062500s system = 2.125000s CPU (99.2%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 314 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.120751s wall, 1.093750s user + 0.031250s system = 1.125000s CPU (100.4%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 513 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.890668s wall, 1.843750s user + 0.046875s system = 1.890625s CPU (100.0%)
+
+PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.126067s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (111.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28668e+06, overlap = 484.094
+PHY-3002 : Step(2): len = 1.18318e+06, overlap = 557.375
+PHY-3002 : Step(3): len = 843931, overlap = 601.625
+PHY-3002 : Step(4): len = 791874, overlap = 624.344
+PHY-3002 : Step(5): len = 609615, overlap = 754.969
+PHY-3002 : Step(6): len = 529112, overlap = 805.719
+PHY-3002 : Step(7): len = 456874, overlap = 912.031
+PHY-3002 : Step(8): len = 425331, overlap = 995.844
+PHY-3002 : Step(9): len = 378282, overlap = 1057.66
+PHY-3002 : Step(10): len = 340965, overlap = 1115.97
+PHY-3002 : Step(11): len = 297218, overlap = 1185.28
+PHY-3002 : Step(12): len = 272422, overlap = 1214.28
+PHY-3002 : Step(13): len = 251103, overlap = 1252.66
+PHY-3002 : Step(14): len = 233830, overlap = 1297.31
+PHY-3002 : Step(15): len = 207240, overlap = 1327.09
+PHY-3002 : Step(16): len = 192315, overlap = 1358.84
+PHY-3002 : Step(17): len = 174239, overlap = 1404.44
+PHY-3002 : Step(18): len = 162009, overlap = 1423.03
+PHY-3002 : Step(19): len = 147685, overlap = 1465.97
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2036e-06
+PHY-3002 : Step(20): len = 148424, overlap = 1423.66
+PHY-3002 : Step(21): len = 179191, overlap = 1304.53
+PHY-3002 : Step(22): len = 190294, overlap = 1232.22
+PHY-3002 : Step(23): len = 199319, overlap = 1189.78
+PHY-3002 : Step(24): len = 198566, overlap = 1179.34
+PHY-3002 : Step(25): len = 198247, overlap = 1163.12
+PHY-3002 : Step(26): len = 195020, overlap = 1157.25
+PHY-3002 : Step(27): len = 194648, overlap = 1158.09
+PHY-3002 : Step(28): len = 193918, overlap = 1142.66
+PHY-3002 : Step(29): len = 192851, overlap = 1149.03
+PHY-3002 : Step(30): len = 191764, overlap = 1148.06
+PHY-3002 : Step(31): len = 190566, overlap = 1168.28
+PHY-3002 : Step(32): len = 188829, overlap = 1145.56
+PHY-3002 : Step(33): len = 188125, overlap = 1149.47
+PHY-3002 : Step(34): len = 187128, overlap = 1136
+PHY-3002 : Step(35): len = 186806, overlap = 1099.56
+PHY-3002 : Step(36): len = 184419, overlap = 1073.5
+PHY-3002 : Step(37): len = 183688, overlap = 1074.06
+PHY-3002 : Step(38): len = 181963, overlap = 1075.84
+PHY-3002 : Step(39): len = 180821, overlap = 1100.16
+PHY-3002 : Step(40): len = 180049, overlap = 1107.62
+PHY-3002 : Step(41): len = 178563, overlap = 1115.78
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.40721e-06
+PHY-3002 : Step(42): len = 182212, overlap = 1088.72
+PHY-3002 : Step(43): len = 192003, overlap = 1041.94
+PHY-3002 : Step(44): len = 195313, overlap = 996.5
+PHY-3002 : Step(45): len = 200502, overlap = 971.938
+PHY-3002 : Step(46): len = 203704, overlap = 964.062
+PHY-3002 : Step(47): len = 207043, overlap = 946.125
+PHY-3002 : Step(48): len = 207363, overlap = 916.281
+PHY-3002 : Step(49): len = 207868, overlap = 907.031
+PHY-3002 : Step(50): len = 206820, overlap = 918.844
+PHY-3002 : Step(51): len = 206254, overlap = 931.125
+PHY-3002 : Step(52): len = 204603, overlap = 938.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.81441e-06
+PHY-3002 : Step(53): len = 211487, overlap = 931
+PHY-3002 : Step(54): len = 228174, overlap = 895.562
+PHY-3002 : Step(55): len = 237150, overlap = 803.812
+PHY-3002 : Step(56): len = 242854, overlap = 767.344
+PHY-3002 : Step(57): len = 244809, overlap = 750.625
+PHY-3002 : Step(58): len = 247200, overlap = 746.219
+PHY-3002 : Step(59): len = 246762, overlap = 749.906
+PHY-3002 : Step(60): len = 246476, overlap = 758.188
+PHY-3002 : Step(61): len = 245504, overlap = 776.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.62883e-06
+PHY-3002 : Step(62): len = 259270, overlap = 736.844
+PHY-3002 : Step(63): len = 280310, overlap = 622.125
+PHY-3002 : Step(64): len = 289452, overlap = 594.688
+PHY-3002 : Step(65): len = 292950, overlap = 596.625
+PHY-3002 : Step(66): len = 291834, overlap = 562.719
+PHY-3002 : Step(67): len = 289272, overlap = 547.375
+PHY-3002 : Step(68): len = 287091, overlap = 546.344
+PHY-3002 : Step(69): len = 287110, overlap = 528.281
+PHY-3002 : Step(70): len = 287591, overlap = 509.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.92577e-05
+PHY-3002 : Step(71): len = 306070, overlap = 487.531
+PHY-3002 : Step(72): len = 321535, overlap = 471.406
+PHY-3002 : Step(73): len = 327807, overlap = 437.219
+PHY-3002 : Step(74): len = 332649, overlap = 431.281
+PHY-3002 : Step(75): len = 331947, overlap = 424.094
+PHY-3002 : Step(76): len = 332519, overlap = 428.656
+PHY-3002 : Step(77): len = 332226, overlap = 415.594
+PHY-3002 : Step(78): len = 331189, overlap = 397.969
+PHY-3002 : Step(79): len = 330580, overlap = 386.438
+PHY-3002 : Step(80): len = 331430, overlap = 383.438
+PHY-3002 : Step(81): len = 332546, overlap = 365.906
+PHY-3002 : Step(82): len = 332833, overlap = 367.281
+PHY-3002 : Step(83): len = 331822, overlap = 367.219
+PHY-3002 : Step(84): len = 332233, overlap = 356.375
+PHY-3002 : Step(85): len = 331344, overlap = 344.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.85153e-05
+PHY-3002 : Step(86): len = 350518, overlap = 322.5
+PHY-3002 : Step(87): len = 360328, overlap = 306.594
+PHY-3002 : Step(88): len = 357880, overlap = 317.406
+PHY-3002 : Step(89): len = 358822, overlap = 305.344
+PHY-3002 : Step(90): len = 363911, overlap = 302.406
+PHY-3002 : Step(91): len = 367835, overlap = 304.938
+PHY-3002 : Step(92): len = 363522, overlap = 317.188
+PHY-3002 : Step(93): len = 365018, overlap = 310.875
+PHY-3002 : Step(94): len = 367761, overlap = 310.25
+PHY-3002 : Step(95): len = 369860, overlap = 319.094
+PHY-3002 : Step(96): len = 365177, overlap = 314.25
+PHY-3002 : Step(97): len = 363436, overlap = 316.188
+PHY-3002 : Step(98): len = 364963, overlap = 322.094
+PHY-3002 : Step(99): len = 366885, overlap = 314
+PHY-3002 : Step(100): len = 363632, overlap = 313.844
+PHY-3002 : Step(101): len = 363549, overlap = 310.25
+PHY-3002 : Step(102): len = 364192, overlap = 304.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.70306e-05
+PHY-3002 : Step(103): len = 382186, overlap = 300.719
+PHY-3002 : Step(104): len = 393320, overlap = 290.438
+PHY-3002 : Step(105): len = 390061, overlap = 265.469
+PHY-3002 : Step(106): len = 389428, overlap = 253.938
+PHY-3002 : Step(107): len = 394384, overlap = 237.344
+PHY-3002 : Step(108): len = 399627, overlap = 227.5
+PHY-3002 : Step(109): len = 397812, overlap = 236.219
+PHY-3002 : Step(110): len = 399415, overlap = 243.656
+PHY-3002 : Step(111): len = 402607, overlap = 242.125
+PHY-3002 : Step(112): len = 404322, overlap = 239.312
+PHY-3002 : Step(113): len = 400761, overlap = 240.844
+PHY-3002 : Step(114): len = 399368, overlap = 243.125
+PHY-3002 : Step(115): len = 401595, overlap = 233.938
+PHY-3002 : Step(116): len = 404676, overlap = 239.812
+PHY-3002 : Step(117): len = 400962, overlap = 247.219
+PHY-3002 : Step(118): len = 400739, overlap = 247.281
+PHY-3002 : Step(119): len = 402377, overlap = 239.938
+PHY-3002 : Step(120): len = 404242, overlap = 244.781
+PHY-3002 : Step(121): len = 401723, overlap = 248.594
+PHY-3002 : Step(122): len = 401871, overlap = 252.375
+PHY-3002 : Step(123): len = 404195, overlap = 251.375
+PHY-3002 : Step(124): len = 406140, overlap = 257.312
+PHY-3002 : Step(125): len = 403540, overlap = 259.656
+PHY-3002 : Step(126): len = 403245, overlap = 259.188
+PHY-3002 : Step(127): len = 403984, overlap = 258
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154061
+PHY-3002 : Step(128): len = 419164, overlap = 244.906
+PHY-3002 : Step(129): len = 428463, overlap = 233.125
+PHY-3002 : Step(130): len = 426829, overlap = 217.812
+PHY-3002 : Step(131): len = 427102, overlap = 211.844
+PHY-3002 : Step(132): len = 429947, overlap = 210.938
+PHY-3002 : Step(133): len = 431921, overlap = 206.281
+PHY-3002 : Step(134): len = 429822, overlap = 204.156
+PHY-3002 : Step(135): len = 430225, overlap = 212.344
+PHY-3002 : Step(136): len = 432285, overlap = 210.5
+PHY-3002 : Step(137): len = 434226, overlap = 207.281
+PHY-3002 : Step(138): len = 433644, overlap = 199.531
+PHY-3002 : Step(139): len = 434785, overlap = 208.406
+PHY-3002 : Step(140): len = 436011, overlap = 203.75
+PHY-3002 : Step(141): len = 437222, overlap = 200.469
+PHY-3002 : Step(142): len = 436221, overlap = 201.188
+PHY-3002 : Step(143): len = 436724, overlap = 207.406
+PHY-3002 : Step(144): len = 437985, overlap = 207.875
+PHY-3002 : Step(145): len = 439045, overlap = 207.375
+PHY-3002 : Step(146): len = 437923, overlap = 207.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000297449
+PHY-3002 : Step(147): len = 447213, overlap = 201.406
+PHY-3002 : Step(148): len = 454452, overlap = 203.656
+PHY-3002 : Step(149): len = 454959, overlap = 198.281
+PHY-3002 : Step(150): len = 455780, overlap = 191
+PHY-3002 : Step(151): len = 458270, overlap = 186.562
+PHY-3002 : Step(152): len = 459849, overlap = 184
+PHY-3002 : Step(153): len = 458838, overlap = 186.688
+PHY-3002 : Step(154): len = 459485, overlap = 181.969
+PHY-3002 : Step(155): len = 461789, overlap = 184.562
+PHY-3002 : Step(156): len = 463496, overlap = 173.094
+PHY-3002 : Step(157): len = 462326, overlap = 171.438
+PHY-3002 : Step(158): len = 462656, overlap = 170.656
+PHY-3002 : Step(159): len = 464690, overlap = 167.469
+PHY-3002 : Step(160): len = 466201, overlap = 171.656
+PHY-3002 : Step(161): len = 465166, overlap = 165.188
+PHY-3002 : Step(162): len = 465218, overlap = 167.594
+PHY-3002 : Step(163): len = 466623, overlap = 165.719
+PHY-3002 : Step(164): len = 467287, overlap = 162.25
+PHY-3002 : Step(165): len = 466412, overlap = 161.688
+PHY-3002 : Step(166): len = 466327, overlap = 158.469
+PHY-3002 : Step(167): len = 467295, overlap = 161.75
+PHY-3002 : Step(168): len = 468354, overlap = 160.594
+PHY-3002 : Step(169): len = 468124, overlap = 155.656
+PHY-3002 : Step(170): len = 468614, overlap = 159.062
+PHY-3002 : Step(171): len = 469394, overlap = 153.281
+PHY-3002 : Step(172): len = 469789, overlap = 151.75
+PHY-3002 : Step(173): len = 470169, overlap = 135.656
+PHY-3002 : Step(174): len = 471663, overlap = 137.594
+PHY-3002 : Step(175): len = 472466, overlap = 133.844
+PHY-3002 : Step(176): len = 473025, overlap = 132.812
+PHY-3002 : Step(177): len = 472951, overlap = 135.25
+PHY-3002 : Step(178): len = 473084, overlap = 136.938
+PHY-3002 : Step(179): len = 473356, overlap = 135.25
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000566962
+PHY-3002 : Step(180): len = 479949, overlap = 132.312
+PHY-3002 : Step(181): len = 485650, overlap = 134
+PHY-3002 : Step(182): len = 486958, overlap = 125.781
+PHY-3002 : Step(183): len = 488201, overlap = 126
+PHY-3002 : Step(184): len = 490404, overlap = 126.844
+PHY-3002 : Step(185): len = 492125, overlap = 131.5
+PHY-3002 : Step(186): len = 492854, overlap = 128.094
+PHY-3002 : Step(187): len = 494116, overlap = 125.406
+PHY-3002 : Step(188): len = 496340, overlap = 126.312
+PHY-3002 : Step(189): len = 497988, overlap = 123.688
+PHY-3002 : Step(190): len = 498041, overlap = 122.812
+PHY-3002 : Step(191): len = 498102, overlap = 120.5
+PHY-3002 : Step(192): len = 498689, overlap = 124.594
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109183
+PHY-3002 : Step(193): len = 502699, overlap = 120.406
+PHY-3002 : Step(194): len = 508726, overlap = 117.844
+PHY-3002 : Step(195): len = 511069, overlap = 114.281
+PHY-3002 : Step(196): len = 512644, overlap = 114.906
+PHY-3002 : Step(197): len = 513979, overlap = 114.875
+PHY-3002 : Step(198): len = 515197, overlap = 112.781
+PHY-3002 : Step(199): len = 515367, overlap = 112.906
+PHY-3002 : Step(200): len = 515820, overlap = 108.875
+PHY-3002 : Step(201): len = 516704, overlap = 111.188
+PHY-3002 : Step(202): len = 517142, overlap = 112.75
+PHY-3002 : Step(203): len = 517073, overlap = 107.688
+PHY-3002 : Step(204): len = 517115, overlap = 107.688
+PHY-3002 : Step(205): len = 517492, overlap = 112
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00191502
+PHY-3002 : Step(206): len = 520575, overlap = 107.125
+PHY-3002 : Step(207): len = 525493, overlap = 102.531
+PHY-3002 : Step(208): len = 526615, overlap = 100.969
+PHY-3002 : Step(209): len = 527208, overlap = 101.75
+PHY-3002 : Step(210): len = 528067, overlap = 102.562
+PHY-3002 : Step(211): len = 529197, overlap = 104.125
+PHY-3002 : Step(212): len = 530271, overlap = 102.125
+PHY-3002 : Step(213): len = 532302, overlap = 102.125
+PHY-3002 : Step(214): len = 533399, overlap = 103.219
+PHY-3002 : Step(215): len = 533896, overlap = 100.969
+PHY-3002 : Step(216): len = 534380, overlap = 98.9375
+PHY-3002 : Step(217): len = 534814, overlap = 96.5
+PHY-3002 : Step(218): len = 535308, overlap = 96.6875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.011535s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (135.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 705016, over cnt = 1536(4%), over = 7270, worst = 58
+PHY-1001 : End global iterations;  0.691043s wall, 0.984375s user + 0.046875s system = 1.031250s CPU (149.2%)
+
+PHY-1001 : Congestion index: top1 = 78.64, top5 = 60.55, top10 = 51.46, top15 = 45.82.
+PHY-3001 : End congestion estimation;  0.916884s wall, 1.203125s user + 0.046875s system = 1.250000s CPU (136.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.233140s wall, 1.218750s user + 0.015625s system = 1.234375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143207
+PHY-3002 : Step(219): len = 646213, overlap = 36.1875
+PHY-3002 : Step(220): len = 644319, overlap = 34.0938
+PHY-3002 : Step(221): len = 639708, overlap = 39.3438
+PHY-3002 : Step(222): len = 639697, overlap = 46.5312
+PHY-3002 : Step(223): len = 642009, overlap = 48.0312
+PHY-3002 : Step(224): len = 641422, overlap = 47.8125
+PHY-3002 : Step(225): len = 640251, overlap = 44.2188
+PHY-3002 : Step(226): len = 638069, overlap = 35.5625
+PHY-3002 : Step(227): len = 635262, overlap = 23.5
+PHY-3002 : Step(228): len = 631544, overlap = 27.6875
+PHY-3002 : Step(229): len = 628555, overlap = 28.2812
+PHY-3002 : Step(230): len = 626551, overlap = 29.0312
+PHY-3002 : Step(231): len = 624331, overlap = 32.0312
+PHY-3002 : Step(232): len = 622629, overlap = 37.5625
+PHY-3002 : Step(233): len = 620279, overlap = 34.2812
+PHY-3002 : Step(234): len = 620152, overlap = 34.7812
+PHY-3002 : Step(235): len = 617309, overlap = 36.5625
+PHY-3002 : Step(236): len = 615563, overlap = 38.2188
+PHY-3002 : Step(237): len = 614250, overlap = 37.7812
+PHY-3002 : Step(238): len = 613568, overlap = 37.75
+PHY-3002 : Step(239): len = 611804, overlap = 36.5
+PHY-3002 : Step(240): len = 610938, overlap = 38.875
+PHY-3002 : Step(241): len = 609379, overlap = 39.9062
+PHY-3002 : Step(242): len = 608310, overlap = 39.2812
+PHY-3002 : Step(243): len = 607656, overlap = 40.0312
+PHY-3002 : Step(244): len = 605710, overlap = 41.8438
+PHY-3002 : Step(245): len = 605011, overlap = 44.0625
+PHY-3002 : Step(246): len = 603058, overlap = 43.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000286414
+PHY-3002 : Step(247): len = 605841, overlap = 43.4688
+PHY-3002 : Step(248): len = 609140, overlap = 42.8438
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000469768
+PHY-3002 : Step(249): len = 613099, overlap = 42.2188
+PHY-3002 : Step(250): len = 620558, overlap = 41.125
+PHY-3002 : Step(251): len = 635556, overlap = 34.5938
+PHY-3002 : Step(252): len = 638311, overlap = 33.125
+PHY-3002 : Step(253): len = 640895, overlap = 31.9375
+PHY-3002 : Step(254): len = 642045, overlap = 32.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731656, over cnt = 2654(7%), over = 12250, worst = 64
+PHY-1001 : End global iterations;  1.715597s wall, 2.328125s user + 0.015625s system = 2.343750s CPU (136.6%)
+
+PHY-1001 : Congestion index: top1 = 85.02, top5 = 66.04, top10 = 57.79, top15 = 52.68.
+PHY-3001 : End congestion estimation;  1.972284s wall, 2.578125s user + 0.031250s system = 2.609375s CPU (132.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.870517s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012412
+PHY-3002 : Step(255): len = 634493, overlap = 218.594
+PHY-3002 : Step(256): len = 633945, overlap = 186.656
+PHY-3002 : Step(257): len = 624281, overlap = 182.938
+PHY-3002 : Step(258): len = 620956, overlap = 176.469
+PHY-3002 : Step(259): len = 616979, overlap = 157.156
+PHY-3002 : Step(260): len = 613520, overlap = 135.344
+PHY-3002 : Step(261): len = 609779, overlap = 127.906
+PHY-3002 : Step(262): len = 608368, overlap = 127.469
+PHY-3002 : Step(263): len = 603987, overlap = 124.812
+PHY-3002 : Step(264): len = 601816, overlap = 126.906
+PHY-3002 : Step(265): len = 599563, overlap = 125.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00024824
+PHY-3002 : Step(266): len = 599695, overlap = 121.312
+PHY-3002 : Step(267): len = 601392, overlap = 118.5
+PHY-3002 : Step(268): len = 603887, overlap = 117.031
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000496481
+PHY-3002 : Step(269): len = 610653, overlap = 103.031
+PHY-3002 : Step(270): len = 617658, overlap = 96.375
+PHY-3002 : Step(271): len = 621957, overlap = 93.625
+PHY-3002 : Step(272): len = 624159, overlap = 89.5625
+PHY-3002 : Step(273): len = 623537, overlap = 89.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.413531s wall, 1.390625s user + 0.031250s system = 1.421875s CPU (100.6%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 563 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 402.84 peak overflow 2.69
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 966/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725272, over cnt = 2983(8%), over = 10954, worst = 26
+PHY-1001 : End global iterations;  1.163557s wall, 1.718750s user + 0.062500s system = 1.781250s CPU (153.1%)
+
+PHY-1001 : Congestion index: top1 = 65.78, top5 = 55.57, top10 = 50.32, top15 = 46.98.
+PHY-1001 : End incremental global routing;  1.479958s wall, 2.015625s user + 0.062500s system = 2.078125s CPU (140.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.886052s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.5%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 332 needs to be replaced
+PHY-3001 : design contains 17952 instances, 7503 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6004 pins
+PHY-3001 : Found 1238 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 648311
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16555/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741400, over cnt = 3040(8%), over = 11005, worst = 23
+PHY-1001 : End global iterations;  0.235348s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (132.8%)
+
+PHY-1001 : Congestion index: top1 = 66.03, top5 = 56.05, top10 = 50.69, top15 = 47.27.
+PHY-3001 : End congestion estimation;  0.491321s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (114.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85749, tnet num: 20354, tinst num: 17952, tnode num: 116398, tedge num: 137520.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.425550s wall, 1.359375s user + 0.078125s system = 1.437500s CPU (100.8%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 610 MB, peak memory is 712 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.353804s wall, 2.281250s user + 0.078125s system = 2.359375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(274): len = 647207, overlap = 0.4375
+PHY-3002 : Step(275): len = 646813, overlap = 0.4375
+PHY-3002 : Step(276): len = 646562, overlap = 0.4375
+PHY-3002 : Step(277): len = 646329, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16669/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738224, over cnt = 3040(8%), over = 11020, worst = 23
+PHY-1001 : End global iterations;  0.187018s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (150.4%)
+
+PHY-1001 : Congestion index: top1 = 66.44, top5 = 56.30, top10 = 50.96, top15 = 47.56.
+PHY-3001 : End congestion estimation;  0.437522s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (121.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.912237s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000327438
+PHY-3002 : Step(278): len = 646336, overlap = 91.7812
+PHY-3002 : Step(279): len = 646431, overlap = 91.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000654876
+PHY-3002 : Step(280): len = 646360, overlap = 90.7812
+PHY-3002 : Step(281): len = 646751, overlap = 91.4375
+PHY-3001 : Final: Len = 646751, Over = 91.4375
+PHY-3001 : End incremental placement;  4.820834s wall, 5.031250s user + 0.281250s system = 5.312500s CPU (110.2%)
+
+OPT-1001 : Total overflow 409.66 peak overflow 2.69
+OPT-1001 : End high-fanout net optimization;  7.711482s wall, 8.531250s user + 0.375000s system = 8.906250s CPU (115.5%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 710, peak = 732.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16602/20532.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740224, over cnt = 2991(8%), over = 9937, worst = 20
+PHY-1002 : len = 794184, over cnt = 2008(5%), over = 4860, worst = 18
+PHY-1002 : len = 828048, over cnt = 869(2%), over = 1996, worst = 17
+PHY-1002 : len = 852104, over cnt = 293(0%), over = 560, worst = 11
+PHY-1002 : len = 861664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.811430s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (136.3%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.28, top10 = 45.86, top15 = 43.68.
+OPT-1001 : End congestion update;  2.063954s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (131.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20354 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.797574s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1018 TNS -1565 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 96 cells processed and 6778 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 7 cells processed and 350 slack improved
+OPT-1001 : End global optimization;  2.909525s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (122.4%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 690, peak = 732.
+OPT-1001 : End physical optimization;  12.557493s wall, 14.109375s user + 0.406250s system = 14.515625s CPU (115.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7503 LUT to BLE ...
+SYN-4008 : Packed 7503 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6095 remaining SEQ's ...
+SYN-4005 : Packed 3693 SEQ with LUT/SLICE
+SYN-4006 : 969 single LUT's are left
+SYN-4006 : 2402 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9905/13636 primitive instances ...
+PHY-3001 : End packing;  1.584751s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6890 instances
+RUN-1001 : 3371 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17530 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5758 nets have [3 - 5] pins
+RUN-1001 : 1123 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6888 instances, 6742 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3560 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 657912, Over = 251
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7593/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 813888, over cnt = 1952(5%), over = 3148, worst = 7
+PHY-1002 : len = 821784, over cnt = 1230(3%), over = 1767, worst = 6
+PHY-1002 : len = 830520, over cnt = 722(2%), over = 1019, worst = 6
+PHY-1002 : len = 837008, over cnt = 475(1%), over = 681, worst = 6
+PHY-1002 : len = 845584, over cnt = 109(0%), over = 150, worst = 6
+PHY-1001 : End global iterations;  1.476445s wall, 2.000000s user + 0.031250s system = 2.031250s CPU (137.6%)
+
+PHY-1001 : Congestion index: top1 = 57.65, top5 = 50.04, top10 = 45.96, top15 = 43.38.
+PHY-3001 : End congestion estimation;  1.858186s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6888, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.603691s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (100.4%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 608 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.652369s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (94.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.75783e-05
+PHY-3002 : Step(282): len = 645888, overlap = 249.75
+PHY-3002 : Step(283): len = 639979, overlap = 245.5
+PHY-3002 : Step(284): len = 636462, overlap = 252.5
+PHY-3002 : Step(285): len = 633658, overlap = 252.5
+PHY-3002 : Step(286): len = 630887, overlap = 260.75
+PHY-3002 : Step(287): len = 627447, overlap = 264
+PHY-3002 : Step(288): len = 624149, overlap = 268
+PHY-3002 : Step(289): len = 621609, overlap = 270.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.51567e-05
+PHY-3002 : Step(290): len = 624770, overlap = 262
+PHY-3002 : Step(291): len = 629314, overlap = 250.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000190313
+PHY-3002 : Step(292): len = 633723, overlap = 244
+PHY-3002 : Step(293): len = 645927, overlap = 215.75
+PHY-3002 : Step(294): len = 648474, overlap = 213.5
+PHY-3002 : Step(295): len = 649771, overlap = 210.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.380418s wall, 0.328125s user + 0.656250s system = 0.984375s CPU (258.8%)
+
+PHY-3001 : Trial Legalized: Len = 725964
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 759/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840944, over cnt = 2673(7%), over = 4537, worst = 8
+PHY-1002 : len = 859824, over cnt = 1524(4%), over = 2187, worst = 7
+PHY-1002 : len = 878400, over cnt = 481(1%), over = 720, worst = 7
+PHY-1002 : len = 886200, over cnt = 114(0%), over = 174, worst = 7
+PHY-1002 : len = 888632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.333990s wall, 3.421875s user + 0.031250s system = 3.453125s CPU (147.9%)
+
+PHY-1001 : Congestion index: top1 = 53.23, top5 = 48.36, top10 = 45.74, top15 = 43.97.
+PHY-3001 : End congestion estimation;  2.776012s wall, 3.859375s user + 0.031250s system = 3.890625s CPU (140.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.841897s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160038
+PHY-3002 : Step(296): len = 699842, overlap = 38.5
+PHY-3002 : Step(297): len = 685178, overlap = 66.25
+PHY-3002 : Step(298): len = 673051, overlap = 91.75
+PHY-3002 : Step(299): len = 666043, overlap = 117.25
+PHY-3002 : Step(300): len = 661142, overlap = 139.5
+PHY-3002 : Step(301): len = 658978, overlap = 146.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320077
+PHY-3002 : Step(302): len = 665134, overlap = 141.75
+PHY-3002 : Step(303): len = 670968, overlap = 139.75
+PHY-3002 : Step(304): len = 671541, overlap = 147.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00063987
+PHY-3002 : Step(305): len = 676138, overlap = 148.5
+PHY-3002 : Step(306): len = 686491, overlap = 145
+PHY-3002 : Step(307): len = 691560, overlap = 146.25
+PHY-3002 : Step(308): len = 692892, overlap = 151.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.033135s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (94.3%)
+
+PHY-3001 : Legalized: Len = 721430, Over = 0
+PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.103375s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (90.7%)
+
+PHY-3001 : 612 instances has been re-located, deltaX = 269, deltaY = 342, maxDist = 3.
+PHY-3001 : Final: Len = 732202, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6891, tnode num: 96233, tedge num: 123821.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.849871s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (100.5%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 653 MB, peak memory is 732 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3456/17530.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859832, over cnt = 2564(7%), over = 4193, worst = 8
+PHY-1002 : len = 875568, over cnt = 1522(4%), over = 2156, worst = 6
+PHY-1002 : len = 887848, over cnt = 801(2%), over = 1128, worst = 6
+PHY-1002 : len = 899448, over cnt = 263(0%), over = 372, worst = 5
+PHY-1002 : len = 905456, over cnt = 12(0%), over = 15, worst = 2
+PHY-1001 : End global iterations;  1.843232s wall, 2.890625s user + 0.000000s system = 2.890625s CPU (156.8%)
+
+PHY-1001 : Congestion index: top1 = 53.38, top5 = 48.42, top10 = 45.65, top15 = 43.88.
+PHY-1001 : End incremental global routing;  2.196656s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (148.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17352 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.854563s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.7%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6798 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735387
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15975/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909520, over cnt = 90(0%), over = 105, worst = 5
+PHY-1002 : len = 909704, over cnt = 43(0%), over = 44, worst = 2
+PHY-1002 : len = 910104, over cnt = 19(0%), over = 19, worst = 1
+PHY-1002 : len = 910456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.592033s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 53.36, top5 = 48.44, top10 = 45.71, top15 = 43.96.
+PHY-3001 : End congestion estimation;  0.892876s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (103.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.851195s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (100.4%)
+
+RUN-1004 : used memory is 663 MB, reserved memory is 672 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.719248s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(309): len = 734474, overlap = 0
+PHY-3002 : Step(310): len = 734081, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15963/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 908160, over cnt = 75(0%), over = 95, worst = 4
+PHY-1002 : len = 908296, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 908824, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 908920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.569273s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (107.0%)
+
+PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.44, top10 = 45.71, top15 = 43.95.
+PHY-3001 : End congestion estimation;  0.867352s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (104.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.841037s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333503
+PHY-3002 : Step(311): len = 734109, overlap = 1.5
+PHY-3002 : Step(312): len = 734482, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005729s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 734542, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058254s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.5%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 734724, Over = 0
+PHY-3001 : End incremental placement;  5.812345s wall, 5.984375s user + 0.046875s system = 6.031250s CPU (103.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.338731s wall, 10.671875s user + 0.046875s system = 10.718750s CPU (114.8%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 743, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15926/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909344, over cnt = 69(0%), over = 91, worst = 7
+PHY-1002 : len = 909360, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 909488, over cnt = 18(0%), over = 18, worst = 1
+PHY-1002 : len = 909728, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 909752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.761173s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.37, top10 = 45.65, top15 = 43.90.
+OPT-1001 : End congestion update;  1.055668s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (103.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.705583s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.7%)
+
+OPT-0007 : Start: WNS -1040 TNS -1754 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 739128, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062410s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-3001 : 29 instances has been re-located, deltaX = 25, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 739360, Over = 0
+PHY-3001 : End incremental legalization;  0.375798s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.8%)
+
+OPT-0007 : Iter 1: improved WNS -990 TNS -1625 NUM_FEPS 2 with 35 cells processed and 11554 slack improved
+OPT-0007 : Iter 2: improved WNS -990 TNS -1625 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.272273s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (101.8%)
+
+OPT-1001 : Current memory(MB): used = 743, reserve = 743, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.729604s wall, 0.718750s user + 0.015625s system = 0.734375s CPU (100.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15842/17552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913768, over cnt = 81(0%), over = 92, worst = 4
+PHY-1002 : len = 913880, over cnt = 38(0%), over = 40, worst = 2
+PHY-1002 : len = 914048, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 914240, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 914256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.805782s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 53.56, top5 = 48.50, top10 = 45.71, top15 = 43.94.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.717327s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1040 TNS -1725 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.103448
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1040ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17552 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17552 nets
+OPT-1001 : End physical optimization;  16.375981s wall, 17.750000s user + 0.093750s system = 17.843750s CPU (109.0%)
+
+RUN-1003 : finish command "place" in  56.595156s wall, 83.140625s user + 6.187500s system = 89.328125s CPU (157.8%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 661 MB, peak memory is 746 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.701395s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (173.6%)
+
+RUN-1004 : used memory is 647 MB, reserved memory is 662 MB, peak memory is 746 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6915 instances
+RUN-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17552 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9969 nets have 2 pins
+RUN-1001 : 5757 nets have [3 - 5] pins
+RUN-1001 : 1125 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.578862s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.0%)
+
+RUN-1004 : used memory is 630 MB, reserved memory is 628 MB, peak memory is 746 MB
+PHY-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847752, over cnt = 2759(7%), over = 4572, worst = 8
+PHY-1002 : len = 866784, over cnt = 1589(4%), over = 2268, worst = 8
+PHY-1002 : len = 884376, over cnt = 660(1%), over = 927, worst = 6
+PHY-1002 : len = 898472, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 898536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.753856s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (143.5%)
+
+PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.37, top10 = 45.59, top15 = 43.67.
+PHY-1001 : End global routing;  3.073461s wall, 4.265625s user + 0.015625s system = 4.281250s CPU (139.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 713, reserve = 715, peak = 746.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 988, reserve = 989, peak = 988.
+PHY-1001 : End build detailed router design. 3.940248s wall, 3.906250s user + 0.031250s system = 3.937500s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.035934s wall, 5.015625s user + 0.015625s system = 5.031250s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.406754s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1023, reserve = 1025, peak = 1023.
+PHY-1001 : End phase 1; 5.455630s wall, 5.437500s user + 0.015625s system = 5.453125s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.31459e+06, over cnt = 1958(0%), over = 1962, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1038, peak = 1036.
+PHY-1001 : End initial routed; 21.559115s wall, 54.234375s user + 0.296875s system = 54.531250s CPU (252.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.084   |  -4.275   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.236856s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1048, reserve = 1050, peak = 1048.
+PHY-1001 : End phase 2; 24.796039s wall, 57.468750s user + 0.296875s system = 57.765625s CPU (233.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.149699s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.4%)
+
+PHY-1022 : len = 2.31459e+06, over cnt = 1960(0%), over = 1964, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.426196s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.28119e+06, over cnt = 722(0%), over = 722, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.226625s wall, 2.250000s user + 0.031250s system = 2.281250s CPU (186.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.27972e+06, over cnt = 191(0%), over = 191, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.579011s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (180.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.28086e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.430110s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (119.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.28087e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.229915s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (108.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.200370s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.283206s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.215832s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1151, reserve = 1157, peak = 1151.
+PHY-1001 : End phase 3; 8.995251s wall, 10.578125s user + 0.031250s system = 10.609375s CPU (117.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.142916s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.4%)
+
+PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.376061s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.945ns, -4.090ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16475(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.288739s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 589 feed throughs used by 429 nets
+PHY-1001 : End commit to database; 2.288548s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1166, peak = 1160.
+PHY-1001 : End phase 4; 5.978630s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.28094e+06
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1168, peak = 1162.
+PHY-1001 : End export database. 0.059791s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+
+PHY-1001 : End detail routing;  49.613583s wall, 83.828125s user + 0.375000s system = 84.203125s CPU (169.7%)
+
+RUN-1003 : finish command "route" in  55.312668s wall, 90.703125s user + 0.406250s system = 91.109375s CPU (164.7%)
+
+RUN-1004 : used memory is 1087 MB, reserved memory is 1089 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10273   out of  19600   52.41%
+#reg                     9368   out of  19600   47.80%
+#le                     12618
+  #lut only              3250   out of  12618   25.76%
+  #reg only              2345   out of  12618   18.58%
+  #lut&reg               7023   out of  12618   55.66%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1810
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1425
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1358
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               942
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    143
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_277.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/reg10_syn_122.f1                         3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12618  |9246    |1027    |9400    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |561    |454     |23      |449     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |110    |93      |4       |93      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |32     |32      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |9       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |781    |337     |96      |583     |0       |0       |
+|    u_ADconfig                |AD_config            |191    |118     |25      |142     |0       |0       |
+|    u_gen_sp                  |gen_sp               |269    |158     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |379     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |129     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |259    |144     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3071   |2501    |306     |2076    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |137     |17      |133     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2855   |2346    |289     |1907    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |1       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |9      |4       |0       |9       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2407   |1999    |253     |1544    |22      |0       |
+|        channelPart           |channel_part_8478    |143    |136     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |41      |0       |0       |
+|        ram_switch            |ram_switch           |1870   |1532    |197     |1149    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |247    |220     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |31     |28      |3       |17      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |965    |654     |170     |661     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |658    |658     |0       |365     |0       |0       |
+|        read_ram_i            |read_ram             |300    |255     |44      |195     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |240    |200     |40      |155     |0       |0       |
+|          read_ram_data       |read_ram_data        |56     |51      |4       |36      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |337    |245     |36      |283     |3       |0       |
+|        u0_soft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3397   |2743    |349     |2088    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |189    |127     |17      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |3178   |2597    |332     |1911    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2741   |2251    |290     |1561    |22      |1       |
+|        channelPart           |channel_part_8478    |243    |238     |3       |137     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |2023   |1671    |197     |1132    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |219    |192     |27      |98      |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |6       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |6       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|          insert              |insert               |982    |658     |170     |674     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |822    |821     |0       |360     |0       |0       |
+|        read_ram_i            |read_ram_rev         |378    |263     |81      |214     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |311    |226     |73      |165     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |67     |37      |8       |49      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9907  
+    #2         2       3801  
+    #3         3       1374  
+    #4         4       579   
+    #5        5-10     1189  
+    #6       11-50     584   
+    #7       51-100     22   
+    #8        >500      1    
+  Average     2.92           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.070151s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (171.3%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1090 MB, peak memory is 1162 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.573175s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.3%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1095 MB, peak memory is 1162 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.464521s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.2%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1097 MB, peak memory is 1162 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6913
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17552, pip num: 172527
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 589
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 479670 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.581590s wall, 64.562500s user + 0.218750s system = 64.781250s CPU (676.1%)
+
+RUN-1004 : used memory is 1261 MB, reserved memory is 1265 MB, peak memory is 1377 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_104647.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_105655.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_105655.log
new file mode 100644
index 0000000..7ea75db
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_105655.log
@@ -0,0 +1,382 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:56:55 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.151544s wall, 2.093750s user + 0.062500s system = 2.156250s CPU (100.2%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+USR-8086 ERROR: Failed to add cell sampling_fe_b/u_sort_rev/u_data_prebuffer_rev/ram_switch/insert to bound bound3: Please force keep hierarchy in source if necessary.
+PHY-9101 ERROR: Initial place errored out.
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_105655.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_105902.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_105902.log
new file mode 100644
index 0000000..3e437b0
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_105902.log
@@ -0,0 +1,1042 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:59:02 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.111511s wall, 2.046875s user + 0.062500s system = 2.109375s CPU (99.9%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.114354s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (99.6%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 513 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.893193s wall, 1.843750s user + 0.046875s system = 1.890625s CPU (99.9%)
+
+PHY-3001 : Found 3481 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.143551s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (141.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.27947e+06, overlap = 496.406
+PHY-3002 : Step(2): len = 1.17041e+06, overlap = 559.844
+PHY-3002 : Step(3): len = 844712, overlap = 618.219
+PHY-3002 : Step(4): len = 793165, overlap = 636.375
+PHY-3002 : Step(5): len = 615167, overlap = 766.062
+PHY-3002 : Step(6): len = 533758, overlap = 820.406
+PHY-3002 : Step(7): len = 453111, overlap = 920.719
+PHY-3002 : Step(8): len = 417245, overlap = 971.156
+PHY-3002 : Step(9): len = 369976, overlap = 1052.47
+PHY-3002 : Step(10): len = 336934, overlap = 1113.22
+PHY-3002 : Step(11): len = 298692, overlap = 1171.91
+PHY-3002 : Step(12): len = 273905, overlap = 1199.06
+PHY-3002 : Step(13): len = 244064, overlap = 1211.69
+PHY-3002 : Step(14): len = 219599, overlap = 1259.97
+PHY-3002 : Step(15): len = 200144, overlap = 1289.47
+PHY-3002 : Step(16): len = 183828, overlap = 1356.41
+PHY-3002 : Step(17): len = 172180, overlap = 1373.12
+PHY-3002 : Step(18): len = 159179, overlap = 1401.81
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.01494e-06
+PHY-3002 : Step(19): len = 160335, overlap = 1386.81
+PHY-3002 : Step(20): len = 188209, overlap = 1315.75
+PHY-3002 : Step(21): len = 190031, overlap = 1246.44
+PHY-3002 : Step(22): len = 193853, overlap = 1231.69
+PHY-3002 : Step(23): len = 193143, overlap = 1249.19
+PHY-3002 : Step(24): len = 192596, overlap = 1276.44
+PHY-3002 : Step(25): len = 190875, overlap = 1244.19
+PHY-3002 : Step(26): len = 189683, overlap = 1226.81
+PHY-3002 : Step(27): len = 187588, overlap = 1220.72
+PHY-3002 : Step(28): len = 184726, overlap = 1203
+PHY-3002 : Step(29): len = 183740, overlap = 1210.69
+PHY-3002 : Step(30): len = 182451, overlap = 1212.94
+PHY-3002 : Step(31): len = 182208, overlap = 1212.25
+PHY-3002 : Step(32): len = 180280, overlap = 1221.44
+PHY-3002 : Step(33): len = 181063, overlap = 1236.78
+PHY-3002 : Step(34): len = 180365, overlap = 1233.31
+PHY-3002 : Step(35): len = 179766, overlap = 1248.47
+PHY-3002 : Step(36): len = 178570, overlap = 1229.34
+PHY-3002 : Step(37): len = 179218, overlap = 1214.03
+PHY-3002 : Step(38): len = 179908, overlap = 1183.72
+PHY-3002 : Step(39): len = 179461, overlap = 1170.28
+PHY-3002 : Step(40): len = 178832, overlap = 1178
+PHY-3002 : Step(41): len = 177362, overlap = 1171.62
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.02988e-06
+PHY-3002 : Step(42): len = 181214, overlap = 1174.75
+PHY-3002 : Step(43): len = 192268, overlap = 1125.5
+PHY-3002 : Step(44): len = 196287, overlap = 1122.41
+PHY-3002 : Step(45): len = 201454, overlap = 1135.56
+PHY-3002 : Step(46): len = 204456, overlap = 1103.38
+PHY-3002 : Step(47): len = 206584, overlap = 1091.91
+PHY-3002 : Step(48): len = 204688, overlap = 1085.59
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.05976e-06
+PHY-3002 : Step(49): len = 212529, overlap = 1029.78
+PHY-3002 : Step(50): len = 229700, overlap = 979.312
+PHY-3002 : Step(51): len = 235380, overlap = 988.906
+PHY-3002 : Step(52): len = 240303, overlap = 990.094
+PHY-3002 : Step(53): len = 244068, overlap = 929.781
+PHY-3002 : Step(54): len = 245688, overlap = 905.844
+PHY-3002 : Step(55): len = 246402, overlap = 900.938
+PHY-3002 : Step(56): len = 246871, overlap = 907.438
+PHY-3002 : Step(57): len = 246890, overlap = 909.188
+PHY-3002 : Step(58): len = 244865, overlap = 915.094
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.11953e-06
+PHY-3002 : Step(59): len = 259806, overlap = 873.25
+PHY-3002 : Step(60): len = 276551, overlap = 821.344
+PHY-3002 : Step(61): len = 283240, overlap = 767.188
+PHY-3002 : Step(62): len = 285885, overlap = 732.031
+PHY-3002 : Step(63): len = 286177, overlap = 713.812
+PHY-3002 : Step(64): len = 286230, overlap = 690.531
+PHY-3002 : Step(65): len = 286092, overlap = 671.062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.62391e-05
+PHY-3002 : Step(66): len = 303726, overlap = 613.688
+PHY-3002 : Step(67): len = 322284, overlap = 537.688
+PHY-3002 : Step(68): len = 331855, overlap = 501.469
+PHY-3002 : Step(69): len = 338433, overlap = 477.719
+PHY-3002 : Step(70): len = 340697, overlap = 452.844
+PHY-3002 : Step(71): len = 341174, overlap = 430.406
+PHY-3002 : Step(72): len = 337150, overlap = 410.531
+PHY-3002 : Step(73): len = 338720, overlap = 408.062
+PHY-3002 : Step(74): len = 338271, overlap = 393.969
+PHY-3002 : Step(75): len = 338530, overlap = 389.531
+PHY-3002 : Step(76): len = 335964, overlap = 396.812
+PHY-3002 : Step(77): len = 335855, overlap = 400.312
+PHY-3002 : Step(78): len = 334352, overlap = 413.031
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.24781e-05
+PHY-3002 : Step(79): len = 355974, overlap = 360.188
+PHY-3002 : Step(80): len = 370032, overlap = 329.469
+PHY-3002 : Step(81): len = 368217, overlap = 348.281
+PHY-3002 : Step(82): len = 369016, overlap = 352.25
+PHY-3002 : Step(83): len = 369151, overlap = 338.594
+PHY-3002 : Step(84): len = 370110, overlap = 337.844
+PHY-3002 : Step(85): len = 367171, overlap = 342.469
+PHY-3002 : Step(86): len = 368326, overlap = 352.188
+PHY-3002 : Step(87): len = 371063, overlap = 343.406
+PHY-3002 : Step(88): len = 372816, overlap = 337
+PHY-3002 : Step(89): len = 370114, overlap = 319.938
+PHY-3002 : Step(90): len = 369791, overlap = 327.375
+PHY-3002 : Step(91): len = 370301, overlap = 323.844
+PHY-3002 : Step(92): len = 371561, overlap = 323.75
+PHY-3002 : Step(93): len = 369318, overlap = 325.25
+PHY-3002 : Step(94): len = 369657, overlap = 319.969
+PHY-3002 : Step(95): len = 369768, overlap = 331.469
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.49562e-05
+PHY-3002 : Step(96): len = 387516, overlap = 333.156
+PHY-3002 : Step(97): len = 398609, overlap = 324
+PHY-3002 : Step(98): len = 398129, overlap = 317.719
+PHY-3002 : Step(99): len = 399959, overlap = 320.375
+PHY-3002 : Step(100): len = 402528, overlap = 305.906
+PHY-3002 : Step(101): len = 405024, overlap = 298
+PHY-3002 : Step(102): len = 402593, overlap = 297.25
+PHY-3002 : Step(103): len = 404094, overlap = 298.375
+PHY-3002 : Step(104): len = 407632, overlap = 292.125
+PHY-3002 : Step(105): len = 410267, overlap = 281.844
+PHY-3002 : Step(106): len = 408030, overlap = 274.156
+PHY-3002 : Step(107): len = 409205, overlap = 268.812
+PHY-3002 : Step(108): len = 411580, overlap = 253.031
+PHY-3002 : Step(109): len = 411851, overlap = 252.375
+PHY-3002 : Step(110): len = 410278, overlap = 259.281
+PHY-3002 : Step(111): len = 410373, overlap = 253.75
+PHY-3002 : Step(112): len = 410699, overlap = 240.688
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000129912
+PHY-3002 : Step(113): len = 423461, overlap = 246.625
+PHY-3002 : Step(114): len = 432212, overlap = 237.125
+PHY-3002 : Step(115): len = 431898, overlap = 237.25
+PHY-3002 : Step(116): len = 432782, overlap = 239.656
+PHY-3002 : Step(117): len = 433462, overlap = 250.562
+PHY-3002 : Step(118): len = 435541, overlap = 238.75
+PHY-3002 : Step(119): len = 436488, overlap = 227.031
+PHY-3002 : Step(120): len = 438619, overlap = 226.844
+PHY-3002 : Step(121): len = 439879, overlap = 226.188
+PHY-3002 : Step(122): len = 440872, overlap = 224.656
+PHY-3002 : Step(123): len = 439394, overlap = 223.656
+PHY-3002 : Step(124): len = 439508, overlap = 218.406
+PHY-3002 : Step(125): len = 439650, overlap = 223.656
+PHY-3002 : Step(126): len = 440218, overlap = 222.781
+PHY-3002 : Step(127): len = 438467, overlap = 220.219
+PHY-3002 : Step(128): len = 438510, overlap = 220.719
+PHY-3002 : Step(129): len = 439267, overlap = 220.219
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00025933
+PHY-3002 : Step(130): len = 451489, overlap = 205.906
+PHY-3002 : Step(131): len = 457696, overlap = 205.312
+PHY-3002 : Step(132): len = 456559, overlap = 200.562
+PHY-3002 : Step(133): len = 456486, overlap = 205.094
+PHY-3002 : Step(134): len = 458894, overlap = 201.594
+PHY-3002 : Step(135): len = 460932, overlap = 198.656
+PHY-3002 : Step(136): len = 460359, overlap = 187.062
+PHY-3002 : Step(137): len = 460626, overlap = 185.469
+PHY-3002 : Step(138): len = 462133, overlap = 190.594
+PHY-3002 : Step(139): len = 464014, overlap = 186.438
+PHY-3002 : Step(140): len = 463211, overlap = 184.938
+PHY-3002 : Step(141): len = 463132, overlap = 185.438
+PHY-3002 : Step(142): len = 464158, overlap = 179.812
+PHY-3002 : Step(143): len = 465135, overlap = 181.875
+PHY-3002 : Step(144): len = 464280, overlap = 177.719
+PHY-3002 : Step(145): len = 464177, overlap = 176.094
+PHY-3002 : Step(146): len = 464473, overlap = 178.5
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00050829
+PHY-3002 : Step(147): len = 471587, overlap = 176.312
+PHY-3002 : Step(148): len = 478583, overlap = 177.219
+PHY-3002 : Step(149): len = 480222, overlap = 167.094
+PHY-3002 : Step(150): len = 482571, overlap = 169.938
+PHY-3002 : Step(151): len = 484980, overlap = 160.25
+PHY-3002 : Step(152): len = 487163, overlap = 158.75
+PHY-3002 : Step(153): len = 487657, overlap = 157.156
+PHY-3002 : Step(154): len = 488023, overlap = 153.906
+PHY-3002 : Step(155): len = 488417, overlap = 158
+PHY-3002 : Step(156): len = 488026, overlap = 155.312
+PHY-3002 : Step(157): len = 486892, overlap = 157.375
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000964848
+PHY-3002 : Step(158): len = 490616, overlap = 159.594
+PHY-3002 : Step(159): len = 494590, overlap = 165.188
+PHY-3002 : Step(160): len = 495348, overlap = 166.656
+PHY-3002 : Step(161): len = 496418, overlap = 165.781
+PHY-3002 : Step(162): len = 498202, overlap = 168.344
+PHY-3002 : Step(163): len = 499574, overlap = 166.5
+PHY-3002 : Step(164): len = 499726, overlap = 170.25
+PHY-3002 : Step(165): len = 500096, overlap = 168.406
+PHY-3002 : Step(166): len = 501106, overlap = 166.75
+PHY-3002 : Step(167): len = 501717, overlap = 169
+PHY-3002 : Step(168): len = 501329, overlap = 168.062
+PHY-3002 : Step(169): len = 501846, overlap = 166.812
+PHY-3002 : Step(170): len = 503006, overlap = 167.781
+PHY-3002 : Step(171): len = 503583, overlap = 163.062
+PHY-3002 : Step(172): len = 503337, overlap = 162.156
+PHY-3002 : Step(173): len = 503267, overlap = 164.656
+PHY-3002 : Step(174): len = 504341, overlap = 164.719
+PHY-3002 : Step(175): len = 505481, overlap = 167.688
+PHY-3002 : Step(176): len = 505033, overlap = 161.312
+PHY-3002 : Step(177): len = 504882, overlap = 158.875
+PHY-3002 : Step(178): len = 505238, overlap = 161.406
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00192582
+PHY-3002 : Step(179): len = 507219, overlap = 158.469
+PHY-3002 : Step(180): len = 511502, overlap = 158.938
+PHY-3002 : Step(181): len = 513030, overlap = 155.406
+PHY-3002 : Step(182): len = 514298, overlap = 153.062
+PHY-3002 : Step(183): len = 514698, overlap = 153.281
+PHY-3002 : Step(184): len = 514920, overlap = 155.625
+PHY-3002 : Step(185): len = 515195, overlap = 154.344
+PHY-3002 : Step(186): len = 515388, overlap = 152.281
+PHY-3002 : Step(187): len = 515371, overlap = 151.844
+PHY-3002 : Step(188): len = 515371, overlap = 151.844
+PHY-3002 : Step(189): len = 515322, overlap = 152.531
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00311597
+PHY-3002 : Step(190): len = 516555, overlap = 153.375
+PHY-3002 : Step(191): len = 520404, overlap = 144.062
+PHY-3002 : Step(192): len = 521454, overlap = 143.781
+PHY-3002 : Step(193): len = 522003, overlap = 136.594
+PHY-3002 : Step(194): len = 522580, overlap = 145.188
+PHY-3002 : Step(195): len = 523093, overlap = 141.375
+PHY-3002 : Step(196): len = 523629, overlap = 136
+PHY-3002 : Step(197): len = 524070, overlap = 134.25
+PHY-3002 : Step(198): len = 524410, overlap = 132.875
+PHY-3002 : Step(199): len = 524976, overlap = 132.562
+PHY-3002 : Step(200): len = 525507, overlap = 137
+PHY-3002 : Step(201): len = 525907, overlap = 137.719
+PHY-3002 : Step(202): len = 525985, overlap = 136.438
+PHY-3002 : Step(203): len = 525974, overlap = 135.75
+PHY-3002 : Step(204): len = 525848, overlap = 137.5
+PHY-3001 : :::14::: Try harder cell spreading with beta_ = 0.0054418
+PHY-3002 : Step(205): len = 526734, overlap = 136.438
+PHY-3002 : Step(206): len = 528056, overlap = 137.281
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.018113s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (258.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 670640, over cnt = 1553(4%), over = 7022, worst = 29
+PHY-1001 : End global iterations;  0.674778s wall, 1.046875s user + 0.046875s system = 1.093750s CPU (162.1%)
+
+PHY-1001 : Congestion index: top1 = 76.83, top5 = 59.39, top10 = 50.57, top15 = 45.25.
+PHY-3001 : End congestion estimation;  0.893973s wall, 1.281250s user + 0.046875s system = 1.328125s CPU (148.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.836937s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.01736e-05
+PHY-3002 : Step(207): len = 610266, overlap = 77.1562
+PHY-3002 : Step(208): len = 621489, overlap = 79.1562
+PHY-3002 : Step(209): len = 623138, overlap = 76.9375
+PHY-3002 : Step(210): len = 622781, overlap = 71
+PHY-3002 : Step(211): len = 631139, overlap = 74.4062
+PHY-3002 : Step(212): len = 646058, overlap = 62.1562
+PHY-3002 : Step(213): len = 654221, overlap = 70.8125
+PHY-3002 : Step(214): len = 661925, overlap = 78.7812
+PHY-3002 : Step(215): len = 666680, overlap = 70.1875
+PHY-3002 : Step(216): len = 672898, overlap = 66.4375
+PHY-3002 : Step(217): len = 678180, overlap = 55.125
+PHY-3002 : Step(218): len = 684742, overlap = 61.0312
+PHY-3002 : Step(219): len = 687626, overlap = 49.8125
+PHY-3002 : Step(220): len = 690059, overlap = 48.4688
+PHY-3002 : Step(221): len = 690366, overlap = 56.8438
+PHY-3002 : Step(222): len = 692765, overlap = 58.8438
+PHY-3002 : Step(223): len = 692026, overlap = 60.4062
+PHY-3002 : Step(224): len = 692450, overlap = 58.6875
+PHY-3002 : Step(225): len = 691925, overlap = 56.5
+PHY-3002 : Step(226): len = 690634, overlap = 57.3438
+PHY-3002 : Step(227): len = 689548, overlap = 60.0625
+PHY-3002 : Step(228): len = 688198, overlap = 63.875
+PHY-3002 : Step(229): len = 687511, overlap = 68
+PHY-3002 : Step(230): len = 686860, overlap = 69.75
+PHY-3002 : Step(231): len = 686333, overlap = 74.6562
+PHY-3002 : Step(232): len = 683938, overlap = 79.4375
+PHY-3002 : Step(233): len = 682189, overlap = 82.3438
+PHY-3002 : Step(234): len = 678987, overlap = 81.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000160347
+PHY-3002 : Step(235): len = 680859, overlap = 80.5312
+PHY-3002 : Step(236): len = 683332, overlap = 77.2812
+PHY-3002 : Step(237): len = 687334, overlap = 75.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000318663
+PHY-3002 : Step(238): len = 693149, overlap = 70.8125
+PHY-3002 : Step(239): len = 706039, overlap = 57.9375
+PHY-3002 : Step(240): len = 716655, overlap = 48.1875
+PHY-3002 : Step(241): len = 717978, overlap = 41.7812
+PHY-3002 : Step(242): len = 718546, overlap = 35.7188
+PHY-3002 : Step(243): len = 716457, overlap = 32.375
+PHY-3002 : Step(244): len = 715876, overlap = 29.6562
+PHY-3002 : Step(245): len = 715224, overlap = 27.6562
+PHY-3002 : Step(246): len = 716016, overlap = 26.4062
+PHY-3002 : Step(247): len = 715748, overlap = 23.4062
+PHY-3002 : Step(248): len = 717454, overlap = 25.7812
+PHY-3002 : Step(249): len = 718095, overlap = 26.4062
+PHY-3002 : Step(250): len = 718784, overlap = 29.8125
+PHY-3002 : Step(251): len = 719785, overlap = 33.4062
+PHY-3002 : Step(252): len = 719727, overlap = 31.625
+PHY-3002 : Step(253): len = 720907, overlap = 33.2188
+PHY-3002 : Step(254): len = 723399, overlap = 39.1875
+PHY-3002 : Step(255): len = 724268, overlap = 41.0312
+PHY-3002 : Step(256): len = 725227, overlap = 38.0312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000637325
+PHY-3002 : Step(257): len = 728114, overlap = 37.375
+PHY-3002 : Step(258): len = 733302, overlap = 34.5938
+PHY-3002 : Step(259): len = 738481, overlap = 30.6562
+PHY-3002 : Step(260): len = 744335, overlap = 25.9688
+PHY-3002 : Step(261): len = 748246, overlap = 27.6562
+PHY-3002 : Step(262): len = 751871, overlap = 29.2812
+PHY-3002 : Step(263): len = 751727, overlap = 29.75
+PHY-3002 : Step(264): len = 751859, overlap = 32.25
+PHY-3002 : Step(265): len = 751113, overlap = 30.3125
+PHY-3002 : Step(266): len = 750415, overlap = 29.9375
+PHY-3002 : Step(267): len = 751361, overlap = 29
+PHY-3002 : Step(268): len = 751403, overlap = 28.4375
+PHY-3002 : Step(269): len = 751324, overlap = 31.5938
+PHY-3002 : Step(270): len = 750374, overlap = 30.375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00127465
+PHY-3002 : Step(271): len = 752096, overlap = 28.4375
+PHY-3002 : Step(272): len = 754907, overlap = 28.0312
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 833224, over cnt = 2754(7%), over = 13958, worst = 73
+PHY-1001 : End global iterations;  1.308611s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (149.3%)
+
+PHY-1001 : Congestion index: top1 = 110.86, top5 = 77.87, top10 = 65.60, top15 = 58.58.
+PHY-3001 : End congestion estimation;  1.588614s wall, 2.203125s user + 0.015625s system = 2.218750s CPU (139.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.861679s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (101.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000112951
+PHY-3002 : Step(273): len = 753095, overlap = 245.969
+PHY-3002 : Step(274): len = 756187, overlap = 206.75
+PHY-3002 : Step(275): len = 748379, overlap = 186.844
+PHY-3002 : Step(276): len = 746912, overlap = 167.5
+PHY-3002 : Step(277): len = 741227, overlap = 154.531
+PHY-3002 : Step(278): len = 737608, overlap = 153.094
+PHY-3002 : Step(279): len = 733703, overlap = 150.594
+PHY-3002 : Step(280): len = 728813, overlap = 142.281
+PHY-3002 : Step(281): len = 724541, overlap = 139.656
+PHY-3002 : Step(282): len = 720756, overlap = 132.562
+PHY-3002 : Step(283): len = 717196, overlap = 139.594
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000225901
+PHY-3002 : Step(284): len = 719518, overlap = 130.656
+PHY-3002 : Step(285): len = 720887, overlap = 132.562
+PHY-3002 : Step(286): len = 721033, overlap = 125.188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000442623
+PHY-3002 : Step(287): len = 726638, overlap = 117.844
+PHY-3002 : Step(288): len = 733555, overlap = 111.094
+PHY-3002 : Step(289): len = 736379, overlap = 100.219
+PHY-3002 : Step(290): len = 735229, overlap = 100.281
+PHY-3002 : Step(291): len = 735312, overlap = 99.5938
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.398718s wall, 1.343750s user + 0.046875s system = 1.390625s CPU (99.4%)
+
+RUN-1004 : used memory is 573 MB, reserved memory is 562 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 450.78 peak overflow 3.91
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 948/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826056, over cnt = 3150(8%), over = 12444, worst = 44
+PHY-1001 : End global iterations;  1.149629s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (142.7%)
+
+PHY-1001 : Congestion index: top1 = 85.19, top5 = 64.29, top10 = 56.30, top15 = 51.92.
+PHY-1001 : End incremental global routing;  1.456891s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (134.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.882695s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (99.1%)
+
+OPT-1001 : 54 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17532 has valid locations, 350 needs to be replaced
+PHY-3001 : design contains 17967 instances, 7512 luts, 9234 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6024 pins
+PHY-3001 : Found 3518 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 757985
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16664/20547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843808, over cnt = 3184(9%), over = 12571, worst = 44
+PHY-1001 : End global iterations;  0.239695s wall, 0.281250s user + 0.046875s system = 0.328125s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 84.98, top5 = 64.58, top10 = 56.65, top15 = 52.29.
+PHY-3001 : End congestion estimation;  0.495094s wall, 0.531250s user + 0.046875s system = 0.578125s CPU (116.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85813, tnet num: 20369, tinst num: 17967, tnode num: 116493, tedge num: 137618.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.412299s wall, 1.375000s user + 0.031250s system = 1.406250s CPU (99.6%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 611 MB, peak memory is 714 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.335017s wall, 2.265625s user + 0.062500s system = 2.328125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(292): len = 756636, overlap = 4.09375
+PHY-3002 : Step(293): len = 756195, overlap = 4.09375
+PHY-3002 : Step(294): len = 755772, overlap = 4.59375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000132649
+PHY-3002 : Step(295): len = 755611, overlap = 4.65625
+PHY-3002 : Step(296): len = 755953, overlap = 4.46875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000265299
+PHY-3002 : Step(297): len = 756132, overlap = 4.09375
+PHY-3002 : Step(298): len = 757737, overlap = 4.28125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16692/20547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842592, over cnt = 3203(9%), over = 12670, worst = 44
+PHY-1001 : End global iterations;  0.215049s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (145.3%)
+
+PHY-1001 : Congestion index: top1 = 85.47, top5 = 64.83, top10 = 56.83, top15 = 52.43.
+PHY-3001 : End congestion estimation;  0.460413s wall, 0.546875s user + 0.015625s system = 0.562500s CPU (122.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.899590s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000684824
+PHY-3002 : Step(299): len = 757561, overlap = 102.812
+PHY-3002 : Step(300): len = 757684, overlap = 102.312
+PHY-3001 : Final: Len = 757684, Over = 102.312
+PHY-3001 : End incremental placement;  4.911723s wall, 5.218750s user + 0.265625s system = 5.484375s CPU (111.7%)
+
+OPT-1001 : Total overflow 456.28 peak overflow 3.91
+OPT-1001 : End high-fanout net optimization;  7.768474s wall, 8.640625s user + 0.296875s system = 8.937500s CPU (115.0%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 710, peak = 733.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16843/20547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844504, over cnt = 3182(9%), over = 12051, worst = 44
+PHY-1002 : len = 906896, over cnt = 2321(6%), over = 6459, worst = 41
+PHY-1002 : len = 945608, over cnt = 1156(3%), over = 2968, worst = 24
+PHY-1002 : len = 982856, over cnt = 150(0%), over = 326, worst = 12
+PHY-1002 : len = 987576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.023961s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (138.2%)
+
+PHY-1001 : Congestion index: top1 = 63.43, top5 = 56.11, top10 = 51.76, top15 = 49.03.
+OPT-1001 : End congestion update;  2.285798s wall, 3.046875s user + 0.000000s system = 3.046875s CPU (133.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.779682s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 68 cells processed and 6057 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 29 cells processed and 2650 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 7 cells processed and 650 slack improved
+OPT-1001 : End global optimization;  3.107704s wall, 3.875000s user + 0.000000s system = 3.875000s CPU (124.7%)
+
+OPT-1001 : Current memory(MB): used = 693, reserve = 689, peak = 733.
+OPT-1001 : End physical optimization;  12.884054s wall, 14.578125s user + 0.343750s system = 14.921875s CPU (115.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7512 LUT to BLE ...
+SYN-4008 : Packed 7512 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6101 remaining SEQ's ...
+SYN-4005 : Packed 3839 SEQ with LUT/SLICE
+SYN-4006 : 844 single LUT's are left
+SYN-4006 : 2262 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9774/13505 primitive instances ...
+PHY-3001 : End packing;  1.551958s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6710 instances
+RUN-1001 : 3281 mslices, 3281 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17545 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9981 nets have 2 pins
+RUN-1001 : 5765 nets have [3 - 5] pins
+RUN-1001 : 1105 nets have [6 - 10] pins
+RUN-1001 : 317 nets have [11 - 20] pins
+RUN-1001 : 346 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6708 instances, 6562 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3496 pins
+PHY-3001 : Found 1537 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 765223, Over = 255
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[56] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7518/17545.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 923528, over cnt = 1952(5%), over = 3225, worst = 10
+PHY-1002 : len = 930664, over cnt = 1265(3%), over = 1874, worst = 8
+PHY-1002 : len = 944440, over cnt = 516(1%), over = 713, worst = 6
+PHY-1002 : len = 952968, over cnt = 116(0%), over = 154, worst = 4
+PHY-1002 : len = 955272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.582669s wall, 2.218750s user + 0.031250s system = 2.250000s CPU (142.2%)
+
+PHY-1001 : Congestion index: top1 = 62.44, top5 = 54.66, top10 = 50.12, top15 = 47.41.
+PHY-3001 : End congestion estimation;  1.963774s wall, 2.593750s user + 0.031250s system = 2.625000s CPU (133.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73362, tnet num: 17367, tinst num: 6708, tnode num: 95605, tedge num: 123152.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.581654s wall, 1.546875s user + 0.031250s system = 1.578125s CPU (99.8%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 611 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17367 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.434595s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.57196e-05
+PHY-3002 : Step(301): len = 752907, overlap = 252.5
+PHY-3002 : Step(302): len = 746278, overlap = 255.75
+PHY-3002 : Step(303): len = 740933, overlap = 261.25
+PHY-3002 : Step(304): len = 736535, overlap = 262
+PHY-3002 : Step(305): len = 732510, overlap = 279
+PHY-3002 : Step(306): len = 728948, overlap = 288.5
+PHY-3002 : Step(307): len = 724749, overlap = 298.25
+PHY-3002 : Step(308): len = 721410, overlap = 300
+PHY-3002 : Step(309): len = 718558, overlap = 306
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.14392e-05
+PHY-3002 : Step(310): len = 721527, overlap = 297.25
+PHY-3002 : Step(311): len = 726528, overlap = 286.25
+PHY-3002 : Step(312): len = 727205, overlap = 287.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000182878
+PHY-3002 : Step(313): len = 738228, overlap = 272
+PHY-3002 : Step(314): len = 743586, overlap = 258.75
+PHY-3002 : Step(315): len = 741908, overlap = 260.5
+PHY-3001 : Legalization ...
+PHY-9048 ERROR: Legalize hard bound bound3 failed due to insufficient space.
+PHY-9042 ERROR: Legalize MSLICE failed.
+RUN-1003 : finish command "place" in  38.195735s wall, 70.281250s user + 5.437500s system = 75.718750s CPU (198.2%)
+
+RUN-1004 : used memory is 544 MB, reserved memory is 531 MB, peak memory is 733 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_105902.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_110122.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_110122.log
new file mode 100644
index 0000000..2843a94
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_110122.log
@@ -0,0 +1,1028 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 11:01:22 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.124626s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (100.0%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.123679s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.1%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 513 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.917587s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (100.2%)
+
+PHY-3001 : Found 3481 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.140013s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.2801e+06, overlap = 496.562
+PHY-3002 : Step(2): len = 1.17137e+06, overlap = 568.469
+PHY-3002 : Step(3): len = 844870, overlap = 622.406
+PHY-3002 : Step(4): len = 793219, overlap = 647
+PHY-3002 : Step(5): len = 615280, overlap = 783.062
+PHY-3002 : Step(6): len = 534746, overlap = 830.75
+PHY-3002 : Step(7): len = 454280, overlap = 929.344
+PHY-3002 : Step(8): len = 418190, overlap = 970.438
+PHY-3002 : Step(9): len = 370919, overlap = 1055.62
+PHY-3002 : Step(10): len = 337494, overlap = 1117.03
+PHY-3002 : Step(11): len = 299511, overlap = 1182.88
+PHY-3002 : Step(12): len = 275970, overlap = 1211.66
+PHY-3002 : Step(13): len = 244659, overlap = 1228.72
+PHY-3002 : Step(14): len = 219696, overlap = 1280.12
+PHY-3002 : Step(15): len = 200016, overlap = 1292.31
+PHY-3002 : Step(16): len = 185082, overlap = 1337.62
+PHY-3002 : Step(17): len = 174037, overlap = 1364.19
+PHY-3002 : Step(18): len = 160012, overlap = 1405.41
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.03256e-06
+PHY-3002 : Step(19): len = 161459, overlap = 1386.84
+PHY-3002 : Step(20): len = 187849, overlap = 1340.03
+PHY-3002 : Step(21): len = 191345, overlap = 1270.31
+PHY-3002 : Step(22): len = 195501, overlap = 1235.06
+PHY-3002 : Step(23): len = 196086, overlap = 1220.72
+PHY-3002 : Step(24): len = 196302, overlap = 1223.5
+PHY-3002 : Step(25): len = 191802, overlap = 1222.59
+PHY-3002 : Step(26): len = 189862, overlap = 1214.41
+PHY-3002 : Step(27): len = 186956, overlap = 1192.94
+PHY-3002 : Step(28): len = 186146, overlap = 1190.19
+PHY-3002 : Step(29): len = 182884, overlap = 1187.03
+PHY-3002 : Step(30): len = 181755, overlap = 1184.53
+PHY-3002 : Step(31): len = 179944, overlap = 1211.72
+PHY-3002 : Step(32): len = 180095, overlap = 1202.19
+PHY-3002 : Step(33): len = 178435, overlap = 1186.22
+PHY-3002 : Step(34): len = 177971, overlap = 1190.03
+PHY-3002 : Step(35): len = 177797, overlap = 1187
+PHY-3002 : Step(36): len = 178592, overlap = 1195.12
+PHY-3002 : Step(37): len = 178136, overlap = 1166.38
+PHY-3002 : Step(38): len = 178605, overlap = 1139.25
+PHY-3002 : Step(39): len = 177233, overlap = 1133.59
+PHY-3002 : Step(40): len = 175701, overlap = 1133.78
+PHY-3002 : Step(41): len = 174998, overlap = 1139.16
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.06511e-06
+PHY-3002 : Step(42): len = 179511, overlap = 1123.34
+PHY-3002 : Step(43): len = 192992, overlap = 1126.47
+PHY-3002 : Step(44): len = 197264, overlap = 1085.94
+PHY-3002 : Step(45): len = 201710, overlap = 1076.09
+PHY-3002 : Step(46): len = 203216, overlap = 1075.41
+PHY-3002 : Step(47): len = 204842, overlap = 1056.38
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.13023e-06
+PHY-3002 : Step(48): len = 213794, overlap = 1023.66
+PHY-3002 : Step(49): len = 235348, overlap = 939.594
+PHY-3002 : Step(50): len = 246649, overlap = 913.719
+PHY-3002 : Step(51): len = 252666, overlap = 891.812
+PHY-3002 : Step(52): len = 253172, overlap = 878.844
+PHY-3002 : Step(53): len = 252638, overlap = 873.438
+PHY-3002 : Step(54): len = 251528, overlap = 887.156
+PHY-3002 : Step(55): len = 249714, overlap = 902.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.26045e-06
+PHY-3002 : Step(56): len = 266330, overlap = 837.188
+PHY-3002 : Step(57): len = 287956, overlap = 737.438
+PHY-3002 : Step(58): len = 295570, overlap = 706.75
+PHY-3002 : Step(59): len = 299566, overlap = 694.594
+PHY-3002 : Step(60): len = 299395, overlap = 685.906
+PHY-3002 : Step(61): len = 299211, overlap = 676.219
+PHY-3002 : Step(62): len = 297613, overlap = 669.656
+PHY-3002 : Step(63): len = 296116, overlap = 661.594
+PHY-3002 : Step(64): len = 295963, overlap = 660.312
+PHY-3002 : Step(65): len = 294306, overlap = 652.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.65209e-05
+PHY-3002 : Step(66): len = 311947, overlap = 595.219
+PHY-3002 : Step(67): len = 333483, overlap = 484.344
+PHY-3002 : Step(68): len = 343632, overlap = 469.5
+PHY-3002 : Step(69): len = 347111, overlap = 473.406
+PHY-3002 : Step(70): len = 344839, overlap = 490.938
+PHY-3002 : Step(71): len = 342687, overlap = 487
+PHY-3002 : Step(72): len = 340746, overlap = 492.344
+PHY-3002 : Step(73): len = 339469, overlap = 504.188
+PHY-3002 : Step(74): len = 338121, overlap = 501.625
+PHY-3002 : Step(75): len = 336660, overlap = 479.969
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.30418e-05
+PHY-3002 : Step(76): len = 356722, overlap = 438.562
+PHY-3002 : Step(77): len = 371980, overlap = 398.531
+PHY-3002 : Step(78): len = 374924, overlap = 381.688
+PHY-3002 : Step(79): len = 376428, overlap = 378.062
+PHY-3002 : Step(80): len = 379373, overlap = 386.188
+PHY-3002 : Step(81): len = 381874, overlap = 370.375
+PHY-3002 : Step(82): len = 379903, overlap = 361.719
+PHY-3002 : Step(83): len = 380210, overlap = 353.094
+PHY-3002 : Step(84): len = 379626, overlap = 343.844
+PHY-3002 : Step(85): len = 378869, overlap = 323.125
+PHY-3002 : Step(86): len = 377514, overlap = 329.438
+PHY-3002 : Step(87): len = 378362, overlap = 326.312
+PHY-3002 : Step(88): len = 378216, overlap = 339.25
+PHY-3002 : Step(89): len = 378022, overlap = 334.062
+PHY-3002 : Step(90): len = 376603, overlap = 350.25
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.60836e-05
+PHY-3002 : Step(91): len = 397769, overlap = 320.688
+PHY-3002 : Step(92): len = 410587, overlap = 310.5
+PHY-3002 : Step(93): len = 407809, overlap = 321.281
+PHY-3002 : Step(94): len = 407982, overlap = 330.625
+PHY-3002 : Step(95): len = 410671, overlap = 323.656
+PHY-3002 : Step(96): len = 413574, overlap = 319.219
+PHY-3002 : Step(97): len = 412766, overlap = 309.875
+PHY-3002 : Step(98): len = 414390, overlap = 304.906
+PHY-3002 : Step(99): len = 416878, overlap = 275.312
+PHY-3002 : Step(100): len = 418836, overlap = 262.688
+PHY-3002 : Step(101): len = 417285, overlap = 264.844
+PHY-3002 : Step(102): len = 418273, overlap = 258.438
+PHY-3002 : Step(103): len = 417854, overlap = 250.062
+PHY-3002 : Step(104): len = 417630, overlap = 239.031
+PHY-3002 : Step(105): len = 415636, overlap = 237.219
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000131579
+PHY-3002 : Step(106): len = 429705, overlap = 217.281
+PHY-3002 : Step(107): len = 438846, overlap = 199.094
+PHY-3002 : Step(108): len = 438536, overlap = 200.094
+PHY-3002 : Step(109): len = 439803, overlap = 208.625
+PHY-3002 : Step(110): len = 442340, overlap = 210.688
+PHY-3002 : Step(111): len = 444950, overlap = 197.25
+PHY-3002 : Step(112): len = 444173, overlap = 199.5
+PHY-3002 : Step(113): len = 444848, overlap = 198.781
+PHY-3002 : Step(114): len = 447528, overlap = 194.75
+PHY-3002 : Step(115): len = 449350, overlap = 194.656
+PHY-3002 : Step(116): len = 446945, overlap = 211.125
+PHY-3002 : Step(117): len = 445837, overlap = 215.938
+PHY-3002 : Step(118): len = 446580, overlap = 207.781
+PHY-3002 : Step(119): len = 447310, overlap = 212.812
+PHY-3002 : Step(120): len = 445838, overlap = 207.562
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000251292
+PHY-3002 : Step(121): len = 455074, overlap = 193.938
+PHY-3002 : Step(122): len = 461349, overlap = 182.969
+PHY-3002 : Step(123): len = 461067, overlap = 179.031
+PHY-3002 : Step(124): len = 461817, overlap = 175.969
+PHY-3002 : Step(125): len = 464750, overlap = 169
+PHY-3002 : Step(126): len = 467613, overlap = 165.438
+PHY-3002 : Step(127): len = 466271, overlap = 169.719
+PHY-3002 : Step(128): len = 466658, overlap = 170.25
+PHY-3002 : Step(129): len = 470064, overlap = 154.188
+PHY-3002 : Step(130): len = 473526, overlap = 143.156
+PHY-3002 : Step(131): len = 472072, overlap = 152.188
+PHY-3002 : Step(132): len = 472048, overlap = 154.656
+PHY-3002 : Step(133): len = 473744, overlap = 155.062
+PHY-3002 : Step(134): len = 474575, overlap = 153.562
+PHY-3002 : Step(135): len = 472839, overlap = 156.031
+PHY-3002 : Step(136): len = 472474, overlap = 158.375
+PHY-3002 : Step(137): len = 473703, overlap = 153.875
+PHY-3002 : Step(138): len = 474287, overlap = 151.219
+PHY-3002 : Step(139): len = 473210, overlap = 156.125
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000480125
+PHY-3002 : Step(140): len = 479302, overlap = 164.688
+PHY-3002 : Step(141): len = 484897, overlap = 163.062
+PHY-3002 : Step(142): len = 485814, overlap = 160.469
+PHY-3002 : Step(143): len = 487212, overlap = 156.156
+PHY-3002 : Step(144): len = 489419, overlap = 152.469
+PHY-3002 : Step(145): len = 490885, overlap = 152.531
+PHY-3002 : Step(146): len = 490289, overlap = 154.094
+PHY-3002 : Step(147): len = 490536, overlap = 151.938
+PHY-3002 : Step(148): len = 491744, overlap = 151.125
+PHY-3002 : Step(149): len = 492865, overlap = 147.344
+PHY-3002 : Step(150): len = 492373, overlap = 140.406
+PHY-3002 : Step(151): len = 492715, overlap = 138.594
+PHY-3002 : Step(152): len = 493301, overlap = 129.469
+PHY-3002 : Step(153): len = 493760, overlap = 129.281
+PHY-3002 : Step(154): len = 493134, overlap = 134.938
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000888934
+PHY-3002 : Step(155): len = 497766, overlap = 133.625
+PHY-3002 : Step(156): len = 504179, overlap = 134.938
+PHY-3002 : Step(157): len = 504541, overlap = 124.875
+PHY-3002 : Step(158): len = 504942, overlap = 124.094
+PHY-3002 : Step(159): len = 506358, overlap = 127.156
+PHY-3002 : Step(160): len = 507239, overlap = 130.781
+PHY-3002 : Step(161): len = 506728, overlap = 131.875
+PHY-3002 : Step(162): len = 506706, overlap = 136.844
+PHY-3002 : Step(163): len = 508014, overlap = 143.688
+PHY-3002 : Step(164): len = 509013, overlap = 141.812
+PHY-3002 : Step(165): len = 508372, overlap = 139.25
+PHY-3002 : Step(166): len = 508208, overlap = 140.281
+PHY-3002 : Step(167): len = 508615, overlap = 134.688
+PHY-3002 : Step(168): len = 509101, overlap = 135.344
+PHY-3002 : Step(169): len = 508887, overlap = 130.75
+PHY-3002 : Step(170): len = 509209, overlap = 131.375
+PHY-3002 : Step(171): len = 509884, overlap = 133.562
+PHY-3002 : Step(172): len = 510179, overlap = 135.562
+PHY-3002 : Step(173): len = 509461, overlap = 134.312
+PHY-3002 : Step(174): len = 509056, overlap = 137.344
+PHY-3002 : Step(175): len = 509316, overlap = 140.625
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0017244
+PHY-3002 : Step(176): len = 512084, overlap = 137.844
+PHY-3002 : Step(177): len = 515894, overlap = 135.312
+PHY-3002 : Step(178): len = 516647, overlap = 133.594
+PHY-3002 : Step(179): len = 517490, overlap = 125.406
+PHY-3002 : Step(180): len = 518955, overlap = 122.875
+PHY-3002 : Step(181): len = 519726, overlap = 119
+PHY-3002 : Step(182): len = 519416, overlap = 119.438
+PHY-3002 : Step(183): len = 519950, overlap = 116.781
+PHY-3002 : Step(184): len = 521295, overlap = 114.594
+PHY-3002 : Step(185): len = 521920, overlap = 121.719
+PHY-3002 : Step(186): len = 521053, overlap = 120.25
+PHY-3002 : Step(187): len = 520760, overlap = 120.844
+PHY-3002 : Step(188): len = 521399, overlap = 121.844
+PHY-3002 : Step(189): len = 521629, overlap = 117.719
+PHY-3002 : Step(190): len = 520962, overlap = 115.75
+PHY-3002 : Step(191): len = 520855, overlap = 115.875
+PHY-3002 : Step(192): len = 521509, overlap = 113.469
+PHY-3002 : Step(193): len = 521942, overlap = 111.281
+PHY-3002 : Step(194): len = 521429, overlap = 113.844
+PHY-3002 : Step(195): len = 521320, overlap = 115.719
+PHY-3002 : Step(196): len = 521925, overlap = 115.188
+PHY-3002 : Step(197): len = 523048, overlap = 115.906
+PHY-3002 : Step(198): len = 523015, overlap = 107.562
+PHY-3002 : Step(199): len = 523461, overlap = 111.375
+PHY-3002 : Step(200): len = 524443, overlap = 110.312
+PHY-3002 : Step(201): len = 524622, overlap = 109.656
+PHY-3002 : Step(202): len = 523708, overlap = 105.531
+PHY-3002 : Step(203): len = 523268, overlap = 105.156
+PHY-3002 : Step(204): len = 523450, overlap = 107.406
+PHY-3002 : Step(205): len = 523463, overlap = 108.812
+PHY-3002 : Step(206): len = 522904, overlap = 111.719
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016069s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (291.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 659328, over cnt = 1505(4%), over = 7233, worst = 43
+PHY-1001 : End global iterations;  0.674790s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (138.9%)
+
+PHY-1001 : Congestion index: top1 = 80.39, top5 = 60.85, top10 = 51.72, top15 = 46.20.
+PHY-3001 : End congestion estimation;  0.899894s wall, 1.140625s user + 0.031250s system = 1.171875s CPU (130.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.838878s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.30043e-05
+PHY-3002 : Step(207): len = 598073, overlap = 75.6562
+PHY-3002 : Step(208): len = 606524, overlap = 81.5
+PHY-3002 : Step(209): len = 608062, overlap = 82.6562
+PHY-3002 : Step(210): len = 612808, overlap = 93.25
+PHY-3002 : Step(211): len = 618111, overlap = 92.7812
+PHY-3002 : Step(212): len = 632050, overlap = 94.0312
+PHY-3002 : Step(213): len = 636188, overlap = 91.0938
+PHY-3002 : Step(214): len = 642110, overlap = 89.5938
+PHY-3002 : Step(215): len = 650514, overlap = 81.4062
+PHY-3002 : Step(216): len = 665132, overlap = 77.25
+PHY-3002 : Step(217): len = 667429, overlap = 67.75
+PHY-3002 : Step(218): len = 668163, overlap = 55.75
+PHY-3002 : Step(219): len = 670751, overlap = 49.9062
+PHY-3002 : Step(220): len = 674162, overlap = 47.5938
+PHY-3002 : Step(221): len = 673182, overlap = 44.6875
+PHY-3002 : Step(222): len = 672865, overlap = 45.0938
+PHY-3002 : Step(223): len = 673192, overlap = 43.9688
+PHY-3002 : Step(224): len = 670992, overlap = 47.5938
+PHY-3002 : Step(225): len = 668862, overlap = 38.6562
+PHY-3002 : Step(226): len = 669061, overlap = 35.7188
+PHY-3002 : Step(227): len = 667598, overlap = 35.9375
+PHY-3002 : Step(228): len = 666035, overlap = 34.875
+PHY-3002 : Step(229): len = 665606, overlap = 33.3125
+PHY-3002 : Step(230): len = 664972, overlap = 30.9688
+PHY-3002 : Step(231): len = 664935, overlap = 31.2812
+PHY-3002 : Step(232): len = 665363, overlap = 30.5
+PHY-3002 : Step(233): len = 663287, overlap = 30.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000166009
+PHY-3002 : Step(234): len = 665070, overlap = 29.6875
+PHY-3002 : Step(235): len = 666191, overlap = 29.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 60/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 742136, over cnt = 2716(7%), over = 13181, worst = 45
+PHY-1001 : End global iterations;  1.401665s wall, 1.906250s user + 0.046875s system = 1.953125s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 97.37, top5 = 73.63, top10 = 63.43, top15 = 57.37.
+PHY-3001 : End congestion estimation;  1.679622s wall, 2.187500s user + 0.046875s system = 2.234375s CPU (133.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.253370s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.16158e-05
+PHY-3002 : Step(236): len = 664864, overlap = 303.781
+PHY-3002 : Step(237): len = 667781, overlap = 277.094
+PHY-3002 : Step(238): len = 666490, overlap = 246.094
+PHY-3002 : Step(239): len = 665895, overlap = 230.938
+PHY-3002 : Step(240): len = 666669, overlap = 211.375
+PHY-3002 : Step(241): len = 665168, overlap = 199.469
+PHY-3002 : Step(242): len = 664094, overlap = 190.406
+PHY-3002 : Step(243): len = 665025, overlap = 183.406
+PHY-3002 : Step(244): len = 663106, overlap = 172.875
+PHY-3002 : Step(245): len = 661446, overlap = 167.25
+PHY-3002 : Step(246): len = 661042, overlap = 167.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000143232
+PHY-3002 : Step(247): len = 662050, overlap = 161.281
+PHY-3002 : Step(248): len = 663622, overlap = 159.281
+PHY-3002 : Step(249): len = 667663, overlap = 152
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000286463
+PHY-3002 : Step(250): len = 674848, overlap = 133.938
+PHY-3002 : Step(251): len = 682793, overlap = 126.375
+PHY-3002 : Step(252): len = 689740, overlap = 112.938
+PHY-3002 : Step(253): len = 689942, overlap = 108.406
+PHY-3002 : Step(254): len = 688702, overlap = 104.156
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.398473s wall, 1.343750s user + 0.046875s system = 1.390625s CPU (99.4%)
+
+RUN-1004 : used memory is 572 MB, reserved memory is 560 MB, peak memory is 708 MB
+OPT-1001 : Total overflow 468.56 peak overflow 5.62
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1524/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 775912, over cnt = 3111(8%), over = 12149, worst = 24
+PHY-1001 : End global iterations;  1.007483s wall, 1.468750s user + 0.062500s system = 1.531250s CPU (152.0%)
+
+PHY-1001 : Congestion index: top1 = 82.05, top5 = 64.55, top10 = 56.65, top15 = 52.09.
+PHY-1001 : End incremental global routing;  1.306341s wall, 1.765625s user + 0.062500s system = 1.828125s CPU (139.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.229271s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (99.1%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 326 needs to be replaced
+PHY-3001 : design contains 17946 instances, 7502 luts, 9223 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6018 pins
+PHY-3001 : Found 3515 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 710127
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16479/20526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 791032, over cnt = 3153(8%), over = 12200, worst = 24
+PHY-1001 : End global iterations;  0.219201s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (135.4%)
+
+PHY-1001 : Congestion index: top1 = 82.35, top5 = 64.83, top10 = 57.03, top15 = 52.44.
+PHY-3001 : End congestion estimation;  0.459259s wall, 0.515625s user + 0.015625s system = 0.531250s CPU (115.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85742, tnet num: 20348, tinst num: 17946, tnode num: 116388, tedge num: 137518.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.466039s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (100.2%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 608 MB, peak memory is 710 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.780654s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(255): len = 709168, overlap = 2.53125
+PHY-3002 : Step(256): len = 708644, overlap = 2.40625
+PHY-3002 : Step(257): len = 708364, overlap = 2.59375
+PHY-3002 : Step(258): len = 708020, overlap = 2.59375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000115143
+PHY-3002 : Step(259): len = 707861, overlap = 2.59375
+PHY-3002 : Step(260): len = 707651, overlap = 2.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000230286
+PHY-3002 : Step(261): len = 707793, overlap = 2.71875
+PHY-3002 : Step(262): len = 709086, overlap = 2.78125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16495/20526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 788800, over cnt = 3143(8%), over = 12369, worst = 24
+PHY-1001 : End global iterations;  0.202211s wall, 0.234375s user + 0.031250s system = 0.265625s CPU (131.4%)
+
+PHY-1001 : Congestion index: top1 = 82.72, top5 = 65.24, top10 = 57.37, top15 = 52.75.
+PHY-3001 : End congestion estimation;  0.443333s wall, 0.468750s user + 0.031250s system = 0.500000s CPU (112.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.977107s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000552483
+PHY-3002 : Step(263): len = 708860, overlap = 107.406
+PHY-3002 : Step(264): len = 708918, overlap = 107.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00108202
+PHY-3002 : Step(265): len = 709736, overlap = 106.312
+PHY-3002 : Step(266): len = 710432, overlap = 106.094
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00216404
+PHY-3002 : Step(267): len = 711047, overlap = 106.156
+PHY-3002 : Step(268): len = 711632, overlap = 106.5
+PHY-3001 : Final: Len = 711632, Over = 106.5
+PHY-3001 : End incremental placement;  5.483983s wall, 5.921875s user + 0.359375s system = 6.281250s CPU (114.5%)
+
+OPT-1001 : Total overflow 472.34 peak overflow 5.62
+OPT-1001 : End high-fanout net optimization;  8.542031s wall, 9.484375s user + 0.437500s system = 9.921875s CPU (116.2%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 707, peak = 729.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16523/20526.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 793320, over cnt = 3106(8%), over = 11320, worst = 24
+PHY-1002 : len = 854160, over cnt = 2273(6%), over = 6031, worst = 22
+PHY-1002 : len = 904168, over cnt = 923(2%), over = 2028, worst = 22
+PHY-1002 : len = 914288, over cnt = 417(1%), over = 1020, worst = 17
+PHY-1002 : len = 931720, over cnt = 7(0%), over = 11, worst = 5
+PHY-1001 : End global iterations;  2.098262s wall, 2.796875s user + 0.015625s system = 2.812500s CPU (134.0%)
+
+PHY-1001 : Congestion index: top1 = 63.25, top5 = 55.19, top10 = 51.26, top15 = 48.79.
+OPT-1001 : End congestion update;  2.348177s wall, 3.031250s user + 0.015625s system = 3.046875s CPU (129.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20348 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.776578s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.6%)
+
+OPT-0007 : Start: WNS -968 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1478 NUM_FEPS 2 with 78 cells processed and 6126 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1478 NUM_FEPS 2 with 18 cells processed and 876 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1478 NUM_FEPS 2 with 12 cells processed and 100 slack improved
+OPT-1001 : End global optimization;  3.168023s wall, 3.843750s user + 0.015625s system = 3.859375s CPU (121.8%)
+
+OPT-1001 : Current memory(MB): used = 690, reserve = 687, peak = 729.
+OPT-1001 : End physical optimization;  13.717574s wall, 15.390625s user + 0.500000s system = 15.890625s CPU (115.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7502 LUT to BLE ...
+SYN-4008 : Packed 7502 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6090 remaining SEQ's ...
+SYN-4005 : Packed 3715 SEQ with LUT/SLICE
+SYN-4006 : 949 single LUT's are left
+SYN-4006 : 2375 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9877/13608 primitive instances ...
+PHY-3001 : End packing;  1.552412s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6794 instances
+RUN-1001 : 3323 mslices, 3323 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17524 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9989 nets have 2 pins
+RUN-1001 : 5737 nets have [3 - 5] pins
+RUN-1001 : 1114 nets have [6 - 10] pins
+RUN-1001 : 314 nets have [11 - 20] pins
+RUN-1001 : 339 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6792 instances, 6646 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3509 pins
+PHY-3001 : Found 1545 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 717807, Over = 281.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_data[45] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7505/17524.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 868744, over cnt = 1921(5%), over = 3261, worst = 9
+PHY-1002 : len = 877112, over cnt = 1232(3%), over = 1817, worst = 9
+PHY-1002 : len = 890808, over cnt = 548(1%), over = 749, worst = 9
+PHY-1002 : len = 895920, over cnt = 349(0%), over = 465, worst = 9
+PHY-1002 : len = 903712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.575626s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 61.53, top5 = 53.79, top10 = 49.77, top15 = 47.09.
+PHY-3001 : End congestion estimation;  1.943298s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (135.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73416, tnet num: 17346, tinst num: 6792, tnode num: 95662, tedge num: 123265.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.572623s wall, 1.546875s user + 0.015625s system = 1.562500s CPU (99.4%)
+
+RUN-1004 : used memory is 608 MB, reserved memory is 608 MB, peak memory is 729 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17346 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.415137s wall, 2.343750s user + 0.062500s system = 2.406250s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.32905e-05
+PHY-3002 : Step(269): len = 705562, overlap = 286.25
+PHY-3002 : Step(270): len = 699430, overlap = 285.25
+PHY-3002 : Step(271): len = 695123, overlap = 284
+PHY-3002 : Step(272): len = 692797, overlap = 289
+PHY-3002 : Step(273): len = 689764, overlap = 292.5
+PHY-3002 : Step(274): len = 687359, overlap = 294
+PHY-3002 : Step(275): len = 684567, overlap = 285.5
+PHY-3002 : Step(276): len = 682565, overlap = 289.75
+PHY-3002 : Step(277): len = 680802, overlap = 290.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.6581e-05
+PHY-3002 : Step(278): len = 685215, overlap = 279.5
+PHY-3002 : Step(279): len = 687975, overlap = 273.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000173162
+PHY-3002 : Step(280): len = 695382, overlap = 265
+PHY-3002 : Step(281): len = 707013, overlap = 257.25
+PHY-3002 : Step(282): len = 706840, overlap = 252
+PHY-3002 : Step(283): len = 706816, overlap = 245.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00030455
+PHY-3002 : Step(284): len = 713158, overlap = 246.75
+PHY-3002 : Step(285): len = 725518, overlap = 232.5
+PHY-3002 : Step(286): len = 736936, overlap = 219.75
+PHY-3002 : Step(287): len = 735645, overlap = 221.25
+PHY-3002 : Step(288): len = 734026, overlap = 220.75
+PHY-3002 : Step(289): len = 735231, overlap = 216
+PHY-3002 : Step(290): len = 737313, overlap = 209.25
+PHY-3002 : Step(291): len = 738136, overlap = 209.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000609099
+PHY-3002 : Step(292): len = 742556, overlap = 202
+PHY-3002 : Step(293): len = 749827, overlap = 201.25
+PHY-3002 : Step(294): len = 754590, overlap = 198
+PHY-3002 : Step(295): len = 758498, overlap = 202.5
+PHY-3002 : Step(296): len = 763284, overlap = 205
+PHY-3002 : Step(297): len = 765405, overlap = 199.75
+PHY-3002 : Step(298): len = 766249, overlap = 193
+PHY-3002 : Step(299): len = 766097, overlap = 196.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00117649
+PHY-3002 : Step(300): len = 769365, overlap = 192.5
+PHY-3002 : Step(301): len = 775138, overlap = 191.25
+PHY-3001 : Legalization ...
+PHY-9048 ERROR: Legalize hard bound bound3 failed due to insufficient space.
+PHY-9042 ERROR: Legalize MSLICE failed.
+RUN-1003 : finish command "place" in  37.305563s wall, 61.156250s user + 5.109375s system = 66.265625s CPU (177.6%)
+
+RUN-1004 : used memory is 539 MB, reserved memory is 542 MB, peak memory is 729 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_110122.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_110338.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_110338.log
new file mode 100644
index 0000000..2e67e5b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_110338.log
@@ -0,0 +1,1891 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 11:03:38 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.112734s wall, 2.078125s user + 0.031250s system = 2.109375s CPU (99.8%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 341 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13316 nets have 2 pins
+RUN-1001 : 5518 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.115858s wall, 1.046875s user + 0.062500s system = 1.109375s CPU (99.4%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 513 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.879083s wall, 1.796875s user + 0.078125s system = 1.875000s CPU (99.8%)
+
+PHY-3001 : Found 3481 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2000.
+PHY-3001 : End clustering;  0.121534s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (115.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28084e+06, overlap = 500.094
+PHY-3002 : Step(2): len = 1.17242e+06, overlap = 571.344
+PHY-3002 : Step(3): len = 844613, overlap = 622.125
+PHY-3002 : Step(4): len = 792819, overlap = 647.156
+PHY-3002 : Step(5): len = 614985, overlap = 782.562
+PHY-3002 : Step(6): len = 535173, overlap = 831.781
+PHY-3002 : Step(7): len = 456657, overlap = 923.094
+PHY-3002 : Step(8): len = 420915, overlap = 973.969
+PHY-3002 : Step(9): len = 371717, overlap = 1062.31
+PHY-3002 : Step(10): len = 339124, overlap = 1119.84
+PHY-3002 : Step(11): len = 300352, overlap = 1184.75
+PHY-3002 : Step(12): len = 276977, overlap = 1214.19
+PHY-3002 : Step(13): len = 248580, overlap = 1242.31
+PHY-3002 : Step(14): len = 222584, overlap = 1297.5
+PHY-3002 : Step(15): len = 202557, overlap = 1310.28
+PHY-3002 : Step(16): len = 187824, overlap = 1362.09
+PHY-3002 : Step(17): len = 175909, overlap = 1387.69
+PHY-3002 : Step(18): len = 161635, overlap = 1409.44
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.43137e-07
+PHY-3002 : Step(19): len = 162629, overlap = 1383.94
+PHY-3002 : Step(20): len = 192915, overlap = 1309.94
+PHY-3002 : Step(21): len = 194848, overlap = 1264.97
+PHY-3002 : Step(22): len = 197365, overlap = 1245.53
+PHY-3002 : Step(23): len = 192851, overlap = 1237.84
+PHY-3002 : Step(24): len = 191145, overlap = 1256.47
+PHY-3002 : Step(25): len = 187170, overlap = 1258.16
+PHY-3002 : Step(26): len = 186016, overlap = 1246.91
+PHY-3002 : Step(27): len = 182600, overlap = 1245.31
+PHY-3002 : Step(28): len = 181707, overlap = 1248.72
+PHY-3002 : Step(29): len = 178592, overlap = 1264.5
+PHY-3002 : Step(30): len = 176900, overlap = 1276.94
+PHY-3002 : Step(31): len = 174603, overlap = 1273.5
+PHY-3002 : Step(32): len = 175179, overlap = 1258.69
+PHY-3002 : Step(33): len = 173241, overlap = 1260.44
+PHY-3002 : Step(34): len = 173403, overlap = 1260.94
+PHY-3002 : Step(35): len = 171198, overlap = 1253.09
+PHY-3002 : Step(36): len = 171943, overlap = 1241.03
+PHY-3002 : Step(37): len = 169338, overlap = 1221.91
+PHY-3002 : Step(38): len = 169627, overlap = 1197.22
+PHY-3002 : Step(39): len = 168988, overlap = 1180.41
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.88627e-06
+PHY-3002 : Step(40): len = 174137, overlap = 1158.94
+PHY-3002 : Step(41): len = 188992, overlap = 1093.81
+PHY-3002 : Step(42): len = 197964, overlap = 1062.72
+PHY-3002 : Step(43): len = 203066, overlap = 1051.31
+PHY-3002 : Step(44): len = 203363, overlap = 1044.44
+PHY-3002 : Step(45): len = 203494, overlap = 1025.34
+PHY-3002 : Step(46): len = 202359, overlap = 1025.44
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.77255e-06
+PHY-3002 : Step(47): len = 212231, overlap = 1015.16
+PHY-3002 : Step(48): len = 228516, overlap = 981.156
+PHY-3002 : Step(49): len = 237174, overlap = 939.594
+PHY-3002 : Step(50): len = 240870, overlap = 906.5
+PHY-3002 : Step(51): len = 242254, overlap = 885.75
+PHY-3002 : Step(52): len = 242276, overlap = 878.781
+PHY-3002 : Step(53): len = 240233, overlap = 879.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.5451e-06
+PHY-3002 : Step(54): len = 256591, overlap = 840.688
+PHY-3002 : Step(55): len = 282738, overlap = 738.656
+PHY-3002 : Step(56): len = 295938, overlap = 692.781
+PHY-3002 : Step(57): len = 299140, overlap = 686.938
+PHY-3002 : Step(58): len = 299295, overlap = 653
+PHY-3002 : Step(59): len = 298493, overlap = 652.094
+PHY-3002 : Step(60): len = 296475, overlap = 639.875
+PHY-3002 : Step(61): len = 295924, overlap = 630.312
+PHY-3002 : Step(62): len = 293896, overlap = 624.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.50902e-05
+PHY-3002 : Step(63): len = 311897, overlap = 566
+PHY-3002 : Step(64): len = 335179, overlap = 479
+PHY-3002 : Step(65): len = 347123, overlap = 434.5
+PHY-3002 : Step(66): len = 352596, overlap = 444.594
+PHY-3002 : Step(67): len = 353547, overlap = 439.938
+PHY-3002 : Step(68): len = 353012, overlap = 436.438
+PHY-3002 : Step(69): len = 352384, overlap = 424.344
+PHY-3002 : Step(70): len = 349369, overlap = 410.781
+PHY-3002 : Step(71): len = 347416, overlap = 426.25
+PHY-3002 : Step(72): len = 345565, overlap = 429.969
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.01804e-05
+PHY-3002 : Step(73): len = 364910, overlap = 391.844
+PHY-3002 : Step(74): len = 379141, overlap = 343.875
+PHY-3002 : Step(75): len = 378634, overlap = 362.312
+PHY-3002 : Step(76): len = 379284, overlap = 364.281
+PHY-3002 : Step(77): len = 380644, overlap = 359.875
+PHY-3002 : Step(78): len = 381948, overlap = 345.625
+PHY-3002 : Step(79): len = 380907, overlap = 363.062
+PHY-3002 : Step(80): len = 382065, overlap = 348.938
+PHY-3002 : Step(81): len = 383498, overlap = 364.5
+PHY-3002 : Step(82): len = 383995, overlap = 360.219
+PHY-3002 : Step(83): len = 383056, overlap = 355.656
+PHY-3002 : Step(84): len = 383987, overlap = 359.562
+PHY-3002 : Step(85): len = 384796, overlap = 364.281
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.03608e-05
+PHY-3002 : Step(86): len = 402974, overlap = 340.5
+PHY-3002 : Step(87): len = 413716, overlap = 332.344
+PHY-3002 : Step(88): len = 412472, overlap = 327.562
+PHY-3002 : Step(89): len = 414032, overlap = 320.562
+PHY-3002 : Step(90): len = 418360, overlap = 310.375
+PHY-3002 : Step(91): len = 421340, overlap = 305.344
+PHY-3002 : Step(92): len = 419101, overlap = 294.438
+PHY-3002 : Step(93): len = 419188, overlap = 296.781
+PHY-3002 : Step(94): len = 420079, overlap = 293.562
+PHY-3002 : Step(95): len = 420905, overlap = 287.781
+PHY-3002 : Step(96): len = 420132, overlap = 291.406
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000118432
+PHY-3002 : Step(97): len = 433708, overlap = 284.656
+PHY-3002 : Step(98): len = 444191, overlap = 261.531
+PHY-3002 : Step(99): len = 443656, overlap = 251.5
+PHY-3002 : Step(100): len = 444761, overlap = 251.344
+PHY-3002 : Step(101): len = 448214, overlap = 253.375
+PHY-3002 : Step(102): len = 452628, overlap = 237.375
+PHY-3002 : Step(103): len = 451148, overlap = 245.125
+PHY-3002 : Step(104): len = 451869, overlap = 236.156
+PHY-3002 : Step(105): len = 453293, overlap = 230.031
+PHY-3002 : Step(106): len = 454330, overlap = 225.719
+PHY-3002 : Step(107): len = 452548, overlap = 234.25
+PHY-3002 : Step(108): len = 452026, overlap = 221.438
+PHY-3002 : Step(109): len = 453672, overlap = 217.75
+PHY-3002 : Step(110): len = 454976, overlap = 223.062
+PHY-3002 : Step(111): len = 453417, overlap = 213.812
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000221303
+PHY-3002 : Step(112): len = 462838, overlap = 215.312
+PHY-3002 : Step(113): len = 469356, overlap = 199.531
+PHY-3002 : Step(114): len = 469551, overlap = 191.094
+PHY-3002 : Step(115): len = 470604, overlap = 184.531
+PHY-3002 : Step(116): len = 473328, overlap = 189.031
+PHY-3002 : Step(117): len = 475879, overlap = 190.875
+PHY-3002 : Step(118): len = 475213, overlap = 189.406
+PHY-3002 : Step(119): len = 475790, overlap = 185.281
+PHY-3002 : Step(120): len = 477620, overlap = 178.125
+PHY-3002 : Step(121): len = 479302, overlap = 181.656
+PHY-3002 : Step(122): len = 478329, overlap = 173.094
+PHY-3002 : Step(123): len = 479066, overlap = 176.5
+PHY-3002 : Step(124): len = 481122, overlap = 182.625
+PHY-3002 : Step(125): len = 482264, overlap = 185.125
+PHY-3002 : Step(126): len = 481937, overlap = 182.031
+PHY-3002 : Step(127): len = 482763, overlap = 175.906
+PHY-3002 : Step(128): len = 483608, overlap = 180.75
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000442037
+PHY-3002 : Step(129): len = 492813, overlap = 169.312
+PHY-3002 : Step(130): len = 501660, overlap = 164.406
+PHY-3002 : Step(131): len = 502683, overlap = 161.594
+PHY-3002 : Step(132): len = 504142, overlap = 164.25
+PHY-3002 : Step(133): len = 507331, overlap = 172.5
+PHY-3002 : Step(134): len = 509157, overlap = 174.344
+PHY-3002 : Step(135): len = 508550, overlap = 170.188
+PHY-3002 : Step(136): len = 508990, overlap = 175
+PHY-3002 : Step(137): len = 511194, overlap = 171.219
+PHY-3002 : Step(138): len = 512714, overlap = 164.562
+PHY-3002 : Step(139): len = 512143, overlap = 163.719
+PHY-3002 : Step(140): len = 512818, overlap = 163.062
+PHY-3002 : Step(141): len = 514590, overlap = 156.125
+PHY-3002 : Step(142): len = 515065, overlap = 149.281
+PHY-3002 : Step(143): len = 513588, overlap = 148.562
+PHY-3002 : Step(144): len = 513172, overlap = 146.688
+PHY-3002 : Step(145): len = 513656, overlap = 140.781
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000870441
+PHY-3002 : Step(146): len = 519657, overlap = 140.094
+PHY-3002 : Step(147): len = 526873, overlap = 131.75
+PHY-3002 : Step(148): len = 529031, overlap = 135.719
+PHY-3002 : Step(149): len = 530317, overlap = 129.438
+PHY-3002 : Step(150): len = 532138, overlap = 131.125
+PHY-3002 : Step(151): len = 534501, overlap = 136.031
+PHY-3002 : Step(152): len = 535280, overlap = 136
+PHY-3002 : Step(153): len = 535826, overlap = 136.688
+PHY-3002 : Step(154): len = 535842, overlap = 130.531
+PHY-3002 : Step(155): len = 535692, overlap = 138.656
+PHY-3002 : Step(156): len = 535887, overlap = 143.281
+PHY-3002 : Step(157): len = 535890, overlap = 141.406
+PHY-3002 : Step(158): len = 536098, overlap = 144.156
+PHY-3002 : Step(159): len = 536645, overlap = 145.062
+PHY-3002 : Step(160): len = 537226, overlap = 145.062
+PHY-3002 : Step(161): len = 536624, overlap = 146.594
+PHY-3002 : Step(162): len = 536237, overlap = 148
+PHY-3002 : Step(163): len = 536236, overlap = 140.719
+PHY-3002 : Step(164): len = 536513, overlap = 141.844
+PHY-3002 : Step(165): len = 536270, overlap = 141.094
+PHY-3002 : Step(166): len = 536158, overlap = 141.156
+PHY-3002 : Step(167): len = 536085, overlap = 138.125
+PHY-3002 : Step(168): len = 536214, overlap = 138.094
+PHY-3002 : Step(169): len = 536049, overlap = 140.969
+PHY-3002 : Step(170): len = 536085, overlap = 138.188
+PHY-3002 : Step(171): len = 535991, overlap = 135.219
+PHY-3002 : Step(172): len = 535942, overlap = 133.125
+PHY-3002 : Step(173): len = 535673, overlap = 134.344
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00158547
+PHY-3002 : Step(174): len = 537766, overlap = 132.906
+PHY-3002 : Step(175): len = 539201, overlap = 133.156
+PHY-3002 : Step(176): len = 539731, overlap = 133.719
+PHY-3002 : Step(177): len = 540260, overlap = 134.656
+PHY-3002 : Step(178): len = 541295, overlap = 135.219
+PHY-3002 : Step(179): len = 542142, overlap = 136.719
+PHY-3002 : Step(180): len = 542540, overlap = 135.281
+PHY-3002 : Step(181): len = 542767, overlap = 133.875
+PHY-3002 : Step(182): len = 542912, overlap = 132.219
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00261343
+PHY-3002 : Step(183): len = 544436, overlap = 132.406
+PHY-3002 : Step(184): len = 547743, overlap = 128.188
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014865s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (105.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 684464, over cnt = 1551(4%), over = 7322, worst = 53
+PHY-1001 : End global iterations;  0.666746s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (152.3%)
+
+PHY-1001 : Congestion index: top1 = 84.81, top5 = 62.45, top10 = 52.34, top15 = 46.58.
+PHY-3001 : End congestion estimation;  0.900263s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (140.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.886303s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.92885e-05
+PHY-3002 : Step(185): len = 623860, overlap = 82.6562
+PHY-3002 : Step(186): len = 634110, overlap = 77.7812
+PHY-3002 : Step(187): len = 634425, overlap = 88.5625
+PHY-3002 : Step(188): len = 636045, overlap = 86.25
+PHY-3002 : Step(189): len = 640088, overlap = 70.4375
+PHY-3002 : Step(190): len = 652070, overlap = 72.1875
+PHY-3002 : Step(191): len = 654137, overlap = 73.9062
+PHY-3002 : Step(192): len = 658401, overlap = 70.25
+PHY-3002 : Step(193): len = 663727, overlap = 64.6875
+PHY-3002 : Step(194): len = 668346, overlap = 62.3125
+PHY-3002 : Step(195): len = 668225, overlap = 64.3125
+PHY-3002 : Step(196): len = 670385, overlap = 57.6875
+PHY-3002 : Step(197): len = 671934, overlap = 48.75
+PHY-3002 : Step(198): len = 672763, overlap = 44.5
+PHY-3002 : Step(199): len = 674042, overlap = 41.375
+PHY-3002 : Step(200): len = 673147, overlap = 40.625
+PHY-3002 : Step(201): len = 673467, overlap = 43.5312
+PHY-3002 : Step(202): len = 673855, overlap = 42.0625
+PHY-3002 : Step(203): len = 671989, overlap = 42.3438
+PHY-3002 : Step(204): len = 669259, overlap = 35.7188
+PHY-3002 : Step(205): len = 666901, overlap = 33.5
+PHY-3002 : Step(206): len = 664581, overlap = 31.8438
+PHY-3002 : Step(207): len = 663880, overlap = 32.4375
+PHY-3002 : Step(208): len = 663225, overlap = 35.5625
+PHY-3002 : Step(209): len = 663914, overlap = 39.125
+PHY-3002 : Step(210): len = 662757, overlap = 39.0938
+PHY-3002 : Step(211): len = 661657, overlap = 40.9375
+PHY-3002 : Step(212): len = 659867, overlap = 41.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000198577
+PHY-3002 : Step(213): len = 661153, overlap = 40
+PHY-3002 : Step(214): len = 663409, overlap = 39.5938
+PHY-3002 : Step(215): len = 670481, overlap = 38.5312
+PHY-3002 : Step(216): len = 671125, overlap = 38.9375
+PHY-3002 : Step(217): len = 672366, overlap = 38.25
+PHY-3002 : Step(218): len = 672844, overlap = 37.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000397154
+PHY-3002 : Step(219): len = 676126, overlap = 38.125
+PHY-3002 : Step(220): len = 685283, overlap = 36.0938
+PHY-3002 : Step(221): len = 696713, overlap = 37.3438
+PHY-3002 : Step(222): len = 699455, overlap = 40.625
+PHY-3002 : Step(223): len = 698323, overlap = 41.0938
+PHY-3002 : Step(224): len = 697168, overlap = 45.7812
+PHY-3002 : Step(225): len = 693985, overlap = 47.25
+PHY-3002 : Step(226): len = 694116, overlap = 50.7188
+PHY-3002 : Step(227): len = 696929, overlap = 50.625
+PHY-3002 : Step(228): len = 696578, overlap = 51.4688
+PHY-3002 : Step(229): len = 696289, overlap = 52.5
+PHY-3002 : Step(230): len = 698963, overlap = 46.8438
+PHY-3002 : Step(231): len = 699029, overlap = 48.5625
+PHY-3002 : Step(232): len = 700584, overlap = 48.0312
+PHY-3002 : Step(233): len = 700797, overlap = 45.6875
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000794308
+PHY-3002 : Step(234): len = 703306, overlap = 47.875
+PHY-3002 : Step(235): len = 708762, overlap = 46.4062
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 51/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 787888, over cnt = 2763(7%), over = 14234, worst = 100
+PHY-1001 : End global iterations;  1.448805s wall, 1.828125s user + 0.031250s system = 1.859375s CPU (128.3%)
+
+PHY-1001 : Congestion index: top1 = 108.90, top5 = 75.79, top10 = 64.09, top15 = 57.74.
+PHY-3001 : End congestion estimation;  1.702128s wall, 2.093750s user + 0.031250s system = 2.125000s CPU (124.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.210806s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000105114
+PHY-3002 : Step(236): len = 706207, overlap = 283.594
+PHY-3002 : Step(237): len = 711789, overlap = 226
+PHY-3002 : Step(238): len = 710814, overlap = 205.719
+PHY-3002 : Step(239): len = 707860, overlap = 190.938
+PHY-3002 : Step(240): len = 704044, overlap = 167.531
+PHY-3002 : Step(241): len = 701978, overlap = 145.281
+PHY-3002 : Step(242): len = 698445, overlap = 137.656
+PHY-3002 : Step(243): len = 693882, overlap = 135.531
+PHY-3002 : Step(244): len = 691058, overlap = 134.031
+PHY-3002 : Step(245): len = 688796, overlap = 135.469
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000210228
+PHY-3002 : Step(246): len = 689136, overlap = 130.594
+PHY-3002 : Step(247): len = 691394, overlap = 123.156
+PHY-3002 : Step(248): len = 692003, overlap = 123
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000420456
+PHY-3002 : Step(249): len = 697858, overlap = 111.125
+PHY-3002 : Step(250): len = 705576, overlap = 102.812
+PHY-3002 : Step(251): len = 706892, overlap = 100.094
+PHY-3002 : Step(252): len = 707033, overlap = 99.0938
+PHY-3002 : Step(253): len = 706503, overlap = 98.375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000840912
+PHY-3002 : Step(254): len = 709483, overlap = 95.3125
+PHY-3002 : Step(255): len = 714743, overlap = 86.9062
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00139064
+PHY-3002 : Step(256): len = 716408, overlap = 84.6875
+PHY-3002 : Step(257): len = 721738, overlap = 76.1875
+PHY-3002 : Step(258): len = 729414, overlap = 69.8438
+PHY-3002 : Step(259): len = 732153, overlap = 68.7188
+PHY-3002 : Step(260): len = 733296, overlap = 62.9062
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.473873s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (99.7%)
+
+RUN-1004 : used memory is 574 MB, reserved memory is 562 MB, peak memory is 709 MB
+OPT-1001 : Total overflow 385.75 peak overflow 4.25
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1134/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 835792, over cnt = 3150(8%), over = 12033, worst = 86
+PHY-1001 : End global iterations;  1.242379s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 87.61, top5 = 64.35, top10 = 56.02, top15 = 51.40.
+PHY-1001 : End incremental global routing;  1.557623s wall, 2.015625s user + 0.031250s system = 2.046875s CPU (131.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.893789s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (99.6%)
+
+OPT-1001 : 53 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17533 has valid locations, 362 needs to be replaced
+PHY-3001 : design contains 17980 instances, 7521 luts, 9238 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6031 pins
+PHY-3001 : Found 3517 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 756428
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16887/20560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853352, over cnt = 3196(9%), over = 12105, worst = 86
+PHY-1001 : End global iterations;  0.243777s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (153.8%)
+
+PHY-1001 : Congestion index: top1 = 87.97, top5 = 64.83, top10 = 56.51, top15 = 51.86.
+PHY-3001 : End congestion estimation;  0.493674s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (129.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85866, tnet num: 20382, tinst num: 17980, tnode num: 116560, tedge num: 137698.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.424381s wall, 1.390625s user + 0.031250s system = 1.421875s CPU (99.8%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 614 MB, peak memory is 713 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.362258s wall, 2.328125s user + 0.031250s system = 2.359375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(261): len = 755292, overlap = 0
+PHY-3002 : Step(262): len = 754638, overlap = 0
+PHY-3002 : Step(263): len = 754210, overlap = 0
+PHY-3002 : Step(264): len = 753944, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17018/20560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 849968, over cnt = 3218(9%), over = 12192, worst = 86
+PHY-1001 : End global iterations;  0.199509s wall, 0.234375s user + 0.046875s system = 0.281250s CPU (141.0%)
+
+PHY-1001 : Congestion index: top1 = 88.58, top5 = 65.14, top10 = 56.80, top15 = 52.09.
+PHY-3001 : End congestion estimation;  0.490015s wall, 0.484375s user + 0.046875s system = 0.531250s CPU (108.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.921778s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000569948
+PHY-3002 : Step(265): len = 753930, overlap = 64.875
+PHY-3002 : Step(266): len = 754111, overlap = 64.8125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.0011399
+PHY-3002 : Step(267): len = 754036, overlap = 64.8125
+PHY-3002 : Step(268): len = 754614, overlap = 64.8125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00226217
+PHY-3002 : Step(269): len = 754929, overlap = 65.5938
+PHY-3002 : Step(270): len = 755310, overlap = 65.2812
+PHY-3001 : Final: Len = 755310, Over = 65.2812
+PHY-3001 : End incremental placement;  4.972325s wall, 5.250000s user + 0.234375s system = 5.484375s CPU (110.3%)
+
+OPT-1001 : Total overflow 392.31 peak overflow 4.25
+OPT-1001 : End high-fanout net optimization;  7.953890s wall, 8.765625s user + 0.296875s system = 9.062500s CPU (113.9%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 712, peak = 734.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16913/20560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853456, over cnt = 3154(8%), over = 11183, worst = 86
+PHY-1002 : len = 905144, over cnt = 2328(6%), over = 6061, worst = 41
+PHY-1002 : len = 949568, over cnt = 947(2%), over = 2186, worst = 17
+PHY-1002 : len = 967144, over cnt = 367(1%), over = 800, worst = 16
+PHY-1002 : len = 979224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.863984s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (137.5%)
+
+PHY-1001 : Congestion index: top1 = 63.49, top5 = 54.87, top10 = 50.39, top15 = 47.67.
+OPT-1001 : End congestion update;  2.119742s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (132.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.803776s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (99.1%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 37 cells processed and 8400 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 39 cells processed and 2607 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 20 cells processed and 2600 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 20 cells processed and 850 slack improved
+OPT-1001 : End global optimization;  2.970750s wall, 3.640625s user + 0.015625s system = 3.656250s CPU (123.1%)
+
+OPT-1001 : Current memory(MB): used = 695, reserve = 694, peak = 734.
+OPT-1001 : End physical optimization;  13.176364s wall, 14.734375s user + 0.343750s system = 15.078125s CPU (114.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7521 LUT to BLE ...
+SYN-4008 : Packed 7521 LUT and 3132 SEQ to BLE.
+SYN-4003 : Packing 6106 remaining SEQ's ...
+SYN-4005 : Packed 4062 SEQ with LUT/SLICE
+SYN-4006 : 620 single LUT's are left
+SYN-4006 : 2044 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9565/13296 primitive instances ...
+PHY-3001 : End packing;  1.592889s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6733 instances
+RUN-1001 : 3293 mslices, 3292 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17558 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10003 nets have 2 pins
+RUN-1001 : 5745 nets have [3 - 5] pins
+RUN-1001 : 1107 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 342 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6731 instances, 6585 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3563 pins
+PHY-3001 : Found 1575 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 758504, Over = 249
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7321/17558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 917856, over cnt = 2085(5%), over = 3441, worst = 8
+PHY-1002 : len = 926120, over cnt = 1317(3%), over = 1920, worst = 8
+PHY-1002 : len = 941504, over cnt = 453(1%), over = 593, worst = 6
+PHY-1002 : len = 946016, over cnt = 226(0%), over = 286, worst = 6
+PHY-1002 : len = 950840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.725933s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 60.91, top5 = 52.71, top10 = 48.75, top15 = 46.16.
+PHY-3001 : End congestion estimation;  2.113925s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (133.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73714, tnet num: 17380, tinst num: 6731, tnode num: 96154, tedge num: 123748.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.576434s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.1%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 615 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.425272s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.32339e-05
+PHY-3002 : Step(271): len = 743011, overlap = 241.25
+PHY-3002 : Step(272): len = 734694, overlap = 243
+PHY-3002 : Step(273): len = 729290, overlap = 244.5
+PHY-3002 : Step(274): len = 725509, overlap = 244
+PHY-3002 : Step(275): len = 722064, overlap = 240.5
+PHY-3002 : Step(276): len = 718908, overlap = 245.5
+PHY-3002 : Step(277): len = 715849, overlap = 246
+PHY-3002 : Step(278): len = 713621, overlap = 252
+PHY-3002 : Step(279): len = 711752, overlap = 251.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000106468
+PHY-3002 : Step(280): len = 715233, overlap = 243.5
+PHY-3002 : Step(281): len = 719361, overlap = 231.5
+PHY-3002 : Step(282): len = 719659, overlap = 227.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000212936
+PHY-3002 : Step(283): len = 727040, overlap = 221
+PHY-3002 : Step(284): len = 737239, overlap = 205.5
+PHY-3002 : Step(285): len = 736213, overlap = 205.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.365791s wall, 0.250000s user + 0.640625s system = 0.890625s CPU (243.5%)
+
+PHY-3001 : Trial Legalized: Len = 902449
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 638/17558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.02257e+06, over cnt = 2801(7%), over = 4718, worst = 7
+PHY-1002 : len = 1.04056e+06, over cnt = 1659(4%), over = 2362, worst = 7
+PHY-1002 : len = 1.06032e+06, over cnt = 587(1%), over = 777, worst = 5
+PHY-1002 : len = 1.06961e+06, over cnt = 134(0%), over = 156, worst = 3
+PHY-1002 : len = 1.07318e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1001 : End global iterations;  2.658144s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 62.52, top5 = 56.22, top10 = 52.70, top15 = 50.21.
+PHY-3001 : End congestion estimation;  3.119038s wall, 4.125000s user + 0.000000s system = 4.125000s CPU (132.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.152355s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000166361
+PHY-3002 : Step(286): len = 857743, overlap = 73.75
+PHY-3002 : Step(287): len = 835082, overlap = 97
+PHY-3002 : Step(288): len = 818670, overlap = 117.75
+PHY-3002 : Step(289): len = 807467, overlap = 137.25
+PHY-3002 : Step(290): len = 800344, overlap = 146
+PHY-3002 : Step(291): len = 792463, overlap = 155.25
+PHY-3002 : Step(292): len = 785938, overlap = 168.75
+PHY-3002 : Step(293): len = 782863, overlap = 170.75
+PHY-3002 : Step(294): len = 779843, overlap = 170.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000332723
+PHY-3002 : Step(295): len = 784404, overlap = 167.75
+PHY-3002 : Step(296): len = 787783, overlap = 169.75
+PHY-3002 : Step(297): len = 790252, overlap = 167.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000626912
+PHY-3002 : Step(298): len = 796734, overlap = 165
+PHY-3002 : Step(299): len = 799613, overlap = 162.5
+PHY-3002 : Step(300): len = 801585, overlap = 163
+PHY-3002 : Step(301): len = 803206, overlap = 162.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.080384s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (97.2%)
+
+PHY-3001 : Legalized: Len = 864948, Over = 0
+PHY-3001 : Spreading special nets. 446 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.110197s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.3%)
+
+PHY-3001 : 653 instances has been re-located, deltaX = 263, deltaY = 400, maxDist = 6.
+PHY-3001 : Final: Len = 875222, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73714, tnet num: 17380, tinst num: 6734, tnode num: 96154, tedge num: 123748.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.862522s wall, 1.828125s user + 0.031250s system = 1.859375s CPU (99.8%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 608 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3284/17558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00867e+06, over cnt = 2667(7%), over = 4302, worst = 7
+PHY-1002 : len = 1.02087e+06, over cnt = 1694(4%), over = 2523, worst = 7
+PHY-1002 : len = 1.04002e+06, over cnt = 650(1%), over = 931, worst = 6
+PHY-1002 : len = 1.0512e+06, over cnt = 154(0%), over = 208, worst = 4
+PHY-1002 : len = 1.05515e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.924282s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (151.0%)
+
+PHY-1001 : Congestion index: top1 = 62.39, top5 = 54.63, top10 = 50.95, top15 = 48.64.
+PHY-1001 : End incremental global routing;  2.294152s wall, 3.250000s user + 0.031250s system = 3.281250s CPU (143.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.867166s wall, 0.828125s user + 0.031250s system = 0.859375s CPU (99.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6642 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6753 instances, 6604 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3640 pins
+PHY-3001 : Found 1579 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 878207
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16081/17578.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05898e+06, over cnt = 80(0%), over = 93, worst = 4
+PHY-1002 : len = 1.0592e+06, over cnt = 42(0%), over = 43, worst = 2
+PHY-1002 : len = 1.05958e+06, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 1.05974e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.05978e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.743681s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (107.2%)
+
+PHY-1001 : Congestion index: top1 = 62.39, top5 = 54.64, top10 = 50.97, top15 = 48.67.
+PHY-3001 : End congestion estimation;  1.046354s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (104.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73921, tnet num: 17400, tinst num: 6753, tnode num: 96393, tedge num: 123989.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.837141s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.4%)
+
+RUN-1004 : used memory is 665 MB, reserved memory is 672 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17400 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.739537s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(302): len = 877268, overlap = 0
+PHY-3002 : Step(303): len = 876828, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16066/17578.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05694e+06, over cnt = 51(0%), over = 70, worst = 4
+PHY-1002 : len = 1.05714e+06, over cnt = 21(0%), over = 22, worst = 2
+PHY-1002 : len = 1.05726e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.05733e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.05741e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.791761s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 62.39, top5 = 54.62, top10 = 50.95, top15 = 48.65.
+PHY-3001 : End congestion estimation;  1.122304s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (101.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17400 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.886955s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000226475
+PHY-3002 : Step(304): len = 876868, overlap = 2.25
+PHY-3002 : Step(305): len = 876868, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.006120s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 877102, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061938s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.9%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 3, deltaY = 4, maxDist = 1.
+PHY-3001 : Final: Len = 877222, Over = 0
+PHY-3001 : End incremental placement;  6.250055s wall, 6.390625s user + 0.031250s system = 6.421875s CPU (102.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.924646s wall, 10.984375s user + 0.093750s system = 11.078125s CPU (111.6%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 739, peak = 745.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16050/17578.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05782e+06, over cnt = 35(0%), over = 52, worst = 4
+PHY-1002 : len = 1.05798e+06, over cnt = 7(0%), over = 11, worst = 3
+PHY-1002 : len = 1.05804e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.428082s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (109.5%)
+
+PHY-1001 : Congestion index: top1 = 62.39, top5 = 54.61, top10 = 50.95, top15 = 48.66.
+OPT-1001 : End congestion update;  0.742043s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (107.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17400 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.713809s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.5%)
+
+OPT-0007 : Start: WNS -1033 TNS -1947 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6665 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6753 instances, 6604 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3640 pins
+PHY-3001 : Found 1579 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 881138, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061243s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.1%)
+
+PHY-3001 : 26 instances has been re-located, deltaX = 6, deltaY = 28, maxDist = 8.
+PHY-3001 : Final: Len = 882046, Over = 0
+PHY-3001 : End incremental legalization;  0.372602s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (113.2%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 35 cells processed and 10885 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6665 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6753 instances, 6604 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3640 pins
+PHY-3001 : Found 1579 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 884040, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.057700s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.2%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 884126, Over = 0
+PHY-3001 : End incremental legalization;  0.362224s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.2%)
+
+OPT-0007 : Iter 2: improved WNS -983 TNS -1847 NUM_FEPS 3 with 14 cells processed and 3461 slack improved
+OPT-0007 : Iter 3: improved WNS -983 TNS -1847 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.456054s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (103.7%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 739, peak = 745.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17400 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.726700s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15897/17578.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06499e+06, over cnt = 167(0%), over = 204, worst = 4
+PHY-1002 : len = 1.06508e+06, over cnt = 96(0%), over = 104, worst = 3
+PHY-1002 : len = 1.0659e+06, over cnt = 31(0%), over = 34, worst = 3
+PHY-1002 : len = 1.06629e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.06652e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.854475s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 62.78, top5 = 54.83, top10 = 51.13, top15 = 48.82.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17400 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.706399s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1033 TNS -1947 NUM_FEPS 3
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 62.275862
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1033ps with logic level 2 
+RUN-1001 :       #2 path slack -947ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17578 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17578 nets
+OPT-1001 : End physical optimization;  17.210108s wall, 18.375000s user + 0.140625s system = 18.515625s CPU (107.6%)
+
+RUN-1003 : finish command "place" in  59.765168s wall, 91.062500s user + 5.625000s system = 96.687500s CPU (161.8%)
+
+RUN-1004 : used memory is 608 MB, reserved memory is 620 MB, peak memory is 745 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.676471s wall, 2.890625s user + 0.000000s system = 2.890625s CPU (172.4%)
+
+RUN-1004 : used memory is 608 MB, reserved memory is 621 MB, peak memory is 745 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6755 instances
+RUN-1001 : 3303 mslices, 3301 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17578 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10003 nets have 2 pins
+RUN-1001 : 5739 nets have [3 - 5] pins
+RUN-1001 : 1117 nets have [6 - 10] pins
+RUN-1001 : 336 nets have [11 - 20] pins
+RUN-1001 : 354 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73921, tnet num: 17400, tinst num: 6753, tnode num: 96393, tedge num: 123989.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.556500s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.4%)
+
+RUN-1004 : used memory is 600 MB, reserved memory is 599 MB, peak memory is 745 MB
+PHY-1001 : 3303 mslices, 3301 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17400 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 996440, over cnt = 2891(8%), over = 4679, worst = 7
+PHY-1002 : len = 1.0125e+06, over cnt = 1861(5%), over = 2750, worst = 7
+PHY-1002 : len = 1.03524e+06, over cnt = 660(1%), over = 954, worst = 6
+PHY-1002 : len = 1.04871e+06, over cnt = 9(0%), over = 10, worst = 2
+PHY-1002 : len = 1.04898e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.160385s wall, 4.109375s user + 0.046875s system = 4.156250s CPU (131.5%)
+
+PHY-1001 : Congestion index: top1 = 62.50, top5 = 54.71, top10 = 50.95, top15 = 48.50.
+PHY-1001 : End global routing;  3.483956s wall, 4.421875s user + 0.046875s system = 4.468750s CPU (128.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 709, reserve = 710, peak = 745.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 983, reserve = 985, peak = 983.
+PHY-1001 : End build detailed router design. 3.916164s wall, 3.859375s user + 0.031250s system = 3.890625s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270576, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.959346s wall, 4.953125s user + 0.000000s system = 4.953125s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270632, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.422335s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1021, peak = 1018.
+PHY-1001 : End phase 1; 5.395434s wall, 5.390625s user + 0.000000s system = 5.390625s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.54635e+06, over cnt = 1676(0%), over = 1678, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1040, peak = 1038.
+PHY-1001 : End initial routed; 42.938062s wall, 69.609375s user + 0.531250s system = 70.140625s CPU (163.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16501(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.747   |  -4.291   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.154102s wall, 3.156250s user + 0.000000s system = 3.156250s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1053, peak = 1051.
+PHY-1001 : End phase 2; 46.092231s wall, 72.765625s user + 0.531250s system = 73.296875s CPU (159.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.747ns STNS -4.013ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.135735s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.6%)
+
+PHY-1022 : len = 2.54635e+06, over cnt = 1677(0%), over = 1679, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.388742s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.51479e+06, over cnt = 595(0%), over = 595, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.703834s wall, 2.296875s user + 0.031250s system = 2.328125s CPU (136.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.51241e+06, over cnt = 117(0%), over = 117, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.757998s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (140.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.51318e+06, over cnt = 21(0%), over = 21, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.344138s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (118.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.51339e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.214141s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.51348e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.204012s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.51348e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.234898s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.51348e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.317622s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (98.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.5135e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.206865s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.5135e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.165585s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16501(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.747   |  -4.013   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.243897s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 561 feed throughs used by 419 nets
+PHY-1001 : End commit to database; 2.324501s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1162, peak = 1156.
+PHY-1001 : End phase 3; 10.517962s wall, 11.421875s user + 0.078125s system = 11.500000s CPU (109.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.747ns STNS -4.013ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.132872s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.1%)
+
+PHY-1022 : len = 2.5135e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.364914s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.747ns, -4.013ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16501(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.747   |  -4.013   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.189535s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 561 feed throughs used by 419 nets
+PHY-1001 : End commit to database; 2.378310s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1171, peak = 1164.
+PHY-1001 : End phase 4; 5.956940s wall, 5.953125s user + 0.000000s system = 5.953125s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.5135e+06
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1173, peak = 1167.
+PHY-1001 : End export database. 0.060899s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.6%)
+
+PHY-1001 : End detail routing;  72.330282s wall, 99.843750s user + 0.640625s system = 100.484375s CPU (138.9%)
+
+RUN-1003 : finish command "route" in  78.408224s wall, 106.828125s user + 0.718750s system = 107.546875s CPU (137.2%)
+
+RUN-1004 : used memory is 1088 MB, reserved memory is 1096 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10268   out of  19600   52.39%
+#reg                     9371   out of  19600   47.81%
+#le                     12230
+  #lut only              2859   out of  12230   23.38%
+  #reg only              1962   out of  12230   16.04%
+  #lut&reg               7409   out of  12230   60.58%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1813
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1404
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1288
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               983
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    142
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               22
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg7_syn_119.f0                          3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             sampling_fe_a/u0_soft_n/reg0_syn_25.f0             3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12230  |9241    |1027    |9403    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |541    |468     |23      |438     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |106    |98      |4       |88      |4       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |10      |0       |0       |
+|    U_crc16_24b               |crc16_24b            |22     |22      |0       |16      |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |772    |400     |96      |578     |0       |0       |
+|    u_ADconfig                |AD_config            |195    |131     |25      |143     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |162     |71      |121     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |754    |504     |96      |557     |0       |0       |
+|    u_ADconfig                |AD_config            |180    |145     |25      |128     |0       |0       |
+|    u_gen_sp                  |gen_sp               |262    |181     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2942   |2285    |306     |2080    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |5       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |131     |17      |140     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2727   |2132    |289     |1905    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2304   |1852    |253     |1555    |22      |0       |
+|        channelPart           |channel_part_8478    |152    |145     |3       |127     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |40      |0       |0       |
+|        ram_switch            |ram_switch           |1778   |1399    |197     |1170    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |218    |191     |27      |121     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |16      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |10      |0       |0       |
+|          insert              |insert               |1004   |652     |170     |713     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |556    |556     |0       |336     |0       |0       |
+|        read_ram_i            |read_ram             |291    |238     |44      |196     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |232    |192     |40      |153     |0       |0       |
+|          read_ram_data       |read_ram_data        |56     |44      |4       |40      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |330    |207     |36      |281     |3       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3056   |2362    |349     |2100    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |183    |131     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |2839   |2211    |332     |1918    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |1       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2416   |1884    |290     |1565    |22      |1       |
+|        channelPart           |channel_part_8478    |232    |227     |3       |146     |0       |0       |
+|        fifo_adc              |fifo_adc             |61     |52      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |1741   |1342    |197     |1143    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |225    |198     |27      |116     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |17      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |5       |0       |0       |
+|          insert              |insert               |1002   |635     |170     |696     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |514    |509     |0       |331     |0       |0       |
+|        read_ram_i            |read_ram_rev         |355    |242     |81      |205     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |286    |201     |73      |154     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |69     |41      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets  
+    #1          1       9941  
+    #2          2       3759  
+    #3          3       1406  
+    #4          4       571   
+    #5        5-10      1180  
+    #6        11-50     602   
+    #7       51-100      22   
+    #8       101-500     1    
+    #9        >500       1    
+  Average     2.91            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.054441s wall, 3.531250s user + 0.015625s system = 3.546875s CPU (172.6%)
+
+RUN-1004 : used memory is 1089 MB, reserved memory is 1097 MB, peak memory is 1167 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73921, tnet num: 17400, tinst num: 6753, tnode num: 96393, tedge num: 123989.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.554682s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.5%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1101 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17400 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.433755s wall, 1.437500s user + 0.000000s system = 1.437500s CPU (100.3%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1106 MB, peak memory is 1167 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6753
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17578, pip num: 178111
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 561
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3246 valid insts, and 490102 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.673796s wall, 64.859375s user + 0.156250s system = 65.015625s CPU (672.1%)
+
+RUN-1004 : used memory is 1264 MB, reserved memory is 1267 MB, peak memory is 1380 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_110338.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_135156.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_135156.log
new file mode 100644
index 0000000..bd12543
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_135156.log
@@ -0,0 +1,3380 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 13:51:56 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.183634s wall, 2.125000s user + 0.062500s system = 2.187500s CPU (100.2%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 320 MB, peak memory is 347 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2869 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18339 instances
+RUN-0007 : 7416 luts, 9700 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20917 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14014 nets have 2 pins
+RUN-1001 : 5446 nets have [3 - 5] pins
+RUN-1001 : 1046 nets have [6 - 10] pins
+RUN-1001 : 157 nets have [11 - 20] pins
+RUN-1001 : 180 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4130     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18337 instances, 7416 luts, 9700 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6554 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87317, tnet num: 20739, tinst num: 18337, tnode num: 119372, tedge num: 139886.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.153405s wall, 1.109375s user + 0.046875s system = 1.156250s CPU (100.2%)
+
+RUN-1004 : used memory is 543 MB, reserved memory is 527 MB, peak memory is 543 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.944096s wall, 1.890625s user + 0.046875s system = 1.937500s CPU (99.7%)
+
+PHY-3001 : Found 3478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.26661e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18337.
+PHY-3001 : Level 1 #clusters 2100.
+PHY-3001 : End clustering;  0.126678s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (148.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29052e+06, overlap = 504.562
+PHY-3002 : Step(2): len = 1.21167e+06, overlap = 521.531
+PHY-3002 : Step(3): len = 837651, overlap = 606.375
+PHY-3002 : Step(4): len = 782198, overlap = 639.5
+PHY-3002 : Step(5): len = 598854, overlap = 746.688
+PHY-3002 : Step(6): len = 531278, overlap = 831.344
+PHY-3002 : Step(7): len = 454920, overlap = 904.312
+PHY-3002 : Step(8): len = 423691, overlap = 951.906
+PHY-3002 : Step(9): len = 379121, overlap = 989.969
+PHY-3002 : Step(10): len = 342425, overlap = 1054.25
+PHY-3002 : Step(11): len = 308541, overlap = 1086.38
+PHY-3002 : Step(12): len = 284276, overlap = 1152.78
+PHY-3002 : Step(13): len = 256521, overlap = 1197.28
+PHY-3002 : Step(14): len = 239974, overlap = 1225.69
+PHY-3002 : Step(15): len = 215446, overlap = 1243.62
+PHY-3002 : Step(16): len = 198495, overlap = 1302.72
+PHY-3002 : Step(17): len = 183235, overlap = 1317.28
+PHY-3002 : Step(18): len = 169809, overlap = 1350.41
+PHY-3002 : Step(19): len = 161590, overlap = 1381.31
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.22792e-06
+PHY-3002 : Step(20): len = 163219, overlap = 1347.62
+PHY-3002 : Step(21): len = 194101, overlap = 1300.06
+PHY-3002 : Step(22): len = 196165, overlap = 1225.78
+PHY-3002 : Step(23): len = 200655, overlap = 1231.31
+PHY-3002 : Step(24): len = 198318, overlap = 1209.12
+PHY-3002 : Step(25): len = 197312, overlap = 1218.06
+PHY-3002 : Step(26): len = 195416, overlap = 1222.22
+PHY-3002 : Step(27): len = 195025, overlap = 1217.47
+PHY-3002 : Step(28): len = 192543, overlap = 1218.41
+PHY-3002 : Step(29): len = 189628, overlap = 1201.94
+PHY-3002 : Step(30): len = 188148, overlap = 1214.22
+PHY-3002 : Step(31): len = 184561, overlap = 1204.16
+PHY-3002 : Step(32): len = 183719, overlap = 1198.19
+PHY-3002 : Step(33): len = 182980, overlap = 1210.56
+PHY-3002 : Step(34): len = 182701, overlap = 1218.28
+PHY-3002 : Step(35): len = 182513, overlap = 1216.25
+PHY-3002 : Step(36): len = 183664, overlap = 1205.16
+PHY-3002 : Step(37): len = 183438, overlap = 1195.59
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.45584e-06
+PHY-3002 : Step(38): len = 187567, overlap = 1163.47
+PHY-3002 : Step(39): len = 202125, overlap = 1086.28
+PHY-3002 : Step(40): len = 209473, overlap = 1026.62
+PHY-3002 : Step(41): len = 215746, overlap = 1018.19
+PHY-3002 : Step(42): len = 217937, overlap = 1013.72
+PHY-3002 : Step(43): len = 219296, overlap = 1007.47
+PHY-3002 : Step(44): len = 219224, overlap = 979.344
+PHY-3002 : Step(45): len = 217397, overlap = 978.031
+PHY-3002 : Step(46): len = 215863, overlap = 983.219
+PHY-3002 : Step(47): len = 213060, overlap = 986.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.91167e-06
+PHY-3002 : Step(48): len = 221865, overlap = 988.781
+PHY-3002 : Step(49): len = 238590, overlap = 931.844
+PHY-3002 : Step(50): len = 249034, overlap = 881.719
+PHY-3002 : Step(51): len = 256889, overlap = 841.625
+PHY-3002 : Step(52): len = 261593, overlap = 827.312
+PHY-3002 : Step(53): len = 265076, overlap = 820.875
+PHY-3002 : Step(54): len = 266178, overlap = 808.406
+PHY-3002 : Step(55): len = 265690, overlap = 818.344
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.82335e-06
+PHY-3002 : Step(56): len = 284609, overlap = 772.344
+PHY-3002 : Step(57): len = 310646, overlap = 635.375
+PHY-3002 : Step(58): len = 319794, overlap = 626.906
+PHY-3002 : Step(59): len = 323254, overlap = 592.156
+PHY-3002 : Step(60): len = 321088, overlap = 569.281
+PHY-3002 : Step(61): len = 319211, overlap = 545.469
+PHY-3002 : Step(62): len = 316135, overlap = 541.625
+PHY-3002 : Step(63): len = 314017, overlap = 540.438
+PHY-3002 : Step(64): len = 312154, overlap = 525.812
+PHY-3002 : Step(65): len = 311820, overlap = 511.688
+PHY-3002 : Step(66): len = 310740, overlap = 528.469
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.96467e-05
+PHY-3002 : Step(67): len = 332848, overlap = 473.938
+PHY-3002 : Step(68): len = 347540, overlap = 445.688
+PHY-3002 : Step(69): len = 348706, overlap = 408.562
+PHY-3002 : Step(70): len = 349971, overlap = 386.031
+PHY-3002 : Step(71): len = 349971, overlap = 373.281
+PHY-3002 : Step(72): len = 351120, overlap = 364.219
+PHY-3002 : Step(73): len = 349552, overlap = 353.312
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.92934e-05
+PHY-3002 : Step(74): len = 370328, overlap = 352.312
+PHY-3002 : Step(75): len = 384585, overlap = 336.156
+PHY-3002 : Step(76): len = 383045, overlap = 314.375
+PHY-3002 : Step(77): len = 385767, overlap = 296.969
+PHY-3002 : Step(78): len = 388795, overlap = 278.875
+PHY-3002 : Step(79): len = 391449, overlap = 267.25
+PHY-3002 : Step(80): len = 390271, overlap = 269.688
+PHY-3002 : Step(81): len = 390297, overlap = 281.438
+PHY-3002 : Step(82): len = 391648, overlap = 299.594
+PHY-3002 : Step(83): len = 392336, overlap = 303.656
+PHY-3002 : Step(84): len = 391709, overlap = 299.844
+PHY-3002 : Step(85): len = 390439, overlap = 306.281
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.85868e-05
+PHY-3002 : Step(86): len = 408046, overlap = 292.75
+PHY-3002 : Step(87): len = 422679, overlap = 277.594
+PHY-3002 : Step(88): len = 422584, overlap = 255.969
+PHY-3002 : Step(89): len = 425160, overlap = 253.656
+PHY-3002 : Step(90): len = 429218, overlap = 236.406
+PHY-3002 : Step(91): len = 432189, overlap = 222.844
+PHY-3002 : Step(92): len = 428667, overlap = 234.406
+PHY-3002 : Step(93): len = 429455, overlap = 236.594
+PHY-3002 : Step(94): len = 430523, overlap = 234.844
+PHY-3002 : Step(95): len = 431236, overlap = 243.969
+PHY-3002 : Step(96): len = 428398, overlap = 239.594
+PHY-3002 : Step(97): len = 428179, overlap = 250.594
+PHY-3002 : Step(98): len = 429304, overlap = 240.625
+PHY-3002 : Step(99): len = 430691, overlap = 229.875
+PHY-3002 : Step(100): len = 429039, overlap = 217.312
+PHY-3002 : Step(101): len = 429220, overlap = 205.594
+PHY-3002 : Step(102): len = 430065, overlap = 198.438
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000157174
+PHY-3002 : Step(103): len = 443911, overlap = 196.219
+PHY-3002 : Step(104): len = 453873, overlap = 198.688
+PHY-3002 : Step(105): len = 453919, overlap = 202.938
+PHY-3002 : Step(106): len = 456357, overlap = 213.406
+PHY-3002 : Step(107): len = 459514, overlap = 226.375
+PHY-3002 : Step(108): len = 462967, overlap = 224.562
+PHY-3002 : Step(109): len = 463925, overlap = 219.938
+PHY-3002 : Step(110): len = 465289, overlap = 201.531
+PHY-3002 : Step(111): len = 464896, overlap = 200.031
+PHY-3002 : Step(112): len = 464878, overlap = 198.781
+PHY-3002 : Step(113): len = 464551, overlap = 197.25
+PHY-3002 : Step(114): len = 464647, overlap = 181.188
+PHY-3002 : Step(115): len = 465045, overlap = 186.562
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000314347
+PHY-3002 : Step(116): len = 473188, overlap = 193.062
+PHY-3002 : Step(117): len = 480236, overlap = 200.438
+PHY-3002 : Step(118): len = 481334, overlap = 193
+PHY-3002 : Step(119): len = 482671, overlap = 194.594
+PHY-3002 : Step(120): len = 484325, overlap = 189.812
+PHY-3002 : Step(121): len = 486797, overlap = 191.125
+PHY-3002 : Step(122): len = 487747, overlap = 185.562
+PHY-3002 : Step(123): len = 490599, overlap = 181.469
+PHY-3002 : Step(124): len = 493039, overlap = 173.344
+PHY-3002 : Step(125): len = 494892, overlap = 167.281
+PHY-3002 : Step(126): len = 493577, overlap = 167.938
+PHY-3002 : Step(127): len = 493634, overlap = 159.375
+PHY-3002 : Step(128): len = 494707, overlap = 157.781
+PHY-3002 : Step(129): len = 495288, overlap = 155.594
+PHY-3002 : Step(130): len = 494119, overlap = 157.438
+PHY-3002 : Step(131): len = 493506, overlap = 154.844
+PHY-3002 : Step(132): len = 494032, overlap = 155.438
+PHY-3002 : Step(133): len = 494971, overlap = 152.875
+PHY-3002 : Step(134): len = 494030, overlap = 150.906
+PHY-3002 : Step(135): len = 493749, overlap = 150.344
+PHY-3002 : Step(136): len = 493778, overlap = 150.562
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000625949
+PHY-3002 : Step(137): len = 499548, overlap = 151.125
+PHY-3002 : Step(138): len = 507024, overlap = 150.438
+PHY-3002 : Step(139): len = 508226, overlap = 143.188
+PHY-3002 : Step(140): len = 509787, overlap = 144.375
+PHY-3002 : Step(141): len = 511941, overlap = 136.188
+PHY-3002 : Step(142): len = 513457, overlap = 126.531
+PHY-3002 : Step(143): len = 512923, overlap = 129.344
+PHY-3002 : Step(144): len = 512942, overlap = 131.219
+PHY-3002 : Step(145): len = 514283, overlap = 130.25
+PHY-3002 : Step(146): len = 515709, overlap = 130.844
+PHY-3002 : Step(147): len = 516275, overlap = 126.906
+PHY-3002 : Step(148): len = 517121, overlap = 126.781
+PHY-3002 : Step(149): len = 517671, overlap = 123.844
+PHY-3002 : Step(150): len = 517915, overlap = 124.531
+PHY-3002 : Step(151): len = 517461, overlap = 131.406
+PHY-3002 : Step(152): len = 517470, overlap = 128.719
+PHY-3002 : Step(153): len = 518073, overlap = 130.219
+PHY-3002 : Step(154): len = 518187, overlap = 130.625
+PHY-3002 : Step(155): len = 517304, overlap = 133.719
+PHY-3002 : Step(156): len = 517049, overlap = 138.812
+PHY-3002 : Step(157): len = 517330, overlap = 135.219
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00118602
+PHY-3002 : Step(158): len = 520915, overlap = 141.344
+PHY-3002 : Step(159): len = 525421, overlap = 143.281
+PHY-3002 : Step(160): len = 526739, overlap = 138.094
+PHY-3002 : Step(161): len = 527619, overlap = 127.25
+PHY-3002 : Step(162): len = 528659, overlap = 131.219
+PHY-3002 : Step(163): len = 529445, overlap = 131.562
+PHY-3002 : Step(164): len = 529830, overlap = 132.531
+PHY-3002 : Step(165): len = 530146, overlap = 133.625
+PHY-3002 : Step(166): len = 530736, overlap = 136.625
+PHY-3002 : Step(167): len = 531327, overlap = 136.688
+PHY-3002 : Step(168): len = 531268, overlap = 135.219
+PHY-3002 : Step(169): len = 531406, overlap = 135.438
+PHY-3002 : Step(170): len = 531693, overlap = 135.562
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00206061
+PHY-3002 : Step(171): len = 533107, overlap = 135.625
+PHY-3002 : Step(172): len = 536271, overlap = 139.875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.011971s wall, 0.000000s user + 0.046875s system = 0.046875s CPU (391.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 718328, over cnt = 1662(4%), over = 7669, worst = 33
+PHY-1001 : End global iterations;  0.749806s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (122.9%)
+
+PHY-1001 : Congestion index: top1 = 87.16, top5 = 64.22, top10 = 54.12, top15 = 47.80.
+PHY-3001 : End congestion estimation;  0.972002s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (117.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.893704s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (101.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.35256e-05
+PHY-3002 : Step(173): len = 660051, overlap = 74.4688
+PHY-3002 : Step(174): len = 670217, overlap = 78.2812
+PHY-3002 : Step(175): len = 667628, overlap = 76.9062
+PHY-3002 : Step(176): len = 663068, overlap = 76.1875
+PHY-3002 : Step(177): len = 661496, overlap = 79.3125
+PHY-3002 : Step(178): len = 667356, overlap = 76.7188
+PHY-3002 : Step(179): len = 678080, overlap = 71.2812
+PHY-3002 : Step(180): len = 683975, overlap = 79.1562
+PHY-3002 : Step(181): len = 685686, overlap = 86.125
+PHY-3002 : Step(182): len = 687615, overlap = 86.0312
+PHY-3002 : Step(183): len = 689660, overlap = 90.125
+PHY-3002 : Step(184): len = 692675, overlap = 94.2188
+PHY-3002 : Step(185): len = 698147, overlap = 100.031
+PHY-3002 : Step(186): len = 700300, overlap = 94.2812
+PHY-3002 : Step(187): len = 701332, overlap = 83.0625
+PHY-3002 : Step(188): len = 701042, overlap = 81.3438
+PHY-3002 : Step(189): len = 703288, overlap = 83.75
+PHY-3002 : Step(190): len = 705930, overlap = 82.25
+PHY-3002 : Step(191): len = 705892, overlap = 84.5
+PHY-3002 : Step(192): len = 704792, overlap = 81.2188
+PHY-3002 : Step(193): len = 703774, overlap = 77.0312
+PHY-3002 : Step(194): len = 702077, overlap = 77.125
+PHY-3002 : Step(195): len = 702047, overlap = 72.5625
+PHY-3002 : Step(196): len = 701006, overlap = 69.8438
+PHY-3002 : Step(197): len = 699682, overlap = 68.6875
+PHY-3002 : Step(198): len = 698801, overlap = 71.9688
+PHY-3002 : Step(199): len = 696698, overlap = 71.9062
+PHY-3002 : Step(200): len = 695104, overlap = 69.7812
+PHY-3002 : Step(201): len = 694017, overlap = 69.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000187051
+PHY-3002 : Step(202): len = 695550, overlap = 69.6562
+PHY-3002 : Step(203): len = 697983, overlap = 70.6562
+PHY-3002 : Step(204): len = 700079, overlap = 71.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 60/20917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 777416, over cnt = 2810(7%), over = 13830, worst = 65
+PHY-1001 : End global iterations;  1.556202s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (132.5%)
+
+PHY-1001 : Congestion index: top1 = 101.57, top5 = 77.15, top10 = 65.94, top15 = 59.45.
+PHY-3001 : End congestion estimation;  1.830563s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (128.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.887142s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.78661e-05
+PHY-3002 : Step(205): len = 700838, overlap = 312.406
+PHY-3002 : Step(206): len = 706286, overlap = 274.312
+PHY-3002 : Step(207): len = 705768, overlap = 243.406
+PHY-3002 : Step(208): len = 704775, overlap = 222.438
+PHY-3002 : Step(209): len = 702941, overlap = 209.031
+PHY-3002 : Step(210): len = 704110, overlap = 192.812
+PHY-3002 : Step(211): len = 702316, overlap = 189.219
+PHY-3002 : Step(212): len = 700489, overlap = 192.906
+PHY-3002 : Step(213): len = 698452, overlap = 185.844
+PHY-3002 : Step(214): len = 697121, overlap = 187.906
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000155732
+PHY-3002 : Step(215): len = 696813, overlap = 178.656
+PHY-3002 : Step(216): len = 698514, overlap = 169.281
+PHY-3002 : Step(217): len = 700332, overlap = 158.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000311464
+PHY-3002 : Step(218): len = 704540, overlap = 150.094
+PHY-3002 : Step(219): len = 714819, overlap = 133.875
+PHY-3002 : Step(220): len = 718816, overlap = 129.938
+PHY-3002 : Step(221): len = 720153, overlap = 125.094
+PHY-3002 : Step(222): len = 721767, overlap = 120.969
+PHY-3002 : Step(223): len = 721669, overlap = 116.281
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87317, tnet num: 20739, tinst num: 18337, tnode num: 119372, tedge num: 139886.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.466011s wall, 1.359375s user + 0.109375s system = 1.468750s CPU (100.2%)
+
+RUN-1004 : used memory is 585 MB, reserved memory is 574 MB, peak memory is 726 MB
+OPT-1001 : Total overflow 503.31 peak overflow 3.66
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1478/20917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812048, over cnt = 3181(9%), over = 12433, worst = 37
+PHY-1001 : End global iterations;  1.117481s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (138.4%)
+
+PHY-1001 : Congestion index: top1 = 82.16, top5 = 65.71, top10 = 58.16, top15 = 53.89.
+PHY-1001 : End incremental global routing;  1.440689s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (129.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.926376s wall, 0.890625s user + 0.046875s system = 0.937500s CPU (101.2%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18201 has valid locations, 337 needs to be replaced
+PHY-3001 : design contains 18623 instances, 7518 luts, 9884 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6675 pins
+PHY-3001 : Found 3513 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 742552
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17122/21203.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 824552, over cnt = 3194(9%), over = 12494, worst = 37
+PHY-1001 : End global iterations;  0.223610s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (160.7%)
+
+PHY-1001 : Congestion index: top1 = 82.05, top5 = 66.01, top10 = 58.53, top15 = 54.21.
+PHY-3001 : End congestion estimation;  0.475128s wall, 0.593750s user + 0.015625s system = 0.609375s CPU (128.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88482, tnet num: 21025, tinst num: 18623, tnode num: 121100, tedge num: 141644.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.464422s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (99.2%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 641 MB, peak memory is 728 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21025 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.424815s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(224): len = 741486, overlap = 1.25
+PHY-3002 : Step(225): len = 741160, overlap = 1.21875
+PHY-3002 : Step(226): len = 740836, overlap = 1.21875
+PHY-3002 : Step(227): len = 740448, overlap = 1.21875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17210/21203.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 821568, over cnt = 3215(9%), over = 12562, worst = 37
+PHY-1001 : End global iterations;  0.194540s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.4%)
+
+PHY-1001 : Congestion index: top1 = 82.18, top5 = 66.17, top10 = 58.73, top15 = 54.40.
+PHY-3001 : End congestion estimation;  0.450173s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21025 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.931709s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000261787
+PHY-3002 : Step(228): len = 740488, overlap = 119
+PHY-3002 : Step(229): len = 740573, overlap = 119.375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000523574
+PHY-3002 : Step(230): len = 740804, overlap = 119.781
+PHY-3002 : Step(231): len = 741059, overlap = 119.844
+PHY-3001 : Final: Len = 741059, Over = 119.844
+PHY-3001 : End incremental placement;  4.943498s wall, 5.234375s user + 0.187500s system = 5.421875s CPU (109.7%)
+
+OPT-1001 : Total overflow 509.72 peak overflow 3.66
+OPT-1001 : End high-fanout net optimization;  7.852177s wall, 8.562500s user + 0.250000s system = 8.812500s CPU (112.2%)
+
+OPT-1001 : Current memory(MB): used = 731, reserve = 725, peak = 748.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17186/21203.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826568, over cnt = 3195(9%), over = 11662, worst = 37
+PHY-1002 : len = 885096, over cnt = 2386(6%), over = 6227, worst = 26
+PHY-1002 : len = 938528, over cnt = 1046(2%), over = 2161, worst = 17
+PHY-1002 : len = 965376, over cnt = 259(0%), over = 551, worst = 17
+PHY-1002 : len = 976584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.096792s wall, 2.921875s user + 0.015625s system = 2.937500s CPU (140.1%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 58.02, top10 = 53.89, top15 = 51.29.
+OPT-1001 : End congestion update;  2.356301s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (135.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21025 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.835219s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.2%)
+
+OPT-0007 : Start: WNS -1018 TNS -1652 NUM_FEPS 4
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1652 NUM_FEPS 4 with 49 cells processed and 8166 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1652 NUM_FEPS 4 with 40 cells processed and 2366 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1652 NUM_FEPS 4 with 24 cells processed and 2100 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1652 NUM_FEPS 4 with 14 cells processed and 684 slack improved
+OPT-1001 : End global optimization;  3.237732s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (126.0%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 703, peak = 748.
+OPT-1001 : End physical optimization;  13.308206s wall, 14.828125s user + 0.390625s system = 15.218750s CPU (114.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7518 LUT to BLE ...
+SYN-4008 : Packed 7518 LUT and 3153 SEQ to BLE.
+SYN-4003 : Packing 6731 remaining SEQ's ...
+SYN-4005 : Packed 3956 SEQ with LUT/SLICE
+SYN-4006 : 718 single LUT's are left
+SYN-4006 : 2775 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10293/14024 primitive instances ...
+PHY-3001 : End packing;  1.708573s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (100.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7027 instances
+RUN-1001 : 3439 mslices, 3440 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18177 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10662 nets have 2 pins
+RUN-1001 : 5690 nets have [3 - 5] pins
+RUN-1001 : 1151 nets have [6 - 10] pins
+RUN-1001 : 303 nets have [11 - 20] pins
+RUN-1001 : 339 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 7025 instances, 6879 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3843 pins
+PHY-3001 : Found 1562 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 749469, Over = 319.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7753/18177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910704, over cnt = 2092(5%), over = 3487, worst = 8
+PHY-1002 : len = 917864, over cnt = 1498(4%), over = 2197, worst = 8
+PHY-1002 : len = 929488, over cnt = 823(2%), over = 1183, worst = 8
+PHY-1002 : len = 942080, over cnt = 275(0%), over = 389, worst = 6
+PHY-1002 : len = 948992, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations;  1.688470s wall, 2.281250s user + 0.046875s system = 2.328125s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 64.78, top5 = 56.84, top10 = 52.36, top15 = 49.55.
+PHY-3001 : End congestion estimation;  2.065944s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (130.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75395, tnet num: 17999, tinst num: 7025, tnode num: 98877, tedge num: 126284.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.626127s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (99.9%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 624 MB, peak memory is 748 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.551942s wall, 2.515625s user + 0.031250s system = 2.546875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.1931e-05
+PHY-3002 : Step(232): len = 738712, overlap = 310
+PHY-3002 : Step(233): len = 732064, overlap = 309
+PHY-3002 : Step(234): len = 726939, overlap = 312.75
+PHY-3002 : Step(235): len = 721971, overlap = 312.5
+PHY-3002 : Step(236): len = 718404, overlap = 308.75
+PHY-3002 : Step(237): len = 715317, overlap = 316.75
+PHY-3002 : Step(238): len = 712496, overlap = 314.75
+PHY-3002 : Step(239): len = 710941, overlap = 310.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.3862e-05
+PHY-3002 : Step(240): len = 712635, overlap = 301.5
+PHY-3002 : Step(241): len = 716409, overlap = 287.75
+PHY-3002 : Step(242): len = 717552, overlap = 285.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000167724
+PHY-3002 : Step(243): len = 724872, overlap = 273.75
+PHY-3002 : Step(244): len = 736265, overlap = 257.25
+PHY-3002 : Step(245): len = 736204, overlap = 259
+PHY-3002 : Step(246): len = 735386, overlap = 255
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.339535s wall, 0.312500s user + 0.359375s system = 0.671875s CPU (197.9%)
+
+PHY-3001 : Trial Legalized: Len = 972335
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 740/18177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09007e+06, over cnt = 2939(8%), over = 5133, worst = 8
+PHY-1002 : len = 1.11073e+06, over cnt = 1912(5%), over = 2790, worst = 8
+PHY-1002 : len = 1.13443e+06, over cnt = 773(2%), over = 1042, worst = 7
+PHY-1002 : len = 1.14656e+06, over cnt = 253(0%), over = 333, worst = 6
+PHY-1002 : len = 1.15339e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1001 : End global iterations;  2.801687s wall, 3.734375s user + 0.031250s system = 3.765625s CPU (134.4%)
+
+PHY-1001 : Congestion index: top1 = 70.00, top5 = 62.79, top10 = 58.22, top15 = 55.46.
+PHY-3001 : End congestion estimation;  3.236532s wall, 4.171875s user + 0.031250s system = 4.203125s CPU (129.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.886683s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000172827
+PHY-3002 : Step(247): len = 923580, overlap = 88.25
+PHY-3002 : Step(248): len = 897748, overlap = 117.25
+PHY-3002 : Step(249): len = 878285, overlap = 143.5
+PHY-3002 : Step(250): len = 865920, overlap = 160.75
+PHY-3002 : Step(251): len = 853664, overlap = 180.75
+PHY-3002 : Step(252): len = 845053, overlap = 192.75
+PHY-3002 : Step(253): len = 836284, overlap = 201.5
+PHY-3002 : Step(254): len = 829979, overlap = 212
+PHY-3002 : Step(255): len = 824449, overlap = 219.75
+PHY-3002 : Step(256): len = 818826, overlap = 227.25
+PHY-3002 : Step(257): len = 815436, overlap = 227.5
+PHY-3002 : Step(258): len = 812104, overlap = 227.25
+PHY-3002 : Step(259): len = 808876, overlap = 227.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000344134
+PHY-3002 : Step(260): len = 815051, overlap = 221
+PHY-3002 : Step(261): len = 817636, overlap = 218.75
+PHY-3002 : Step(262): len = 819614, overlap = 210.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000556809
+PHY-3002 : Step(263): len = 824528, overlap = 207.25
+PHY-3002 : Step(264): len = 830029, overlap = 201
+PHY-3002 : Step(265): len = 832174, overlap = 197.25
+PHY-3002 : Step(266): len = 833995, overlap = 190.5
+PHY-3002 : Step(267): len = 835125, overlap = 188.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.090666s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (103.4%)
+
+PHY-3001 : Legalized: Len = 926939, Over = 0
+PHY-3001 : Spreading special nets. 496 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.131755s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.9%)
+
+PHY-3001 : 759 instances has been re-located, deltaX = 353, deltaY = 483, maxDist = 8.
+PHY-3001 : Final: Len = 940093, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75395, tnet num: 17999, tinst num: 7028, tnode num: 98877, tedge num: 126284.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.981569s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (99.4%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 651 MB, peak memory is 748 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 2411/18177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06378e+06, over cnt = 2799(7%), over = 4749, worst = 7
+PHY-1002 : len = 1.08239e+06, over cnt = 1723(4%), over = 2489, worst = 6
+PHY-1002 : len = 1.10284e+06, over cnt = 667(1%), over = 936, worst = 6
+PHY-1002 : len = 1.11923e+06, over cnt = 80(0%), over = 97, worst = 6
+PHY-1002 : len = 1.12097e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations;  2.358651s wall, 3.359375s user + 0.046875s system = 3.406250s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 67.39, top5 = 60.02, top10 = 55.88, top15 = 53.20.
+PHY-1001 : End incremental global routing;  2.776704s wall, 3.781250s user + 0.046875s system = 3.828125s CPU (137.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.056274s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (97.6%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6934 has valid locations, 32 needs to be replaced
+PHY-3001 : design contains 7054 instances, 6905 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3925 pins
+PHY-3001 : Found 1565 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 943203
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16668/18221.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12431e+06, over cnt = 91(0%), over = 98, worst = 3
+PHY-1002 : len = 1.12406e+06, over cnt = 54(0%), over = 56, worst = 2
+PHY-1002 : len = 1.12439e+06, over cnt = 32(0%), over = 33, worst = 2
+PHY-1002 : len = 1.12472e+06, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 1.12512e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.787398s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 67.37, top5 = 60.09, top10 = 55.93, top15 = 53.23.
+PHY-3001 : End congestion estimation;  1.099361s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (102.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75637, tnet num: 18043, tinst num: 7054, tnode num: 99196, tedge num: 126638.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.879290s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (99.8%)
+
+RUN-1004 : used memory is 681 MB, reserved memory is 681 MB, peak memory is 748 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.771985s wall, 2.750000s user + 0.015625s system = 2.765625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(268): len = 942591, overlap = 0.5
+PHY-3002 : Step(269): len = 942350, overlap = 1.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16660/18221.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12371e+06, over cnt = 87(0%), over = 103, worst = 6
+PHY-1002 : len = 1.12378e+06, over cnt = 42(0%), over = 42, worst = 1
+PHY-1002 : len = 1.12417e+06, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 1.12422e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.12439e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.785714s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (105.4%)
+
+PHY-1001 : Congestion index: top1 = 67.37, top5 = 60.06, top10 = 55.96, top15 = 53.27.
+PHY-3001 : End congestion estimation;  1.098166s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (102.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.864499s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000228551
+PHY-3002 : Step(270): len = 942283, overlap = 2.5
+PHY-3002 : Step(271): len = 942253, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005631s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (277.5%)
+
+PHY-3001 : Legalized: Len = 942339, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060338s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.6%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 6, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 942413, Over = 0
+PHY-3001 : End incremental placement;  6.322814s wall, 6.328125s user + 0.062500s system = 6.390625s CPU (101.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.687750s wall, 11.687500s user + 0.109375s system = 11.796875s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 756, peak = 760.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16615/18221.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.1242e+06, over cnt = 87(0%), over = 95, worst = 3
+PHY-1002 : len = 1.12406e+06, over cnt = 49(0%), over = 52, worst = 2
+PHY-1002 : len = 1.12443e+06, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 1.12468e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.12478e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.811007s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 67.31, top5 = 60.04, top10 = 55.90, top15 = 53.23.
+OPT-1001 : End congestion update;  1.121557s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (105.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.728876s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.8%)
+
+OPT-0007 : Start: WNS -1183 TNS -1887 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6966 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7054 instances, 6905 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3925 pins
+PHY-3001 : Found 1565 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 945675, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.074246s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (105.2%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 28, deltaY = 15, maxDist = 4.
+PHY-3001 : Final: Len = 946491, Over = 0
+PHY-3001 : End incremental legalization;  0.456145s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.3%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 29 cells processed and 8488 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6966 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7054 instances, 6905 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3925 pins
+PHY-3001 : Found 1565 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 950309, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063419s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.6%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 17, deltaY = 16, maxDist = 4.
+PHY-3001 : Final: Len = 950655, Over = 0
+PHY-3001 : End incremental legalization;  0.396983s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.3%)
+
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 25 cells processed and 4993 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6966 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7054 instances, 6905 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3925 pins
+PHY-3001 : Found 1565 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 952243, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.066075s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.6%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 9, deltaY = 17, maxDist = 4.
+PHY-3001 : Final: Len = 952539, Over = 0
+PHY-3001 : End incremental legalization;  0.429325s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (101.9%)
+
+OPT-0007 : Iter 3: improved WNS -983 TNS -1518 NUM_FEPS 2 with 14 cells processed and 2801 slack improved
+OPT-0007 : Iter 4: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  3.583437s wall, 3.609375s user + 0.031250s system = 3.640625s CPU (101.6%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 757, peak = 760.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.734973s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (102.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16393/18221.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.13538e+06, over cnt = 217(0%), over = 257, worst = 4
+PHY-1002 : len = 1.13481e+06, over cnt = 156(0%), over = 174, worst = 4
+PHY-1002 : len = 1.13546e+06, over cnt = 72(0%), over = 77, worst = 3
+PHY-1002 : len = 1.1364e+06, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 1.13667e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.920076s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (112.1%)
+
+PHY-1001 : Congestion index: top1 = 66.59, top5 = 59.72, top10 = 55.93, top15 = 53.41.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.917461s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1183 TNS -1818 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 66.137931
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1183ps with logic level 2 
+RUN-1001 :       #2 path slack -1097ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 18221 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 18221 nets
+OPT-1001 : End physical optimization;  19.535154s wall, 20.625000s user + 0.171875s system = 20.796875s CPU (106.5%)
+
+RUN-1003 : finish command "place" in  60.753443s wall, 86.875000s user + 5.359375s system = 92.234375s CPU (151.8%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 635 MB, peak memory is 760 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.718730s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (173.6%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 636 MB, peak memory is 760 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7056 instances
+RUN-1001 : 3460 mslices, 3445 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18221 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10678 nets have 2 pins
+RUN-1001 : 5695 nets have [3 - 5] pins
+RUN-1001 : 1155 nets have [6 - 10] pins
+RUN-1001 : 310 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75637, tnet num: 18043, tinst num: 7054, tnode num: 99196, tedge num: 126638.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.610945s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.9%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 622 MB, peak memory is 760 MB
+PHY-1001 : 3460 mslices, 3445 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06119e+06, over cnt = 2978(8%), over = 5046, worst = 7
+PHY-1002 : len = 1.07814e+06, over cnt = 2006(5%), over = 3015, worst = 7
+PHY-1002 : len = 1.10678e+06, over cnt = 668(1%), over = 945, worst = 5
+PHY-1002 : len = 1.12278e+06, over cnt = 24(0%), over = 25, worst = 2
+PHY-1002 : len = 1.12367e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.261658s wall, 4.046875s user + 0.046875s system = 4.093750s CPU (125.5%)
+
+PHY-1001 : Congestion index: top1 = 65.65, top5 = 59.46, top10 = 55.69, top15 = 53.18.
+PHY-1001 : End global routing;  3.590421s wall, 4.375000s user + 0.046875s system = 4.421875s CPU (123.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 725, reserve = 734, peak = 760.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 998, reserve = 1004, peak = 998.
+PHY-1001 : End build detailed router design. 3.928917s wall, 3.875000s user + 0.046875s system = 3.921875s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 262112, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.853739s wall, 4.859375s user + 0.000000s system = 4.859375s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 262168, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.469598s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1034, reserve = 1041, peak = 1034.
+PHY-1001 : End phase 1; 5.334873s wall, 5.328125s user + 0.000000s system = 5.328125s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.56792e+06, over cnt = 2334(0%), over = 2340, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1055, reserve = 1061, peak = 1055.
+PHY-1001 : End initial routed; 47.828926s wall, 76.375000s user + 0.562500s system = 76.937500s CPU (160.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17144(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.117   |  -4.021   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.445723s wall, 3.406250s user + 0.031250s system = 3.437500s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1060, reserve = 1071, peak = 1060.
+PHY-1001 : End phase 2; 51.274717s wall, 79.781250s user + 0.609375s system = 80.390625s CPU (156.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.994ns STNS -3.898ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.135869s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.0%)
+
+PHY-1022 : len = 2.56794e+06, over cnt = 2336(0%), over = 2342, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.397378s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.5228e+06, over cnt = 975(0%), over = 975, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 3.220071s wall, 4.343750s user + 0.000000s system = 4.343750s CPU (134.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.51933e+06, over cnt = 302(0%), over = 302, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.497743s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (147.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.52206e+06, over cnt = 77(0%), over = 77, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.613138s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (112.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.52358e+06, over cnt = 12(0%), over = 12, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.538278s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (110.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.52387e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.373067s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.52387e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.446742s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.52387e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.867093s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.52386e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.180685s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.52386e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.175127s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.203816s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.195297s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.0%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.229869s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.2%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.172758s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.196735s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.181601s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.193520s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.236317s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.347676s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (103.4%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.171731s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (118.3%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.172532s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.180319s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (112.6%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.192528s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.231351s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.348376s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.971922s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.168867s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.166041s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.187631s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.199592s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.229363s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.341565s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (96.1%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.926272s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.924331s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.173870s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.168745s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.184593s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.199039s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.1%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.235416s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.334653s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.123865s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.931939s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.949233s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.174207s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.6%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.172570s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.194381s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.5%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.202636s wall, 0.234375s user + 0.031250s system = 0.265625s CPU (131.1%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.227983s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.341222s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.960939s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.949506s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.899040s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.909187s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.171123s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.168786s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.178678s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.192866s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (129.6%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.228540s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.7%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.349553s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.956663s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.183029s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.933115s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.922858s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.932963s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.170019s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (119.5%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.169795s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.186404s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.213434s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.234315s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (106.7%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.353127s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.944496s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.945478s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.923092s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.950180s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.945649s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.165695s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17144(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.994   |  -3.898   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.320375s wall, 3.281250s user + 0.046875s system = 3.328125s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1063, reserve = 1075, peak = 1067.
+PHY-1001 : End phase 3; 42.191400s wall, 44.140625s user + 0.203125s system = 44.343750s CPU (105.1%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.994ns STNS -3.898ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.140579s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.0%)
+
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.387206s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.994ns, -3.898ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.167869s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.176756s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.206789s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.170284s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 5 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.166417s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.9%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.180740s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.225960s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.231668s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.2%)
+
+PHY-1001 : ===== DR Iter 9 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.548247s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (31.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.176089s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.187380s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.192171s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.229353s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.360440s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 15 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.171140s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.170402s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.182789s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (119.7%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.214539s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (94.7%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.233584s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.352928s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 1.118310s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.6%)
+
+PHY-1001 : ===== DR Iter 22 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.176470s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.170780s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.182408s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.194535s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.230836s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.337013s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.952029s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.946913s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 30 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.201047s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.166866s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (121.7%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.186894s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.195874s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.234647s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.335944s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.909474s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.930983s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.942239s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 39 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.169977s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.173006s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (144.5%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.179023s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.191507s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.228732s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.346214s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.931977s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.089651s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.918692s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.001717s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 49 =====
+PHY-1022 : len = 2.52391e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.169823s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.168755s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.6%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.181295s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (112.0%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.193861s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.233018s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.343100s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.926851s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.938603s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.939808s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.914492s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.966570s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 60 =====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.168717s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (120.4%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.163921s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.180064s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.5%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.193164s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (113.2%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.236076s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.419940s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 1.015695s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.912122s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.947951s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.915396s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.933858s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.5239e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.942176s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17144(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.994   |  -3.898   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.330373s wall, 3.328125s user + 0.015625s system = 3.343750s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1061, reserve = 1075, peak = 1068.
+PHY-1001 : End phase 4; 35.009688s wall, 34.671875s user + 0.156250s system = 34.828125s CPU (99.5%)
+
+PHY-1003 : Routed, final wirelength = 2.5239e+06
+PHY-1001 : 736 feed throughs used by 545 nets
+PHY-1001 : Current memory(MB): used = 1171, reserve = 1188, peak = 1171.
+PHY-1001 : End export database. 3.332808s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (73.1%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7056 instances
+RUN-1001 : 3460 mslices, 3445 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18221 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10678 nets have 2 pins
+RUN-1001 : 5695 nets have [3 - 5] pins
+RUN-1001 : 1155 nets have [6 - 10] pins
+RUN-1001 : 310 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |      0      
+RUN-1001 :   No   |  No   |  Yes  |      0      
+RUN-1001 :   No   |  Yes  |  No   |      0      
+RUN-1001 :   Yes  |  No   |  No   |      0      
+RUN-1001 :   Yes  |  No   |  Yes  |      0      
+RUN-1001 :   Yes  |  Yes  |  No   |      0      
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    10   |   1   |     1      
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 18 0) is for feedthrough
+PHY-3001 : eco cells: (1 25 0) is for feedthrough
+PHY-3001 : eco cells: (2 8 0) is for feedthrough
+PHY-3001 : eco cells: (2 36 2) is for feedthrough
+PHY-3001 : eco cells: (2 40 3) is for feedthrough
+PHY-3001 : eco cells: (2 48 2) is for feedthrough
+PHY-3001 : eco cells: (3 5 0) is for feedthrough
+PHY-3001 : eco cells: (3 13 1) is for feedthrough
+PHY-3001 : eco cells: (3 38 0) is for feedthrough
+PHY-3001 : eco cells: (3 39 2) is for feedthrough
+PHY-3001 : eco cells: (3 41 1) is for feedthrough
+PHY-3001 : eco cells: (3 46 0) is for feedthrough
+PHY-3001 : eco cells: (3 49 0) is for feedthrough
+PHY-3001 : eco cells: (3 52 1) is for feedthrough
+PHY-3001 : eco cells: (3 68 1) is for feedthrough
+PHY-3001 : eco cells: (4 10 0) is for feedthrough
+PHY-3001 : eco cells: (4 10 1) is for feedthrough
+PHY-3001 : eco cells: (4 11 1) is for feedthrough
+PHY-3001 : eco cells: (4 12 2) is for feedthrough
+PHY-3001 : eco cells: (4 12 3) is for feedthrough
+PHY-3001 : eco cells: (4 24 1) is for feedthrough
+PHY-3001 : eco cells: (4 36 1) is for feedthrough
+PHY-3001 : eco cells: (4 37 3) is for feedthrough
+PHY-3001 : eco cells: (4 41 2) is for feedthrough
+PHY-3001 : eco cells: (4 47 1) is for feedthrough
+PHY-3001 : eco cells: (4 50 0) is for feedthrough
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+PHY-3001 : eco cells: (27 40 2) is for feedthrough
+PHY-3001 : eco cells: (27 46 0) is for feedthrough
+PHY-3001 : eco cells: (27 46 3) is for feedthrough
+PHY-3001 : eco cells: (27 47 1) is for feedthrough
+PHY-3001 : eco cells: (27 48 1) is for feedthrough
+PHY-3001 : eco cells: (27 51 1) is for feedthrough
+PHY-3001 : eco cells: (27 54 3) is for feedthrough
+PHY-3001 : eco cells: (27 56 2) is for feedthrough
+PHY-3001 : eco cells: (27 59 0) is for feedthrough
+PHY-3001 : eco cells: (27 60 1) is for feedthrough
+PHY-3001 : eco cells: (27 60 3) is for feedthrough
+PHY-3001 : eco cells: (28 1 0) is for feedthrough
+PHY-3001 : eco cells: (28 2 1) is for feedthrough
+PHY-3001 : eco cells: (28 3 2) is for feedthrough
+PHY-3001 : eco cells: (28 5 2) is for feedthrough
+PHY-3001 : eco cells: (28 7 0) is for feedthrough
+PHY-3001 : eco cells: (28 7 3) is for feedthrough
+PHY-3001 : eco cells: (28 9 2) is for feedthrough
+PHY-3001 : eco cells: (28 12 0) is for feedthrough
+PHY-3001 : eco cells: (28 12 1) is for feedthrough
+PHY-3001 : eco cells: (28 13 1) is for feedthrough
+PHY-3001 : eco cells: (28 18 1) is for feedthrough
+PHY-3001 : eco cells: (28 20 3) is for feedthrough
+PHY-3001 : eco cells: (28 21 0) is for feedthrough
+PHY-3001 : eco cells: (28 41 1) is for feedthrough
+PHY-3001 : eco cells: (28 45 1) is for feedthrough
+PHY-3001 : eco cells: (28 48 0) is for feedthrough
+PHY-3001 : eco cells: (28 49 1) is for feedthrough
+PHY-3001 : eco cells: (28 50 3) is for feedthrough
+PHY-3001 : eco cells: (28 51 3) is for feedthrough
+PHY-3001 : eco cells: (28 55 2) is for feedthrough
+PHY-3001 : eco cells: (28 60 1) is for feedthrough
+PHY-3001 : eco cells: (29 4 3) is for feedthrough
+PHY-3001 : eco cells: (29 7 3) is for feedthrough
+PHY-3001 : eco cells: (29 8 2) is for feedthrough
+PHY-3001 : eco cells: (29 8 3) is for feedthrough
+PHY-3001 : eco cells: (29 9 2) is for feedthrough
+PHY-3001 : eco cells: (29 10 3) is for feedthrough
+PHY-3001 : eco cells: (29 24 3) is for feedthrough
+PHY-3001 : eco cells: (29 26 2) is for feedthrough
+PHY-3001 : eco cells: (29 34 3) is for feedthrough
+PHY-3001 : eco cells: (29 36 1) is for feedthrough
+PHY-3001 : eco cells: (29 37 2) is for feedthrough
+PHY-3001 : eco cells: (29 44 0) is for feedthrough
+PHY-3001 : eco cells: (29 44 3) is for feedthrough
+PHY-3001 : eco cells: (29 45 3) is for feedthrough
+PHY-3001 : eco cells: (29 47 3) is for feedthrough
+PHY-3001 : eco cells: (29 51 3) is for feedthrough
+PHY-3001 : eco cells: (29 53 3) is for feedthrough
+PHY-3001 : eco cells: (29 57 3) is for feedthrough
+PHY-3001 : eco cells: (29 58 0) is for feedthrough
+PHY-3001 : eco cells: (29 69 0) is for feedthrough
+PHY-3001 : eco cells: (30 4 2) is for feedthrough
+PHY-3001 : eco cells: (30 5 1) is for feedthrough
+PHY-3001 : eco cells: (30 5 3) is for feedthrough
+PHY-3001 : eco cells: (30 6 2) is for feedthrough
+PHY-3001 : eco cells: (30 6 3) is for feedthrough
+PHY-3001 : eco cells: (30 9 2) is for feedthrough
+PHY-3001 : eco cells: (30 10 1) is for feedthrough
+PHY-3001 : eco cells: (30 11 0) is for feedthrough
+PHY-3001 : eco cells: (30 11 2) is for feedthrough
+PHY-3001 : eco cells: (30 12 1) is for feedthrough
+PHY-3001 : eco cells: (30 12 2) is for feedthrough
+PHY-3001 : eco cells: (30 14 2) is for feedthrough
+PHY-3001 : eco cells: (30 46 3) is for feedthrough
+PHY-3001 : eco cells: (30 47 2) is for feedthrough
+PHY-3001 : eco cells: (30 51 1) is for feedthrough
+PHY-3001 : eco cells: (30 53 3) is for feedthrough
+PHY-3001 : eco cells: (30 59 3) is for feedthrough
+PHY-3001 : eco cells: (30 62 2) is for feedthrough
+PHY-3001 : eco cells: (30 68 2) is for feedthrough
+PHY-3001 : eco cells: (31 2 2) is for feedthrough
+PHY-3001 : eco cells: (31 4 2) is for feedthrough
+PHY-3001 : eco cells: (31 10 0) is for feedthrough
+PHY-3001 : eco cells: (31 11 1) is for feedthrough
+PHY-3001 : eco cells: (31 11 3) is for feedthrough
+PHY-3001 : eco cells: (31 12 1) is for feedthrough
+PHY-3001 : eco cells: (31 14 2) is for feedthrough
+PHY-3001 : eco cells: (31 15 3) is for feedthrough
+PHY-3001 : eco cells: (31 17 0) is for feedthrough
+PHY-3001 : eco cells: (31 46 1) is for feedthrough
+PHY-3001 : eco cells: (31 52 0) is for feedthrough
+PHY-3001 : eco cells: (33 6 3) is for feedthrough
+PHY-3001 : eco cells: (33 10 2) is for feedthrough
+PHY-3001 : eco cells: (33 13 3) is for feedthrough
+PHY-3001 : eco cells: (33 16 1) is for feedthrough
+PHY-3001 : eco cells: (33 16 2) is for feedthrough
+PHY-3001 : eco cells: (33 20 1) is for feedthrough
+PHY-3001 : eco cells: (33 20 2) is for feedthrough
+PHY-3001 : eco cells: (33 20 3) is for feedthrough
+PHY-3001 : eco cells: (33 21 3) is for feedthrough
+PHY-3001 : eco cells: (33 49 1) is for feedthrough
+PHY-3001 : eco cells: (33 54 3) is for feedthrough
+PHY-3001 : eco cells: (33 59 0) is for feedthrough
+PHY-3001 : eco cells: (34 1 2) is for feedthrough
+PHY-3001 : eco cells: (34 2 1) is for feedthrough
+PHY-3001 : eco cells: (34 3 0) is for feedthrough
+PHY-3001 : eco cells: (34 3 3) is for feedthrough
+PHY-3001 : eco cells: (34 5 3) is for feedthrough
+PHY-3001 : eco cells: (34 6 0) is for feedthrough
+PHY-3001 : eco cells: (34 9 1) is for feedthrough
+PHY-3001 : eco cells: (34 11 3) is for feedthrough
+PHY-3001 : eco cells: (34 12 2) is for feedthrough
+PHY-3001 : eco cells: (34 15 3) is for feedthrough
+PHY-3001 : eco cells: (34 16 3) is for feedthrough
+PHY-3001 : eco cells: (34 17 3) is for feedthrough
+PHY-3001 : eco cells: (34 20 2) is for feedthrough
+PHY-3001 : eco cells: (34 41 3) is for feedthrough
+PHY-3001 : eco cells: (34 49 1) is for feedthrough
+PHY-3001 : eco cells: (35 1 2) is for feedthrough
+PHY-3001 : eco cells: (35 2 0) is for feedthrough
+PHY-3001 : eco cells: (35 7 3) is for feedthrough
+PHY-3001 : eco cells: (35 8 2) is for feedthrough
+PHY-3001 : eco cells: (35 9 0) is for feedthrough
+PHY-3001 : eco cells: (35 10 1) is for feedthrough
+PHY-3001 : eco cells: (35 11 3) is for feedthrough
+PHY-3001 : eco cells: (35 18 3) is for feedthrough
+PHY-3001 : eco cells: (35 19 3) is for feedthrough
+PHY-3001 : eco cells: (35 21 0) is for feedthrough
+PHY-3001 : eco cells: (35 39 2) is for feedthrough
+PHY-3001 : eco cells: (35 42 1) is for feedthrough
+PHY-3001 : eco cells: (35 45 0) is for feedthrough
+PHY-3001 : eco cells: (35 45 1) is for feedthrough
+PHY-3001 : eco cells: (35 51 3) is for feedthrough
+PHY-3001 : eco cells: (36 4 3) is for feedthrough
+PHY-3001 : eco cells: (36 8 0) is for feedthrough
+PHY-3001 : eco cells: (36 8 1) is for feedthrough
+PHY-3001 : eco cells: (36 8 3) is for feedthrough
+PHY-3001 : eco cells: (36 9 2) is for feedthrough
+PHY-3001 : eco cells: (36 10 3) is for feedthrough
+PHY-3001 : eco cells: (36 11 3) is for feedthrough
+PHY-3001 : eco cells: (36 18 2) is for feedthrough
+PHY-3001 : eco cells: (36 18 3) is for feedthrough
+PHY-3001 : eco cells: (36 19 1) is for feedthrough
+PHY-3001 : eco cells: (36 21 0) is for feedthrough
+PHY-3001 : eco cells: (36 21 2) is for feedthrough
+PHY-3001 : eco cells: (36 23 1) is for feedthrough
+PHY-3001 : eco cells: (36 31 1) is for feedthrough
+PHY-3001 : eco cells: (36 42 0) is for feedthrough
+PHY-3001 : eco cells: (36 42 3) is for feedthrough
+PHY-3001 : eco cells: (36 48 3) is for feedthrough
+PHY-3001 : eco cells: (37 3 2) is for feedthrough
+PHY-3001 : eco cells: (37 10 1) is for feedthrough
+PHY-3001 : eco cells: (37 11 0) is for feedthrough
+PHY-3001 : eco cells: (37 11 1) is for feedthrough
+PHY-3001 : eco cells: (37 13 2) is for feedthrough
+PHY-3001 : eco cells: (37 13 3) is for feedthrough
+PHY-3001 : eco cells: (37 20 3) is for feedthrough
+PHY-3001 : eco cells: (37 22 1) is for feedthrough
+PHY-3001 : eco cells: (37 44 1) is for feedthrough
+PHY-3001 : eco cells: (38 1 1) is for feedthrough
+PHY-3001 : eco cells: (38 5 1) is for feedthrough
+PHY-3001 : eco cells: (38 5 2) is for feedthrough
+PHY-3001 : eco cells: (38 6 2) is for feedthrough
+PHY-3001 : eco cells: (38 7 3) is for feedthrough
+PHY-3001 : eco cells: (38 9 1) is for feedthrough
+PHY-3001 : eco cells: (38 13 1) is for feedthrough
+PHY-3001 : eco cells: (38 13 3) is for feedthrough
+PHY-3001 : eco cells: (39 4 3) is for feedthrough
+PHY-3001 : eco cells: (39 5 2) is for feedthrough
+PHY-3001 : eco cells: (39 7 0) is for feedthrough
+PHY-3001 : eco cells: (39 7 1) is for feedthrough
+PHY-3001 : eco cells: (39 10 1) is for feedthrough
+PHY-3001 : eco cells: (39 10 2) is for feedthrough
+PHY-3001 : eco cells: (39 13 0) is for feedthrough
+PHY-3001 : eco cells: (39 15 1) is for feedthrough
+PHY-3001 : eco cells: (39 16 1) is for feedthrough
+PHY-3001 : eco cells: (39 30 2) is for feedthrough
+PHY-3001 : eco cells: (39 44 0) is for feedthrough
+PHY-3001 : eco cells: (39 44 1) is for feedthrough
+PHY-3001 : eco cells: 6965 has valid locations, 1 needs to be replaced
+PHY-3001 : design contains 7054 instances, 6905 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3925 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.786834s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.3%)
+
+PHY-3001 : Found 1565 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 952945
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 70%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(272): len = 952518, overlap = 0.25
+PHY-3002 : Step(273): len = 952450, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.003657s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (427.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16689/18221.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12358e+06, over cnt = 3(0%), over = 4, worst = 2
+PHY-1002 : len = 1.12359e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.12359e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.311573s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.3%)
+
+PHY-1001 : Congestion index: top1 = 65.71, top5 = 59.45, top10 = 55.69, top15 = 53.19.
+PHY-3001 : End congestion estimation;  0.571712s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (98.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.932037s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117236
+PHY-3002 : Step(274): len = 952402, overlap = 0.25
+PHY-3002 : Step(275): len = 952394, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16689/18221.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12352e+06, over cnt = 11(0%), over = 12, worst = 2
+PHY-1002 : len = 1.12349e+06, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 1.12356e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.1236e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.432227s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.6%)
+
+PHY-1001 : Congestion index: top1 = 65.75, top5 = 59.43, top10 = 55.67, top15 = 53.16.
+PHY-3001 : End congestion estimation;  0.705263s wall, 0.687500s user + 0.015625s system = 0.703125s CPU (99.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.923396s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0009475
+PHY-3002 : Step(276): len = 952394, overlap = 0.25
+PHY-3002 : Step(277): len = 952394, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.006491s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (240.7%)
+
+PHY-3001 : Trial Legalized: Len = 952499
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16689/18221.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12371e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.096606s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (97.0%)
+
+PHY-1001 : Congestion index: top1 = 65.69, top5 = 59.40, top10 = 55.65, top15 = 53.16.
+PHY-3001 : End congestion estimation;  0.370221s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.927534s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0105786
+PHY-3002 : Step(278): len = 952499, overlap = 0
+PHY-3002 : Step(279): len = 952499, overlap = 0
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005217s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 952499, Over = 0
+PHY-3001 : End spreading;  0.057981s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.8%)
+
+PHY-3001 : Final: Len = 952499, Over = 0
+RUN-1003 : finish command "place -eco" in  5.920758s wall, 6.062500s user + 0.156250s system = 6.218750s CPU (105.0%)
+
+RUN-1004 : used memory is 1168 MB, reserved memory is 1185 MB, peak memory is 1173 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7056 instances
+RUN-1001 : 3460 mslices, 3445 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18221 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10678 nets have 2 pins
+RUN-1001 : 5695 nets have [3 - 5] pins
+RUN-1001 : 1155 nets have [6 - 10] pins
+RUN-1001 : 310 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3460 mslices, 3445 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18043 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1173, reserve = 1190, peak = 1173.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1025 : Net sys_initial_done_dup_1163 is open after eco import.
+PHY-1025 : Net sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/current_state[5]_syn_479 is open after eco import.
+PHY-1025 : Net sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/current_state[5]_syn_473 is open after eco import.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1025 : Net sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/RD_addr_i[86] is open after eco import.
+PHY-1025 : Net sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/RD_addr_i[82] is open after eco import.
+PHY-1025 : Net sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/RD_addr_i_b46[6] is open after eco import.
+PHY-1025 : Net sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/RD_addr_i_b46[2] is open after eco import.
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-5011 WARNING: x22y22_slice0_clk: 5071: is dangling
+PHY-1025 : Net u_pll/clk0_buf is open after eco import.
+PHY-1001 : eco open net = 8
+PHY-1001 : Current memory(MB): used = 1187, reserve = 1204, peak = 1187.
+PHY-1001 : End build detailed router design. 1.822127s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (99.5%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.15632e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 1.012546s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.15632e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.037090s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.15632e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.109565s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.15632e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 1.108885s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.15632e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 1.142279s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.15632e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 1.082935s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1187, reserve = 1204, peak = 1187.
+PHY-1001 : End phase 1; 6.529053s wall, 6.531250s user + 0.000000s system = 6.531250s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 94% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.52524e+06, over cnt = 349(0%), over = 349, worst = 1, crit = 0
+PHY-1001 : End Routed; 1.278120s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (100.2%)
+
+PHY-1022 : len = 2.52524e+06, over cnt = 349(0%), over = 349, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1193, reserve = 1211, peak = 1195.
+PHY-1001 : End initial routed; 22.215427s wall, 22.140625s user + 0.062500s system = 22.203125s CPU (99.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17144(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.994   |  -3.898   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.293090s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1201, reserve = 1219, peak = 1201.
+PHY-1001 : End phase 3; 25.508578s wall, 25.437500s user + 0.062500s system = 25.500000s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.994ns STNS -3.898ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.118333s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (105.6%)
+
+PHY-1022 : len = 2.52524e+06, over cnt = 349(0%), over = 349, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.353216s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.994ns, -3.898ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.5167e+06, over cnt = 246(0%), over = 246, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.338195s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.51124e+06, over cnt = 135(0%), over = 135, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 2.234932s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (107.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50966e+06, over cnt = 62(0%), over = 62, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 1.549803s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (104.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50948e+06, over cnt = 19(0%), over = 19, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 1.495342s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (108.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50937e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.708296s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.5%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.784713s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.934893s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.50935e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.261643s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (89.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.50935e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.245061s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.261298s wall, 0.250000s user + 0.031250s system = 0.281250s CPU (107.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.288679s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.535471s wall, 0.546875s user + 0.031250s system = 0.578125s CPU (108.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.50935e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.270986s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.50935e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.244374s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.255863s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (103.8%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.290492s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.529742s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.525737s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.50935e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.244354s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.50935e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.244483s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.257467s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.282449s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.545930s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.50934e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.545060s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.350918s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.224419s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.238260s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.219136s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.228737s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.422113s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.443578s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.218735s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.207053s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.240207s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (104.1%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.234450s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.226311s wall, 0.250000s user + 0.062500s system = 0.312500s CPU (138.1%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.225833s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.9%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.405788s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.452212s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.208369s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.171494s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.332840s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.240469s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.236493s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (112.3%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.224562s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.228227s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.416795s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.432766s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.187302s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.190722s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.203344s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.198742s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.232014s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.266835s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.227825s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.226845s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.410377s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.447806s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.327544s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.199721s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.216913s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.224643s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.204893s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.223078s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.237744s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.238537s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.217322s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (107.8%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.451856s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.454936s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.176392s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.187857s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.364883s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.165540s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.193898s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.5093e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.196743s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17144(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.994   |  -3.898   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.267187s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1209, reserve = 1227, peak = 1209.
+PHY-1001 : End phase 4; 54.316405s wall, 54.656250s user + 0.187500s system = 54.843750s CPU (101.0%)
+
+PHY-1001 : 838 feed throughs used by 546 nets
+PHY-1001 : Current memory(MB): used = 1211, reserve = 1229, peak = 1211.
+PHY-1001 : End export database. 2.482022s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (100.1%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y20_clk0), nets: sampling_fe_a/u_sort/data_o_b2[4]_syn_22 u_pll/clk0_buf
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in  91.868616s wall, 92.140625s user + 0.250000s system = 92.390625s CPU (100.6%)
+
+RUN-1004 : used memory is 1206 MB, reserved memory is 1223 MB, peak memory is 1211 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x22y20_clk0), nets: sampling_fe_a/u_sort/data_o_b2[4]_syn_22 u_pll/clk0_buf
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in  245.299688s wall, 275.609375s user + 1.500000s system = 277.109375s CPU (113.0%)
+
+RUN-1004 : used memory is 1206 MB, reserved memory is 1223 MB, peak memory is 1211 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_135156.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_140053.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_140053.log
new file mode 100644
index 0000000..fd40be4
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_140053.log
@@ -0,0 +1,3308 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:00:53 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.156678s wall, 2.093750s user + 0.062500s system = 2.156250s CPU (100.0%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 321 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2934 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18401 instances
+RUN-0007 : 7415 luts, 9763 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20982 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14069 nets have 2 pins
+RUN-1001 : 5439 nets have [3 - 5] pins
+RUN-1001 : 1060 nets have [6 - 10] pins
+RUN-1001 : 164 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     794     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4192     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18399 instances, 7415 luts, 9763 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6554 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87640, tnet num: 20804, tinst num: 18399, tnode num: 119890, tedge num: 140412.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.155432s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (100.1%)
+
+RUN-1004 : used memory is 545 MB, reserved memory is 529 MB, peak memory is 545 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.951632s wall, 1.906250s user + 0.046875s system = 1.953125s CPU (100.1%)
+
+PHY-3001 : Found 3480 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.23988e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18399.
+PHY-3001 : Level 1 #clusters 2119.
+PHY-3001 : End clustering;  0.130445s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (143.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29065e+06, overlap = 492.812
+PHY-3002 : Step(2): len = 1.23148e+06, overlap = 531.438
+PHY-3002 : Step(3): len = 841619, overlap = 678.75
+PHY-3002 : Step(4): len = 776941, overlap = 724.875
+PHY-3002 : Step(5): len = 597380, overlap = 856.781
+PHY-3002 : Step(6): len = 538102, overlap = 934.906
+PHY-3002 : Step(7): len = 446997, overlap = 1010.53
+PHY-3002 : Step(8): len = 421208, overlap = 1050.81
+PHY-3002 : Step(9): len = 371502, overlap = 1106.34
+PHY-3002 : Step(10): len = 344490, overlap = 1145.06
+PHY-3002 : Step(11): len = 306348, overlap = 1181.66
+PHY-3002 : Step(12): len = 284110, overlap = 1202.81
+PHY-3002 : Step(13): len = 259023, overlap = 1237.47
+PHY-3002 : Step(14): len = 237509, overlap = 1289.88
+PHY-3002 : Step(15): len = 221083, overlap = 1328.28
+PHY-3002 : Step(16): len = 204552, overlap = 1339
+PHY-3002 : Step(17): len = 185874, overlap = 1394.94
+PHY-3002 : Step(18): len = 173501, overlap = 1437.09
+PHY-3002 : Step(19): len = 164652, overlap = 1457.62
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.19989e-06
+PHY-3002 : Step(20): len = 166192, overlap = 1428.16
+PHY-3002 : Step(21): len = 197849, overlap = 1320.78
+PHY-3002 : Step(22): len = 197823, overlap = 1311.72
+PHY-3002 : Step(23): len = 199846, overlap = 1290.91
+PHY-3002 : Step(24): len = 198517, overlap = 1281.56
+PHY-3002 : Step(25): len = 199164, overlap = 1259.94
+PHY-3002 : Step(26): len = 195618, overlap = 1264
+PHY-3002 : Step(27): len = 194047, overlap = 1249.53
+PHY-3002 : Step(28): len = 190646, overlap = 1241.34
+PHY-3002 : Step(29): len = 188112, overlap = 1230.59
+PHY-3002 : Step(30): len = 186482, overlap = 1222.16
+PHY-3002 : Step(31): len = 185803, overlap = 1210.53
+PHY-3002 : Step(32): len = 184703, overlap = 1187.84
+PHY-3002 : Step(33): len = 184820, overlap = 1196.62
+PHY-3002 : Step(34): len = 184180, overlap = 1184.31
+PHY-3002 : Step(35): len = 184440, overlap = 1171
+PHY-3002 : Step(36): len = 182831, overlap = 1159.59
+PHY-3002 : Step(37): len = 183283, overlap = 1152.66
+PHY-3002 : Step(38): len = 181263, overlap = 1152.19
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.39977e-06
+PHY-3002 : Step(39): len = 186801, overlap = 1163.12
+PHY-3002 : Step(40): len = 200672, overlap = 1142.59
+PHY-3002 : Step(41): len = 209609, overlap = 1125.62
+PHY-3002 : Step(42): len = 214723, overlap = 1070.81
+PHY-3002 : Step(43): len = 216094, overlap = 1049.59
+PHY-3002 : Step(44): len = 215412, overlap = 1029.53
+PHY-3002 : Step(45): len = 214045, overlap = 1026.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.79955e-06
+PHY-3002 : Step(46): len = 219886, overlap = 1020.56
+PHY-3002 : Step(47): len = 234626, overlap = 985.562
+PHY-3002 : Step(48): len = 245325, overlap = 963.781
+PHY-3002 : Step(49): len = 252880, overlap = 936.438
+PHY-3002 : Step(50): len = 255023, overlap = 923.531
+PHY-3002 : Step(51): len = 257483, overlap = 892.562
+PHY-3002 : Step(52): len = 256932, overlap = 873.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.5991e-06
+PHY-3002 : Step(53): len = 278510, overlap = 778.344
+PHY-3002 : Step(54): len = 306390, overlap = 641.531
+PHY-3002 : Step(55): len = 316605, overlap = 589.125
+PHY-3002 : Step(56): len = 318485, overlap = 578.438
+PHY-3002 : Step(57): len = 315979, overlap = 573
+PHY-3002 : Step(58): len = 315629, overlap = 555.656
+PHY-3002 : Step(59): len = 314219, overlap = 567.562
+PHY-3002 : Step(60): len = 314763, overlap = 553.406
+PHY-3002 : Step(61): len = 312680, overlap = 564.375
+PHY-3002 : Step(62): len = 312182, overlap = 566.438
+PHY-3002 : Step(63): len = 310541, overlap = 540.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.91982e-05
+PHY-3002 : Step(64): len = 329989, overlap = 514.312
+PHY-3002 : Step(65): len = 345906, overlap = 477.656
+PHY-3002 : Step(66): len = 349651, overlap = 484.062
+PHY-3002 : Step(67): len = 350522, overlap = 465.156
+PHY-3002 : Step(68): len = 350974, overlap = 437.969
+PHY-3002 : Step(69): len = 352095, overlap = 436.344
+PHY-3002 : Step(70): len = 351805, overlap = 425.219
+PHY-3002 : Step(71): len = 353023, overlap = 435.906
+PHY-3002 : Step(72): len = 353755, overlap = 416.469
+PHY-3002 : Step(73): len = 352990, overlap = 433.906
+PHY-3002 : Step(74): len = 351620, overlap = 439.281
+PHY-3002 : Step(75): len = 351663, overlap = 450.844
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.83964e-05
+PHY-3002 : Step(76): len = 370718, overlap = 416
+PHY-3002 : Step(77): len = 382390, overlap = 395.25
+PHY-3002 : Step(78): len = 380858, overlap = 384.562
+PHY-3002 : Step(79): len = 381474, overlap = 373.406
+PHY-3002 : Step(80): len = 384374, overlap = 363.281
+PHY-3002 : Step(81): len = 388045, overlap = 347.062
+PHY-3002 : Step(82): len = 386434, overlap = 342.656
+PHY-3002 : Step(83): len = 388402, overlap = 329.5
+PHY-3002 : Step(84): len = 391046, overlap = 332.25
+PHY-3002 : Step(85): len = 392850, overlap = 317.406
+PHY-3002 : Step(86): len = 392843, overlap = 307.281
+PHY-3002 : Step(87): len = 393455, overlap = 305.25
+PHY-3002 : Step(88): len = 394532, overlap = 301.281
+PHY-3002 : Step(89): len = 394295, overlap = 295.438
+PHY-3002 : Step(90): len = 395833, overlap = 298.188
+PHY-3002 : Step(91): len = 395633, overlap = 296.062
+PHY-3002 : Step(92): len = 396309, overlap = 282.281
+PHY-3002 : Step(93): len = 394711, overlap = 276.188
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.67928e-05
+PHY-3002 : Step(94): len = 408839, overlap = 271
+PHY-3002 : Step(95): len = 416478, overlap = 272.031
+PHY-3002 : Step(96): len = 415884, overlap = 268.281
+PHY-3002 : Step(97): len = 417589, overlap = 277.438
+PHY-3002 : Step(98): len = 420939, overlap = 275.094
+PHY-3002 : Step(99): len = 423717, overlap = 267.719
+PHY-3002 : Step(100): len = 422548, overlap = 262.656
+PHY-3002 : Step(101): len = 422649, overlap = 271.875
+PHY-3002 : Step(102): len = 423458, overlap = 263.625
+PHY-3002 : Step(103): len = 424166, overlap = 244.156
+PHY-3002 : Step(104): len = 422550, overlap = 255.281
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000148885
+PHY-3002 : Step(105): len = 435725, overlap = 242.438
+PHY-3002 : Step(106): len = 444793, overlap = 230.156
+PHY-3002 : Step(107): len = 444831, overlap = 223.969
+PHY-3002 : Step(108): len = 447534, overlap = 223.562
+PHY-3002 : Step(109): len = 451649, overlap = 219.844
+PHY-3002 : Step(110): len = 454718, overlap = 208.062
+PHY-3002 : Step(111): len = 453098, overlap = 215.562
+PHY-3002 : Step(112): len = 453062, overlap = 216.281
+PHY-3002 : Step(113): len = 455132, overlap = 203.75
+PHY-3002 : Step(114): len = 456082, overlap = 190.656
+PHY-3002 : Step(115): len = 454155, overlap = 195.75
+PHY-3002 : Step(116): len = 453865, overlap = 191.938
+PHY-3002 : Step(117): len = 455770, overlap = 188.281
+PHY-3002 : Step(118): len = 456633, overlap = 185.625
+PHY-3002 : Step(119): len = 454747, overlap = 181.344
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000277738
+PHY-3002 : Step(120): len = 464032, overlap = 178.219
+PHY-3002 : Step(121): len = 469074, overlap = 179.094
+PHY-3002 : Step(122): len = 468607, overlap = 180.531
+PHY-3002 : Step(123): len = 470078, overlap = 178.281
+PHY-3002 : Step(124): len = 475299, overlap = 176.5
+PHY-3002 : Step(125): len = 480008, overlap = 179.719
+PHY-3002 : Step(126): len = 478805, overlap = 182.188
+PHY-3002 : Step(127): len = 479103, overlap = 174.375
+PHY-3002 : Step(128): len = 481751, overlap = 177.594
+PHY-3002 : Step(129): len = 483551, overlap = 174.188
+PHY-3002 : Step(130): len = 481926, overlap = 177.375
+PHY-3002 : Step(131): len = 481556, overlap = 176.125
+PHY-3002 : Step(132): len = 483083, overlap = 171.625
+PHY-3002 : Step(133): len = 483796, overlap = 170.531
+PHY-3002 : Step(134): len = 482637, overlap = 167.094
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000521647
+PHY-3002 : Step(135): len = 488475, overlap = 166.031
+PHY-3002 : Step(136): len = 494912, overlap = 167.438
+PHY-3002 : Step(137): len = 494774, overlap = 163.25
+PHY-3002 : Step(138): len = 495204, overlap = 162.031
+PHY-3002 : Step(139): len = 497814, overlap = 165.656
+PHY-3002 : Step(140): len = 500420, overlap = 165.531
+PHY-3002 : Step(141): len = 499910, overlap = 165.656
+PHY-3002 : Step(142): len = 500197, overlap = 166.594
+PHY-3002 : Step(143): len = 502270, overlap = 165.844
+PHY-3002 : Step(144): len = 504045, overlap = 168.25
+PHY-3002 : Step(145): len = 502651, overlap = 169.094
+PHY-3002 : Step(146): len = 502338, overlap = 168.594
+PHY-3002 : Step(147): len = 504108, overlap = 168.969
+PHY-3002 : Step(148): len = 505836, overlap = 156.719
+PHY-3002 : Step(149): len = 504787, overlap = 154.469
+PHY-3002 : Step(150): len = 504414, overlap = 151.906
+PHY-3002 : Step(151): len = 505828, overlap = 152.938
+PHY-3002 : Step(152): len = 507593, overlap = 146.719
+PHY-3002 : Step(153): len = 506687, overlap = 139.25
+PHY-3002 : Step(154): len = 506573, overlap = 137.031
+PHY-3002 : Step(155): len = 507395, overlap = 142.062
+PHY-3002 : Step(156): len = 507583, overlap = 139.875
+PHY-3002 : Step(157): len = 506653, overlap = 137.344
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000924664
+PHY-3002 : Step(158): len = 510278, overlap = 137.031
+PHY-3002 : Step(159): len = 513741, overlap = 139.531
+PHY-3002 : Step(160): len = 513978, overlap = 133.656
+PHY-3002 : Step(161): len = 514489, overlap = 133.406
+PHY-3002 : Step(162): len = 516380, overlap = 134.469
+PHY-3002 : Step(163): len = 517974, overlap = 134.375
+PHY-3002 : Step(164): len = 517570, overlap = 133.438
+PHY-3002 : Step(165): len = 517885, overlap = 130.625
+PHY-3002 : Step(166): len = 519744, overlap = 129.188
+PHY-3002 : Step(167): len = 520819, overlap = 127.938
+PHY-3002 : Step(168): len = 520023, overlap = 132.5
+PHY-3002 : Step(169): len = 519722, overlap = 133.875
+PHY-3002 : Step(170): len = 520786, overlap = 136.281
+PHY-3002 : Step(171): len = 521718, overlap = 135.188
+PHY-3002 : Step(172): len = 520794, overlap = 139.688
+PHY-3002 : Step(173): len = 520501, overlap = 139.75
+PHY-3002 : Step(174): len = 521286, overlap = 136.375
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00171068
+PHY-3002 : Step(175): len = 523250, overlap = 131.438
+PHY-3002 : Step(176): len = 527167, overlap = 130.281
+PHY-3002 : Step(177): len = 528693, overlap = 125.125
+PHY-3002 : Step(178): len = 529734, overlap = 125.344
+PHY-3002 : Step(179): len = 530502, overlap = 127.875
+PHY-3002 : Step(180): len = 531521, overlap = 121.906
+PHY-3002 : Step(181): len = 532196, overlap = 119.094
+PHY-3002 : Step(182): len = 532685, overlap = 118.344
+PHY-3002 : Step(183): len = 532959, overlap = 116.469
+PHY-3002 : Step(184): len = 533579, overlap = 115.531
+PHY-3002 : Step(185): len = 534002, overlap = 113.906
+PHY-3002 : Step(186): len = 534319, overlap = 113.562
+PHY-3002 : Step(187): len = 534868, overlap = 112.156
+PHY-3002 : Step(188): len = 535568, overlap = 110.594
+PHY-3002 : Step(189): len = 535741, overlap = 105.625
+PHY-3002 : Step(190): len = 535739, overlap = 104.844
+PHY-3002 : Step(191): len = 535479, overlap = 109.375
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015542s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (100.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 674528, over cnt = 1626(4%), over = 7236, worst = 45
+PHY-1001 : End global iterations;  0.742080s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (128.4%)
+
+PHY-1001 : Congestion index: top1 = 76.57, top5 = 58.95, top10 = 50.63, top15 = 45.40.
+PHY-3001 : End congestion estimation;  0.971990s wall, 1.156250s user + 0.046875s system = 1.203125s CPU (123.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.863923s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.61598e-05
+PHY-3002 : Step(192): len = 615402, overlap = 60.5
+PHY-3002 : Step(193): len = 617863, overlap = 57.1875
+PHY-3002 : Step(194): len = 621922, overlap = 58.1562
+PHY-3002 : Step(195): len = 624620, overlap = 55.5625
+PHY-3002 : Step(196): len = 628395, overlap = 57.5
+PHY-3002 : Step(197): len = 635282, overlap = 61.9062
+PHY-3002 : Step(198): len = 645852, overlap = 56.4688
+PHY-3002 : Step(199): len = 655011, overlap = 62.3125
+PHY-3002 : Step(200): len = 661482, overlap = 73.2812
+PHY-3002 : Step(201): len = 666151, overlap = 81.0938
+PHY-3002 : Step(202): len = 668737, overlap = 75.125
+PHY-3002 : Step(203): len = 674961, overlap = 64.2188
+PHY-3002 : Step(204): len = 682405, overlap = 51.2812
+PHY-3002 : Step(205): len = 683501, overlap = 43.4688
+PHY-3002 : Step(206): len = 683459, overlap = 43.4062
+PHY-3002 : Step(207): len = 683113, overlap = 44.75
+PHY-3002 : Step(208): len = 684819, overlap = 51.625
+PHY-3002 : Step(209): len = 684211, overlap = 49.4062
+PHY-3002 : Step(210): len = 683894, overlap = 46.0312
+PHY-3002 : Step(211): len = 682801, overlap = 46.9375
+PHY-3002 : Step(212): len = 681586, overlap = 45.8438
+PHY-3002 : Step(213): len = 679633, overlap = 44.25
+PHY-3002 : Step(214): len = 677794, overlap = 40.5
+PHY-3002 : Step(215): len = 676824, overlap = 38.0938
+PHY-3002 : Step(216): len = 676458, overlap = 36.7188
+PHY-3002 : Step(217): len = 674975, overlap = 35.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00019232
+PHY-3002 : Step(218): len = 679048, overlap = 34.625
+PHY-3002 : Step(219): len = 683996, overlap = 34.4062
+PHY-3002 : Step(220): len = 685650, overlap = 32.4375
+PHY-3002 : Step(221): len = 687368, overlap = 30.875
+PHY-3002 : Step(222): len = 689296, overlap = 29.9062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000384639
+PHY-3002 : Step(223): len = 694929, overlap = 32.4688
+PHY-3002 : Step(224): len = 704425, overlap = 29.8125
+PHY-3002 : Step(225): len = 715296, overlap = 28.875
+PHY-3002 : Step(226): len = 719806, overlap = 30.7188
+PHY-3002 : Step(227): len = 722054, overlap = 34.5
+PHY-3002 : Step(228): len = 725193, overlap = 35.0625
+PHY-3002 : Step(229): len = 723456, overlap = 33.7188
+PHY-3002 : Step(230): len = 721952, overlap = 34.6875
+PHY-3002 : Step(231): len = 722659, overlap = 37.0312
+PHY-3002 : Step(232): len = 725352, overlap = 31.6562
+PHY-3002 : Step(233): len = 722707, overlap = 29.5312
+PHY-3002 : Step(234): len = 719868, overlap = 29.75
+PHY-3002 : Step(235): len = 718311, overlap = 33.0938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000647262
+PHY-3002 : Step(236): len = 721517, overlap = 32.375
+PHY-3002 : Step(237): len = 727874, overlap = 32.0625
+PHY-3002 : Step(238): len = 734806, overlap = 33.1875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00105102
+PHY-3002 : Step(239): len = 733937, overlap = 31.875
+PHY-3002 : Step(240): len = 735819, overlap = 33.4375
+PHY-3002 : Step(241): len = 758295, overlap = 33.9375
+PHY-3002 : Step(242): len = 763667, overlap = 34
+PHY-3002 : Step(243): len = 761358, overlap = 34.5625
+PHY-3002 : Step(244): len = 759524, overlap = 28.875
+PHY-3002 : Step(245): len = 759358, overlap = 30.1562
+PHY-3002 : Step(246): len = 759623, overlap = 31.2188
+PHY-3002 : Step(247): len = 759314, overlap = 30.6562
+PHY-3002 : Step(248): len = 761343, overlap = 29.2188
+PHY-3002 : Step(249): len = 763393, overlap = 28.5938
+PHY-3002 : Step(250): len = 763917, overlap = 27.2188
+PHY-3002 : Step(251): len = 763712, overlap = 27.4688
+PHY-3002 : Step(252): len = 762234, overlap = 31.7188
+PHY-3002 : Step(253): len = 761506, overlap = 29.1875
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00183542
+PHY-3002 : Step(254): len = 762485, overlap = 30.7812
+PHY-3002 : Step(255): len = 765210, overlap = 30.9062
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 48/20982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842616, over cnt = 2884(8%), over = 14573, worst = 104
+PHY-1001 : End global iterations;  1.476829s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 116.96, top5 = 77.66, top10 = 65.43, top15 = 58.65.
+PHY-3001 : End congestion estimation;  1.798469s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (135.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.892082s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000131893
+PHY-3002 : Step(256): len = 760159, overlap = 241.125
+PHY-3002 : Step(257): len = 759415, overlap = 203.219
+PHY-3002 : Step(258): len = 750905, overlap = 181.781
+PHY-3002 : Step(259): len = 744825, overlap = 162.594
+PHY-3002 : Step(260): len = 739324, overlap = 150.688
+PHY-3002 : Step(261): len = 735106, overlap = 145.438
+PHY-3002 : Step(262): len = 729908, overlap = 133.969
+PHY-3002 : Step(263): len = 725892, overlap = 126.906
+PHY-3002 : Step(264): len = 720293, overlap = 135.375
+PHY-3002 : Step(265): len = 715832, overlap = 137.125
+PHY-3002 : Step(266): len = 710075, overlap = 136.438
+PHY-3002 : Step(267): len = 707015, overlap = 134.844
+PHY-3002 : Step(268): len = 702654, overlap = 132.688
+PHY-3002 : Step(269): len = 699300, overlap = 135.312
+PHY-3002 : Step(270): len = 696222, overlap = 143.719
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000263786
+PHY-3002 : Step(271): len = 697440, overlap = 138.781
+PHY-3002 : Step(272): len = 702012, overlap = 130.938
+PHY-3002 : Step(273): len = 703818, overlap = 129.812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000527572
+PHY-3002 : Step(274): len = 707766, overlap = 118.812
+PHY-3002 : Step(275): len = 717884, overlap = 101.5
+PHY-3002 : Step(276): len = 723967, overlap = 90.9062
+PHY-3002 : Step(277): len = 721248, overlap = 97.4062
+PHY-3002 : Step(278): len = 719726, overlap = 97
+PHY-3002 : Step(279): len = 719390, overlap = 93.6562
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87640, tnet num: 20804, tinst num: 18399, tnode num: 119890, tedge num: 140412.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.441005s wall, 1.375000s user + 0.062500s system = 1.437500s CPU (99.8%)
+
+RUN-1004 : used memory is 587 MB, reserved memory is 577 MB, peak memory is 729 MB
+OPT-1001 : Total overflow 447.09 peak overflow 3.81
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 755/20982.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 811280, over cnt = 3167(8%), over = 12459, worst = 82
+PHY-1001 : End global iterations;  1.350687s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (149.2%)
+
+PHY-1001 : Congestion index: top1 = 94.12, top5 = 67.60, top10 = 58.17, top15 = 52.86.
+PHY-1001 : End incremental global routing;  1.697059s wall, 2.328125s user + 0.031250s system = 2.359375s CPU (139.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20804 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.285128s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (99.7%)
+
+OPT-1001 : 52 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18262 has valid locations, 348 needs to be replaced
+PHY-3001 : design contains 18695 instances, 7525 luts, 9949 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6686 pins
+PHY-3001 : Found 3513 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 741796
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17252/21278.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 827856, over cnt = 3203(9%), over = 12580, worst = 82
+PHY-1001 : End global iterations;  0.227193s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (123.8%)
+
+PHY-1001 : Congestion index: top1 = 93.60, top5 = 67.61, top10 = 58.36, top15 = 53.22.
+PHY-3001 : End congestion estimation;  0.582305s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (110.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88857, tnet num: 21100, tinst num: 18695, tnode num: 121701, tedge num: 142254.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.458282s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.7%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 636 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21100 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.789727s wall, 2.312500s user + 0.093750s system = 2.406250s CPU (86.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(280): len = 740711, overlap = 1
+PHY-3002 : Step(281): len = 740116, overlap = 1
+PHY-3002 : Step(282): len = 739822, overlap = 1
+PHY-3002 : Step(283): len = 739530, overlap = 0.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17355/21278.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825440, over cnt = 3224(9%), over = 12684, worst = 82
+PHY-1001 : End global iterations;  0.201228s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (116.5%)
+
+PHY-1001 : Congestion index: top1 = 94.89, top5 = 68.05, top10 = 58.71, top15 = 53.43.
+PHY-3001 : End congestion estimation;  0.447019s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (108.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21100 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.938934s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000369442
+PHY-3002 : Step(284): len = 739555, overlap = 96.2188
+PHY-3002 : Step(285): len = 739608, overlap = 96.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000738883
+PHY-3002 : Step(286): len = 739639, overlap = 96.25
+PHY-3002 : Step(287): len = 740225, overlap = 96.2188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00147777
+PHY-3002 : Step(288): len = 740229, overlap = 95.5
+PHY-3002 : Step(289): len = 741219, overlap = 95.6562
+PHY-3001 : Final: Len = 741219, Over = 95.6562
+PHY-3001 : End incremental placement;  5.488903s wall, 5.328125s user + 0.218750s system = 5.546875s CPU (101.1%)
+
+OPT-1001 : Total overflow 452.75 peak overflow 3.81
+OPT-1001 : End high-fanout net optimization;  9.017260s wall, 9.593750s user + 0.250000s system = 9.843750s CPU (109.2%)
+
+OPT-1001 : Current memory(MB): used = 737, reserve = 732, peak = 754.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17292/21278.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 828640, over cnt = 3141(8%), over = 11619, worst = 82
+PHY-1002 : len = 889704, over cnt = 2201(6%), over = 5854, worst = 55
+PHY-1002 : len = 927360, over cnt = 1049(2%), over = 2711, worst = 25
+PHY-1002 : len = 958416, over cnt = 318(0%), over = 624, worst = 17
+PHY-1002 : len = 969720, over cnt = 5(0%), over = 5, worst = 1
+PHY-1001 : End global iterations;  2.224031s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (133.5%)
+
+PHY-1001 : Congestion index: top1 = 65.73, top5 = 57.57, top10 = 52.93, top15 = 49.88.
+OPT-1001 : End congestion update;  2.482531s wall, 3.187500s user + 0.031250s system = 3.218750s CPU (129.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21100 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.619721s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (50.2%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 66 cells processed and 6050 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 26 cells processed and 1566 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 16 cells processed and 300 slack improved
+OPT-1001 : End global optimization;  4.147218s wall, 4.031250s user + 0.031250s system = 4.062500s CPU (98.0%)
+
+OPT-1001 : Current memory(MB): used = 711, reserve = 706, peak = 754.
+OPT-1001 : End physical optimization;  15.233192s wall, 15.703125s user + 0.390625s system = 16.093750s CPU (105.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7525 LUT to BLE ...
+SYN-4008 : Packed 7525 LUT and 3154 SEQ to BLE.
+SYN-4003 : Packing 6795 remaining SEQ's ...
+SYN-4005 : Packed 4172 SEQ with LUT/SLICE
+SYN-4006 : 512 single LUT's are left
+SYN-4006 : 2623 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10148/13879 primitive instances ...
+PHY-3001 : End packing;  1.689780s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6994 instances
+RUN-1001 : 3423 mslices, 3423 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18253 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10707 nets have 2 pins
+RUN-1001 : 5698 nets have [3 - 5] pins
+RUN-1001 : 1155 nets have [6 - 10] pins
+RUN-1001 : 328 nets have [11 - 20] pins
+RUN-1001 : 333 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6992 instances, 6846 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3869 pins
+PHY-3001 : Found 1568 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 751006, Over = 297
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7651/18253.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 909584, over cnt = 2087(5%), over = 3471, worst = 9
+PHY-1002 : len = 916608, over cnt = 1501(4%), over = 2241, worst = 8
+PHY-1002 : len = 935656, over cnt = 439(1%), over = 595, worst = 7
+PHY-1002 : len = 942056, over cnt = 153(0%), over = 201, worst = 6
+PHY-1002 : len = 946872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.579079s wall, 2.156250s user + 0.031250s system = 2.187500s CPU (138.5%)
+
+PHY-1001 : Congestion index: top1 = 62.87, top5 = 54.82, top10 = 50.37, top15 = 47.67.
+PHY-3001 : End congestion estimation;  1.960535s wall, 2.531250s user + 0.031250s system = 2.562500s CPU (130.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75754, tnet num: 18075, tinst num: 6992, tnode num: 99495, tedge num: 126846.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.607451s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.1%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 633 MB, peak memory is 754 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18075 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.485859s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.48216e-05
+PHY-3002 : Step(290): len = 739917, overlap = 291.25
+PHY-3002 : Step(291): len = 732783, overlap = 292.25
+PHY-3002 : Step(292): len = 727849, overlap = 287
+PHY-3002 : Step(293): len = 723113, overlap = 293.5
+PHY-3002 : Step(294): len = 719545, overlap = 288.5
+PHY-3002 : Step(295): len = 715544, overlap = 293
+PHY-3002 : Step(296): len = 710527, overlap = 299.5
+PHY-3002 : Step(297): len = 706796, overlap = 298.25
+PHY-3002 : Step(298): len = 702935, overlap = 294.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.96433e-05
+PHY-3002 : Step(299): len = 705627, overlap = 288
+PHY-3002 : Step(300): len = 710063, overlap = 279.5
+PHY-3002 : Step(301): len = 711507, overlap = 272.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000179287
+PHY-3002 : Step(302): len = 718046, overlap = 264.75
+PHY-3002 : Step(303): len = 727237, overlap = 246.5
+PHY-3002 : Step(304): len = 728559, overlap = 243.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000358573
+PHY-3002 : Step(305): len = 734404, overlap = 233
+PHY-3002 : Step(306): len = 744621, overlap = 222.25
+PHY-3002 : Step(307): len = 745914, overlap = 219.75
+PHY-3002 : Step(308): len = 745920, overlap = 221.25
+PHY-3002 : Step(309): len = 747396, overlap = 223.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.324774s wall, 0.312500s user + 0.546875s system = 0.859375s CPU (264.6%)
+
+PHY-3001 : Trial Legalized: Len = 950808
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 565/18253.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06926e+06, over cnt = 2962(8%), over = 4996, worst = 8
+PHY-1002 : len = 1.08578e+06, over cnt = 1942(5%), over = 2899, worst = 7
+PHY-1002 : len = 1.11227e+06, over cnt = 659(1%), over = 939, worst = 7
+PHY-1002 : len = 1.12218e+06, over cnt = 255(0%), over = 352, worst = 7
+PHY-1002 : len = 1.12905e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.530738s wall, 3.703125s user + 0.046875s system = 3.750000s CPU (148.2%)
+
+PHY-1001 : Congestion index: top1 = 68.04, top5 = 60.34, top10 = 55.94, top15 = 53.08.
+PHY-3001 : End congestion estimation;  2.979802s wall, 4.156250s user + 0.046875s system = 4.203125s CPU (141.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18075 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.880315s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164725
+PHY-3002 : Step(310): len = 904870, overlap = 77.5
+PHY-3002 : Step(311): len = 880842, overlap = 107.5
+PHY-3002 : Step(312): len = 863342, overlap = 132.25
+PHY-3002 : Step(313): len = 848686, overlap = 161.5
+PHY-3002 : Step(314): len = 837857, overlap = 178.5
+PHY-3002 : Step(315): len = 827764, overlap = 193.5
+PHY-3002 : Step(316): len = 820089, overlap = 204.25
+PHY-3002 : Step(317): len = 812409, overlap = 216
+PHY-3002 : Step(318): len = 808021, overlap = 220
+PHY-3002 : Step(319): len = 803814, overlap = 217.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00032945
+PHY-3002 : Step(320): len = 809213, overlap = 214
+PHY-3002 : Step(321): len = 812255, overlap = 210.25
+PHY-3002 : Step(322): len = 813539, overlap = 206.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000559883
+PHY-3002 : Step(323): len = 819931, overlap = 200.5
+PHY-3002 : Step(324): len = 822069, overlap = 198.75
+PHY-3002 : Step(325): len = 824683, overlap = 197.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.083518s wall, 0.062500s user + 0.015625s system = 0.078125s CPU (93.5%)
+
+PHY-3001 : Legalized: Len = 894373, Over = 0
+PHY-3001 : Spreading special nets. 451 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.149415s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.6%)
+
+PHY-3001 : 650 instances has been re-located, deltaX = 333, deltaY = 391, maxDist = 10.
+PHY-3001 : Final: Len = 905784, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75754, tnet num: 18075, tinst num: 6995, tnode num: 99495, tedge num: 126846.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.880924s wall, 1.843750s user + 0.031250s system = 1.875000s CPU (99.7%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 617 MB, peak memory is 754 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3652/18253.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03573e+06, over cnt = 2758(7%), over = 4541, worst = 8
+PHY-1002 : len = 1.04847e+06, over cnt = 1864(5%), over = 2718, worst = 8
+PHY-1002 : len = 1.06501e+06, over cnt = 957(2%), over = 1388, worst = 6
+PHY-1002 : len = 1.08274e+06, over cnt = 233(0%), over = 328, worst = 4
+PHY-1002 : len = 1.08759e+06, over cnt = 9(0%), over = 11, worst = 2
+PHY-1001 : End global iterations;  2.231584s wall, 3.125000s user + 0.015625s system = 3.140625s CPU (140.7%)
+
+PHY-1001 : Congestion index: top1 = 64.74, top5 = 57.85, top10 = 54.11, top15 = 51.61.
+PHY-1001 : End incremental global routing;  2.615316s wall, 3.515625s user + 0.015625s system = 3.531250s CPU (135.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18075 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.194044s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (98.1%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6902 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 7016 instances, 6867 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3937 pins
+PHY-3001 : Found 1575 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 908953
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16718/18277.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09118e+06, over cnt = 91(0%), over = 106, worst = 4
+PHY-1002 : len = 1.09134e+06, over cnt = 37(0%), over = 41, worst = 2
+PHY-1002 : len = 1.09172e+06, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 1.09179e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.0919e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.827508s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (107.6%)
+
+PHY-1001 : Congestion index: top1 = 64.74, top5 = 57.86, top10 = 54.12, top15 = 51.62.
+PHY-3001 : End congestion estimation;  1.157649s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (105.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75976, tnet num: 18099, tinst num: 7016, tnode num: 99764, tedge num: 127121.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.936542s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (100.0%)
+
+RUN-1004 : used memory is 674 MB, reserved memory is 676 MB, peak memory is 754 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.867496s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(326): len = 908322, overlap = 0
+PHY-3002 : Step(327): len = 907871, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16710/18277.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09011e+06, over cnt = 47(0%), over = 56, worst = 3
+PHY-1002 : len = 1.09014e+06, over cnt = 28(0%), over = 30, worst = 2
+PHY-1002 : len = 1.09038e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.0904e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.09039e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.388293s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (59.7%)
+
+PHY-1001 : Congestion index: top1 = 64.74, top5 = 57.86, top10 = 54.13, top15 = 51.62.
+PHY-3001 : End congestion estimation;  1.719235s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (67.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.910082s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000905641
+PHY-3002 : Step(328): len = 908090, overlap = 2.5
+PHY-3002 : Step(329): len = 907954, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.006005s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (260.2%)
+
+PHY-3001 : Legalized: Len = 908073, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059588s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.9%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 6, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 908117, Over = 0
+PHY-3001 : End incremental placement;  7.168631s wall, 6.656250s user + 0.062500s system = 6.718750s CPU (93.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  11.507462s wall, 11.875000s user + 0.078125s system = 11.953125s CPU (103.9%)
+
+OPT-1001 : Current memory(MB): used = 758, reserve = 761, peak = 761.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16688/18277.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09022e+06, over cnt = 67(0%), over = 83, worst = 6
+PHY-1002 : len = 1.09027e+06, over cnt = 33(0%), over = 36, worst = 2
+PHY-1002 : len = 1.09057e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.0907e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.607392s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (110.6%)
+
+PHY-1001 : Congestion index: top1 = 64.74, top5 = 57.86, top10 = 54.14, top15 = 51.63.
+OPT-1001 : End congestion update;  0.930025s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (105.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.754568s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.5%)
+
+OPT-0007 : Start: WNS -1036 TNS -1700 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6928 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7016 instances, 6867 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3937 pins
+PHY-3001 : Found 1575 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 911187, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061664s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.4%)
+
+PHY-3001 : 20 instances has been re-located, deltaX = 11, deltaY = 13, maxDist = 2.
+PHY-3001 : Final: Len = 911301, Over = 0
+PHY-3001 : End incremental legalization;  0.397230s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.3%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1621 NUM_FEPS 2 with 29 cells processed and 7050 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6928 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7016 instances, 6867 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3937 pins
+PHY-3001 : Found 1575 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 912761, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058424s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.0%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 6, deltaY = 10, maxDist = 3.
+PHY-3001 : Final: Len = 912957, Over = 0
+PHY-3001 : End incremental legalization;  0.402995s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.9%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1421 NUM_FEPS 2 with 18 cells processed and 2950 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6928 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7016 instances, 6867 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3937 pins
+PHY-3001 : Found 1575 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 912819, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060513s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.3%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 8, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 912787, Over = 0
+PHY-3001 : End incremental legalization;  0.382382s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.1%)
+
+OPT-0007 : Iter 3: improved WNS -936 TNS -1421 NUM_FEPS 2 with 14 cells processed and 500 slack improved
+OPT-1001 : End path based optimization;  3.263276s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (104.9%)
+
+OPT-1001 : Current memory(MB): used = 758, reserve = 761, peak = 761.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.742523s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16517/18277.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09493e+06, over cnt = 164(0%), over = 192, worst = 4
+PHY-1002 : len = 1.095e+06, over cnt = 121(0%), over = 124, worst = 3
+PHY-1002 : len = 1.09548e+06, over cnt = 48(0%), over = 48, worst = 1
+PHY-1002 : len = 1.09605e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.09632e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.870646s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (104.1%)
+
+PHY-1001 : Congestion index: top1 = 63.53, top5 = 57.55, top10 = 54.04, top15 = 51.61.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.731200s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1036 TNS -1721 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 63.103448
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1036ps with logic level 2 
+RUN-1001 :       #2 path slack -990ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 18277 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 18277 nets
+OPT-1001 : End physical optimization;  19.679963s wall, 20.187500s user + 0.125000s system = 20.312500s CPU (103.2%)
+
+RUN-1003 : finish command "place" in  65.735396s wall, 98.187500s user + 6.265625s system = 104.453125s CPU (158.9%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 659 MB, peak memory is 761 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.708077s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (174.7%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 660 MB, peak memory is 761 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7018 instances
+RUN-1001 : 3436 mslices, 3431 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18277 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10703 nets have 2 pins
+RUN-1001 : 5689 nets have [3 - 5] pins
+RUN-1001 : 1175 nets have [6 - 10] pins
+RUN-1001 : 336 nets have [11 - 20] pins
+RUN-1001 : 345 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75976, tnet num: 18099, tinst num: 7016, tnode num: 99764, tedge num: 127121.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.620456s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.3%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 638 MB, peak memory is 761 MB
+PHY-1001 : 3436 mslices, 3431 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[102] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.02013e+06, over cnt = 2928(8%), over = 4885, worst = 8
+PHY-1002 : len = 1.04057e+06, over cnt = 1764(5%), over = 2463, worst = 6
+PHY-1002 : len = 1.06367e+06, over cnt = 529(1%), over = 716, worst = 5
+PHY-1002 : len = 1.07455e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.07487e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.135839s wall, 4.250000s user + 0.031250s system = 4.281250s CPU (136.5%)
+
+PHY-1001 : Congestion index: top1 = 63.36, top5 = 57.34, top10 = 53.68, top15 = 51.09.
+PHY-1001 : End global routing;  3.483717s wall, 4.593750s user + 0.031250s system = 4.625000s CPU (132.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 724, reserve = 727, peak = 761.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 998, reserve = 1002, peak = 998.
+PHY-1001 : End build detailed router design. 4.007555s wall, 3.937500s user + 0.062500s system = 4.000000s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 263496, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.467515s wall, 5.453125s user + 0.000000s system = 5.453125s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 263552, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.427671s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.6%)
+
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1038, peak = 1033.
+PHY-1001 : End phase 1; 5.906539s wall, 5.890625s user + 0.000000s system = 5.890625s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.55233e+06, over cnt = 2160(0%), over = 2172, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1055, peak = 1052.
+PHY-1001 : End initial routed; 44.987026s wall, 72.125000s user + 0.453125s system = 72.578125s CPU (161.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17199(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.217   |  -4.121   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.342472s wall, 3.296875s user + 0.046875s system = 3.343750s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1065, reserve = 1069, peak = 1065.
+PHY-1001 : End phase 2; 48.329561s wall, 75.421875s user + 0.500000s system = 75.921875s CPU (157.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.096ns STNS -4.000ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.142685s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.6%)
+
+PHY-1022 : len = 2.55234e+06, over cnt = 2160(0%), over = 2172, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.409712s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50832e+06, over cnt = 864(0%), over = 865, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.652476s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (153.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50456e+06, over cnt = 179(0%), over = 179, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.137350s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (140.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50566e+06, over cnt = 39(0%), over = 39, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.468028s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (130.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50628e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.300289s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (109.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50648e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.461254s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.50657e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.475431s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.50657e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.480957s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (97.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.177512s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.50657e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.183513s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.7%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.50657e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.278449s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.50657e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.294644s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.50657e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.459301s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.7%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.231361s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.188131s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.215899s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.3%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.230698s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.316221s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.372428s wall, 0.390625s user + 0.031250s system = 0.421875s CPU (113.3%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.172356s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.172585s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.194197s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.6%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.207433s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.9%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.295958s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.373573s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (112.9%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.108734s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.170450s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.171241s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.205040s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.211223s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.294153s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.372927s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.104080s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 1.108177s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.175785s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.8%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.171970s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.200284s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (93.6%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.211401s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (110.9%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.288100s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.375946s wall, 0.390625s user + 0.031250s system = 0.421875s CPU (112.2%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 1.137072s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 1.218032s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.099960s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.173978s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.174251s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.198034s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.208097s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.6%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.292515s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.382205s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.1%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.254819s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.115146s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.108481s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.109410s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.172906s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.174740s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (116.2%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.193338s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.206154s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.296540s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.382108s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.276039s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.121626s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.109572s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.078423s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.113681s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.189459s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.181059s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.196427s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (127.3%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.206692s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.289952s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (102.4%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.380603s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.118261s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.095881s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.199648s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 1.213891s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 1.109160s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.128497s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (101.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17199(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.096   |  -4.000   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.295681s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1073, reserve = 1077, peak = 1073.
+PHY-1001 : End phase 3; 45.561460s wall, 47.640625s user + 0.156250s system = 47.796875s CPU (104.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.096ns STNS -4.000ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.144799s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.1%)
+
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.388352s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.096ns, -4.000ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.198858s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.186613s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (108.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.219093s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.170688s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.7%)
+
+PHY-1001 : ==== DR Iter 5 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.170267s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (119.3%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.197541s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.212651s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (110.2%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.297078s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 9 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.176106s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.5%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.177062s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (97.1%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.205707s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.234539s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.342533s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.430852s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (108.8%)
+
+PHY-1001 : ===== DR Iter 15 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.174667s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.175362s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (89.1%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.202316s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (115.8%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.230460s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (108.5%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.299450s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.370762s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 1.099932s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 22 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.172349s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.170826s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.198901s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.3%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.214978s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (116.3%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.289999s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (107.8%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.381206s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 1.114500s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 1.111438s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 30 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.169567s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (92.1%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.173058s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.200293s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.211086s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.292491s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.375421s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 1.099819s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 1.321768s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.113518s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 39 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.915821s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (20.5%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.175616s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.8%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.198560s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (94.4%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.208648s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (104.8%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.303960s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.367042s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 1.102560s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.124415s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.126744s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.112277s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 49 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.173349s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.173834s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (116.8%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.198063s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.219611s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.293390s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.418189s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 1.193646s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 1.106265s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.109182s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 1.104721s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.4%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.115274s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 60 =====
+PHY-1022 : len = 2.50662e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.171329s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.172663s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.199929s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.214127s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.299653s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.368502s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 1.103446s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 1.100498s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.441273s wall, 1.437500s user + 0.000000s system = 1.437500s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.118021s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.107260s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.208383s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17199(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.096   |  -4.000   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.347410s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1076, reserve = 1080, peak = 1076.
+PHY-1001 : End phase 4; 40.466648s wall, 39.765625s user + 0.109375s system = 39.875000s CPU (98.5%)
+
+PHY-1003 : Routed, final wirelength = 2.50659e+06
+PHY-1001 : 674 feed throughs used by 475 nets
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1185, peak = 1178.
+PHY-1001 : End export database. 2.765739s wall, 2.734375s user + 0.031250s system = 2.765625s CPU (100.0%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7018 instances
+RUN-1001 : 3436 mslices, 3431 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18277 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10703 nets have 2 pins
+RUN-1001 : 5689 nets have [3 - 5] pins
+RUN-1001 : 1175 nets have [6 - 10] pins
+RUN-1001 : 336 nets have [11 - 20] pins
+RUN-1001 : 345 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |      0      
+RUN-1001 :   No   |  No   |  Yes  |      0      
+RUN-1001 :   No   |  Yes  |  No   |      0      
+RUN-1001 :   Yes  |  No   |  No   |      0      
+RUN-1001 :   Yes  |  No   |  Yes  |      0      
+RUN-1001 :   Yes  |  Yes  |  No   |      0      
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    10   |   1   |     1      
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 44 0) is for feedthrough
+PHY-3001 : eco cells: (2 7 1) is for feedthrough
+PHY-3001 : eco cells: (2 10 0) is for feedthrough
+PHY-3001 : eco cells: (2 36 2) is for feedthrough
+PHY-3001 : eco cells: (2 40 3) is for feedthrough
+PHY-3001 : eco cells: (2 41 1) is for feedthrough
+PHY-3001 : eco cells: (2 46 0) is for feedthrough
+PHY-3001 : eco cells: (2 57 3) is for feedthrough
+PHY-3001 : eco cells: (2 60 0) is for feedthrough
+PHY-3001 : eco cells: (2 68 0) is for feedthrough
+PHY-3001 : eco cells: (3 4 1) is for feedthrough
+PHY-3001 : eco cells: (3 8 1) is for feedthrough
+PHY-3001 : eco cells: (3 29 1) is for feedthrough
+PHY-3001 : eco cells: (3 39 2) is for feedthrough
+PHY-3001 : eco cells: (3 57 0) is for feedthrough
+PHY-3001 : eco cells: (3 58 3) is for feedthrough
+PHY-3001 : eco cells: (4 8 3) is for feedthrough
+PHY-3001 : eco cells: (4 9 1) is for feedthrough
+PHY-3001 : eco cells: (4 25 1) is for feedthrough
+PHY-3001 : eco cells: (4 38 2) is for feedthrough
+PHY-3001 : eco cells: (4 50 3) is for feedthrough
+PHY-3001 : eco cells: (4 54 0) is for feedthrough
+PHY-3001 : eco cells: (4 57 0) is for feedthrough
+PHY-3001 : eco cells: (4 60 2) is for feedthrough
+PHY-3001 : eco cells: (4 68 0) is for feedthrough
+PHY-3001 : eco cells: (5 2 2) is for feedthrough
+PHY-3001 : eco cells: (5 4 3) is for feedthrough
+PHY-3001 : eco cells: (5 7 3) is for feedthrough
+PHY-3001 : eco cells: (5 11 0) is for feedthrough
+PHY-3001 : eco cells: (5 13 2) is for feedthrough
+PHY-3001 : eco cells: (5 20 0) is for feedthrough
+PHY-3001 : eco cells: (5 22 0) is for feedthrough
+PHY-3001 : eco cells: (5 29 0) is for feedthrough
+PHY-3001 : eco cells: (5 51 0) is for feedthrough
+PHY-3001 : eco cells: (5 55 1) is for feedthrough
+PHY-3001 : eco cells: (5 55 3) is for feedthrough
+PHY-3001 : eco cells: (5 58 3) is for feedthrough
+PHY-3001 : eco cells: (5 59 1) is for feedthrough
+PHY-3001 : eco cells: (5 62 3) is for feedthrough
+PHY-3001 : eco cells: (6 14 0) is for feedthrough
+PHY-3001 : eco cells: (6 15 1) is for feedthrough
+PHY-3001 : eco cells: (6 40 3) is for feedthrough
+PHY-3001 : eco cells: (6 54 1) is for feedthrough
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+PHY-3001 : eco cells: (29 2 1) is for feedthrough
+PHY-3001 : eco cells: (29 9 2) is for feedthrough
+PHY-3001 : eco cells: (29 23 3) is for feedthrough
+PHY-3001 : eco cells: (29 26 3) is for feedthrough
+PHY-3001 : eco cells: (29 29 2) is for feedthrough
+PHY-3001 : eco cells: (29 32 0) is for feedthrough
+PHY-3001 : eco cells: (29 39 0) is for feedthrough
+PHY-3001 : eco cells: (29 43 2) is for feedthrough
+PHY-3001 : eco cells: (29 43 3) is for feedthrough
+PHY-3001 : eco cells: (29 44 3) is for feedthrough
+PHY-3001 : eco cells: (29 45 3) is for feedthrough
+PHY-3001 : eco cells: (29 46 2) is for feedthrough
+PHY-3001 : eco cells: (29 48 1) is for feedthrough
+PHY-3001 : eco cells: (29 49 3) is for feedthrough
+PHY-3001 : eco cells: (29 50 2) is for feedthrough
+PHY-3001 : eco cells: (29 56 3) is for feedthrough
+PHY-3001 : eco cells: (29 57 3) is for feedthrough
+PHY-3001 : eco cells: (29 64 3) is for feedthrough
+PHY-3001 : eco cells: (29 65 3) is for feedthrough
+PHY-3001 : eco cells: (30 3 1) is for feedthrough
+PHY-3001 : eco cells: (30 8 0) is for feedthrough
+PHY-3001 : eco cells: (30 12 2) is for feedthrough
+PHY-3001 : eco cells: (30 14 1) is for feedthrough
+PHY-3001 : eco cells: (30 20 2) is for feedthrough
+PHY-3001 : eco cells: (30 21 0) is for feedthrough
+PHY-3001 : eco cells: (30 26 3) is for feedthrough
+PHY-3001 : eco cells: (30 31 2) is for feedthrough
+PHY-3001 : eco cells: (30 31 3) is for feedthrough
+PHY-3001 : eco cells: (30 34 3) is for feedthrough
+PHY-3001 : eco cells: (30 38 0) is for feedthrough
+PHY-3001 : eco cells: (30 38 1) is for feedthrough
+PHY-3001 : eco cells: (30 43 3) is for feedthrough
+PHY-3001 : eco cells: (30 45 0) is for feedthrough
+PHY-3001 : eco cells: (30 45 1) is for feedthrough
+PHY-3001 : eco cells: (30 46 0) is for feedthrough
+PHY-3001 : eco cells: (30 49 1) is for feedthrough
+PHY-3001 : eco cells: (30 50 0) is for feedthrough
+PHY-3001 : eco cells: (30 50 3) is for feedthrough
+PHY-3001 : eco cells: (30 59 0) is for feedthrough
+PHY-3001 : eco cells: (31 36 1) is for feedthrough
+PHY-3001 : eco cells: (31 46 3) is for feedthrough
+PHY-3001 : eco cells: (31 53 1) is for feedthrough
+PHY-3001 : eco cells: (31 62 3) is for feedthrough
+PHY-3001 : eco cells: (31 66 0) is for feedthrough
+PHY-3001 : eco cells: (33 4 0) is for feedthrough
+PHY-3001 : eco cells: (33 4 1) is for feedthrough
+PHY-3001 : eco cells: (33 10 3) is for feedthrough
+PHY-3001 : eco cells: (33 11 3) is for feedthrough
+PHY-3001 : eco cells: (33 27 3) is for feedthrough
+PHY-3001 : eco cells: (33 28 2) is for feedthrough
+PHY-3001 : eco cells: (33 37 3) is for feedthrough
+PHY-3001 : eco cells: (33 44 0) is for feedthrough
+PHY-3001 : eco cells: (33 48 0) is for feedthrough
+PHY-3001 : eco cells: (33 49 2) is for feedthrough
+PHY-3001 : eco cells: (34 9 2) is for feedthrough
+PHY-3001 : eco cells: (34 13 1) is for feedthrough
+PHY-3001 : eco cells: (34 16 3) is for feedthrough
+PHY-3001 : eco cells: (34 18 1) is for feedthrough
+PHY-3001 : eco cells: (34 42 0) is for feedthrough
+PHY-3001 : eco cells: (34 47 3) is for feedthrough
+PHY-3001 : eco cells: (34 52 2) is for feedthrough
+PHY-3001 : eco cells: (34 53 3) is for feedthrough
+PHY-3001 : eco cells: (34 54 2) is for feedthrough
+PHY-3001 : eco cells: (34 66 1) is for feedthrough
+PHY-3001 : eco cells: (34 70 3) is for feedthrough
+PHY-3001 : eco cells: (35 8 1) is for feedthrough
+PHY-3001 : eco cells: (35 9 0) is for feedthrough
+PHY-3001 : eco cells: (35 14 2) is for feedthrough
+PHY-3001 : eco cells: (35 15 2) is for feedthrough
+PHY-3001 : eco cells: (35 15 3) is for feedthrough
+PHY-3001 : eco cells: (35 16 1) is for feedthrough
+PHY-3001 : eco cells: (35 18 0) is for feedthrough
+PHY-3001 : eco cells: (35 20 3) is for feedthrough
+PHY-3001 : eco cells: (35 53 2) is for feedthrough
+PHY-3001 : eco cells: (35 53 3) is for feedthrough
+PHY-3001 : eco cells: (35 69 2) is for feedthrough
+PHY-3001 : eco cells: (36 2 3) is for feedthrough
+PHY-3001 : eco cells: (36 3 3) is for feedthrough
+PHY-3001 : eco cells: (36 4 2) is for feedthrough
+PHY-3001 : eco cells: (36 10 3) is for feedthrough
+PHY-3001 : eco cells: (36 11 3) is for feedthrough
+PHY-3001 : eco cells: (36 12 1) is for feedthrough
+PHY-3001 : eco cells: (36 13 2) is for feedthrough
+PHY-3001 : eco cells: (36 15 2) is for feedthrough
+PHY-3001 : eco cells: (36 20 1) is for feedthrough
+PHY-3001 : eco cells: (36 21 0) is for feedthrough
+PHY-3001 : eco cells: (36 21 1) is for feedthrough
+PHY-3001 : eco cells: (36 35 2) is for feedthrough
+PHY-3001 : eco cells: (36 36 3) is for feedthrough
+PHY-3001 : eco cells: (36 44 1) is for feedthrough
+PHY-3001 : eco cells: (36 63 2) is for feedthrough
+PHY-3001 : eco cells: (36 69 3) is for feedthrough
+PHY-3001 : eco cells: (37 1 3) is for feedthrough
+PHY-3001 : eco cells: (37 4 0) is for feedthrough
+PHY-3001 : eco cells: (37 5 3) is for feedthrough
+PHY-3001 : eco cells: (37 7 3) is for feedthrough
+PHY-3001 : eco cells: (37 8 3) is for feedthrough
+PHY-3001 : eco cells: (37 9 1) is for feedthrough
+PHY-3001 : eco cells: (37 10 3) is for feedthrough
+PHY-3001 : eco cells: (37 12 1) is for feedthrough
+PHY-3001 : eco cells: (37 13 2) is for feedthrough
+PHY-3001 : eco cells: (37 15 1) is for feedthrough
+PHY-3001 : eco cells: (37 16 3) is for feedthrough
+PHY-3001 : eco cells: (37 37 2) is for feedthrough
+PHY-3001 : eco cells: (37 69 1) is for feedthrough
+PHY-3001 : eco cells: (38 4 2) is for feedthrough
+PHY-3001 : eco cells: (38 6 3) is for feedthrough
+PHY-3001 : eco cells: (38 9 2) is for feedthrough
+PHY-3001 : eco cells: (38 9 3) is for feedthrough
+PHY-3001 : eco cells: (38 11 0) is for feedthrough
+PHY-3001 : eco cells: (38 16 2) is for feedthrough
+PHY-3001 : eco cells: (38 17 1) is for feedthrough
+PHY-3001 : eco cells: (38 18 2) is for feedthrough
+PHY-3001 : eco cells: (38 44 0) is for feedthrough
+PHY-3001 : eco cells: (38 44 1) is for feedthrough
+PHY-3001 : eco cells: (38 46 3) is for feedthrough
+PHY-3001 : eco cells: (38 57 3) is for feedthrough
+PHY-3001 : eco cells: (38 68 1) is for feedthrough
+PHY-3001 : eco cells: (39 3 2) is for feedthrough
+PHY-3001 : eco cells: (39 48 2) is for feedthrough
+PHY-3001 : eco cells: (39 56 1) is for feedthrough
+PHY-3001 : eco cells: (39 58 1) is for feedthrough
+PHY-3001 : eco cells: 6928 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7016 instances, 6867 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3937 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.796783s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.0%)
+
+PHY-3001 : Found 1575 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in  1.231193s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.3%)
+
+RUN-1004 : used memory is 1174 MB, reserved memory is 1182 MB, peak memory is 1178 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7018 instances
+RUN-1001 : 3436 mslices, 3431 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18277 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10703 nets have 2 pins
+RUN-1001 : 5689 nets have [3 - 5] pins
+RUN-1001 : 1175 nets have [6 - 10] pins
+RUN-1001 : 336 nets have [11 - 20] pins
+RUN-1001 : 345 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3436 mslices, 3431 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18099 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1179, reserve = 1186, peak = 1179.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1202, reserve = 1210, peak = 1202.
+PHY-1001 : End build detailed router design. 1.885040s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.5%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.021839s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (143.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.030088s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (103.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.028790s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (108.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.028973s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (107.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.029842s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (52.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.031518s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (99.1%)
+
+PHY-1001 : Current memory(MB): used = 1202, reserve = 1210, peak = 1202.
+PHY-1001 : End phase 1; 0.207102s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1202, reserve = 1210, peak = 1202.
+PHY-1001 : End initial routed; 0.154668s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (101.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17199(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.096   |  -4.000   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.331431s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1203, reserve = 1210, peak = 1203.
+PHY-1001 : End phase 2; 3.486156s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.096ns STNS -4.000ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.120419s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (103.8%)
+
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.348956s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (103.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.133459s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.135400s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.134991s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.184571s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.148983s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.4%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.138519s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.140834s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.138117s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (113.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.139123s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.141158s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.140986s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.149638s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (114.9%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.136628s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.134104s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.2%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.134278s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (116.4%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.181910s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.1%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.133236s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.8%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.136663s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (114.3%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.135905s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.133465s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.7%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.132936s wall, 0.187500s user + 0.046875s system = 0.234375s CPU (176.3%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.134131s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.8%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.183723s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.6%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.133553s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.3%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.136876s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.133343s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.7%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.133520s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (105.3%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.132881s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.8%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.134071s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.2%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.133132s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.6%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.136612s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.5%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.135299s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.9%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.140237s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (144.8%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.187881s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.141350s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (121.6%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.143688s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (141.4%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.137381s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.0%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.137521s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.134072s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.2%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.133661s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.5%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.134364s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.7%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.137488s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.134364s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.182386s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.2%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.147352s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (116.6%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.136946s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.133507s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.6%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.134815s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.3%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.180313s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.3%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.132706s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.131781s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.9%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.136787s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (125.7%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.135497s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.8%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.132081s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.6%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.180683s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (112.4%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.134085s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.133242s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.136655s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.134261s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.1%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.134168s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.8%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.135993s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.4%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.141780s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.145258s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.8%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.138305s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.7%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.134095s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.133201s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.134700s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.134653s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.132529s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.3%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.137079s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.146689s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.134721s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.133341s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.7%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.50659e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.133448s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17199(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.096   |  -4.000   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.314345s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1204, reserve = 1212, peak = 1204.
+PHY-1001 : End phase 3; 14.196671s wall, 14.390625s user + 0.140625s system = 14.531250s CPU (102.4%)
+
+PHY-1001 : 674 feed throughs used by 475 nets
+PHY-1001 : Current memory(MB): used = 1204, reserve = 1212, peak = 1204.
+PHY-1001 : End export database. 2.807720s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (99.6%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x13y42_local1), nets: sys_initial_done_dup_1163 sampling_fe_b/u_sort/u_transfer_300_to_200/mux11_syn_173
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in  23.741821s wall, 23.937500s user + 0.140625s system = 24.078125s CPU (101.4%)
+
+RUN-1004 : used memory is 1184 MB, reserved memory is 1192 MB, peak memory is 1204 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x13y42_local1), nets: sys_initial_done_dup_1163 sampling_fe_b/u_sort/u_transfer_300_to_200/mux11_syn_173
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in  178.353367s wall, 208.015625s user + 1.046875s system = 209.062500s CPU (117.2%)
+
+RUN-1004 : used memory is 1184 MB, reserved memory is 1192 MB, peak memory is 1204 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_140053.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_140815.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_140815.log
new file mode 100644
index 0000000..f8dcbd0
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_140815.log
@@ -0,0 +1,2056 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:08:15 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.233765s wall, 2.109375s user + 0.125000s system = 2.234375s CPU (100.0%)
+
+RUN-1004 : used memory is 350 MB, reserved memory is 328 MB, peak memory is 355 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2937 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2777 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 19099 instances
+RUN-0007 : 7387 luts, 10489 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21683 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14746 nets have 2 pins
+RUN-1001 : 5474 nets have [3 - 5] pins
+RUN-1001 : 1051 nets have [6 - 10] pins
+RUN-1001 : 165 nets have [11 - 20] pins
+RUN-1001 : 173 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4917     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 19097 instances, 7387 luts, 10489 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 7217 pins
+PHY-0007 : Cell area utilization is 54%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 90450, tnet num: 21505, tinst num: 19097, tnode num: 124884, tedge num: 144640.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.187605s wall, 1.156250s user + 0.031250s system = 1.187500s CPU (100.0%)
+
+RUN-1004 : used memory is 557 MB, reserved memory is 541 MB, peak memory is 557 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 21505 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.012733s wall, 1.953125s user + 0.062500s system = 2.015625s CPU (100.1%)
+
+PHY-3001 : Found 3477 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.02523e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 19097.
+PHY-3001 : Level 1 #clusters 2160.
+PHY-3001 : End clustering;  0.133953s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 54%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.26945e+06, overlap = 519.469
+PHY-3002 : Step(2): len = 1.20849e+06, overlap = 534.531
+PHY-3002 : Step(3): len = 833336, overlap = 662.781
+PHY-3002 : Step(4): len = 762487, overlap = 709.969
+PHY-3002 : Step(5): len = 588431, overlap = 820.031
+PHY-3002 : Step(6): len = 524767, overlap = 898.875
+PHY-3002 : Step(7): len = 448707, overlap = 979.562
+PHY-3002 : Step(8): len = 422353, overlap = 1043.53
+PHY-3002 : Step(9): len = 374589, overlap = 1108.09
+PHY-3002 : Step(10): len = 343042, overlap = 1150.88
+PHY-3002 : Step(11): len = 298823, overlap = 1215.69
+PHY-3002 : Step(12): len = 280843, overlap = 1244.03
+PHY-3002 : Step(13): len = 255777, overlap = 1300.31
+PHY-3002 : Step(14): len = 240147, overlap = 1330.06
+PHY-3002 : Step(15): len = 217728, overlap = 1391.22
+PHY-3002 : Step(16): len = 197759, overlap = 1402.38
+PHY-3002 : Step(17): len = 186188, overlap = 1426.41
+PHY-3002 : Step(18): len = 172565, overlap = 1435.69
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.04661e-06
+PHY-3002 : Step(19): len = 174030, overlap = 1408
+PHY-3002 : Step(20): len = 204409, overlap = 1367.44
+PHY-3002 : Step(21): len = 210587, overlap = 1318.09
+PHY-3002 : Step(22): len = 215126, overlap = 1326.75
+PHY-3002 : Step(23): len = 211300, overlap = 1310.66
+PHY-3002 : Step(24): len = 209814, overlap = 1285.97
+PHY-3002 : Step(25): len = 207287, overlap = 1261.19
+PHY-3002 : Step(26): len = 205858, overlap = 1215.53
+PHY-3002 : Step(27): len = 200441, overlap = 1200.34
+PHY-3002 : Step(28): len = 197356, overlap = 1209.75
+PHY-3002 : Step(29): len = 193913, overlap = 1210.56
+PHY-3002 : Step(30): len = 190460, overlap = 1206.75
+PHY-3002 : Step(31): len = 188199, overlap = 1207.5
+PHY-3002 : Step(32): len = 187133, overlap = 1214.66
+PHY-3002 : Step(33): len = 186117, overlap = 1213.25
+PHY-3002 : Step(34): len = 187192, overlap = 1228.78
+PHY-3002 : Step(35): len = 186129, overlap = 1218.47
+PHY-3002 : Step(36): len = 185535, overlap = 1202.59
+PHY-3002 : Step(37): len = 184274, overlap = 1214.09
+PHY-3002 : Step(38): len = 183897, overlap = 1201.78
+PHY-3002 : Step(39): len = 182500, overlap = 1190.44
+PHY-3002 : Step(40): len = 181171, overlap = 1191.25
+PHY-3002 : Step(41): len = 180660, overlap = 1202.94
+PHY-3002 : Step(42): len = 180285, overlap = 1210.16
+PHY-3002 : Step(43): len = 179856, overlap = 1232.59
+PHY-3002 : Step(44): len = 180425, overlap = 1260.53
+PHY-3002 : Step(45): len = 179564, overlap = 1279.94
+PHY-3002 : Step(46): len = 180130, overlap = 1282.97
+PHY-3002 : Step(47): len = 179394, overlap = 1269.81
+PHY-3002 : Step(48): len = 179559, overlap = 1276.19
+PHY-3002 : Step(49): len = 177403, overlap = 1282.28
+PHY-3002 : Step(50): len = 176857, overlap = 1273.22
+PHY-3002 : Step(51): len = 174078, overlap = 1296.47
+PHY-3002 : Step(52): len = 173930, overlap = 1283.12
+PHY-3002 : Step(53): len = 173161, overlap = 1274.94
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.09321e-06
+PHY-3002 : Step(54): len = 175225, overlap = 1263.78
+PHY-3002 : Step(55): len = 184746, overlap = 1243.66
+PHY-3002 : Step(56): len = 188698, overlap = 1208.12
+PHY-3002 : Step(57): len = 193635, overlap = 1161.97
+PHY-3002 : Step(58): len = 194910, overlap = 1140.03
+PHY-3002 : Step(59): len = 196899, overlap = 1133.44
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.18642e-06
+PHY-3002 : Step(60): len = 204373, overlap = 1114.53
+PHY-3002 : Step(61): len = 222370, overlap = 1015.38
+PHY-3002 : Step(62): len = 226658, overlap = 949.969
+PHY-3002 : Step(63): len = 233556, overlap = 947.188
+PHY-3002 : Step(64): len = 236246, overlap = 918.5
+PHY-3002 : Step(65): len = 238360, overlap = 885.312
+PHY-3002 : Step(66): len = 237502, overlap = 874.031
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.37285e-06
+PHY-3002 : Step(67): len = 251846, overlap = 842.562
+PHY-3002 : Step(68): len = 275840, overlap = 757.594
+PHY-3002 : Step(69): len = 287906, overlap = 707.125
+PHY-3002 : Step(70): len = 294201, overlap = 663.281
+PHY-3002 : Step(71): len = 294086, overlap = 649
+PHY-3002 : Step(72): len = 292525, overlap = 628.938
+PHY-3002 : Step(73): len = 290202, overlap = 628.406
+PHY-3002 : Step(74): len = 289750, overlap = 621.344
+PHY-3002 : Step(75): len = 288819, overlap = 634.781
+PHY-3002 : Step(76): len = 287718, overlap = 628.812
+PHY-3002 : Step(77): len = 284686, overlap = 650.062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.67457e-05
+PHY-3002 : Step(78): len = 302855, overlap = 583.156
+PHY-3002 : Step(79): len = 316435, overlap = 519.594
+PHY-3002 : Step(80): len = 320685, overlap = 519.906
+PHY-3002 : Step(81): len = 323676, overlap = 522.125
+PHY-3002 : Step(82): len = 322942, overlap = 528.969
+PHY-3002 : Step(83): len = 324141, overlap = 533.406
+PHY-3002 : Step(84): len = 321932, overlap = 547.719
+PHY-3002 : Step(85): len = 320765, overlap = 523.719
+PHY-3002 : Step(86): len = 319480, overlap = 517.469
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.34914e-05
+PHY-3002 : Step(87): len = 336946, overlap = 509.25
+PHY-3002 : Step(88): len = 348294, overlap = 474.688
+PHY-3002 : Step(89): len = 348275, overlap = 409.094
+PHY-3002 : Step(90): len = 350414, overlap = 401.438
+PHY-3002 : Step(91): len = 352534, overlap = 397.719
+PHY-3002 : Step(92): len = 355960, overlap = 390.344
+PHY-3002 : Step(93): len = 354869, overlap = 379.062
+PHY-3002 : Step(94): len = 356506, overlap = 366.344
+PHY-3002 : Step(95): len = 359801, overlap = 367.969
+PHY-3002 : Step(96): len = 361612, overlap = 368.344
+PHY-3002 : Step(97): len = 360544, overlap = 364.906
+PHY-3002 : Step(98): len = 360780, overlap = 356.938
+PHY-3002 : Step(99): len = 360713, overlap = 342.938
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.69828e-05
+PHY-3002 : Step(100): len = 376708, overlap = 344.844
+PHY-3002 : Step(101): len = 386649, overlap = 335.188
+PHY-3002 : Step(102): len = 386082, overlap = 317.969
+PHY-3002 : Step(103): len = 388045, overlap = 304.656
+PHY-3002 : Step(104): len = 391848, overlap = 297.5
+PHY-3002 : Step(105): len = 397597, overlap = 291.406
+PHY-3002 : Step(106): len = 396611, overlap = 297.656
+PHY-3002 : Step(107): len = 397201, overlap = 303.906
+PHY-3002 : Step(108): len = 399800, overlap = 276.75
+PHY-3002 : Step(109): len = 401720, overlap = 284.375
+PHY-3002 : Step(110): len = 399393, overlap = 290.156
+PHY-3002 : Step(111): len = 400355, overlap = 298.031
+PHY-3002 : Step(112): len = 402332, overlap = 287.062
+PHY-3002 : Step(113): len = 401113, overlap = 277.312
+PHY-3002 : Step(114): len = 401092, overlap = 259.188
+PHY-3002 : Step(115): len = 399494, overlap = 279.219
+PHY-3002 : Step(116): len = 398924, overlap = 290.75
+PHY-3002 : Step(117): len = 398869, overlap = 293.062
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000133966
+PHY-3002 : Step(118): len = 411487, overlap = 288.156
+PHY-3002 : Step(119): len = 419722, overlap = 273.188
+PHY-3002 : Step(120): len = 419137, overlap = 253.906
+PHY-3002 : Step(121): len = 420980, overlap = 242.656
+PHY-3002 : Step(122): len = 423561, overlap = 242.781
+PHY-3002 : Step(123): len = 425856, overlap = 242.094
+PHY-3002 : Step(124): len = 423347, overlap = 246.031
+PHY-3002 : Step(125): len = 423178, overlap = 241.312
+PHY-3002 : Step(126): len = 425572, overlap = 250.406
+PHY-3002 : Step(127): len = 427903, overlap = 246.969
+PHY-3002 : Step(128): len = 425958, overlap = 247.438
+PHY-3002 : Step(129): len = 426122, overlap = 226.188
+PHY-3002 : Step(130): len = 427535, overlap = 217.125
+PHY-3002 : Step(131): len = 428629, overlap = 224.5
+PHY-3002 : Step(132): len = 426103, overlap = 225.5
+PHY-3002 : Step(133): len = 425197, overlap = 227.281
+PHY-3002 : Step(134): len = 425940, overlap = 221.688
+PHY-3002 : Step(135): len = 427192, overlap = 219.25
+PHY-3002 : Step(136): len = 425767, overlap = 233.344
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000257552
+PHY-3002 : Step(137): len = 432818, overlap = 228.75
+PHY-3002 : Step(138): len = 437562, overlap = 225.562
+PHY-3002 : Step(139): len = 437767, overlap = 224.125
+PHY-3002 : Step(140): len = 439077, overlap = 221.031
+PHY-3002 : Step(141): len = 442163, overlap = 213.875
+PHY-3002 : Step(142): len = 444867, overlap = 209.219
+PHY-3002 : Step(143): len = 444783, overlap = 205.75
+PHY-3002 : Step(144): len = 446452, overlap = 196.156
+PHY-3002 : Step(145): len = 448677, overlap = 199.031
+PHY-3002 : Step(146): len = 450036, overlap = 211.281
+PHY-3002 : Step(147): len = 448414, overlap = 223.812
+PHY-3002 : Step(148): len = 448097, overlap = 228.156
+PHY-3002 : Step(149): len = 448956, overlap = 230.375
+PHY-3002 : Step(150): len = 449138, overlap = 232
+PHY-3002 : Step(151): len = 448052, overlap = 224
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000473752
+PHY-3002 : Step(152): len = 453433, overlap = 213.062
+PHY-3002 : Step(153): len = 457455, overlap = 208.875
+PHY-3002 : Step(154): len = 456625, overlap = 210
+PHY-3002 : Step(155): len = 457033, overlap = 209.062
+PHY-3002 : Step(156): len = 459682, overlap = 201.094
+PHY-3002 : Step(157): len = 462256, overlap = 192.375
+PHY-3002 : Step(158): len = 461045, overlap = 191
+PHY-3002 : Step(159): len = 460859, overlap = 189.719
+PHY-3002 : Step(160): len = 462685, overlap = 187.406
+PHY-3002 : Step(161): len = 464065, overlap = 194.188
+PHY-3002 : Step(162): len = 463179, overlap = 204.625
+PHY-3002 : Step(163): len = 463340, overlap = 210.688
+PHY-3002 : Step(164): len = 464586, overlap = 207.625
+PHY-3002 : Step(165): len = 465252, overlap = 209.25
+PHY-3002 : Step(166): len = 464654, overlap = 208.719
+PHY-3002 : Step(167): len = 465371, overlap = 209.031
+PHY-3002 : Step(168): len = 467071, overlap = 206.406
+PHY-3002 : Step(169): len = 467750, overlap = 208.875
+PHY-3002 : Step(170): len = 465947, overlap = 212.875
+PHY-3002 : Step(171): len = 465469, overlap = 207.906
+PHY-3002 : Step(172): len = 466054, overlap = 212.031
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000939748
+PHY-3002 : Step(173): len = 470111, overlap = 201.188
+PHY-3002 : Step(174): len = 474678, overlap = 198.875
+PHY-3002 : Step(175): len = 475569, overlap = 195.062
+PHY-3002 : Step(176): len = 476974, overlap = 190.875
+PHY-3002 : Step(177): len = 478575, overlap = 191.406
+PHY-3002 : Step(178): len = 479867, overlap = 193.531
+PHY-3002 : Step(179): len = 480018, overlap = 191.906
+PHY-3002 : Step(180): len = 480198, overlap = 186.281
+PHY-3002 : Step(181): len = 480634, overlap = 185.625
+PHY-3002 : Step(182): len = 480966, overlap = 192
+PHY-3002 : Step(183): len = 480714, overlap = 186.156
+PHY-3002 : Step(184): len = 480911, overlap = 185.031
+PHY-3002 : Step(185): len = 481288, overlap = 190.5
+PHY-3002 : Step(186): len = 481784, overlap = 191.906
+PHY-3002 : Step(187): len = 481864, overlap = 190.125
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0016735
+PHY-3002 : Step(188): len = 483642, overlap = 188.375
+PHY-3002 : Step(189): len = 486048, overlap = 186.312
+PHY-3002 : Step(190): len = 487134, overlap = 191.25
+PHY-3002 : Step(191): len = 488107, overlap = 188.875
+PHY-3002 : Step(192): len = 489419, overlap = 187.5
+PHY-3002 : Step(193): len = 490439, overlap = 190.5
+PHY-3002 : Step(194): len = 490735, overlap = 194.594
+PHY-3002 : Step(195): len = 490834, overlap = 193.188
+PHY-3002 : Step(196): len = 490852, overlap = 192.844
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00282459
+PHY-3002 : Step(197): len = 492717, overlap = 193.344
+PHY-3002 : Step(198): len = 495567, overlap = 190.875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016656s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (93.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 61%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21683.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 639136, over cnt = 1620(4%), over = 7258, worst = 45
+PHY-1001 : End global iterations;  0.700815s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (133.8%)
+
+PHY-1001 : Congestion index: top1 = 84.07, top5 = 64.18, top10 = 53.83, top15 = 47.32.
+PHY-3001 : End congestion estimation;  0.966803s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (126.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21505 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.937679s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000122819
+PHY-3002 : Step(199): len = 584928, overlap = 154
+PHY-3002 : Step(200): len = 595482, overlap = 141.188
+PHY-3002 : Step(201): len = 597434, overlap = 130.5
+PHY-3002 : Step(202): len = 599033, overlap = 123.875
+PHY-3002 : Step(203): len = 605212, overlap = 117.125
+PHY-3002 : Step(204): len = 614727, overlap = 104.594
+PHY-3002 : Step(205): len = 615888, overlap = 98.7812
+PHY-3002 : Step(206): len = 616678, overlap = 97.375
+PHY-3002 : Step(207): len = 618058, overlap = 89.0312
+PHY-3002 : Step(208): len = 622856, overlap = 85.25
+PHY-3002 : Step(209): len = 624620, overlap = 78.5312
+PHY-3002 : Step(210): len = 623437, overlap = 76.7188
+PHY-3002 : Step(211): len = 621070, overlap = 73.8438
+PHY-3002 : Step(212): len = 621019, overlap = 72.4062
+PHY-3002 : Step(213): len = 619583, overlap = 75.75
+PHY-3002 : Step(214): len = 618006, overlap = 76.5938
+PHY-3002 : Step(215): len = 615367, overlap = 77.8125
+PHY-3002 : Step(216): len = 613904, overlap = 74.7188
+PHY-3002 : Step(217): len = 612095, overlap = 73.9062
+PHY-3002 : Step(218): len = 611261, overlap = 73.375
+PHY-3002 : Step(219): len = 609055, overlap = 74.5625
+PHY-3002 : Step(220): len = 607457, overlap = 75.6875
+PHY-3002 : Step(221): len = 605432, overlap = 78.9062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000245639
+PHY-3002 : Step(222): len = 605999, overlap = 78.3438
+PHY-3002 : Step(223): len = 609878, overlap = 78.6875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000424716
+PHY-3002 : Step(224): len = 612743, overlap = 77.625
+PHY-3002 : Step(225): len = 619513, overlap = 75
+PHY-3002 : Step(226): len = 630040, overlap = 77.5625
+PHY-3002 : Step(227): len = 636929, overlap = 74.9688
+PHY-3002 : Step(228): len = 644114, overlap = 65.25
+PHY-3002 : Step(229): len = 644390, overlap = 67.2812
+PHY-3002 : Step(230): len = 643293, overlap = 67.5312
+PHY-3002 : Step(231): len = 644164, overlap = 65.1562
+PHY-3002 : Step(232): len = 642048, overlap = 68.2188
+PHY-3002 : Step(233): len = 642801, overlap = 69.375
+PHY-3002 : Step(234): len = 643173, overlap = 74.3125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000849432
+PHY-3002 : Step(235): len = 647160, overlap = 67.7812
+PHY-3002 : Step(236): len = 654614, overlap = 63.7188
+PHY-3002 : Step(237): len = 659525, overlap = 61.6875
+PHY-3002 : Step(238): len = 662115, overlap = 61.1562
+PHY-3002 : Step(239): len = 667912, overlap = 58.3125
+PHY-3002 : Step(240): len = 674867, overlap = 59.1875
+PHY-3002 : Step(241): len = 676803, overlap = 64.5938
+PHY-3002 : Step(242): len = 677729, overlap = 68.8125
+PHY-3002 : Step(243): len = 678997, overlap = 73.9688
+PHY-3002 : Step(244): len = 678193, overlap = 74.625
+PHY-3002 : Step(245): len = 676314, overlap = 78.9688
+PHY-3002 : Step(246): len = 675770, overlap = 77.625
+PHY-3002 : Step(247): len = 677628, overlap = 76.7188
+PHY-3002 : Step(248): len = 677149, overlap = 79.5625
+PHY-3002 : Step(249): len = 677018, overlap = 78.1562
+PHY-3002 : Step(250): len = 677377, overlap = 76.3125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00160191
+PHY-3002 : Step(251): len = 677922, overlap = 78
+PHY-3002 : Step(252): len = 682812, overlap = 78.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 61%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 40/21683.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 761104, over cnt = 2869(8%), over = 13984, worst = 50
+PHY-1001 : End global iterations;  1.587153s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (135.9%)
+
+PHY-1001 : Congestion index: top1 = 98.77, top5 = 72.63, top10 = 62.51, top15 = 56.74.
+PHY-3001 : End congestion estimation;  1.896123s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (131.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21505 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.138201s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000120974
+PHY-3002 : Step(253): len = 679622, overlap = 274.562
+PHY-3002 : Step(254): len = 683122, overlap = 222.219
+PHY-3002 : Step(255): len = 677922, overlap = 183.531
+PHY-3002 : Step(256): len = 674448, overlap = 168.75
+PHY-3002 : Step(257): len = 667779, overlap = 155.969
+PHY-3002 : Step(258): len = 662589, overlap = 146
+PHY-3002 : Step(259): len = 654583, overlap = 146.219
+PHY-3002 : Step(260): len = 651071, overlap = 148.125
+PHY-3002 : Step(261): len = 644242, overlap = 142.188
+PHY-3002 : Step(262): len = 640514, overlap = 141.5
+PHY-3002 : Step(263): len = 636553, overlap = 132.5
+PHY-3002 : Step(264): len = 632571, overlap = 139.125
+PHY-3002 : Step(265): len = 627495, overlap = 150.375
+PHY-3002 : Step(266): len = 625553, overlap = 155.188
+PHY-3002 : Step(267): len = 621636, overlap = 154.625
+PHY-3002 : Step(268): len = 618788, overlap = 151.438
+PHY-3002 : Step(269): len = 616210, overlap = 150.594
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000241948
+PHY-3002 : Step(270): len = 616170, overlap = 147.812
+PHY-3002 : Step(271): len = 617257, overlap = 145.5
+PHY-3002 : Step(272): len = 620156, overlap = 141.406
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000483897
+PHY-3002 : Step(273): len = 624754, overlap = 127.688
+PHY-3002 : Step(274): len = 631332, overlap = 119.75
+PHY-3002 : Step(275): len = 634769, overlap = 112.812
+PHY-3002 : Step(276): len = 636051, overlap = 114.531
+PHY-3002 : Step(277): len = 636248, overlap = 111.938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000967794
+PHY-3002 : Step(278): len = 638370, overlap = 106.688
+PHY-3002 : Step(279): len = 640639, overlap = 103.688
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 90450, tnet num: 21505, tinst num: 19097, tnode num: 124884, tedge num: 144640.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.522463s wall, 1.484375s user + 0.046875s system = 1.531250s CPU (100.6%)
+
+RUN-1004 : used memory is 601 MB, reserved memory is 590 MB, peak memory is 746 MB
+OPT-1001 : Total overflow 486.53 peak overflow 3.50
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 709/21683.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 729992, over cnt = 3074(8%), over = 11769, worst = 41
+PHY-1001 : End global iterations;  1.276698s wall, 1.984375s user + 0.031250s system = 2.015625s CPU (157.9%)
+
+PHY-1001 : Congestion index: top1 = 71.92, top5 = 59.42, top10 = 53.19, top15 = 49.42.
+PHY-1001 : End incremental global routing;  1.626405s wall, 2.328125s user + 0.031250s system = 2.359375s CPU (145.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21505 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.961554s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (99.1%)
+
+OPT-1001 : 53 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18959 has valid locations, 338 needs to be replaced
+PHY-3001 : design contains 19382 instances, 7491 luts, 10670 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 7341 pins
+PHY-3001 : Found 3516 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 661724
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17622/21968.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 743768, over cnt = 3133(8%), over = 11819, worst = 41
+PHY-1001 : End global iterations;  0.232676s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 71.96, top5 = 59.48, top10 = 53.44, top15 = 49.78.
+PHY-3001 : End congestion estimation;  0.486805s wall, 0.531250s user + 0.031250s system = 0.562500s CPU (115.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 91600, tnet num: 21790, tinst num: 19382, tnode num: 126587, tedge num: 146370.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.513738s wall, 1.484375s user + 0.031250s system = 1.515625s CPU (100.1%)
+
+RUN-1004 : used memory is 649 MB, reserved memory is 653 MB, peak memory is 749 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21790 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.516685s wall, 2.437500s user + 0.078125s system = 2.515625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(280): len = 660711, overlap = 1.625
+PHY-3002 : Step(281): len = 660303, overlap = 1.625
+PHY-3002 : Step(282): len = 660159, overlap = 1.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17761/21968.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741344, over cnt = 3159(8%), over = 11888, worst = 41
+PHY-1001 : End global iterations;  0.177281s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (123.4%)
+
+PHY-1001 : Congestion index: top1 = 72.28, top5 = 59.60, top10 = 53.51, top15 = 49.81.
+PHY-3001 : End congestion estimation;  0.521780s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (107.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21790 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.657560s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000447537
+PHY-3002 : Step(283): len = 659913, overlap = 105.906
+PHY-3002 : Step(284): len = 660047, overlap = 105.375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000895074
+PHY-3002 : Step(285): len = 660431, overlap = 105.75
+PHY-3002 : Step(286): len = 661072, overlap = 106
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00179015
+PHY-3002 : Step(287): len = 661079, overlap = 105.844
+PHY-3002 : Step(288): len = 661585, overlap = 105.5
+PHY-3001 : Final: Len = 661585, Over = 105.5
+PHY-3001 : End incremental placement;  5.928472s wall, 6.156250s user + 0.281250s system = 6.437500s CPU (108.6%)
+
+OPT-1001 : Total overflow 493.47 peak overflow 3.50
+OPT-1001 : End high-fanout net optimization;  9.077531s wall, 10.093750s user + 0.343750s system = 10.437500s CPU (115.0%)
+
+OPT-1001 : Current memory(MB): used = 752, reserve = 747, peak = 770.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17644/21968.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 745336, over cnt = 3101(8%), over = 10928, worst = 41
+PHY-1002 : len = 804896, over cnt = 2229(6%), over = 5524, worst = 21
+PHY-1002 : len = 855424, over cnt = 801(2%), over = 1705, worst = 18
+PHY-1002 : len = 878208, over cnt = 213(0%), over = 392, worst = 11
+PHY-1002 : len = 886184, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.153465s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 59.78, top5 = 52.60, top10 = 48.93, top15 = 46.57.
+OPT-1001 : End congestion update;  2.414554s wall, 3.203125s user + 0.015625s system = 3.218750s CPU (133.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21790 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.824581s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.4%)
+
+OPT-0007 : Start: WNS -968 TNS -1428 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1428 NUM_FEPS 2 with 56 cells processed and 8100 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1428 NUM_FEPS 2 with 45 cells processed and 1982 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1428 NUM_FEPS 2 with 30 cells processed and 3000 slack improved
+OPT-0007 : Iter 4: improved WNS -968 TNS -1428 NUM_FEPS 2 with 33 cells processed and 2000 slack improved
+OPT-0007 : Iter 5: improved WNS -968 TNS -1428 NUM_FEPS 2 with 1 cells processed and 200 slack improved
+OPT-1001 : End global optimization;  3.284834s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (124.6%)
+
+OPT-1001 : Current memory(MB): used = 727, reserve = 726, peak = 770.
+OPT-1001 : End physical optimization;  14.780784s wall, 16.640625s user + 0.421875s system = 17.062500s CPU (115.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7491 LUT to BLE ...
+SYN-4008 : Packed 7491 LUT and 3177 SEQ to BLE.
+SYN-4003 : Packing 7493 remaining SEQ's ...
+SYN-4005 : Packed 4216 SEQ with LUT/SLICE
+SYN-4006 : 431 single LUT's are left
+SYN-4006 : 3277 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10768/14499 primitive instances ...
+PHY-3001 : End packing;  1.906055s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7297 instances
+RUN-1001 : 3575 mslices, 3574 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18921 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 11316 nets have 2 pins
+RUN-1001 : 5748 nets have [3 - 5] pins
+RUN-1001 : 1166 nets have [6 - 10] pins
+RUN-1001 : 336 nets have [11 - 20] pins
+RUN-1001 : 323 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 7295 instances, 7149 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 4158 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : After packing: Len = 670571, Over = 292.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7787/18921.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826808, over cnt = 1974(5%), over = 3277, worst = 8
+PHY-1002 : len = 834600, over cnt = 1284(3%), over = 1840, worst = 6
+PHY-1002 : len = 849216, over cnt = 454(1%), over = 636, worst = 6
+PHY-1002 : len = 855536, over cnt = 192(0%), over = 239, worst = 4
+PHY-1002 : len = 860568, over cnt = 10(0%), over = 10, worst = 1
+PHY-1001 : End global iterations;  1.624002s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (142.4%)
+
+PHY-1001 : Congestion index: top1 = 58.06, top5 = 51.67, top10 = 47.88, top15 = 45.56.
+PHY-3001 : End congestion estimation;  2.017558s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (134.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 77799, tnet num: 18743, tinst num: 7295, tnode num: 102845, tedge num: 130047.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.703844s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (100.0%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 648 MB, peak memory is 770 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18743 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.612671s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.34165e-05
+PHY-3002 : Step(289): len = 658609, overlap = 300
+PHY-3002 : Step(290): len = 653204, overlap = 292.5
+PHY-3002 : Step(291): len = 650262, overlap = 295.75
+PHY-3002 : Step(292): len = 648375, overlap = 308
+PHY-3002 : Step(293): len = 646492, overlap = 312.75
+PHY-3002 : Step(294): len = 644094, overlap = 310.25
+PHY-3002 : Step(295): len = 641633, overlap = 300.5
+PHY-3002 : Step(296): len = 640087, overlap = 308.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.68331e-05
+PHY-3002 : Step(297): len = 642396, overlap = 302.25
+PHY-3002 : Step(298): len = 647209, overlap = 301.75
+PHY-3002 : Step(299): len = 648254, overlap = 298.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000173666
+PHY-3002 : Step(300): len = 654871, overlap = 287.5
+PHY-3002 : Step(301): len = 662943, overlap = 276.5
+PHY-3002 : Step(302): len = 663103, overlap = 275
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.349320s wall, 0.343750s user + 0.578125s system = 0.921875s CPU (263.9%)
+
+PHY-3001 : Trial Legalized: Len = 828250
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 806/18921.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 943296, over cnt = 2884(8%), over = 4987, worst = 8
+PHY-1002 : len = 962648, over cnt = 1823(5%), over = 2693, worst = 8
+PHY-1002 : len = 975904, over cnt = 1155(3%), over = 1690, worst = 8
+PHY-1002 : len = 992136, over cnt = 526(1%), over = 797, worst = 6
+PHY-1002 : len = 1.00852e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.570000s wall, 3.562500s user + 0.015625s system = 3.578125s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 59.09, top5 = 53.71, top10 = 50.75, top15 = 48.76.
+PHY-3001 : End congestion estimation;  3.039281s wall, 4.046875s user + 0.015625s system = 4.062500s CPU (133.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18743 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.904185s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000154528
+PHY-3002 : Step(303): len = 789389, overlap = 68
+PHY-3002 : Step(304): len = 766553, overlap = 98
+PHY-3002 : Step(305): len = 751428, overlap = 120.25
+PHY-3002 : Step(306): len = 738709, overlap = 150
+PHY-3002 : Step(307): len = 728816, overlap = 166.25
+PHY-3002 : Step(308): len = 718291, overlap = 192
+PHY-3002 : Step(309): len = 713522, overlap = 199.25
+PHY-3002 : Step(310): len = 709279, overlap = 204.25
+PHY-3002 : Step(311): len = 705533, overlap = 209
+PHY-3002 : Step(312): len = 703444, overlap = 210.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000309056
+PHY-3002 : Step(313): len = 707870, overlap = 202.25
+PHY-3002 : Step(314): len = 711630, overlap = 201
+PHY-3002 : Step(315): len = 715262, overlap = 202
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000600707
+PHY-3002 : Step(316): len = 720626, overlap = 196.5
+PHY-3002 : Step(317): len = 728801, overlap = 195
+PHY-3002 : Step(318): len = 733292, overlap = 185.75
+PHY-3002 : Step(319): len = 734086, overlap = 190
+PHY-3002 : Step(320): len = 734799, overlap = 185.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.087773s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (106.8%)
+
+PHY-3001 : Legalized: Len = 804181, Over = 0
+PHY-3001 : Spreading special nets. 459 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.125836s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (111.8%)
+
+PHY-3001 : 710 instances has been re-located, deltaX = 298, deltaY = 476, maxDist = 7.
+PHY-3001 : Final: Len = 815365, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 77799, tnet num: 18743, tinst num: 7298, tnode num: 102845, tedge num: 130047.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.970572s wall, 1.921875s user + 0.046875s system = 1.968750s CPU (99.9%)
+
+RUN-1004 : used memory is 664 MB, reserved memory is 685 MB, peak memory is 770 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3035/18921.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 939824, over cnt = 2748(7%), over = 4612, worst = 7
+PHY-1002 : len = 955040, over cnt = 1748(4%), over = 2627, worst = 7
+PHY-1002 : len = 972112, over cnt = 887(2%), over = 1335, worst = 7
+PHY-1002 : len = 989752, over cnt = 227(0%), over = 346, worst = 7
+PHY-1002 : len = 995120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.165389s wall, 3.156250s user + 0.015625s system = 3.171875s CPU (146.5%)
+
+PHY-1001 : Congestion index: top1 = 57.41, top5 = 52.71, top10 = 49.83, top15 = 47.91.
+PHY-1001 : End incremental global routing;  2.563386s wall, 3.562500s user + 0.015625s system = 3.578125s CPU (139.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18743 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.908281s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.8%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7206 has valid locations, 18 needs to be replaced
+PHY-3001 : design contains 7312 instances, 7163 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 4216 pins
+PHY-3001 : Found 1562 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 817290
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17350/18932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 997272, over cnt = 59(0%), over = 65, worst = 3
+PHY-1002 : len = 997344, over cnt = 21(0%), over = 22, worst = 2
+PHY-1002 : len = 997536, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 997664, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 997680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.778731s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.3%)
+
+PHY-1001 : Congestion index: top1 = 57.50, top5 = 52.82, top10 = 49.91, top15 = 47.97.
+PHY-3001 : End congestion estimation;  1.106811s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (101.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 77909, tnet num: 18754, tinst num: 7312, tnode num: 102981, tedge num: 130181.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.932378s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (100.3%)
+
+RUN-1004 : used memory is 693 MB, reserved memory is 697 MB, peak memory is 770 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.858471s wall, 2.828125s user + 0.031250s system = 2.859375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(321): len = 816646, overlap = 0
+PHY-3002 : Step(322): len = 816476, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17336/18932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 996296, over cnt = 40(0%), over = 53, worst = 3
+PHY-1002 : len = 996408, over cnt = 15(0%), over = 16, worst = 2
+PHY-1002 : len = 996560, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 996616, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 996632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.759744s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (102.8%)
+
+PHY-1001 : Congestion index: top1 = 57.41, top5 = 52.77, top10 = 49.86, top15 = 47.93.
+PHY-3001 : End congestion estimation;  1.085049s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (102.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.259608s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000332247
+PHY-3002 : Step(323): len = 816424, overlap = 2
+PHY-3002 : Step(324): len = 816467, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005678s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 816651, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061802s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.1%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 2, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 816663, Over = 0
+PHY-3001 : End incremental placement;  6.790589s wall, 6.812500s user + 0.078125s system = 6.890625s CPU (101.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.762877s wall, 11.890625s user + 0.093750s system = 11.984375s CPU (111.3%)
+
+OPT-1001 : Current memory(MB): used = 773, reserve = 776, peak = 778.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17323/18932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 996760, over cnt = 30(0%), over = 34, worst = 3
+PHY-1002 : len = 996816, over cnt = 18(0%), over = 19, worst = 2
+PHY-1002 : len = 997008, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 997016, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.607708s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (105.4%)
+
+PHY-1001 : Congestion index: top1 = 57.46, top5 = 52.77, top10 = 49.85, top15 = 47.92.
+OPT-1001 : End congestion update;  0.934632s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (103.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.801383s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.4%)
+
+OPT-0007 : Start: WNS -986 TNS -1650 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7224 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7312 instances, 7163 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 4216 pins
+PHY-3001 : Found 1562 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 818373, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.067324s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (116.0%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 10, deltaY = 12, maxDist = 2.
+PHY-3001 : Final: Len = 818465, Over = 0
+PHY-3001 : End incremental legalization;  0.410251s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (99.0%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1471 NUM_FEPS 2 with 24 cells processed and 6250 slack improved
+OPT-0007 : Iter 2: improved WNS -986 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.298203s wall, 2.296875s user + 0.031250s system = 2.328125s CPU (101.3%)
+
+OPT-1001 : Current memory(MB): used = 773, reserve = 777, peak = 778.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.776777s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17227/18932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 998680, over cnt = 91(0%), over = 101, worst = 4
+PHY-1002 : len = 998600, over cnt = 53(0%), over = 53, worst = 1
+PHY-1002 : len = 998880, over cnt = 31(0%), over = 31, worst = 1
+PHY-1002 : len = 999512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.682471s wall, 0.687500s user + 0.015625s system = 0.703125s CPU (103.0%)
+
+PHY-1001 : Congestion index: top1 = 57.18, top5 = 52.79, top10 = 49.86, top15 = 47.93.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.774760s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -986 TNS -1471 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 56.689655
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -986ps with logic level 2 
+RUN-1001 :       #2 path slack -940ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 18932 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 18932 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7224 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7312 instances, 7163 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 4216 pins
+PHY-3001 : Found 1562 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 78%
+PHY-3001 : Initial: Len = 818465, Over = 0
+PHY-3001 : End spreading;  0.062110s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.6%)
+
+PHY-3001 : Final: Len = 818465, Over = 0
+PHY-3001 : End incremental legalization;  0.398752s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (129.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.756571s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.2%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17361/18932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 999512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.143148s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (109.2%)
+
+PHY-1001 : Congestion index: top1 = 57.18, top5 = 52.79, top10 = 49.86, top15 = 47.93.
+OPT-1001 : End congestion update;  0.483048s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.773105s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.0%)
+
+OPT-0007 : Start: WNS -986 TNS -1471 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -986 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.270374s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (99.6%)
+
+OPT-1001 : Current memory(MB): used = 774, reserve = 777, peak = 778.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17361/18932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 999512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.138144s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.8%)
+
+PHY-1001 : Congestion index: top1 = 57.18, top5 = 52.79, top10 = 49.86, top15 = 47.93.
+OPT-1001 : End congestion update;  0.478491s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.755933s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.2%)
+
+OPT-0007 : Start: WNS -986 TNS -1471 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -986 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -986 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.401436s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (100.3%)
+
+OPT-1001 : Current memory(MB): used = 774, reserve = 777, peak = 778.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.780990s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 774, reserve = 777, peak = 778.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.779369s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17361/18932.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 999512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.136882s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 57.18, top5 = 52.79, top10 = 49.86, top15 = 47.93.
+RUN-1001 : End congestion update;  0.463969s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.0%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.247154s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.2%)
+
+OPT-1001 : Current memory(MB): used = 774, reserve = 777, peak = 778.
+OPT-1001 : End physical optimization;  24.075189s wall, 25.265625s user + 0.187500s system = 25.453125s CPU (105.7%)
+
+RUN-1003 : finish command "place" in  70.812174s wall, 107.531250s user + 6.343750s system = 113.875000s CPU (160.8%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 636 MB, peak memory is 778 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.761990s wall, 3.062500s user + 0.000000s system = 3.062500s CPU (173.8%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 637 MB, peak memory is 778 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7314 instances
+RUN-1001 : 3589 mslices, 3574 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18932 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 11308 nets have 2 pins
+RUN-1001 : 5747 nets have [3 - 5] pins
+RUN-1001 : 1175 nets have [6 - 10] pins
+RUN-1001 : 339 nets have [11 - 20] pins
+RUN-1001 : 335 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 77909, tnet num: 18754, tinst num: 7312, tnode num: 102981, tedge num: 130181.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.646020s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.7%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 670 MB, peak memory is 778 MB
+PHY-1001 : 3589 mslices, 3574 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 922312, over cnt = 2990(8%), over = 4944, worst = 8
+PHY-1002 : len = 943184, over cnt = 1777(5%), over = 2519, worst = 7
+PHY-1002 : len = 961288, over cnt = 857(2%), over = 1190, worst = 7
+PHY-1002 : len = 980840, over cnt = 20(0%), over = 25, worst = 3
+PHY-1002 : len = 981704, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.305123s wall, 4.453125s user + 0.031250s system = 4.484375s CPU (135.7%)
+
+PHY-1001 : Congestion index: top1 = 57.24, top5 = 52.32, top10 = 49.50, top15 = 47.37.
+PHY-1001 : End global routing;  3.654044s wall, 4.781250s user + 0.046875s system = 4.828125s CPU (132.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 745, reserve = 751, peak = 778.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1021, reserve = 1028, peak = 1021.
+PHY-1001 : End build detailed router design. 4.056290s wall, 4.046875s user + 0.000000s system = 4.046875s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 265896, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.972843s wall, 4.953125s user + 0.000000s system = 4.953125s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 265952, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.436870s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1057, reserve = 1065, peak = 1057.
+PHY-1001 : End phase 1; 5.421879s wall, 5.406250s user + 0.000000s system = 5.406250s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.40226e+06, over cnt = 2431(0%), over = 2437, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1074, reserve = 1079, peak = 1074.
+PHY-1001 : End initial routed; 25.295223s wall, 52.093750s user + 0.453125s system = 52.546875s CPU (207.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17855(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.013   |  -3.917   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.366878s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1083, reserve = 1090, peak = 1083.
+PHY-1001 : End phase 2; 28.662166s wall, 55.468750s user + 0.453125s system = 55.921875s CPU (195.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.893ns STNS -3.797ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.144706s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (108.0%)
+
+PHY-1022 : len = 2.40227e+06, over cnt = 2432(0%), over = 2438, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.417932s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.35929e+06, over cnt = 988(0%), over = 988, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.802983s wall, 4.250000s user + 0.000000s system = 4.250000s CPU (151.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.35278e+06, over cnt = 217(0%), over = 217, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.342948s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (137.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.35405e+06, over cnt = 29(0%), over = 29, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.546698s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (134.3%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.35472e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.258049s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (115.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.35483e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.228125s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (102.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.35483e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.247908s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.35483e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.325883s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.35483e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.178293s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.4%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.35491e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.182682s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (119.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17855(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.893   |  -3.797   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.377191s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 768 feed throughs used by 544 nets
+PHY-1001 : End commit to database; 2.311065s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1192, reserve = 1202, peak = 1192.
+PHY-1001 : End phase 3; 12.643192s wall, 14.812500s user + 0.031250s system = 14.843750s CPU (117.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.893ns STNS -3.797ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.144551s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.3%)
+
+PHY-1022 : len = 2.35491e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.403959s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.893ns, -3.797ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17855(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.893   |  -3.797   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.387085s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 768 feed throughs used by 544 nets
+PHY-1001 : End commit to database; 2.392713s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1202, reserve = 1213, peak = 1202.
+PHY-1001 : End phase 4; 6.212465s wall, 6.218750s user + 0.000000s system = 6.218750s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.35491e+06
+PHY-1001 : Current memory(MB): used = 1204, reserve = 1215, peak = 1204.
+PHY-1001 : End export database. 0.062356s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.2%)
+
+PHY-1001 : End detail routing;  57.461860s wall, 86.406250s user + 0.484375s system = 86.890625s CPU (151.2%)
+
+RUN-1003 : finish command "route" in  63.880789s wall, 93.953125s user + 0.531250s system = 94.484375s CPU (147.9%)
+
+RUN-1004 : used memory is 1125 MB, reserved memory is 1133 MB, peak memory is 1204 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10251   out of  19600   52.30%
+#reg                    10808   out of  19600   55.14%
+#le                     13427
+  #lut only              2619   out of  13427   19.51%
+  #reg only              3176   out of  13427   23.65%
+  #lut&reg               7632   out of  13427   56.84%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1792
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1723
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1666
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               927
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    136
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         76
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg1_syn_175.f0                          3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_softrst_done/reg0_syn_27.f0                      3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P147       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P109       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P82        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P71        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |13427  |9224    |1027    |10840   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |543    |432     |23      |447     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |97     |84      |4       |90      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |30     |30      |0       |18      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |8       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |787    |347     |96      |586     |0       |0       |
+|    u_ADconfig                |AD_config            |185    |115     |25      |142     |0       |0       |
+|    u_gen_sp                  |gen_sp               |281    |170     |71      |123     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |755    |367     |96      |569     |0       |0       |
+|    u_ADconfig                |AD_config            |185    |110     |25      |133     |0       |0       |
+|    u_gen_sp                  |gen_sp               |252    |146     |71      |118     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3471   |2539    |306     |2767    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |6       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |192    |120     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |3242   |2411    |289     |2584    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |6      |2       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |2       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2739   |2061    |253     |2151    |22      |0       |
+|        channelPart           |channel_part_8478    |120    |107     |3       |113     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |1615   |1280    |197     |1133    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |200    |173     |27      |126     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |16      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |13      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|          insert              |insert               |982    |674     |170     |702     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |433    |433     |0       |305     |0       |0       |
+|        read_ram_i            |read_ram             |283    |239     |44      |202     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |222    |182     |40      |156     |0       |0       |
+|          read_ram_data       |read_ram_data        |54     |50      |4       |39      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |7      |7       |0       |7       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |333    |232     |36      |288     |3       |0       |
+|        u0_soft_n             |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3762   |2817    |349     |2753    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |185    |105     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |3546   |2703    |332     |2574    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |3       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |3050   |2346    |290     |2168    |22      |1       |
+|        channelPart           |channel_part_8478    |273    |269     |3       |138     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |42      |0       |1       |
+|        ram_switch            |ram_switch           |1716   |1261    |197     |1136    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |201    |174     |27      |118     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |10     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |15      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |17      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |7       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|          insert              |insert               |992    |564     |170     |699     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |523    |523     |0       |319     |0       |0       |
+|        read_ram_i            |read_ram_rev         |358    |245     |81      |208     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |287    |202     |73      |157     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |71     |43      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       11246  
+    #2         2       3816   
+    #3         3       1355   
+    #4         4        573   
+    #5        5-10     1231   
+    #6       11-50      589   
+    #7       51-100     26    
+    #8        >500       1    
+  Average     2.81            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.164978s wall, 3.750000s user + 0.015625s system = 3.765625s CPU (173.9%)
+
+RUN-1004 : used memory is 1126 MB, reserved memory is 1134 MB, peak memory is 1204 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 77909, tnet num: 18754, tinst num: 7312, tnode num: 102981, tedge num: 130181.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.685149s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.1%)
+
+RUN-1004 : used memory is 1132 MB, reserved memory is 1139 MB, peak memory is 1204 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18754 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.533091s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (99.9%)
+
+RUN-1004 : used memory is 1135 MB, reserved memory is 1142 MB, peak memory is 1204 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7312
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18932, pip num: 179285
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 768
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3243 valid insts, and 498180 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.128767s wall, 66.906250s user + 0.156250s system = 67.062500s CPU (662.1%)
+
+RUN-1004 : used memory is 1307 MB, reserved memory is 1312 MB, peak memory is 1422 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_140815.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_141745.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_141745.log
new file mode 100644
index 0000000..4a59418
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_141745.log
@@ -0,0 +1,1953 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:17:45 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.219480s wall, 2.078125s user + 0.140625s system = 2.218750s CPU (100.0%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 322 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2703 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2937 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2777 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18503 instances
+RUN-0007 : 7140 luts, 10255 seqs, 626 mslices, 334 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20860 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14207 nets have 2 pins
+RUN-1001 : 5235 nets have [3 - 5] pins
+RUN-1001 : 1020 nets have [6 - 10] pins
+RUN-1001 : 150 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 51 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     782     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4886     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2483     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  75   |     55     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 139
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18501 instances, 7140 luts, 10255 seqs, 960 slices, 197 macros(960 instances: 626 mslices 334 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_721 with 7006 pins
+PHY-0007 : Cell area utilization is 52%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87139, tnet num: 20682, tinst num: 18501, tnode num: 120600, tedge num: 139000.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.152913s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (98.9%)
+
+RUN-1004 : used memory is 545 MB, reserved memory is 529 MB, peak memory is 545 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20682 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.946789s wall, 1.890625s user + 0.046875s system = 1.937500s CPU (99.5%)
+
+PHY-3001 : Found 3478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.88661e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18501.
+PHY-3001 : Level 1 #clusters 2119.
+PHY-3001 : End clustering;  0.248110s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (94.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 52%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.1875e+06, overlap = 516.156
+PHY-3002 : Step(2): len = 1.08956e+06, overlap = 562.531
+PHY-3002 : Step(3): len = 775658, overlap = 665.219
+PHY-3002 : Step(4): len = 665819, overlap = 726.812
+PHY-3002 : Step(5): len = 532258, overlap = 833.188
+PHY-3002 : Step(6): len = 495359, overlap = 888.469
+PHY-3002 : Step(7): len = 418711, overlap = 993.594
+PHY-3002 : Step(8): len = 380299, overlap = 1053.59
+PHY-3002 : Step(9): len = 337563, overlap = 1096.34
+PHY-3002 : Step(10): len = 304456, overlap = 1140.03
+PHY-3002 : Step(11): len = 278552, overlap = 1160.97
+PHY-3002 : Step(12): len = 259090, overlap = 1210.66
+PHY-3002 : Step(13): len = 242295, overlap = 1269.28
+PHY-3002 : Step(14): len = 229791, overlap = 1297.75
+PHY-3002 : Step(15): len = 211352, overlap = 1325.31
+PHY-3002 : Step(16): len = 196045, overlap = 1386.31
+PHY-3002 : Step(17): len = 178989, overlap = 1419.97
+PHY-3002 : Step(18): len = 168246, overlap = 1447
+PHY-3002 : Step(19): len = 156616, overlap = 1461.22
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.67325e-07
+PHY-3002 : Step(20): len = 157264, overlap = 1440.56
+PHY-3002 : Step(21): len = 188734, overlap = 1350.38
+PHY-3002 : Step(22): len = 194794, overlap = 1321.59
+PHY-3002 : Step(23): len = 198503, overlap = 1275.16
+PHY-3002 : Step(24): len = 198244, overlap = 1221.34
+PHY-3002 : Step(25): len = 197552, overlap = 1184.97
+PHY-3002 : Step(26): len = 195846, overlap = 1151.84
+PHY-3002 : Step(27): len = 192555, overlap = 1157.84
+PHY-3002 : Step(28): len = 190108, overlap = 1181.25
+PHY-3002 : Step(29): len = 185435, overlap = 1202.44
+PHY-3002 : Step(30): len = 181809, overlap = 1207.66
+PHY-3002 : Step(31): len = 178370, overlap = 1197.69
+PHY-3002 : Step(32): len = 176311, overlap = 1187.84
+PHY-3002 : Step(33): len = 173986, overlap = 1173.59
+PHY-3002 : Step(34): len = 173796, overlap = 1171.12
+PHY-3002 : Step(35): len = 172618, overlap = 1190.41
+PHY-3002 : Step(36): len = 171792, overlap = 1196.72
+PHY-3002 : Step(37): len = 170430, overlap = 1175.91
+PHY-3002 : Step(38): len = 170102, overlap = 1162.34
+PHY-3002 : Step(39): len = 169028, overlap = 1157.97
+PHY-3002 : Step(40): len = 168241, overlap = 1164.81
+PHY-3002 : Step(41): len = 167310, overlap = 1192.03
+PHY-3002 : Step(42): len = 166188, overlap = 1183.72
+PHY-3002 : Step(43): len = 165346, overlap = 1189.28
+PHY-3002 : Step(44): len = 163333, overlap = 1194.53
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.73465e-06
+PHY-3002 : Step(45): len = 165408, overlap = 1171.94
+PHY-3002 : Step(46): len = 176148, overlap = 1163.53
+PHY-3002 : Step(47): len = 181331, overlap = 1188.59
+PHY-3002 : Step(48): len = 184151, overlap = 1179.59
+PHY-3002 : Step(49): len = 185180, overlap = 1163.91
+PHY-3002 : Step(50): len = 185990, overlap = 1156.03
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.4693e-06
+PHY-3002 : Step(51): len = 191051, overlap = 1126.22
+PHY-3002 : Step(52): len = 202047, overlap = 1096.12
+PHY-3002 : Step(53): len = 209604, overlap = 995
+PHY-3002 : Step(54): len = 217585, overlap = 933.875
+PHY-3002 : Step(55): len = 222421, overlap = 916.531
+PHY-3002 : Step(56): len = 226065, overlap = 904.312
+PHY-3002 : Step(57): len = 228446, overlap = 870.875
+PHY-3002 : Step(58): len = 228318, overlap = 867.406
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.9386e-06
+PHY-3002 : Step(59): len = 239426, overlap = 883.906
+PHY-3002 : Step(60): len = 259466, overlap = 826.312
+PHY-3002 : Step(61): len = 265028, overlap = 766.75
+PHY-3002 : Step(62): len = 268152, overlap = 746.125
+PHY-3002 : Step(63): len = 269775, overlap = 727.188
+PHY-3002 : Step(64): len = 271053, overlap = 712.625
+PHY-3002 : Step(65): len = 271159, overlap = 690.438
+PHY-3002 : Step(66): len = 270412, overlap = 679.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.38772e-05
+PHY-3002 : Step(67): len = 287327, overlap = 625.25
+PHY-3002 : Step(68): len = 305900, overlap = 541.719
+PHY-3002 : Step(69): len = 311807, overlap = 501.469
+PHY-3002 : Step(70): len = 315964, overlap = 475.281
+PHY-3002 : Step(71): len = 317799, overlap = 463.125
+PHY-3002 : Step(72): len = 318795, overlap = 455.25
+PHY-3002 : Step(73): len = 317176, overlap = 446.969
+PHY-3002 : Step(74): len = 316057, overlap = 440.062
+PHY-3002 : Step(75): len = 313911, overlap = 436.75
+PHY-3002 : Step(76): len = 312332, overlap = 435.219
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.77544e-05
+PHY-3002 : Step(77): len = 329820, overlap = 414.156
+PHY-3002 : Step(78): len = 341164, overlap = 397.656
+PHY-3002 : Step(79): len = 342890, overlap = 386.906
+PHY-3002 : Step(80): len = 345210, overlap = 369.375
+PHY-3002 : Step(81): len = 346033, overlap = 377
+PHY-3002 : Step(82): len = 347427, overlap = 368.094
+PHY-3002 : Step(83): len = 345819, overlap = 356.781
+PHY-3002 : Step(84): len = 346137, overlap = 348.156
+PHY-3002 : Step(85): len = 347037, overlap = 344.156
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.55088e-05
+PHY-3002 : Step(86): len = 363086, overlap = 328.844
+PHY-3002 : Step(87): len = 375785, overlap = 279.219
+PHY-3002 : Step(88): len = 376709, overlap = 267.375
+PHY-3002 : Step(89): len = 378904, overlap = 261.125
+PHY-3002 : Step(90): len = 382077, overlap = 256.062
+PHY-3002 : Step(91): len = 384695, overlap = 259.5
+PHY-3002 : Step(92): len = 381240, overlap = 262.531
+PHY-3002 : Step(93): len = 380421, overlap = 260.625
+PHY-3002 : Step(94): len = 381574, overlap = 269.656
+PHY-3002 : Step(95): len = 384713, overlap = 248.469
+PHY-3002 : Step(96): len = 381821, overlap = 270.281
+PHY-3002 : Step(97): len = 381288, overlap = 263.875
+PHY-3002 : Step(98): len = 381793, overlap = 256.25
+PHY-3002 : Step(99): len = 383063, overlap = 248.094
+PHY-3002 : Step(100): len = 380894, overlap = 249.75
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000110492
+PHY-3002 : Step(101): len = 394172, overlap = 234.656
+PHY-3002 : Step(102): len = 401680, overlap = 229.812
+PHY-3002 : Step(103): len = 398989, overlap = 234.219
+PHY-3002 : Step(104): len = 402000, overlap = 244.5
+PHY-3002 : Step(105): len = 405527, overlap = 228.844
+PHY-3002 : Step(106): len = 408914, overlap = 226.781
+PHY-3002 : Step(107): len = 406786, overlap = 238.531
+PHY-3002 : Step(108): len = 406807, overlap = 241.656
+PHY-3002 : Step(109): len = 409371, overlap = 236
+PHY-3002 : Step(110): len = 410990, overlap = 231.312
+PHY-3002 : Step(111): len = 408705, overlap = 232.719
+PHY-3002 : Step(112): len = 408893, overlap = 229
+PHY-3002 : Step(113): len = 409838, overlap = 221.562
+PHY-3002 : Step(114): len = 410839, overlap = 210.062
+PHY-3002 : Step(115): len = 409276, overlap = 199.781
+PHY-3002 : Step(116): len = 409884, overlap = 200.062
+PHY-3002 : Step(117): len = 410690, overlap = 189.312
+PHY-3002 : Step(118): len = 411085, overlap = 184.688
+PHY-3002 : Step(119): len = 409330, overlap = 188.031
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000202318
+PHY-3002 : Step(120): len = 417690, overlap = 176.875
+PHY-3002 : Step(121): len = 423215, overlap = 178.812
+PHY-3002 : Step(122): len = 422955, overlap = 179.906
+PHY-3002 : Step(123): len = 424872, overlap = 174.312
+PHY-3002 : Step(124): len = 428020, overlap = 178.344
+PHY-3002 : Step(125): len = 430759, overlap = 182.156
+PHY-3002 : Step(126): len = 428336, overlap = 180.75
+PHY-3002 : Step(127): len = 427915, overlap = 189.344
+PHY-3002 : Step(128): len = 429591, overlap = 190.312
+PHY-3002 : Step(129): len = 431418, overlap = 194.594
+PHY-3002 : Step(130): len = 428882, overlap = 200.562
+PHY-3002 : Step(131): len = 428742, overlap = 203.938
+PHY-3002 : Step(132): len = 430591, overlap = 199.688
+PHY-3002 : Step(133): len = 431740, overlap = 197.281
+PHY-3002 : Step(134): len = 430008, overlap = 201.188
+PHY-3002 : Step(135): len = 429912, overlap = 192.469
+PHY-3002 : Step(136): len = 431059, overlap = 191.062
+PHY-3002 : Step(137): len = 432123, overlap = 199.844
+PHY-3002 : Step(138): len = 431047, overlap = 191.531
+PHY-3002 : Step(139): len = 431509, overlap = 190.562
+PHY-3002 : Step(140): len = 432938, overlap = 185.844
+PHY-3002 : Step(141): len = 434500, overlap = 180.625
+PHY-3002 : Step(142): len = 432483, overlap = 184.656
+PHY-3002 : Step(143): len = 432217, overlap = 181.844
+PHY-3002 : Step(144): len = 433396, overlap = 180.594
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000404636
+PHY-3002 : Step(145): len = 439196, overlap = 172.438
+PHY-3002 : Step(146): len = 445340, overlap = 158.75
+PHY-3002 : Step(147): len = 444859, overlap = 155.094
+PHY-3002 : Step(148): len = 446094, overlap = 154.281
+PHY-3002 : Step(149): len = 449155, overlap = 157.719
+PHY-3002 : Step(150): len = 451988, overlap = 164.25
+PHY-3002 : Step(151): len = 450083, overlap = 160.344
+PHY-3002 : Step(152): len = 449223, overlap = 163.969
+PHY-3002 : Step(153): len = 450376, overlap = 164.812
+PHY-3002 : Step(154): len = 451716, overlap = 165.969
+PHY-3002 : Step(155): len = 449936, overlap = 171.531
+PHY-3002 : Step(156): len = 450194, overlap = 171.594
+PHY-3002 : Step(157): len = 451992, overlap = 167.188
+PHY-3002 : Step(158): len = 453100, overlap = 162.438
+PHY-3002 : Step(159): len = 451487, overlap = 166.219
+PHY-3002 : Step(160): len = 451125, overlap = 167.344
+PHY-3002 : Step(161): len = 451844, overlap = 167.188
+PHY-3002 : Step(162): len = 452052, overlap = 167.562
+PHY-3002 : Step(163): len = 451302, overlap = 163.219
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00073729
+PHY-3002 : Step(164): len = 454628, overlap = 166.562
+PHY-3002 : Step(165): len = 458281, overlap = 166.719
+PHY-3002 : Step(166): len = 458953, overlap = 167.875
+PHY-3002 : Step(167): len = 460562, overlap = 165.531
+PHY-3002 : Step(168): len = 462161, overlap = 162.531
+PHY-3002 : Step(169): len = 462961, overlap = 162.969
+PHY-3002 : Step(170): len = 461666, overlap = 164.219
+PHY-3002 : Step(171): len = 461209, overlap = 159.625
+PHY-3002 : Step(172): len = 462255, overlap = 157.5
+PHY-3002 : Step(173): len = 463184, overlap = 155.25
+PHY-3002 : Step(174): len = 462201, overlap = 150.781
+PHY-3002 : Step(175): len = 462212, overlap = 150.469
+PHY-3002 : Step(176): len = 463582, overlap = 151.062
+PHY-3002 : Step(177): len = 464356, overlap = 153.562
+PHY-3002 : Step(178): len = 463470, overlap = 150.375
+PHY-3002 : Step(179): len = 462892, overlap = 148.688
+PHY-3002 : Step(180): len = 463799, overlap = 153.562
+PHY-3002 : Step(181): len = 464245, overlap = 151.844
+PHY-3002 : Step(182): len = 463528, overlap = 148.938
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00125127
+PHY-3002 : Step(183): len = 465612, overlap = 152.656
+PHY-3002 : Step(184): len = 467135, overlap = 153.375
+PHY-3002 : Step(185): len = 467219, overlap = 156.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014906s wall, 0.031250s user + 0.046875s system = 0.078125s CPU (524.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20860.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 603536, over cnt = 1439(4%), over = 6779, worst = 36
+PHY-1001 : End global iterations;  0.669040s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (144.8%)
+
+PHY-1001 : Congestion index: top1 = 80.71, top5 = 60.09, top10 = 50.81, top15 = 45.00.
+PHY-3001 : End congestion estimation;  0.908574s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (132.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20682 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.855636s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000104788
+PHY-3002 : Step(186): len = 546375, overlap = 103.719
+PHY-3002 : Step(187): len = 550228, overlap = 88.4375
+PHY-3002 : Step(188): len = 553035, overlap = 89.7812
+PHY-3002 : Step(189): len = 552571, overlap = 93.0938
+PHY-3002 : Step(190): len = 552305, overlap = 95.875
+PHY-3002 : Step(191): len = 555688, overlap = 86.5938
+PHY-3002 : Step(192): len = 567011, overlap = 77.1562
+PHY-3002 : Step(193): len = 576354, overlap = 69.4375
+PHY-3002 : Step(194): len = 578006, overlap = 68.7188
+PHY-3002 : Step(195): len = 577687, overlap = 67.2812
+PHY-3002 : Step(196): len = 578581, overlap = 57.5625
+PHY-3002 : Step(197): len = 579155, overlap = 56.3125
+PHY-3002 : Step(198): len = 578142, overlap = 54.0938
+PHY-3002 : Step(199): len = 576359, overlap = 55.9375
+PHY-3002 : Step(200): len = 575556, overlap = 57.2188
+PHY-3002 : Step(201): len = 575288, overlap = 60.5
+PHY-3002 : Step(202): len = 574252, overlap = 64.5
+PHY-3002 : Step(203): len = 571932, overlap = 64.6875
+PHY-3002 : Step(204): len = 570077, overlap = 65.1562
+PHY-3002 : Step(205): len = 569328, overlap = 66.8125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000209577
+PHY-3002 : Step(206): len = 570571, overlap = 66.2812
+PHY-3002 : Step(207): len = 576494, overlap = 65.8438
+PHY-3002 : Step(208): len = 579862, overlap = 65.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000419153
+PHY-3002 : Step(209): len = 584677, overlap = 64.2188
+PHY-3002 : Step(210): len = 596773, overlap = 60.875
+PHY-3002 : Step(211): len = 605503, overlap = 57.9062
+PHY-3002 : Step(212): len = 608666, overlap = 61.8125
+PHY-3002 : Step(213): len = 610855, overlap = 63.625
+PHY-3002 : Step(214): len = 610800, overlap = 61.9375
+PHY-3002 : Step(215): len = 611135, overlap = 64.25
+PHY-3002 : Step(216): len = 612660, overlap = 67.5938
+PHY-3002 : Step(217): len = 614040, overlap = 70.4688
+PHY-3002 : Step(218): len = 613070, overlap = 69.7188
+PHY-3002 : Step(219): len = 611546, overlap = 67.875
+PHY-3002 : Step(220): len = 609832, overlap = 65.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000837296
+PHY-3002 : Step(221): len = 614355, overlap = 65.75
+PHY-3002 : Step(222): len = 620899, overlap = 68.3438
+PHY-3002 : Step(223): len = 629506, overlap = 68.0312
+PHY-3002 : Step(224): len = 637383, overlap = 63.8438
+PHY-3002 : Step(225): len = 638754, overlap = 65.9062
+PHY-3002 : Step(226): len = 640213, overlap = 63.625
+PHY-3002 : Step(227): len = 639751, overlap = 65.0312
+PHY-3002 : Step(228): len = 639492, overlap = 68.75
+PHY-3002 : Step(229): len = 638617, overlap = 71.75
+PHY-3002 : Step(230): len = 638516, overlap = 70
+PHY-3002 : Step(231): len = 639125, overlap = 69.9062
+PHY-3002 : Step(232): len = 639397, overlap = 70.75
+PHY-3002 : Step(233): len = 638349, overlap = 70.0938
+PHY-3002 : Step(234): len = 636610, overlap = 68.4688
+PHY-3002 : Step(235): len = 636028, overlap = 68.4688
+PHY-3002 : Step(236): len = 634464, overlap = 69.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00141305
+PHY-3002 : Step(237): len = 636339, overlap = 68.625
+PHY-3002 : Step(238): len = 639381, overlap = 72.3125
+PHY-3002 : Step(239): len = 642067, overlap = 70.8125
+PHY-3002 : Step(240): len = 646622, overlap = 69.5938
+PHY-3002 : Step(241): len = 651082, overlap = 71.375
+PHY-3002 : Step(242): len = 651901, overlap = 69.6562
+PHY-3002 : Step(243): len = 651906, overlap = 76.1875
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00245803
+PHY-3002 : Step(244): len = 652275, overlap = 71.0938
+PHY-3002 : Step(245): len = 653932, overlap = 67.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 24/20860.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719352, over cnt = 2683(7%), over = 14373, worst = 53
+PHY-1001 : End global iterations;  1.338886s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 108.04, top5 = 77.80, top10 = 65.85, top15 = 58.90.
+PHY-3001 : End congestion estimation;  1.614682s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (137.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20682 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.882671s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000104958
+PHY-3002 : Step(246): len = 654734, overlap = 268.25
+PHY-3002 : Step(247): len = 653450, overlap = 212.938
+PHY-3002 : Step(248): len = 645336, overlap = 190.406
+PHY-3002 : Step(249): len = 637401, overlap = 180.188
+PHY-3002 : Step(250): len = 631356, overlap = 165.938
+PHY-3002 : Step(251): len = 626634, overlap = 161.812
+PHY-3002 : Step(252): len = 621767, overlap = 157.562
+PHY-3002 : Step(253): len = 616080, overlap = 159
+PHY-3002 : Step(254): len = 612838, overlap = 160
+PHY-3002 : Step(255): len = 609757, overlap = 156.188
+PHY-3002 : Step(256): len = 606945, overlap = 153.25
+PHY-3002 : Step(257): len = 602799, overlap = 147.188
+PHY-3002 : Step(258): len = 599177, overlap = 142.469
+PHY-3002 : Step(259): len = 594008, overlap = 138.812
+PHY-3002 : Step(260): len = 590294, overlap = 134.969
+PHY-3002 : Step(261): len = 586579, overlap = 136.281
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000209917
+PHY-3002 : Step(262): len = 587490, overlap = 131.688
+PHY-3002 : Step(263): len = 590062, overlap = 129.875
+PHY-3002 : Step(264): len = 591528, overlap = 123.906
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000419834
+PHY-3002 : Step(265): len = 593444, overlap = 118.938
+PHY-3002 : Step(266): len = 598789, overlap = 110.188
+PHY-3002 : Step(267): len = 604191, overlap = 102.25
+PHY-3002 : Step(268): len = 604742, overlap = 102.312
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87139, tnet num: 20682, tinst num: 18501, tnode num: 120600, tedge num: 139000.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.495895s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (98.2%)
+
+RUN-1004 : used memory is 588 MB, reserved memory is 577 MB, peak memory is 727 MB
+OPT-1001 : Total overflow 442.41 peak overflow 3.62
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 474/20860.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 688152, over cnt = 2967(8%), over = 10746, worst = 30
+PHY-1001 : End global iterations;  1.448551s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (137.0%)
+
+PHY-1001 : Congestion index: top1 = 67.33, top5 = 54.82, top10 = 49.48, top15 = 46.37.
+PHY-1001 : End incremental global routing;  1.769214s wall, 2.265625s user + 0.031250s system = 2.296875s CPU (129.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20682 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.916992s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.5%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18369 has valid locations, 307 needs to be replaced
+PHY-3001 : design contains 18761 instances, 7210 luts, 10445 seqs, 960 slices, 197 macros(960 instances: 626 mslices 334 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_721 with 7145 pins
+PHY-3001 : Found 3512 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 624203
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 61%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17069/21120.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 701904, over cnt = 3017(8%), over = 10852, worst = 31
+PHY-1001 : End global iterations;  0.229151s wall, 0.312500s user + 0.031250s system = 0.343750s CPU (150.0%)
+
+PHY-1001 : Congestion index: top1 = 67.63, top5 = 55.29, top10 = 50.00, top15 = 46.84.
+PHY-3001 : End congestion estimation;  0.469079s wall, 0.546875s user + 0.031250s system = 0.578125s CPU (123.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88198, tnet num: 20942, tinst num: 18761, tnode num: 122276, tedge num: 140598.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.773743s wall, 1.750000s user + 0.015625s system = 1.765625s CPU (99.5%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 639 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20942 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  3.086528s wall, 3.046875s user + 0.031250s system = 3.078125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(269): len = 623226, overlap = 0.5
+PHY-3002 : Step(270): len = 622922, overlap = 0.4375
+PHY-3002 : Step(271): len = 622593, overlap = 0.4375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 61%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17153/21120.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700184, over cnt = 3009(8%), over = 10865, worst = 30
+PHY-1001 : End global iterations;  0.180678s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (112.4%)
+
+PHY-1001 : Congestion index: top1 = 67.80, top5 = 55.44, top10 = 50.08, top15 = 46.90.
+PHY-3001 : End congestion estimation;  0.420669s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (107.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20942 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.923531s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000245087
+PHY-3002 : Step(272): len = 622358, overlap = 104.875
+PHY-3002 : Step(273): len = 622423, overlap = 104.875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000490174
+PHY-3002 : Step(274): len = 622564, overlap = 104.469
+PHY-3002 : Step(275): len = 623139, overlap = 104.312
+PHY-3001 : Final: Len = 623139, Over = 104.312
+PHY-3001 : End incremental placement;  5.527772s wall, 5.734375s user + 0.140625s system = 5.875000s CPU (106.3%)
+
+OPT-1001 : Total overflow 447.62 peak overflow 3.62
+OPT-1001 : End high-fanout net optimization;  8.739118s wall, 9.437500s user + 0.187500s system = 9.625000s CPU (110.1%)
+
+OPT-1001 : Current memory(MB): used = 734, reserve = 728, peak = 752.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17113/21120.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 702384, over cnt = 2900(8%), over = 9892, worst = 30
+PHY-1002 : len = 753624, over cnt = 2073(5%), over = 5130, worst = 18
+PHY-1002 : len = 786896, over cnt = 1035(2%), over = 2389, worst = 15
+PHY-1002 : len = 808200, over cnt = 569(1%), over = 1193, worst = 13
+PHY-1002 : len = 830656, over cnt = 4(0%), over = 6, worst = 2
+PHY-1001 : End global iterations;  1.737628s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (137.6%)
+
+PHY-1001 : Congestion index: top1 = 55.00, top5 = 49.42, top10 = 46.40, top15 = 44.35.
+OPT-1001 : End congestion update;  1.986163s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (132.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20942 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.798788s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1118 TNS -1778 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1678 NUM_FEPS 2 with 49 cells processed and 8650 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1678 NUM_FEPS 2 with 34 cells processed and 2468 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1678 NUM_FEPS 2 with 23 cells processed and 1836 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1678 NUM_FEPS 2 with 19 cells processed and 550 slack improved
+OPT-1001 : End global optimization;  2.829575s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (122.6%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 712, peak = 752.
+OPT-1001 : End physical optimization;  13.804889s wall, 15.187500s user + 0.203125s system = 15.390625s CPU (111.5%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7210 LUT to BLE ...
+SYN-4008 : Packed 7210 LUT and 2923 SEQ to BLE.
+SYN-4003 : Packing 7522 remaining SEQ's ...
+SYN-4005 : Packed 4162 SEQ with LUT/SLICE
+SYN-4006 : 413 single LUT's are left
+SYN-4006 : 3360 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10570/14186 primitive instances ...
+PHY-3001 : End packing;  1.797610s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7040 instances
+RUN-1001 : 3446 mslices, 3446 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18323 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 11020 nets have 2 pins
+RUN-1001 : 5491 nets have [3 - 5] pins
+RUN-1001 : 1183 nets have [6 - 10] pins
+RUN-1001 : 273 nets have [11 - 20] pins
+RUN-1001 : 323 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 7038 instances, 6892 slices, 197 macros(960 instances: 626 mslices 334 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_721 with 4056 pins
+PHY-3001 : Found 1589 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 634448, Over = 317.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7467/18323.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 779560, over cnt = 1960(5%), over = 3313, worst = 8
+PHY-1002 : len = 787680, over cnt = 1205(3%), over = 1772, worst = 7
+PHY-1002 : len = 802184, over cnt = 400(1%), over = 553, worst = 7
+PHY-1002 : len = 808624, over cnt = 111(0%), over = 163, worst = 7
+PHY-1002 : len = 812232, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.598297s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 55.28, top5 = 48.85, top10 = 45.67, top15 = 43.50.
+PHY-3001 : End congestion estimation;  1.981234s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (136.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74917, tnet num: 18145, tinst num: 7038, tnode num: 99331, tedge num: 124678.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.605509s wall, 1.546875s user + 0.046875s system = 1.593750s CPU (99.3%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 628 MB, peak memory is 752 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18145 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.463167s wall, 2.375000s user + 0.078125s system = 2.453125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 3.94289e-05
+PHY-3002 : Step(276): len = 625051, overlap = 309.75
+PHY-3002 : Step(277): len = 618252, overlap = 303.75
+PHY-3002 : Step(278): len = 613287, overlap = 301.5
+PHY-3002 : Step(279): len = 610039, overlap = 294
+PHY-3002 : Step(280): len = 607167, overlap = 291.5
+PHY-3002 : Step(281): len = 603703, overlap = 292.25
+PHY-3002 : Step(282): len = 601602, overlap = 302
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 7.88578e-05
+PHY-3002 : Step(283): len = 604246, overlap = 292.75
+PHY-3002 : Step(284): len = 607346, overlap = 290.25
+PHY-3002 : Step(285): len = 607400, overlap = 288.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000154089
+PHY-3002 : Step(286): len = 615306, overlap = 279.25
+PHY-3002 : Step(287): len = 623059, overlap = 278.25
+PHY-3002 : Step(288): len = 621824, overlap = 273.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000308179
+PHY-3002 : Step(289): len = 628465, overlap = 268.5
+PHY-3002 : Step(290): len = 639695, overlap = 243.75
+PHY-3002 : Step(291): len = 639318, overlap = 240
+PHY-3002 : Step(292): len = 637862, overlap = 238.5
+PHY-3002 : Step(293): len = 638029, overlap = 232.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.378468s wall, 0.390625s user + 0.640625s system = 1.031250s CPU (272.5%)
+
+PHY-3001 : Trial Legalized: Len = 771625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 767/18323.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879520, over cnt = 2687(7%), over = 4585, worst = 6
+PHY-1002 : len = 895616, over cnt = 1648(4%), over = 2484, worst = 6
+PHY-1002 : len = 915824, over cnt = 645(1%), over = 1036, worst = 6
+PHY-1002 : len = 929624, over cnt = 136(0%), over = 223, worst = 6
+PHY-1002 : len = 933920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.370530s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (143.7%)
+
+PHY-1001 : Congestion index: top1 = 56.42, top5 = 50.80, top10 = 47.99, top15 = 46.10.
+PHY-3001 : End congestion estimation;  2.849809s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (136.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18145 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.873431s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000159913
+PHY-3002 : Step(294): len = 735582, overlap = 63.5
+PHY-3002 : Step(295): len = 717695, overlap = 93.25
+PHY-3002 : Step(296): len = 702061, overlap = 117.25
+PHY-3002 : Step(297): len = 687892, overlap = 154.75
+PHY-3002 : Step(298): len = 677111, overlap = 182.25
+PHY-3002 : Step(299): len = 671133, overlap = 194.75
+PHY-3002 : Step(300): len = 665205, overlap = 204.25
+PHY-3002 : Step(301): len = 661481, overlap = 213.75
+PHY-3002 : Step(302): len = 658836, overlap = 214.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000319827
+PHY-3002 : Step(303): len = 663226, overlap = 208.25
+PHY-3002 : Step(304): len = 666361, overlap = 204.25
+PHY-3002 : Step(305): len = 666510, overlap = 201.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000539792
+PHY-3002 : Step(306): len = 669333, overlap = 195.25
+PHY-3002 : Step(307): len = 673752, overlap = 187
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.080155s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (97.5%)
+
+PHY-3001 : Legalized: Len = 727338, Over = 0
+PHY-3001 : Spreading special nets. 420 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.112186s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (97.5%)
+
+PHY-3001 : 629 instances has been re-located, deltaX = 248, deltaY = 416, maxDist = 5.
+PHY-3001 : Final: Len = 738050, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74917, tnet num: 18145, tinst num: 7041, tnode num: 99331, tedge num: 124678.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.838864s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (100.3%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 651 MB, peak memory is 752 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3758/18323.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853504, over cnt = 2536(7%), over = 4183, worst = 7
+PHY-1002 : len = 867960, over cnt = 1527(4%), over = 2181, worst = 6
+PHY-1002 : len = 888184, over cnt = 416(1%), over = 595, worst = 6
+PHY-1002 : len = 895016, over cnt = 157(0%), over = 198, worst = 6
+PHY-1002 : len = 899088, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.926852s wall, 2.750000s user + 0.062500s system = 2.812500s CPU (146.0%)
+
+PHY-1001 : Congestion index: top1 = 54.29, top5 = 49.56, top10 = 46.69, top15 = 44.82.
+PHY-1001 : End incremental global routing;  2.276403s wall, 3.109375s user + 0.062500s system = 3.171875s CPU (139.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18145 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.913131s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.2%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6948 has valid locations, 22 needs to be replaced
+PHY-3001 : design contains 7058 instances, 6909 slices, 197 macros(960 instances: 626 mslices 334 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_721 with 4114 pins
+PHY-3001 : Found 1597 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 739819
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16778/18335.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900784, over cnt = 55(0%), over = 60, worst = 3
+PHY-1002 : len = 900992, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 901056, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.412894s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (121.1%)
+
+PHY-1001 : Congestion index: top1 = 54.29, top5 = 49.57, top10 = 46.70, top15 = 44.84.
+PHY-3001 : End congestion estimation;  0.714920s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (109.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75006, tnet num: 18157, tinst num: 7058, tnode num: 99452, tedge num: 124788.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.829140s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (99.1%)
+
+RUN-1004 : used memory is 672 MB, reserved memory is 675 MB, peak memory is 752 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18157 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.714581s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(308): len = 739358, overlap = 1
+PHY-3002 : Step(309): len = 739329, overlap = 1.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16768/18335.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900104, over cnt = 59(0%), over = 68, worst = 3
+PHY-1002 : len = 900080, over cnt = 13(0%), over = 14, worst = 2
+PHY-1002 : len = 900256, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 900272, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 900280, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.734449s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (106.4%)
+
+PHY-1001 : Congestion index: top1 = 54.29, top5 = 49.56, top10 = 46.69, top15 = 44.82.
+PHY-3001 : End congestion estimation;  1.035843s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (105.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18157 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.900640s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00010756
+PHY-3002 : Step(310): len = 739199, overlap = 1
+PHY-3002 : Step(311): len = 739180, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005781s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 739292, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059059s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.4%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 739320, Over = 0
+PHY-3001 : End incremental placement;  5.824399s wall, 6.046875s user + 0.078125s system = 6.125000s CPU (105.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.588824s wall, 10.750000s user + 0.140625s system = 10.890625s CPU (113.6%)
+
+OPT-1001 : Current memory(MB): used = 755, reserve = 757, peak = 758.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16768/18335.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900280, over cnt = 45(0%), over = 59, worst = 5
+PHY-1002 : len = 900392, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 900536, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 900592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.567292s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 54.33, top5 = 49.57, top10 = 46.71, top15 = 44.84.
+OPT-1001 : End congestion update;  0.866025s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (102.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18157 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.714018s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.7%)
+
+OPT-0007 : Start: WNS -1086 TNS -2050 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6970 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7058 instances, 6909 slices, 197 macros(960 instances: 626 mslices 334 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_721 with 4114 pins
+PHY-3001 : Found 1597 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 741522, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059742s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.5%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 11, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 741736, Over = 0
+PHY-3001 : End incremental legalization;  0.379196s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (123.6%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1950 NUM_FEPS 3 with 24 cells processed and 6000 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1950 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.104647s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (110.6%)
+
+OPT-1001 : Current memory(MB): used = 755, reserve = 757, peak = 758.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18157 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.716290s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16676/18335.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902520, over cnt = 85(0%), over = 100, worst = 4
+PHY-1002 : len = 902480, over cnt = 43(0%), over = 44, worst = 2
+PHY-1002 : len = 902688, over cnt = 27(0%), over = 27, worst = 1
+PHY-1002 : len = 902848, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 903176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.811355s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (104.0%)
+
+PHY-1001 : Congestion index: top1 = 54.18, top5 = 49.41, top10 = 46.65, top15 = 44.77.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18157 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.716195s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1086 TNS -2100 NUM_FEPS 3
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.758621
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1086ps with logic level 2 
+RUN-1001 :       #2 path slack -1040ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 18335 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 18335 nets
+OPT-1001 : End physical optimization;  16.457900s wall, 17.843750s user + 0.171875s system = 18.015625s CPU (109.5%)
+
+RUN-1003 : finish command "place" in  61.182553s wall, 96.343750s user + 5.765625s system = 102.109375s CPU (166.9%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 656 MB, peak memory is 758 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.724831s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (173.9%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 657 MB, peak memory is 758 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7060 instances
+RUN-1001 : 3457 mslices, 3452 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18335 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 11013 nets have 2 pins
+RUN-1001 : 5494 nets have [3 - 5] pins
+RUN-1001 : 1188 nets have [6 - 10] pins
+RUN-1001 : 273 nets have [11 - 20] pins
+RUN-1001 : 337 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75006, tnet num: 18157, tinst num: 7058, tnode num: 99452, tedge num: 124788.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.602854s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.4%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 640 MB, peak memory is 758 MB
+PHY-1001 : 3457 mslices, 3452 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18157 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[33] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 834512, over cnt = 2753(7%), over = 4629, worst = 6
+PHY-1002 : len = 855072, over cnt = 1515(4%), over = 2177, worst = 6
+PHY-1002 : len = 873960, over cnt = 595(1%), over = 793, worst = 6
+PHY-1002 : len = 885584, over cnt = 69(0%), over = 92, worst = 4
+PHY-1002 : len = 886880, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.001644s wall, 4.046875s user + 0.031250s system = 4.078125s CPU (135.9%)
+
+PHY-1001 : Congestion index: top1 = 54.50, top5 = 49.24, top10 = 46.36, top15 = 44.44.
+PHY-1001 : End global routing;  3.318992s wall, 4.359375s user + 0.031250s system = 4.390625s CPU (132.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 722, reserve = 727, peak = 758.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 997, reserve = 1001, peak = 997.
+PHY-1001 : End build detailed router design. 3.943944s wall, 3.906250s user + 0.046875s system = 3.953125s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 251064, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.839150s wall, 4.812500s user + 0.015625s system = 4.828125s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 251120, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.400627s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.4%)
+
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1038, peak = 1033.
+PHY-1001 : End phase 1; 5.251698s wall, 5.234375s user + 0.015625s system = 5.250000s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.27371e+06, over cnt = 2235(0%), over = 2248, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1054, peak = 1050.
+PHY-1001 : End initial routed; 18.169940s wall, 41.187500s user + 0.218750s system = 41.406250s CPU (227.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17347(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.172   |  -4.431   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.263932s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1065, reserve = 1069, peak = 1065.
+PHY-1001 : End phase 2; 21.433934s wall, 44.453125s user + 0.218750s system = 44.671875s CPU (208.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.034ns STNS -4.290ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.150245s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.0%)
+
+PHY-1022 : len = 2.27373e+06, over cnt = 2239(0%), over = 2252, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.433113s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.23426e+06, over cnt = 787(0%), over = 789, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.799521s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (186.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.23212e+06, over cnt = 186(0%), over = 186, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.011975s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (152.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.23357e+06, over cnt = 30(0%), over = 30, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.460888s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (118.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.23408e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.279857s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (122.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.23432e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.274105s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (102.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.23432e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.420438s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.23432e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.837337s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (84.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.23433e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.169195s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.2343e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.681008s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (22.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.2343e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.178700s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.2343e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.231543s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (94.5%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.2343e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.358139s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.23429e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.168732s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.23429e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.157138s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17347(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.034   |  -4.290   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.286067s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 710 feed throughs used by 507 nets
+PHY-1001 : End commit to database; 2.214999s wall, 2.171875s user + 0.046875s system = 2.218750s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1177, peak = 1169.
+PHY-1001 : End phase 3; 13.385871s wall, 14.937500s user + 0.046875s system = 14.984375s CPU (111.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.034ns STNS -4.290ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.144358s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1022 : len = 2.23429e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.384175s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.034ns, -4.290ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17347(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.034   |  -4.290   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.278748s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 710 feed throughs used by 507 nets
+PHY-1001 : End commit to database; 2.269641s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1179, reserve = 1187, peak = 1179.
+PHY-1001 : End phase 4; 5.957890s wall, 5.953125s user + 0.000000s system = 5.953125s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.23429e+06
+PHY-1001 : Current memory(MB): used = 1180, reserve = 1188, peak = 1180.
+PHY-1001 : End export database. 0.059824s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+
+PHY-1001 : End detail routing;  50.425146s wall, 74.921875s user + 0.328125s system = 75.250000s CPU (149.2%)
+
+RUN-1003 : finish command "route" in  56.430478s wall, 81.937500s user + 0.390625s system = 82.328125s CPU (145.9%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1114 MB, peak memory is 1180 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                     9667   out of  19600   49.32%
+#reg                    10566   out of  19600   53.91%
+#le                     12937
+  #lut only              2371   out of  12937   18.33%
+  #reg only              3270   out of  12937   25.28%
+  #lut&reg               7296   out of  12937   56.40%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1728
+#2        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1669
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1643
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               927
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             BUSY_MIPI_sync_d1_reg_syn_12.q0                    136
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             u_mipi_sot_min/reg1_syn_295.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/u_local_bus_slve_cis/reg47_syn_188.f0    3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P39        LVCMOS25          N/A           N/A        NONE    
+       paper_in            INPUT        P119       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P16        LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P148       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P110       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P173       LVCMOS33           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12937  |8755    |912     |10598   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |520    |412     |23      |443     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |97     |78      |4       |90      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |27     |27      |0       |19      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |6      |6       |0       |5       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |789    |361     |96      |602     |0       |0       |
+|    u_ADconfig                |AD_config            |201    |119     |25      |156     |0       |0       |
+|    u_gen_sp                  |gen_sp               |262    |175     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |734    |360     |96      |541     |0       |0       |
+|    u_ADconfig                |AD_config            |170    |115     |25      |119     |0       |0       |
+|    u_gen_sp                  |gen_sp               |266    |162     |71      |124     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3329   |2366    |270     |2635    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |7       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |190    |118     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|    u_sort                    |sort                 |3104   |2240    |253     |2454    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2590   |1919    |217     |2042    |22      |0       |
+|        channelPart           |channel_part_8478    |105    |102     |3       |100     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |1673   |1332    |197     |1168    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |204    |177     |27      |127     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |17      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|          insert              |insert               |993    |679     |170     |712     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |476    |476     |0       |329     |0       |0       |
+|        read_ram_i            |read_ram             |71     |61      |8       |48      |0       |0       |
+|          read_ram_data       |read_ram_data        |65     |57      |8       |42      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |359    |228     |36      |283     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3388   |2547    |270     |2646    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |190    |141     |17      |153     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |3166   |2383    |253     |2461    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |5       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2695   |2048    |217     |2051    |22      |1       |
+|        channelPart           |channel_part_8478    |172    |166     |3       |121     |0       |0       |
+|        fifo_adc              |fifo_adc             |55     |46      |9       |39      |0       |1       |
+|        ram_switch            |ram_switch           |1721   |1247    |197     |1165    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |207    |178     |27      |117     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |7       |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|          insert              |insert               |992    |547     |170     |704     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |522    |522     |0       |344     |0       |0       |
+|        read_ram_i            |read_ram_rev         |67     |47      |8       |48      |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |67     |47      |8       |48      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10951  
+    #2         2       3884   
+    #3         3       1146   
+    #4         4        461   
+    #5        5-10     1225   
+    #6       11-50      554   
+    #7       51-100     17    
+    #8        >500       1    
+  Average     2.78            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.104153s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (172.3%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1116 MB, peak memory is 1180 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75006, tnet num: 18157, tinst num: 7058, tnode num: 99452, tedge num: 124788.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.603583s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.4%)
+
+RUN-1004 : used memory is 1110 MB, reserved memory is 1122 MB, peak memory is 1180 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18157 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.450223s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.1%)
+
+RUN-1004 : used memory is 1113 MB, reserved memory is 1125 MB, peak memory is 1180 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7058
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18335, pip num: 171259
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 710
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3257 valid insts, and 476519 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.898174s wall, 67.203125s user + 0.218750s system = 67.421875s CPU (681.2%)
+
+RUN-1004 : used memory is 1279 MB, reserved memory is 1282 MB, peak memory is 1394 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_141745.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_142935.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_142935.log
new file mode 100644
index 0000000..6dea83a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_142935.log
@@ -0,0 +1,1995 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:29:36 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.154103s wall, 2.062500s user + 0.093750s system = 2.156250s CPU (100.1%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 315 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2277 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17824 instances
+RUN-0007 : 7432 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20408 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13489 nets have 2 pins
+RUN-1001 : 5483 nets have [3 - 5] pins
+RUN-1001 : 1024 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 180 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3597     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17822 instances, 7432 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85222, tnet num: 20230, tinst num: 17822, tnode num: 115696, tedge num: 136734.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.135778s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.4%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 516 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20230 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.913351s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (100.4%)
+
+PHY-3001 : Found 3483 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.10955e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17822.
+PHY-3001 : Level 1 #clusters 2011.
+PHY-3001 : End clustering;  0.127682s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28043e+06, overlap = 497.344
+PHY-3002 : Step(2): len = 1.18687e+06, overlap = 568
+PHY-3002 : Step(3): len = 826815, overlap = 643
+PHY-3002 : Step(4): len = 767000, overlap = 668
+PHY-3002 : Step(5): len = 586966, overlap = 784.562
+PHY-3002 : Step(6): len = 524618, overlap = 829.25
+PHY-3002 : Step(7): len = 453562, overlap = 910.219
+PHY-3002 : Step(8): len = 429763, overlap = 960.406
+PHY-3002 : Step(9): len = 379935, overlap = 1037.97
+PHY-3002 : Step(10): len = 353453, overlap = 1066.34
+PHY-3002 : Step(11): len = 313352, overlap = 1125.38
+PHY-3002 : Step(12): len = 296648, overlap = 1168.88
+PHY-3002 : Step(13): len = 266937, overlap = 1204.34
+PHY-3002 : Step(14): len = 257080, overlap = 1241.62
+PHY-3002 : Step(15): len = 227482, overlap = 1284.53
+PHY-3002 : Step(16): len = 220098, overlap = 1289.22
+PHY-3002 : Step(17): len = 195069, overlap = 1319.94
+PHY-3002 : Step(18): len = 186731, overlap = 1336.53
+PHY-3002 : Step(19): len = 173055, overlap = 1377.88
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.1199e-06
+PHY-3002 : Step(20): len = 170720, overlap = 1345.97
+PHY-3002 : Step(21): len = 199265, overlap = 1295.19
+PHY-3002 : Step(22): len = 203640, overlap = 1249.53
+PHY-3002 : Step(23): len = 202327, overlap = 1250.12
+PHY-3002 : Step(24): len = 200219, overlap = 1244.78
+PHY-3002 : Step(25): len = 198174, overlap = 1218.25
+PHY-3002 : Step(26): len = 195621, overlap = 1221.62
+PHY-3002 : Step(27): len = 193923, overlap = 1203.28
+PHY-3002 : Step(28): len = 192636, overlap = 1176.62
+PHY-3002 : Step(29): len = 189599, overlap = 1180.38
+PHY-3002 : Step(30): len = 186927, overlap = 1158.84
+PHY-3002 : Step(31): len = 184190, overlap = 1169.38
+PHY-3002 : Step(32): len = 183233, overlap = 1180.94
+PHY-3002 : Step(33): len = 180192, overlap = 1182.16
+PHY-3002 : Step(34): len = 178233, overlap = 1173.81
+PHY-3002 : Step(35): len = 177458, overlap = 1164.25
+PHY-3002 : Step(36): len = 176989, overlap = 1169.31
+PHY-3002 : Step(37): len = 176351, overlap = 1162.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.2398e-06
+PHY-3002 : Step(38): len = 178268, overlap = 1154.38
+PHY-3002 : Step(39): len = 186803, overlap = 1088.56
+PHY-3002 : Step(40): len = 190541, overlap = 1064.59
+PHY-3002 : Step(41): len = 196127, overlap = 1049.84
+PHY-3002 : Step(42): len = 197505, overlap = 1052.28
+PHY-3002 : Step(43): len = 199191, overlap = 1073.38
+PHY-3002 : Step(44): len = 199492, overlap = 1073.72
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.47961e-06
+PHY-3002 : Step(45): len = 208959, overlap = 1052.81
+PHY-3002 : Step(46): len = 230998, overlap = 987.281
+PHY-3002 : Step(47): len = 242978, overlap = 927.906
+PHY-3002 : Step(48): len = 250123, overlap = 892.219
+PHY-3002 : Step(49): len = 253109, overlap = 882
+PHY-3002 : Step(50): len = 255361, overlap = 864.438
+PHY-3002 : Step(51): len = 253969, overlap = 863.812
+PHY-3002 : Step(52): len = 252783, overlap = 857.219
+PHY-3002 : Step(53): len = 250765, overlap = 853.5
+PHY-3002 : Step(54): len = 249815, overlap = 859.219
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.95921e-06
+PHY-3002 : Step(55): len = 265622, overlap = 826.125
+PHY-3002 : Step(56): len = 288397, overlap = 729.625
+PHY-3002 : Step(57): len = 297463, overlap = 640.719
+PHY-3002 : Step(58): len = 302781, overlap = 594.125
+PHY-3002 : Step(59): len = 303121, overlap = 577.781
+PHY-3002 : Step(60): len = 303063, overlap = 567.281
+PHY-3002 : Step(61): len = 300721, overlap = 586.812
+PHY-3002 : Step(62): len = 300120, overlap = 568.844
+PHY-3002 : Step(63): len = 299121, overlap = 577.312
+PHY-3002 : Step(64): len = 296711, overlap = 580.281
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.79184e-05
+PHY-3002 : Step(65): len = 315869, overlap = 522.906
+PHY-3002 : Step(66): len = 331230, overlap = 485.062
+PHY-3002 : Step(67): len = 334923, overlap = 446.156
+PHY-3002 : Step(68): len = 337413, overlap = 420.812
+PHY-3002 : Step(69): len = 337043, overlap = 409.438
+PHY-3002 : Step(70): len = 338845, overlap = 393.219
+PHY-3002 : Step(71): len = 338757, overlap = 386.344
+PHY-3002 : Step(72): len = 339578, overlap = 394.062
+PHY-3002 : Step(73): len = 338373, overlap = 389.469
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.58368e-05
+PHY-3002 : Step(74): len = 356975, overlap = 345.062
+PHY-3002 : Step(75): len = 368546, overlap = 332.688
+PHY-3002 : Step(76): len = 368823, overlap = 316.094
+PHY-3002 : Step(77): len = 370900, overlap = 299.781
+PHY-3002 : Step(78): len = 373856, overlap = 302.469
+PHY-3002 : Step(79): len = 377865, overlap = 285.969
+PHY-3002 : Step(80): len = 375357, overlap = 275.156
+PHY-3002 : Step(81): len = 376893, overlap = 286.156
+PHY-3002 : Step(82): len = 377522, overlap = 285.969
+PHY-3002 : Step(83): len = 378752, overlap = 265.469
+PHY-3002 : Step(84): len = 378218, overlap = 261.688
+PHY-3002 : Step(85): len = 378618, overlap = 270.5
+PHY-3002 : Step(86): len = 379657, overlap = 279.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.16737e-05
+PHY-3002 : Step(87): len = 397797, overlap = 262.656
+PHY-3002 : Step(88): len = 409342, overlap = 260.719
+PHY-3002 : Step(89): len = 408689, overlap = 244.031
+PHY-3002 : Step(90): len = 409994, overlap = 233.125
+PHY-3002 : Step(91): len = 413046, overlap = 225.812
+PHY-3002 : Step(92): len = 416462, overlap = 225.781
+PHY-3002 : Step(93): len = 413259, overlap = 227.531
+PHY-3002 : Step(94): len = 414305, overlap = 226.438
+PHY-3002 : Step(95): len = 417642, overlap = 232.344
+PHY-3002 : Step(96): len = 419736, overlap = 221.281
+PHY-3002 : Step(97): len = 416062, overlap = 223.594
+PHY-3002 : Step(98): len = 415296, overlap = 222.875
+PHY-3002 : Step(99): len = 416697, overlap = 222.531
+PHY-3002 : Step(100): len = 417462, overlap = 221.781
+PHY-3002 : Step(101): len = 415971, overlap = 233.531
+PHY-3002 : Step(102): len = 416781, overlap = 231.312
+PHY-3002 : Step(103): len = 417956, overlap = 230.719
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000143347
+PHY-3002 : Step(104): len = 433281, overlap = 220.344
+PHY-3002 : Step(105): len = 444289, overlap = 216.594
+PHY-3002 : Step(106): len = 443884, overlap = 215.25
+PHY-3002 : Step(107): len = 445234, overlap = 225.438
+PHY-3002 : Step(108): len = 448257, overlap = 224.188
+PHY-3002 : Step(109): len = 451577, overlap = 218.812
+PHY-3002 : Step(110): len = 450917, overlap = 216.75
+PHY-3002 : Step(111): len = 453791, overlap = 202.031
+PHY-3002 : Step(112): len = 454338, overlap = 205.062
+PHY-3002 : Step(113): len = 454065, overlap = 204.125
+PHY-3002 : Step(114): len = 451159, overlap = 215.656
+PHY-3002 : Step(115): len = 450589, overlap = 211.812
+PHY-3002 : Step(116): len = 451980, overlap = 209.219
+PHY-3002 : Step(117): len = 452376, overlap = 200.969
+PHY-3002 : Step(118): len = 450656, overlap = 205.438
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000279542
+PHY-3002 : Step(119): len = 461427, overlap = 202.312
+PHY-3002 : Step(120): len = 469064, overlap = 198.594
+PHY-3002 : Step(121): len = 469135, overlap = 194.375
+PHY-3002 : Step(122): len = 469806, overlap = 204.562
+PHY-3002 : Step(123): len = 472351, overlap = 202.219
+PHY-3002 : Step(124): len = 474667, overlap = 198.188
+PHY-3002 : Step(125): len = 475166, overlap = 207.594
+PHY-3002 : Step(126): len = 477216, overlap = 214.906
+PHY-3002 : Step(127): len = 479912, overlap = 203.781
+PHY-3002 : Step(128): len = 482207, overlap = 201.969
+PHY-3002 : Step(129): len = 481605, overlap = 201.438
+PHY-3002 : Step(130): len = 481827, overlap = 194.344
+PHY-3002 : Step(131): len = 482926, overlap = 190.156
+PHY-3002 : Step(132): len = 482905, overlap = 184.062
+PHY-3002 : Step(133): len = 481336, overlap = 180.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000502189
+PHY-3002 : Step(134): len = 487191, overlap = 184.719
+PHY-3002 : Step(135): len = 491833, overlap = 177.188
+PHY-3002 : Step(136): len = 492435, overlap = 179.062
+PHY-3002 : Step(137): len = 493027, overlap = 179.281
+PHY-3002 : Step(138): len = 494380, overlap = 170.188
+PHY-3002 : Step(139): len = 495688, overlap = 169.875
+PHY-3002 : Step(140): len = 496183, overlap = 163.438
+PHY-3002 : Step(141): len = 499163, overlap = 149.062
+PHY-3002 : Step(142): len = 502377, overlap = 144.969
+PHY-3002 : Step(143): len = 504596, overlap = 144.781
+PHY-3002 : Step(144): len = 504751, overlap = 143.406
+PHY-3002 : Step(145): len = 505539, overlap = 147.938
+PHY-3002 : Step(146): len = 506625, overlap = 139.844
+PHY-3002 : Step(147): len = 507016, overlap = 141.656
+PHY-3002 : Step(148): len = 506147, overlap = 144.938
+PHY-3002 : Step(149): len = 505570, overlap = 145.469
+PHY-3002 : Step(150): len = 506264, overlap = 148.812
+PHY-3002 : Step(151): len = 506554, overlap = 150.375
+PHY-3002 : Step(152): len = 505866, overlap = 150.25
+PHY-3002 : Step(153): len = 505627, overlap = 150.438
+PHY-3002 : Step(154): len = 506179, overlap = 152.75
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000971212
+PHY-3002 : Step(155): len = 510309, overlap = 150.938
+PHY-3002 : Step(156): len = 516500, overlap = 147.031
+PHY-3002 : Step(157): len = 518206, overlap = 149.688
+PHY-3002 : Step(158): len = 519165, overlap = 149.188
+PHY-3002 : Step(159): len = 520495, overlap = 150.469
+PHY-3002 : Step(160): len = 521940, overlap = 155.406
+PHY-3002 : Step(161): len = 522437, overlap = 147
+PHY-3002 : Step(162): len = 523272, overlap = 150.5
+PHY-3002 : Step(163): len = 524483, overlap = 148.094
+PHY-3002 : Step(164): len = 524954, overlap = 148.875
+PHY-3002 : Step(165): len = 524793, overlap = 153.5
+PHY-3002 : Step(166): len = 524872, overlap = 153.375
+PHY-3002 : Step(167): len = 525463, overlap = 153.062
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00171012
+PHY-3002 : Step(168): len = 528184, overlap = 157.906
+PHY-3002 : Step(169): len = 535206, overlap = 154.531
+PHY-3002 : Step(170): len = 536927, overlap = 151.031
+PHY-3002 : Step(171): len = 538363, overlap = 143.562
+PHY-3002 : Step(172): len = 539880, overlap = 143.812
+PHY-3002 : Step(173): len = 540481, overlap = 145.375
+PHY-3002 : Step(174): len = 540258, overlap = 146.531
+PHY-3002 : Step(175): len = 540163, overlap = 146.531
+PHY-3002 : Step(176): len = 540704, overlap = 143.938
+PHY-3002 : Step(177): len = 541066, overlap = 147.344
+PHY-3002 : Step(178): len = 541357, overlap = 147.031
+PHY-3002 : Step(179): len = 541880, overlap = 148.25
+PHY-3002 : Step(180): len = 542626, overlap = 142.5
+PHY-3002 : Step(181): len = 542990, overlap = 137.812
+PHY-3002 : Step(182): len = 543034, overlap = 139.562
+PHY-3002 : Step(183): len = 543055, overlap = 143.75
+PHY-3002 : Step(184): len = 543148, overlap = 145.438
+PHY-3002 : Step(185): len = 543190, overlap = 140.625
+PHY-3002 : Step(186): len = 543048, overlap = 141.312
+PHY-3002 : Step(187): len = 543053, overlap = 140.938
+PHY-3002 : Step(188): len = 543207, overlap = 140.938
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00305211
+PHY-3002 : Step(189): len = 545696, overlap = 139.5
+PHY-3002 : Step(190): len = 551827, overlap = 139.938
+PHY-3002 : Step(191): len = 554288, overlap = 134.812
+PHY-3002 : Step(192): len = 556986, overlap = 127.75
+PHY-3002 : Step(193): len = 559314, overlap = 126.219
+PHY-3002 : Step(194): len = 560739, overlap = 119.062
+PHY-3002 : Step(195): len = 560923, overlap = 113.094
+PHY-3002 : Step(196): len = 561103, overlap = 114.906
+PHY-3002 : Step(197): len = 561493, overlap = 114.656
+PHY-3002 : Step(198): len = 561560, overlap = 114.969
+PHY-3002 : Step(199): len = 560918, overlap = 116.938
+PHY-3002 : Step(200): len = 560456, overlap = 119.281
+PHY-3002 : Step(201): len = 560274, overlap = 118.625
+PHY-3002 : Step(202): len = 560183, overlap = 116.594
+PHY-3002 : Step(203): len = 560223, overlap = 115.125
+PHY-3002 : Step(204): len = 560077, overlap = 115.625
+PHY-3002 : Step(205): len = 559799, overlap = 114.469
+PHY-3002 : Step(206): len = 559776, overlap = 116.406
+PHY-3002 : Step(207): len = 559979, overlap = 115.781
+PHY-3002 : Step(208): len = 559981, overlap = 116.531
+PHY-3002 : Step(209): len = 559697, overlap = 116.031
+PHY-3002 : Step(210): len = 559558, overlap = 115.438
+PHY-3002 : Step(211): len = 559620, overlap = 116.344
+PHY-3002 : Step(212): len = 559620, overlap = 116.344
+PHY-3002 : Step(213): len = 559568, overlap = 116.188
+PHY-3001 : :::14::: Try harder cell spreading with beta_ = 0.00496596
+PHY-3002 : Step(214): len = 560921, overlap = 115.844
+PHY-3002 : Step(215): len = 563998, overlap = 110.875
+PHY-3002 : Step(216): len = 564814, overlap = 111.688
+PHY-3002 : Step(217): len = 565963, overlap = 107.969
+PHY-3002 : Step(218): len = 567518, overlap = 100.344
+PHY-3002 : Step(219): len = 568358, overlap = 98.4688
+PHY-3002 : Step(220): len = 567950, overlap = 98.6562
+PHY-3002 : Step(221): len = 567781, overlap = 97.9062
+PHY-3002 : Step(222): len = 568353, overlap = 99.7188
+PHY-3002 : Step(223): len = 568353, overlap = 99.7188
+PHY-3002 : Step(224): len = 568143, overlap = 98.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016399s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (95.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20408.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 726080, over cnt = 1613(4%), over = 7717, worst = 48
+PHY-1001 : End global iterations;  0.707181s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (143.6%)
+
+PHY-1001 : Congestion index: top1 = 80.71, top5 = 61.13, top10 = 52.62, top15 = 47.11.
+PHY-3001 : End congestion estimation;  0.916748s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (134.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20230 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.850406s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.59276e-05
+PHY-3002 : Step(225): len = 660661, overlap = 72.125
+PHY-3002 : Step(226): len = 669889, overlap = 71.4375
+PHY-3002 : Step(227): len = 663119, overlap = 65.8438
+PHY-3002 : Step(228): len = 660969, overlap = 74.2188
+PHY-3002 : Step(229): len = 662372, overlap = 67.5
+PHY-3002 : Step(230): len = 675241, overlap = 68.4375
+PHY-3002 : Step(231): len = 678133, overlap = 76.5938
+PHY-3002 : Step(232): len = 682547, overlap = 74.8125
+PHY-3002 : Step(233): len = 686637, overlap = 72.1562
+PHY-3002 : Step(234): len = 693395, overlap = 67.3438
+PHY-3002 : Step(235): len = 694607, overlap = 60.3438
+PHY-3002 : Step(236): len = 699382, overlap = 56.2812
+PHY-3002 : Step(237): len = 704151, overlap = 64.6562
+PHY-3002 : Step(238): len = 704614, overlap = 64.4688
+PHY-3002 : Step(239): len = 705219, overlap = 61.5312
+PHY-3002 : Step(240): len = 708118, overlap = 53.125
+PHY-3002 : Step(241): len = 710343, overlap = 45.7188
+PHY-3002 : Step(242): len = 709263, overlap = 43.5938
+PHY-3002 : Step(243): len = 709253, overlap = 40.6875
+PHY-3002 : Step(244): len = 709725, overlap = 34.5
+PHY-3002 : Step(245): len = 708110, overlap = 32.1875
+PHY-3002 : Step(246): len = 707066, overlap = 34.375
+PHY-3002 : Step(247): len = 706119, overlap = 41.25
+PHY-3002 : Step(248): len = 704909, overlap = 41.375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000191855
+PHY-3002 : Step(249): len = 706290, overlap = 40.4062
+PHY-3002 : Step(250): len = 710140, overlap = 36.9062
+PHY-3002 : Step(251): len = 711972, overlap = 33.4688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000347606
+PHY-3002 : Step(252): len = 720457, overlap = 24.875
+PHY-3002 : Step(253): len = 733428, overlap = 24.1875
+PHY-3002 : Step(254): len = 735341, overlap = 25.1562
+PHY-3002 : Step(255): len = 736080, overlap = 28.5312
+PHY-3002 : Step(256): len = 737505, overlap = 30.25
+PHY-3002 : Step(257): len = 736864, overlap = 29.0625
+PHY-3002 : Step(258): len = 737637, overlap = 31.6875
+PHY-3002 : Step(259): len = 740862, overlap = 31.75
+PHY-3002 : Step(260): len = 739645, overlap = 32.5625
+PHY-3002 : Step(261): len = 740118, overlap = 35.2188
+PHY-3002 : Step(262): len = 739784, overlap = 36.1562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00067513
+PHY-3002 : Step(263): len = 743389, overlap = 35.0938
+PHY-3002 : Step(264): len = 750785, overlap = 34.0312
+PHY-3002 : Step(265): len = 754641, overlap = 33.9688
+PHY-3002 : Step(266): len = 759058, overlap = 33.8438
+PHY-3002 : Step(267): len = 770738, overlap = 30.3125
+PHY-3002 : Step(268): len = 777484, overlap = 33.3438
+PHY-3002 : Step(269): len = 775943, overlap = 33.5938
+PHY-3002 : Step(270): len = 774869, overlap = 32.5938
+PHY-3002 : Step(271): len = 773463, overlap = 34.4062
+PHY-3002 : Step(272): len = 770591, overlap = 35.375
+PHY-3002 : Step(273): len = 769674, overlap = 33.625
+PHY-3002 : Step(274): len = 771430, overlap = 32.9375
+PHY-3002 : Step(275): len = 771964, overlap = 33.25
+PHY-3002 : Step(276): len = 772278, overlap = 33
+PHY-3002 : Step(277): len = 773687, overlap = 32.8438
+PHY-3002 : Step(278): len = 772886, overlap = 33.8438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00128551
+PHY-3002 : Step(279): len = 775554, overlap = 32.6875
+PHY-3002 : Step(280): len = 781742, overlap = 32.9688
+PHY-3002 : Step(281): len = 785522, overlap = 34.3438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 37/20408.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860520, over cnt = 2734(7%), over = 14640, worst = 86
+PHY-1001 : End global iterations;  1.361645s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 124.76, top5 = 82.81, top10 = 69.64, top15 = 62.03.
+PHY-3001 : End congestion estimation;  1.655655s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (133.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20230 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868542s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000129647
+PHY-3002 : Step(282): len = 784827, overlap = 263.281
+PHY-3002 : Step(283): len = 787844, overlap = 212.938
+PHY-3002 : Step(284): len = 778827, overlap = 176.594
+PHY-3002 : Step(285): len = 773839, overlap = 162.344
+PHY-3002 : Step(286): len = 766205, overlap = 140.875
+PHY-3002 : Step(287): len = 761086, overlap = 134.312
+PHY-3002 : Step(288): len = 754667, overlap = 130.812
+PHY-3002 : Step(289): len = 751248, overlap = 134.281
+PHY-3002 : Step(290): len = 744820, overlap = 130.312
+PHY-3002 : Step(291): len = 740809, overlap = 129.188
+PHY-3002 : Step(292): len = 734366, overlap = 123.062
+PHY-3002 : Step(293): len = 729558, overlap = 124.5
+PHY-3002 : Step(294): len = 725966, overlap = 121.656
+PHY-3002 : Step(295): len = 722360, overlap = 124
+PHY-3002 : Step(296): len = 719184, overlap = 122.125
+PHY-3002 : Step(297): len = 717362, overlap = 122.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000259295
+PHY-3002 : Step(298): len = 717523, overlap = 116.938
+PHY-3002 : Step(299): len = 720111, overlap = 110.344
+PHY-3002 : Step(300): len = 723348, overlap = 104.906
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000518589
+PHY-3002 : Step(301): len = 729080, overlap = 91.0938
+PHY-3002 : Step(302): len = 737224, overlap = 80.6875
+PHY-3002 : Step(303): len = 741789, overlap = 73.875
+PHY-3002 : Step(304): len = 739148, overlap = 74.7812
+PHY-3002 : Step(305): len = 738195, overlap = 75.3125
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85222, tnet num: 20230, tinst num: 17822, tnode num: 115696, tedge num: 136734.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.447294s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (100.4%)
+
+RUN-1004 : used memory is 578 MB, reserved memory is 568 MB, peak memory is 714 MB
+OPT-1001 : Total overflow 428.62 peak overflow 3.38
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 486/20408.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 832064, over cnt = 3236(9%), over = 12407, worst = 40
+PHY-1001 : End global iterations;  1.327712s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (144.8%)
+
+PHY-1001 : Congestion index: top1 = 85.45, top5 = 65.57, top10 = 57.55, top15 = 52.85.
+PHY-1001 : End incremental global routing;  1.648752s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (136.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20230 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.895422s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.5%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17686 has valid locations, 361 needs to be replaced
+PHY-3001 : design contains 18132 instances, 7543 luts, 9368 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6029 pins
+PHY-3001 : Found 3515 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 761582
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16748/20718.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 850240, over cnt = 3292(9%), over = 12503, worst = 40
+PHY-1001 : End global iterations;  0.248140s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (125.9%)
+
+PHY-1001 : Congestion index: top1 = 85.28, top5 = 65.91, top10 = 57.91, top15 = 53.39.
+PHY-3001 : End congestion estimation;  0.492126s wall, 0.531250s user + 0.031250s system = 0.562500s CPU (114.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86491, tnet num: 20540, tinst num: 18132, tnode num: 117586, tedge num: 138652.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.479890s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (100.3%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 617 MB, peak memory is 718 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.428029s wall, 2.359375s user + 0.062500s system = 2.421875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(306): len = 760673, overlap = 0
+PHY-3002 : Step(307): len = 760217, overlap = 0
+PHY-3002 : Step(308): len = 759992, overlap = 0
+PHY-3002 : Step(309): len = 759760, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16841/20718.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847416, over cnt = 3267(9%), over = 12548, worst = 40
+PHY-1001 : End global iterations;  0.206725s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 86.62, top5 = 66.42, top10 = 58.24, top15 = 53.52.
+PHY-3001 : End congestion estimation;  0.451495s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (103.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.275158s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000357858
+PHY-3002 : Step(310): len = 759741, overlap = 80.0938
+PHY-3002 : Step(311): len = 759796, overlap = 78.9062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000715716
+PHY-3002 : Step(312): len = 759961, overlap = 78.9375
+PHY-3002 : Step(313): len = 760546, overlap = 78.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00139643
+PHY-3002 : Step(314): len = 761434, overlap = 78.2812
+PHY-3002 : Step(315): len = 762581, overlap = 77.875
+PHY-3001 : Final: Len = 762581, Over = 77.875
+PHY-3001 : End incremental placement;  5.360300s wall, 5.453125s user + 0.328125s system = 5.781250s CPU (107.9%)
+
+OPT-1001 : Total overflow 435.66 peak overflow 3.38
+OPT-1001 : End high-fanout net optimization;  8.445986s wall, 9.234375s user + 0.343750s system = 9.578125s CPU (113.4%)
+
+OPT-1001 : Current memory(MB): used = 721, reserve = 715, peak = 737.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16767/20718.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 852576, over cnt = 3254(9%), over = 11473, worst = 40
+PHY-1002 : len = 907280, over cnt = 2448(6%), over = 6261, worst = 31
+PHY-1002 : len = 949152, over cnt = 1184(3%), over = 2833, worst = 20
+PHY-1002 : len = 964608, over cnt = 700(1%), over = 1617, worst = 20
+PHY-1002 : len = 990512, over cnt = 23(0%), over = 43, worst = 11
+PHY-1001 : End global iterations;  1.996725s wall, 2.625000s user + 0.015625s system = 2.640625s CPU (132.2%)
+
+PHY-1001 : Congestion index: top1 = 66.14, top5 = 57.27, top10 = 52.98, top15 = 50.19.
+OPT-1001 : End congestion update;  2.259555s wall, 2.906250s user + 0.015625s system = 2.921875s CPU (129.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.792499s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.6%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 64 cells processed and 8600 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 42 cells processed and 2748 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 21 cells processed and 1168 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 17 cells processed and 500 slack improved
+OPT-1001 : End global optimization;  3.095641s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (121.1%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 697, peak = 737.
+OPT-1001 : End physical optimization;  13.720446s wall, 15.109375s user + 0.390625s system = 15.500000s CPU (113.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7543 LUT to BLE ...
+SYN-4008 : Packed 7543 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6235 remaining SEQ's ...
+SYN-4005 : Packed 3921 SEQ with LUT/SLICE
+SYN-4006 : 783 single LUT's are left
+SYN-4006 : 2314 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9857/13588 primitive instances ...
+PHY-3001 : End packing;  1.552697s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6818 instances
+RUN-1001 : 3335 mslices, 3335 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17715 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10144 nets have 2 pins
+RUN-1001 : 5721 nets have [3 - 5] pins
+RUN-1001 : 1161 nets have [6 - 10] pins
+RUN-1001 : 327 nets have [11 - 20] pins
+RUN-1001 : 330 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6816 instances, 6670 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3528 pins
+PHY-3001 : Found 1578 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 772353, Over = 256.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7474/17715.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934472, over cnt = 2119(6%), over = 3519, worst = 9
+PHY-1002 : len = 941752, over cnt = 1509(4%), over = 2297, worst = 8
+PHY-1002 : len = 957576, over cnt = 610(1%), over = 915, worst = 8
+PHY-1002 : len = 970192, over cnt = 141(0%), over = 186, worst = 5
+PHY-1002 : len = 974176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.670681s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (130.0%)
+
+PHY-1001 : Congestion index: top1 = 64.66, top5 = 55.97, top10 = 51.28, top15 = 48.43.
+PHY-3001 : End congestion estimation;  2.051112s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (124.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74081, tnet num: 17537, tinst num: 6816, tnode num: 96706, tedge num: 124287.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.590905s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.2%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 620 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17537 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.461971s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.98188e-05
+PHY-3002 : Step(316): len = 761053, overlap = 257.25
+PHY-3002 : Step(317): len = 754301, overlap = 256.5
+PHY-3002 : Step(318): len = 749430, overlap = 262.25
+PHY-3002 : Step(319): len = 745683, overlap = 259
+PHY-3002 : Step(320): len = 742048, overlap = 257.25
+PHY-3002 : Step(321): len = 738462, overlap = 265
+PHY-3002 : Step(322): len = 735667, overlap = 269.75
+PHY-3002 : Step(323): len = 732782, overlap = 272.75
+PHY-3002 : Step(324): len = 731118, overlap = 273.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.96377e-05
+PHY-3002 : Step(325): len = 732910, overlap = 269.75
+PHY-3002 : Step(326): len = 735903, overlap = 259.75
+PHY-3002 : Step(327): len = 737319, overlap = 255.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000199275
+PHY-3002 : Step(328): len = 744873, overlap = 245.25
+PHY-3002 : Step(329): len = 753520, overlap = 234.25
+PHY-3002 : Step(330): len = 752549, overlap = 235.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000398551
+PHY-3002 : Step(331): len = 760656, overlap = 220
+PHY-3002 : Step(332): len = 772259, overlap = 199.25
+PHY-3002 : Step(333): len = 770284, overlap = 203
+PHY-3002 : Step(334): len = 768242, overlap = 202.25
+PHY-3002 : Step(335): len = 768891, overlap = 198.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.375049s wall, 0.390625s user + 0.656250s system = 1.046875s CPU (279.1%)
+
+PHY-3001 : Trial Legalized: Len = 928819
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 689/17715.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04964e+06, over cnt = 2829(8%), over = 4832, worst = 8
+PHY-1002 : len = 1.06613e+06, over cnt = 1777(5%), over = 2704, worst = 8
+PHY-1002 : len = 1.08941e+06, over cnt = 614(1%), over = 882, worst = 8
+PHY-1002 : len = 1.09366e+06, over cnt = 419(1%), over = 606, worst = 7
+PHY-1002 : len = 1.10185e+06, over cnt = 166(0%), over = 247, worst = 4
+PHY-1001 : End global iterations;  2.456575s wall, 3.421875s user + 0.031250s system = 3.453125s CPU (140.6%)
+
+PHY-1001 : Congestion index: top1 = 67.65, top5 = 59.56, top10 = 54.82, top15 = 51.88.
+PHY-3001 : End congestion estimation;  2.900459s wall, 3.875000s user + 0.031250s system = 3.906250s CPU (134.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17537 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.835402s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001542
+PHY-3002 : Step(336): len = 889695, overlap = 64.5
+PHY-3002 : Step(337): len = 871666, overlap = 82.75
+PHY-3002 : Step(338): len = 857733, overlap = 100
+PHY-3002 : Step(339): len = 843285, overlap = 122.25
+PHY-3002 : Step(340): len = 832022, overlap = 143.5
+PHY-3002 : Step(341): len = 824068, overlap = 155.5
+PHY-3002 : Step(342): len = 817122, overlap = 166.75
+PHY-3002 : Step(343): len = 812516, overlap = 176.75
+PHY-3002 : Step(344): len = 808290, overlap = 181.5
+PHY-3002 : Step(345): len = 805336, overlap = 185.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000308399
+PHY-3002 : Step(346): len = 810260, overlap = 178.5
+PHY-3002 : Step(347): len = 812834, overlap = 182
+PHY-3002 : Step(348): len = 813780, overlap = 179.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000554358
+PHY-3002 : Step(349): len = 819982, overlap = 172.5
+PHY-3002 : Step(350): len = 821695, overlap = 169.5
+PHY-3002 : Step(351): len = 823693, overlap = 168.25
+PHY-3002 : Step(352): len = 824954, overlap = 169.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.079970s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (97.7%)
+
+PHY-3001 : Legalized: Len = 880948, Over = 0
+PHY-3001 : Spreading special nets. 477 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.120071s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (91.1%)
+
+PHY-3001 : 696 instances has been re-located, deltaX = 334, deltaY = 396, maxDist = 15.
+PHY-3001 : Final: Len = 891984, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74081, tnet num: 17537, tinst num: 6819, tnode num: 96706, tedge num: 124287.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.814094s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (99.9%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 636 MB, peak memory is 737 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3593/17715.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.02354e+06, over cnt = 2639(7%), over = 4456, worst = 8
+PHY-1002 : len = 1.04099e+06, over cnt = 1540(4%), over = 2217, worst = 6
+PHY-1002 : len = 1.06153e+06, over cnt = 428(1%), over = 566, worst = 5
+PHY-1002 : len = 1.0677e+06, over cnt = 176(0%), over = 233, worst = 5
+PHY-1002 : len = 1.07161e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.069039s wall, 3.078125s user + 0.031250s system = 3.109375s CPU (150.3%)
+
+PHY-1001 : Congestion index: top1 = 66.62, top5 = 57.97, top10 = 53.62, top15 = 50.87.
+PHY-1001 : End incremental global routing;  2.434549s wall, 3.437500s user + 0.031250s system = 3.468750s CPU (142.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17537 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.866469s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.0%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6726 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6837 instances, 6688 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3598 pins
+PHY-3001 : Found 1584 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 894336
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16184/17729.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0738e+06, over cnt = 70(0%), over = 81, worst = 3
+PHY-1002 : len = 1.07388e+06, over cnt = 22(0%), over = 25, worst = 2
+PHY-1002 : len = 1.07405e+06, over cnt = 7(0%), over = 9, worst = 2
+PHY-1002 : len = 1.07415e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.07417e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.752188s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (103.9%)
+
+PHY-1001 : Congestion index: top1 = 66.62, top5 = 57.98, top10 = 53.63, top15 = 50.88.
+PHY-3001 : End congestion estimation;  1.056693s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (102.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74233, tnet num: 17551, tinst num: 6837, tnode num: 96894, tedge num: 124468.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.823149s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.3%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 660 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17551 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.696452s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(353): len = 893742, overlap = 0
+PHY-3002 : Step(354): len = 893319, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16167/17729.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07255e+06, over cnt = 44(0%), over = 57, worst = 3
+PHY-1002 : len = 1.07272e+06, over cnt = 17(0%), over = 19, worst = 3
+PHY-1002 : len = 1.07289e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.07294e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.565273s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 66.62, top5 = 57.98, top10 = 53.65, top15 = 50.89.
+PHY-3001 : End congestion estimation;  0.868357s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (104.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17551 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.845713s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000288523
+PHY-3002 : Step(355): len = 893326, overlap = 2.75
+PHY-3002 : Step(356): len = 893328, overlap = 3
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.006164s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 893452, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058954s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.5%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 893670, Over = 0
+PHY-3001 : End incremental placement;  5.964698s wall, 6.062500s user + 0.125000s system = 6.187500s CPU (103.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.749039s wall, 10.968750s user + 0.156250s system = 11.125000s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 741, peak = 744.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16150/17729.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07351e+06, over cnt = 69(0%), over = 80, worst = 4
+PHY-1002 : len = 1.07354e+06, over cnt = 25(0%), over = 25, worst = 1
+PHY-1002 : len = 1.07362e+06, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 1.07385e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.565147s wall, 0.609375s user + 0.031250s system = 0.640625s CPU (113.4%)
+
+PHY-1001 : Congestion index: top1 = 66.62, top5 = 57.98, top10 = 53.65, top15 = 50.89.
+OPT-1001 : End congestion update;  0.868856s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (107.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17551 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.709505s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.3%)
+
+OPT-0007 : Start: WNS -1233 TNS -1947 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6749 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6837 instances, 6688 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3598 pins
+PHY-3001 : Found 1584 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 896576, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.068423s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (114.2%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 13, deltaY = 57, maxDist = 19.
+PHY-3001 : Final: Len = 898642, Over = 0
+PHY-3001 : End incremental legalization;  0.380736s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.5%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 38 cells processed and 8643 slack improved
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.108587s wall, 2.218750s user + 0.031250s system = 2.250000s CPU (106.7%)
+
+OPT-1001 : Current memory(MB): used = 742, reserve = 742, peak = 745.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17551 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.744220s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16033/17729.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07873e+06, over cnt = 106(0%), over = 135, worst = 5
+PHY-1002 : len = 1.07896e+06, over cnt = 52(0%), over = 60, worst = 3
+PHY-1002 : len = 1.07944e+06, over cnt = 13(0%), over = 16, worst = 2
+PHY-1002 : len = 1.07968e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.07978e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.800524s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (111.3%)
+
+PHY-1001 : Congestion index: top1 = 66.42, top5 = 57.95, top10 = 53.64, top15 = 50.89.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17551 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.707656s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1033 TNS -1618 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 65.965517
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1033ps with logic level 2 
+RUN-1001 :       #2 path slack -947ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17729 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17729 nets
+OPT-1001 : End physical optimization;  16.587972s wall, 18.093750s user + 0.203125s system = 18.296875s CPU (110.3%)
+
+RUN-1003 : finish command "place" in  61.878233s wall, 97.468750s user + 7.156250s system = 104.625000s CPU (169.1%)
+
+RUN-1004 : used memory is 685 MB, reserved memory is 697 MB, peak memory is 745 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.678410s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (175.0%)
+
+RUN-1004 : used memory is 686 MB, reserved memory is 698 MB, peak memory is 745 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6839 instances
+RUN-1001 : 3347 mslices, 3341 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17729 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10134 nets have 2 pins
+RUN-1001 : 5724 nets have [3 - 5] pins
+RUN-1001 : 1168 nets have [6 - 10] pins
+RUN-1001 : 332 nets have [11 - 20] pins
+RUN-1001 : 342 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74233, tnet num: 17551, tinst num: 6837, tnode num: 96894, tedge num: 124468.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.569021s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.6%)
+
+RUN-1004 : used memory is 668 MB, reserved memory is 675 MB, peak memory is 745 MB
+PHY-1001 : 3347 mslices, 3341 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17551 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00782e+06, over cnt = 2864(8%), over = 4843, worst = 8
+PHY-1002 : len = 1.02536e+06, over cnt = 1881(5%), over = 2861, worst = 8
+PHY-1002 : len = 1.0517e+06, over cnt = 608(1%), over = 859, worst = 6
+PHY-1002 : len = 1.06546e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.06564e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.798562s wall, 3.625000s user + 0.046875s system = 3.671875s CPU (131.2%)
+
+PHY-1001 : Congestion index: top1 = 67.13, top5 = 57.53, top10 = 53.17, top15 = 50.47.
+PHY-1001 : End global routing;  3.125796s wall, 3.953125s user + 0.046875s system = 4.000000s CPU (128.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 719, reserve = 722, peak = 745.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 991, reserve = 992, peak = 991.
+PHY-1001 : End build detailed router design. 3.923832s wall, 3.890625s user + 0.046875s system = 3.937500s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 264544, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.708499s wall, 4.703125s user + 0.000000s system = 4.703125s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 264600, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.409867s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.1%)
+
+PHY-1001 : Current memory(MB): used = 1027, reserve = 1027, peak = 1027.
+PHY-1001 : End phase 1; 5.130967s wall, 5.125000s user + 0.000000s system = 5.125000s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.54191e+06, over cnt = 2030(0%), over = 2045, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1041, reserve = 1042, peak = 1041.
+PHY-1001 : End initial routed; 54.097321s wall, 80.140625s user + 0.328125s system = 80.468750s CPU (148.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16652(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.923   |  -4.428   |   7   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.326206s wall, 3.296875s user + 0.015625s system = 3.312500s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1051, peak = 1050.
+PHY-1001 : End phase 2; 57.423594s wall, 83.437500s user + 0.343750s system = 83.781250s CPU (145.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -1.800ns STNS -4.170ns FEP 7.
+PHY-1001 : End OPT Iter 1; 0.183394s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.7%)
+
+PHY-1022 : len = 2.54193e+06, over cnt = 2032(0%), over = 2047, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.491785s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50216e+06, over cnt = 860(0%), over = 861, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.013005s wall, 3.453125s user + 0.015625s system = 3.468750s CPU (172.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.4994e+06, over cnt = 316(0%), over = 316, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.798732s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (135.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.49855e+06, over cnt = 53(0%), over = 53, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.823312s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (123.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.4991e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.377317s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (103.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.49912e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.253620s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.49912e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.357605s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.49912e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.644780s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.49912e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.170142s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.49917e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.189911s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.49917e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.216859s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.49917e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.226502s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.49917e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.292931s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (96.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.49915e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.165404s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.49915e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.162342s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (105.9%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.49917e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 15; 0.173714s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16652(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.800   |  -4.170   |   7   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.307443s wall, 3.265625s user + 0.015625s system = 3.281250s CPU (99.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 629 feed throughs used by 442 nets
+PHY-1001 : End commit to database; 2.254586s wall, 2.218750s user + 0.031250s system = 2.250000s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1154, reserve = 1158, peak = 1154.
+PHY-1001 : End phase 3; 13.345396s wall, 15.140625s user + 0.078125s system = 15.218750s CPU (114.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -1.800ns STNS -4.170ns FEP 7.
+PHY-1001 : End OPT Iter 1; 0.156486s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.8%)
+
+PHY-1022 : len = 2.49917e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.410443s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.800ns, -4.170ns, 7}
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16652(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.800   |  -4.170   |   7   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.215947s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 629 feed throughs used by 442 nets
+PHY-1001 : End commit to database; 2.362810s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1167, peak = 1162.
+PHY-1001 : End phase 4; 6.016741s wall, 6.015625s user + 0.000000s system = 6.015625s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.49917e+06
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1170, peak = 1164.
+PHY-1001 : End export database. 0.142251s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.9%)
+
+PHY-1001 : End detail routing;  86.382776s wall, 114.140625s user + 0.468750s system = 114.609375s CPU (132.7%)
+
+RUN-1003 : finish command "route" in  92.125009s wall, 120.718750s user + 0.515625s system = 121.234375s CPU (131.6%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1098 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10267   out of  19600   52.38%
+#reg                     9509   out of  19600   48.52%
+#le                     12493
+  #lut only              2984   out of  12493   23.89%
+  #reg only              2226   out of  12493   17.82%
+  #lut&reg               7283   out of  12493   58.30%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                                   Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                                     1830
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                                1414
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                               1315
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                                     979
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             u_bus_top/u_local_bus_slve_cis/sel23_syn_6823.q0         132
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                                69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                               69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                                     24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                                     4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg4_syn_192.f1                                3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             exdev_ctl_b/u_ADconfig/en_adc_cfg_all_d1_reg_syn_5.f1    3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                                    1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                                    1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                                    1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                                     1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P88        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12493  |9240    |1027    |9541    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |564    |464     |23      |446     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |107    |90      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |31     |31      |0       |19      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |778    |363     |96      |576     |0       |0       |
+|    u_ADconfig                |AD_config            |182    |126     |25      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |283    |184     |71      |125     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |732    |423     |96      |544     |0       |0       |
+|    u_ADconfig                |AD_config            |171    |132     |25      |127     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |171     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3102   |2398    |306     |2150    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |1       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |181    |114     |17      |145     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2889   |2277    |289     |1973    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2405   |1938    |253     |1560    |22      |0       |
+|        channelPart           |channel_part_8478    |108    |104     |3       |98      |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |1930   |1535    |197     |1195    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |227    |199     |27      |117     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |7      |3       |3       |3       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|          insert              |insert               |1014   |648     |170     |728     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |689    |688     |0       |350     |0       |0       |
+|        read_ram_i            |read_ram             |277    |229     |44      |195     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |214    |174     |40      |148     |0       |0       |
+|          read_ram_data       |read_ram_data        |59     |53      |4       |43      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |329    |219     |36      |282     |3       |0       |
+|        u0_soft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3167   |2415    |349     |2162    |25      |1       |
+|    u_ad_sampling             |ad_sampling          |181    |119     |17      |143     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2965   |2285    |332     |1998    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |4       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2455   |1871    |290     |1583    |22      |1       |
+|        channelPart           |channel_part_8478    |235    |228     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |40      |0       |1       |
+|        ram_switch            |ram_switch           |1782   |1330    |197     |1168    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |206    |177     |27      |114     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |9       |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |13      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |6       |0       |0       |
+|          insert              |insert               |1003   |590     |170     |712     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |573    |563     |0       |342     |0       |0       |
+|        read_ram_i            |read_ram_rev         |356    |244     |81      |207     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |292    |209     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |64     |35      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10072  
+    #2         2       3783   
+    #3         3       1382   
+    #4         4        556   
+    #5        5-10     1221   
+    #6       11-50      591   
+    #7       51-100     28    
+    #8        >500       1    
+  Average     2.89            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.074556s wall, 3.546875s user + 0.031250s system = 3.578125s CPU (172.5%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1098 MB, peak memory is 1164 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74233, tnet num: 17551, tinst num: 6837, tnode num: 96894, tedge num: 124468.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.602285s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.5%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1103 MB, peak memory is 1164 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17551 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.446631s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.4%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1106 MB, peak memory is 1164 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6837
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17729, pip num: 177637
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 629
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3217 valid insts, and 490001 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.786858s wall, 67.953125s user + 0.109375s system = 68.062500s CPU (695.4%)
+
+RUN-1004 : used memory is 1264 MB, reserved memory is 1266 MB, peak memory is 1379 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_142935.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_143701.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_143701.log
new file mode 100644
index 0000000..abc051c
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_143701.log
@@ -0,0 +1,2091 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:37:01 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.103446s wall, 2.000000s user + 0.078125s system = 2.078125s CPU (98.8%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 315 MB, peak memory is 342 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2277 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17809 instances
+RUN-0007 : 7417 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20393 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13487 nets have 2 pins
+RUN-1001 : 5461 nets have [3 - 5] pins
+RUN-1001 : 1034 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 179 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3597     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17807 instances, 7417 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85154, tnet num: 20215, tinst num: 17807, tnode num: 115622, tedge num: 136628.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.116166s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (99.4%)
+
+RUN-1004 : used memory is 532 MB, reserved memory is 515 MB, peak memory is 532 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20215 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.903353s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (99.3%)
+
+PHY-3001 : Found 3477 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.08801e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17807.
+PHY-3001 : Level 1 #clusters 2022.
+PHY-3001 : End clustering;  0.125242s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.25798e+06, overlap = 510.312
+PHY-3002 : Step(2): len = 1.16999e+06, overlap = 561.469
+PHY-3002 : Step(3): len = 822578, overlap = 624.781
+PHY-3002 : Step(4): len = 769488, overlap = 671.125
+PHY-3002 : Step(5): len = 591995, overlap = 805.125
+PHY-3002 : Step(6): len = 522816, overlap = 864.938
+PHY-3002 : Step(7): len = 437838, overlap = 933.719
+PHY-3002 : Step(8): len = 409795, overlap = 978.469
+PHY-3002 : Step(9): len = 361421, overlap = 1057.81
+PHY-3002 : Step(10): len = 335339, overlap = 1086.5
+PHY-3002 : Step(11): len = 296521, overlap = 1155.69
+PHY-3002 : Step(12): len = 282105, overlap = 1226
+PHY-3002 : Step(13): len = 243267, overlap = 1278.19
+PHY-3002 : Step(14): len = 232157, overlap = 1307.28
+PHY-3002 : Step(15): len = 200863, overlap = 1367.16
+PHY-3002 : Step(16): len = 192257, overlap = 1379
+PHY-3002 : Step(17): len = 171106, overlap = 1406.84
+PHY-3002 : Step(18): len = 169407, overlap = 1431.06
+PHY-3002 : Step(19): len = 154160, overlap = 1459.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.07849e-06
+PHY-3002 : Step(20): len = 156746, overlap = 1414.47
+PHY-3002 : Step(21): len = 188731, overlap = 1359.47
+PHY-3002 : Step(22): len = 191343, overlap = 1346.59
+PHY-3002 : Step(23): len = 195700, overlap = 1302.91
+PHY-3002 : Step(24): len = 192920, overlap = 1279.78
+PHY-3002 : Step(25): len = 192427, overlap = 1261.94
+PHY-3002 : Step(26): len = 189815, overlap = 1265.94
+PHY-3002 : Step(27): len = 188748, overlap = 1224.62
+PHY-3002 : Step(28): len = 187199, overlap = 1214.59
+PHY-3002 : Step(29): len = 185579, overlap = 1186.31
+PHY-3002 : Step(30): len = 183545, overlap = 1171.75
+PHY-3002 : Step(31): len = 181126, overlap = 1168.94
+PHY-3002 : Step(32): len = 179681, overlap = 1185.06
+PHY-3002 : Step(33): len = 179047, overlap = 1190.59
+PHY-3002 : Step(34): len = 179468, overlap = 1174
+PHY-3002 : Step(35): len = 178831, overlap = 1169.66
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.15698e-06
+PHY-3002 : Step(36): len = 181933, overlap = 1132
+PHY-3002 : Step(37): len = 195646, overlap = 1115.84
+PHY-3002 : Step(38): len = 203613, overlap = 1111.53
+PHY-3002 : Step(39): len = 207530, overlap = 1087.69
+PHY-3002 : Step(40): len = 207800, overlap = 1064.09
+PHY-3002 : Step(41): len = 208254, overlap = 1052.66
+PHY-3002 : Step(42): len = 208404, overlap = 1032.59
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.31395e-06
+PHY-3002 : Step(43): len = 218492, overlap = 966.531
+PHY-3002 : Step(44): len = 240650, overlap = 831.094
+PHY-3002 : Step(45): len = 252804, overlap = 791.156
+PHY-3002 : Step(46): len = 258423, overlap = 778.594
+PHY-3002 : Step(47): len = 257968, overlap = 773.469
+PHY-3002 : Step(48): len = 259538, overlap = 786
+PHY-3002 : Step(49): len = 258330, overlap = 792.25
+PHY-3002 : Step(50): len = 257210, overlap = 789.938
+PHY-3002 : Step(51): len = 255918, overlap = 786.062
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.6279e-06
+PHY-3002 : Step(52): len = 271482, overlap = 746.312
+PHY-3002 : Step(53): len = 296154, overlap = 702.719
+PHY-3002 : Step(54): len = 310293, overlap = 590.375
+PHY-3002 : Step(55): len = 316221, overlap = 527.594
+PHY-3002 : Step(56): len = 314847, overlap = 499.281
+PHY-3002 : Step(57): len = 314556, overlap = 506.844
+PHY-3002 : Step(58): len = 311238, overlap = 524.562
+PHY-3002 : Step(59): len = 310339, overlap = 528.281
+PHY-3002 : Step(60): len = 308298, overlap = 541.812
+PHY-3002 : Step(61): len = 306311, overlap = 544.812
+PHY-3002 : Step(62): len = 303826, overlap = 547.156
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.72558e-05
+PHY-3002 : Step(63): len = 324898, overlap = 539.031
+PHY-3002 : Step(64): len = 342057, overlap = 496.031
+PHY-3002 : Step(65): len = 346464, overlap = 491
+PHY-3002 : Step(66): len = 348432, overlap = 488.062
+PHY-3002 : Step(67): len = 347922, overlap = 483.531
+PHY-3002 : Step(68): len = 347912, overlap = 474.5
+PHY-3002 : Step(69): len = 346254, overlap = 457.75
+PHY-3002 : Step(70): len = 344972, overlap = 447.406
+PHY-3002 : Step(71): len = 344354, overlap = 435.844
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.45116e-05
+PHY-3002 : Step(72): len = 364226, overlap = 399.844
+PHY-3002 : Step(73): len = 378080, overlap = 384.344
+PHY-3002 : Step(74): len = 378933, overlap = 370.719
+PHY-3002 : Step(75): len = 380867, overlap = 345.594
+PHY-3002 : Step(76): len = 384669, overlap = 330.938
+PHY-3002 : Step(77): len = 389166, overlap = 319.312
+PHY-3002 : Step(78): len = 385948, overlap = 310.344
+PHY-3002 : Step(79): len = 387145, overlap = 310.219
+PHY-3002 : Step(80): len = 388115, overlap = 311.594
+PHY-3002 : Step(81): len = 388038, overlap = 312.781
+PHY-3002 : Step(82): len = 385738, overlap = 296.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.89609e-05
+PHY-3002 : Step(83): len = 405204, overlap = 282.844
+PHY-3002 : Step(84): len = 418308, overlap = 285.219
+PHY-3002 : Step(85): len = 416569, overlap = 272.844
+PHY-3002 : Step(86): len = 417875, overlap = 256.281
+PHY-3002 : Step(87): len = 422660, overlap = 260.656
+PHY-3002 : Step(88): len = 426688, overlap = 261.625
+PHY-3002 : Step(89): len = 424503, overlap = 267.938
+PHY-3002 : Step(90): len = 425789, overlap = 267.844
+PHY-3002 : Step(91): len = 429108, overlap = 275.75
+PHY-3002 : Step(92): len = 429192, overlap = 269.656
+PHY-3002 : Step(93): len = 424899, overlap = 266.281
+PHY-3002 : Step(94): len = 424110, overlap = 264.031
+PHY-3002 : Step(95): len = 425678, overlap = 246.406
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000137922
+PHY-3002 : Step(96): len = 442538, overlap = 244.688
+PHY-3002 : Step(97): len = 455414, overlap = 208.062
+PHY-3002 : Step(98): len = 457367, overlap = 211.906
+PHY-3002 : Step(99): len = 459531, overlap = 206.5
+PHY-3002 : Step(100): len = 461772, overlap = 207.719
+PHY-3002 : Step(101): len = 463045, overlap = 207.656
+PHY-3002 : Step(102): len = 460447, overlap = 207.25
+PHY-3002 : Step(103): len = 459873, overlap = 194.375
+PHY-3002 : Step(104): len = 461047, overlap = 198.344
+PHY-3002 : Step(105): len = 462656, overlap = 197.5
+PHY-3002 : Step(106): len = 461198, overlap = 191.094
+PHY-3002 : Step(107): len = 461429, overlap = 182.188
+PHY-3002 : Step(108): len = 461584, overlap = 180.344
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000275843
+PHY-3002 : Step(109): len = 473296, overlap = 170.281
+PHY-3002 : Step(110): len = 483503, overlap = 168.625
+PHY-3002 : Step(111): len = 483751, overlap = 176.719
+PHY-3002 : Step(112): len = 484394, overlap = 176.812
+PHY-3002 : Step(113): len = 486350, overlap = 178.875
+PHY-3002 : Step(114): len = 487829, overlap = 175.375
+PHY-3002 : Step(115): len = 486723, overlap = 182.906
+PHY-3002 : Step(116): len = 487145, overlap = 182.875
+PHY-3002 : Step(117): len = 489650, overlap = 196.031
+PHY-3002 : Step(118): len = 491539, overlap = 181.531
+PHY-3002 : Step(119): len = 490069, overlap = 182.188
+PHY-3002 : Step(120): len = 490018, overlap = 183.188
+PHY-3002 : Step(121): len = 491436, overlap = 189.844
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000551687
+PHY-3002 : Step(122): len = 499827, overlap = 187.781
+PHY-3002 : Step(123): len = 510284, overlap = 168.75
+PHY-3002 : Step(124): len = 510937, overlap = 165.031
+PHY-3002 : Step(125): len = 511989, overlap = 156.906
+PHY-3002 : Step(126): len = 514986, overlap = 160.844
+PHY-3002 : Step(127): len = 517407, overlap = 162.906
+PHY-3002 : Step(128): len = 517114, overlap = 154.375
+PHY-3002 : Step(129): len = 517483, overlap = 153.531
+PHY-3002 : Step(130): len = 519435, overlap = 142.344
+PHY-3002 : Step(131): len = 521110, overlap = 137.031
+PHY-3002 : Step(132): len = 520591, overlap = 132.125
+PHY-3002 : Step(133): len = 520771, overlap = 123.5
+PHY-3002 : Step(134): len = 522110, overlap = 123.688
+PHY-3002 : Step(135): len = 522740, overlap = 121.438
+PHY-3002 : Step(136): len = 521416, overlap = 115.281
+PHY-3002 : Step(137): len = 520948, overlap = 116.281
+PHY-3002 : Step(138): len = 522067, overlap = 121.812
+PHY-3002 : Step(139): len = 524298, overlap = 131.281
+PHY-3002 : Step(140): len = 522929, overlap = 125.188
+PHY-3002 : Step(141): len = 522366, overlap = 121.875
+PHY-3002 : Step(142): len = 522569, overlap = 127.094
+PHY-3002 : Step(143): len = 522655, overlap = 129.406
+PHY-3002 : Step(144): len = 521589, overlap = 134.969
+PHY-3002 : Step(145): len = 521428, overlap = 131.844
+PHY-3002 : Step(146): len = 522279, overlap = 133.531
+PHY-3002 : Step(147): len = 522902, overlap = 127.938
+PHY-3002 : Step(148): len = 522191, overlap = 129.25
+PHY-3002 : Step(149): len = 521847, overlap = 126.5
+PHY-3002 : Step(150): len = 522522, overlap = 126.875
+PHY-3002 : Step(151): len = 523211, overlap = 124.812
+PHY-3002 : Step(152): len = 522636, overlap = 121.531
+PHY-3002 : Step(153): len = 522425, overlap = 122.875
+PHY-3002 : Step(154): len = 522688, overlap = 124.531
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00107473
+PHY-3002 : Step(155): len = 527709, overlap = 122.25
+PHY-3002 : Step(156): len = 534764, overlap = 129.531
+PHY-3002 : Step(157): len = 536703, overlap = 126.844
+PHY-3002 : Step(158): len = 537610, overlap = 126.281
+PHY-3002 : Step(159): len = 538748, overlap = 120.781
+PHY-3002 : Step(160): len = 539275, overlap = 119.969
+PHY-3002 : Step(161): len = 538699, overlap = 120.281
+PHY-3002 : Step(162): len = 538477, overlap = 122.531
+PHY-3002 : Step(163): len = 539349, overlap = 115.375
+PHY-3002 : Step(164): len = 539953, overlap = 114.625
+PHY-3002 : Step(165): len = 539733, overlap = 113.625
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00174579
+PHY-3002 : Step(166): len = 541332, overlap = 115.625
+PHY-3002 : Step(167): len = 543180, overlap = 114.125
+PHY-3002 : Step(168): len = 544676, overlap = 117.438
+PHY-3002 : Step(169): len = 546417, overlap = 124.844
+PHY-3002 : Step(170): len = 547322, overlap = 121.25
+PHY-3002 : Step(171): len = 547561, overlap = 121.562
+PHY-3002 : Step(172): len = 547328, overlap = 116
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.011478s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (136.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20393.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 692072, over cnt = 1547(4%), over = 7154, worst = 34
+PHY-1001 : End global iterations;  0.728126s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (135.2%)
+
+PHY-1001 : Congestion index: top1 = 85.60, top5 = 61.31, top10 = 51.74, top15 = 46.03.
+PHY-3001 : End congestion estimation;  0.945712s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (127.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20215 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.834346s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.62054e-05
+PHY-3002 : Step(173): len = 627840, overlap = 75.75
+PHY-3002 : Step(174): len = 633959, overlap = 75
+PHY-3002 : Step(175): len = 627450, overlap = 76.2188
+PHY-3002 : Step(176): len = 623797, overlap = 62.125
+PHY-3002 : Step(177): len = 632218, overlap = 54.2812
+PHY-3002 : Step(178): len = 646258, overlap = 50.9688
+PHY-3002 : Step(179): len = 650146, overlap = 57.4688
+PHY-3002 : Step(180): len = 650758, overlap = 66.5
+PHY-3002 : Step(181): len = 653412, overlap = 57.6875
+PHY-3002 : Step(182): len = 660475, overlap = 56.1875
+PHY-3002 : Step(183): len = 665766, overlap = 59.625
+PHY-3002 : Step(184): len = 668982, overlap = 62.0312
+PHY-3002 : Step(185): len = 671867, overlap = 68.5938
+PHY-3002 : Step(186): len = 675709, overlap = 58.6875
+PHY-3002 : Step(187): len = 677191, overlap = 59.0625
+PHY-3002 : Step(188): len = 678654, overlap = 62
+PHY-3002 : Step(189): len = 679956, overlap = 60.6875
+PHY-3002 : Step(190): len = 679498, overlap = 58.8438
+PHY-3002 : Step(191): len = 679032, overlap = 57.375
+PHY-3002 : Step(192): len = 679666, overlap = 53.4062
+PHY-3002 : Step(193): len = 678469, overlap = 54.3438
+PHY-3002 : Step(194): len = 678637, overlap = 48.75
+PHY-3002 : Step(195): len = 676485, overlap = 49
+PHY-3002 : Step(196): len = 675177, overlap = 46.6562
+PHY-3002 : Step(197): len = 673085, overlap = 44.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000192411
+PHY-3002 : Step(198): len = 675226, overlap = 43.8438
+PHY-3002 : Step(199): len = 680110, overlap = 42.1875
+PHY-3002 : Step(200): len = 684952, overlap = 41.6875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000384822
+PHY-3002 : Step(201): len = 689188, overlap = 38.25
+PHY-3002 : Step(202): len = 700430, overlap = 32.6875
+PHY-3002 : Step(203): len = 712712, overlap = 34.125
+PHY-3002 : Step(204): len = 713248, overlap = 31.6875
+PHY-3002 : Step(205): len = 713972, overlap = 29.0312
+PHY-3002 : Step(206): len = 715907, overlap = 27.6875
+PHY-3002 : Step(207): len = 716051, overlap = 26.9375
+PHY-3002 : Step(208): len = 717452, overlap = 25.5938
+PHY-3002 : Step(209): len = 717679, overlap = 25.4688
+PHY-3002 : Step(210): len = 717450, overlap = 27.4688
+PHY-3002 : Step(211): len = 716195, overlap = 30.75
+PHY-3002 : Step(212): len = 717713, overlap = 30.6562
+PHY-3002 : Step(213): len = 718502, overlap = 33.8125
+PHY-3002 : Step(214): len = 717726, overlap = 34.5625
+PHY-3002 : Step(215): len = 717082, overlap = 35.75
+PHY-3002 : Step(216): len = 718385, overlap = 37.625
+PHY-3002 : Step(217): len = 720437, overlap = 40.6562
+PHY-3002 : Step(218): len = 719991, overlap = 40.1562
+PHY-3002 : Step(219): len = 718872, overlap = 42.5938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000769643
+PHY-3002 : Step(220): len = 722687, overlap = 40.8125
+PHY-3002 : Step(221): len = 729377, overlap = 43.0312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00129931
+PHY-3002 : Step(222): len = 729064, overlap = 42.3438
+PHY-3002 : Step(223): len = 732948, overlap = 41.4688
+PHY-3002 : Step(224): len = 751223, overlap = 36.4375
+PHY-3002 : Step(225): len = 758058, overlap = 32.875
+PHY-3002 : Step(226): len = 757086, overlap = 33
+PHY-3002 : Step(227): len = 754495, overlap = 30.8125
+PHY-3002 : Step(228): len = 754700, overlap = 32.2812
+PHY-3002 : Step(229): len = 756445, overlap = 32.6562
+PHY-3002 : Step(230): len = 757701, overlap = 34.1875
+PHY-3002 : Step(231): len = 760876, overlap = 36.5312
+PHY-3002 : Step(232): len = 762775, overlap = 39.2812
+PHY-3002 : Step(233): len = 768768, overlap = 38
+PHY-3002 : Step(234): len = 768225, overlap = 36.9688
+PHY-3002 : Step(235): len = 767476, overlap = 35.1875
+PHY-3002 : Step(236): len = 765403, overlap = 35.875
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00218681
+PHY-3002 : Step(237): len = 766378, overlap = 36.4375
+PHY-3002 : Step(238): len = 767596, overlap = 36.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 34/20393.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842504, over cnt = 2829(8%), over = 14475, worst = 53
+PHY-1001 : End global iterations;  1.395587s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (134.4%)
+
+PHY-1001 : Congestion index: top1 = 114.38, top5 = 79.80, top10 = 67.82, top15 = 60.81.
+PHY-3001 : End congestion estimation;  1.675155s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (128.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20215 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.916772s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012059
+PHY-3002 : Step(239): len = 765125, overlap = 230.938
+PHY-3002 : Step(240): len = 764533, overlap = 189.438
+PHY-3002 : Step(241): len = 755774, overlap = 156.719
+PHY-3002 : Step(242): len = 750314, overlap = 143.125
+PHY-3002 : Step(243): len = 741168, overlap = 132.125
+PHY-3002 : Step(244): len = 738298, overlap = 124.625
+PHY-3002 : Step(245): len = 731693, overlap = 128.344
+PHY-3002 : Step(246): len = 727266, overlap = 125.219
+PHY-3002 : Step(247): len = 720656, overlap = 123.5
+PHY-3002 : Step(248): len = 715214, overlap = 126.062
+PHY-3002 : Step(249): len = 710032, overlap = 124.062
+PHY-3002 : Step(250): len = 706529, overlap = 124.75
+PHY-3002 : Step(251): len = 701738, overlap = 128.094
+PHY-3002 : Step(252): len = 699204, overlap = 123.312
+PHY-3002 : Step(253): len = 695437, overlap = 123.625
+PHY-3002 : Step(254): len = 691786, overlap = 129.438
+PHY-3002 : Step(255): len = 688924, overlap = 129.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000241179
+PHY-3002 : Step(256): len = 690633, overlap = 116.281
+PHY-3002 : Step(257): len = 692060, overlap = 114.906
+PHY-3002 : Step(258): len = 695535, overlap = 107.312
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000482359
+PHY-3002 : Step(259): len = 700209, overlap = 102.844
+PHY-3002 : Step(260): len = 704859, overlap = 96.7812
+PHY-3002 : Step(261): len = 706796, overlap = 89.0938
+PHY-3002 : Step(262): len = 708465, overlap = 86.8125
+PHY-3002 : Step(263): len = 710476, overlap = 84.0312
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85154, tnet num: 20215, tinst num: 17807, tnode num: 115622, tedge num: 136628.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.392256s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.9%)
+
+RUN-1004 : used memory is 575 MB, reserved memory is 565 MB, peak memory is 713 MB
+OPT-1001 : Total overflow 428.25 peak overflow 4.50
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 493/20393.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 806360, over cnt = 3155(8%), over = 11934, worst = 43
+PHY-1001 : End global iterations;  1.358665s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (138.0%)
+
+PHY-1001 : Congestion index: top1 = 88.00, top5 = 65.72, top10 = 57.01, top15 = 52.08.
+PHY-1001 : End incremental global routing;  1.672070s wall, 2.171875s user + 0.015625s system = 2.187500s CPU (130.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20215 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.885758s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (98.8%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17671 has valid locations, 350 needs to be replaced
+PHY-3001 : design contains 18106 instances, 7515 luts, 9370 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6033 pins
+PHY-3001 : Found 3515 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 733612
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16664/20692.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 822264, over cnt = 3155(8%), over = 12121, worst = 43
+PHY-1001 : End global iterations;  0.247056s wall, 0.343750s user + 0.031250s system = 0.375000s CPU (151.8%)
+
+PHY-1001 : Congestion index: top1 = 87.84, top5 = 65.93, top10 = 57.24, top15 = 52.34.
+PHY-3001 : End congestion estimation;  0.490558s wall, 0.578125s user + 0.046875s system = 0.625000s CPU (127.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86379, tnet num: 20514, tinst num: 18106, tnode num: 117490, tedge num: 138480.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.440550s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (99.8%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 618 MB, peak memory is 717 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20514 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.407499s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(264): len = 732555, overlap = 1.25
+PHY-3002 : Step(265): len = 732041, overlap = 0.75
+PHY-3002 : Step(266): len = 731602, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16810/20692.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 819664, over cnt = 3184(9%), over = 12156, worst = 43
+PHY-1001 : End global iterations;  0.186821s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (125.5%)
+
+PHY-1001 : Congestion index: top1 = 88.56, top5 = 66.20, top10 = 57.37, top15 = 52.47.
+PHY-3001 : End congestion estimation;  0.432014s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (112.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20514 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.283565s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000442951
+PHY-3002 : Step(267): len = 731380, overlap = 87.3125
+PHY-3002 : Step(268): len = 731615, overlap = 86.8125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000885902
+PHY-3002 : Step(269): len = 731791, overlap = 87.2188
+PHY-3002 : Step(270): len = 732513, overlap = 87.0625
+PHY-3001 : Final: Len = 732513, Over = 87.0625
+PHY-3001 : End incremental placement;  5.209046s wall, 5.343750s user + 0.156250s system = 5.500000s CPU (105.6%)
+
+OPT-1001 : Total overflow 434.44 peak overflow 4.50
+OPT-1001 : End high-fanout net optimization;  8.290840s wall, 9.031250s user + 0.171875s system = 9.203125s CPU (111.0%)
+
+OPT-1001 : Current memory(MB): used = 722, reserve = 716, peak = 738.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16726/20692.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 823816, over cnt = 3138(8%), over = 11154, worst = 43
+PHY-1002 : len = 886200, over cnt = 2231(6%), over = 5461, worst = 34
+PHY-1002 : len = 925776, over cnt = 985(2%), over = 2007, worst = 16
+PHY-1002 : len = 948824, over cnt = 229(0%), over = 426, worst = 15
+PHY-1002 : len = 956664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.914118s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (137.1%)
+
+PHY-1001 : Congestion index: top1 = 64.74, top5 = 55.72, top10 = 51.22, top15 = 48.48.
+OPT-1001 : End congestion update;  2.161847s wall, 2.875000s user + 0.000000s system = 2.875000s CPU (133.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20514 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.789613s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.9%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 62 cells processed and 6984 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 17 cells processed and 550 slack improved
+OPT-1001 : End global optimization;  2.994235s wall, 3.703125s user + 0.000000s system = 3.703125s CPU (123.7%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 695, peak = 738.
+OPT-1001 : End physical optimization;  13.175358s wall, 14.703125s user + 0.203125s system = 14.906250s CPU (113.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7515 LUT to BLE ...
+SYN-4008 : Packed 7515 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6237 remaining SEQ's ...
+SYN-4005 : Packed 4158 SEQ with LUT/SLICE
+SYN-4006 : 514 single LUT's are left
+SYN-4006 : 2079 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9594/13325 primitive instances ...
+PHY-3001 : End packing;  1.577976s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6732 instances
+RUN-1001 : 3292 mslices, 3292 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17688 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10130 nets have 2 pins
+RUN-1001 : 5715 nets have [3 - 5] pins
+RUN-1001 : 1152 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 339 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6730 instances, 6584 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3528 pins
+PHY-3001 : Found 1535 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 743461, Over = 240.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7336/17688.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 901376, over cnt = 2042(5%), over = 3372, worst = 9
+PHY-1002 : len = 908904, over cnt = 1321(3%), over = 1909, worst = 6
+PHY-1002 : len = 921112, over cnt = 599(1%), over = 831, worst = 5
+PHY-1002 : len = 930096, over cnt = 220(0%), over = 282, worst = 5
+PHY-1002 : len = 936264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.628285s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (142.0%)
+
+PHY-1001 : Congestion index: top1 = 61.96, top5 = 53.54, top10 = 49.76, top15 = 47.16.
+PHY-3001 : End congestion estimation;  2.009678s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (133.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73991, tnet num: 17510, tinst num: 6730, tnode num: 96631, tedge num: 124160.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.585071s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.6%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 613 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17510 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.494882s wall, 2.484375s user + 0.015625s system = 2.500000s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.93334e-05
+PHY-3002 : Step(271): len = 731772, overlap = 243
+PHY-3002 : Step(272): len = 724753, overlap = 242
+PHY-3002 : Step(273): len = 719660, overlap = 251
+PHY-3002 : Step(274): len = 715719, overlap = 258.25
+PHY-3002 : Step(275): len = 711852, overlap = 262.75
+PHY-3002 : Step(276): len = 708489, overlap = 265.25
+PHY-3002 : Step(277): len = 705765, overlap = 261
+PHY-3002 : Step(278): len = 703460, overlap = 255
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.86668e-05
+PHY-3002 : Step(279): len = 707317, overlap = 248.5
+PHY-3002 : Step(280): len = 711244, overlap = 240
+PHY-3002 : Step(281): len = 711467, overlap = 237
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000197334
+PHY-3002 : Step(282): len = 718498, overlap = 223
+PHY-3002 : Step(283): len = 727982, overlap = 214.25
+PHY-3002 : Step(284): len = 727373, overlap = 207.5
+PHY-3002 : Step(285): len = 726125, overlap = 205.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.360680s wall, 0.421875s user + 0.562500s system = 0.984375s CPU (272.9%)
+
+PHY-3001 : Trial Legalized: Len = 894609
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 742/17688.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0122e+06, over cnt = 2741(7%), over = 4742, worst = 9
+PHY-1002 : len = 1.0317e+06, over cnt = 1644(4%), over = 2380, worst = 6
+PHY-1002 : len = 1.04747e+06, over cnt = 832(2%), over = 1137, worst = 5
+PHY-1002 : len = 1.05738e+06, over cnt = 430(1%), over = 576, worst = 5
+PHY-1002 : len = 1.06781e+06, over cnt = 13(0%), over = 14, worst = 2
+PHY-1001 : End global iterations;  2.559249s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (139.8%)
+
+PHY-1001 : Congestion index: top1 = 62.07, top5 = 55.77, top10 = 52.26, top15 = 49.94.
+PHY-3001 : End congestion estimation;  3.002686s wall, 4.015625s user + 0.000000s system = 4.015625s CPU (133.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17510 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.843214s wall, 0.796875s user + 0.046875s system = 0.843750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155595
+PHY-3002 : Step(286): len = 854266, overlap = 67.75
+PHY-3002 : Step(287): len = 832080, overlap = 90.25
+PHY-3002 : Step(288): len = 816979, overlap = 110.75
+PHY-3002 : Step(289): len = 804831, overlap = 129
+PHY-3002 : Step(290): len = 794744, overlap = 143
+PHY-3002 : Step(291): len = 786371, overlap = 159.25
+PHY-3002 : Step(292): len = 779936, overlap = 165.5
+PHY-3002 : Step(293): len = 775462, overlap = 174.5
+PHY-3002 : Step(294): len = 771111, overlap = 184
+PHY-3002 : Step(295): len = 768077, overlap = 182.25
+PHY-3002 : Step(296): len = 765645, overlap = 181.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00031119
+PHY-3002 : Step(297): len = 770966, overlap = 175
+PHY-3002 : Step(298): len = 773444, overlap = 177.5
+PHY-3002 : Step(299): len = 774798, overlap = 173.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000539309
+PHY-3002 : Step(300): len = 780640, overlap = 168.5
+PHY-3002 : Step(301): len = 782959, overlap = 168.5
+PHY-3002 : Step(302): len = 785310, overlap = 166
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.083402s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (93.7%)
+
+PHY-3001 : Legalized: Len = 850918, Over = 0
+PHY-3001 : Spreading special nets. 473 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.122815s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.8%)
+
+PHY-3001 : 715 instances has been re-located, deltaX = 291, deltaY = 471, maxDist = 18.
+PHY-3001 : Final: Len = 864330, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73991, tnet num: 17510, tinst num: 6733, tnode num: 96631, tedge num: 124160.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.856013s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (99.3%)
+
+RUN-1004 : used memory is 612 MB, reserved memory is 611 MB, peak memory is 738 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3109/17688.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994096, over cnt = 2612(7%), over = 4295, worst = 7
+PHY-1002 : len = 1.00822e+06, over cnt = 1607(4%), over = 2372, worst = 7
+PHY-1002 : len = 1.02916e+06, over cnt = 527(1%), over = 675, worst = 5
+PHY-1002 : len = 1.03554e+06, over cnt = 238(0%), over = 276, worst = 3
+PHY-1002 : len = 1.04005e+06, over cnt = 8(0%), over = 8, worst = 1
+PHY-1001 : End global iterations;  2.157453s wall, 2.921875s user + 0.046875s system = 2.968750s CPU (137.6%)
+
+PHY-1001 : Congestion index: top1 = 60.65, top5 = 54.04, top10 = 50.55, top15 = 48.31.
+PHY-1001 : End incremental global routing;  2.524927s wall, 3.281250s user + 0.046875s system = 3.328125s CPU (131.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17510 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.857889s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.2%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6641 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6750 instances, 6601 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3590 pins
+PHY-3001 : Found 1539 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 867108
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16123/17701.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04303e+06, over cnt = 70(0%), over = 95, worst = 5
+PHY-1002 : len = 1.04333e+06, over cnt = 32(0%), over = 37, worst = 4
+PHY-1002 : len = 1.04354e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.04366e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.558910s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (106.2%)
+
+PHY-1001 : Congestion index: top1 = 60.67, top5 = 54.04, top10 = 50.57, top15 = 48.33.
+PHY-3001 : End congestion estimation;  0.869298s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (104.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74150, tnet num: 17523, tinst num: 6750, tnode num: 96823, tedge num: 124347.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.805355s wall, 1.734375s user + 0.062500s system = 1.796875s CPU (99.5%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 641 MB, peak memory is 738 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.947599s wall, 2.875000s user + 0.062500s system = 2.937500s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(303): len = 866379, overlap = 0
+PHY-3002 : Step(304): len = 866121, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16117/17701.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0425e+06, over cnt = 44(0%), over = 56, worst = 4
+PHY-1002 : len = 1.04281e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.04286e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.04288e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.544059s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (103.4%)
+
+PHY-1001 : Congestion index: top1 = 60.67, top5 = 54.03, top10 = 50.56, top15 = 48.32.
+PHY-3001 : End congestion estimation;  0.841414s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (102.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.870399s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00116945
+PHY-3002 : Step(305): len = 866118, overlap = 0.75
+PHY-3002 : Step(306): len = 866189, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005822s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (268.4%)
+
+PHY-3001 : Legalized: Len = 866198, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061197s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.1%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 5, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 866260, Over = 0
+PHY-3001 : End incremental placement;  6.022182s wall, 6.046875s user + 0.078125s system = 6.125000s CPU (101.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.886362s wall, 10.640625s user + 0.156250s system = 10.796875s CPU (109.2%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 742, peak = 744.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16114/17701.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04252e+06, over cnt = 35(0%), over = 44, worst = 5
+PHY-1002 : len = 1.04273e+06, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 1.04279e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.04282e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.548018s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (102.6%)
+
+PHY-1001 : Congestion index: top1 = 60.67, top5 = 54.02, top10 = 50.56, top15 = 48.31.
+OPT-1001 : End congestion update;  0.865787s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.706242s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.6%)
+
+OPT-0007 : Start: WNS -1086 TNS -2100 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6662 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6750 instances, 6601 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3590 pins
+PHY-3001 : Found 1539 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 869214, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.057097s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.5%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 2, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 869316, Over = 0
+PHY-3001 : End incremental legalization;  0.367083s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (97.9%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1750 NUM_FEPS 3 with 31 cells processed and 8000 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6662 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6750 instances, 6601 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3590 pins
+PHY-3001 : Found 1539 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 871376, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.057774s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.2%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 8, deltaY = 17, maxDist = 5.
+PHY-3001 : Final: Len = 871802, Over = 0
+PHY-3001 : End incremental legalization;  0.358112s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (96.0%)
+
+OPT-0007 : Iter 2: improved WNS -986 TNS -1750 NUM_FEPS 3 with 14 cells processed and 3439 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6662 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6750 instances, 6601 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3590 pins
+PHY-3001 : Found 1539 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 871650, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059363s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.3%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 0, deltaY = 10, maxDist = 3.
+PHY-3001 : Final: Len = 871694, Over = 0
+PHY-3001 : End incremental legalization;  0.364629s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (115.7%)
+
+OPT-0007 : Iter 3: improved WNS -936 TNS -1650 NUM_FEPS 3 with 8 cells processed and 250 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6662 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6750 instances, 6601 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3590 pins
+PHY-3001 : Found 1539 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 871736, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.055582s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (112.4%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 0, deltaY = 17, maxDist = 5.
+PHY-3001 : Final: Len = 871806, Over = 0
+PHY-3001 : End incremental legalization;  0.355932s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (96.6%)
+
+OPT-0007 : Iter 4: improved WNS -936 TNS -1650 NUM_FEPS 3 with 6 cells processed and 250 slack improved
+OPT-1001 : End path based optimization;  3.509371s wall, 3.859375s user + 0.000000s system = 3.859375s CPU (110.0%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 743, peak = 744.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.706435s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15957/17701.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04871e+06, over cnt = 118(0%), over = 132, worst = 4
+PHY-1002 : len = 1.04863e+06, over cnt = 61(0%), over = 62, worst = 2
+PHY-1002 : len = 1.04895e+06, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 1.04918e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.04927e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.775612s wall, 0.812500s user + 0.046875s system = 0.859375s CPU (110.8%)
+
+PHY-1001 : Congestion index: top1 = 60.75, top5 = 53.98, top10 = 50.57, top15 = 48.36.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.714197s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -936 TNS -1650 NUM_FEPS 3
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 60.379310
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -936ps with logic level 2 
+RUN-1001 :       #2 path slack -890ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 17701 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17701 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6662 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6750 instances, 6601 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3590 pins
+PHY-3001 : Found 1539 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 871806, Over = 0
+PHY-3001 : End spreading;  0.056055s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (111.5%)
+
+PHY-3001 : Final: Len = 871806, Over = 0
+PHY-3001 : End incremental legalization;  0.365250s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.707290s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.4%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16138/17701.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04927e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.126835s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (110.9%)
+
+PHY-1001 : Congestion index: top1 = 60.75, top5 = 53.98, top10 = 50.57, top15 = 48.36.
+OPT-1001 : End congestion update;  0.428552s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.722301s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.5%)
+
+OPT-0007 : Start: WNS -936 TNS -1650 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6662 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6750 instances, 6601 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3590 pins
+PHY-3001 : Found 1539 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 871816, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.056082s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (111.4%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 871868, Over = 0
+PHY-3001 : End incremental legalization;  0.360493s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1650 NUM_FEPS 3 with 3 cells processed and 250 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1650 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.657023s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (106.6%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 743, peak = 744.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16137/17701.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04935e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.126877s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.5%)
+
+PHY-1001 : Congestion index: top1 = 60.75, top5 = 53.99, top10 = 50.58, top15 = 48.37.
+OPT-1001 : End congestion update;  0.425293s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.739731s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.3%)
+
+OPT-0007 : Start: WNS -936 TNS -1650 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -936 TNS -1650 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1650 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.326053s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (99.0%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 743, peak = 744.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.708760s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 739, reserve = 743, peak = 744.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.707632s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.4%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16138/17701.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04935e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.126834s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.6%)
+
+PHY-1001 : Congestion index: top1 = 60.75, top5 = 53.99, top10 = 50.58, top15 = 48.37.
+RUN-1001 : End congestion update;  0.431246s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.5%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.142042s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.9%)
+
+OPT-1001 : Current memory(MB): used = 739, reserve = 743, peak = 744.
+OPT-1001 : End physical optimization;  24.162955s wall, 25.468750s user + 0.218750s system = 25.687500s CPU (106.3%)
+
+RUN-1003 : finish command "place" in  67.150910s wall, 100.156250s user + 6.312500s system = 106.468750s CPU (158.6%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 609 MB, peak memory is 744 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.685782s wall, 2.875000s user + 0.031250s system = 2.906250s CPU (172.4%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 610 MB, peak memory is 744 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6752 instances
+RUN-1001 : 3300 mslices, 3301 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17701 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10118 nets have 2 pins
+RUN-1001 : 5711 nets have [3 - 5] pins
+RUN-1001 : 1168 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 351 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74150, tnet num: 17523, tinst num: 6750, tnode num: 96823, tedge num: 124347.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.581197s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.8%)
+
+RUN-1004 : used memory is 601 MB, reserved memory is 593 MB, peak memory is 744 MB
+PHY-1001 : 3300 mslices, 3301 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 980928, over cnt = 2769(7%), over = 4549, worst = 8
+PHY-1002 : len = 996520, over cnt = 1793(5%), over = 2665, worst = 7
+PHY-1002 : len = 1.01846e+06, over cnt = 694(1%), over = 930, worst = 6
+PHY-1002 : len = 1.03304e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.0333e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.980432s wall, 3.750000s user + 0.015625s system = 3.765625s CPU (126.3%)
+
+PHY-1001 : Congestion index: top1 = 60.11, top5 = 53.84, top10 = 50.40, top15 = 48.12.
+PHY-1001 : End global routing;  3.303846s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (123.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 712, reserve = 719, peak = 744.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 982, reserve = 988, peak = 982.
+PHY-1001 : End build detailed router design. 3.931107s wall, 3.875000s user + 0.062500s system = 3.937500s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271536, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.708668s wall, 4.687500s user + 0.015625s system = 4.703125s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271592, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.651357s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (62.4%)
+
+PHY-1001 : Current memory(MB): used = 1018, reserve = 1024, peak = 1018.
+PHY-1001 : End phase 1; 5.372502s wall, 5.109375s user + 0.015625s system = 5.125000s CPU (95.4%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.52598e+06, over cnt = 1907(0%), over = 1913, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1039, reserve = 1044, peak = 1039.
+PHY-1001 : End initial routed; 36.704018s wall, 64.062500s user + 0.281250s system = 64.343750s CPU (175.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16624(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.884   |  -4.139   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.169085s wall, 3.156250s user + 0.000000s system = 3.156250s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1060, reserve = 1066, peak = 1060.
+PHY-1001 : End phase 2; 39.873171s wall, 67.218750s user + 0.281250s system = 67.500000s CPU (169.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 6 pins with SWNS -1.884ns STNS -3.983ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.145235s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.8%)
+
+PHY-1022 : len = 2.52604e+06, over cnt = 1912(0%), over = 1918, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.408055s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.49159e+06, over cnt = 662(0%), over = 662, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.899819s wall, 3.000000s user + 0.000000s system = 3.000000s CPU (157.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.49074e+06, over cnt = 189(0%), over = 189, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.703919s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (144.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.49081e+06, over cnt = 27(0%), over = 27, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.420875s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (118.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.49117e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.261383s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.49114e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.175938s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16624(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.884   |  -3.983   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.166046s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 622 feed throughs used by 463 nets
+PHY-1001 : End commit to database; 2.241715s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1176, peak = 1166.
+PHY-1001 : End phase 3; 9.660376s wall, 11.140625s user + 0.015625s system = 11.156250s CPU (115.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.884ns STNS -3.983ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.139679s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (89.5%)
+
+PHY-1022 : len = 2.49114e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.367066s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.884ns, -3.983ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16624(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.884   |  -3.983   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.176876s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 622 feed throughs used by 463 nets
+PHY-1001 : End commit to database; 2.348803s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1172, reserve = 1182, peak = 1172.
+PHY-1001 : End phase 4; 5.916979s wall, 5.921875s user + 0.000000s system = 5.921875s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.49114e+06
+PHY-1001 : Current memory(MB): used = 1177, reserve = 1187, peak = 1177.
+PHY-1001 : End export database. 0.148259s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.4%)
+
+PHY-1001 : End detail routing;  65.287173s wall, 93.796875s user + 0.375000s system = 94.171875s CPU (144.2%)
+
+RUN-1003 : finish command "route" in  71.218298s wall, 100.484375s user + 0.406250s system = 100.890625s CPU (141.7%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1106 MB, peak memory is 1177 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10249   out of  19600   52.29%
+#reg                     9509   out of  19600   48.52%
+#le                     12266
+  #lut only              2757   out of  12266   22.48%
+  #reg only              2017   out of  12266   16.44%
+  #lut&reg               7492   out of  12266   61.08%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1801
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1430
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1328
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               975
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    144
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          70
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_pic_cnt/reg1_syn_379.f1                          3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg2_syn_84.f1              2
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P35        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P115       LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12266  |9222    |1027    |9539    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |529    |458     |23      |438     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |101    |90      |4       |89      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |24     |24      |0       |17      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |760    |424     |96      |562     |0       |0       |
+|    u_ADconfig                |AD_config            |186    |138     |25      |137     |0       |0       |
+|    u_gen_sp                  |gen_sp               |266    |166     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |773    |558     |96      |559     |0       |0       |
+|    u_ADconfig                |AD_config            |193    |168     |25      |131     |0       |0       |
+|    u_gen_sp                  |gen_sp               |268    |187     |71      |116     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3015   |2349    |306     |2139    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |190    |132     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2794   |2201    |289     |1962    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |6      |3       |0       |6       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2321   |1863    |253     |1564    |22      |0       |
+|        channelPart           |channel_part_8478    |144    |139     |3       |133     |0       |0       |
+|        fifo_adc              |fifo_adc             |61     |52      |9       |42      |0       |0       |
+|        ram_switch            |ram_switch           |1828   |1447    |197     |1180    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |237    |210     |27      |120     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |993    |639     |170     |695     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |598    |598     |0       |365     |0       |0       |
+|        read_ram_i            |read_ram             |264    |209     |44      |185     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |207    |167     |40      |142     |0       |0       |
+|          read_ram_data       |read_ram_data        |53     |38      |4       |39      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |305    |219     |36      |270     |3       |0       |
+|        u0_soft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3079   |2357    |349     |2176    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |178    |133     |17      |140     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2868   |2208    |332     |2003    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |5       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |5       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2370   |1816    |290     |1577    |22      |1       |
+|        channelPart           |channel_part_8478    |225    |215     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |37      |0       |1       |
+|        ram_switch            |ram_switch           |1702   |1272    |197     |1162    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |221    |193     |27      |121     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |11      |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |12      |0       |0       |
+|          insert              |insert               |1008   |616     |170     |711     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |473    |463     |0       |330     |0       |0       |
+|        read_ram_i            |read_ram_rev         |363    |261     |81      |211     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |294    |211     |73      |161     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |69     |50      |8       |50      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10056  
+    #2         2       3786   
+    #3         3       1404   
+    #4         4        518   
+    #5        5-10     1224   
+    #6       11-50      592   
+    #7       51-100     25    
+    #8        >500       1    
+  Average     2.89            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.062975s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (171.9%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1107 MB, peak memory is 1177 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74150, tnet num: 17523, tinst num: 6750, tnode num: 96823, tedge num: 124347.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.545936s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.1%)
+
+RUN-1004 : used memory is 1101 MB, reserved memory is 1110 MB, peak memory is 1177 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17523 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.466870s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.1%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1113 MB, peak memory is 1177 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6750
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17701, pip num: 177985
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 622
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3251 valid insts, and 490424 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.047378s wall, 69.484375s user + 0.187500s system = 69.671875s CPU (693.4%)
+
+RUN-1004 : used memory is 1263 MB, reserved memory is 1265 MB, peak memory is 1379 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_143701.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_144444.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_144444.log
new file mode 100644
index 0000000..23db6b8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_144444.log
@@ -0,0 +1,1935 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:44:44 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.147122s wall, 2.093750s user + 0.046875s system = 2.140625s CPU (99.7%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 322 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2937 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18472 instances
+RUN-0007 : 7420 luts, 9829 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21056 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14136 nets have 2 pins
+RUN-1001 : 5461 nets have [3 - 5] pins
+RUN-1001 : 1049 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 178 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4257     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18470 instances, 7420 luts, 9829 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6555 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87845, tnet num: 20878, tinst num: 18470, tnode num: 120293, tedge num: 140684.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.183807s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (100.3%)
+
+RUN-1004 : used memory is 545 MB, reserved memory is 529 MB, peak memory is 545 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.975731s wall, 1.937500s user + 0.046875s system = 1.984375s CPU (100.4%)
+
+PHY-3001 : Found 3477 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.19517e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18470.
+PHY-3001 : Level 1 #clusters 2130.
+PHY-3001 : End clustering;  0.127668s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (134.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.25808e+06, overlap = 505.875
+PHY-3002 : Step(2): len = 1.16701e+06, overlap = 523.25
+PHY-3002 : Step(3): len = 826698, overlap = 658.281
+PHY-3002 : Step(4): len = 759006, overlap = 722.594
+PHY-3002 : Step(5): len = 598294, overlap = 851.281
+PHY-3002 : Step(6): len = 536764, overlap = 862.281
+PHY-3002 : Step(7): len = 450689, overlap = 969.406
+PHY-3002 : Step(8): len = 416402, overlap = 1040.41
+PHY-3002 : Step(9): len = 372815, overlap = 1073.5
+PHY-3002 : Step(10): len = 339225, overlap = 1110.72
+PHY-3002 : Step(11): len = 303656, overlap = 1175.06
+PHY-3002 : Step(12): len = 280656, overlap = 1211.56
+PHY-3002 : Step(13): len = 251525, overlap = 1264.91
+PHY-3002 : Step(14): len = 232912, overlap = 1282.53
+PHY-3002 : Step(15): len = 212083, overlap = 1345.5
+PHY-3002 : Step(16): len = 188914, overlap = 1371.09
+PHY-3002 : Step(17): len = 176688, overlap = 1379.19
+PHY-3002 : Step(18): len = 165332, overlap = 1407.22
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.37351e-06
+PHY-3002 : Step(19): len = 166554, overlap = 1381.16
+PHY-3002 : Step(20): len = 197463, overlap = 1259.94
+PHY-3002 : Step(21): len = 201847, overlap = 1280.44
+PHY-3002 : Step(22): len = 202989, overlap = 1299.5
+PHY-3002 : Step(23): len = 201071, overlap = 1251.19
+PHY-3002 : Step(24): len = 199910, overlap = 1235.28
+PHY-3002 : Step(25): len = 197550, overlap = 1201.81
+PHY-3002 : Step(26): len = 196037, overlap = 1184.97
+PHY-3002 : Step(27): len = 193148, overlap = 1176.25
+PHY-3002 : Step(28): len = 191107, overlap = 1150.72
+PHY-3002 : Step(29): len = 189580, overlap = 1144.03
+PHY-3002 : Step(30): len = 189144, overlap = 1166.5
+PHY-3002 : Step(31): len = 188775, overlap = 1174.81
+PHY-3002 : Step(32): len = 189093, overlap = 1187.09
+PHY-3002 : Step(33): len = 188005, overlap = 1174.94
+PHY-3002 : Step(34): len = 187964, overlap = 1167.28
+PHY-3002 : Step(35): len = 188419, overlap = 1144
+PHY-3002 : Step(36): len = 188397, overlap = 1104.03
+PHY-3002 : Step(37): len = 188338, overlap = 1094.81
+PHY-3002 : Step(38): len = 187506, overlap = 1099.75
+PHY-3002 : Step(39): len = 186769, overlap = 1090.97
+PHY-3002 : Step(40): len = 184859, overlap = 1095.22
+PHY-3002 : Step(41): len = 184074, overlap = 1103.44
+PHY-3002 : Step(42): len = 182041, overlap = 1118.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.74701e-06
+PHY-3002 : Step(43): len = 189148, overlap = 1111
+PHY-3002 : Step(44): len = 202380, overlap = 1056.34
+PHY-3002 : Step(45): len = 209055, overlap = 981.469
+PHY-3002 : Step(46): len = 214863, overlap = 978
+PHY-3002 : Step(47): len = 217330, overlap = 951.031
+PHY-3002 : Step(48): len = 218594, overlap = 946.625
+PHY-3002 : Step(49): len = 218094, overlap = 940.156
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.49403e-06
+PHY-3002 : Step(50): len = 228825, overlap = 931.625
+PHY-3002 : Step(51): len = 250844, overlap = 884.625
+PHY-3002 : Step(52): len = 261039, overlap = 842.75
+PHY-3002 : Step(53): len = 267482, overlap = 814.656
+PHY-3002 : Step(54): len = 269467, overlap = 792.562
+PHY-3002 : Step(55): len = 269925, overlap = 769.625
+PHY-3002 : Step(56): len = 270962, overlap = 759.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.09881e-05
+PHY-3002 : Step(57): len = 292988, overlap = 720.688
+PHY-3002 : Step(58): len = 319311, overlap = 647.688
+PHY-3002 : Step(59): len = 330198, overlap = 585.75
+PHY-3002 : Step(60): len = 332090, overlap = 560.844
+PHY-3002 : Step(61): len = 327411, overlap = 554.031
+PHY-3002 : Step(62): len = 325043, overlap = 533.875
+PHY-3002 : Step(63): len = 320877, overlap = 515.531
+PHY-3002 : Step(64): len = 320269, overlap = 517.719
+PHY-3002 : Step(65): len = 318805, overlap = 522.594
+PHY-3002 : Step(66): len = 317957, overlap = 521.781
+PHY-3002 : Step(67): len = 317230, overlap = 521.906
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.19761e-05
+PHY-3002 : Step(68): len = 338383, overlap = 493.312
+PHY-3002 : Step(69): len = 353865, overlap = 478.844
+PHY-3002 : Step(70): len = 356731, overlap = 447.375
+PHY-3002 : Step(71): len = 358812, overlap = 421.906
+PHY-3002 : Step(72): len = 358948, overlap = 421.125
+PHY-3002 : Step(73): len = 360870, overlap = 417.25
+PHY-3002 : Step(74): len = 358334, overlap = 402.062
+PHY-3002 : Step(75): len = 359422, overlap = 381.219
+PHY-3002 : Step(76): len = 360533, overlap = 374.219
+PHY-3002 : Step(77): len = 360510, overlap = 365.594
+PHY-3002 : Step(78): len = 359183, overlap = 352.125
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.39522e-05
+PHY-3002 : Step(79): len = 375575, overlap = 324.75
+PHY-3002 : Step(80): len = 389029, overlap = 315.062
+PHY-3002 : Step(81): len = 389364, overlap = 318.188
+PHY-3002 : Step(82): len = 391595, overlap = 316.531
+PHY-3002 : Step(83): len = 394986, overlap = 305.094
+PHY-3002 : Step(84): len = 397974, overlap = 296.469
+PHY-3002 : Step(85): len = 395477, overlap = 295.75
+PHY-3002 : Step(86): len = 396453, overlap = 307.281
+PHY-3002 : Step(87): len = 398101, overlap = 300.5
+PHY-3002 : Step(88): len = 400022, overlap = 270.969
+PHY-3002 : Step(89): len = 398055, overlap = 274.938
+PHY-3002 : Step(90): len = 398440, overlap = 281
+PHY-3002 : Step(91): len = 398794, overlap = 296.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.79044e-05
+PHY-3002 : Step(92): len = 417329, overlap = 302.781
+PHY-3002 : Step(93): len = 431341, overlap = 291.125
+PHY-3002 : Step(94): len = 430400, overlap = 268.594
+PHY-3002 : Step(95): len = 430375, overlap = 262.719
+PHY-3002 : Step(96): len = 431517, overlap = 266.938
+PHY-3002 : Step(97): len = 432622, overlap = 267.438
+PHY-3002 : Step(98): len = 430061, overlap = 269.812
+PHY-3002 : Step(99): len = 431864, overlap = 281.094
+PHY-3002 : Step(100): len = 433882, overlap = 272.156
+PHY-3002 : Step(101): len = 435795, overlap = 255.25
+PHY-3002 : Step(102): len = 433683, overlap = 257.156
+PHY-3002 : Step(103): len = 433380, overlap = 259.938
+PHY-3002 : Step(104): len = 434241, overlap = 257.219
+PHY-3002 : Step(105): len = 435415, overlap = 253.094
+PHY-3002 : Step(106): len = 432251, overlap = 249.281
+PHY-3002 : Step(107): len = 432128, overlap = 245.812
+PHY-3002 : Step(108): len = 433159, overlap = 248.719
+PHY-3002 : Step(109): len = 434278, overlap = 243.219
+PHY-3002 : Step(110): len = 431771, overlap = 244.531
+PHY-3002 : Step(111): len = 431463, overlap = 244.188
+PHY-3002 : Step(112): len = 432661, overlap = 245.594
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000175809
+PHY-3002 : Step(113): len = 445813, overlap = 232.594
+PHY-3002 : Step(114): len = 454759, overlap = 227.406
+PHY-3002 : Step(115): len = 454772, overlap = 229.562
+PHY-3002 : Step(116): len = 455001, overlap = 225.031
+PHY-3002 : Step(117): len = 456019, overlap = 224.344
+PHY-3002 : Step(118): len = 457229, overlap = 229.281
+PHY-3002 : Step(119): len = 456170, overlap = 231.406
+PHY-3002 : Step(120): len = 457185, overlap = 225.344
+PHY-3002 : Step(121): len = 459177, overlap = 213.938
+PHY-3002 : Step(122): len = 460204, overlap = 216.531
+PHY-3002 : Step(123): len = 458623, overlap = 223.625
+PHY-3002 : Step(124): len = 458377, overlap = 218.625
+PHY-3002 : Step(125): len = 459246, overlap = 218.656
+PHY-3002 : Step(126): len = 460414, overlap = 226.031
+PHY-3002 : Step(127): len = 459496, overlap = 229.469
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000335646
+PHY-3002 : Step(128): len = 467219, overlap = 222.219
+PHY-3002 : Step(129): len = 474754, overlap = 222.688
+PHY-3002 : Step(130): len = 475456, overlap = 215.062
+PHY-3002 : Step(131): len = 476608, overlap = 218.5
+PHY-3002 : Step(132): len = 479144, overlap = 220.219
+PHY-3002 : Step(133): len = 481228, overlap = 220.938
+PHY-3002 : Step(134): len = 481311, overlap = 214.156
+PHY-3002 : Step(135): len = 481888, overlap = 206.438
+PHY-3002 : Step(136): len = 483617, overlap = 210.844
+PHY-3002 : Step(137): len = 485140, overlap = 208.719
+PHY-3002 : Step(138): len = 485054, overlap = 202.312
+PHY-3002 : Step(139): len = 484714, overlap = 197.844
+PHY-3002 : Step(140): len = 484967, overlap = 194.156
+PHY-3002 : Step(141): len = 485667, overlap = 183.469
+PHY-3002 : Step(142): len = 484684, overlap = 179.156
+PHY-3002 : Step(143): len = 484891, overlap = 176.406
+PHY-3002 : Step(144): len = 486060, overlap = 180.094
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000671291
+PHY-3002 : Step(145): len = 491460, overlap = 178.281
+PHY-3002 : Step(146): len = 498211, overlap = 171.188
+PHY-3002 : Step(147): len = 499447, overlap = 165.531
+PHY-3002 : Step(148): len = 500738, overlap = 157.656
+PHY-3002 : Step(149): len = 502384, overlap = 152.781
+PHY-3002 : Step(150): len = 503448, overlap = 153.5
+PHY-3002 : Step(151): len = 503444, overlap = 146.219
+PHY-3002 : Step(152): len = 503762, overlap = 147.156
+PHY-3002 : Step(153): len = 504196, overlap = 138.125
+PHY-3002 : Step(154): len = 504627, overlap = 135.375
+PHY-3002 : Step(155): len = 504760, overlap = 138.344
+PHY-3002 : Step(156): len = 505924, overlap = 142.594
+PHY-3002 : Step(157): len = 506876, overlap = 139.5
+PHY-3002 : Step(158): len = 507681, overlap = 142.344
+PHY-3002 : Step(159): len = 507956, overlap = 135.938
+PHY-3002 : Step(160): len = 508244, overlap = 134.75
+PHY-3002 : Step(161): len = 508747, overlap = 134.562
+PHY-3002 : Step(162): len = 508909, overlap = 135.094
+PHY-3002 : Step(163): len = 508670, overlap = 133.188
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00122291
+PHY-3002 : Step(164): len = 511411, overlap = 128.406
+PHY-3002 : Step(165): len = 515599, overlap = 127.812
+PHY-3002 : Step(166): len = 516236, overlap = 122.156
+PHY-3002 : Step(167): len = 516798, overlap = 114.5
+PHY-3002 : Step(168): len = 517797, overlap = 114.469
+PHY-3002 : Step(169): len = 518427, overlap = 123.969
+PHY-3002 : Step(170): len = 518405, overlap = 120.969
+PHY-3002 : Step(171): len = 518626, overlap = 121.031
+PHY-3002 : Step(172): len = 519277, overlap = 117.781
+PHY-3002 : Step(173): len = 519537, overlap = 118.594
+PHY-3002 : Step(174): len = 519079, overlap = 123.469
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0020508
+PHY-3002 : Step(175): len = 521420, overlap = 121.844
+PHY-3002 : Step(176): len = 526353, overlap = 109.25
+PHY-3002 : Step(177): len = 526930, overlap = 109.125
+PHY-3002 : Step(178): len = 527395, overlap = 117.25
+PHY-3002 : Step(179): len = 528458, overlap = 118.688
+PHY-3002 : Step(180): len = 529533, overlap = 114.594
+PHY-3002 : Step(181): len = 529492, overlap = 121.094
+PHY-3002 : Step(182): len = 529552, overlap = 120.125
+PHY-3002 : Step(183): len = 529743, overlap = 122.594
+PHY-3002 : Step(184): len = 529931, overlap = 120.406
+PHY-3002 : Step(185): len = 529822, overlap = 122.5
+PHY-3002 : Step(186): len = 529628, overlap = 123.531
+PHY-3002 : Step(187): len = 529596, overlap = 123.875
+PHY-3002 : Step(188): len = 529794, overlap = 121.25
+PHY-3002 : Step(189): len = 529842, overlap = 126.031
+PHY-3002 : Step(190): len = 529892, overlap = 123.969
+PHY-3002 : Step(191): len = 529817, overlap = 121.25
+PHY-3002 : Step(192): len = 529835, overlap = 125.062
+PHY-3002 : Step(193): len = 529882, overlap = 126
+PHY-3002 : Step(194): len = 529901, overlap = 125.438
+PHY-3002 : Step(195): len = 529911, overlap = 126.344
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.017347s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (90.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21056.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 682496, over cnt = 1636(4%), over = 7650, worst = 43
+PHY-1001 : End global iterations;  0.697704s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (132.1%)
+
+PHY-1001 : Congestion index: top1 = 86.72, top5 = 66.22, top10 = 54.33, top15 = 47.67.
+PHY-3001 : End congestion estimation;  0.921543s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (125.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.854979s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.31248e-05
+PHY-3002 : Step(196): len = 621567, overlap = 76.375
+PHY-3002 : Step(197): len = 630174, overlap = 78.1562
+PHY-3002 : Step(198): len = 627622, overlap = 75.75
+PHY-3002 : Step(199): len = 626288, overlap = 66.1562
+PHY-3002 : Step(200): len = 627222, overlap = 71.9062
+PHY-3002 : Step(201): len = 636493, overlap = 73.0312
+PHY-3002 : Step(202): len = 648591, overlap = 72
+PHY-3002 : Step(203): len = 654493, overlap = 68.3125
+PHY-3002 : Step(204): len = 658326, overlap = 78.2188
+PHY-3002 : Step(205): len = 664693, overlap = 68.0625
+PHY-3002 : Step(206): len = 666667, overlap = 67.6875
+PHY-3002 : Step(207): len = 669075, overlap = 68.0625
+PHY-3002 : Step(208): len = 673650, overlap = 64.8125
+PHY-3002 : Step(209): len = 676258, overlap = 56.0312
+PHY-3002 : Step(210): len = 679197, overlap = 46.5312
+PHY-3002 : Step(211): len = 678440, overlap = 36.875
+PHY-3002 : Step(212): len = 678508, overlap = 35
+PHY-3002 : Step(213): len = 675310, overlap = 31.75
+PHY-3002 : Step(214): len = 674319, overlap = 30.8125
+PHY-3002 : Step(215): len = 671555, overlap = 31.7812
+PHY-3002 : Step(216): len = 669968, overlap = 33.0312
+PHY-3002 : Step(217): len = 668400, overlap = 32.4375
+PHY-3002 : Step(218): len = 667202, overlap = 33.75
+PHY-3002 : Step(219): len = 665391, overlap = 27.625
+PHY-3002 : Step(220): len = 664717, overlap = 27.6562
+PHY-3002 : Step(221): len = 662405, overlap = 29.25
+PHY-3002 : Step(222): len = 661362, overlap = 29.5312
+PHY-3002 : Step(223): len = 660094, overlap = 33.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00018625
+PHY-3002 : Step(224): len = 661934, overlap = 31.5
+PHY-3002 : Step(225): len = 665643, overlap = 28.4062
+PHY-3002 : Step(226): len = 670778, overlap = 26.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000372499
+PHY-3002 : Step(227): len = 673260, overlap = 28.875
+PHY-3002 : Step(228): len = 685405, overlap = 30
+PHY-3002 : Step(229): len = 699661, overlap = 28.5625
+PHY-3002 : Step(230): len = 700201, overlap = 27.7812
+PHY-3002 : Step(231): len = 700270, overlap = 26.375
+PHY-3002 : Step(232): len = 700334, overlap = 25.6875
+PHY-3002 : Step(233): len = 703123, overlap = 29.7188
+PHY-3002 : Step(234): len = 703621, overlap = 30.5
+PHY-3002 : Step(235): len = 707031, overlap = 30.8125
+PHY-3002 : Step(236): len = 705724, overlap = 32.4062
+PHY-3002 : Step(237): len = 705308, overlap = 31.9375
+PHY-3002 : Step(238): len = 703432, overlap = 31.8438
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000744998
+PHY-3002 : Step(239): len = 707300, overlap = 29.5312
+PHY-3002 : Step(240): len = 712399, overlap = 32.7812
+PHY-3002 : Step(241): len = 716895, overlap = 30.5938
+PHY-3002 : Step(242): len = 726162, overlap = 36.6875
+PHY-3002 : Step(243): len = 728506, overlap = 39.7188
+PHY-3002 : Step(244): len = 730377, overlap = 42.6875
+PHY-3002 : Step(245): len = 732798, overlap = 42.5938
+PHY-3002 : Step(246): len = 730736, overlap = 43.1562
+PHY-3002 : Step(247): len = 730916, overlap = 42.5312
+PHY-3002 : Step(248): len = 731906, overlap = 43.5625
+PHY-3002 : Step(249): len = 734403, overlap = 42.1875
+PHY-3002 : Step(250): len = 735570, overlap = 45.25
+PHY-3002 : Step(251): len = 731210, overlap = 42.9062
+PHY-3002 : Step(252): len = 729836, overlap = 43.75
+PHY-3002 : Step(253): len = 729181, overlap = 42.4375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00126035
+PHY-3002 : Step(254): len = 730628, overlap = 42.8438
+PHY-3002 : Step(255): len = 735052, overlap = 45.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 24/21056.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812472, over cnt = 2689(7%), over = 14514, worst = 73
+PHY-1001 : End global iterations;  1.459072s wall, 1.937500s user + 0.015625s system = 1.953125s CPU (133.9%)
+
+PHY-1001 : Congestion index: top1 = 117.76, top5 = 80.12, top10 = 67.67, top15 = 60.59.
+PHY-3001 : End congestion estimation;  1.740982s wall, 2.234375s user + 0.015625s system = 2.250000s CPU (129.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.276883s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00010882
+PHY-3002 : Step(256): len = 734316, overlap = 265.344
+PHY-3002 : Step(257): len = 740297, overlap = 221.688
+PHY-3002 : Step(258): len = 727943, overlap = 212.938
+PHY-3002 : Step(259): len = 723225, overlap = 193.406
+PHY-3002 : Step(260): len = 718364, overlap = 180.094
+PHY-3002 : Step(261): len = 715575, overlap = 171.25
+PHY-3002 : Step(262): len = 710066, overlap = 159.188
+PHY-3002 : Step(263): len = 705715, overlap = 154.062
+PHY-3002 : Step(264): len = 702380, overlap = 154.031
+PHY-3002 : Step(265): len = 698485, overlap = 158.375
+PHY-3002 : Step(266): len = 694224, overlap = 152.219
+PHY-3002 : Step(267): len = 691072, overlap = 152
+PHY-3002 : Step(268): len = 686738, overlap = 156
+PHY-3002 : Step(269): len = 685591, overlap = 162.344
+PHY-3002 : Step(270): len = 681332, overlap = 164.875
+PHY-3002 : Step(271): len = 679363, overlap = 160.125
+PHY-3002 : Step(272): len = 675694, overlap = 155.781
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000217639
+PHY-3002 : Step(273): len = 678028, overlap = 152.656
+PHY-3002 : Step(274): len = 679709, overlap = 147.094
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00036017
+PHY-3002 : Step(275): len = 683718, overlap = 134.156
+PHY-3002 : Step(276): len = 690837, overlap = 127.312
+PHY-3002 : Step(277): len = 701338, overlap = 116.844
+PHY-3002 : Step(278): len = 696610, overlap = 119.281
+PHY-3002 : Step(279): len = 694542, overlap = 119.188
+PHY-3002 : Step(280): len = 692036, overlap = 120.062
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000663606
+PHY-3002 : Step(281): len = 696653, overlap = 113.75
+PHY-3002 : Step(282): len = 704365, overlap = 102.125
+PHY-3002 : Step(283): len = 710351, overlap = 98.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87845, tnet num: 20878, tinst num: 18470, tnode num: 120293, tedge num: 140684.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.428925s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.6%)
+
+RUN-1004 : used memory is 588 MB, reserved memory is 577 MB, peak memory is 730 MB
+OPT-1001 : Total overflow 448.91 peak overflow 3.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 608/21056.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 800408, over cnt = 3278(9%), over = 12246, worst = 49
+PHY-1001 : End global iterations;  1.387620s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (143.0%)
+
+PHY-1001 : Congestion index: top1 = 78.06, top5 = 64.49, top10 = 57.00, top15 = 52.46.
+PHY-1001 : End incremental global routing;  1.742652s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (133.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.921007s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.1%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18334 has valid locations, 328 needs to be replaced
+PHY-3001 : design contains 18747 instances, 7521 luts, 10005 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6680 pins
+PHY-3001 : Found 3514 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 732784
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17490/21333.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 815816, over cnt = 3287(9%), over = 12317, worst = 49
+PHY-1001 : End global iterations;  0.220142s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (127.8%)
+
+PHY-1001 : Congestion index: top1 = 78.99, top5 = 64.71, top10 = 57.29, top15 = 52.78.
+PHY-3001 : End congestion estimation;  0.474552s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (115.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88965, tnet num: 21155, tinst num: 18747, tnode num: 121963, tedge num: 142370.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.452867s wall, 1.390625s user + 0.062500s system = 1.453125s CPU (100.0%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 637 MB, peak memory is 732 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21155 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.411438s wall, 2.296875s user + 0.109375s system = 2.406250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(284): len = 731573, overlap = 1.375
+PHY-3002 : Step(285): len = 731023, overlap = 1.3125
+PHY-3002 : Step(286): len = 730570, overlap = 1.0625
+PHY-3002 : Step(287): len = 730233, overlap = 1
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17580/21333.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 813328, over cnt = 3295(9%), over = 12352, worst = 49
+PHY-1001 : End global iterations;  0.188739s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (132.5%)
+
+PHY-1001 : Congestion index: top1 = 79.16, top5 = 65.11, top10 = 57.63, top15 = 53.09.
+PHY-3001 : End congestion estimation;  0.437570s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (114.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21155 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.934569s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000367252
+PHY-3002 : Step(288): len = 730180, overlap = 101.125
+PHY-3002 : Step(289): len = 730223, overlap = 100.656
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000734505
+PHY-3002 : Step(290): len = 730665, overlap = 101.062
+PHY-3002 : Step(291): len = 731211, overlap = 100.969
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00146901
+PHY-3002 : Step(292): len = 731377, overlap = 100.625
+PHY-3002 : Step(293): len = 732163, overlap = 100.969
+PHY-3001 : Final: Len = 732163, Over = 100.969
+PHY-3001 : End incremental placement;  5.068473s wall, 5.187500s user + 0.453125s system = 5.640625s CPU (111.3%)
+
+OPT-1001 : Total overflow 455.97 peak overflow 3.97
+OPT-1001 : End high-fanout net optimization;  8.269751s wall, 9.062500s user + 0.468750s system = 9.531250s CPU (115.3%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 729, peak = 753.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17507/21333.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 817544, over cnt = 3246(9%), over = 11365, worst = 49
+PHY-1002 : len = 879848, over cnt = 2394(6%), over = 5771, worst = 22
+PHY-1002 : len = 916720, over cnt = 1209(3%), over = 2878, worst = 22
+PHY-1002 : len = 946544, over cnt = 365(1%), over = 848, worst = 13
+PHY-1002 : len = 960936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.379641s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (111.0%)
+
+PHY-1001 : Congestion index: top1 = 64.12, top5 = 56.66, top10 = 52.38, top15 = 49.53.
+OPT-1001 : End congestion update;  2.631391s wall, 2.890625s user + 0.000000s system = 2.890625s CPU (109.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21155 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.845355s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 49 cells processed and 12750 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 58 cells processed and 3850 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 26 cells processed and 1468 slack improved
+OPT-1001 : End global optimization;  3.521851s wall, 3.781250s user + 0.000000s system = 3.781250s CPU (107.4%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 713, peak = 753.
+OPT-1001 : End physical optimization;  13.856804s wall, 14.875000s user + 0.515625s system = 15.390625s CPU (111.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7521 LUT to BLE ...
+SYN-4008 : Packed 7521 LUT and 3155 SEQ to BLE.
+SYN-4003 : Packing 6850 remaining SEQ's ...
+SYN-4005 : Packed 4135 SEQ with LUT/SLICE
+SYN-4006 : 541 single LUT's are left
+SYN-4006 : 2715 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10236/13967 primitive instances ...
+PHY-3001 : End packing;  1.726040s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (100.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6989 instances
+RUN-1001 : 3420 mslices, 3421 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18307 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10786 nets have 2 pins
+RUN-1001 : 5691 nets have [3 - 5] pins
+RUN-1001 : 1140 nets have [6 - 10] pins
+RUN-1001 : 320 nets have [11 - 20] pins
+RUN-1001 : 338 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6987 instances, 6841 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3825 pins
+PHY-3001 : Found 1558 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 738484, Over = 300.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7671/18307.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896712, over cnt = 2093(5%), over = 3370, worst = 8
+PHY-1002 : len = 903080, over cnt = 1494(4%), over = 2172, worst = 7
+PHY-1002 : len = 915240, over cnt = 766(2%), over = 1058, worst = 6
+PHY-1002 : len = 924408, over cnt = 358(1%), over = 501, worst = 5
+PHY-1002 : len = 932848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.658675s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (144.1%)
+
+PHY-1001 : Congestion index: top1 = 61.75, top5 = 55.09, top10 = 50.87, top15 = 47.80.
+PHY-3001 : End congestion estimation;  2.039904s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (135.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75644, tnet num: 18129, tinst num: 6987, tnode num: 99391, tedge num: 126619.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.611353s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (99.9%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 627 MB, peak memory is 753 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18129 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.484663s wall, 2.437500s user + 0.046875s system = 2.484375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.6792e-05
+PHY-3002 : Step(294): len = 724507, overlap = 300.5
+PHY-3002 : Step(295): len = 716339, overlap = 295.75
+PHY-3002 : Step(296): len = 710976, overlap = 284.75
+PHY-3002 : Step(297): len = 706676, overlap = 288.5
+PHY-3002 : Step(298): len = 703298, overlap = 296.25
+PHY-3002 : Step(299): len = 700016, overlap = 297.75
+PHY-3002 : Step(300): len = 696677, overlap = 303.25
+PHY-3002 : Step(301): len = 694025, overlap = 309
+PHY-3002 : Step(302): len = 691225, overlap = 312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.3584e-05
+PHY-3002 : Step(303): len = 693987, overlap = 304.25
+PHY-3002 : Step(304): len = 698785, overlap = 294
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000187168
+PHY-3002 : Step(305): len = 704541, overlap = 287.5
+PHY-3002 : Step(306): len = 717226, overlap = 266.25
+PHY-3002 : Step(307): len = 718529, overlap = 256.75
+PHY-3002 : Step(308): len = 717837, overlap = 254.5
+PHY-3002 : Step(309): len = 717701, overlap = 251.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.334688s wall, 0.343750s user + 0.406250s system = 0.750000s CPU (224.1%)
+
+PHY-3001 : Trial Legalized: Len = 934066
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 600/18307.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0534e+06, over cnt = 2994(8%), over = 5135, worst = 8
+PHY-1002 : len = 1.07282e+06, over cnt = 1841(5%), over = 2778, worst = 6
+PHY-1002 : len = 1.08977e+06, over cnt = 940(2%), over = 1481, worst = 6
+PHY-1002 : len = 1.11637e+06, over cnt = 109(0%), over = 157, worst = 6
+PHY-1002 : len = 1.11974e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.539027s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 65.99, top5 = 59.29, top10 = 55.55, top15 = 52.99.
+PHY-3001 : End congestion estimation;  2.980766s wall, 4.062500s user + 0.000000s system = 4.062500s CPU (136.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18129 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.861734s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165635
+PHY-3002 : Step(310): len = 886587, overlap = 76
+PHY-3002 : Step(311): len = 861728, overlap = 102
+PHY-3002 : Step(312): len = 843325, overlap = 130
+PHY-3002 : Step(313): len = 830750, overlap = 148.75
+PHY-3002 : Step(314): len = 821880, overlap = 156.75
+PHY-3002 : Step(315): len = 813075, overlap = 169.25
+PHY-3002 : Step(316): len = 805515, overlap = 180.25
+PHY-3002 : Step(317): len = 800173, overlap = 185.5
+PHY-3002 : Step(318): len = 794708, overlap = 194
+PHY-3002 : Step(319): len = 790731, overlap = 197
+PHY-3002 : Step(320): len = 787445, overlap = 195.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00033127
+PHY-3002 : Step(321): len = 792475, overlap = 191
+PHY-3002 : Step(322): len = 796117, overlap = 186.5
+PHY-3002 : Step(323): len = 797260, overlap = 186.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000583746
+PHY-3002 : Step(324): len = 804948, overlap = 176.75
+PHY-3002 : Step(325): len = 806478, overlap = 177.5
+PHY-3002 : Step(326): len = 809751, overlap = 172
+PHY-3002 : Step(327): len = 810577, overlap = 172
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.082601s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (113.5%)
+
+PHY-3001 : Legalized: Len = 889239, Over = 0
+PHY-3001 : Spreading special nets. 490 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.113970s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (109.7%)
+
+PHY-3001 : 723 instances has been re-located, deltaX = 304, deltaY = 446, maxDist = 4.
+PHY-3001 : Final: Len = 900651, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75644, tnet num: 18129, tinst num: 6990, tnode num: 99391, tedge num: 126619.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.842850s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.0%)
+
+RUN-1004 : used memory is 645 MB, reserved memory is 661 MB, peak memory is 753 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3257/18307.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03311e+06, over cnt = 2718(7%), over = 4578, worst = 8
+PHY-1002 : len = 1.04705e+06, over cnt = 1733(4%), over = 2593, worst = 7
+PHY-1002 : len = 1.07023e+06, over cnt = 537(1%), over = 726, worst = 7
+PHY-1002 : len = 1.08027e+06, over cnt = 79(0%), over = 100, worst = 4
+PHY-1002 : len = 1.08208e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.152580s wall, 3.078125s user + 0.000000s system = 3.078125s CPU (143.0%)
+
+PHY-1001 : Congestion index: top1 = 63.17, top5 = 56.96, top10 = 53.51, top15 = 51.16.
+PHY-1001 : End incremental global routing;  2.510352s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (136.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18129 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.869862s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (98.8%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6898 has valid locations, 18 needs to be replaced
+PHY-3001 : design contains 7004 instances, 6855 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3899 pins
+PHY-3001 : Found 1561 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 902968
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16802/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08421e+06, over cnt = 58(0%), over = 64, worst = 3
+PHY-1002 : len = 1.08433e+06, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 1.08451e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.08461e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.607953s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (102.8%)
+
+PHY-1001 : Congestion index: top1 = 63.17, top5 = 56.97, top10 = 53.53, top15 = 51.17.
+PHY-3001 : End congestion estimation;  0.936418s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (101.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75770, tnet num: 18144, tinst num: 7004, tnode num: 99549, tedge num: 126773.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.839309s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.2%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 689 MB, peak memory is 753 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.716999s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(328): len = 902037, overlap = 0
+PHY-3002 : Step(329): len = 901699, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16792/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08291e+06, over cnt = 38(0%), over = 42, worst = 4
+PHY-1002 : len = 1.08298e+06, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 1.08308e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.08311e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.579377s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 63.17, top5 = 56.97, top10 = 53.52, top15 = 51.17.
+PHY-3001 : End congestion estimation;  0.890046s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (101.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.869362s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000138989
+PHY-3002 : Step(330): len = 901564, overlap = 1
+PHY-3002 : Step(331): len = 901564, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005521s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (283.0%)
+
+PHY-3001 : Legalized: Len = 901645, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058179s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.4%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 901577, Over = 0
+PHY-3001 : End incremental placement;  5.891860s wall, 5.984375s user + 0.156250s system = 6.140625s CPU (104.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.849423s wall, 10.859375s user + 0.156250s system = 11.015625s CPU (111.8%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 756, peak = 760.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16785/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08281e+06, over cnt = 24(0%), over = 29, worst = 3
+PHY-1002 : len = 1.08286e+06, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 1.08296e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.08302e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.581833s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 63.21, top5 = 56.99, top10 = 53.52, top15 = 51.16.
+OPT-1001 : End congestion update;  0.895508s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (104.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.722287s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.5%)
+
+OPT-0007 : Start: WNS -1633 TNS -2947 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6916 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7004 instances, 6855 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3899 pins
+PHY-3001 : Found 1561 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 903379, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059391s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.2%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 11, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 903517, Over = 0
+PHY-3001 : End incremental legalization;  0.378918s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.0%)
+
+OPT-0007 : Iter 1: improved WNS -1633 TNS -2818 NUM_FEPS 2 with 27 cells processed and 7400 slack improved
+OPT-0007 : Iter 2: improved WNS -1633 TNS -2818 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.141624s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (101.4%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 755, peak = 760.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.720935s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16673/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08462e+06, over cnt = 112(0%), over = 134, worst = 4
+PHY-1002 : len = 1.08483e+06, over cnt = 73(0%), over = 74, worst = 2
+PHY-1002 : len = 1.08533e+06, over cnt = 31(0%), over = 31, worst = 1
+PHY-1002 : len = 1.08586e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.08591e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.845752s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (105.3%)
+
+PHY-1001 : Congestion index: top1 = 63.38, top5 = 57.08, top10 = 53.53, top15 = 51.14.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.755446s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1633 TNS -2818 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 62.965517
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1633ps with logic level 2 
+RUN-1001 :       #2 path slack -1547ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 18322 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 18322 nets
+OPT-1001 : End physical optimization;  16.850932s wall, 17.906250s user + 0.187500s system = 18.093750s CPU (107.4%)
+
+RUN-1003 : finish command "place" in  62.329067s wall, 98.234375s user + 6.328125s system = 104.562500s CPU (167.8%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 619 MB, peak memory is 760 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.713888s wall, 2.968750s user + 0.000000s system = 2.968750s CPU (173.2%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 620 MB, peak memory is 760 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7006 instances
+RUN-1001 : 3426 mslices, 3429 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18322 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10787 nets have 2 pins
+RUN-1001 : 5693 nets have [3 - 5] pins
+RUN-1001 : 1140 nets have [6 - 10] pins
+RUN-1001 : 324 nets have [11 - 20] pins
+RUN-1001 : 349 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75770, tnet num: 18144, tinst num: 7004, tnode num: 99549, tedge num: 126773.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.601472s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.5%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 644 MB, peak memory is 760 MB
+PHY-1001 : 3426 mslices, 3429 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.01318e+06, over cnt = 2889(8%), over = 4955, worst = 8
+PHY-1002 : len = 1.03244e+06, over cnt = 1886(5%), over = 2815, worst = 8
+PHY-1002 : len = 1.05026e+06, over cnt = 1052(2%), over = 1487, worst = 7
+PHY-1002 : len = 1.07289e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.785312s wall, 3.812500s user + 0.093750s system = 3.906250s CPU (140.2%)
+
+PHY-1001 : Congestion index: top1 = 63.36, top5 = 57.02, top10 = 53.47, top15 = 50.95.
+PHY-1001 : End global routing;  3.107772s wall, 4.140625s user + 0.093750s system = 4.234375s CPU (136.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 725, reserve = 730, peak = 760.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1002, reserve = 1006, peak = 1002.
+PHY-1001 : End build detailed router design. 4.139866s wall, 4.109375s user + 0.031250s system = 4.140625s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 263904, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.855459s wall, 4.843750s user + 0.015625s system = 4.859375s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 263960, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.402365s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.0%)
+
+PHY-1001 : Current memory(MB): used = 1037, reserve = 1042, peak = 1037.
+PHY-1001 : End phase 1; 5.269195s wall, 5.265625s user + 0.015625s system = 5.281250s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.55074e+06, over cnt = 2102(0%), over = 2111, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1056, peak = 1054.
+PHY-1001 : End initial routed; 41.445293s wall, 68.296875s user + 0.406250s system = 68.703125s CPU (165.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.672   |  -4.968   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.263075s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1062, reserve = 1065, peak = 1062.
+PHY-1001 : End phase 2; 44.708430s wall, 71.562500s user + 0.406250s system = 71.968750s CPU (161.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.580ns STNS -4.876ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.158285s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.7%)
+
+PHY-1022 : len = 2.55075e+06, over cnt = 2105(0%), over = 2114, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.422217s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50835e+06, over cnt = 705(0%), over = 705, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.489652s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (141.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50621e+06, over cnt = 169(0%), over = 169, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.180784s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (131.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50678e+06, over cnt = 36(0%), over = 36, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.468787s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (116.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50749e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.278265s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (106.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50762e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.202420s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (92.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.580   |  -4.876   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.295728s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 688 feed throughs used by 487 nets
+PHY-1001 : End commit to database; 2.301737s wall, 2.281250s user + 0.015625s system = 2.296875s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1176, peak = 1169.
+PHY-1001 : End phase 3; 11.023077s wall, 12.484375s user + 0.015625s system = 12.500000s CPU (113.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.580ns STNS -4.876ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.156364s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.9%)
+
+PHY-1022 : len = 2.50762e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.393948s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (103.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.580ns, -4.876ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.580   |  -4.876   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.238473s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 688 feed throughs used by 487 nets
+PHY-1001 : End commit to database; 2.405421s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1179, reserve = 1186, peak = 1179.
+PHY-1001 : End phase 4; 6.066239s wall, 6.031250s user + 0.015625s system = 6.046875s CPU (99.7%)
+
+PHY-1003 : Routed, final wirelength = 2.50762e+06
+PHY-1001 : Current memory(MB): used = 1181, reserve = 1188, peak = 1181.
+PHY-1001 : End export database. 0.061500s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.6%)
+
+PHY-1001 : End detail routing;  71.663850s wall, 99.890625s user + 0.500000s system = 100.390625s CPU (140.1%)
+
+RUN-1003 : finish command "route" in  77.463420s wall, 106.718750s user + 0.609375s system = 107.328125s CPU (138.6%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1112 MB, peak memory is 1181 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10221   out of  19600   52.15%
+#reg                    10147   out of  19600   51.77%
+#le                     12873
+  #lut only              2726   out of  12873   21.18%
+  #reg only              2652   out of  12873   20.60%
+  #lut&reg               7495   out of  12873   58.22%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1761
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1753
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1305
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               960
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    145
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             ua_lvds_rx/reg8_syn_170.f1                         3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg1_syn_157.f0             3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P147       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P109       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12873  |9194    |1027    |10177   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |529    |402     |23      |439     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |105    |90      |4       |90      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |26     |26      |0       |18      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |785    |410     |96      |569     |0       |0       |
+|    u_ADconfig                |AD_config            |194    |108     |25      |145     |0       |0       |
+|    u_gen_sp                  |gen_sp               |280    |189     |71      |113     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |427     |96      |550     |0       |0       |
+|    u_ADconfig                |AD_config            |179    |116     |25      |129     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |163     |71      |119     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3528   |2592    |306     |2746    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |188    |121     |17      |142     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |3307   |2448    |289     |2571    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |1       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2832   |2139    |253     |2164    |22      |0       |
+|        channelPart           |channel_part_8478    |116    |105     |3       |111     |0       |0       |
+|        fifo_adc              |fifo_adc             |67     |58      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |1703   |1361    |197     |1143    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |193    |166     |27      |112     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |977    |666     |170     |700     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |533    |529     |0       |331     |0       |0       |
+|        read_ram_i            |read_ram             |284    |237     |44      |204     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |212    |172     |40      |151     |0       |0       |
+|          read_ram_data       |read_ram_data        |69     |63      |4       |50      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |329    |242     |36      |278     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3179   |2383    |349     |2200    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |6      |0       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |182    |105     |17      |144     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |0       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |2964   |2258    |332     |2024    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |8      |6       |0       |8       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2468   |1896    |290     |1611    |22      |1       |
+|        channelPart           |channel_part_8478    |252    |245     |3       |146     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |41      |0       |1       |
+|        ram_switch            |ram_switch           |1759   |1307    |197     |1182    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |214    |187     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |13      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|          insert              |insert               |1004   |585     |170     |710     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |541    |535     |0       |349     |0       |0       |
+|        read_ram_i            |read_ram_rev         |372    |271     |81      |217     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |302    |222     |73      |166     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |70     |49      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10725  
+    #2         2       3794   
+    #3         3       1350   
+    #4         4        546   
+    #5        5-10     1199   
+    #6       11-50      591   
+    #7       51-100     20    
+    #8        >500       1    
+  Average     2.84            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.129375s wall, 3.578125s user + 0.062500s system = 3.640625s CPU (171.0%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1114 MB, peak memory is 1181 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75770, tnet num: 18144, tinst num: 7004, tnode num: 99549, tedge num: 126773.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.581530s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.8%)
+
+RUN-1004 : used memory is 1112 MB, reserved memory is 1120 MB, peak memory is 1181 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.457559s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (100.8%)
+
+RUN-1004 : used memory is 1115 MB, reserved memory is 1122 MB, peak memory is 1181 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7004
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18322, pip num: 179766
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 688
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3238 valid insts, and 496493 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.100630s wall, 69.984375s user + 0.312500s system = 70.296875s CPU (696.0%)
+
+RUN-1004 : used memory is 1286 MB, reserved memory is 1290 MB, peak memory is 1402 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_144444.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_145615.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_145615.log
new file mode 100644
index 0000000..5407636
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_145615.log
@@ -0,0 +1,1887 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:56:15 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.189787s wall, 2.093750s user + 0.093750s system = 2.187500s CPU (99.9%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 321 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2937 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18472 instances
+RUN-0007 : 7420 luts, 9829 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 21056 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 14136 nets have 2 pins
+RUN-1001 : 5461 nets have [3 - 5] pins
+RUN-1001 : 1049 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 178 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4257     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18470 instances, 7420 luts, 9829 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6555 pins
+PHY-0007 : Cell area utilization is 50%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87845, tnet num: 20878, tinst num: 18470, tnode num: 120293, tedge num: 140684.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.173121s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (99.9%)
+
+RUN-1004 : used memory is 545 MB, reserved memory is 529 MB, peak memory is 545 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.996505s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.2%)
+
+PHY-3001 : Found 3477 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.19517e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18470.
+PHY-3001 : Level 1 #clusters 2130.
+PHY-3001 : End clustering;  0.129190s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (120.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 50%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.25808e+06, overlap = 505.875
+PHY-3002 : Step(2): len = 1.16701e+06, overlap = 523.25
+PHY-3002 : Step(3): len = 826698, overlap = 658.281
+PHY-3002 : Step(4): len = 759006, overlap = 722.594
+PHY-3002 : Step(5): len = 598294, overlap = 851.281
+PHY-3002 : Step(6): len = 536764, overlap = 862.281
+PHY-3002 : Step(7): len = 450689, overlap = 969.406
+PHY-3002 : Step(8): len = 416402, overlap = 1040.41
+PHY-3002 : Step(9): len = 372815, overlap = 1073.5
+PHY-3002 : Step(10): len = 339225, overlap = 1110.72
+PHY-3002 : Step(11): len = 303656, overlap = 1175.06
+PHY-3002 : Step(12): len = 280656, overlap = 1211.56
+PHY-3002 : Step(13): len = 251525, overlap = 1264.91
+PHY-3002 : Step(14): len = 232912, overlap = 1282.53
+PHY-3002 : Step(15): len = 212083, overlap = 1345.5
+PHY-3002 : Step(16): len = 188914, overlap = 1371.09
+PHY-3002 : Step(17): len = 176688, overlap = 1379.19
+PHY-3002 : Step(18): len = 165332, overlap = 1407.22
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.37351e-06
+PHY-3002 : Step(19): len = 166554, overlap = 1381.16
+PHY-3002 : Step(20): len = 197463, overlap = 1259.94
+PHY-3002 : Step(21): len = 201847, overlap = 1280.44
+PHY-3002 : Step(22): len = 202989, overlap = 1299.5
+PHY-3002 : Step(23): len = 201071, overlap = 1251.19
+PHY-3002 : Step(24): len = 199910, overlap = 1235.28
+PHY-3002 : Step(25): len = 197550, overlap = 1201.81
+PHY-3002 : Step(26): len = 196037, overlap = 1184.97
+PHY-3002 : Step(27): len = 193148, overlap = 1176.25
+PHY-3002 : Step(28): len = 191107, overlap = 1150.72
+PHY-3002 : Step(29): len = 189580, overlap = 1144.03
+PHY-3002 : Step(30): len = 189144, overlap = 1166.5
+PHY-3002 : Step(31): len = 188775, overlap = 1174.81
+PHY-3002 : Step(32): len = 189093, overlap = 1187.09
+PHY-3002 : Step(33): len = 188005, overlap = 1174.94
+PHY-3002 : Step(34): len = 187964, overlap = 1167.28
+PHY-3002 : Step(35): len = 188419, overlap = 1144
+PHY-3002 : Step(36): len = 188397, overlap = 1104.03
+PHY-3002 : Step(37): len = 188338, overlap = 1094.81
+PHY-3002 : Step(38): len = 187506, overlap = 1099.75
+PHY-3002 : Step(39): len = 186769, overlap = 1090.97
+PHY-3002 : Step(40): len = 184859, overlap = 1095.22
+PHY-3002 : Step(41): len = 184074, overlap = 1103.44
+PHY-3002 : Step(42): len = 182041, overlap = 1118.47
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.74701e-06
+PHY-3002 : Step(43): len = 189148, overlap = 1111
+PHY-3002 : Step(44): len = 202380, overlap = 1056.34
+PHY-3002 : Step(45): len = 209055, overlap = 981.469
+PHY-3002 : Step(46): len = 214863, overlap = 978
+PHY-3002 : Step(47): len = 217330, overlap = 951.031
+PHY-3002 : Step(48): len = 218594, overlap = 946.625
+PHY-3002 : Step(49): len = 218094, overlap = 940.156
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.49403e-06
+PHY-3002 : Step(50): len = 228825, overlap = 931.625
+PHY-3002 : Step(51): len = 250844, overlap = 884.625
+PHY-3002 : Step(52): len = 261039, overlap = 842.75
+PHY-3002 : Step(53): len = 267482, overlap = 814.656
+PHY-3002 : Step(54): len = 269467, overlap = 792.562
+PHY-3002 : Step(55): len = 269925, overlap = 769.625
+PHY-3002 : Step(56): len = 270962, overlap = 759.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.09881e-05
+PHY-3002 : Step(57): len = 292988, overlap = 720.688
+PHY-3002 : Step(58): len = 319311, overlap = 647.688
+PHY-3002 : Step(59): len = 330198, overlap = 585.75
+PHY-3002 : Step(60): len = 332090, overlap = 560.844
+PHY-3002 : Step(61): len = 327411, overlap = 554.031
+PHY-3002 : Step(62): len = 325043, overlap = 533.875
+PHY-3002 : Step(63): len = 320877, overlap = 515.531
+PHY-3002 : Step(64): len = 320269, overlap = 517.719
+PHY-3002 : Step(65): len = 318805, overlap = 522.594
+PHY-3002 : Step(66): len = 317957, overlap = 521.781
+PHY-3002 : Step(67): len = 317230, overlap = 521.906
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.19761e-05
+PHY-3002 : Step(68): len = 338383, overlap = 493.312
+PHY-3002 : Step(69): len = 353865, overlap = 478.844
+PHY-3002 : Step(70): len = 356731, overlap = 447.375
+PHY-3002 : Step(71): len = 358812, overlap = 421.906
+PHY-3002 : Step(72): len = 358948, overlap = 421.125
+PHY-3002 : Step(73): len = 360870, overlap = 417.25
+PHY-3002 : Step(74): len = 358334, overlap = 402.062
+PHY-3002 : Step(75): len = 359422, overlap = 381.219
+PHY-3002 : Step(76): len = 360533, overlap = 374.219
+PHY-3002 : Step(77): len = 360510, overlap = 365.594
+PHY-3002 : Step(78): len = 359183, overlap = 352.125
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.39522e-05
+PHY-3002 : Step(79): len = 375575, overlap = 324.75
+PHY-3002 : Step(80): len = 389029, overlap = 315.062
+PHY-3002 : Step(81): len = 389364, overlap = 318.188
+PHY-3002 : Step(82): len = 391595, overlap = 316.531
+PHY-3002 : Step(83): len = 394986, overlap = 305.094
+PHY-3002 : Step(84): len = 397974, overlap = 296.469
+PHY-3002 : Step(85): len = 395477, overlap = 295.75
+PHY-3002 : Step(86): len = 396453, overlap = 307.281
+PHY-3002 : Step(87): len = 398101, overlap = 300.5
+PHY-3002 : Step(88): len = 400022, overlap = 270.969
+PHY-3002 : Step(89): len = 398055, overlap = 274.938
+PHY-3002 : Step(90): len = 398440, overlap = 281
+PHY-3002 : Step(91): len = 398794, overlap = 296.562
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.79044e-05
+PHY-3002 : Step(92): len = 417329, overlap = 302.781
+PHY-3002 : Step(93): len = 431341, overlap = 291.125
+PHY-3002 : Step(94): len = 430400, overlap = 268.594
+PHY-3002 : Step(95): len = 430375, overlap = 262.719
+PHY-3002 : Step(96): len = 431517, overlap = 266.938
+PHY-3002 : Step(97): len = 432622, overlap = 267.438
+PHY-3002 : Step(98): len = 430061, overlap = 269.812
+PHY-3002 : Step(99): len = 431864, overlap = 281.094
+PHY-3002 : Step(100): len = 433882, overlap = 272.156
+PHY-3002 : Step(101): len = 435795, overlap = 255.25
+PHY-3002 : Step(102): len = 433683, overlap = 257.156
+PHY-3002 : Step(103): len = 433380, overlap = 259.938
+PHY-3002 : Step(104): len = 434241, overlap = 257.219
+PHY-3002 : Step(105): len = 435415, overlap = 253.094
+PHY-3002 : Step(106): len = 432251, overlap = 249.281
+PHY-3002 : Step(107): len = 432128, overlap = 245.812
+PHY-3002 : Step(108): len = 433159, overlap = 248.719
+PHY-3002 : Step(109): len = 434278, overlap = 243.219
+PHY-3002 : Step(110): len = 431771, overlap = 244.531
+PHY-3002 : Step(111): len = 431463, overlap = 244.188
+PHY-3002 : Step(112): len = 432661, overlap = 245.594
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000175809
+PHY-3002 : Step(113): len = 445813, overlap = 232.594
+PHY-3002 : Step(114): len = 454759, overlap = 227.406
+PHY-3002 : Step(115): len = 454772, overlap = 229.562
+PHY-3002 : Step(116): len = 455001, overlap = 225.031
+PHY-3002 : Step(117): len = 456019, overlap = 224.344
+PHY-3002 : Step(118): len = 457229, overlap = 229.281
+PHY-3002 : Step(119): len = 456170, overlap = 231.406
+PHY-3002 : Step(120): len = 457185, overlap = 225.344
+PHY-3002 : Step(121): len = 459177, overlap = 213.938
+PHY-3002 : Step(122): len = 460204, overlap = 216.531
+PHY-3002 : Step(123): len = 458623, overlap = 223.625
+PHY-3002 : Step(124): len = 458377, overlap = 218.625
+PHY-3002 : Step(125): len = 459246, overlap = 218.656
+PHY-3002 : Step(126): len = 460414, overlap = 226.031
+PHY-3002 : Step(127): len = 459496, overlap = 229.469
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000335646
+PHY-3002 : Step(128): len = 467219, overlap = 222.219
+PHY-3002 : Step(129): len = 474754, overlap = 222.688
+PHY-3002 : Step(130): len = 475456, overlap = 215.062
+PHY-3002 : Step(131): len = 476608, overlap = 218.5
+PHY-3002 : Step(132): len = 479144, overlap = 220.219
+PHY-3002 : Step(133): len = 481228, overlap = 220.938
+PHY-3002 : Step(134): len = 481311, overlap = 214.156
+PHY-3002 : Step(135): len = 481888, overlap = 206.438
+PHY-3002 : Step(136): len = 483617, overlap = 210.844
+PHY-3002 : Step(137): len = 485140, overlap = 208.719
+PHY-3002 : Step(138): len = 485054, overlap = 202.312
+PHY-3002 : Step(139): len = 484714, overlap = 197.844
+PHY-3002 : Step(140): len = 484967, overlap = 194.156
+PHY-3002 : Step(141): len = 485667, overlap = 183.469
+PHY-3002 : Step(142): len = 484684, overlap = 179.156
+PHY-3002 : Step(143): len = 484891, overlap = 176.406
+PHY-3002 : Step(144): len = 486060, overlap = 180.094
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000671291
+PHY-3002 : Step(145): len = 491460, overlap = 178.281
+PHY-3002 : Step(146): len = 498211, overlap = 171.188
+PHY-3002 : Step(147): len = 499447, overlap = 165.531
+PHY-3002 : Step(148): len = 500738, overlap = 157.656
+PHY-3002 : Step(149): len = 502384, overlap = 152.781
+PHY-3002 : Step(150): len = 503448, overlap = 153.5
+PHY-3002 : Step(151): len = 503444, overlap = 146.219
+PHY-3002 : Step(152): len = 503762, overlap = 147.156
+PHY-3002 : Step(153): len = 504196, overlap = 138.125
+PHY-3002 : Step(154): len = 504627, overlap = 135.375
+PHY-3002 : Step(155): len = 504760, overlap = 138.344
+PHY-3002 : Step(156): len = 505924, overlap = 142.594
+PHY-3002 : Step(157): len = 506876, overlap = 139.5
+PHY-3002 : Step(158): len = 507681, overlap = 142.344
+PHY-3002 : Step(159): len = 507956, overlap = 135.938
+PHY-3002 : Step(160): len = 508244, overlap = 134.75
+PHY-3002 : Step(161): len = 508747, overlap = 134.562
+PHY-3002 : Step(162): len = 508909, overlap = 135.094
+PHY-3002 : Step(163): len = 508670, overlap = 133.188
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00122291
+PHY-3002 : Step(164): len = 511411, overlap = 128.406
+PHY-3002 : Step(165): len = 515599, overlap = 127.812
+PHY-3002 : Step(166): len = 516236, overlap = 122.156
+PHY-3002 : Step(167): len = 516798, overlap = 114.5
+PHY-3002 : Step(168): len = 517797, overlap = 114.469
+PHY-3002 : Step(169): len = 518427, overlap = 123.969
+PHY-3002 : Step(170): len = 518405, overlap = 120.969
+PHY-3002 : Step(171): len = 518626, overlap = 121.031
+PHY-3002 : Step(172): len = 519277, overlap = 117.781
+PHY-3002 : Step(173): len = 519537, overlap = 118.594
+PHY-3002 : Step(174): len = 519079, overlap = 123.469
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0020508
+PHY-3002 : Step(175): len = 521420, overlap = 121.844
+PHY-3002 : Step(176): len = 526353, overlap = 109.25
+PHY-3002 : Step(177): len = 526930, overlap = 109.125
+PHY-3002 : Step(178): len = 527395, overlap = 117.25
+PHY-3002 : Step(179): len = 528458, overlap = 118.688
+PHY-3002 : Step(180): len = 529533, overlap = 114.594
+PHY-3002 : Step(181): len = 529492, overlap = 121.094
+PHY-3002 : Step(182): len = 529552, overlap = 120.125
+PHY-3002 : Step(183): len = 529743, overlap = 122.594
+PHY-3002 : Step(184): len = 529931, overlap = 120.406
+PHY-3002 : Step(185): len = 529822, overlap = 122.5
+PHY-3002 : Step(186): len = 529628, overlap = 123.531
+PHY-3002 : Step(187): len = 529596, overlap = 123.875
+PHY-3002 : Step(188): len = 529794, overlap = 121.25
+PHY-3002 : Step(189): len = 529842, overlap = 126.031
+PHY-3002 : Step(190): len = 529892, overlap = 123.969
+PHY-3002 : Step(191): len = 529817, overlap = 121.25
+PHY-3002 : Step(192): len = 529835, overlap = 125.062
+PHY-3002 : Step(193): len = 529882, overlap = 126
+PHY-3002 : Step(194): len = 529901, overlap = 125.438
+PHY-3002 : Step(195): len = 529911, overlap = 126.344
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015891s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (98.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/21056.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 682496, over cnt = 1636(4%), over = 7650, worst = 43
+PHY-1001 : End global iterations;  0.713144s wall, 0.968750s user + 0.031250s system = 1.000000s CPU (140.2%)
+
+PHY-1001 : Congestion index: top1 = 86.72, top5 = 66.22, top10 = 54.33, top15 = 47.67.
+PHY-3001 : End congestion estimation;  0.936130s wall, 1.203125s user + 0.031250s system = 1.234375s CPU (131.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868152s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.31248e-05
+PHY-3002 : Step(196): len = 621567, overlap = 76.375
+PHY-3002 : Step(197): len = 630174, overlap = 78.1562
+PHY-3002 : Step(198): len = 627622, overlap = 75.75
+PHY-3002 : Step(199): len = 626288, overlap = 66.1562
+PHY-3002 : Step(200): len = 627222, overlap = 71.9062
+PHY-3002 : Step(201): len = 636493, overlap = 73.0312
+PHY-3002 : Step(202): len = 648591, overlap = 72
+PHY-3002 : Step(203): len = 654493, overlap = 68.3125
+PHY-3002 : Step(204): len = 658326, overlap = 78.2188
+PHY-3002 : Step(205): len = 664693, overlap = 68.0625
+PHY-3002 : Step(206): len = 666667, overlap = 67.6875
+PHY-3002 : Step(207): len = 669075, overlap = 68.0625
+PHY-3002 : Step(208): len = 673650, overlap = 64.8125
+PHY-3002 : Step(209): len = 676258, overlap = 56.0312
+PHY-3002 : Step(210): len = 679197, overlap = 46.5312
+PHY-3002 : Step(211): len = 678440, overlap = 36.875
+PHY-3002 : Step(212): len = 678508, overlap = 35
+PHY-3002 : Step(213): len = 675310, overlap = 31.75
+PHY-3002 : Step(214): len = 674319, overlap = 30.8125
+PHY-3002 : Step(215): len = 671555, overlap = 31.7812
+PHY-3002 : Step(216): len = 669968, overlap = 33.0312
+PHY-3002 : Step(217): len = 668400, overlap = 32.4375
+PHY-3002 : Step(218): len = 667202, overlap = 33.75
+PHY-3002 : Step(219): len = 665391, overlap = 27.625
+PHY-3002 : Step(220): len = 664717, overlap = 27.6562
+PHY-3002 : Step(221): len = 662405, overlap = 29.25
+PHY-3002 : Step(222): len = 661362, overlap = 29.5312
+PHY-3002 : Step(223): len = 660094, overlap = 33.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00018625
+PHY-3002 : Step(224): len = 661934, overlap = 31.5
+PHY-3002 : Step(225): len = 665643, overlap = 28.4062
+PHY-3002 : Step(226): len = 670778, overlap = 26.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000372499
+PHY-3002 : Step(227): len = 673260, overlap = 28.875
+PHY-3002 : Step(228): len = 685405, overlap = 30
+PHY-3002 : Step(229): len = 699661, overlap = 28.5625
+PHY-3002 : Step(230): len = 700201, overlap = 27.7812
+PHY-3002 : Step(231): len = 700270, overlap = 26.375
+PHY-3002 : Step(232): len = 700334, overlap = 25.6875
+PHY-3002 : Step(233): len = 703123, overlap = 29.7188
+PHY-3002 : Step(234): len = 703621, overlap = 30.5
+PHY-3002 : Step(235): len = 707031, overlap = 30.8125
+PHY-3002 : Step(236): len = 705724, overlap = 32.4062
+PHY-3002 : Step(237): len = 705308, overlap = 31.9375
+PHY-3002 : Step(238): len = 703432, overlap = 31.8438
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000744998
+PHY-3002 : Step(239): len = 707300, overlap = 29.5312
+PHY-3002 : Step(240): len = 712399, overlap = 32.7812
+PHY-3002 : Step(241): len = 716895, overlap = 30.5938
+PHY-3002 : Step(242): len = 726162, overlap = 36.6875
+PHY-3002 : Step(243): len = 728506, overlap = 39.7188
+PHY-3002 : Step(244): len = 730377, overlap = 42.6875
+PHY-3002 : Step(245): len = 732798, overlap = 42.5938
+PHY-3002 : Step(246): len = 730736, overlap = 43.1562
+PHY-3002 : Step(247): len = 730916, overlap = 42.5312
+PHY-3002 : Step(248): len = 731906, overlap = 43.5625
+PHY-3002 : Step(249): len = 734403, overlap = 42.1875
+PHY-3002 : Step(250): len = 735570, overlap = 45.25
+PHY-3002 : Step(251): len = 731210, overlap = 42.9062
+PHY-3002 : Step(252): len = 729836, overlap = 43.75
+PHY-3002 : Step(253): len = 729181, overlap = 42.4375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00126035
+PHY-3002 : Step(254): len = 730628, overlap = 42.8438
+PHY-3002 : Step(255): len = 735052, overlap = 45.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 24/21056.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812472, over cnt = 2689(7%), over = 14514, worst = 73
+PHY-1001 : End global iterations;  1.469034s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (135.1%)
+
+PHY-1001 : Congestion index: top1 = 117.76, top5 = 80.12, top10 = 67.67, top15 = 60.59.
+PHY-3001 : End congestion estimation;  1.744542s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (129.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.927533s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00010882
+PHY-3002 : Step(256): len = 734316, overlap = 265.344
+PHY-3002 : Step(257): len = 740297, overlap = 221.688
+PHY-3002 : Step(258): len = 727943, overlap = 212.938
+PHY-3002 : Step(259): len = 723225, overlap = 193.406
+PHY-3002 : Step(260): len = 718364, overlap = 180.094
+PHY-3002 : Step(261): len = 715575, overlap = 171.25
+PHY-3002 : Step(262): len = 710066, overlap = 159.188
+PHY-3002 : Step(263): len = 705715, overlap = 154.062
+PHY-3002 : Step(264): len = 702380, overlap = 154.031
+PHY-3002 : Step(265): len = 698485, overlap = 158.375
+PHY-3002 : Step(266): len = 694224, overlap = 152.219
+PHY-3002 : Step(267): len = 691072, overlap = 152
+PHY-3002 : Step(268): len = 686738, overlap = 156
+PHY-3002 : Step(269): len = 685591, overlap = 162.344
+PHY-3002 : Step(270): len = 681332, overlap = 164.875
+PHY-3002 : Step(271): len = 679363, overlap = 160.125
+PHY-3002 : Step(272): len = 675694, overlap = 155.781
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000217639
+PHY-3002 : Step(273): len = 678028, overlap = 152.656
+PHY-3002 : Step(274): len = 679709, overlap = 147.094
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00036017
+PHY-3002 : Step(275): len = 683718, overlap = 134.156
+PHY-3002 : Step(276): len = 690837, overlap = 127.312
+PHY-3002 : Step(277): len = 701338, overlap = 116.844
+PHY-3002 : Step(278): len = 696610, overlap = 119.281
+PHY-3002 : Step(279): len = 694542, overlap = 119.188
+PHY-3002 : Step(280): len = 692036, overlap = 120.062
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000663606
+PHY-3002 : Step(281): len = 696653, overlap = 113.75
+PHY-3002 : Step(282): len = 704365, overlap = 102.125
+PHY-3002 : Step(283): len = 710351, overlap = 98.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87845, tnet num: 20878, tinst num: 18470, tnode num: 120293, tedge num: 140684.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.444360s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (99.5%)
+
+RUN-1004 : used memory is 588 MB, reserved memory is 577 MB, peak memory is 730 MB
+OPT-1001 : Total overflow 448.91 peak overflow 3.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 608/21056.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 800408, over cnt = 3278(9%), over = 12246, worst = 49
+PHY-1001 : End global iterations;  1.361646s wall, 1.890625s user + 0.015625s system = 1.906250s CPU (140.0%)
+
+PHY-1001 : Congestion index: top1 = 78.06, top5 = 64.49, top10 = 57.00, top15 = 52.46.
+PHY-1001 : End incremental global routing;  1.702554s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (131.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20878 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.926766s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (101.2%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18334 has valid locations, 328 needs to be replaced
+PHY-3001 : design contains 18747 instances, 7521 luts, 10005 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6680 pins
+PHY-3001 : Found 3514 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 732784
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17490/21333.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 815816, over cnt = 3287(9%), over = 12317, worst = 49
+PHY-1001 : End global iterations;  0.243247s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (134.9%)
+
+PHY-1001 : Congestion index: top1 = 78.99, top5 = 64.71, top10 = 57.29, top15 = 52.78.
+PHY-3001 : End congestion estimation;  0.513630s wall, 0.578125s user + 0.015625s system = 0.593750s CPU (115.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88965, tnet num: 21155, tinst num: 18747, tnode num: 121963, tedge num: 142370.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.482935s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (100.1%)
+
+RUN-1004 : used memory is 635 MB, reserved memory is 641 MB, peak memory is 733 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21155 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.510961s wall, 2.468750s user + 0.046875s system = 2.515625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(284): len = 731573, overlap = 1.375
+PHY-3002 : Step(285): len = 731023, overlap = 1.3125
+PHY-3002 : Step(286): len = 730570, overlap = 1.0625
+PHY-3002 : Step(287): len = 730233, overlap = 1
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17580/21333.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 813328, over cnt = 3295(9%), over = 12352, worst = 49
+PHY-1001 : End global iterations;  0.193517s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (145.3%)
+
+PHY-1001 : Congestion index: top1 = 79.16, top5 = 65.11, top10 = 57.63, top15 = 53.09.
+PHY-3001 : End congestion estimation;  0.447158s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (122.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21155 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.946852s wall, 0.921875s user + 0.031250s system = 0.953125s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000367252
+PHY-3002 : Step(288): len = 730180, overlap = 101.125
+PHY-3002 : Step(289): len = 730223, overlap = 100.656
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000734505
+PHY-3002 : Step(290): len = 730665, overlap = 101.062
+PHY-3002 : Step(291): len = 731211, overlap = 100.969
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00146901
+PHY-3002 : Step(292): len = 731377, overlap = 100.625
+PHY-3002 : Step(293): len = 732163, overlap = 100.969
+PHY-3001 : Final: Len = 732163, Over = 100.969
+PHY-3001 : End incremental placement;  5.181202s wall, 5.531250s user + 0.250000s system = 5.781250s CPU (111.6%)
+
+OPT-1001 : Total overflow 455.97 peak overflow 3.97
+OPT-1001 : End high-fanout net optimization;  8.369306s wall, 9.234375s user + 0.281250s system = 9.515625s CPU (113.7%)
+
+OPT-1001 : Current memory(MB): used = 735, reserve = 730, peak = 752.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17507/21333.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 817544, over cnt = 3246(9%), over = 11365, worst = 49
+PHY-1002 : len = 879848, over cnt = 2394(6%), over = 5771, worst = 22
+PHY-1002 : len = 916720, over cnt = 1209(3%), over = 2878, worst = 22
+PHY-1002 : len = 946544, over cnt = 365(1%), over = 848, worst = 13
+PHY-1002 : len = 960936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.096690s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (132.6%)
+
+PHY-1001 : Congestion index: top1 = 64.12, top5 = 56.66, top10 = 52.38, top15 = 49.53.
+OPT-1001 : End congestion update;  2.369357s wall, 3.062500s user + 0.000000s system = 3.062500s CPU (129.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21155 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.844436s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 49 cells processed and 12750 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 58 cells processed and 3850 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 26 cells processed and 1468 slack improved
+OPT-1001 : End global optimization;  3.259088s wall, 3.937500s user + 0.000000s system = 3.937500s CPU (120.8%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 710, peak = 752.
+OPT-1001 : End physical optimization;  13.704807s wall, 15.328125s user + 0.312500s system = 15.640625s CPU (114.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7521 LUT to BLE ...
+SYN-4008 : Packed 7521 LUT and 3155 SEQ to BLE.
+SYN-4003 : Packing 6850 remaining SEQ's ...
+SYN-4005 : Packed 4135 SEQ with LUT/SLICE
+SYN-4006 : 541 single LUT's are left
+SYN-4006 : 2715 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10236/13967 primitive instances ...
+PHY-3001 : End packing;  1.745768s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (100.2%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6989 instances
+RUN-1001 : 3420 mslices, 3421 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18307 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10786 nets have 2 pins
+RUN-1001 : 5691 nets have [3 - 5] pins
+RUN-1001 : 1140 nets have [6 - 10] pins
+RUN-1001 : 320 nets have [11 - 20] pins
+RUN-1001 : 338 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6987 instances, 6841 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3825 pins
+PHY-3001 : Found 1558 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 738484, Over = 300.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7671/18307.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896712, over cnt = 2093(5%), over = 3370, worst = 8
+PHY-1002 : len = 903080, over cnt = 1494(4%), over = 2172, worst = 7
+PHY-1002 : len = 915240, over cnt = 766(2%), over = 1058, worst = 6
+PHY-1002 : len = 924408, over cnt = 358(1%), over = 501, worst = 5
+PHY-1002 : len = 932848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.655635s wall, 2.218750s user + 0.000000s system = 2.218750s CPU (134.0%)
+
+PHY-1001 : Congestion index: top1 = 61.75, top5 = 55.09, top10 = 50.87, top15 = 47.80.
+PHY-3001 : End congestion estimation;  2.061589s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (127.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75644, tnet num: 18129, tinst num: 6987, tnode num: 99391, tedge num: 126619.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.652366s wall, 1.625000s user + 0.031250s system = 1.656250s CPU (100.2%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 619 MB, peak memory is 752 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18129 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.532450s wall, 2.453125s user + 0.078125s system = 2.531250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.6792e-05
+PHY-3002 : Step(294): len = 724507, overlap = 300.5
+PHY-3002 : Step(295): len = 716339, overlap = 295.75
+PHY-3002 : Step(296): len = 710976, overlap = 284.75
+PHY-3002 : Step(297): len = 706676, overlap = 288.5
+PHY-3002 : Step(298): len = 703298, overlap = 296.25
+PHY-3002 : Step(299): len = 700016, overlap = 297.75
+PHY-3002 : Step(300): len = 696677, overlap = 303.25
+PHY-3002 : Step(301): len = 694025, overlap = 309
+PHY-3002 : Step(302): len = 691225, overlap = 312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.3584e-05
+PHY-3002 : Step(303): len = 693987, overlap = 304.25
+PHY-3002 : Step(304): len = 698785, overlap = 294
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000187168
+PHY-3002 : Step(305): len = 704541, overlap = 287.5
+PHY-3002 : Step(306): len = 717226, overlap = 266.25
+PHY-3002 : Step(307): len = 718529, overlap = 256.75
+PHY-3002 : Step(308): len = 717837, overlap = 254.5
+PHY-3002 : Step(309): len = 717701, overlap = 251.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.334208s wall, 0.390625s user + 0.390625s system = 0.781250s CPU (233.8%)
+
+PHY-3001 : Trial Legalized: Len = 934066
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 600/18307.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0534e+06, over cnt = 2994(8%), over = 5135, worst = 8
+PHY-1002 : len = 1.07282e+06, over cnt = 1841(5%), over = 2778, worst = 6
+PHY-1002 : len = 1.08977e+06, over cnt = 940(2%), over = 1481, worst = 6
+PHY-1002 : len = 1.11637e+06, over cnt = 109(0%), over = 157, worst = 6
+PHY-1002 : len = 1.11974e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.553467s wall, 3.750000s user + 0.000000s system = 3.750000s CPU (146.9%)
+
+PHY-1001 : Congestion index: top1 = 65.99, top5 = 59.29, top10 = 55.55, top15 = 52.99.
+PHY-3001 : End congestion estimation;  2.997287s wall, 4.203125s user + 0.000000s system = 4.203125s CPU (140.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18129 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.878018s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165635
+PHY-3002 : Step(310): len = 886587, overlap = 76
+PHY-3002 : Step(311): len = 861728, overlap = 102
+PHY-3002 : Step(312): len = 843325, overlap = 130
+PHY-3002 : Step(313): len = 830750, overlap = 148.75
+PHY-3002 : Step(314): len = 821880, overlap = 156.75
+PHY-3002 : Step(315): len = 813075, overlap = 169.25
+PHY-3002 : Step(316): len = 805515, overlap = 180.25
+PHY-3002 : Step(317): len = 800173, overlap = 185.5
+PHY-3002 : Step(318): len = 794708, overlap = 194
+PHY-3002 : Step(319): len = 790731, overlap = 197
+PHY-3002 : Step(320): len = 787445, overlap = 195.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00033127
+PHY-3002 : Step(321): len = 792475, overlap = 191
+PHY-3002 : Step(322): len = 796117, overlap = 186.5
+PHY-3002 : Step(323): len = 797260, overlap = 186.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000583746
+PHY-3002 : Step(324): len = 804948, overlap = 176.75
+PHY-3002 : Step(325): len = 806478, overlap = 177.5
+PHY-3002 : Step(326): len = 809751, overlap = 172
+PHY-3002 : Step(327): len = 810577, overlap = 172
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.082301s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (94.9%)
+
+PHY-3001 : Legalized: Len = 889239, Over = 0
+PHY-3001 : Spreading special nets. 490 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.115596s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (94.6%)
+
+PHY-3001 : 723 instances has been re-located, deltaX = 304, deltaY = 446, maxDist = 4.
+PHY-3001 : Final: Len = 900651, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75644, tnet num: 18129, tinst num: 6990, tnode num: 99391, tedge num: 126619.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.890233s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.0%)
+
+RUN-1004 : used memory is 646 MB, reserved memory is 657 MB, peak memory is 752 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3257/18307.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03311e+06, over cnt = 2718(7%), over = 4578, worst = 8
+PHY-1002 : len = 1.04705e+06, over cnt = 1733(4%), over = 2593, worst = 7
+PHY-1002 : len = 1.07023e+06, over cnt = 537(1%), over = 726, worst = 7
+PHY-1002 : len = 1.08027e+06, over cnt = 79(0%), over = 100, worst = 4
+PHY-1002 : len = 1.08208e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.152625s wall, 3.109375s user + 0.031250s system = 3.140625s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 63.17, top5 = 56.96, top10 = 53.51, top15 = 51.16.
+PHY-1001 : End incremental global routing;  2.508026s wall, 3.468750s user + 0.031250s system = 3.500000s CPU (139.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18129 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.870218s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (100.5%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6898 has valid locations, 18 needs to be replaced
+PHY-3001 : design contains 7004 instances, 6855 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3899 pins
+PHY-3001 : Found 1561 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 902968
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16802/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08421e+06, over cnt = 58(0%), over = 64, worst = 3
+PHY-1002 : len = 1.08433e+06, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 1.08451e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.08461e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.603400s wall, 0.640625s user + 0.031250s system = 0.671875s CPU (111.3%)
+
+PHY-1001 : Congestion index: top1 = 63.17, top5 = 56.97, top10 = 53.53, top15 = 51.17.
+PHY-3001 : End congestion estimation;  0.927360s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (106.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75770, tnet num: 18144, tinst num: 7004, tnode num: 99549, tedge num: 126773.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.874468s wall, 1.843750s user + 0.015625s system = 1.859375s CPU (99.2%)
+
+RUN-1004 : used memory is 678 MB, reserved memory is 681 MB, peak memory is 752 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.810929s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(328): len = 902037, overlap = 0
+PHY-3002 : Step(329): len = 901699, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16792/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08291e+06, over cnt = 38(0%), over = 42, worst = 4
+PHY-1002 : len = 1.08298e+06, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 1.08308e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.08311e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.577112s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 63.17, top5 = 56.97, top10 = 53.52, top15 = 51.17.
+PHY-3001 : End congestion estimation;  0.898624s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (104.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.876454s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000138989
+PHY-3002 : Step(330): len = 901564, overlap = 1
+PHY-3002 : Step(331): len = 901564, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005777s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 901645, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059748s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 901577, Over = 0
+PHY-3001 : End incremental placement;  5.997132s wall, 6.078125s user + 0.156250s system = 6.234375s CPU (104.0%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.868304s wall, 10.859375s user + 0.234375s system = 11.093750s CPU (112.4%)
+
+OPT-1001 : Current memory(MB): used = 759, reserve = 759, peak = 764.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16785/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08281e+06, over cnt = 24(0%), over = 29, worst = 3
+PHY-1002 : len = 1.08286e+06, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 1.08296e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.08302e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.600546s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (101.5%)
+
+PHY-1001 : Congestion index: top1 = 63.21, top5 = 56.99, top10 = 53.52, top15 = 51.16.
+OPT-1001 : End congestion update;  0.913876s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (102.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.745837s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.5%)
+
+OPT-0007 : Start: WNS -1633 TNS -2947 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6916 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7004 instances, 6855 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3899 pins
+PHY-3001 : Found 1561 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 903379, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059968s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.2%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 11, deltaY = 15, maxDist = 3.
+PHY-3001 : Final: Len = 903517, Over = 0
+PHY-3001 : End incremental legalization;  0.380336s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.6%)
+
+OPT-0007 : Iter 1: improved WNS -1633 TNS -2818 NUM_FEPS 2 with 27 cells processed and 7400 slack improved
+OPT-0007 : Iter 2: improved WNS -1633 TNS -2818 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.176572s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 757, reserve = 758, peak = 764.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.735404s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16673/18322.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.08462e+06, over cnt = 112(0%), over = 134, worst = 4
+PHY-1002 : len = 1.08483e+06, over cnt = 73(0%), over = 74, worst = 2
+PHY-1002 : len = 1.08533e+06, over cnt = 31(0%), over = 31, worst = 1
+PHY-1002 : len = 1.08586e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.08591e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.837400s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (104.5%)
+
+PHY-1001 : Congestion index: top1 = 63.38, top5 = 57.08, top10 = 53.53, top15 = 51.14.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.755399s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1633 TNS -2818 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 62.965517
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1633ps with logic level 2 
+RUN-1001 :       #2 path slack -1547ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 18322 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 18322 nets
+OPT-1001 : End physical optimization;  16.945711s wall, 18.000000s user + 0.234375s system = 18.234375s CPU (107.6%)
+
+RUN-1003 : finish command "place" in  61.852890s wall, 97.000000s user + 6.218750s system = 103.218750s CPU (166.9%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 621 MB, peak memory is 764 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.710091s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (174.5%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 622 MB, peak memory is 764 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7006 instances
+RUN-1001 : 3426 mslices, 3429 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18322 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10787 nets have 2 pins
+RUN-1001 : 5693 nets have [3 - 5] pins
+RUN-1001 : 1140 nets have [6 - 10] pins
+RUN-1001 : 324 nets have [11 - 20] pins
+RUN-1001 : 349 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75770, tnet num: 18144, tinst num: 7004, tnode num: 99549, tedge num: 126773.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.645693s wall, 1.625000s user + 0.015625s system = 1.640625s CPU (99.7%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 646 MB, peak memory is 764 MB
+PHY-1001 : 3426 mslices, 3429 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[105] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.01318e+06, over cnt = 2889(8%), over = 4955, worst = 8
+PHY-1002 : len = 1.03244e+06, over cnt = 1886(5%), over = 2815, worst = 8
+PHY-1002 : len = 1.05026e+06, over cnt = 1052(2%), over = 1487, worst = 7
+PHY-1002 : len = 1.07289e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.865415s wall, 3.968750s user + 0.015625s system = 3.984375s CPU (139.1%)
+
+PHY-1001 : Congestion index: top1 = 63.36, top5 = 57.02, top10 = 53.47, top15 = 50.95.
+PHY-1001 : End global routing;  3.206156s wall, 4.296875s user + 0.015625s system = 4.312500s CPU (134.5%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 729, reserve = 734, peak = 764.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1006, reserve = 1012, peak = 1006.
+PHY-1001 : End build detailed router design. 4.016832s wall, 3.937500s user + 0.078125s system = 4.015625s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 263904, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.067882s wall, 5.046875s user + 0.000000s system = 5.046875s CPU (99.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 263960, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.428296s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.5%)
+
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1047, peak = 1040.
+PHY-1001 : End phase 1; 5.508856s wall, 5.484375s user + 0.000000s system = 5.484375s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.55074e+06, over cnt = 2102(0%), over = 2111, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1057, reserve = 1061, peak = 1057.
+PHY-1001 : End initial routed; 45.817020s wall, 73.609375s user + 0.437500s system = 74.046875s CPU (161.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.672   |  -4.968   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.226071s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1063, reserve = 1069, peak = 1063.
+PHY-1001 : End phase 2; 49.043154s wall, 76.828125s user + 0.437500s system = 77.265625s CPU (157.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.580ns STNS -4.876ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.157947s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.9%)
+
+PHY-1022 : len = 2.55075e+06, over cnt = 2105(0%), over = 2114, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.419092s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (96.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50835e+06, over cnt = 705(0%), over = 705, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.668219s wall, 3.765625s user + 0.000000s system = 3.765625s CPU (141.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50621e+06, over cnt = 169(0%), over = 169, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.180444s wall, 1.484375s user + 0.015625s system = 1.500000s CPU (127.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50678e+06, over cnt = 36(0%), over = 36, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.474707s wall, 0.531250s user + 0.015625s system = 0.546875s CPU (115.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50749e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.270417s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (104.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50762e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.200865s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (101.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.580   |  -4.876   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.529527s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 688 feed throughs used by 487 nets
+PHY-1001 : End commit to database; 2.530468s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1171, reserve = 1181, peak = 1171.
+PHY-1001 : End phase 3; 11.645172s wall, 13.109375s user + 0.031250s system = 13.140625s CPU (112.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.580ns STNS -4.876ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.165406s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.9%)
+
+PHY-1022 : len = 2.50762e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.407586s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.580ns, -4.876ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17244(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.580   |  -4.876   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.690609s wall, 3.687500s user + 0.000000s system = 3.687500s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 688 feed throughs used by 487 nets
+PHY-1001 : End commit to database; 2.437294s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1181, reserve = 1191, peak = 1181.
+PHY-1001 : End phase 4; 6.564971s wall, 6.562500s user + 0.000000s system = 6.562500s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.50762e+06
+PHY-1001 : Current memory(MB): used = 1183, reserve = 1193, peak = 1183.
+PHY-1001 : End export database. 0.063840s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.9%)
+
+PHY-1001 : End detail routing;  77.307687s wall, 106.468750s user + 0.546875s system = 107.015625s CPU (138.4%)
+
+RUN-1003 : finish command "route" in  83.270567s wall, 113.500000s user + 0.578125s system = 114.078125s CPU (137.0%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1114 MB, peak memory is 1183 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10221   out of  19600   52.15%
+#reg                    10147   out of  19600   51.77%
+#le                     12873
+  #lut only              2726   out of  12873   21.18%
+  #reg only              2652   out of  12873   20.60%
+  #lut&reg               7495   out of  12873   58.22%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1761
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1753
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1305
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               960
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    145
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             ua_lvds_rx/reg8_syn_170.f1                         3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg1_syn_157.f0             3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P147       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P109       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12873  |9194    |1027    |10177   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |529    |402     |23      |439     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |105    |90      |4       |90      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |26     |26      |0       |18      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |785    |410     |96      |569     |0       |0       |
+|    u_ADconfig                |AD_config            |194    |108     |25      |145     |0       |0       |
+|    u_gen_sp                  |gen_sp               |280    |189     |71      |113     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |427     |96      |550     |0       |0       |
+|    u_ADconfig                |AD_config            |179    |116     |25      |129     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |163     |71      |119     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3528   |2592    |306     |2746    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |188    |121     |17      |142     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |3307   |2448    |289     |2571    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |1       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2832   |2139    |253     |2164    |22      |0       |
+|        channelPart           |channel_part_8478    |116    |105     |3       |111     |0       |0       |
+|        fifo_adc              |fifo_adc             |67     |58      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |1703   |1361    |197     |1143    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |193    |166     |27      |112     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |977    |666     |170     |700     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |533    |529     |0       |331     |0       |0       |
+|        read_ram_i            |read_ram             |284    |237     |44      |204     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |212    |172     |40      |151     |0       |0       |
+|          read_ram_data       |read_ram_data        |69     |63      |4       |50      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |329    |242     |36      |278     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3179   |2383    |349     |2200    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |6      |0       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |182    |105     |17      |144     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |0       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |2964   |2258    |332     |2024    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |8      |6       |0       |8       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2468   |1896    |290     |1611    |22      |1       |
+|        channelPart           |channel_part_8478    |252    |245     |3       |146     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |41      |0       |1       |
+|        ram_switch            |ram_switch           |1759   |1307    |197     |1182    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |214    |187     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |13      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|          insert              |insert               |1004   |585     |170     |710     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |541    |535     |0       |349     |0       |0       |
+|        read_ram_i            |read_ram_rev         |372    |271     |81      |217     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |302    |222     |73      |166     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |70     |49      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10725  
+    #2         2       3794   
+    #3         3       1350   
+    #4         4        546   
+    #5        5-10     1199   
+    #6       11-50      591   
+    #7       51-100     20    
+    #8        >500       1    
+  Average     2.84            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.086435s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (173.7%)
+
+RUN-1004 : used memory is 1108 MB, reserved memory is 1117 MB, peak memory is 1183 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75770, tnet num: 18144, tinst num: 7004, tnode num: 99549, tedge num: 126773.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.609875s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.0%)
+
+RUN-1004 : used memory is 1114 MB, reserved memory is 1123 MB, peak memory is 1183 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18144 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.549882s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (99.8%)
+
+RUN-1004 : used memory is 1117 MB, reserved memory is 1125 MB, peak memory is 1183 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7004
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18322, pip num: 179766
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 688
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3238 valid insts, and 496493 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.711016s wall, 68.671875s user + 0.078125s system = 68.750000s CPU (641.9%)
+
+RUN-1004 : used memory is 1288 MB, reserved memory is 1291 MB, peak memory is 1403 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_145615.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_151722.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_151722.log
new file mode 100644
index 0000000..084807e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_151722.log
@@ -0,0 +1,2044 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:17:22 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.101460s wall, 2.015625s user + 0.078125s system = 2.093750s CPU (99.6%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 316 MB, peak memory is 343 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2343 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17794 instances
+RUN-0007 : 7336 luts, 9235 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20378 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13369 nets have 2 pins
+RUN-1001 : 5720 nets have [3 - 5] pins
+RUN-1001 : 876 nets have [6 - 10] pins
+RUN-1001 : 157 nets have [11 - 20] pins
+RUN-1001 : 181 nets have [21 - 99] pins
+RUN-1001 : 55 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3663     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17792 instances, 7336 luts, 9235 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85071, tnet num: 20200, tinst num: 17792, tnode num: 115737, tedge num: 136492.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.114493s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (100.9%)
+
+RUN-1004 : used memory is 533 MB, reserved memory is 517 MB, peak memory is 533 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.880248s wall, 1.843750s user + 0.046875s system = 1.890625s CPU (100.6%)
+
+PHY-3001 : Found 3485 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.0287e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17792.
+PHY-3001 : Level 1 #clusters 2023.
+PHY-3001 : End clustering;  0.128212s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.2685e+06, overlap = 477.906
+PHY-3002 : Step(2): len = 1.18979e+06, overlap = 502.125
+PHY-3002 : Step(3): len = 843428, overlap = 550.844
+PHY-3002 : Step(4): len = 788091, overlap = 622.281
+PHY-3002 : Step(5): len = 608692, overlap = 740.156
+PHY-3002 : Step(6): len = 539579, overlap = 812.281
+PHY-3002 : Step(7): len = 455072, overlap = 878.719
+PHY-3002 : Step(8): len = 429654, overlap = 923.094
+PHY-3002 : Step(9): len = 385828, overlap = 978.625
+PHY-3002 : Step(10): len = 352046, overlap = 1015.16
+PHY-3002 : Step(11): len = 315550, overlap = 1093.97
+PHY-3002 : Step(12): len = 290016, overlap = 1133.16
+PHY-3002 : Step(13): len = 259298, overlap = 1170.62
+PHY-3002 : Step(14): len = 244442, overlap = 1203.81
+PHY-3002 : Step(15): len = 222842, overlap = 1270.75
+PHY-3002 : Step(16): len = 208204, overlap = 1296.5
+PHY-3002 : Step(17): len = 185331, overlap = 1323.84
+PHY-3002 : Step(18): len = 168986, overlap = 1352.69
+PHY-3002 : Step(19): len = 157883, overlap = 1391.22
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.08329e-06
+PHY-3002 : Step(20): len = 158692, overlap = 1380.97
+PHY-3002 : Step(21): len = 186505, overlap = 1280.69
+PHY-3002 : Step(22): len = 187565, overlap = 1231.22
+PHY-3002 : Step(23): len = 191123, overlap = 1234.06
+PHY-3002 : Step(24): len = 190375, overlap = 1225.84
+PHY-3002 : Step(25): len = 189634, overlap = 1222.59
+PHY-3002 : Step(26): len = 187980, overlap = 1205.38
+PHY-3002 : Step(27): len = 186308, overlap = 1200.5
+PHY-3002 : Step(28): len = 185356, overlap = 1211.31
+PHY-3002 : Step(29): len = 183587, overlap = 1214.06
+PHY-3002 : Step(30): len = 183203, overlap = 1200.5
+PHY-3002 : Step(31): len = 182123, overlap = 1178.19
+PHY-3002 : Step(32): len = 180066, overlap = 1176.59
+PHY-3002 : Step(33): len = 179289, overlap = 1172.78
+PHY-3002 : Step(34): len = 177906, overlap = 1172.41
+PHY-3002 : Step(35): len = 178992, overlap = 1174.5
+PHY-3002 : Step(36): len = 178333, overlap = 1171.97
+PHY-3002 : Step(37): len = 177872, overlap = 1184.19
+PHY-3002 : Step(38): len = 176317, overlap = 1195.84
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.16659e-06
+PHY-3002 : Step(39): len = 180967, overlap = 1181.19
+PHY-3002 : Step(40): len = 191196, overlap = 1132.47
+PHY-3002 : Step(41): len = 195956, overlap = 1111.12
+PHY-3002 : Step(42): len = 200821, overlap = 1078.41
+PHY-3002 : Step(43): len = 203098, overlap = 1069.47
+PHY-3002 : Step(44): len = 204435, overlap = 1055.22
+PHY-3002 : Step(45): len = 202155, overlap = 1042.12
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.33318e-06
+PHY-3002 : Step(46): len = 209855, overlap = 1029.19
+PHY-3002 : Step(47): len = 228477, overlap = 978.656
+PHY-3002 : Step(48): len = 239667, overlap = 877.531
+PHY-3002 : Step(49): len = 246457, overlap = 842.25
+PHY-3002 : Step(50): len = 249422, overlap = 834.125
+PHY-3002 : Step(51): len = 252085, overlap = 840.062
+PHY-3002 : Step(52): len = 251800, overlap = 839.781
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.66635e-06
+PHY-3002 : Step(53): len = 271748, overlap = 775.281
+PHY-3002 : Step(54): len = 296590, overlap = 683.938
+PHY-3002 : Step(55): len = 302041, overlap = 596.312
+PHY-3002 : Step(56): len = 305325, overlap = 557.531
+PHY-3002 : Step(57): len = 305465, overlap = 553.781
+PHY-3002 : Step(58): len = 307098, overlap = 544.531
+PHY-3002 : Step(59): len = 305987, overlap = 554.594
+PHY-3002 : Step(60): len = 306363, overlap = 557.188
+PHY-3002 : Step(61): len = 305605, overlap = 558.719
+PHY-3002 : Step(62): len = 303495, overlap = 561.625
+PHY-3002 : Step(63): len = 301920, overlap = 564.906
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.73327e-05
+PHY-3002 : Step(64): len = 324895, overlap = 506.469
+PHY-3002 : Step(65): len = 344198, overlap = 439.812
+PHY-3002 : Step(66): len = 347598, overlap = 450.312
+PHY-3002 : Step(67): len = 349427, overlap = 444.594
+PHY-3002 : Step(68): len = 348182, overlap = 429.406
+PHY-3002 : Step(69): len = 348892, overlap = 413.875
+PHY-3002 : Step(70): len = 347289, overlap = 419.75
+PHY-3002 : Step(71): len = 346435, overlap = 423.469
+PHY-3002 : Step(72): len = 344932, overlap = 398.188
+PHY-3002 : Step(73): len = 345194, overlap = 399.594
+PHY-3002 : Step(74): len = 344404, overlap = 413.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.46654e-05
+PHY-3002 : Step(75): len = 366650, overlap = 380.031
+PHY-3002 : Step(76): len = 378982, overlap = 362.656
+PHY-3002 : Step(77): len = 375751, overlap = 367.531
+PHY-3002 : Step(78): len = 377982, overlap = 376.812
+PHY-3002 : Step(79): len = 382723, overlap = 379.812
+PHY-3002 : Step(80): len = 386177, overlap = 365.469
+PHY-3002 : Step(81): len = 383295, overlap = 346.844
+PHY-3002 : Step(82): len = 383872, overlap = 347.656
+PHY-3002 : Step(83): len = 387019, overlap = 325.5
+PHY-3002 : Step(84): len = 388989, overlap = 314.719
+PHY-3002 : Step(85): len = 385519, overlap = 299.562
+PHY-3002 : Step(86): len = 386230, overlap = 295.844
+PHY-3002 : Step(87): len = 386592, overlap = 299.656
+PHY-3002 : Step(88): len = 388677, overlap = 301.188
+PHY-3002 : Step(89): len = 385841, overlap = 284.031
+PHY-3002 : Step(90): len = 385881, overlap = 284.469
+PHY-3002 : Step(91): len = 386530, overlap = 282.812
+PHY-3002 : Step(92): len = 387684, overlap = 290.844
+PHY-3002 : Step(93): len = 384557, overlap = 290.375
+PHY-3002 : Step(94): len = 384224, overlap = 294.625
+PHY-3002 : Step(95): len = 384305, overlap = 306.25
+PHY-3002 : Step(96): len = 385181, overlap = 305.562
+PHY-3002 : Step(97): len = 381647, overlap = 311.938
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.91756e-05
+PHY-3002 : Step(98): len = 400630, overlap = 297.812
+PHY-3002 : Step(99): len = 410038, overlap = 288.469
+PHY-3002 : Step(100): len = 408306, overlap = 290
+PHY-3002 : Step(101): len = 409768, overlap = 288.688
+PHY-3002 : Step(102): len = 414623, overlap = 269.344
+PHY-3002 : Step(103): len = 418747, overlap = 265.031
+PHY-3002 : Step(104): len = 416278, overlap = 256.688
+PHY-3002 : Step(105): len = 417033, overlap = 271.938
+PHY-3002 : Step(106): len = 418939, overlap = 267.688
+PHY-3002 : Step(107): len = 421343, overlap = 259.938
+PHY-3002 : Step(108): len = 417205, overlap = 271.406
+PHY-3002 : Step(109): len = 418010, overlap = 259.594
+PHY-3002 : Step(110): len = 419507, overlap = 272.531
+PHY-3002 : Step(111): len = 420763, overlap = 267.5
+PHY-3002 : Step(112): len = 418978, overlap = 265
+PHY-3002 : Step(113): len = 419589, overlap = 246.656
+PHY-3002 : Step(114): len = 421249, overlap = 249.656
+PHY-3002 : Step(115): len = 423245, overlap = 252.938
+PHY-3002 : Step(116): len = 420750, overlap = 251.5
+PHY-3002 : Step(117): len = 421154, overlap = 250.812
+PHY-3002 : Step(118): len = 422355, overlap = 252
+PHY-3002 : Step(119): len = 423197, overlap = 251.375
+PHY-3002 : Step(120): len = 420855, overlap = 233.781
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000132873
+PHY-3002 : Step(121): len = 436066, overlap = 246.25
+PHY-3002 : Step(122): len = 445253, overlap = 248.344
+PHY-3002 : Step(123): len = 444358, overlap = 238.656
+PHY-3002 : Step(124): len = 445012, overlap = 230.938
+PHY-3002 : Step(125): len = 448101, overlap = 233.219
+PHY-3002 : Step(126): len = 451605, overlap = 220.125
+PHY-3002 : Step(127): len = 451091, overlap = 212.625
+PHY-3002 : Step(128): len = 452182, overlap = 215.312
+PHY-3002 : Step(129): len = 454230, overlap = 212.25
+PHY-3002 : Step(130): len = 455970, overlap = 216.438
+PHY-3002 : Step(131): len = 454792, overlap = 216.656
+PHY-3002 : Step(132): len = 454944, overlap = 217.094
+PHY-3002 : Step(133): len = 456642, overlap = 221.188
+PHY-3002 : Step(134): len = 458497, overlap = 223.312
+PHY-3002 : Step(135): len = 457446, overlap = 223.562
+PHY-3002 : Step(136): len = 457559, overlap = 220.531
+PHY-3002 : Step(137): len = 458826, overlap = 217.188
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000265747
+PHY-3002 : Step(138): len = 470656, overlap = 209.062
+PHY-3002 : Step(139): len = 483184, overlap = 213.688
+PHY-3002 : Step(140): len = 484748, overlap = 204.156
+PHY-3002 : Step(141): len = 486247, overlap = 197.594
+PHY-3002 : Step(142): len = 488601, overlap = 189.844
+PHY-3002 : Step(143): len = 489945, overlap = 188.031
+PHY-3002 : Step(144): len = 488681, overlap = 197
+PHY-3002 : Step(145): len = 488370, overlap = 205.688
+PHY-3002 : Step(146): len = 489832, overlap = 198.062
+PHY-3002 : Step(147): len = 491684, overlap = 197.656
+PHY-3002 : Step(148): len = 490925, overlap = 195.969
+PHY-3002 : Step(149): len = 491081, overlap = 194
+PHY-3002 : Step(150): len = 492047, overlap = 205.688
+PHY-3002 : Step(151): len = 492529, overlap = 207.844
+PHY-3002 : Step(152): len = 491621, overlap = 215.688
+PHY-3002 : Step(153): len = 491436, overlap = 213.594
+PHY-3002 : Step(154): len = 492030, overlap = 211.531
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000526249
+PHY-3002 : Step(155): len = 500444, overlap = 200.656
+PHY-3002 : Step(156): len = 508155, overlap = 199.125
+PHY-3002 : Step(157): len = 509878, overlap = 195.594
+PHY-3002 : Step(158): len = 511108, overlap = 193.062
+PHY-3002 : Step(159): len = 513051, overlap = 185.062
+PHY-3002 : Step(160): len = 514647, overlap = 181.344
+PHY-3002 : Step(161): len = 514606, overlap = 180.812
+PHY-3002 : Step(162): len = 515390, overlap = 174.469
+PHY-3002 : Step(163): len = 516820, overlap = 177.156
+PHY-3002 : Step(164): len = 517791, overlap = 175.375
+PHY-3002 : Step(165): len = 516730, overlap = 169.75
+PHY-3002 : Step(166): len = 516125, overlap = 167.938
+PHY-3002 : Step(167): len = 516730, overlap = 164.469
+PHY-3002 : Step(168): len = 517599, overlap = 168.594
+PHY-3002 : Step(169): len = 516875, overlap = 160.406
+PHY-3002 : Step(170): len = 516606, overlap = 155.281
+PHY-3002 : Step(171): len = 516660, overlap = 156.719
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00102656
+PHY-3002 : Step(172): len = 521485, overlap = 158.125
+PHY-3002 : Step(173): len = 527467, overlap = 155.75
+PHY-3002 : Step(174): len = 528424, overlap = 156.875
+PHY-3002 : Step(175): len = 529371, overlap = 152.281
+PHY-3002 : Step(176): len = 531293, overlap = 151.656
+PHY-3002 : Step(177): len = 532645, overlap = 152.25
+PHY-3002 : Step(178): len = 532452, overlap = 156.875
+PHY-3002 : Step(179): len = 532734, overlap = 155.531
+PHY-3002 : Step(180): len = 534288, overlap = 154.281
+PHY-3002 : Step(181): len = 535470, overlap = 153.906
+PHY-3002 : Step(182): len = 534995, overlap = 157.531
+PHY-3002 : Step(183): len = 534934, overlap = 159.594
+PHY-3002 : Step(184): len = 535826, overlap = 157.625
+PHY-3002 : Step(185): len = 536309, overlap = 158.188
+PHY-3002 : Step(186): len = 536132, overlap = 157.812
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00177344
+PHY-3002 : Step(187): len = 538541, overlap = 158.688
+PHY-3002 : Step(188): len = 541483, overlap = 160.344
+PHY-3002 : Step(189): len = 542315, overlap = 160.688
+PHY-3002 : Step(190): len = 542844, overlap = 160.438
+PHY-3002 : Step(191): len = 543854, overlap = 161.188
+PHY-3002 : Step(192): len = 544240, overlap = 160.531
+PHY-3002 : Step(193): len = 544546, overlap = 156.938
+PHY-3002 : Step(194): len = 545076, overlap = 154.375
+PHY-3002 : Step(195): len = 546175, overlap = 154.312
+PHY-3002 : Step(196): len = 546608, overlap = 153.906
+PHY-3002 : Step(197): len = 546816, overlap = 151.031
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.012287s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (127.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20378.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 705296, over cnt = 1602(4%), over = 7621, worst = 49
+PHY-1001 : End global iterations;  0.666587s wall, 0.921875s user + 0.046875s system = 0.968750s CPU (145.3%)
+
+PHY-1001 : Congestion index: top1 = 85.04, top5 = 63.98, top10 = 54.18, top15 = 48.01.
+PHY-3001 : End congestion estimation;  0.887649s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (133.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.836697s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.82601e-05
+PHY-3002 : Step(198): len = 648590, overlap = 91
+PHY-3002 : Step(199): len = 655508, overlap = 86.5938
+PHY-3002 : Step(200): len = 656350, overlap = 83.4688
+PHY-3002 : Step(201): len = 657157, overlap = 78.6875
+PHY-3002 : Step(202): len = 661441, overlap = 86.375
+PHY-3002 : Step(203): len = 665164, overlap = 69.5312
+PHY-3002 : Step(204): len = 672767, overlap = 79.8125
+PHY-3002 : Step(205): len = 684526, overlap = 67.5938
+PHY-3002 : Step(206): len = 690286, overlap = 72.4062
+PHY-3002 : Step(207): len = 691216, overlap = 71.125
+PHY-3002 : Step(208): len = 693959, overlap = 59.9688
+PHY-3002 : Step(209): len = 703228, overlap = 55.2188
+PHY-3002 : Step(210): len = 705427, overlap = 55.7188
+PHY-3002 : Step(211): len = 704747, overlap = 52.7188
+PHY-3002 : Step(212): len = 705818, overlap = 49.75
+PHY-3002 : Step(213): len = 709073, overlap = 51
+PHY-3002 : Step(214): len = 707947, overlap = 57.125
+PHY-3002 : Step(215): len = 705708, overlap = 51.8125
+PHY-3002 : Step(216): len = 705944, overlap = 49.6875
+PHY-3002 : Step(217): len = 706239, overlap = 49.75
+PHY-3002 : Step(218): len = 706103, overlap = 47.1875
+PHY-3002 : Step(219): len = 706341, overlap = 44.4688
+PHY-3002 : Step(220): len = 706335, overlap = 44.125
+PHY-3002 : Step(221): len = 705723, overlap = 45.3438
+PHY-3002 : Step(222): len = 705029, overlap = 43.5312
+PHY-3002 : Step(223): len = 705883, overlap = 43.5
+PHY-3002 : Step(224): len = 705080, overlap = 46.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00019652
+PHY-3002 : Step(225): len = 707074, overlap = 43.4375
+PHY-3002 : Step(226): len = 712017, overlap = 41.2812
+PHY-3002 : Step(227): len = 715349, overlap = 41.7812
+PHY-3002 : Step(228): len = 718600, overlap = 42.5
+PHY-3002 : Step(229): len = 721323, overlap = 44.2188
+PHY-3002 : Step(230): len = 720724, overlap = 46.3125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000392947
+PHY-3002 : Step(231): len = 724836, overlap = 44.7812
+PHY-3002 : Step(232): len = 738363, overlap = 42.9375
+PHY-3002 : Step(233): len = 756407, overlap = 35
+PHY-3002 : Step(234): len = 757638, overlap = 37.3125
+PHY-3002 : Step(235): len = 754845, overlap = 39.5312
+PHY-3002 : Step(236): len = 752144, overlap = 42.5
+PHY-3002 : Step(237): len = 751412, overlap = 41.1562
+PHY-3002 : Step(238): len = 753581, overlap = 40.375
+PHY-3002 : Step(239): len = 757135, overlap = 31.8125
+PHY-3002 : Step(240): len = 758417, overlap = 27.5
+PHY-3002 : Step(241): len = 758740, overlap = 24.8438
+PHY-3002 : Step(242): len = 761792, overlap = 26.5
+PHY-3002 : Step(243): len = 763945, overlap = 26.5625
+PHY-3002 : Step(244): len = 762987, overlap = 29.375
+PHY-3002 : Step(245): len = 760054, overlap = 30.75
+PHY-3002 : Step(246): len = 759118, overlap = 29.2812
+PHY-3002 : Step(247): len = 757726, overlap = 31.4375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000785894
+PHY-3002 : Step(248): len = 762886, overlap = 29.6562
+PHY-3002 : Step(249): len = 771388, overlap = 27.2812
+PHY-3002 : Step(250): len = 773009, overlap = 25.375
+PHY-3002 : Step(251): len = 772416, overlap = 26.3125
+PHY-3002 : Step(252): len = 774059, overlap = 26.5625
+PHY-3002 : Step(253): len = 778663, overlap = 25.3125
+PHY-3002 : Step(254): len = 781430, overlap = 26.2188
+PHY-3002 : Step(255): len = 783813, overlap = 27.5625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00149931
+PHY-3002 : Step(256): len = 784886, overlap = 27.6875
+PHY-3002 : Step(257): len = 788366, overlap = 27.6875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 72/20378.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865240, over cnt = 2923(8%), over = 15232, worst = 80
+PHY-1001 : End global iterations;  1.359206s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (147.1%)
+
+PHY-1001 : Congestion index: top1 = 117.52, top5 = 81.14, top10 = 67.74, top15 = 60.52.
+PHY-3001 : End congestion estimation;  1.647406s wall, 2.281250s user + 0.015625s system = 2.296875s CPU (139.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.897350s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000138126
+PHY-3002 : Step(258): len = 783911, overlap = 230.812
+PHY-3002 : Step(259): len = 782222, overlap = 176.375
+PHY-3002 : Step(260): len = 773425, overlap = 167.656
+PHY-3002 : Step(261): len = 768757, overlap = 151.094
+PHY-3002 : Step(262): len = 767551, overlap = 133.312
+PHY-3002 : Step(263): len = 762135, overlap = 132.844
+PHY-3002 : Step(264): len = 756203, overlap = 131.312
+PHY-3002 : Step(265): len = 751264, overlap = 120.344
+PHY-3002 : Step(266): len = 747197, overlap = 119.344
+PHY-3002 : Step(267): len = 741377, overlap = 114.625
+PHY-3002 : Step(268): len = 739920, overlap = 114.219
+PHY-3002 : Step(269): len = 736119, overlap = 112.188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000276253
+PHY-3002 : Step(270): len = 737196, overlap = 109.812
+PHY-3002 : Step(271): len = 740521, overlap = 105.312
+PHY-3002 : Step(272): len = 743775, overlap = 101.719
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000552505
+PHY-3002 : Step(273): len = 747548, overlap = 93.4375
+PHY-3002 : Step(274): len = 756137, overlap = 88.875
+PHY-3002 : Step(275): len = 760711, overlap = 78.125
+PHY-3002 : Step(276): len = 760949, overlap = 75.2188
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00110501
+PHY-3002 : Step(277): len = 762837, overlap = 74.2812
+PHY-3002 : Step(278): len = 765382, overlap = 73.0625
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85071, tnet num: 20200, tinst num: 17792, tnode num: 115737, tedge num: 136492.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.444932s wall, 1.390625s user + 0.046875s system = 1.437500s CPU (99.5%)
+
+RUN-1004 : used memory is 578 MB, reserved memory is 567 MB, peak memory is 714 MB
+OPT-1001 : Total overflow 388.97 peak overflow 2.97
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 824/20378.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858368, over cnt = 3165(8%), over = 12519, worst = 100
+PHY-1001 : End global iterations;  1.211295s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (152.2%)
+
+PHY-1001 : Congestion index: top1 = 93.99, top5 = 66.16, top10 = 57.43, top15 = 52.75.
+PHY-1001 : End incremental global routing;  1.528307s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (141.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.882027s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.2%)
+
+OPT-1001 : 52 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17655 has valid locations, 332 needs to be replaced
+PHY-3001 : design contains 18072 instances, 7433 luts, 9418 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6019 pins
+PHY-3001 : Found 3522 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 787867
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16985/20658.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874528, over cnt = 3204(9%), over = 12586, worst = 100
+PHY-1001 : End global iterations;  0.346772s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (108.1%)
+
+PHY-1001 : Congestion index: top1 = 93.60, top5 = 66.25, top10 = 57.58, top15 = 52.96.
+PHY-3001 : End congestion estimation;  0.594587s wall, 0.609375s user + 0.015625s system = 0.625000s CPU (105.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86206, tnet num: 20480, tinst num: 18072, tnode num: 117443, tedge num: 138202.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.409317s wall, 1.328125s user + 0.062500s system = 1.390625s CPU (98.7%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 616 MB, peak memory is 719 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20480 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.370769s wall, 2.281250s user + 0.078125s system = 2.359375s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(279): len = 786742, overlap = 1.1875
+PHY-3002 : Step(280): len = 786142, overlap = 1.125
+PHY-3002 : Step(281): len = 785872, overlap = 1.25
+PHY-3002 : Step(282): len = 785558, overlap = 1.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17069/20658.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 871656, over cnt = 3217(9%), over = 12602, worst = 101
+PHY-1001 : End global iterations;  0.216764s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (115.3%)
+
+PHY-1001 : Congestion index: top1 = 94.50, top5 = 66.98, top10 = 58.19, top15 = 53.39.
+PHY-3001 : End congestion estimation;  0.463766s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (107.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20480 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.903178s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00052714
+PHY-3002 : Step(283): len = 785447, overlap = 76.125
+PHY-3002 : Step(284): len = 785479, overlap = 75.4688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00105428
+PHY-3002 : Step(285): len = 785637, overlap = 75.625
+PHY-3002 : Step(286): len = 786125, overlap = 76.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00210856
+PHY-3002 : Step(287): len = 786690, overlap = 76.125
+PHY-3002 : Step(288): len = 787474, overlap = 76.125
+PHY-3001 : Final: Len = 787474, Over = 76.125
+PHY-3001 : End incremental placement;  5.045440s wall, 5.312500s user + 0.375000s system = 5.687500s CPU (112.7%)
+
+OPT-1001 : Total overflow 394.69 peak overflow 2.97
+OPT-1001 : End high-fanout net optimization;  7.996151s wall, 9.000000s user + 0.375000s system = 9.375000s CPU (117.2%)
+
+OPT-1001 : Current memory(MB): used = 721, reserve = 716, peak = 740.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17021/20658.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 875968, over cnt = 3145(8%), over = 11610, worst = 100
+PHY-1002 : len = 939320, over cnt = 2288(6%), over = 6010, worst = 66
+PHY-1002 : len = 980960, over cnt = 1053(2%), over = 2285, worst = 19
+PHY-1002 : len = 996712, over cnt = 496(1%), over = 1011, worst = 14
+PHY-1002 : len = 1.0107e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations;  1.880834s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 66.03, top5 = 57.49, top10 = 52.79, top15 = 49.92.
+OPT-1001 : End congestion update;  2.134478s wall, 2.890625s user + 0.000000s system = 2.890625s CPU (135.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20480 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.790795s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.8%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 55 cells processed and 6750 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 20 cells processed and 1100 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 13 cells processed and 650 slack improved
+OPT-1001 : End global optimization;  2.969473s wall, 3.718750s user + 0.000000s system = 3.718750s CPU (125.2%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 697, peak = 740.
+OPT-1001 : End physical optimization;  13.041964s wall, 14.812500s user + 0.453125s system = 15.265625s CPU (117.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7433 LUT to BLE ...
+SYN-4008 : Packed 7433 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6285 remaining SEQ's ...
+SYN-4005 : Packed 3904 SEQ with LUT/SLICE
+SYN-4006 : 702 single LUT's are left
+SYN-4006 : 2381 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9814/13545 primitive instances ...
+PHY-3001 : End packing;  1.541228s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6812 instances
+RUN-1001 : 3332 mslices, 3332 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17652 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9991 nets have 2 pins
+RUN-1001 : 6002 nets have [3 - 5] pins
+RUN-1001 : 979 nets have [6 - 10] pins
+RUN-1001 : 303 nets have [11 - 20] pins
+RUN-1001 : 346 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6810 instances, 6664 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3542 pins
+PHY-3001 : Found 1579 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 790167, Over = 250.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7534/17652.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 946504, over cnt = 2001(5%), over = 3366, worst = 9
+PHY-1002 : len = 955432, over cnt = 1360(3%), over = 2003, worst = 7
+PHY-1002 : len = 966576, over cnt = 693(1%), over = 985, worst = 7
+PHY-1002 : len = 977872, over cnt = 192(0%), over = 259, worst = 5
+PHY-1002 : len = 982056, over cnt = 7(0%), over = 9, worst = 2
+PHY-1001 : End global iterations;  1.654114s wall, 2.203125s user + 0.000000s system = 2.203125s CPU (133.2%)
+
+PHY-1001 : Congestion index: top1 = 61.12, top5 = 53.98, top10 = 50.08, top15 = 47.38.
+PHY-3001 : End congestion estimation;  2.034297s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (126.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73922, tnet num: 17474, tinst num: 6810, tnode num: 96625, tedge num: 124130.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.610459s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (99.9%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 614 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.454002s wall, 2.390625s user + 0.062500s system = 2.453125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.13512e-05
+PHY-3002 : Step(289): len = 776076, overlap = 239.5
+PHY-3002 : Step(290): len = 768014, overlap = 243.5
+PHY-3002 : Step(291): len = 761655, overlap = 242.5
+PHY-3002 : Step(292): len = 756177, overlap = 248.25
+PHY-3002 : Step(293): len = 751554, overlap = 252
+PHY-3002 : Step(294): len = 747214, overlap = 253
+PHY-3002 : Step(295): len = 743346, overlap = 267.25
+PHY-3002 : Step(296): len = 739341, overlap = 270.25
+PHY-3002 : Step(297): len = 736644, overlap = 270.5
+PHY-3002 : Step(298): len = 733989, overlap = 270.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000102702
+PHY-3002 : Step(299): len = 736526, overlap = 264.75
+PHY-3002 : Step(300): len = 741963, overlap = 250.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000205405
+PHY-3002 : Step(301): len = 745813, overlap = 239.75
+PHY-3002 : Step(302): len = 755664, overlap = 226.75
+PHY-3002 : Step(303): len = 756998, overlap = 231.5
+PHY-3002 : Step(304): len = 756943, overlap = 226.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00041081
+PHY-3002 : Step(305): len = 762360, overlap = 221.25
+PHY-3002 : Step(306): len = 772029, overlap = 221
+PHY-3002 : Step(307): len = 776749, overlap = 211.25
+PHY-3002 : Step(308): len = 775329, overlap = 206.75
+PHY-3002 : Step(309): len = 773973, overlap = 205.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.352211s wall, 0.468750s user + 0.562500s system = 1.031250s CPU (292.8%)
+
+PHY-3001 : Trial Legalized: Len = 942951
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 585/17652.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06222e+06, over cnt = 2810(7%), over = 4890, worst = 9
+PHY-1002 : len = 1.08266e+06, over cnt = 1741(4%), over = 2560, worst = 8
+PHY-1002 : len = 1.09858e+06, over cnt = 899(2%), over = 1350, worst = 8
+PHY-1002 : len = 1.11479e+06, over cnt = 245(0%), over = 410, worst = 5
+PHY-1002 : len = 1.1216e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.596829s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 67.35, top5 = 59.03, top10 = 54.94, top15 = 52.15.
+PHY-3001 : End congestion estimation;  3.025994s wall, 4.171875s user + 0.015625s system = 4.187500s CPU (138.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.848078s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000164952
+PHY-3002 : Step(310): len = 901892, overlap = 68
+PHY-3002 : Step(311): len = 880545, overlap = 93.75
+PHY-3002 : Step(312): len = 864631, overlap = 119.5
+PHY-3002 : Step(313): len = 851714, overlap = 144.25
+PHY-3002 : Step(314): len = 841330, overlap = 160
+PHY-3002 : Step(315): len = 833743, overlap = 168.75
+PHY-3002 : Step(316): len = 827266, overlap = 186
+PHY-3002 : Step(317): len = 822917, overlap = 189.25
+PHY-3002 : Step(318): len = 819260, overlap = 194
+PHY-3002 : Step(319): len = 816108, overlap = 197.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000328777
+PHY-3002 : Step(320): len = 820292, overlap = 189.25
+PHY-3002 : Step(321): len = 821930, overlap = 187
+PHY-3002 : Step(322): len = 823288, overlap = 183.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00053535
+PHY-3002 : Step(323): len = 827892, overlap = 177
+PHY-3002 : Step(324): len = 829666, overlap = 177.25
+PHY-3002 : Step(325): len = 831193, overlap = 175.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.094647s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (99.1%)
+
+PHY-3001 : Legalized: Len = 898094, Over = 0
+PHY-3001 : Spreading special nets. 460 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.128249s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.5%)
+
+PHY-3001 : 681 instances has been re-located, deltaX = 317, deltaY = 451, maxDist = 16.
+PHY-3001 : Final: Len = 911230, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73922, tnet num: 17474, tinst num: 6813, tnode num: 96625, tedge num: 124130.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.831081s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (99.8%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 648 MB, peak memory is 740 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3355/17652.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04165e+06, over cnt = 2590(7%), over = 4363, worst = 8
+PHY-1002 : len = 1.05538e+06, over cnt = 1601(4%), over = 2410, worst = 7
+PHY-1002 : len = 1.07372e+06, over cnt = 687(1%), over = 974, worst = 6
+PHY-1002 : len = 1.08256e+06, over cnt = 323(0%), over = 418, worst = 5
+PHY-1002 : len = 1.09006e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.216324s wall, 3.234375s user + 0.015625s system = 3.250000s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 67.18, top5 = 58.81, top10 = 54.40, top15 = 51.47.
+PHY-1001 : End incremental global routing;  2.587967s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (140.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17474 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.854993s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.5%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6721 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6830 instances, 6681 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3598 pins
+PHY-3001 : Found 1582 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 913968
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16127/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0927e+06, over cnt = 62(0%), over = 69, worst = 3
+PHY-1002 : len = 1.09274e+06, over cnt = 21(0%), over = 23, worst = 2
+PHY-1002 : len = 1.09298e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.09314e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.613876s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (101.8%)
+
+PHY-1001 : Congestion index: top1 = 67.18, top5 = 58.82, top10 = 54.41, top15 = 51.49.
+PHY-3001 : End congestion estimation;  0.926293s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (99.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74072, tnet num: 17493, tinst num: 6830, tnode num: 96810, tedge num: 124312.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.810262s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (100.1%)
+
+RUN-1004 : used memory is 661 MB, reserved memory is 671 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.687107s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(326): len = 913011, overlap = 0
+PHY-3002 : Step(327): len = 912581, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16113/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09105e+06, over cnt = 50(0%), over = 64, worst = 4
+PHY-1002 : len = 1.09123e+06, over cnt = 17(0%), over = 19, worst = 3
+PHY-1002 : len = 1.09132e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.09135e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.0914e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.803072s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (103.1%)
+
+PHY-1001 : Congestion index: top1 = 67.18, top5 = 58.82, top10 = 54.40, top15 = 51.48.
+PHY-3001 : End congestion estimation;  1.108117s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (102.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.865352s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000129068
+PHY-3002 : Step(328): len = 912499, overlap = 1.5
+PHY-3002 : Step(329): len = 912625, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005813s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (268.8%)
+
+PHY-3001 : Legalized: Len = 912717, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062836s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 3, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 912989, Over = 0
+PHY-3001 : End incremental placement;  6.046472s wall, 6.031250s user + 0.046875s system = 6.078125s CPU (100.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.060982s wall, 11.156250s user + 0.078125s system = 11.234375s CPU (111.7%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 741, peak = 746.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16091/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09146e+06, over cnt = 42(0%), over = 53, worst = 4
+PHY-1002 : len = 1.09157e+06, over cnt = 22(0%), over = 23, worst = 2
+PHY-1002 : len = 1.09179e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.09193e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.593468s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (102.7%)
+
+PHY-1001 : Congestion index: top1 = 67.18, top5 = 58.81, top10 = 54.40, top15 = 51.47.
+OPT-1001 : End congestion update;  0.914489s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.708252s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.5%)
+
+OPT-0007 : Start: WNS -1786 TNS -2450 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6742 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6830 instances, 6681 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3598 pins
+PHY-3001 : Found 1582 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 914385, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058084s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.6%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 8, deltaY = 7, maxDist = 1.
+PHY-3001 : Final: Len = 914635, Over = 0
+PHY-3001 : End incremental legalization;  0.365908s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.2%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1621 NUM_FEPS 2 with 25 cells processed and 6350 slack improved
+OPT-0007 : Iter 2: improved WNS -986 TNS -1621 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.120570s wall, 2.218750s user + 0.000000s system = 2.218750s CPU (104.6%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 741, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.705831s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16028/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0937e+06, over cnt = 91(0%), over = 101, worst = 3
+PHY-1002 : len = 1.09396e+06, over cnt = 40(0%), over = 40, worst = 1
+PHY-1002 : len = 1.09425e+06, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 1.09439e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.09441e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.797884s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (111.6%)
+
+PHY-1001 : Congestion index: top1 = 67.00, top5 = 58.65, top10 = 54.35, top15 = 51.50.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.725924s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -986 TNS -1621 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 66.482759
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -986ps with logic level 2 
+RUN-1001 :       #2 path slack -940ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 17671 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17671 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6742 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6830 instances, 6681 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3598 pins
+PHY-3001 : Found 1582 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 914635, Over = 0
+PHY-3001 : End spreading;  0.059567s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.9%)
+
+PHY-3001 : Final: Len = 914635, Over = 0
+PHY-3001 : End incremental legalization;  0.378699s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (119.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.711778s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.0%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09441e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.128220s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.5%)
+
+PHY-1001 : Congestion index: top1 = 67.00, top5 = 58.65, top10 = 54.35, top15 = 51.50.
+OPT-1001 : End congestion update;  0.428172s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.712057s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.9%)
+
+OPT-0007 : Start: WNS -986 TNS -1621 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -986 TNS -1621 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.155676s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 741, peak = 746.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09441e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.130921s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 67.00, top5 = 58.65, top10 = 54.35, top15 = 51.50.
+OPT-1001 : End congestion update;  0.453903s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.713024s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.6%)
+
+OPT-0007 : Start: WNS -986 TNS -1621 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -986 TNS -1621 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -986 TNS -1621 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.325093s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.2%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 741, peak = 746.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.704551s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 741, reserve = 741, peak = 746.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.723374s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.4%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16148/17671.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09441e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.140043s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.4%)
+
+PHY-1001 : Congestion index: top1 = 67.00, top5 = 58.65, top10 = 54.35, top15 = 51.50.
+RUN-1001 : End congestion update;  0.474663s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (102.0%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.201539s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 741, peak = 746.
+OPT-1001 : End physical optimization;  22.578904s wall, 24.015625s user + 0.093750s system = 24.109375s CPU (106.8%)
+
+RUN-1003 : finish command "place" in  65.504303s wall, 101.250000s user + 5.906250s system = 107.156250s CPU (163.6%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 627 MB, peak memory is 746 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.685698s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (174.3%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 628 MB, peak memory is 746 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6832 instances
+RUN-1001 : 3336 mslices, 3345 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17671 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9987 nets have 2 pins
+RUN-1001 : 5999 nets have [3 - 5] pins
+RUN-1001 : 993 nets have [6 - 10] pins
+RUN-1001 : 305 nets have [11 - 20] pins
+RUN-1001 : 359 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74072, tnet num: 17493, tinst num: 6830, tnode num: 96810, tedge num: 124312.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.564715s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.9%)
+
+RUN-1004 : used memory is 605 MB, reserved memory is 598 MB, peak memory is 746 MB
+PHY-1001 : 3336 mslices, 3345 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[98] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.02246e+06, over cnt = 2772(7%), over = 4677, worst = 7
+PHY-1002 : len = 1.03898e+06, over cnt = 1919(5%), over = 2857, worst = 7
+PHY-1002 : len = 1.06207e+06, over cnt = 739(2%), over = 1092, worst = 6
+PHY-1002 : len = 1.07851e+06, over cnt = 7(0%), over = 11, worst = 4
+PHY-1002 : len = 1.07868e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.785317s wall, 3.656250s user + 0.000000s system = 3.656250s CPU (131.3%)
+
+PHY-1001 : Congestion index: top1 = 67.16, top5 = 58.46, top10 = 53.95, top15 = 51.02.
+PHY-1001 : End global routing;  3.107566s wall, 3.968750s user + 0.000000s system = 3.968750s CPU (127.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 713, reserve = 719, peak = 746.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 987, reserve = 994, peak = 987.
+PHY-1001 : End build detailed router design. 3.978702s wall, 3.906250s user + 0.062500s system = 3.968750s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 269640, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.783608s wall, 4.750000s user + 0.031250s system = 4.781250s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 269696, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.404711s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1023, reserve = 1031, peak = 1023.
+PHY-1001 : End phase 1; 5.200039s wall, 5.171875s user + 0.031250s system = 5.203125s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 46% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.57158e+06, over cnt = 1940(0%), over = 1950, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1041, reserve = 1046, peak = 1041.
+PHY-1001 : End initial routed; 55.893737s wall, 83.843750s user + 0.468750s system = 84.312500s CPU (150.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16593(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.806   |  -3.560   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.179818s wall, 3.156250s user + 0.031250s system = 3.187500s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1055, peak = 1050.
+PHY-1001 : End phase 2; 59.073619s wall, 87.000000s user + 0.500000s system = 87.500000s CPU (148.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.804ns STNS -3.558ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.136593s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1022 : len = 2.57158e+06, over cnt = 1942(0%), over = 1952, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.389506s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.52918e+06, over cnt = 742(0%), over = 743, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.379596s wall, 3.640625s user + 0.015625s system = 3.656250s CPU (153.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.52486e+06, over cnt = 212(0%), over = 212, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.216773s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (136.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.52558e+06, over cnt = 54(0%), over = 54, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.584073s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (139.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.52636e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.313960s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (129.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.52658e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.267717s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (105.1%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.52668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.324022s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (96.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.52668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.312086s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.52668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.170783s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.52668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.172642s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.52668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.232244s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.52668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.243604s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (121.9%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.52668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.333535s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (98.4%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.5267e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.195488s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.52672e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.166872s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16593(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.804   |  -3.558   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.172180s wall, 3.156250s user + 0.015625s system = 3.171875s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 620 feed throughs used by 444 nets
+PHY-1001 : End commit to database; 2.276253s wall, 2.250000s user + 0.015625s system = 2.265625s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1165, peak = 1156.
+PHY-1001 : End phase 3; 13.144223s wall, 15.203125s user + 0.062500s system = 15.265625s CPU (116.1%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.804ns STNS -3.558ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.140564s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.0%)
+
+PHY-1022 : len = 2.52672e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.393546s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.804ns, -3.558ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16593(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.804   |  -3.558   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.265367s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 620 feed throughs used by 444 nets
+PHY-1001 : End commit to database; 2.389316s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1174, peak = 1165.
+PHY-1001 : End phase 4; 6.076430s wall, 6.078125s user + 0.000000s system = 6.078125s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.52672e+06
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1176, peak = 1167.
+PHY-1001 : End export database. 0.060970s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.5%)
+
+PHY-1001 : End detail routing;  87.924775s wall, 117.812500s user + 0.656250s system = 118.468750s CPU (134.7%)
+
+RUN-1003 : finish command "route" in  93.652418s wall, 124.406250s user + 0.656250s system = 125.062500s CPU (133.5%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1100 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10209   out of  19600   52.09%
+#reg                     9561   out of  19600   48.78%
+#le                     12497
+  #lut only              2936   out of  12497   23.49%
+  #reg only              2288   out of  12497   18.31%
+  #lut&reg               7273   out of  12497   58.20%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1823
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1429
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1329
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               975
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    137
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg32_syn_181.f1    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/u_local_bus_slve_cis/reg39_syn_235.f1    2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P163       LVCMOS33           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12497  |9182    |1027    |9591    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |529    |445     |23      |430     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |101    |95      |4       |90      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |27     |27      |0       |20      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |746    |377     |96      |558     |0       |0       |
+|    u_ADconfig                |AD_config            |178    |128     |25      |131     |0       |0       |
+|    u_gen_sp                  |gen_sp               |259    |164     |71      |118     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |750    |412     |96      |558     |0       |0       |
+|    u_ADconfig                |AD_config            |180    |132     |25      |130     |0       |0       |
+|    u_gen_sp                  |gen_sp               |262    |166     |71      |120     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3161   |2472    |306     |2230    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |185    |122     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |2947   |2341    |289     |2053    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2372   |1913    |253     |1577    |22      |0       |
+|        channelPart           |channel_part_8478    |121    |117     |3       |108     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |45      |0       |0       |
+|        ram_switch            |ram_switch           |1879   |1493    |197     |1203    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |253    |226     |27      |120     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |6       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |7       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |9       |0       |0       |
+|          insert              |insert               |1021   |662     |170     |726     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |605    |605     |0       |357     |0       |0       |
+|        read_ram_i            |read_ram             |280    |232     |44      |193     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |223    |183     |40      |151     |0       |0       |
+|          read_ram_data       |read_ram_data        |55     |48      |4       |40      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |342    |249     |36      |278     |3       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3237   |2399    |349     |2185    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |181    |111     |17      |140     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1      |0       |0       |1       |0       |0       |
+|    u_sort                    |sort_rev             |3031   |2266    |332     |2020    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |5       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2504   |1875    |290     |1600    |22      |1       |
+|        channelPart           |channel_part_8478    |237    |225     |3       |149     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |1808   |1315    |197     |1171    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |230    |202     |27      |119     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |10      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |17      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|          insert              |insert               |1009   |546     |170     |720     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |569    |567     |0       |332     |0       |0       |
+|        read_ram_i            |read_ram_rev         |370    |264     |81      |208     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |306    |223     |73      |161     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |64     |41      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9925  
+    #2         2       3882  
+    #3         3       1456  
+    #4         4       658   
+    #5        5-10     1053  
+    #6       11-50     575   
+    #7       51-100     26   
+    #8        >500      1    
+  Average     2.89           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.064085s wall, 3.562500s user + 0.015625s system = 3.578125s CPU (173.4%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1101 MB, peak memory is 1167 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74072, tnet num: 17493, tinst num: 6830, tnode num: 96810, tedge num: 124312.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.590293s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.2%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1105 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17493 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.454007s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (99.9%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1107 MB, peak memory is 1167 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6830
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17671, pip num: 178563
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 620
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3251 valid insts, and 491136 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.795015s wall, 66.125000s user + 0.265625s system = 66.390625s CPU (677.8%)
+
+RUN-1004 : used memory is 1273 MB, reserved memory is 1276 MB, peak memory is 1388 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_151722.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_152936.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_152936.log
new file mode 100644
index 0000000..4029cea
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_152936.log
@@ -0,0 +1,1844 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:29:36 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.135814s wall, 2.015625s user + 0.125000s system = 2.140625s CPU (100.2%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 316 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2316 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17767 instances
+RUN-0007 : 7336 luts, 9208 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20351 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13342 nets have 2 pins
+RUN-1001 : 5720 nets have [3 - 5] pins
+RUN-1001 : 876 nets have [6 - 10] pins
+RUN-1001 : 157 nets have [11 - 20] pins
+RUN-1001 : 181 nets have [21 - 99] pins
+RUN-1001 : 55 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3636     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17765 instances, 7336 luts, 9208 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84963, tnet num: 20173, tinst num: 17765, tnode num: 115548, tedge num: 136330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.154136s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.2%)
+
+RUN-1004 : used memory is 539 MB, reserved memory is 516 MB, peak memory is 539 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20173 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.945491s wall, 1.937500s user + 0.000000s system = 1.937500s CPU (99.6%)
+
+PHY-3001 : Found 3485 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.05751e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17765.
+PHY-3001 : Level 1 #clusters 2033.
+PHY-3001 : End clustering;  0.129354s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (120.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.266e+06, overlap = 474.031
+PHY-3002 : Step(2): len = 1.18776e+06, overlap = 534.406
+PHY-3002 : Step(3): len = 844791, overlap = 591.531
+PHY-3002 : Step(4): len = 776775, overlap = 635.969
+PHY-3002 : Step(5): len = 611444, overlap = 778.812
+PHY-3002 : Step(6): len = 536970, overlap = 820.406
+PHY-3002 : Step(7): len = 467922, overlap = 910.969
+PHY-3002 : Step(8): len = 423317, overlap = 936.25
+PHY-3002 : Step(9): len = 389310, overlap = 998.906
+PHY-3002 : Step(10): len = 363674, overlap = 1028.84
+PHY-3002 : Step(11): len = 320270, overlap = 1106.38
+PHY-3002 : Step(12): len = 299097, overlap = 1134.62
+PHY-3002 : Step(13): len = 267369, overlap = 1173.44
+PHY-3002 : Step(14): len = 255327, overlap = 1211.03
+PHY-3002 : Step(15): len = 232133, overlap = 1252.12
+PHY-3002 : Step(16): len = 214573, overlap = 1272.41
+PHY-3002 : Step(17): len = 195954, overlap = 1319.91
+PHY-3002 : Step(18): len = 183299, overlap = 1355.59
+PHY-3002 : Step(19): len = 166799, overlap = 1399.16
+PHY-3002 : Step(20): len = 157643, overlap = 1419.31
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.09566e-06
+PHY-3002 : Step(21): len = 159125, overlap = 1370.66
+PHY-3002 : Step(22): len = 189405, overlap = 1294.44
+PHY-3002 : Step(23): len = 189716, overlap = 1264.34
+PHY-3002 : Step(24): len = 192615, overlap = 1243.59
+PHY-3002 : Step(25): len = 190719, overlap = 1242.62
+PHY-3002 : Step(26): len = 190597, overlap = 1221.88
+PHY-3002 : Step(27): len = 188760, overlap = 1204.84
+PHY-3002 : Step(28): len = 188512, overlap = 1172.94
+PHY-3002 : Step(29): len = 185568, overlap = 1168.66
+PHY-3002 : Step(30): len = 182981, overlap = 1160.25
+PHY-3002 : Step(31): len = 180377, overlap = 1156.5
+PHY-3002 : Step(32): len = 177388, overlap = 1160.19
+PHY-3002 : Step(33): len = 176443, overlap = 1150.31
+PHY-3002 : Step(34): len = 174987, overlap = 1127.12
+PHY-3002 : Step(35): len = 175252, overlap = 1133.78
+PHY-3002 : Step(36): len = 173205, overlap = 1144.69
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.19133e-06
+PHY-3002 : Step(37): len = 178301, overlap = 1128.44
+PHY-3002 : Step(38): len = 193159, overlap = 1088.62
+PHY-3002 : Step(39): len = 199969, overlap = 1040.78
+PHY-3002 : Step(40): len = 203715, overlap = 1023.84
+PHY-3002 : Step(41): len = 205757, overlap = 1006.41
+PHY-3002 : Step(42): len = 205829, overlap = 994.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.38265e-06
+PHY-3002 : Step(43): len = 215388, overlap = 974.438
+PHY-3002 : Step(44): len = 232089, overlap = 871.781
+PHY-3002 : Step(45): len = 240507, overlap = 792.031
+PHY-3002 : Step(46): len = 248672, overlap = 786.312
+PHY-3002 : Step(47): len = 252500, overlap = 785.781
+PHY-3002 : Step(48): len = 255794, overlap = 805.5
+PHY-3002 : Step(49): len = 255473, overlap = 787.594
+PHY-3002 : Step(50): len = 255433, overlap = 775.188
+PHY-3002 : Step(51): len = 255511, overlap = 777.25
+PHY-3002 : Step(52): len = 255741, overlap = 778.438
+PHY-3002 : Step(53): len = 255732, overlap = 778.125
+PHY-3002 : Step(54): len = 254475, overlap = 777.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.76531e-06
+PHY-3002 : Step(55): len = 270081, overlap = 753.812
+PHY-3002 : Step(56): len = 290003, overlap = 704.125
+PHY-3002 : Step(57): len = 296733, overlap = 651.969
+PHY-3002 : Step(58): len = 300041, overlap = 590.5
+PHY-3002 : Step(59): len = 300594, overlap = 554.062
+PHY-3002 : Step(60): len = 301207, overlap = 548.969
+PHY-3002 : Step(61): len = 302559, overlap = 564.094
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.75306e-05
+PHY-3002 : Step(62): len = 326885, overlap = 495.375
+PHY-3002 : Step(63): len = 355904, overlap = 468.688
+PHY-3002 : Step(64): len = 360884, overlap = 470.438
+PHY-3002 : Step(65): len = 360896, overlap = 466.594
+PHY-3002 : Step(66): len = 357977, overlap = 428.281
+PHY-3002 : Step(67): len = 357263, overlap = 417.906
+PHY-3002 : Step(68): len = 354003, overlap = 434.812
+PHY-3002 : Step(69): len = 353064, overlap = 417.812
+PHY-3002 : Step(70): len = 351174, overlap = 406.938
+PHY-3002 : Step(71): len = 349723, overlap = 411.219
+PHY-3002 : Step(72): len = 348105, overlap = 418.312
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.50612e-05
+PHY-3002 : Step(73): len = 372752, overlap = 377.438
+PHY-3002 : Step(74): len = 389433, overlap = 352.562
+PHY-3002 : Step(75): len = 387391, overlap = 344.938
+PHY-3002 : Step(76): len = 387153, overlap = 339.875
+PHY-3002 : Step(77): len = 388084, overlap = 323.062
+PHY-3002 : Step(78): len = 389673, overlap = 318.5
+PHY-3002 : Step(79): len = 386990, overlap = 314.281
+PHY-3002 : Step(80): len = 387346, overlap = 319.031
+PHY-3002 : Step(81): len = 387807, overlap = 323.781
+PHY-3002 : Step(82): len = 387214, overlap = 314.312
+PHY-3002 : Step(83): len = 385162, overlap = 320.438
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.99488e-05
+PHY-3002 : Step(84): len = 403821, overlap = 304.5
+PHY-3002 : Step(85): len = 417859, overlap = 300.938
+PHY-3002 : Step(86): len = 417206, overlap = 278.844
+PHY-3002 : Step(87): len = 419799, overlap = 267.031
+PHY-3002 : Step(88): len = 423653, overlap = 255.094
+PHY-3002 : Step(89): len = 427345, overlap = 244.656
+PHY-3002 : Step(90): len = 424975, overlap = 236.938
+PHY-3002 : Step(91): len = 425810, overlap = 240.438
+PHY-3002 : Step(92): len = 427549, overlap = 254.25
+PHY-3002 : Step(93): len = 429091, overlap = 244.219
+PHY-3002 : Step(94): len = 426003, overlap = 240.094
+PHY-3002 : Step(95): len = 425468, overlap = 244.25
+PHY-3002 : Step(96): len = 427071, overlap = 247.312
+PHY-3002 : Step(97): len = 428195, overlap = 243.156
+PHY-3002 : Step(98): len = 425689, overlap = 239.812
+PHY-3002 : Step(99): len = 424721, overlap = 229.969
+PHY-3002 : Step(100): len = 425477, overlap = 229.781
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000139898
+PHY-3002 : Step(101): len = 441832, overlap = 216.688
+PHY-3002 : Step(102): len = 452980, overlap = 217.25
+PHY-3002 : Step(103): len = 452353, overlap = 200.969
+PHY-3002 : Step(104): len = 452720, overlap = 210.688
+PHY-3002 : Step(105): len = 455610, overlap = 200.906
+PHY-3002 : Step(106): len = 457500, overlap = 201.531
+PHY-3002 : Step(107): len = 456021, overlap = 195.688
+PHY-3002 : Step(108): len = 456316, overlap = 197.344
+PHY-3002 : Step(109): len = 458775, overlap = 203.656
+PHY-3002 : Step(110): len = 460129, overlap = 204.531
+PHY-3002 : Step(111): len = 458279, overlap = 206.281
+PHY-3002 : Step(112): len = 458069, overlap = 203.094
+PHY-3002 : Step(113): len = 459304, overlap = 204.25
+PHY-3002 : Step(114): len = 460310, overlap = 205.531
+PHY-3002 : Step(115): len = 458936, overlap = 198.531
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000262381
+PHY-3002 : Step(116): len = 469085, overlap = 191
+PHY-3002 : Step(117): len = 476948, overlap = 189.312
+PHY-3002 : Step(118): len = 476848, overlap = 191.25
+PHY-3002 : Step(119): len = 477123, overlap = 187.375
+PHY-3002 : Step(120): len = 480120, overlap = 172.719
+PHY-3002 : Step(121): len = 482615, overlap = 164.688
+PHY-3002 : Step(122): len = 482012, overlap = 166.812
+PHY-3002 : Step(123): len = 483250, overlap = 165.062
+PHY-3002 : Step(124): len = 485075, overlap = 168.156
+PHY-3002 : Step(125): len = 486393, overlap = 164.75
+PHY-3002 : Step(126): len = 485519, overlap = 164.656
+PHY-3002 : Step(127): len = 485347, overlap = 164.469
+PHY-3002 : Step(128): len = 487063, overlap = 164.531
+PHY-3002 : Step(129): len = 488210, overlap = 162.594
+PHY-3002 : Step(130): len = 487133, overlap = 162.062
+PHY-3002 : Step(131): len = 487367, overlap = 160.375
+PHY-3002 : Step(132): len = 488523, overlap = 162.094
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000524761
+PHY-3002 : Step(133): len = 497825, overlap = 163.812
+PHY-3002 : Step(134): len = 505475, overlap = 154.5
+PHY-3002 : Step(135): len = 506969, overlap = 157.094
+PHY-3002 : Step(136): len = 508088, overlap = 151.219
+PHY-3002 : Step(137): len = 509787, overlap = 161.281
+PHY-3002 : Step(138): len = 511819, overlap = 161.562
+PHY-3002 : Step(139): len = 512005, overlap = 163.406
+PHY-3002 : Step(140): len = 512783, overlap = 168.625
+PHY-3002 : Step(141): len = 514358, overlap = 161.312
+PHY-3002 : Step(142): len = 515221, overlap = 157.719
+PHY-3002 : Step(143): len = 513670, overlap = 150.156
+PHY-3002 : Step(144): len = 512865, overlap = 150.594
+PHY-3002 : Step(145): len = 513552, overlap = 147.625
+PHY-3002 : Step(146): len = 513712, overlap = 148.906
+PHY-3002 : Step(147): len = 512977, overlap = 140.25
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000937929
+PHY-3002 : Step(148): len = 516541, overlap = 138.75
+PHY-3002 : Step(149): len = 520900, overlap = 133.531
+PHY-3002 : Step(150): len = 522470, overlap = 136.719
+PHY-3002 : Step(151): len = 523464, overlap = 132.781
+PHY-3002 : Step(152): len = 525064, overlap = 137.312
+PHY-3002 : Step(153): len = 526305, overlap = 139
+PHY-3002 : Step(154): len = 526304, overlap = 125.312
+PHY-3002 : Step(155): len = 527088, overlap = 125.969
+PHY-3002 : Step(156): len = 528996, overlap = 129.062
+PHY-3002 : Step(157): len = 530106, overlap = 127.25
+PHY-3002 : Step(158): len = 529780, overlap = 129.062
+PHY-3002 : Step(159): len = 529981, overlap = 130.719
+PHY-3002 : Step(160): len = 531227, overlap = 131.062
+PHY-3002 : Step(161): len = 531944, overlap = 126.75
+PHY-3002 : Step(162): len = 530895, overlap = 124.562
+PHY-3002 : Step(163): len = 530543, overlap = 121.406
+PHY-3002 : Step(164): len = 531086, overlap = 122.938
+PHY-3002 : Step(165): len = 531677, overlap = 118.5
+PHY-3002 : Step(166): len = 530755, overlap = 125.844
+PHY-3002 : Step(167): len = 530534, overlap = 125.781
+PHY-3002 : Step(168): len = 531531, overlap = 123.281
+PHY-3002 : Step(169): len = 532488, overlap = 121.656
+PHY-3002 : Step(170): len = 532043, overlap = 130.406
+PHY-3002 : Step(171): len = 531828, overlap = 127.938
+PHY-3002 : Step(172): len = 532439, overlap = 122.625
+PHY-3002 : Step(173): len = 532890, overlap = 119.969
+PHY-3002 : Step(174): len = 532347, overlap = 118.125
+PHY-3002 : Step(175): len = 532294, overlap = 119.031
+PHY-3002 : Step(176): len = 532879, overlap = 118.344
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00173632
+PHY-3002 : Step(177): len = 535356, overlap = 118.312
+PHY-3002 : Step(178): len = 538095, overlap = 115.344
+PHY-3002 : Step(179): len = 539540, overlap = 120.031
+PHY-3002 : Step(180): len = 540360, overlap = 121.438
+PHY-3002 : Step(181): len = 540763, overlap = 119.281
+PHY-3002 : Step(182): len = 541056, overlap = 119.281
+PHY-3002 : Step(183): len = 542002, overlap = 120.031
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014453s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (108.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20351.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 680936, over cnt = 1554(4%), over = 7660, worst = 44
+PHY-1001 : End global iterations;  0.676684s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (136.2%)
+
+PHY-1001 : Congestion index: top1 = 88.30, top5 = 64.47, top10 = 53.26, top15 = 46.85.
+PHY-3001 : End congestion estimation;  0.892065s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (127.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20173 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.846933s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.2234e-05
+PHY-3002 : Step(184): len = 626063, overlap = 72.9062
+PHY-3002 : Step(185): len = 631768, overlap = 74.125
+PHY-3002 : Step(186): len = 626330, overlap = 73.7188
+PHY-3002 : Step(187): len = 627646, overlap = 76.8125
+PHY-3002 : Step(188): len = 635506, overlap = 75.2812
+PHY-3002 : Step(189): len = 644026, overlap = 69.6875
+PHY-3002 : Step(190): len = 649095, overlap = 65.7812
+PHY-3002 : Step(191): len = 653358, overlap = 62.9688
+PHY-3002 : Step(192): len = 660707, overlap = 64.3438
+PHY-3002 : Step(193): len = 670248, overlap = 73
+PHY-3002 : Step(194): len = 675849, overlap = 70.75
+PHY-3002 : Step(195): len = 677880, overlap = 71.5312
+PHY-3002 : Step(196): len = 680370, overlap = 73.125
+PHY-3002 : Step(197): len = 683436, overlap = 58.625
+PHY-3002 : Step(198): len = 685051, overlap = 57.9062
+PHY-3002 : Step(199): len = 685969, overlap = 63
+PHY-3002 : Step(200): len = 685220, overlap = 74.5312
+PHY-3002 : Step(201): len = 685037, overlap = 75.8438
+PHY-3002 : Step(202): len = 686733, overlap = 72
+PHY-3002 : Step(203): len = 685075, overlap = 69.5312
+PHY-3002 : Step(204): len = 683345, overlap = 71.625
+PHY-3002 : Step(205): len = 682409, overlap = 70.625
+PHY-3002 : Step(206): len = 681993, overlap = 62.8125
+PHY-3002 : Step(207): len = 680791, overlap = 59.25
+PHY-3002 : Step(208): len = 681021, overlap = 57.375
+PHY-3002 : Step(209): len = 679980, overlap = 50.4688
+PHY-3002 : Step(210): len = 679147, overlap = 46.4062
+PHY-3002 : Step(211): len = 678111, overlap = 43.5312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000184468
+PHY-3002 : Step(212): len = 680111, overlap = 39.3125
+PHY-3002 : Step(213): len = 682826, overlap = 39.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 97/20351.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 761600, over cnt = 2754(7%), over = 13331, worst = 42
+PHY-1001 : End global iterations;  1.475556s wall, 2.031250s user + 0.062500s system = 2.093750s CPU (141.9%)
+
+PHY-1001 : Congestion index: top1 = 103.08, top5 = 75.00, top10 = 64.29, top15 = 57.77.
+PHY-3001 : End congestion estimation;  1.735164s wall, 2.281250s user + 0.062500s system = 2.343750s CPU (135.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20173 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.928573s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.16088e-05
+PHY-3002 : Step(214): len = 682144, overlap = 292.469
+PHY-3002 : Step(215): len = 688561, overlap = 242.844
+PHY-3002 : Step(216): len = 686428, overlap = 227.75
+PHY-3002 : Step(217): len = 684261, overlap = 215.219
+PHY-3002 : Step(218): len = 685584, overlap = 208.688
+PHY-3002 : Step(219): len = 685064, overlap = 196.062
+PHY-3002 : Step(220): len = 682372, overlap = 185.375
+PHY-3002 : Step(221): len = 681516, overlap = 178.469
+PHY-3002 : Step(222): len = 678427, overlap = 172.781
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000163218
+PHY-3002 : Step(223): len = 679862, overlap = 167.938
+PHY-3002 : Step(224): len = 682700, overlap = 161.469
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000295915
+PHY-3002 : Step(225): len = 685751, overlap = 151.938
+PHY-3002 : Step(226): len = 696747, overlap = 132.656
+PHY-3002 : Step(227): len = 705295, overlap = 120.594
+PHY-3002 : Step(228): len = 700440, overlap = 122.219
+PHY-3002 : Step(229): len = 697611, overlap = 119.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000550016
+PHY-3002 : Step(230): len = 703831, overlap = 111.625
+PHY-3002 : Step(231): len = 713668, overlap = 101.406
+PHY-3002 : Step(232): len = 721396, overlap = 92.6875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00110003
+PHY-3002 : Step(233): len = 721008, overlap = 93.1875
+PHY-3002 : Step(234): len = 722858, overlap = 88.9688
+PHY-3002 : Step(235): len = 731414, overlap = 87.625
+PHY-3002 : Step(236): len = 739363, overlap = 82.0625
+PHY-3002 : Step(237): len = 741784, overlap = 79.2188
+PHY-3002 : Step(238): len = 742281, overlap = 77.8125
+PHY-3002 : Step(239): len = 742019, overlap = 75.0625
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00192844
+PHY-3002 : Step(240): len = 743586, overlap = 76.2812
+PHY-3002 : Step(241): len = 747088, overlap = 74.5312
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84963, tnet num: 20173, tinst num: 17765, tnode num: 115548, tedge num: 136330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.434909s wall, 1.390625s user + 0.046875s system = 1.437500s CPU (100.2%)
+
+RUN-1004 : used memory is 582 MB, reserved memory is 565 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 418.81 peak overflow 3.31
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1025/20351.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844008, over cnt = 3249(9%), over = 13052, worst = 82
+PHY-1001 : End global iterations;  1.182695s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (148.0%)
+
+PHY-1001 : Congestion index: top1 = 93.62, top5 = 68.07, top10 = 59.32, top15 = 54.47.
+PHY-1001 : End incremental global routing;  1.489955s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (137.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20173 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.895574s wall, 0.843750s user + 0.046875s system = 0.890625s CPU (99.4%)
+
+OPT-1001 : 52 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17628 has valid locations, 327 needs to be replaced
+PHY-3001 : design contains 18040 instances, 7437 luts, 9382 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6024 pins
+PHY-3001 : Found 3520 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 768784
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17297/20626.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858672, over cnt = 3298(9%), over = 13113, worst = 82
+PHY-1001 : End global iterations;  0.249530s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (112.7%)
+
+PHY-1001 : Congestion index: top1 = 93.47, top5 = 68.06, top10 = 59.49, top15 = 54.82.
+PHY-3001 : End congestion estimation;  0.509466s wall, 0.531250s user + 0.015625s system = 0.546875s CPU (107.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86078, tnet num: 20448, tinst num: 18040, tnode num: 117206, tedge num: 138010.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.463155s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.3%)
+
+RUN-1004 : used memory is 629 MB, reserved memory is 625 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20448 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.416682s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(242): len = 767690, overlap = 0.25
+PHY-3002 : Step(243): len = 767229, overlap = 0.3125
+PHY-3002 : Step(244): len = 766899, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17418/20626.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855672, over cnt = 3289(9%), over = 13175, worst = 82
+PHY-1001 : End global iterations;  0.194188s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (104.6%)
+
+PHY-1001 : Congestion index: top1 = 94.59, top5 = 68.55, top10 = 59.80, top15 = 55.03.
+PHY-3001 : End congestion estimation;  0.447656s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (104.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20448 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.180206s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (76.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000466447
+PHY-3002 : Step(245): len = 766626, overlap = 77.1875
+PHY-3002 : Step(246): len = 766584, overlap = 77.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000932894
+PHY-3002 : Step(247): len = 766693, overlap = 77
+PHY-3002 : Step(248): len = 767151, overlap = 77.8125
+PHY-3001 : Final: Len = 767151, Over = 77.8125
+PHY-3001 : End incremental placement;  5.211821s wall, 5.125000s user + 0.203125s system = 5.328125s CPU (102.2%)
+
+OPT-1001 : Total overflow 424.56 peak overflow 3.31
+OPT-1001 : End high-fanout net optimization;  8.135331s wall, 8.562500s user + 0.250000s system = 8.812500s CPU (108.3%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 713, peak = 742.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17342/20626.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859304, over cnt = 3273(9%), over = 12153, worst = 82
+PHY-1002 : len = 923096, over cnt = 2401(6%), over = 6378, worst = 61
+PHY-1002 : len = 964768, over cnt = 1252(3%), over = 2974, worst = 20
+PHY-1002 : len = 999408, over cnt = 318(0%), over = 733, worst = 16
+PHY-1002 : len = 1.01068e+06, over cnt = 15(0%), over = 47, worst = 6
+PHY-1001 : End global iterations;  2.020379s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (142.3%)
+
+PHY-1001 : Congestion index: top1 = 68.43, top5 = 58.66, top10 = 54.05, top15 = 51.10.
+OPT-1001 : End congestion update;  2.274774s wall, 3.093750s user + 0.031250s system = 3.125000s CPU (137.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20448 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.783067s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 68 cells processed and 3900 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 17 cells processed and 1500 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 2 cells processed and 100 slack improved
+OPT-1001 : End global optimization;  3.099950s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (127.5%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 696, peak = 742.
+OPT-1001 : End physical optimization;  13.279968s wall, 14.593750s user + 0.328125s system = 14.921875s CPU (112.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7437 LUT to BLE ...
+SYN-4008 : Packed 7437 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6249 remaining SEQ's ...
+SYN-4005 : Packed 3906 SEQ with LUT/SLICE
+SYN-4006 : 702 single LUT's are left
+SYN-4006 : 2343 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9780/13511 primitive instances ...
+PHY-3001 : End packing;  1.642997s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6789 instances
+RUN-1001 : 3321 mslices, 3320 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17620 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9973 nets have 2 pins
+RUN-1001 : 5983 nets have [3 - 5] pins
+RUN-1001 : 985 nets have [6 - 10] pins
+RUN-1001 : 289 nets have [11 - 20] pins
+RUN-1001 : 358 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6787 instances, 6641 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3530 pins
+PHY-3001 : Found 1559 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 763025, Over = 252.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7675/17620.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926136, over cnt = 2089(5%), over = 3410, worst = 8
+PHY-1002 : len = 934088, over cnt = 1366(3%), over = 1927, worst = 6
+PHY-1002 : len = 945280, over cnt = 672(1%), over = 931, worst = 6
+PHY-1002 : len = 951968, over cnt = 340(0%), over = 448, worst = 5
+PHY-1002 : len = 960280, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.644239s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (132.1%)
+
+PHY-1001 : Congestion index: top1 = 62.20, top5 = 54.64, top10 = 50.25, top15 = 47.53.
+PHY-3001 : End congestion estimation;  2.035848s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (125.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73757, tnet num: 17442, tinst num: 6787, tnode num: 96366, tedge num: 123878.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.574947s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (100.2%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 611 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17442 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.507225s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.03466e-05
+PHY-3002 : Step(249): len = 747346, overlap = 248
+PHY-3002 : Step(250): len = 739406, overlap = 254.75
+PHY-3002 : Step(251): len = 733533, overlap = 259.5
+PHY-3002 : Step(252): len = 728920, overlap = 260.5
+PHY-3002 : Step(253): len = 725981, overlap = 262.5
+PHY-3002 : Step(254): len = 722482, overlap = 260
+PHY-3002 : Step(255): len = 718700, overlap = 257.75
+PHY-3002 : Step(256): len = 715670, overlap = 270
+PHY-3002 : Step(257): len = 713177, overlap = 271.75
+PHY-3002 : Step(258): len = 710497, overlap = 275.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000100693
+PHY-3002 : Step(259): len = 712660, overlap = 269.75
+PHY-3002 : Step(260): len = 716929, overlap = 256.25
+PHY-3002 : Step(261): len = 718527, overlap = 247
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000201386
+PHY-3002 : Step(262): len = 727450, overlap = 234.75
+PHY-3002 : Step(263): len = 735411, overlap = 220.75
+PHY-3002 : Step(264): len = 734192, overlap = 222.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.350639s wall, 0.390625s user + 0.562500s system = 0.953125s CPU (271.8%)
+
+PHY-3001 : Trial Legalized: Len = 908318
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 665/17620.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.02882e+06, over cnt = 2866(8%), over = 4948, worst = 7
+PHY-1002 : len = 1.04374e+06, over cnt = 1986(5%), over = 3143, worst = 7
+PHY-1002 : len = 1.06894e+06, over cnt = 873(2%), over = 1319, worst = 7
+PHY-1002 : len = 1.0803e+06, over cnt = 384(1%), over = 564, worst = 6
+PHY-1002 : len = 1.09142e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.360963s wall, 3.296875s user + 0.015625s system = 3.312500s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 71.06, top5 = 61.03, top10 = 56.22, top15 = 53.26.
+PHY-3001 : End congestion estimation;  2.793602s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (134.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17442 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.839787s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171789
+PHY-3002 : Step(265): len = 865690, overlap = 77.75
+PHY-3002 : Step(266): len = 844817, overlap = 104.25
+PHY-3002 : Step(267): len = 831463, overlap = 122.75
+PHY-3002 : Step(268): len = 818961, overlap = 145.5
+PHY-3002 : Step(269): len = 812195, overlap = 153.75
+PHY-3002 : Step(270): len = 805892, overlap = 170.25
+PHY-3002 : Step(271): len = 801327, overlap = 177.5
+PHY-3002 : Step(272): len = 796513, overlap = 185.5
+PHY-3002 : Step(273): len = 792487, overlap = 194
+PHY-3002 : Step(274): len = 789291, overlap = 196
+PHY-3002 : Step(275): len = 786451, overlap = 196.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000343577
+PHY-3002 : Step(276): len = 790565, overlap = 185.75
+PHY-3002 : Step(277): len = 793059, overlap = 182.75
+PHY-3002 : Step(278): len = 795012, overlap = 185
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000561373
+PHY-3002 : Step(279): len = 799532, overlap = 179.5
+PHY-3002 : Step(280): len = 803769, overlap = 180
+PHY-3002 : Step(281): len = 806416, overlap = 174.25
+PHY-3002 : Step(282): len = 807744, overlap = 178
+PHY-3002 : Step(283): len = 808974, overlap = 176
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.083544s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (93.5%)
+
+PHY-3001 : Legalized: Len = 867305, Over = 0
+PHY-3001 : Spreading special nets. 480 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.112036s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (97.6%)
+
+PHY-3001 : 718 instances has been re-located, deltaX = 283, deltaY = 448, maxDist = 6.
+PHY-3001 : Final: Len = 877581, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73757, tnet num: 17442, tinst num: 6790, tnode num: 96366, tedge num: 123878.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.800341s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.8%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 645 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 2730/17620.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00888e+06, over cnt = 2761(7%), over = 4585, worst = 8
+PHY-1002 : len = 1.0257e+06, over cnt = 1644(4%), over = 2385, worst = 6
+PHY-1002 : len = 1.04545e+06, over cnt = 645(1%), over = 900, worst = 6
+PHY-1002 : len = 1.05744e+06, over cnt = 68(0%), over = 95, worst = 4
+PHY-1002 : len = 1.05949e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations;  2.271597s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (142.4%)
+
+PHY-1001 : Congestion index: top1 = 67.44, top5 = 57.63, top10 = 53.33, top15 = 50.60.
+PHY-1001 : End incremental global routing;  2.625725s wall, 3.531250s user + 0.031250s system = 3.562500s CPU (135.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17442 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.848157s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (101.3%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6697 has valid locations, 27 needs to be replaced
+PHY-3001 : design contains 6812 instances, 6663 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 1562 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 881007
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16093/17643.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06291e+06, over cnt = 94(0%), over = 110, worst = 5
+PHY-1002 : len = 1.06276e+06, over cnt = 50(0%), over = 52, worst = 2
+PHY-1002 : len = 1.06313e+06, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 1.06328e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.06332e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.742607s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (107.3%)
+
+PHY-1001 : Congestion index: top1 = 67.37, top5 = 57.67, top10 = 53.37, top15 = 50.64.
+PHY-3001 : End congestion estimation;  1.041827s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (105.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73952, tnet num: 17465, tinst num: 6812, tnode num: 96605, tedge num: 124139.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.805900s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (100.4%)
+
+RUN-1004 : used memory is 668 MB, reserved memory is 669 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.714167s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(284): len = 880053, overlap = 0
+PHY-3002 : Step(285): len = 879777, overlap = 0
+PHY-3002 : Step(286): len = 879584, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16080/17643.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06096e+06, over cnt = 66(0%), over = 76, worst = 5
+PHY-1002 : len = 1.06094e+06, over cnt = 29(0%), over = 29, worst = 1
+PHY-1002 : len = 1.06124e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.06126e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.577787s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (102.8%)
+
+PHY-1001 : Congestion index: top1 = 67.31, top5 = 57.65, top10 = 53.38, top15 = 50.64.
+PHY-3001 : End congestion estimation;  0.873900s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (101.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.842704s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000206373
+PHY-3002 : Step(287): len = 879564, overlap = 1.75
+PHY-3002 : Step(288): len = 879607, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005697s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 879723, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060476s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.3%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 11, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 879951, Over = 0
+PHY-3001 : End incremental placement;  5.945946s wall, 6.109375s user + 0.140625s system = 6.250000s CPU (105.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.988564s wall, 11.031250s user + 0.187500s system = 11.218750s CPU (112.3%)
+
+OPT-1001 : Current memory(MB): used = 750, reserve = 744, peak = 753.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16054/17643.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06155e+06, over cnt = 80(0%), over = 96, worst = 3
+PHY-1002 : len = 1.06166e+06, over cnt = 32(0%), over = 32, worst = 1
+PHY-1002 : len = 1.06191e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.06203e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.600023s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (109.4%)
+
+PHY-1001 : Congestion index: top1 = 67.28, top5 = 57.66, top10 = 53.39, top15 = 50.69.
+OPT-1001 : End congestion update;  0.896737s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (106.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.700764s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.3%)
+
+OPT-0007 : Start: WNS -1183 TNS -1818 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6724 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6812 instances, 6663 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 1562 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 882827, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059345s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.3%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 9, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 883205, Over = 0
+PHY-3001 : End incremental legalization;  0.371073s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (113.7%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 27 cells processed and 8646 slack improved
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.111127s wall, 2.265625s user + 0.046875s system = 2.312500s CPU (109.5%)
+
+OPT-1001 : Current memory(MB): used = 750, reserve = 744, peak = 753.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.699718s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (98.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15976/17643.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06513e+06, over cnt = 127(0%), over = 153, worst = 5
+PHY-1002 : len = 1.0651e+06, over cnt = 92(0%), over = 106, worst = 3
+PHY-1002 : len = 1.06566e+06, over cnt = 46(0%), over = 53, worst = 2
+PHY-1002 : len = 1.06643e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.06654e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.766694s wall, 0.843750s user + 0.062500s system = 0.906250s CPU (118.2%)
+
+PHY-1001 : Congestion index: top1 = 66.68, top5 = 57.58, top10 = 53.29, top15 = 50.64.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.708410s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1183 TNS -1718 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 66.241379
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1183ps with logic level 2 
+RUN-1001 :       #2 path slack -1097ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17643 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17643 nets
+OPT-1001 : End physical optimization;  16.728074s wall, 17.984375s user + 0.296875s system = 18.281250s CPU (109.3%)
+
+RUN-1003 : finish command "place" in  58.411828s wall, 84.640625s user + 6.187500s system = 90.828125s CPU (155.5%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 610 MB, peak memory is 753 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.664983s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (174.6%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 611 MB, peak memory is 753 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6814 instances
+RUN-1001 : 3334 mslices, 3329 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17643 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9972 nets have 2 pins
+RUN-1001 : 5979 nets have [3 - 5] pins
+RUN-1001 : 997 nets have [6 - 10] pins
+RUN-1001 : 293 nets have [11 - 20] pins
+RUN-1001 : 374 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73952, tnet num: 17465, tinst num: 6812, tnode num: 96605, tedge num: 124139.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.600951s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.6%)
+
+RUN-1004 : used memory is 638 MB, reserved memory is 638 MB, peak memory is 753 MB
+PHY-1001 : 3334 mslices, 3329 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[39] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994856, over cnt = 2978(8%), over = 4986, worst = 7
+PHY-1002 : len = 1.0169e+06, over cnt = 1763(5%), over = 2452, worst = 7
+PHY-1002 : len = 1.03938e+06, over cnt = 570(1%), over = 739, worst = 5
+PHY-1002 : len = 1.04988e+06, over cnt = 104(0%), over = 133, worst = 5
+PHY-1002 : len = 1.05246e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.031991s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (130.9%)
+
+PHY-1001 : Congestion index: top1 = 67.18, top5 = 57.23, top10 = 52.81, top15 = 50.07.
+PHY-1001 : End global routing;  3.349183s wall, 4.281250s user + 0.015625s system = 4.296875s CPU (128.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 721, reserve = 719, peak = 753.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 991, reserve = 988, peak = 991.
+PHY-1001 : End build detailed router design. 3.969549s wall, 3.921875s user + 0.046875s system = 3.968750s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270360, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.951178s wall, 4.921875s user + 0.000000s system = 4.921875s CPU (99.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270416, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 1.047016s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (38.8%)
+
+PHY-1001 : Current memory(MB): used = 1027, reserve = 1025, peak = 1027.
+PHY-1001 : End phase 1; 6.011152s wall, 5.343750s user + 0.000000s system = 5.343750s CPU (88.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 72% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.50705e+06, over cnt = 2199(0%), over = 2205, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1040, peak = 1044.
+PHY-1001 : End initial routed; 47.006025s wall, 72.828125s user + 0.375000s system = 73.203125s CPU (155.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16565(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.184   |  -3.936   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.216576s wall, 3.203125s user + 0.015625s system = 3.218750s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1051, peak = 1053.
+PHY-1001 : End phase 2; 50.222665s wall, 76.031250s user + 0.390625s system = 76.421875s CPU (152.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.046ns STNS -3.798ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.144560s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.3%)
+
+PHY-1022 : len = 2.50705e+06, over cnt = 2200(0%), over = 2206, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.404544s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.47058e+06, over cnt = 911(0%), over = 913, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.597365s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (126.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.46084e+06, over cnt = 166(0%), over = 166, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.850893s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (130.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.46186e+06, over cnt = 45(0%), over = 45, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.515882s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (127.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.46261e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 1.048029s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (34.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.46262e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.194878s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (96.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16565(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.046   |  -3.798   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.171305s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 724 feed throughs used by 509 nets
+PHY-1001 : End commit to database; 2.261658s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1157, reserve = 1158, peak = 1157.
+PHY-1001 : End phase 3; 12.447825s wall, 13.109375s user + 0.000000s system = 13.109375s CPU (105.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.046ns STNS -3.798ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.136238s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.8%)
+
+PHY-1022 : len = 2.46262e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.366550s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.046ns, -3.798ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16565(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.046   |  -3.798   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.238702s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 724 feed throughs used by 509 nets
+PHY-1001 : End commit to database; 2.355723s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1167, peak = 1165.
+PHY-1001 : End phase 4; 5.985375s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.46262e+06
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1170, peak = 1168.
+PHY-1001 : End export database. 0.059834s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.5%)
+
+PHY-1001 : End detail routing;  79.080320s wall, 104.843750s user + 0.437500s system = 105.281250s CPU (133.1%)
+
+RUN-1003 : finish command "route" in  85.071605s wall, 111.734375s user + 0.468750s system = 112.203125s CPU (131.9%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1096 MB, peak memory is 1168 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10210   out of  19600   52.09%
+#reg                     9529   out of  19600   48.62%
+#le                     12461
+  #lut only              2932   out of  12461   23.53%
+  #reg only              2251   out of  12461   18.06%
+  #lut&reg               7278   out of  12461   58.41%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1784
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1425
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1316
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               988
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    141
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         67
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg13_syn_197.f1                         3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_lv_en_flag/reg0_syn_28.f0                        3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P163       LVCMOS33           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12461  |9183    |1027    |9559    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |520    |431     |23      |432     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |93     |87      |4       |80      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |21     |21      |0       |15      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |5       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |759    |353     |96      |572     |0       |0       |
+|    u_ADconfig                |AD_config            |188    |112     |25      |140     |0       |0       |
+|    u_gen_sp                  |gen_sp               |256    |163     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |748    |413     |96      |552     |0       |0       |
+|    u_ADconfig                |AD_config            |179    |120     |25      |131     |0       |0       |
+|    u_gen_sp                  |gen_sp               |265    |179     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3057   |2452    |306     |2169    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |5       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |174    |133     |17      |139     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |2846   |2307    |289     |1993    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2323   |1897    |253     |1548    |22      |0       |
+|        channelPart           |channel_part_8478    |145    |140     |3       |132     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |37      |0       |0       |
+|        ram_switch            |ram_switch           |1793   |1437    |197     |1148    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |226    |199     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |16      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|          insert              |insert               |982    |653     |170     |681     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |585    |585     |0       |344     |0       |0       |
+|        read_ram_i            |read_ram             |286    |233     |44      |199     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |229    |189     |40      |156     |0       |0       |
+|          read_ram_data       |read_ram_data        |54     |41      |4       |40      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1      |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |323    |253     |36      |278     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3277   |2514    |349     |2155    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |183    |121     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |3066   |2373    |332     |1981    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2595   |2042    |290     |1583    |22      |1       |
+|        channelPart           |channel_part_8478    |241    |235     |3       |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |66     |57      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |1895   |1459    |197     |1151    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |227    |200     |27      |104     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |9       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |6       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|          insert              |insert               |1000   |597     |170     |711     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |668    |662     |0       |336     |0       |0       |
+|        read_ram_i            |read_ram_rev         |355    |260     |81      |207     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |290    |209     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |51      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9910  
+    #2         2       3879  
+    #3         3       1448  
+    #4         4       649   
+    #5        5-10     1060  
+    #6       11-50     578   
+    #7       51-100     23   
+    #8        >500      1    
+  Average     2.90           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.050757s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (173.7%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1097 MB, peak memory is 1168 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73952, tnet num: 17465, tinst num: 6812, tnode num: 96605, tedge num: 124139.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.566966s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.7%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1101 MB, peak memory is 1168 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.467480s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (100.1%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1104 MB, peak memory is 1168 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6812
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17643, pip num: 177724
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 724
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3216 valid insts, and 490526 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.488879s wall, 69.734375s user + 0.234375s system = 69.968750s CPU (667.1%)
+
+RUN-1004 : used memory is 1269 MB, reserved memory is 1265 MB, peak memory is 1384 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_152936.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_153704.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_153704.log
new file mode 100644
index 0000000..be02f6c
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_153704.log
@@ -0,0 +1,2081 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:37:04 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.108531s wall, 2.031250s user + 0.062500s system = 2.093750s CPU (99.3%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2213 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2116 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17738 instances
+RUN-0007 : 7409 luts, 9106 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20319 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13411 nets have 2 pins
+RUN-1001 : 5460 nets have [3 - 5] pins
+RUN-1001 : 1034 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 178 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     794     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3535     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17736 instances, 7409 luts, 9106 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84883, tnet num: 20141, tinst num: 17736, tnode num: 115156, tedge num: 136224.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.121602s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (100.3%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 514 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20141 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.886318s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (100.2%)
+
+PHY-3001 : Found 3482 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.12301e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17736.
+PHY-3001 : Level 1 #clusters 2020.
+PHY-3001 : End clustering;  0.124974s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (125.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.27852e+06, overlap = 492.625
+PHY-3002 : Step(2): len = 1.19046e+06, overlap = 550.312
+PHY-3002 : Step(3): len = 838423, overlap = 575.781
+PHY-3002 : Step(4): len = 770069, overlap = 597.438
+PHY-3002 : Step(5): len = 599089, overlap = 750.562
+PHY-3002 : Step(6): len = 544622, overlap = 801.75
+PHY-3002 : Step(7): len = 455170, overlap = 899.812
+PHY-3002 : Step(8): len = 425681, overlap = 918.094
+PHY-3002 : Step(9): len = 376956, overlap = 983.875
+PHY-3002 : Step(10): len = 356852, overlap = 1024.56
+PHY-3002 : Step(11): len = 316007, overlap = 1045.84
+PHY-3002 : Step(12): len = 296897, overlap = 1122.31
+PHY-3002 : Step(13): len = 266542, overlap = 1183.16
+PHY-3002 : Step(14): len = 251183, overlap = 1234.75
+PHY-3002 : Step(15): len = 219904, overlap = 1286.81
+PHY-3002 : Step(16): len = 203886, overlap = 1293.25
+PHY-3002 : Step(17): len = 182877, overlap = 1342.91
+PHY-3002 : Step(18): len = 172751, overlap = 1360.5
+PHY-3002 : Step(19): len = 157141, overlap = 1386.59
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.04153e-06
+PHY-3002 : Step(20): len = 155270, overlap = 1361.75
+PHY-3002 : Step(21): len = 178996, overlap = 1293.03
+PHY-3002 : Step(22): len = 185425, overlap = 1276.88
+PHY-3002 : Step(23): len = 188125, overlap = 1247.22
+PHY-3002 : Step(24): len = 187270, overlap = 1212.06
+PHY-3002 : Step(25): len = 187044, overlap = 1181
+PHY-3002 : Step(26): len = 183812, overlap = 1172.88
+PHY-3002 : Step(27): len = 182704, overlap = 1161.25
+PHY-3002 : Step(28): len = 180571, overlap = 1174.19
+PHY-3002 : Step(29): len = 178494, overlap = 1181.38
+PHY-3002 : Step(30): len = 176254, overlap = 1199.19
+PHY-3002 : Step(31): len = 174873, overlap = 1201.91
+PHY-3002 : Step(32): len = 173601, overlap = 1195.03
+PHY-3002 : Step(33): len = 173672, overlap = 1183.78
+PHY-3002 : Step(34): len = 173592, overlap = 1184.88
+PHY-3002 : Step(35): len = 174013, overlap = 1159.69
+PHY-3002 : Step(36): len = 173132, overlap = 1154.56
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.08307e-06
+PHY-3002 : Step(37): len = 176265, overlap = 1118.84
+PHY-3002 : Step(38): len = 188333, overlap = 1092.69
+PHY-3002 : Step(39): len = 193682, overlap = 1085.19
+PHY-3002 : Step(40): len = 200527, overlap = 1054.56
+PHY-3002 : Step(41): len = 203229, overlap = 1042.12
+PHY-3002 : Step(42): len = 203799, overlap = 1027.34
+PHY-3002 : Step(43): len = 202917, overlap = 1034.62
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.16613e-06
+PHY-3002 : Step(44): len = 211240, overlap = 1017.38
+PHY-3002 : Step(45): len = 233958, overlap = 916.156
+PHY-3002 : Step(46): len = 243950, overlap = 888.938
+PHY-3002 : Step(47): len = 249002, overlap = 863.844
+PHY-3002 : Step(48): len = 251270, overlap = 844.125
+PHY-3002 : Step(49): len = 249956, overlap = 833.375
+PHY-3002 : Step(50): len = 250030, overlap = 839.844
+PHY-3002 : Step(51): len = 249846, overlap = 809.25
+PHY-3002 : Step(52): len = 249889, overlap = 793.781
+PHY-3002 : Step(53): len = 248013, overlap = 803.812
+PHY-3002 : Step(54): len = 247720, overlap = 809.156
+PHY-3002 : Step(55): len = 245728, overlap = 800.125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.33226e-06
+PHY-3002 : Step(56): len = 263655, overlap = 764.781
+PHY-3002 : Step(57): len = 282776, overlap = 686.125
+PHY-3002 : Step(58): len = 290528, overlap = 635.031
+PHY-3002 : Step(59): len = 294787, overlap = 613.25
+PHY-3002 : Step(60): len = 294585, overlap = 598.438
+PHY-3002 : Step(61): len = 295510, overlap = 576.031
+PHY-3002 : Step(62): len = 294894, overlap = 567.312
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.66645e-05
+PHY-3002 : Step(63): len = 316190, overlap = 519.281
+PHY-3002 : Step(64): len = 335922, overlap = 465.719
+PHY-3002 : Step(65): len = 343397, overlap = 420.375
+PHY-3002 : Step(66): len = 347784, overlap = 399.25
+PHY-3002 : Step(67): len = 344587, overlap = 388.562
+PHY-3002 : Step(68): len = 345469, overlap = 385.906
+PHY-3002 : Step(69): len = 342860, overlap = 415.719
+PHY-3002 : Step(70): len = 341988, overlap = 433.438
+PHY-3002 : Step(71): len = 341664, overlap = 422.75
+PHY-3002 : Step(72): len = 340422, overlap = 422.062
+PHY-3002 : Step(73): len = 339267, overlap = 425.344
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.33291e-05
+PHY-3002 : Step(74): len = 359702, overlap = 386.281
+PHY-3002 : Step(75): len = 372436, overlap = 359.969
+PHY-3002 : Step(76): len = 372289, overlap = 342.906
+PHY-3002 : Step(77): len = 372270, overlap = 331.812
+PHY-3002 : Step(78): len = 373664, overlap = 330.031
+PHY-3002 : Step(79): len = 376439, overlap = 313.344
+PHY-3002 : Step(80): len = 375326, overlap = 316.031
+PHY-3002 : Step(81): len = 377339, overlap = 292.594
+PHY-3002 : Step(82): len = 381823, overlap = 293.281
+PHY-3002 : Step(83): len = 383216, overlap = 294.781
+PHY-3002 : Step(84): len = 380798, overlap = 307.781
+PHY-3002 : Step(85): len = 380563, overlap = 316
+PHY-3002 : Step(86): len = 381259, overlap = 313.938
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.66581e-05
+PHY-3002 : Step(87): len = 402340, overlap = 291.938
+PHY-3002 : Step(88): len = 416426, overlap = 276
+PHY-3002 : Step(89): len = 416286, overlap = 272.75
+PHY-3002 : Step(90): len = 418102, overlap = 283.625
+PHY-3002 : Step(91): len = 421096, overlap = 261.344
+PHY-3002 : Step(92): len = 422578, overlap = 241.094
+PHY-3002 : Step(93): len = 418901, overlap = 254.719
+PHY-3002 : Step(94): len = 418951, overlap = 250.125
+PHY-3002 : Step(95): len = 418857, overlap = 253.562
+PHY-3002 : Step(96): len = 419458, overlap = 254.5
+PHY-3002 : Step(97): len = 417787, overlap = 256.656
+PHY-3002 : Step(98): len = 417716, overlap = 254.219
+PHY-3002 : Step(99): len = 418970, overlap = 263.219
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000133316
+PHY-3002 : Step(100): len = 436863, overlap = 242.906
+PHY-3002 : Step(101): len = 447816, overlap = 228.531
+PHY-3002 : Step(102): len = 446644, overlap = 221.531
+PHY-3002 : Step(103): len = 448024, overlap = 218.719
+PHY-3002 : Step(104): len = 451995, overlap = 216.531
+PHY-3002 : Step(105): len = 455794, overlap = 206.781
+PHY-3002 : Step(106): len = 455646, overlap = 208
+PHY-3002 : Step(107): len = 457143, overlap = 207.031
+PHY-3002 : Step(108): len = 458471, overlap = 209.094
+PHY-3002 : Step(109): len = 459934, overlap = 200.875
+PHY-3002 : Step(110): len = 457780, overlap = 200.594
+PHY-3002 : Step(111): len = 457131, overlap = 198.031
+PHY-3002 : Step(112): len = 457522, overlap = 188.625
+PHY-3002 : Step(113): len = 457142, overlap = 199.188
+PHY-3002 : Step(114): len = 455358, overlap = 197.594
+PHY-3002 : Step(115): len = 455442, overlap = 203.656
+PHY-3002 : Step(116): len = 455881, overlap = 207.438
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000266632
+PHY-3002 : Step(117): len = 467640, overlap = 211.344
+PHY-3002 : Step(118): len = 475476, overlap = 202.5
+PHY-3002 : Step(119): len = 475142, overlap = 204.844
+PHY-3002 : Step(120): len = 475333, overlap = 208.312
+PHY-3002 : Step(121): len = 477209, overlap = 208.5
+PHY-3002 : Step(122): len = 479003, overlap = 201.75
+PHY-3002 : Step(123): len = 478684, overlap = 202.5
+PHY-3002 : Step(124): len = 479331, overlap = 204.156
+PHY-3002 : Step(125): len = 481274, overlap = 204.844
+PHY-3002 : Step(126): len = 482914, overlap = 194.906
+PHY-3002 : Step(127): len = 481896, overlap = 193.688
+PHY-3002 : Step(128): len = 481881, overlap = 197.125
+PHY-3002 : Step(129): len = 482879, overlap = 184.844
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000533265
+PHY-3002 : Step(130): len = 491247, overlap = 182.719
+PHY-3002 : Step(131): len = 499531, overlap = 178.125
+PHY-3002 : Step(132): len = 502139, overlap = 179.656
+PHY-3002 : Step(133): len = 505008, overlap = 162.031
+PHY-3002 : Step(134): len = 508322, overlap = 160.312
+PHY-3002 : Step(135): len = 510163, overlap = 160
+PHY-3002 : Step(136): len = 509622, overlap = 161.406
+PHY-3002 : Step(137): len = 509585, overlap = 159.156
+PHY-3002 : Step(138): len = 509780, overlap = 158.156
+PHY-3002 : Step(139): len = 508674, overlap = 161.531
+PHY-3002 : Step(140): len = 508318, overlap = 166.219
+PHY-3002 : Step(141): len = 509055, overlap = 171.281
+PHY-3002 : Step(142): len = 509398, overlap = 170
+PHY-3002 : Step(143): len = 509722, overlap = 166.938
+PHY-3002 : Step(144): len = 509764, overlap = 166.875
+PHY-3002 : Step(145): len = 509367, overlap = 165.281
+PHY-3002 : Step(146): len = 509335, overlap = 158.406
+PHY-3002 : Step(147): len = 509431, overlap = 155.656
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00102304
+PHY-3002 : Step(148): len = 512789, overlap = 156.875
+PHY-3002 : Step(149): len = 516080, overlap = 155.344
+PHY-3002 : Step(150): len = 517027, overlap = 156.375
+PHY-3002 : Step(151): len = 517664, overlap = 150.5
+PHY-3002 : Step(152): len = 518501, overlap = 153.25
+PHY-3002 : Step(153): len = 519043, overlap = 150.281
+PHY-3002 : Step(154): len = 518881, overlap = 145.438
+PHY-3002 : Step(155): len = 519574, overlap = 136.438
+PHY-3002 : Step(156): len = 521002, overlap = 141.719
+PHY-3002 : Step(157): len = 521319, overlap = 143.281
+PHY-3002 : Step(158): len = 520853, overlap = 143.562
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00176508
+PHY-3002 : Step(159): len = 523903, overlap = 138.656
+PHY-3002 : Step(160): len = 528826, overlap = 136.688
+PHY-3002 : Step(161): len = 529759, overlap = 136.125
+PHY-3002 : Step(162): len = 530386, overlap = 130.531
+PHY-3002 : Step(163): len = 531543, overlap = 130.312
+PHY-3002 : Step(164): len = 531990, overlap = 131.656
+PHY-3002 : Step(165): len = 531596, overlap = 130.781
+PHY-3002 : Step(166): len = 531636, overlap = 134.156
+PHY-3002 : Step(167): len = 532594, overlap = 135.344
+PHY-3002 : Step(168): len = 532823, overlap = 132.906
+PHY-3002 : Step(169): len = 532450, overlap = 131.062
+PHY-3002 : Step(170): len = 532360, overlap = 128.75
+PHY-3002 : Step(171): len = 533229, overlap = 125.719
+PHY-3002 : Step(172): len = 533847, overlap = 125.312
+PHY-3002 : Step(173): len = 533649, overlap = 125.969
+PHY-3002 : Step(174): len = 533629, overlap = 125.531
+PHY-3002 : Step(175): len = 534136, overlap = 124.656
+PHY-3002 : Step(176): len = 534854, overlap = 127.281
+PHY-3002 : Step(177): len = 534666, overlap = 131.031
+PHY-3002 : Step(178): len = 534723, overlap = 129.688
+PHY-3002 : Step(179): len = 535300, overlap = 130.438
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00290634
+PHY-3002 : Step(180): len = 536314, overlap = 132.125
+PHY-3002 : Step(181): len = 539366, overlap = 129.875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015252s wall, 0.000000s user + 0.015625s system = 0.015625s CPU (102.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20319.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 685080, over cnt = 1556(4%), over = 7312, worst = 54
+PHY-1001 : End global iterations;  0.708973s wall, 0.984375s user + 0.109375s system = 1.093750s CPU (154.3%)
+
+PHY-1001 : Congestion index: top1 = 82.20, top5 = 60.84, top10 = 51.99, top15 = 46.32.
+PHY-3001 : End congestion estimation;  0.924725s wall, 1.203125s user + 0.109375s system = 1.312500s CPU (141.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20141 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.829077s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.23505e-05
+PHY-3002 : Step(182): len = 622360, overlap = 72.4688
+PHY-3002 : Step(183): len = 626626, overlap = 62.0938
+PHY-3002 : Step(184): len = 618272, overlap = 65
+PHY-3002 : Step(185): len = 613723, overlap = 60.1875
+PHY-3002 : Step(186): len = 615913, overlap = 65.2812
+PHY-3002 : Step(187): len = 631215, overlap = 58.125
+PHY-3002 : Step(188): len = 638650, overlap = 53.4688
+PHY-3002 : Step(189): len = 638009, overlap = 51.6562
+PHY-3002 : Step(190): len = 639761, overlap = 58.25
+PHY-3002 : Step(191): len = 646376, overlap = 60.3125
+PHY-3002 : Step(192): len = 655470, overlap = 52.0312
+PHY-3002 : Step(193): len = 659565, overlap = 45.9375
+PHY-3002 : Step(194): len = 663170, overlap = 43.0625
+PHY-3002 : Step(195): len = 667052, overlap = 39.2188
+PHY-3002 : Step(196): len = 667854, overlap = 34.75
+PHY-3002 : Step(197): len = 668493, overlap = 41.4688
+PHY-3002 : Step(198): len = 671343, overlap = 40.0938
+PHY-3002 : Step(199): len = 670479, overlap = 43.5938
+PHY-3002 : Step(200): len = 670030, overlap = 40.8438
+PHY-3002 : Step(201): len = 669080, overlap = 37.2188
+PHY-3002 : Step(202): len = 667185, overlap = 34.3125
+PHY-3002 : Step(203): len = 666362, overlap = 33.8438
+PHY-3002 : Step(204): len = 664703, overlap = 35.6875
+PHY-3002 : Step(205): len = 663314, overlap = 36.75
+PHY-3002 : Step(206): len = 662494, overlap = 37.4375
+PHY-3002 : Step(207): len = 660833, overlap = 42.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000184701
+PHY-3002 : Step(208): len = 663007, overlap = 42.3438
+PHY-3002 : Step(209): len = 667886, overlap = 37.9688
+PHY-3002 : Step(210): len = 673892, overlap = 36.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000369402
+PHY-3002 : Step(211): len = 676377, overlap = 39.0938
+PHY-3002 : Step(212): len = 690007, overlap = 39.6875
+PHY-3002 : Step(213): len = 704088, overlap = 39.75
+PHY-3002 : Step(214): len = 701027, overlap = 37.9062
+PHY-3002 : Step(215): len = 700500, overlap = 38.375
+PHY-3002 : Step(216): len = 700476, overlap = 37.375
+PHY-3002 : Step(217): len = 700730, overlap = 36.4375
+PHY-3002 : Step(218): len = 703818, overlap = 39.5312
+PHY-3002 : Step(219): len = 705019, overlap = 39.4375
+PHY-3002 : Step(220): len = 705865, overlap = 38.6875
+PHY-3002 : Step(221): len = 706049, overlap = 38.8125
+PHY-3002 : Step(222): len = 706359, overlap = 35.875
+PHY-3002 : Step(223): len = 708832, overlap = 33.5312
+PHY-3002 : Step(224): len = 707010, overlap = 35.3438
+PHY-3002 : Step(225): len = 706730, overlap = 38.0625
+PHY-3002 : Step(226): len = 706278, overlap = 38.125
+PHY-3002 : Step(227): len = 704800, overlap = 37.4375
+PHY-3002 : Step(228): len = 703831, overlap = 40.875
+PHY-3002 : Step(229): len = 702419, overlap = 42.625
+PHY-3002 : Step(230): len = 703563, overlap = 41.4062
+PHY-3002 : Step(231): len = 703348, overlap = 42.9688
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000695969
+PHY-3002 : Step(232): len = 706555, overlap = 42.6562
+PHY-3002 : Step(233): len = 714077, overlap = 42.2812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00112608
+PHY-3002 : Step(234): len = 716101, overlap = 39.25
+PHY-3002 : Step(235): len = 725426, overlap = 36.7812
+PHY-3002 : Step(236): len = 737460, overlap = 36.3438
+PHY-3002 : Step(237): len = 738687, overlap = 37.9688
+PHY-3002 : Step(238): len = 740073, overlap = 36.9375
+PHY-3002 : Step(239): len = 741499, overlap = 39.875
+PHY-3002 : Step(240): len = 743615, overlap = 39.5312
+PHY-3002 : Step(241): len = 743947, overlap = 39.9688
+PHY-3002 : Step(242): len = 746313, overlap = 40.1562
+PHY-3002 : Step(243): len = 746932, overlap = 38.5625
+PHY-3002 : Step(244): len = 746744, overlap = 37.4062
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00192502
+PHY-3002 : Step(245): len = 747332, overlap = 37.8438
+PHY-3002 : Step(246): len = 751522, overlap = 40.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 45/20319.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 823416, over cnt = 2697(7%), over = 14954, worst = 66
+PHY-1001 : End global iterations;  1.270283s wall, 1.843750s user + 0.062500s system = 1.906250s CPU (150.1%)
+
+PHY-1001 : Congestion index: top1 = 116.92, top5 = 83.92, top10 = 70.18, top15 = 62.14.
+PHY-3001 : End congestion estimation;  1.534749s wall, 2.078125s user + 0.093750s system = 2.171875s CPU (141.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20141 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.865353s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117596
+PHY-3002 : Step(247): len = 747016, overlap = 283.312
+PHY-3002 : Step(248): len = 745442, overlap = 227.156
+PHY-3002 : Step(249): len = 736381, overlap = 201.531
+PHY-3002 : Step(250): len = 730582, overlap = 179.5
+PHY-3002 : Step(251): len = 727443, overlap = 154.219
+PHY-3002 : Step(252): len = 722405, overlap = 130.969
+PHY-3002 : Step(253): len = 719053, overlap = 122.531
+PHY-3002 : Step(254): len = 714543, overlap = 127.625
+PHY-3002 : Step(255): len = 710247, overlap = 114.656
+PHY-3002 : Step(256): len = 705269, overlap = 113.125
+PHY-3002 : Step(257): len = 700686, overlap = 109.844
+PHY-3002 : Step(258): len = 697030, overlap = 105
+PHY-3002 : Step(259): len = 692361, overlap = 106.469
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000235192
+PHY-3002 : Step(260): len = 693368, overlap = 102.219
+PHY-3002 : Step(261): len = 695400, overlap = 97.3438
+PHY-3002 : Step(262): len = 697789, overlap = 89.75
+PHY-3002 : Step(263): len = 698686, overlap = 89.25
+PHY-3002 : Step(264): len = 698913, overlap = 89.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000470384
+PHY-3002 : Step(265): len = 700344, overlap = 84.0938
+PHY-3002 : Step(266): len = 704133, overlap = 81.2812
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84883, tnet num: 20141, tinst num: 17736, tnode num: 115156, tedge num: 136224.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.419588s wall, 1.359375s user + 0.062500s system = 1.421875s CPU (100.2%)
+
+RUN-1004 : used memory is 582 MB, reserved memory is 564 MB, peak memory is 717 MB
+OPT-1001 : Total overflow 410.03 peak overflow 4.12
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 532/20319.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 798168, over cnt = 3033(8%), over = 11660, worst = 64
+PHY-1001 : End global iterations;  1.383503s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (134.4%)
+
+PHY-1001 : Congestion index: top1 = 87.48, top5 = 65.17, top10 = 56.31, top15 = 51.65.
+PHY-1001 : End incremental global routing;  1.704459s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (128.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20141 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.228501s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.5%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17601 has valid locations, 330 needs to be replaced
+PHY-3001 : design contains 18016 instances, 7507 luts, 9288 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6022 pins
+PHY-3001 : Found 3512 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 726024
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16684/20599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 814632, over cnt = 3106(8%), over = 11825, worst = 64
+PHY-1001 : End global iterations;  0.222366s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (133.5%)
+
+PHY-1001 : Congestion index: top1 = 87.18, top5 = 65.35, top10 = 56.73, top15 = 52.15.
+PHY-3001 : End congestion estimation;  0.462249s wall, 0.531250s user + 0.015625s system = 0.546875s CPU (118.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86017, tnet num: 20421, tinst num: 18016, tnode num: 116857, tedge num: 137932.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.442916s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (99.6%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 617 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.369482s wall, 2.328125s user + 0.031250s system = 2.359375s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(267): len = 724850, overlap = 1.0625
+PHY-3002 : Step(268): len = 724291, overlap = 1.125
+PHY-3002 : Step(269): len = 724174, overlap = 1.25
+PHY-3002 : Step(270): len = 723875, overlap = 1.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16774/20599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812096, over cnt = 3128(8%), over = 11930, worst = 64
+PHY-1001 : End global iterations;  0.205254s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (121.8%)
+
+PHY-1001 : Congestion index: top1 = 87.82, top5 = 65.86, top10 = 57.16, top15 = 52.43.
+PHY-3001 : End congestion estimation;  0.458890s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (109.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.923543s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (101.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000356704
+PHY-3002 : Step(271): len = 723835, overlap = 83.7812
+PHY-3002 : Step(272): len = 723894, overlap = 83.4062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000713408
+PHY-3002 : Step(273): len = 723942, overlap = 83.5312
+PHY-3002 : Step(274): len = 724626, overlap = 83.625
+PHY-3001 : Final: Len = 724626, Over = 83.625
+PHY-3001 : End incremental placement;  4.845326s wall, 5.343750s user + 0.312500s system = 5.656250s CPU (116.7%)
+
+OPT-1001 : Total overflow 415.97 peak overflow 4.12
+OPT-1001 : End high-fanout net optimization;  8.467903s wall, 9.390625s user + 0.312500s system = 9.703125s CPU (114.6%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 712, peak = 742.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16733/20599.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 815160, over cnt = 3095(8%), over = 10975, worst = 64
+PHY-1002 : len = 874056, over cnt = 2138(6%), over = 5452, worst = 45
+PHY-1002 : len = 923504, over cnt = 693(1%), over = 1394, worst = 24
+PHY-1002 : len = 934784, over cnt = 267(0%), over = 565, worst = 22
+PHY-1002 : len = 943752, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.013336s wall, 2.859375s user + 0.015625s system = 2.875000s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 65.39, top5 = 56.01, top10 = 51.49, top15 = 48.61.
+OPT-1001 : End congestion update;  2.268126s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (137.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20421 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.787820s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (101.1%)
+
+OPT-0007 : Start: WNS -968 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1478 NUM_FEPS 2 with 72 cells processed and 8100 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1478 NUM_FEPS 2 with 29 cells processed and 2366 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1478 NUM_FEPS 2 with 6 cells processed and 400 slack improved
+OPT-1001 : End global optimization;  3.101169s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (128.0%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 696, peak = 742.
+OPT-1001 : End physical optimization;  13.592231s wall, 15.406250s user + 0.390625s system = 15.796875s CPU (116.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7507 LUT to BLE ...
+SYN-4008 : Packed 7507 LUT and 3132 SEQ to BLE.
+SYN-4003 : Packing 6156 remaining SEQ's ...
+SYN-4005 : Packed 3949 SEQ with LUT/SLICE
+SYN-4006 : 732 single LUT's are left
+SYN-4006 : 2207 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9714/13445 primitive instances ...
+PHY-3001 : End packing;  1.541987s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6738 instances
+RUN-1001 : 3295 mslices, 3295 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17595 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10062 nets have 2 pins
+RUN-1001 : 5704 nets have [3 - 5] pins
+RUN-1001 : 1147 nets have [6 - 10] pins
+RUN-1001 : 308 nets have [11 - 20] pins
+RUN-1001 : 342 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6736 instances, 6590 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3550 pins
+PHY-3001 : Found 1553 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 736038, Over = 250.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7299/17595.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 889016, over cnt = 2033(5%), over = 3414, worst = 8
+PHY-1002 : len = 896272, over cnt = 1395(3%), over = 2106, worst = 7
+PHY-1002 : len = 911216, over cnt = 604(1%), over = 828, worst = 7
+PHY-1002 : len = 918840, over cnt = 292(0%), over = 397, worst = 4
+PHY-1002 : len = 926368, over cnt = 8(0%), over = 8, worst = 1
+PHY-1001 : End global iterations;  1.721902s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (141.6%)
+
+PHY-1001 : Congestion index: top1 = 63.62, top5 = 54.96, top10 = 50.51, top15 = 47.44.
+PHY-3001 : End congestion estimation;  2.106204s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (134.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73696, tnet num: 17417, tinst num: 6736, tnode num: 96123, tedge num: 123691.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.585031s wall, 1.562500s user + 0.015625s system = 1.578125s CPU (99.6%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 615 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17417 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.481778s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.92645e-05
+PHY-3002 : Step(275): len = 724482, overlap = 240
+PHY-3002 : Step(276): len = 717781, overlap = 246.5
+PHY-3002 : Step(277): len = 713192, overlap = 246.25
+PHY-3002 : Step(278): len = 710686, overlap = 249.75
+PHY-3002 : Step(279): len = 708830, overlap = 252
+PHY-3002 : Step(280): len = 706347, overlap = 259.25
+PHY-3002 : Step(281): len = 702872, overlap = 262.75
+PHY-3002 : Step(282): len = 699168, overlap = 256.25
+PHY-3002 : Step(283): len = 694624, overlap = 266.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.85291e-05
+PHY-3002 : Step(284): len = 697871, overlap = 255.75
+PHY-3002 : Step(285): len = 702427, overlap = 243.5
+PHY-3002 : Step(286): len = 703916, overlap = 243.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000197058
+PHY-3002 : Step(287): len = 710814, overlap = 225
+PHY-3002 : Step(288): len = 717739, overlap = 213.5
+PHY-3002 : Step(289): len = 718551, overlap = 214
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000394116
+PHY-3002 : Step(290): len = 726075, overlap = 207
+PHY-3002 : Step(291): len = 739203, overlap = 198
+PHY-3002 : Step(292): len = 739033, overlap = 193.5
+PHY-3002 : Step(293): len = 738720, overlap = 190
+PHY-3002 : Step(294): len = 739861, overlap = 197
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.345869s wall, 0.437500s user + 0.515625s system = 0.953125s CPU (275.6%)
+
+PHY-3001 : Trial Legalized: Len = 936428
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 574/17595.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0609e+06, over cnt = 2842(8%), over = 4724, worst = 8
+PHY-1002 : len = 1.0763e+06, over cnt = 1830(5%), over = 2739, worst = 8
+PHY-1002 : len = 1.09826e+06, over cnt = 732(2%), over = 1031, worst = 8
+PHY-1002 : len = 1.11192e+06, over cnt = 208(0%), over = 273, worst = 4
+PHY-1002 : len = 1.11602e+06, over cnt = 22(0%), over = 24, worst = 2
+PHY-1001 : End global iterations;  2.514224s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (138.0%)
+
+PHY-1001 : Congestion index: top1 = 65.71, top5 = 58.86, top10 = 54.74, top15 = 51.99.
+PHY-3001 : End congestion estimation;  2.956562s wall, 3.921875s user + 0.000000s system = 3.921875s CPU (132.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17417 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.858790s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000170514
+PHY-3002 : Step(295): len = 887590, overlap = 68
+PHY-3002 : Step(296): len = 865400, overlap = 89.5
+PHY-3002 : Step(297): len = 848363, overlap = 109.5
+PHY-3002 : Step(298): len = 832499, overlap = 131.75
+PHY-3002 : Step(299): len = 820248, overlap = 150.25
+PHY-3002 : Step(300): len = 811122, overlap = 168.75
+PHY-3002 : Step(301): len = 802948, overlap = 173.75
+PHY-3002 : Step(302): len = 797198, overlap = 182.5
+PHY-3002 : Step(303): len = 792356, overlap = 187
+PHY-3002 : Step(304): len = 788590, overlap = 180.25
+PHY-3002 : Step(305): len = 785514, overlap = 187.25
+PHY-3002 : Step(306): len = 782868, overlap = 187.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000341027
+PHY-3002 : Step(307): len = 787981, overlap = 180.75
+PHY-3002 : Step(308): len = 791299, overlap = 179
+PHY-3002 : Step(309): len = 793441, overlap = 176.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000594019
+PHY-3002 : Step(310): len = 799839, overlap = 169
+PHY-3002 : Step(311): len = 802756, overlap = 170.75
+PHY-3002 : Step(312): len = 804716, overlap = 166
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.082759s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (94.4%)
+
+PHY-3001 : Legalized: Len = 878136, Over = 0
+PHY-3001 : Spreading special nets. 403 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.107546s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (87.2%)
+
+PHY-3001 : 614 instances has been re-located, deltaX = 233, deltaY = 425, maxDist = 8.
+PHY-3001 : Final: Len = 889832, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73696, tnet num: 17417, tinst num: 6739, tnode num: 96123, tedge num: 123691.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.847287s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (99.8%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 646 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3220/17595.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.02289e+06, over cnt = 2628(7%), over = 4317, worst = 6
+PHY-1002 : len = 1.03623e+06, over cnt = 1736(4%), over = 2551, worst = 6
+PHY-1002 : len = 1.0519e+06, over cnt = 846(2%), over = 1192, worst = 6
+PHY-1002 : len = 1.0587e+06, over cnt = 553(1%), over = 743, worst = 6
+PHY-1002 : len = 1.06636e+06, over cnt = 188(0%), over = 263, worst = 5
+PHY-1001 : End global iterations;  2.237838s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (141.7%)
+
+PHY-1001 : Congestion index: top1 = 63.25, top5 = 56.96, top10 = 53.23, top15 = 50.57.
+PHY-1001 : End incremental global routing;  2.605107s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (136.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17417 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.861334s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.8%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6648 has valid locations, 12 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3615 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 891120
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16117/17604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06744e+06, over cnt = 234(0%), over = 312, worst = 5
+PHY-1002 : len = 1.06833e+06, over cnt = 90(0%), over = 107, worst = 4
+PHY-1002 : len = 1.069e+06, over cnt = 30(0%), over = 36, worst = 3
+PHY-1002 : len = 1.06942e+06, over cnt = 14(0%), over = 16, worst = 3
+PHY-1002 : len = 1.06975e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.819834s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 63.19, top5 = 56.88, top10 = 53.18, top15 = 50.53.
+PHY-3001 : End congestion estimation;  1.133753s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (106.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73777, tnet num: 17426, tinst num: 6748, tnode num: 96224, tedge num: 123795.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.804540s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (99.6%)
+
+RUN-1004 : used memory is 668 MB, reserved memory is 669 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.673926s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(313): len = 890711, overlap = 0
+PHY-3002 : Step(314): len = 890464, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16109/17604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06901e+06, over cnt = 26(0%), over = 35, worst = 5
+PHY-1002 : len = 1.0691e+06, over cnt = 7(0%), over = 8, worst = 2
+PHY-1002 : len = 1.06921e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.06922e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.599436s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (101.7%)
+
+PHY-1001 : Congestion index: top1 = 63.19, top5 = 56.88, top10 = 53.19, top15 = 50.52.
+PHY-3001 : End congestion estimation;  0.913507s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.852254s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000652211
+PHY-3002 : Step(315): len = 890449, overlap = 1
+PHY-3002 : Step(316): len = 890461, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005447s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (286.8%)
+
+PHY-3001 : Legalized: Len = 890534, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.056935s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (109.8%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 890586, Over = 0
+PHY-3001 : End incremental placement;  6.023911s wall, 6.015625s user + 0.093750s system = 6.109375s CPU (101.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.974409s wall, 10.890625s user + 0.109375s system = 11.000000s CPU (110.3%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 740, peak = 752.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16099/17604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06908e+06, over cnt = 22(0%), over = 30, worst = 3
+PHY-1002 : len = 1.0692e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.06926e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.426901s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (109.8%)
+
+PHY-1001 : Congestion index: top1 = 63.19, top5 = 56.88, top10 = 53.19, top15 = 50.52.
+OPT-1001 : End congestion update;  0.732096s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (104.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.719636s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1436 TNS -2321 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3615 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 892807, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061730s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%)
+
+PHY-3001 : 27 instances has been re-located, deltaX = 9, deltaY = 24, maxDist = 3.
+PHY-3001 : Final: Len = 893037, Over = 0
+PHY-3001 : End incremental legalization;  0.375150s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (112.5%)
+
+OPT-0007 : Iter 1: improved WNS -986 TNS -1521 NUM_FEPS 2 with 34 cells processed and 10150 slack improved
+OPT-0007 : Iter 2: improved WNS -986 TNS -1521 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.976437s wall, 2.046875s user + 0.015625s system = 2.062500s CPU (104.4%)
+
+OPT-1001 : Current memory(MB): used = 746, reserve = 739, peak = 752.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.711546s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (96.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15952/17604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07149e+06, over cnt = 111(0%), over = 129, worst = 3
+PHY-1002 : len = 1.07164e+06, over cnt = 54(0%), over = 55, worst = 2
+PHY-1002 : len = 1.07206e+06, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 1.07223e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.07239e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.862673s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (106.9%)
+
+PHY-1001 : Congestion index: top1 = 62.93, top5 = 56.83, top10 = 53.14, top15 = 50.49.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.702206s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -986 TNS -1621 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 62.517241
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -986ps with logic level 2 
+RUN-1001 :       #2 path slack -940ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 17604 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17604 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3615 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 893037, Over = 0
+PHY-3001 : End spreading;  0.056738s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.2%)
+
+PHY-3001 : Final: Len = 893037, Over = 0
+PHY-3001 : End incremental legalization;  0.404539s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (96.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.722470s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.5%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16129/17604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07239e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.130638s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.6%)
+
+PHY-1001 : Congestion index: top1 = 62.93, top5 = 56.83, top10 = 53.14, top15 = 50.49.
+OPT-1001 : End congestion update;  0.432183s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.709236s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.1%)
+
+OPT-0007 : Start: WNS -986 TNS -1621 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3615 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 893047, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.055209s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (84.9%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 893113, Over = 0
+PHY-3001 : End incremental legalization;  0.362884s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (120.6%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1571 NUM_FEPS 2 with 5 cells processed and 450 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1571 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.620370s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (105.1%)
+
+OPT-1001 : Current memory(MB): used = 746, reserve = 740, peak = 752.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16102/17604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07243e+06, over cnt = 21(0%), over = 24, worst = 2
+PHY-1002 : len = 1.0724e+06, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 1.07249e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.437597s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.0%)
+
+PHY-1001 : Congestion index: top1 = 62.87, top5 = 56.79, top10 = 53.10, top15 = 50.46.
+OPT-1001 : End congestion update;  0.746552s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.742875s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.9%)
+
+OPT-0007 : Start: WNS -1036 TNS -1671 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3615 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 893057, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059714s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 893113, Over = 0
+PHY-3001 : End incremental legalization;  0.378297s wall, 0.546875s user + 0.015625s system = 0.562500s CPU (148.7%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1571 NUM_FEPS 2 with 1 cells processed and 100 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3615 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 893057, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.055980s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (83.7%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 893113, Over = 0
+PHY-3001 : End incremental legalization;  0.393801s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.2%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1571 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -936 TNS -1571 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  2.546436s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (111.7%)
+
+OPT-1001 : Current memory(MB): used = 746, reserve = 740, peak = 752.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.706595s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 746, reserve = 740, peak = 752.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.711307s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.8%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16129/17604.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07249e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.127899s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.7%)
+
+PHY-1001 : Congestion index: top1 = 62.87, top5 = 56.79, top10 = 53.10, top15 = 50.46.
+RUN-1001 : End congestion update;  0.434225s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.8%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.148784s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.3%)
+
+OPT-1001 : Current memory(MB): used = 746, reserve = 740, peak = 752.
+OPT-1001 : End physical optimization;  24.027434s wall, 25.281250s user + 0.250000s system = 25.531250s CPU (106.3%)
+
+RUN-1003 : finish command "place" in  67.456010s wall, 101.609375s user + 6.718750s system = 108.328125s CPU (160.6%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 607 MB, peak memory is 752 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.685426s wall, 2.906250s user + 0.015625s system = 2.921875s CPU (173.4%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 608 MB, peak memory is 752 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6750 instances
+RUN-1001 : 3295 mslices, 3304 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17604 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10058 nets have 2 pins
+RUN-1001 : 5708 nets have [3 - 5] pins
+RUN-1001 : 1149 nets have [6 - 10] pins
+RUN-1001 : 310 nets have [11 - 20] pins
+RUN-1001 : 349 nets have [21 - 99] pins
+RUN-1001 : 10 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73777, tnet num: 17426, tinst num: 6748, tnode num: 96224, tedge num: 123795.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.584729s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.6%)
+
+RUN-1004 : used memory is 634 MB, reserved memory is 636 MB, peak memory is 752 MB
+PHY-1001 : 3295 mslices, 3304 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00584e+06, over cnt = 2837(8%), over = 4693, worst = 7
+PHY-1002 : len = 1.02265e+06, over cnt = 1806(5%), over = 2631, worst = 7
+PHY-1002 : len = 1.04185e+06, over cnt = 754(2%), over = 1089, worst = 7
+PHY-1002 : len = 1.05894e+06, over cnt = 25(0%), over = 27, worst = 2
+PHY-1002 : len = 1.05965e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.972404s wall, 4.000000s user + 0.000000s system = 4.000000s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 62.33, top5 = 56.36, top10 = 52.66, top15 = 50.18.
+PHY-1001 : End global routing;  3.329277s wall, 4.343750s user + 0.015625s system = 4.359375s CPU (130.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 721, reserve = 719, peak = 752.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 996, reserve = 995, peak = 996.
+PHY-1001 : End build detailed router design. 3.952104s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267872, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.404469s wall, 5.390625s user + 0.000000s system = 5.390625s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267928, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.434202s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.2%)
+
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1031, peak = 1030.
+PHY-1001 : End phase 1; 5.850064s wall, 5.828125s user + 0.000000s system = 5.828125s CPU (99.6%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.55254e+06, over cnt = 1964(0%), over = 1967, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1043, peak = 1047.
+PHY-1001 : End initial routed; 43.380814s wall, 73.171875s user + 0.562500s system = 73.734375s CPU (170.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16527(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.011   |  -4.181   |   3   
+RUN-1001 :   Hold   |   0.076   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.175924s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1050, peak = 1053.
+PHY-1001 : End phase 2; 46.556803s wall, 76.343750s user + 0.562500s system = 76.906250s CPU (165.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.882ns STNS -3.923ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.137563s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1022 : len = 2.55254e+06, over cnt = 1965(0%), over = 1968, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.398454s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.5097e+06, over cnt = 797(0%), over = 798, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.338970s wall, 3.718750s user + 0.000000s system = 3.718750s CPU (159.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50374e+06, over cnt = 147(0%), over = 147, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.190373s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (126.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50373e+06, over cnt = 29(0%), over = 29, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.513554s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (103.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50378e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.304308s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.303191s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.1%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.221399s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.9%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.319007s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (98.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.167854s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.171736s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.189291s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.272605s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.352816s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.9%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.172099s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.50402e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.165525s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16527(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.882   |  -3.923   |   3   
+RUN-1001 :   Hold   |   0.076   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.193560s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 629 feed throughs used by 478 nets
+PHY-1001 : End commit to database; 2.304765s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1159, peak = 1159.
+PHY-1001 : End phase 3; 12.962365s wall, 14.718750s user + 0.000000s system = 14.718750s CPU (113.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.882ns STNS -3.923ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.146203s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.2%)
+
+PHY-1022 : len = 2.50402e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.383813s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.882ns, -3.923ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50398e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.161263s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16527(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.882   |  -3.923   |   3   
+RUN-1001 :   Hold   |   0.076   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.192645s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 629 feed throughs used by 478 nets
+PHY-1001 : End commit to database; 2.365479s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1169, peak = 1168.
+PHY-1001 : End phase 4; 6.148890s wall, 6.125000s user + 0.000000s system = 6.125000s CPU (99.6%)
+
+PHY-1003 : Routed, final wirelength = 2.50398e+06
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1171, peak = 1170.
+PHY-1001 : End export database. 0.061124s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.3%)
+
+PHY-1001 : End detail routing;  75.916790s wall, 107.390625s user + 0.593750s system = 107.984375s CPU (142.2%)
+
+RUN-1003 : finish command "route" in  81.884099s wall, 114.375000s user + 0.609375s system = 114.984375s CPU (140.4%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1094 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10229   out of  19600   52.19%
+#reg                     9426   out of  19600   48.09%
+#le                     12346
+  #lut only              2920   out of  12346   23.65%
+  #reg only              2117   out of  12346   17.15%
+  #lut&reg               7309   out of  12346   59.20%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                                                               Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                                                                 1781
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                                                            1395
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                                                           1310
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                                                                 978
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             a_frame_pad_d0_reg_syn_17.q0                                                         148
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                                                            69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                                                           68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                                                                 24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                                                                 4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg3_syn_351_syn_2.f1    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/reg8_syn_143.f1                                                            3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                                                                1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                                                                1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                                                                1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                                                                 1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P165       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P70        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12346  |9202    |1027    |9456    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |540    |470     |23      |435     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |104    |86      |4       |93      |4       |0       |
+|    U_ecc_gen                 |ecc_gen              |14     |14      |0       |9       |0       |0       |
+|    U_crc16_24b               |crc16_24b            |24     |24      |0       |17      |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |760    |394     |96      |562     |0       |0       |
+|    u_ADconfig                |AD_config            |189    |110     |25      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |264    |172     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |739    |468     |96      |551     |0       |0       |
+|    u_ADconfig                |AD_config            |172    |100     |25      |127     |0       |0       |
+|    u_gen_sp                  |gen_sp               |260    |165     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3060   |2440    |306     |2090    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |181    |134     |17      |139     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2846   |2297    |289     |1918    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2415   |1978    |253     |1560    |22      |1       |
+|        channelPart           |channel_part_8478    |147    |142     |3       |128     |0       |0       |
+|        fifo_adc              |fifo_adc             |57     |47      |9       |39      |0       |1       |
+|        ram_switch            |ram_switch           |1905   |1548    |197     |1171    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |242    |215     |27      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |8      |5       |3       |2       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |12      |0       |0       |
+|          insert              |insert               |986    |658     |170     |685     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |677    |675     |0       |371     |0       |0       |
+|        read_ram_i            |read_ram             |282    |224     |44      |198     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |224    |184     |40      |157     |0       |0       |
+|          read_ram_data       |read_ram_data        |56     |38      |4       |39      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |339    |235     |36      |283     |3       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|        u0_soft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3177   |2438    |349     |2177    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |182    |130     |17      |143     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2968   |2286    |332     |2007    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2475   |1895    |290     |1599    |22      |0       |
+|        channelPart           |channel_part_8478    |230    |215     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |1801   |1347    |197     |1179    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |215    |188     |27      |122     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |14      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |7       |0       |0       |
+|          insert              |insert               |1006   |585     |170     |705     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |580    |574     |0       |352     |0       |0       |
+|        read_ram_i            |read_ram_rev         |363    |265     |81      |210     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |292    |214     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |71     |51      |8       |50      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets  
+    #1          1       9996  
+    #2          2       3781  
+    #3          3       1407  
+    #4          4       517   
+    #5        5-10      1200  
+    #6        11-50     581   
+    #7       51-100      25   
+    #8       101-500     1    
+    #9        >500       1    
+  Average     2.90            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.077600s wall, 3.562500s user + 0.015625s system = 3.578125s CPU (172.2%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1095 MB, peak memory is 1170 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73777, tnet num: 17426, tinst num: 6748, tnode num: 96224, tedge num: 123795.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.599554s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.6%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1099 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17426 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.544211s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (94.1%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1101 MB, peak memory is 1170 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6748
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17604, pip num: 177509
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 629
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3237 valid insts, and 489408 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.833541s wall, 67.750000s user + 0.156250s system = 67.906250s CPU (690.6%)
+
+RUN-1004 : used memory is 1270 MB, reserved memory is 1266 MB, peak memory is 1385 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_153704.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_154332.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_154332.log
new file mode 100644
index 0000000..8c798c7
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_154332.log
@@ -0,0 +1,1893 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:43:32 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.131439s wall, 2.062500s user + 0.078125s system = 2.140625s CPU (100.4%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 316 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2277 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17728 instances
+RUN-0007 : 7336 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20312 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13303 nets have 2 pins
+RUN-1001 : 5720 nets have [3 - 5] pins
+RUN-1001 : 876 nets have [6 - 10] pins
+RUN-1001 : 157 nets have [11 - 20] pins
+RUN-1001 : 182 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3597     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17726 instances, 7336 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84807, tnet num: 20134, tinst num: 17726, tnode num: 115275, tedge num: 136096.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.166279s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (99.1%)
+
+RUN-1004 : used memory is 538 MB, reserved memory is 515 MB, peak memory is 538 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.941153s wall, 1.875000s user + 0.046875s system = 1.921875s CPU (99.0%)
+
+PHY-3001 : Found 3485 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.98345e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17726.
+PHY-3001 : Level 1 #clusters 2034.
+PHY-3001 : End clustering;  0.126396s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (148.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.24965e+06, overlap = 500
+PHY-3002 : Step(2): len = 1.17654e+06, overlap = 522.125
+PHY-3002 : Step(3): len = 826469, overlap = 607.312
+PHY-3002 : Step(4): len = 771090, overlap = 664.25
+PHY-3002 : Step(5): len = 602310, overlap = 782.531
+PHY-3002 : Step(6): len = 530001, overlap = 828.344
+PHY-3002 : Step(7): len = 453332, overlap = 917.719
+PHY-3002 : Step(8): len = 426339, overlap = 959.719
+PHY-3002 : Step(9): len = 380328, overlap = 996.625
+PHY-3002 : Step(10): len = 355845, overlap = 1028.44
+PHY-3002 : Step(11): len = 314819, overlap = 1091.38
+PHY-3002 : Step(12): len = 296609, overlap = 1122.94
+PHY-3002 : Step(13): len = 259797, overlap = 1191.75
+PHY-3002 : Step(14): len = 245853, overlap = 1220
+PHY-3002 : Step(15): len = 219697, overlap = 1251.47
+PHY-3002 : Step(16): len = 210846, overlap = 1288.69
+PHY-3002 : Step(17): len = 188537, overlap = 1332.53
+PHY-3002 : Step(18): len = 178996, overlap = 1397.72
+PHY-3002 : Step(19): len = 165258, overlap = 1440.25
+PHY-3002 : Step(20): len = 153571, overlap = 1473.97
+PHY-3002 : Step(21): len = 147807, overlap = 1491.09
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.62818e-07
+PHY-3002 : Step(22): len = 146477, overlap = 1443.72
+PHY-3002 : Step(23): len = 179974, overlap = 1337.16
+PHY-3002 : Step(24): len = 187470, overlap = 1269.59
+PHY-3002 : Step(25): len = 192598, overlap = 1177.91
+PHY-3002 : Step(26): len = 191134, overlap = 1135.75
+PHY-3002 : Step(27): len = 188302, overlap = 1178.97
+PHY-3002 : Step(28): len = 185119, overlap = 1188.62
+PHY-3002 : Step(29): len = 181768, overlap = 1220.94
+PHY-3002 : Step(30): len = 179867, overlap = 1211.94
+PHY-3002 : Step(31): len = 176837, overlap = 1225.78
+PHY-3002 : Step(32): len = 175748, overlap = 1238.62
+PHY-3002 : Step(33): len = 174533, overlap = 1237.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.92564e-06
+PHY-3002 : Step(34): len = 177537, overlap = 1232.19
+PHY-3002 : Step(35): len = 190076, overlap = 1174.53
+PHY-3002 : Step(36): len = 196691, overlap = 1106.81
+PHY-3002 : Step(37): len = 201654, overlap = 1113.47
+PHY-3002 : Step(38): len = 204292, overlap = 1095.34
+PHY-3002 : Step(39): len = 205156, overlap = 1079.97
+PHY-3002 : Step(40): len = 204415, overlap = 1055.16
+PHY-3002 : Step(41): len = 205280, overlap = 1036.44
+PHY-3002 : Step(42): len = 202709, overlap = 1011.09
+PHY-3002 : Step(43): len = 201159, overlap = 1003.22
+PHY-3002 : Step(44): len = 198099, overlap = 996.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.85127e-06
+PHY-3002 : Step(45): len = 206332, overlap = 962.156
+PHY-3002 : Step(46): len = 222124, overlap = 923.125
+PHY-3002 : Step(47): len = 232110, overlap = 890.594
+PHY-3002 : Step(48): len = 237185, overlap = 884.938
+PHY-3002 : Step(49): len = 238214, overlap = 865.812
+PHY-3002 : Step(50): len = 237897, overlap = 862.875
+PHY-3002 : Step(51): len = 234960, overlap = 849.781
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.70254e-06
+PHY-3002 : Step(52): len = 245790, overlap = 850.438
+PHY-3002 : Step(53): len = 265340, overlap = 775.75
+PHY-3002 : Step(54): len = 277710, overlap = 699.906
+PHY-3002 : Step(55): len = 287238, overlap = 660.406
+PHY-3002 : Step(56): len = 290393, overlap = 647.906
+PHY-3002 : Step(57): len = 291809, overlap = 634.094
+PHY-3002 : Step(58): len = 290334, overlap = 633.625
+PHY-3002 : Step(59): len = 289852, overlap = 638.594
+PHY-3002 : Step(60): len = 287355, overlap = 650.406
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.54051e-05
+PHY-3002 : Step(61): len = 308726, overlap = 618.062
+PHY-3002 : Step(62): len = 334758, overlap = 562.812
+PHY-3002 : Step(63): len = 343943, overlap = 554.375
+PHY-3002 : Step(64): len = 348076, overlap = 513.906
+PHY-3002 : Step(65): len = 345362, overlap = 483.219
+PHY-3002 : Step(66): len = 344184, overlap = 475.906
+PHY-3002 : Step(67): len = 341236, overlap = 473.344
+PHY-3002 : Step(68): len = 340825, overlap = 472.188
+PHY-3002 : Step(69): len = 338597, overlap = 476.438
+PHY-3002 : Step(70): len = 337260, overlap = 477.094
+PHY-3002 : Step(71): len = 335373, overlap = 478.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.08102e-05
+PHY-3002 : Step(72): len = 359978, overlap = 453.25
+PHY-3002 : Step(73): len = 373860, overlap = 405.281
+PHY-3002 : Step(74): len = 370068, overlap = 415.875
+PHY-3002 : Step(75): len = 370799, overlap = 424.562
+PHY-3002 : Step(76): len = 373724, overlap = 396.062
+PHY-3002 : Step(77): len = 377075, overlap = 371.438
+PHY-3002 : Step(78): len = 375800, overlap = 347.281
+PHY-3002 : Step(79): len = 377669, overlap = 344.344
+PHY-3002 : Step(80): len = 378865, overlap = 355.219
+PHY-3002 : Step(81): len = 379339, overlap = 361.906
+PHY-3002 : Step(82): len = 377595, overlap = 372.281
+PHY-3002 : Step(83): len = 378279, overlap = 381.125
+PHY-3002 : Step(84): len = 377849, overlap = 387.312
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.16204e-05
+PHY-3002 : Step(85): len = 399303, overlap = 370.719
+PHY-3002 : Step(86): len = 412350, overlap = 350.938
+PHY-3002 : Step(87): len = 409749, overlap = 352.281
+PHY-3002 : Step(88): len = 411298, overlap = 340.625
+PHY-3002 : Step(89): len = 415032, overlap = 336
+PHY-3002 : Step(90): len = 418650, overlap = 334
+PHY-3002 : Step(91): len = 417413, overlap = 323.688
+PHY-3002 : Step(92): len = 417742, overlap = 314.5
+PHY-3002 : Step(93): len = 418921, overlap = 295.375
+PHY-3002 : Step(94): len = 420802, overlap = 279.438
+PHY-3002 : Step(95): len = 420203, overlap = 275.969
+PHY-3002 : Step(96): len = 421119, overlap = 291.938
+PHY-3002 : Step(97): len = 422207, overlap = 297.281
+PHY-3002 : Step(98): len = 421586, overlap = 324.969
+PHY-3002 : Step(99): len = 420051, overlap = 324.625
+PHY-3002 : Step(100): len = 421376, overlap = 326
+PHY-3002 : Step(101): len = 421769, overlap = 316.531
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000123241
+PHY-3002 : Step(102): len = 438041, overlap = 289.875
+PHY-3002 : Step(103): len = 447734, overlap = 273.969
+PHY-3002 : Step(104): len = 447576, overlap = 266.312
+PHY-3002 : Step(105): len = 448976, overlap = 263.031
+PHY-3002 : Step(106): len = 450801, overlap = 264.531
+PHY-3002 : Step(107): len = 453201, overlap = 265.719
+PHY-3002 : Step(108): len = 452428, overlap = 271.906
+PHY-3002 : Step(109): len = 453431, overlap = 265.781
+PHY-3002 : Step(110): len = 455144, overlap = 257.125
+PHY-3002 : Step(111): len = 457588, overlap = 251.938
+PHY-3002 : Step(112): len = 455925, overlap = 256.969
+PHY-3002 : Step(113): len = 455890, overlap = 262.594
+PHY-3002 : Step(114): len = 457078, overlap = 266.531
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000245703
+PHY-3002 : Step(115): len = 470605, overlap = 249.781
+PHY-3002 : Step(116): len = 482228, overlap = 223.844
+PHY-3002 : Step(117): len = 485653, overlap = 218.875
+PHY-3002 : Step(118): len = 489001, overlap = 220.5
+PHY-3002 : Step(119): len = 491530, overlap = 223.812
+PHY-3002 : Step(120): len = 493011, overlap = 220.906
+PHY-3002 : Step(121): len = 490925, overlap = 231
+PHY-3002 : Step(122): len = 490637, overlap = 234.219
+PHY-3002 : Step(123): len = 491585, overlap = 221.188
+PHY-3002 : Step(124): len = 492585, overlap = 224.688
+PHY-3002 : Step(125): len = 491425, overlap = 232.312
+PHY-3002 : Step(126): len = 490758, overlap = 232.5
+PHY-3002 : Step(127): len = 491881, overlap = 222.938
+PHY-3002 : Step(128): len = 492650, overlap = 215.344
+PHY-3002 : Step(129): len = 492042, overlap = 219.75
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000468487
+PHY-3002 : Step(130): len = 500461, overlap = 218.75
+PHY-3002 : Step(131): len = 508496, overlap = 219.719
+PHY-3002 : Step(132): len = 508923, overlap = 216.25
+PHY-3002 : Step(133): len = 509847, overlap = 208.25
+PHY-3002 : Step(134): len = 512889, overlap = 209.469
+PHY-3002 : Step(135): len = 514969, overlap = 209.031
+PHY-3002 : Step(136): len = 514507, overlap = 208.156
+PHY-3002 : Step(137): len = 514917, overlap = 199.719
+PHY-3002 : Step(138): len = 517091, overlap = 200.5
+PHY-3002 : Step(139): len = 519617, overlap = 194.438
+PHY-3002 : Step(140): len = 519163, overlap = 192.312
+PHY-3002 : Step(141): len = 519602, overlap = 193.188
+PHY-3002 : Step(142): len = 521025, overlap = 186.25
+PHY-3002 : Step(143): len = 522195, overlap = 182.625
+PHY-3002 : Step(144): len = 521792, overlap = 182.031
+PHY-3002 : Step(145): len = 521758, overlap = 181.375
+PHY-3002 : Step(146): len = 522931, overlap = 180.312
+PHY-3002 : Step(147): len = 524194, overlap = 176.688
+PHY-3002 : Step(148): len = 523421, overlap = 174.469
+PHY-3002 : Step(149): len = 523280, overlap = 170.062
+PHY-3002 : Step(150): len = 524204, overlap = 170.844
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000933672
+PHY-3002 : Step(151): len = 530197, overlap = 173.562
+PHY-3002 : Step(152): len = 539114, overlap = 165.969
+PHY-3002 : Step(153): len = 541437, overlap = 161.438
+PHY-3002 : Step(154): len = 543376, overlap = 156.438
+PHY-3002 : Step(155): len = 545292, overlap = 153.469
+PHY-3002 : Step(156): len = 547670, overlap = 155.094
+PHY-3002 : Step(157): len = 548045, overlap = 153.469
+PHY-3002 : Step(158): len = 548980, overlap = 158.25
+PHY-3002 : Step(159): len = 550187, overlap = 157.406
+PHY-3002 : Step(160): len = 550531, overlap = 160.781
+PHY-3002 : Step(161): len = 549683, overlap = 157.312
+PHY-3002 : Step(162): len = 548989, overlap = 156
+PHY-3002 : Step(163): len = 549403, overlap = 154.812
+PHY-3002 : Step(164): len = 549619, overlap = 154.5
+PHY-3002 : Step(165): len = 549024, overlap = 152.406
+PHY-3002 : Step(166): len = 548699, overlap = 154.188
+PHY-3002 : Step(167): len = 548967, overlap = 155.719
+PHY-3002 : Step(168): len = 548919, overlap = 156.344
+PHY-3002 : Step(169): len = 548281, overlap = 158.156
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00161218
+PHY-3002 : Step(170): len = 551058, overlap = 157.406
+PHY-3002 : Step(171): len = 554912, overlap = 157.344
+PHY-3002 : Step(172): len = 555778, overlap = 154.531
+PHY-3002 : Step(173): len = 556514, overlap = 154.875
+PHY-3002 : Step(174): len = 557250, overlap = 151.844
+PHY-3002 : Step(175): len = 557664, overlap = 150.969
+PHY-3002 : Step(176): len = 557826, overlap = 151.844
+PHY-3002 : Step(177): len = 558446, overlap = 147.219
+PHY-3002 : Step(178): len = 559773, overlap = 147.938
+PHY-3002 : Step(179): len = 561128, overlap = 143.906
+PHY-3002 : Step(180): len = 561360, overlap = 143.062
+PHY-3002 : Step(181): len = 561548, overlap = 144.125
+PHY-3002 : Step(182): len = 561902, overlap = 142.656
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00294263
+PHY-3002 : Step(183): len = 563951, overlap = 141.219
+PHY-3002 : Step(184): len = 568603, overlap = 138.812
+PHY-3002 : Step(185): len = 570110, overlap = 135.719
+PHY-3002 : Step(186): len = 571798, overlap = 128.094
+PHY-3002 : Step(187): len = 573523, overlap = 119.844
+PHY-3002 : Step(188): len = 575606, overlap = 121.406
+PHY-3002 : Step(189): len = 576446, overlap = 121.906
+PHY-3002 : Step(190): len = 576878, overlap = 122.562
+PHY-3002 : Step(191): len = 577089, overlap = 122.125
+PHY-3002 : Step(192): len = 577130, overlap = 121.875
+PHY-3002 : Step(193): len = 577056, overlap = 120.594
+PHY-3002 : Step(194): len = 577225, overlap = 123.25
+PHY-3002 : Step(195): len = 577484, overlap = 125.406
+PHY-3002 : Step(196): len = 577699, overlap = 124.438
+PHY-3002 : Step(197): len = 577933, overlap = 124.312
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014414s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (108.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20312.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715192, over cnt = 1630(4%), over = 7273, worst = 30
+PHY-1001 : End global iterations;  0.729636s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (130.6%)
+
+PHY-1001 : Congestion index: top1 = 80.15, top5 = 61.68, top10 = 52.27, top15 = 46.31.
+PHY-3001 : End congestion estimation;  0.949618s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (125.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.856831s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.96148e-05
+PHY-3002 : Step(198): len = 651157, overlap = 66.9062
+PHY-3002 : Step(199): len = 658474, overlap = 67.6875
+PHY-3002 : Step(200): len = 652229, overlap = 79.125
+PHY-3002 : Step(201): len = 647766, overlap = 74.4375
+PHY-3002 : Step(202): len = 652924, overlap = 79.5312
+PHY-3002 : Step(203): len = 664761, overlap = 88.3438
+PHY-3002 : Step(204): len = 668427, overlap = 92.4062
+PHY-3002 : Step(205): len = 669100, overlap = 82.5625
+PHY-3002 : Step(206): len = 671302, overlap = 86.8125
+PHY-3002 : Step(207): len = 677046, overlap = 87.8438
+PHY-3002 : Step(208): len = 677484, overlap = 82.7812
+PHY-3002 : Step(209): len = 678397, overlap = 79.2188
+PHY-3002 : Step(210): len = 681707, overlap = 70.6875
+PHY-3002 : Step(211): len = 683572, overlap = 68.9688
+PHY-3002 : Step(212): len = 683866, overlap = 67.25
+PHY-3002 : Step(213): len = 683207, overlap = 64.75
+PHY-3002 : Step(214): len = 682054, overlap = 61.6562
+PHY-3002 : Step(215): len = 682092, overlap = 54.5
+PHY-3002 : Step(216): len = 682016, overlap = 51.0312
+PHY-3002 : Step(217): len = 681392, overlap = 43.3125
+PHY-3002 : Step(218): len = 678931, overlap = 37.3438
+PHY-3002 : Step(219): len = 677641, overlap = 39.6562
+PHY-3002 : Step(220): len = 675697, overlap = 37.5938
+PHY-3002 : Step(221): len = 675181, overlap = 34.6875
+PHY-3002 : Step(222): len = 674045, overlap = 32.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00019923
+PHY-3002 : Step(223): len = 674643, overlap = 29.6875
+PHY-3002 : Step(224): len = 677539, overlap = 26.4375
+PHY-3002 : Step(225): len = 682694, overlap = 24.4375
+PHY-3002 : Step(226): len = 687038, overlap = 21.7188
+PHY-3002 : Step(227): len = 689726, overlap = 23.7812
+PHY-3002 : Step(228): len = 688124, overlap = 26.4062
+PHY-3002 : Step(229): len = 687821, overlap = 26.8125
+PHY-3002 : Step(230): len = 685752, overlap = 25.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000398459
+PHY-3002 : Step(231): len = 691152, overlap = 23.25
+PHY-3002 : Step(232): len = 697951, overlap = 24.2188
+PHY-3002 : Step(233): len = 703063, overlap = 23.9062
+PHY-3002 : Step(234): len = 709396, overlap = 23.6562
+PHY-3002 : Step(235): len = 712484, overlap = 22.9375
+PHY-3002 : Step(236): len = 715126, overlap = 22.5
+PHY-3002 : Step(237): len = 715699, overlap = 23
+PHY-3002 : Step(238): len = 717189, overlap = 23.8125
+PHY-3002 : Step(239): len = 716213, overlap = 24.3438
+PHY-3002 : Step(240): len = 715475, overlap = 25.7812
+PHY-3002 : Step(241): len = 714823, overlap = 29.5938
+PHY-3002 : Step(242): len = 717462, overlap = 31.5312
+PHY-3002 : Step(243): len = 715655, overlap = 30.3438
+PHY-3002 : Step(244): len = 715389, overlap = 30.7188
+PHY-3002 : Step(245): len = 715210, overlap = 26.0312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000796919
+PHY-3002 : Step(246): len = 718325, overlap = 27.4062
+PHY-3002 : Step(247): len = 724929, overlap = 27.6875
+PHY-3002 : Step(248): len = 733755, overlap = 31.4375
+PHY-3002 : Step(249): len = 743995, overlap = 31.9688
+PHY-3002 : Step(250): len = 744925, overlap = 31.3125
+PHY-3002 : Step(251): len = 743473, overlap = 30.9062
+PHY-3002 : Step(252): len = 741343, overlap = 30.9375
+PHY-3002 : Step(253): len = 739807, overlap = 31.7188
+PHY-3002 : Step(254): len = 740895, overlap = 29.75
+PHY-3002 : Step(255): len = 740355, overlap = 31.1875
+PHY-3002 : Step(256): len = 743519, overlap = 31.8438
+PHY-3002 : Step(257): len = 749131, overlap = 30.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00153417
+PHY-3002 : Step(258): len = 749178, overlap = 29.5312
+PHY-3002 : Step(259): len = 750564, overlap = 29.75
+PHY-3002 : Step(260): len = 751823, overlap = 32.3438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 46/20312.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 830216, over cnt = 2832(8%), over = 14611, worst = 101
+PHY-1001 : End global iterations;  1.472278s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 116.31, top5 = 77.83, top10 = 66.35, top15 = 59.64.
+PHY-3001 : End congestion estimation;  1.750520s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (130.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.883144s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000119578
+PHY-3002 : Step(261): len = 752130, overlap = 221.969
+PHY-3002 : Step(262): len = 753440, overlap = 190.75
+PHY-3002 : Step(263): len = 742254, overlap = 169.5
+PHY-3002 : Step(264): len = 736095, overlap = 151.438
+PHY-3002 : Step(265): len = 728110, overlap = 140.312
+PHY-3002 : Step(266): len = 724824, overlap = 132.688
+PHY-3002 : Step(267): len = 718216, overlap = 126.125
+PHY-3002 : Step(268): len = 714600, overlap = 122.719
+PHY-3002 : Step(269): len = 710207, overlap = 123.062
+PHY-3002 : Step(270): len = 705599, overlap = 116.906
+PHY-3002 : Step(271): len = 702863, overlap = 120.156
+PHY-3002 : Step(272): len = 698053, overlap = 120.219
+PHY-3002 : Step(273): len = 694835, overlap = 124.062
+PHY-3002 : Step(274): len = 692667, overlap = 121.281
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000239157
+PHY-3002 : Step(275): len = 693077, overlap = 118.406
+PHY-3002 : Step(276): len = 696309, overlap = 109.344
+PHY-3002 : Step(277): len = 699876, overlap = 100.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000478314
+PHY-3002 : Step(278): len = 705248, overlap = 88.375
+PHY-3002 : Step(279): len = 713669, overlap = 78.9688
+PHY-3002 : Step(280): len = 718298, overlap = 76.125
+PHY-3002 : Step(281): len = 717113, overlap = 76.8438
+PHY-3002 : Step(282): len = 716805, overlap = 81.6562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000956628
+PHY-3002 : Step(283): len = 720516, overlap = 76.5938
+PHY-3002 : Step(284): len = 725150, overlap = 73
+PHY-3002 : Step(285): len = 730205, overlap = 69.75
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84807, tnet num: 20134, tinst num: 17726, tnode num: 115275, tedge num: 136096.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.396533s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (99.6%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 565 MB, peak memory is 718 MB
+OPT-1001 : Total overflow 401.78 peak overflow 3.47
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 669/20312.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 827816, over cnt = 3152(8%), over = 12458, worst = 87
+PHY-1001 : End global iterations;  1.303708s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (141.4%)
+
+PHY-1001 : Congestion index: top1 = 84.68, top5 = 63.75, top10 = 55.81, top15 = 51.32.
+PHY-1001 : End incremental global routing;  1.625323s wall, 2.140625s user + 0.031250s system = 2.171875s CPU (133.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.893584s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.7%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17590 has valid locations, 337 needs to be replaced
+PHY-3001 : design contains 18012 instances, 7435 luts, 9356 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6024 pins
+PHY-3001 : Found 3522 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 753123
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17029/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843800, over cnt = 3168(9%), over = 12439, worst = 87
+PHY-1001 : End global iterations;  0.237191s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (112.0%)
+
+PHY-1001 : Congestion index: top1 = 84.98, top5 = 64.00, top10 = 56.04, top15 = 51.55.
+PHY-3001 : End congestion estimation;  0.483870s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85978, tnet num: 20420, tinst num: 18012, tnode num: 117037, tedge num: 137866.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.427579s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (99.6%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 616 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.390503s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(286): len = 751960, overlap = 0.125
+PHY-3002 : Step(287): len = 751311, overlap = 0.1875
+PHY-3002 : Step(288): len = 750989, overlap = 0.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17140/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841216, over cnt = 3181(9%), over = 12503, worst = 87
+PHY-1001 : End global iterations;  0.189352s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (123.8%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 64.43, top10 = 56.38, top15 = 51.79.
+PHY-3001 : End congestion estimation;  0.447636s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (111.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.266398s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000519413
+PHY-3002 : Step(289): len = 750776, overlap = 71.8125
+PHY-3002 : Step(290): len = 750836, overlap = 71.2812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00103883
+PHY-3002 : Step(291): len = 751049, overlap = 71.1562
+PHY-3002 : Step(292): len = 751690, overlap = 71.4688
+PHY-3001 : Final: Len = 751690, Over = 71.4688
+PHY-3001 : End incremental placement;  5.202174s wall, 5.437500s user + 0.234375s system = 5.671875s CPU (109.0%)
+
+OPT-1001 : Total overflow 406.88 peak overflow 3.47
+OPT-1001 : End high-fanout net optimization;  8.330095s wall, 9.171875s user + 0.281250s system = 9.453125s CPU (113.5%)
+
+OPT-1001 : Current memory(MB): used = 727, reserve = 715, peak = 743.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17062/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844256, over cnt = 3150(8%), over = 11512, worst = 87
+PHY-1002 : len = 899472, over cnt = 2367(6%), over = 6351, worst = 71
+PHY-1002 : len = 940680, over cnt = 1094(3%), over = 2682, worst = 17
+PHY-1002 : len = 969896, over cnt = 275(0%), over = 575, worst = 11
+PHY-1002 : len = 978832, over cnt = 10(0%), over = 21, worst = 5
+PHY-1001 : End global iterations;  2.135917s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (132.4%)
+
+PHY-1001 : Congestion index: top1 = 62.31, top5 = 54.50, top10 = 50.53, top15 = 47.93.
+OPT-1001 : End congestion update;  2.386075s wall, 3.078125s user + 0.000000s system = 3.078125s CPU (129.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.777142s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.5%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 75 cells processed and 7900 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 20 cells processed and 1150 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 9 cells processed and 466 slack improved
+OPT-1001 : End global optimization;  3.205057s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (121.4%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 696, peak = 743.
+OPT-1001 : End physical optimization;  13.539465s wall, 15.156250s user + 0.296875s system = 15.453125s CPU (114.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7435 LUT to BLE ...
+SYN-4008 : Packed 7435 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6223 remaining SEQ's ...
+SYN-4005 : Packed 4034 SEQ with LUT/SLICE
+SYN-4006 : 574 single LUT's are left
+SYN-4006 : 2189 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9624/13355 primitive instances ...
+PHY-3001 : End packing;  1.557290s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6730 instances
+RUN-1001 : 3291 mslices, 3291 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17592 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9926 nets have 2 pins
+RUN-1001 : 5996 nets have [3 - 5] pins
+RUN-1001 : 988 nets have [6 - 10] pins
+RUN-1001 : 288 nets have [11 - 20] pins
+RUN-1001 : 363 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6728 instances, 6582 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3532 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 758274, Over = 242
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7597/17592.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919464, over cnt = 2080(5%), over = 3365, worst = 8
+PHY-1002 : len = 928128, over cnt = 1270(3%), over = 1736, worst = 8
+PHY-1002 : len = 941112, over cnt = 490(1%), over = 629, worst = 6
+PHY-1002 : len = 945536, over cnt = 262(0%), over = 349, worst = 6
+PHY-1002 : len = 952448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.637716s wall, 2.265625s user + 0.046875s system = 2.312500s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 59.46, top5 = 52.39, top10 = 48.50, top15 = 46.05.
+PHY-3001 : End congestion estimation;  2.031252s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (133.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73729, tnet num: 17414, tinst num: 6728, tnode num: 96334, tedge num: 123854.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.607009s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.1%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 618 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17414 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.453020s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.53708e-05
+PHY-3002 : Step(293): len = 742128, overlap = 236.5
+PHY-3002 : Step(294): len = 733710, overlap = 236
+PHY-3002 : Step(295): len = 727678, overlap = 239.75
+PHY-3002 : Step(296): len = 722702, overlap = 249
+PHY-3002 : Step(297): len = 719078, overlap = 252.75
+PHY-3002 : Step(298): len = 715606, overlap = 247.75
+PHY-3002 : Step(299): len = 711970, overlap = 247.5
+PHY-3002 : Step(300): len = 708509, overlap = 246
+PHY-3002 : Step(301): len = 704883, overlap = 246
+PHY-3002 : Step(302): len = 701553, overlap = 254.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000110742
+PHY-3002 : Step(303): len = 705427, overlap = 240.5
+PHY-3002 : Step(304): len = 710831, overlap = 226.5
+PHY-3002 : Step(305): len = 711032, overlap = 228.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000221483
+PHY-3002 : Step(306): len = 720566, overlap = 217.25
+PHY-3002 : Step(307): len = 729092, overlap = 212
+PHY-3002 : Step(308): len = 727412, overlap = 210.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.340167s wall, 0.312500s user + 0.531250s system = 0.843750s CPU (248.0%)
+
+PHY-3001 : Trial Legalized: Len = 894771
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 455/17592.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0115e+06, over cnt = 2858(8%), over = 4977, worst = 9
+PHY-1002 : len = 1.03e+06, over cnt = 1859(5%), over = 2801, worst = 7
+PHY-1002 : len = 1.05256e+06, over cnt = 791(2%), over = 1097, worst = 7
+PHY-1002 : len = 1.06812e+06, over cnt = 151(0%), over = 214, worst = 6
+PHY-1002 : len = 1.0719e+06, over cnt = 15(0%), over = 21, worst = 3
+PHY-1001 : End global iterations;  2.468051s wall, 3.562500s user + 0.031250s system = 3.593750s CPU (145.6%)
+
+PHY-1001 : Congestion index: top1 = 63.08, top5 = 56.82, top10 = 53.30, top15 = 50.91.
+PHY-3001 : End congestion estimation;  2.905257s wall, 4.015625s user + 0.031250s system = 4.046875s CPU (139.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17414 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.119877s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000162887
+PHY-3002 : Step(309): len = 849990, overlap = 68.75
+PHY-3002 : Step(310): len = 829172, overlap = 94.5
+PHY-3002 : Step(311): len = 815674, overlap = 112.25
+PHY-3002 : Step(312): len = 804784, overlap = 131.5
+PHY-3002 : Step(313): len = 796641, overlap = 149.75
+PHY-3002 : Step(314): len = 790370, overlap = 168.25
+PHY-3002 : Step(315): len = 786187, overlap = 173.75
+PHY-3002 : Step(316): len = 782439, overlap = 185
+PHY-3002 : Step(317): len = 779344, overlap = 192.5
+PHY-3002 : Step(318): len = 776567, overlap = 195.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000325773
+PHY-3002 : Step(319): len = 781270, overlap = 189.25
+PHY-3002 : Step(320): len = 784663, overlap = 179.25
+PHY-3002 : Step(321): len = 786516, overlap = 176.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000585907
+PHY-3002 : Step(322): len = 792669, overlap = 172
+PHY-3002 : Step(323): len = 795785, overlap = 171.75
+PHY-3002 : Step(324): len = 798462, overlap = 166.75
+PHY-3002 : Step(325): len = 799847, overlap = 163.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.077408s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (100.9%)
+
+PHY-3001 : Legalized: Len = 851078, Over = 0
+PHY-3001 : Spreading special nets. 473 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.113195s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (96.6%)
+
+PHY-3001 : 725 instances has been re-located, deltaX = 258, deltaY = 496, maxDist = 5.
+PHY-3001 : Final: Len = 862753, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73729, tnet num: 17414, tinst num: 6731, tnode num: 96334, tedge num: 123854.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.855038s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (99.4%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 652 MB, peak memory is 743 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3114/17592.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992120, over cnt = 2617(7%), over = 4356, worst = 9
+PHY-1002 : len = 1.00517e+06, over cnt = 1651(4%), over = 2424, worst = 9
+PHY-1002 : len = 1.0228e+06, over cnt = 763(2%), over = 1101, worst = 5
+PHY-1002 : len = 1.03312e+06, over cnt = 315(0%), over = 425, worst = 5
+PHY-1002 : len = 1.03937e+06, over cnt = 57(0%), over = 64, worst = 3
+PHY-1001 : End global iterations;  2.129273s wall, 3.062500s user + 0.093750s system = 3.156250s CPU (148.2%)
+
+PHY-1001 : Congestion index: top1 = 60.65, top5 = 54.54, top10 = 51.21, top15 = 48.94.
+PHY-1001 : End incremental global routing;  2.509352s wall, 3.437500s user + 0.093750s system = 3.531250s CPU (140.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17414 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.882827s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.9%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 1559 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 865013
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16104/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04155e+06, over cnt = 105(0%), over = 124, worst = 3
+PHY-1002 : len = 1.04152e+06, over cnt = 66(0%), over = 67, worst = 2
+PHY-1002 : len = 1.04221e+06, over cnt = 16(0%), over = 17, worst = 2
+PHY-1002 : len = 1.0423e+06, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 1.04295e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.800246s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.5%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.63, top10 = 51.22, top15 = 48.96.
+PHY-3001 : End congestion estimation;  1.113585s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17432, tinst num: 6748, tnode num: 96508, tedge num: 124025.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.844252s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (100.0%)
+
+RUN-1004 : used memory is 673 MB, reserved memory is 670 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.809277s wall, 2.765625s user + 0.031250s system = 2.796875s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(326): len = 864666, overlap = 0.25
+PHY-3002 : Step(327): len = 864319, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16100/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04232e+06, over cnt = 38(0%), over = 49, worst = 4
+PHY-1002 : len = 1.04246e+06, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 1.04258e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.04263e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.597106s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (102.1%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.62, top10 = 51.20, top15 = 48.95.
+PHY-3001 : End congestion estimation;  0.913992s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.881606s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000564311
+PHY-3002 : Step(328): len = 864261, overlap = 1
+PHY-3002 : Step(329): len = 864236, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005621s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 864374, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063068s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.1%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 864420, Over = 0
+PHY-3001 : End incremental placement;  6.209017s wall, 6.234375s user + 0.078125s system = 6.312500s CPU (101.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.129816s wall, 11.078125s user + 0.187500s system = 11.265625s CPU (111.2%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 750, peak = 756.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16076/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04234e+06, over cnt = 63(0%), over = 71, worst = 3
+PHY-1002 : len = 1.04238e+06, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 1.0427e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.04274e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.04276e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.776614s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (106.6%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.63, top10 = 51.21, top15 = 48.94.
+OPT-1001 : End congestion update;  1.101635s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (105.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.750843s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1083 TNS -1716 NUM_FEPS 4
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 1559 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 867673, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059462s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.1%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 10, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 868173, Over = 0
+PHY-3001 : End incremental legalization;  0.377092s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (99.4%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 29 cells processed and 8950 slack improved
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.372998s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (102.1%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 750, peak = 756.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.720732s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15940/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04626e+06, over cnt = 114(0%), over = 144, worst = 4
+PHY-1002 : len = 1.04623e+06, over cnt = 55(0%), over = 59, worst = 2
+PHY-1002 : len = 1.04641e+06, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 1.0467e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.04695e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.810172s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (108.0%)
+
+PHY-1001 : Congestion index: top1 = 60.86, top5 = 54.68, top10 = 51.31, top15 = 49.03.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.706979s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1097 TNS -1632 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 60.448276
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1097ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17610 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17610 nets
+OPT-1001 : End physical optimization;  17.252707s wall, 18.375000s user + 0.203125s system = 18.578125s CPU (107.7%)
+
+RUN-1003 : finish command "place" in  61.141472s wall, 93.921875s user + 6.078125s system = 100.000000s CPU (163.6%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 647 MB, peak memory is 756 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.669541s wall, 2.890625s user + 0.015625s system = 2.906250s CPU (174.1%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 648 MB, peak memory is 756 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6750 instances
+RUN-1001 : 3299 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17610 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9923 nets have 2 pins
+RUN-1001 : 5995 nets have [3 - 5] pins
+RUN-1001 : 996 nets have [6 - 10] pins
+RUN-1001 : 294 nets have [11 - 20] pins
+RUN-1001 : 374 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17432, tinst num: 6748, tnode num: 96508, tedge num: 124025.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.568882s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (100.6%)
+
+RUN-1004 : used memory is 672 MB, reserved memory is 675 MB, peak memory is 756 MB
+PHY-1001 : 3299 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 976752, over cnt = 2835(8%), over = 4759, worst = 9
+PHY-1002 : len = 993576, over cnt = 1860(5%), over = 2759, worst = 7
+PHY-1002 : len = 1.01687e+06, over cnt = 717(2%), over = 1000, worst = 6
+PHY-1002 : len = 1.03206e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.03218e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.953009s wall, 4.000000s user + 0.078125s system = 4.078125s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 60.09, top5 = 54.03, top10 = 50.82, top15 = 48.68.
+PHY-1001 : End global routing;  3.278006s wall, 4.328125s user + 0.078125s system = 4.406250s CPU (134.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 723, reserve = 721, peak = 756.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 995, reserve = 993, peak = 995.
+PHY-1001 : End build detailed router design. 3.907876s wall, 3.765625s user + 0.140625s system = 3.906250s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270184, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.040418s wall, 5.046875s user + 0.000000s system = 5.046875s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270240, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.421854s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1029, peak = 1031.
+PHY-1001 : End phase 1; 5.473943s wall, 5.484375s user + 0.000000s system = 5.484375s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.50711e+06, over cnt = 2085(0%), over = 2089, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1043, peak = 1047.
+PHY-1001 : End initial routed; 41.678758s wall, 70.390625s user + 0.328125s system = 70.718750s CPU (169.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16533(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.798   |  -3.771   |   5   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.289145s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1059, reserve = 1055, peak = 1059.
+PHY-1001 : End phase 2; 44.967965s wall, 73.671875s user + 0.328125s system = 74.000000s CPU (164.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 6 pins with SWNS -1.795ns STNS -3.586ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.147088s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.2%)
+
+PHY-1022 : len = 2.50714e+06, over cnt = 2092(0%), over = 2096, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.407629s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (103.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.47083e+06, over cnt = 911(0%), over = 914, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.444900s wall, 3.953125s user + 0.000000s system = 3.953125s CPU (161.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.46177e+06, over cnt = 254(0%), over = 254, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.282867s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (127.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.4619e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.702203s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (142.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.46214e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.309252s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (101.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.46214e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.201331s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.4622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.281001s wall, 0.265625s user + 0.015625s system = 0.281250s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.4622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.298083s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.46222e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.165977s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.46222e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.158064s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (98.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16533(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.795   |  -3.586   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.187900s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 683 feed throughs used by 469 nets
+PHY-1001 : End commit to database; 2.275612s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1162, reserve = 1163, peak = 1162.
+PHY-1001 : End phase 3; 12.120293s wall, 14.265625s user + 0.015625s system = 14.281250s CPU (117.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -1.795ns STNS -3.586ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.151058s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.4%)
+
+PHY-1022 : len = 2.46222e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.403672s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.795ns, -3.586ns, 4}
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16533(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.795   |  -3.586   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.236202s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 683 feed throughs used by 469 nets
+PHY-1001 : End commit to database; 2.363787s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1171, reserve = 1172, peak = 1171.
+PHY-1001 : End phase 4; 6.030469s wall, 6.031250s user + 0.000000s system = 6.031250s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.46222e+06
+PHY-1001 : Current memory(MB): used = 1173, reserve = 1174, peak = 1173.
+PHY-1001 : End export database. 0.062595s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
+
+PHY-1001 : End detail routing;  72.950157s wall, 103.656250s user + 0.484375s system = 104.140625s CPU (142.8%)
+
+RUN-1003 : finish command "route" in  78.830338s wall, 110.562500s user + 0.578125s system = 111.140625s CPU (141.0%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1099 MB, peak memory is 1173 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10197   out of  19600   52.03%
+#reg                     9499   out of  19600   48.46%
+#le                     12302
+  #lut only              2803   out of  12302   22.78%
+  #reg only              2105   out of  12302   17.11%
+  #lut&reg               7394   out of  12302   60.10%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1788
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1420
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1309
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               994
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    142
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_pic_cnt/reg1_syn_371.f0                          3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             ua_lvds_rx/reg8_syn_197.f0                         3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P163       LVCMOS33           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12302  |9170    |1027    |9529    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |529    |408     |23      |444     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |89      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |27     |27      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |8       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |768    |430     |96      |578     |0       |0       |
+|    u_ADconfig                |AD_config            |188    |125     |25      |142     |0       |0       |
+|    u_gen_sp                  |gen_sp               |269    |155     |71      |125     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |754    |450     |96      |560     |0       |0       |
+|    u_ADconfig                |AD_config            |176    |118     |25      |130     |0       |0       |
+|    u_gen_sp                  |gen_sp               |276    |179     |71      |129     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2980   |2354    |306     |2135    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |3      |0       |0       |3       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |172    |120     |17      |135     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2780   |2220    |289     |1972    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |7      |2       |0       |7       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |8      |6       |0       |8       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2268   |1823    |253     |1555    |22      |0       |
+|        channelPart           |channel_part_8478    |142    |136     |3       |131     |0       |0       |
+|        fifo_adc              |fifo_adc             |52     |43      |9       |36      |0       |0       |
+|        ram_switch            |ram_switch           |1790   |1428    |197     |1187    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |229    |202     |27      |124     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |15      |0       |0       |
+|          insert              |insert               |1001   |667     |170     |705     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |560    |559     |0       |358     |0       |0       |
+|        read_ram_i            |read_ram             |264    |206     |44      |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |211    |171     |40      |142     |0       |0       |
+|          read_ram_data       |read_ram_data        |49     |31      |4       |35      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |319    |225     |36      |278     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3143   |2360    |349     |2190    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |188    |127     |17      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2927   |2207    |332     |2015    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |3      |3       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2424   |1820    |290     |1587    |22      |1       |
+|        channelPart           |channel_part_8478    |236    |232     |3       |148     |0       |0       |
+|        fifo_adc              |fifo_adc             |64     |55      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |1729   |1244    |197     |1154    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |216    |189     |27      |120     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |17      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |17      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|          insert              |insert               |1011   |560     |170     |714     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |502    |495     |0       |320     |0       |0       |
+|        read_ram_i            |read_ram_rev         |366    |264     |81      |211     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |296    |211     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |70     |53      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9861  
+    #2         2       3890  
+    #3         3       1457  
+    #4         4       645   
+    #5        5-10     1045  
+    #6       11-50     588   
+    #7       51-100     28   
+    #8        >500      1    
+  Average     2.90           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.053232s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (172.0%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1100 MB, peak memory is 1173 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17432, tinst num: 6748, tnode num: 96508, tedge num: 124025.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.650303s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.4%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1105 MB, peak memory is 1173 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.525879s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (100.4%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1107 MB, peak memory is 1173 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6748
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17610, pip num: 176978
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 683
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3244 valid insts, and 488283 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.291538s wall, 69.781250s user + 0.140625s system = 69.921875s CPU (679.4%)
+
+RUN-1004 : used memory is 1271 MB, reserved memory is 1267 MB, peak memory is 1386 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_154332.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_161244.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_161244.log
new file mode 100644
index 0000000..08296bd
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_161244.log
@@ -0,0 +1,1893 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:12:44 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.106589s wall, 2.000000s user + 0.093750s system = 2.093750s CPU (99.4%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2277 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17728 instances
+RUN-0007 : 7336 luts, 9169 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20312 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13303 nets have 2 pins
+RUN-1001 : 5720 nets have [3 - 5] pins
+RUN-1001 : 876 nets have [6 - 10] pins
+RUN-1001 : 157 nets have [11 - 20] pins
+RUN-1001 : 182 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     795     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3597     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17726 instances, 7336 luts, 9169 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84807, tnet num: 20134, tinst num: 17726, tnode num: 115275, tedge num: 136096.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.117363s wall, 1.109375s user + 0.015625s system = 1.125000s CPU (100.7%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 515 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.877111s wall, 1.843750s user + 0.031250s system = 1.875000s CPU (99.9%)
+
+PHY-3001 : Found 3485 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.98345e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17726.
+PHY-3001 : Level 1 #clusters 2034.
+PHY-3001 : End clustering;  0.122641s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (89.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.24965e+06, overlap = 500
+PHY-3002 : Step(2): len = 1.17654e+06, overlap = 522.125
+PHY-3002 : Step(3): len = 826469, overlap = 607.312
+PHY-3002 : Step(4): len = 771090, overlap = 664.25
+PHY-3002 : Step(5): len = 602310, overlap = 782.531
+PHY-3002 : Step(6): len = 530001, overlap = 828.344
+PHY-3002 : Step(7): len = 453332, overlap = 917.719
+PHY-3002 : Step(8): len = 426339, overlap = 959.719
+PHY-3002 : Step(9): len = 380328, overlap = 996.625
+PHY-3002 : Step(10): len = 355845, overlap = 1028.44
+PHY-3002 : Step(11): len = 314819, overlap = 1091.38
+PHY-3002 : Step(12): len = 296609, overlap = 1122.94
+PHY-3002 : Step(13): len = 259797, overlap = 1191.75
+PHY-3002 : Step(14): len = 245853, overlap = 1220
+PHY-3002 : Step(15): len = 219697, overlap = 1251.47
+PHY-3002 : Step(16): len = 210846, overlap = 1288.69
+PHY-3002 : Step(17): len = 188537, overlap = 1332.53
+PHY-3002 : Step(18): len = 178996, overlap = 1397.72
+PHY-3002 : Step(19): len = 165258, overlap = 1440.25
+PHY-3002 : Step(20): len = 153571, overlap = 1473.97
+PHY-3002 : Step(21): len = 147807, overlap = 1491.09
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.62818e-07
+PHY-3002 : Step(22): len = 146477, overlap = 1443.72
+PHY-3002 : Step(23): len = 179974, overlap = 1337.16
+PHY-3002 : Step(24): len = 187470, overlap = 1269.59
+PHY-3002 : Step(25): len = 192598, overlap = 1177.91
+PHY-3002 : Step(26): len = 191134, overlap = 1135.75
+PHY-3002 : Step(27): len = 188302, overlap = 1178.97
+PHY-3002 : Step(28): len = 185119, overlap = 1188.62
+PHY-3002 : Step(29): len = 181768, overlap = 1220.94
+PHY-3002 : Step(30): len = 179867, overlap = 1211.94
+PHY-3002 : Step(31): len = 176837, overlap = 1225.78
+PHY-3002 : Step(32): len = 175748, overlap = 1238.62
+PHY-3002 : Step(33): len = 174533, overlap = 1237.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.92564e-06
+PHY-3002 : Step(34): len = 177537, overlap = 1232.19
+PHY-3002 : Step(35): len = 190076, overlap = 1174.53
+PHY-3002 : Step(36): len = 196691, overlap = 1106.81
+PHY-3002 : Step(37): len = 201654, overlap = 1113.47
+PHY-3002 : Step(38): len = 204292, overlap = 1095.34
+PHY-3002 : Step(39): len = 205156, overlap = 1079.97
+PHY-3002 : Step(40): len = 204415, overlap = 1055.16
+PHY-3002 : Step(41): len = 205280, overlap = 1036.44
+PHY-3002 : Step(42): len = 202709, overlap = 1011.09
+PHY-3002 : Step(43): len = 201159, overlap = 1003.22
+PHY-3002 : Step(44): len = 198099, overlap = 996.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.85127e-06
+PHY-3002 : Step(45): len = 206332, overlap = 962.156
+PHY-3002 : Step(46): len = 222124, overlap = 923.125
+PHY-3002 : Step(47): len = 232110, overlap = 890.594
+PHY-3002 : Step(48): len = 237185, overlap = 884.938
+PHY-3002 : Step(49): len = 238214, overlap = 865.812
+PHY-3002 : Step(50): len = 237897, overlap = 862.875
+PHY-3002 : Step(51): len = 234960, overlap = 849.781
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.70254e-06
+PHY-3002 : Step(52): len = 245790, overlap = 850.438
+PHY-3002 : Step(53): len = 265340, overlap = 775.75
+PHY-3002 : Step(54): len = 277710, overlap = 699.906
+PHY-3002 : Step(55): len = 287238, overlap = 660.406
+PHY-3002 : Step(56): len = 290393, overlap = 647.906
+PHY-3002 : Step(57): len = 291809, overlap = 634.094
+PHY-3002 : Step(58): len = 290334, overlap = 633.625
+PHY-3002 : Step(59): len = 289852, overlap = 638.594
+PHY-3002 : Step(60): len = 287355, overlap = 650.406
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.54051e-05
+PHY-3002 : Step(61): len = 308726, overlap = 618.062
+PHY-3002 : Step(62): len = 334758, overlap = 562.812
+PHY-3002 : Step(63): len = 343943, overlap = 554.375
+PHY-3002 : Step(64): len = 348076, overlap = 513.906
+PHY-3002 : Step(65): len = 345362, overlap = 483.219
+PHY-3002 : Step(66): len = 344184, overlap = 475.906
+PHY-3002 : Step(67): len = 341236, overlap = 473.344
+PHY-3002 : Step(68): len = 340825, overlap = 472.188
+PHY-3002 : Step(69): len = 338597, overlap = 476.438
+PHY-3002 : Step(70): len = 337260, overlap = 477.094
+PHY-3002 : Step(71): len = 335373, overlap = 478.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.08102e-05
+PHY-3002 : Step(72): len = 359978, overlap = 453.25
+PHY-3002 : Step(73): len = 373860, overlap = 405.281
+PHY-3002 : Step(74): len = 370068, overlap = 415.875
+PHY-3002 : Step(75): len = 370799, overlap = 424.562
+PHY-3002 : Step(76): len = 373724, overlap = 396.062
+PHY-3002 : Step(77): len = 377075, overlap = 371.438
+PHY-3002 : Step(78): len = 375800, overlap = 347.281
+PHY-3002 : Step(79): len = 377669, overlap = 344.344
+PHY-3002 : Step(80): len = 378865, overlap = 355.219
+PHY-3002 : Step(81): len = 379339, overlap = 361.906
+PHY-3002 : Step(82): len = 377595, overlap = 372.281
+PHY-3002 : Step(83): len = 378279, overlap = 381.125
+PHY-3002 : Step(84): len = 377849, overlap = 387.312
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.16204e-05
+PHY-3002 : Step(85): len = 399303, overlap = 370.719
+PHY-3002 : Step(86): len = 412350, overlap = 350.938
+PHY-3002 : Step(87): len = 409749, overlap = 352.281
+PHY-3002 : Step(88): len = 411298, overlap = 340.625
+PHY-3002 : Step(89): len = 415032, overlap = 336
+PHY-3002 : Step(90): len = 418650, overlap = 334
+PHY-3002 : Step(91): len = 417413, overlap = 323.688
+PHY-3002 : Step(92): len = 417742, overlap = 314.5
+PHY-3002 : Step(93): len = 418921, overlap = 295.375
+PHY-3002 : Step(94): len = 420802, overlap = 279.438
+PHY-3002 : Step(95): len = 420203, overlap = 275.969
+PHY-3002 : Step(96): len = 421119, overlap = 291.938
+PHY-3002 : Step(97): len = 422207, overlap = 297.281
+PHY-3002 : Step(98): len = 421586, overlap = 324.969
+PHY-3002 : Step(99): len = 420051, overlap = 324.625
+PHY-3002 : Step(100): len = 421376, overlap = 326
+PHY-3002 : Step(101): len = 421769, overlap = 316.531
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000123241
+PHY-3002 : Step(102): len = 438041, overlap = 289.875
+PHY-3002 : Step(103): len = 447734, overlap = 273.969
+PHY-3002 : Step(104): len = 447576, overlap = 266.312
+PHY-3002 : Step(105): len = 448976, overlap = 263.031
+PHY-3002 : Step(106): len = 450801, overlap = 264.531
+PHY-3002 : Step(107): len = 453201, overlap = 265.719
+PHY-3002 : Step(108): len = 452428, overlap = 271.906
+PHY-3002 : Step(109): len = 453431, overlap = 265.781
+PHY-3002 : Step(110): len = 455144, overlap = 257.125
+PHY-3002 : Step(111): len = 457588, overlap = 251.938
+PHY-3002 : Step(112): len = 455925, overlap = 256.969
+PHY-3002 : Step(113): len = 455890, overlap = 262.594
+PHY-3002 : Step(114): len = 457078, overlap = 266.531
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000245703
+PHY-3002 : Step(115): len = 470605, overlap = 249.781
+PHY-3002 : Step(116): len = 482228, overlap = 223.844
+PHY-3002 : Step(117): len = 485653, overlap = 218.875
+PHY-3002 : Step(118): len = 489001, overlap = 220.5
+PHY-3002 : Step(119): len = 491530, overlap = 223.812
+PHY-3002 : Step(120): len = 493011, overlap = 220.906
+PHY-3002 : Step(121): len = 490925, overlap = 231
+PHY-3002 : Step(122): len = 490637, overlap = 234.219
+PHY-3002 : Step(123): len = 491585, overlap = 221.188
+PHY-3002 : Step(124): len = 492585, overlap = 224.688
+PHY-3002 : Step(125): len = 491425, overlap = 232.312
+PHY-3002 : Step(126): len = 490758, overlap = 232.5
+PHY-3002 : Step(127): len = 491881, overlap = 222.938
+PHY-3002 : Step(128): len = 492650, overlap = 215.344
+PHY-3002 : Step(129): len = 492042, overlap = 219.75
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000468487
+PHY-3002 : Step(130): len = 500461, overlap = 218.75
+PHY-3002 : Step(131): len = 508496, overlap = 219.719
+PHY-3002 : Step(132): len = 508923, overlap = 216.25
+PHY-3002 : Step(133): len = 509847, overlap = 208.25
+PHY-3002 : Step(134): len = 512889, overlap = 209.469
+PHY-3002 : Step(135): len = 514969, overlap = 209.031
+PHY-3002 : Step(136): len = 514507, overlap = 208.156
+PHY-3002 : Step(137): len = 514917, overlap = 199.719
+PHY-3002 : Step(138): len = 517091, overlap = 200.5
+PHY-3002 : Step(139): len = 519617, overlap = 194.438
+PHY-3002 : Step(140): len = 519163, overlap = 192.312
+PHY-3002 : Step(141): len = 519602, overlap = 193.188
+PHY-3002 : Step(142): len = 521025, overlap = 186.25
+PHY-3002 : Step(143): len = 522195, overlap = 182.625
+PHY-3002 : Step(144): len = 521792, overlap = 182.031
+PHY-3002 : Step(145): len = 521758, overlap = 181.375
+PHY-3002 : Step(146): len = 522931, overlap = 180.312
+PHY-3002 : Step(147): len = 524194, overlap = 176.688
+PHY-3002 : Step(148): len = 523421, overlap = 174.469
+PHY-3002 : Step(149): len = 523280, overlap = 170.062
+PHY-3002 : Step(150): len = 524204, overlap = 170.844
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000933672
+PHY-3002 : Step(151): len = 530197, overlap = 173.562
+PHY-3002 : Step(152): len = 539114, overlap = 165.969
+PHY-3002 : Step(153): len = 541437, overlap = 161.438
+PHY-3002 : Step(154): len = 543376, overlap = 156.438
+PHY-3002 : Step(155): len = 545292, overlap = 153.469
+PHY-3002 : Step(156): len = 547670, overlap = 155.094
+PHY-3002 : Step(157): len = 548045, overlap = 153.469
+PHY-3002 : Step(158): len = 548980, overlap = 158.25
+PHY-3002 : Step(159): len = 550187, overlap = 157.406
+PHY-3002 : Step(160): len = 550531, overlap = 160.781
+PHY-3002 : Step(161): len = 549683, overlap = 157.312
+PHY-3002 : Step(162): len = 548989, overlap = 156
+PHY-3002 : Step(163): len = 549403, overlap = 154.812
+PHY-3002 : Step(164): len = 549619, overlap = 154.5
+PHY-3002 : Step(165): len = 549024, overlap = 152.406
+PHY-3002 : Step(166): len = 548699, overlap = 154.188
+PHY-3002 : Step(167): len = 548967, overlap = 155.719
+PHY-3002 : Step(168): len = 548919, overlap = 156.344
+PHY-3002 : Step(169): len = 548281, overlap = 158.156
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00161218
+PHY-3002 : Step(170): len = 551058, overlap = 157.406
+PHY-3002 : Step(171): len = 554912, overlap = 157.344
+PHY-3002 : Step(172): len = 555778, overlap = 154.531
+PHY-3002 : Step(173): len = 556514, overlap = 154.875
+PHY-3002 : Step(174): len = 557250, overlap = 151.844
+PHY-3002 : Step(175): len = 557664, overlap = 150.969
+PHY-3002 : Step(176): len = 557826, overlap = 151.844
+PHY-3002 : Step(177): len = 558446, overlap = 147.219
+PHY-3002 : Step(178): len = 559773, overlap = 147.938
+PHY-3002 : Step(179): len = 561128, overlap = 143.906
+PHY-3002 : Step(180): len = 561360, overlap = 143.062
+PHY-3002 : Step(181): len = 561548, overlap = 144.125
+PHY-3002 : Step(182): len = 561902, overlap = 142.656
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00294263
+PHY-3002 : Step(183): len = 563951, overlap = 141.219
+PHY-3002 : Step(184): len = 568603, overlap = 138.812
+PHY-3002 : Step(185): len = 570110, overlap = 135.719
+PHY-3002 : Step(186): len = 571798, overlap = 128.094
+PHY-3002 : Step(187): len = 573523, overlap = 119.844
+PHY-3002 : Step(188): len = 575606, overlap = 121.406
+PHY-3002 : Step(189): len = 576446, overlap = 121.906
+PHY-3002 : Step(190): len = 576878, overlap = 122.562
+PHY-3002 : Step(191): len = 577089, overlap = 122.125
+PHY-3002 : Step(192): len = 577130, overlap = 121.875
+PHY-3002 : Step(193): len = 577056, overlap = 120.594
+PHY-3002 : Step(194): len = 577225, overlap = 123.25
+PHY-3002 : Step(195): len = 577484, overlap = 125.406
+PHY-3002 : Step(196): len = 577699, overlap = 124.438
+PHY-3002 : Step(197): len = 577933, overlap = 124.312
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014761s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (105.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20312.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715192, over cnt = 1630(4%), over = 7273, worst = 30
+PHY-1001 : End global iterations;  0.724524s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (144.5%)
+
+PHY-1001 : Congestion index: top1 = 80.15, top5 = 61.68, top10 = 52.27, top15 = 46.31.
+PHY-3001 : End congestion estimation;  0.953914s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (132.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.836993s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.96148e-05
+PHY-3002 : Step(198): len = 651157, overlap = 66.9062
+PHY-3002 : Step(199): len = 658474, overlap = 67.6875
+PHY-3002 : Step(200): len = 652229, overlap = 79.125
+PHY-3002 : Step(201): len = 647766, overlap = 74.4375
+PHY-3002 : Step(202): len = 652924, overlap = 79.5312
+PHY-3002 : Step(203): len = 664761, overlap = 88.3438
+PHY-3002 : Step(204): len = 668427, overlap = 92.4062
+PHY-3002 : Step(205): len = 669100, overlap = 82.5625
+PHY-3002 : Step(206): len = 671302, overlap = 86.8125
+PHY-3002 : Step(207): len = 677046, overlap = 87.8438
+PHY-3002 : Step(208): len = 677484, overlap = 82.7812
+PHY-3002 : Step(209): len = 678397, overlap = 79.2188
+PHY-3002 : Step(210): len = 681707, overlap = 70.6875
+PHY-3002 : Step(211): len = 683572, overlap = 68.9688
+PHY-3002 : Step(212): len = 683866, overlap = 67.25
+PHY-3002 : Step(213): len = 683207, overlap = 64.75
+PHY-3002 : Step(214): len = 682054, overlap = 61.6562
+PHY-3002 : Step(215): len = 682092, overlap = 54.5
+PHY-3002 : Step(216): len = 682016, overlap = 51.0312
+PHY-3002 : Step(217): len = 681392, overlap = 43.3125
+PHY-3002 : Step(218): len = 678931, overlap = 37.3438
+PHY-3002 : Step(219): len = 677641, overlap = 39.6562
+PHY-3002 : Step(220): len = 675697, overlap = 37.5938
+PHY-3002 : Step(221): len = 675181, overlap = 34.6875
+PHY-3002 : Step(222): len = 674045, overlap = 32.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00019923
+PHY-3002 : Step(223): len = 674643, overlap = 29.6875
+PHY-3002 : Step(224): len = 677539, overlap = 26.4375
+PHY-3002 : Step(225): len = 682694, overlap = 24.4375
+PHY-3002 : Step(226): len = 687038, overlap = 21.7188
+PHY-3002 : Step(227): len = 689726, overlap = 23.7812
+PHY-3002 : Step(228): len = 688124, overlap = 26.4062
+PHY-3002 : Step(229): len = 687821, overlap = 26.8125
+PHY-3002 : Step(230): len = 685752, overlap = 25.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000398459
+PHY-3002 : Step(231): len = 691152, overlap = 23.25
+PHY-3002 : Step(232): len = 697951, overlap = 24.2188
+PHY-3002 : Step(233): len = 703063, overlap = 23.9062
+PHY-3002 : Step(234): len = 709396, overlap = 23.6562
+PHY-3002 : Step(235): len = 712484, overlap = 22.9375
+PHY-3002 : Step(236): len = 715126, overlap = 22.5
+PHY-3002 : Step(237): len = 715699, overlap = 23
+PHY-3002 : Step(238): len = 717189, overlap = 23.8125
+PHY-3002 : Step(239): len = 716213, overlap = 24.3438
+PHY-3002 : Step(240): len = 715475, overlap = 25.7812
+PHY-3002 : Step(241): len = 714823, overlap = 29.5938
+PHY-3002 : Step(242): len = 717462, overlap = 31.5312
+PHY-3002 : Step(243): len = 715655, overlap = 30.3438
+PHY-3002 : Step(244): len = 715389, overlap = 30.7188
+PHY-3002 : Step(245): len = 715210, overlap = 26.0312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000796919
+PHY-3002 : Step(246): len = 718325, overlap = 27.4062
+PHY-3002 : Step(247): len = 724929, overlap = 27.6875
+PHY-3002 : Step(248): len = 733755, overlap = 31.4375
+PHY-3002 : Step(249): len = 743995, overlap = 31.9688
+PHY-3002 : Step(250): len = 744925, overlap = 31.3125
+PHY-3002 : Step(251): len = 743473, overlap = 30.9062
+PHY-3002 : Step(252): len = 741343, overlap = 30.9375
+PHY-3002 : Step(253): len = 739807, overlap = 31.7188
+PHY-3002 : Step(254): len = 740895, overlap = 29.75
+PHY-3002 : Step(255): len = 740355, overlap = 31.1875
+PHY-3002 : Step(256): len = 743519, overlap = 31.8438
+PHY-3002 : Step(257): len = 749131, overlap = 30.1562
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00153417
+PHY-3002 : Step(258): len = 749178, overlap = 29.5312
+PHY-3002 : Step(259): len = 750564, overlap = 29.75
+PHY-3002 : Step(260): len = 751823, overlap = 32.3438
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 46/20312.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 830216, over cnt = 2832(8%), over = 14611, worst = 101
+PHY-1001 : End global iterations;  1.477953s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 116.31, top5 = 77.83, top10 = 66.35, top15 = 59.64.
+PHY-3001 : End congestion estimation;  1.755989s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (129.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.871374s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000119578
+PHY-3002 : Step(261): len = 752130, overlap = 221.969
+PHY-3002 : Step(262): len = 753440, overlap = 190.75
+PHY-3002 : Step(263): len = 742254, overlap = 169.5
+PHY-3002 : Step(264): len = 736095, overlap = 151.438
+PHY-3002 : Step(265): len = 728110, overlap = 140.312
+PHY-3002 : Step(266): len = 724824, overlap = 132.688
+PHY-3002 : Step(267): len = 718216, overlap = 126.125
+PHY-3002 : Step(268): len = 714600, overlap = 122.719
+PHY-3002 : Step(269): len = 710207, overlap = 123.062
+PHY-3002 : Step(270): len = 705599, overlap = 116.906
+PHY-3002 : Step(271): len = 702863, overlap = 120.156
+PHY-3002 : Step(272): len = 698053, overlap = 120.219
+PHY-3002 : Step(273): len = 694835, overlap = 124.062
+PHY-3002 : Step(274): len = 692667, overlap = 121.281
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000239157
+PHY-3002 : Step(275): len = 693077, overlap = 118.406
+PHY-3002 : Step(276): len = 696309, overlap = 109.344
+PHY-3002 : Step(277): len = 699876, overlap = 100.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000478314
+PHY-3002 : Step(278): len = 705248, overlap = 88.375
+PHY-3002 : Step(279): len = 713669, overlap = 78.9688
+PHY-3002 : Step(280): len = 718298, overlap = 76.125
+PHY-3002 : Step(281): len = 717113, overlap = 76.8438
+PHY-3002 : Step(282): len = 716805, overlap = 81.6562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000956628
+PHY-3002 : Step(283): len = 720516, overlap = 76.5938
+PHY-3002 : Step(284): len = 725150, overlap = 73
+PHY-3002 : Step(285): len = 730205, overlap = 69.75
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84807, tnet num: 20134, tinst num: 17726, tnode num: 115275, tedge num: 136096.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.411196s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (100.8%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 565 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 401.78 peak overflow 3.47
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 669/20312.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 827816, over cnt = 3152(8%), over = 12458, worst = 87
+PHY-1001 : End global iterations;  1.302958s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (145.1%)
+
+PHY-1001 : Congestion index: top1 = 84.68, top5 = 63.75, top10 = 55.81, top15 = 51.32.
+PHY-1001 : End incremental global routing;  1.627652s wall, 2.187500s user + 0.031250s system = 2.218750s CPU (136.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20134 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.235416s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (99.9%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17590 has valid locations, 337 needs to be replaced
+PHY-3001 : design contains 18012 instances, 7435 luts, 9356 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6024 pins
+PHY-3001 : Found 3522 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 753123
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17029/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843800, over cnt = 3168(9%), over = 12439, worst = 87
+PHY-1001 : End global iterations;  0.237574s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 84.98, top5 = 64.00, top10 = 56.04, top15 = 51.55.
+PHY-3001 : End congestion estimation;  0.508719s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (119.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85978, tnet num: 20420, tinst num: 18012, tnode num: 117037, tedge num: 137866.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.414872s wall, 1.359375s user + 0.062500s system = 1.421875s CPU (100.5%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 641 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.378660s wall, 2.312500s user + 0.062500s system = 2.375000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(286): len = 751960, overlap = 0.125
+PHY-3002 : Step(287): len = 751311, overlap = 0.1875
+PHY-3002 : Step(288): len = 750989, overlap = 0.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17140/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841216, over cnt = 3181(9%), over = 12503, worst = 87
+PHY-1001 : End global iterations;  0.189243s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (115.6%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 64.43, top10 = 56.38, top15 = 51.79.
+PHY-3001 : End congestion estimation;  0.438723s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (106.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.907159s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000519413
+PHY-3002 : Step(289): len = 750776, overlap = 71.8125
+PHY-3002 : Step(290): len = 750836, overlap = 71.2812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00103883
+PHY-3002 : Step(291): len = 751049, overlap = 71.1562
+PHY-3002 : Step(292): len = 751690, overlap = 71.4688
+PHY-3001 : Final: Len = 751690, Over = 71.4688
+PHY-3001 : End incremental placement;  4.863805s wall, 5.140625s user + 0.265625s system = 5.406250s CPU (111.2%)
+
+OPT-1001 : Total overflow 406.88 peak overflow 3.47
+OPT-1001 : End high-fanout net optimization;  8.248371s wall, 9.187500s user + 0.296875s system = 9.484375s CPU (115.0%)
+
+OPT-1001 : Current memory(MB): used = 728, reserve = 716, peak = 744.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17062/20598.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 844256, over cnt = 3150(8%), over = 11512, worst = 87
+PHY-1002 : len = 899472, over cnt = 2367(6%), over = 6351, worst = 71
+PHY-1002 : len = 940680, over cnt = 1094(3%), over = 2682, worst = 17
+PHY-1002 : len = 969896, over cnt = 275(0%), over = 575, worst = 11
+PHY-1002 : len = 978832, over cnt = 10(0%), over = 21, worst = 5
+PHY-1001 : End global iterations;  2.110905s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (135.5%)
+
+PHY-1001 : Congestion index: top1 = 62.31, top5 = 54.50, top10 = 50.53, top15 = 47.93.
+OPT-1001 : End congestion update;  2.366801s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (131.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20420 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.772973s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.0%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 75 cells processed and 7900 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 20 cells processed and 1150 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 9 cells processed and 466 slack improved
+OPT-1001 : End global optimization;  3.183788s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (123.2%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 695, peak = 744.
+OPT-1001 : End physical optimization;  13.450620s wall, 15.046875s user + 0.375000s system = 15.421875s CPU (114.7%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7435 LUT to BLE ...
+SYN-4008 : Packed 7435 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6223 remaining SEQ's ...
+SYN-4005 : Packed 4034 SEQ with LUT/SLICE
+SYN-4006 : 574 single LUT's are left
+SYN-4006 : 2189 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9624/13355 primitive instances ...
+PHY-3001 : End packing;  1.552824s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6730 instances
+RUN-1001 : 3291 mslices, 3291 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17592 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9926 nets have 2 pins
+RUN-1001 : 5996 nets have [3 - 5] pins
+RUN-1001 : 988 nets have [6 - 10] pins
+RUN-1001 : 288 nets have [11 - 20] pins
+RUN-1001 : 363 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6728 instances, 6582 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3532 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 758274, Over = 242
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7597/17592.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919464, over cnt = 2080(5%), over = 3365, worst = 8
+PHY-1002 : len = 928128, over cnt = 1270(3%), over = 1736, worst = 8
+PHY-1002 : len = 941112, over cnt = 490(1%), over = 629, worst = 6
+PHY-1002 : len = 945536, over cnt = 262(0%), over = 349, worst = 6
+PHY-1002 : len = 952448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.628329s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (145.9%)
+
+PHY-1001 : Congestion index: top1 = 59.46, top5 = 52.39, top10 = 48.50, top15 = 46.05.
+PHY-3001 : End congestion estimation;  2.011450s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (137.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73729, tnet num: 17414, tinst num: 6728, tnode num: 96334, tedge num: 123854.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.615166s wall, 1.562500s user + 0.046875s system = 1.609375s CPU (99.6%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 613 MB, peak memory is 744 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17414 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.466147s wall, 2.390625s user + 0.062500s system = 2.453125s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.53708e-05
+PHY-3002 : Step(293): len = 742128, overlap = 236.5
+PHY-3002 : Step(294): len = 733710, overlap = 236
+PHY-3002 : Step(295): len = 727678, overlap = 239.75
+PHY-3002 : Step(296): len = 722702, overlap = 249
+PHY-3002 : Step(297): len = 719078, overlap = 252.75
+PHY-3002 : Step(298): len = 715606, overlap = 247.75
+PHY-3002 : Step(299): len = 711970, overlap = 247.5
+PHY-3002 : Step(300): len = 708509, overlap = 246
+PHY-3002 : Step(301): len = 704883, overlap = 246
+PHY-3002 : Step(302): len = 701553, overlap = 254.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000110742
+PHY-3002 : Step(303): len = 705427, overlap = 240.5
+PHY-3002 : Step(304): len = 710831, overlap = 226.5
+PHY-3002 : Step(305): len = 711032, overlap = 228.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000221483
+PHY-3002 : Step(306): len = 720566, overlap = 217.25
+PHY-3002 : Step(307): len = 729092, overlap = 212
+PHY-3002 : Step(308): len = 727412, overlap = 210.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.340220s wall, 0.218750s user + 0.515625s system = 0.734375s CPU (215.9%)
+
+PHY-3001 : Trial Legalized: Len = 894771
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 455/17592.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0115e+06, over cnt = 2858(8%), over = 4977, worst = 9
+PHY-1002 : len = 1.03e+06, over cnt = 1859(5%), over = 2801, worst = 7
+PHY-1002 : len = 1.05256e+06, over cnt = 791(2%), over = 1097, worst = 7
+PHY-1002 : len = 1.06812e+06, over cnt = 151(0%), over = 214, worst = 6
+PHY-1002 : len = 1.0719e+06, over cnt = 15(0%), over = 21, worst = 3
+PHY-1001 : End global iterations;  2.495551s wall, 3.671875s user + 0.031250s system = 3.703125s CPU (148.4%)
+
+PHY-1001 : Congestion index: top1 = 63.08, top5 = 56.82, top10 = 53.30, top15 = 50.91.
+PHY-3001 : End congestion estimation;  2.944011s wall, 4.125000s user + 0.031250s system = 4.156250s CPU (141.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17414 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.847932s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000162887
+PHY-3002 : Step(309): len = 849990, overlap = 68.75
+PHY-3002 : Step(310): len = 829172, overlap = 94.5
+PHY-3002 : Step(311): len = 815674, overlap = 112.25
+PHY-3002 : Step(312): len = 804784, overlap = 131.5
+PHY-3002 : Step(313): len = 796641, overlap = 149.75
+PHY-3002 : Step(314): len = 790370, overlap = 168.25
+PHY-3002 : Step(315): len = 786187, overlap = 173.75
+PHY-3002 : Step(316): len = 782439, overlap = 185
+PHY-3002 : Step(317): len = 779344, overlap = 192.5
+PHY-3002 : Step(318): len = 776567, overlap = 195.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000325773
+PHY-3002 : Step(319): len = 781270, overlap = 189.25
+PHY-3002 : Step(320): len = 784663, overlap = 179.25
+PHY-3002 : Step(321): len = 786516, overlap = 176.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000585907
+PHY-3002 : Step(322): len = 792669, overlap = 172
+PHY-3002 : Step(323): len = 795785, overlap = 171.75
+PHY-3002 : Step(324): len = 798462, overlap = 166.75
+PHY-3002 : Step(325): len = 799847, overlap = 163.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.077709s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (100.5%)
+
+PHY-3001 : Legalized: Len = 851078, Over = 0
+PHY-3001 : Spreading special nets. 473 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.109022s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.3%)
+
+PHY-3001 : 725 instances has been re-located, deltaX = 258, deltaY = 496, maxDist = 5.
+PHY-3001 : Final: Len = 862753, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73729, tnet num: 17414, tinst num: 6731, tnode num: 96334, tedge num: 123854.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.853630s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (99.5%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 648 MB, peak memory is 744 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3114/17592.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 992120, over cnt = 2617(7%), over = 4356, worst = 9
+PHY-1002 : len = 1.00517e+06, over cnt = 1651(4%), over = 2424, worst = 9
+PHY-1002 : len = 1.0228e+06, over cnt = 763(2%), over = 1101, worst = 5
+PHY-1002 : len = 1.03312e+06, over cnt = 315(0%), over = 425, worst = 5
+PHY-1002 : len = 1.03937e+06, over cnt = 57(0%), over = 64, worst = 3
+PHY-1001 : End global iterations;  2.119781s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (151.1%)
+
+PHY-1001 : Congestion index: top1 = 60.65, top5 = 54.54, top10 = 51.21, top15 = 48.94.
+PHY-1001 : End incremental global routing;  2.489377s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (143.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17414 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.865544s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.3%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6639 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 1559 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 865013
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16104/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04155e+06, over cnt = 105(0%), over = 124, worst = 3
+PHY-1002 : len = 1.04152e+06, over cnt = 66(0%), over = 67, worst = 2
+PHY-1002 : len = 1.04221e+06, over cnt = 16(0%), over = 17, worst = 2
+PHY-1002 : len = 1.0423e+06, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 1.04295e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.793675s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (106.3%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.63, top10 = 51.22, top15 = 48.96.
+PHY-3001 : End congestion estimation;  1.113814s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (103.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17432, tinst num: 6748, tnode num: 96508, tedge num: 124025.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.823813s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.2%)
+
+RUN-1004 : used memory is 671 MB, reserved memory is 676 MB, peak memory is 744 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.693043s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(326): len = 864666, overlap = 0.25
+PHY-3002 : Step(327): len = 864319, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16100/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04232e+06, over cnt = 38(0%), over = 49, worst = 4
+PHY-1002 : len = 1.04246e+06, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 1.04258e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.04263e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.593346s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.62, top10 = 51.20, top15 = 48.95.
+PHY-3001 : End congestion estimation;  0.899346s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.852567s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000564311
+PHY-3002 : Step(328): len = 864261, overlap = 1
+PHY-3002 : Step(329): len = 864236, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005523s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (282.9%)
+
+PHY-3001 : Legalized: Len = 864374, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.057723s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.3%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 864420, Over = 0
+PHY-3001 : End incremental placement;  6.016159s wall, 6.140625s user + 0.140625s system = 6.281250s CPU (104.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.944631s wall, 11.156250s user + 0.140625s system = 11.296875s CPU (113.6%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 743, peak = 753.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16076/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04234e+06, over cnt = 63(0%), over = 71, worst = 3
+PHY-1002 : len = 1.04238e+06, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 1.0427e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.04274e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.04276e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.793172s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (102.4%)
+
+PHY-1001 : Congestion index: top1 = 60.84, top5 = 54.63, top10 = 51.21, top15 = 48.94.
+OPT-1001 : End congestion update;  1.104259s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (103.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.845547s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1083 TNS -1716 NUM_FEPS 4
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6660 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6748 instances, 6599 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3597 pins
+PHY-3001 : Found 1559 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 867673, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.057694s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.3%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 10, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 868173, Over = 0
+PHY-3001 : End incremental legalization;  0.368933s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.6%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 29 cells processed and 8950 slack improved
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.463471s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (101.5%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 743, peak = 753.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.704874s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15940/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04626e+06, over cnt = 114(0%), over = 144, worst = 4
+PHY-1002 : len = 1.04623e+06, over cnt = 55(0%), over = 59, worst = 2
+PHY-1002 : len = 1.04641e+06, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 1.0467e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.04695e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.832919s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 60.86, top5 = 54.68, top10 = 51.31, top15 = 49.03.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.707961s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1097 TNS -1632 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 60.448276
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1097ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17610 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17610 nets
+OPT-1001 : End physical optimization;  17.175645s wall, 18.546875s user + 0.156250s system = 18.703125s CPU (108.9%)
+
+RUN-1003 : finish command "place" in  60.848906s wall, 94.781250s user + 6.953125s system = 101.734375s CPU (167.2%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 616 MB, peak memory is 753 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.677325s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (173.3%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 617 MB, peak memory is 753 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6750 instances
+RUN-1001 : 3299 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17610 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9923 nets have 2 pins
+RUN-1001 : 5995 nets have [3 - 5] pins
+RUN-1001 : 996 nets have [6 - 10] pins
+RUN-1001 : 294 nets have [11 - 20] pins
+RUN-1001 : 374 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17432, tinst num: 6748, tnode num: 96508, tedge num: 124025.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.603018s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.4%)
+
+RUN-1004 : used memory is 613 MB, reserved memory is 602 MB, peak memory is 753 MB
+PHY-1001 : 3299 mslices, 3300 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 976752, over cnt = 2835(8%), over = 4759, worst = 9
+PHY-1002 : len = 993576, over cnt = 1860(5%), over = 2759, worst = 7
+PHY-1002 : len = 1.01687e+06, over cnt = 717(2%), over = 1000, worst = 6
+PHY-1002 : len = 1.03206e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.03218e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.957351s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 60.09, top5 = 54.03, top10 = 50.82, top15 = 48.68.
+PHY-1001 : End global routing;  3.276543s wall, 4.359375s user + 0.031250s system = 4.390625s CPU (134.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 721, reserve = 721, peak = 753.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 989, reserve = 989, peak = 989.
+PHY-1001 : End build detailed router design. 3.952621s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270184, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.207701s wall, 5.203125s user + 0.000000s system = 5.203125s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270240, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.452746s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1026, peak = 1025.
+PHY-1001 : End phase 1; 5.672193s wall, 5.671875s user + 0.000000s system = 5.671875s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.50711e+06, over cnt = 2085(0%), over = 2089, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1043, peak = 1044.
+PHY-1001 : End initial routed; 40.593882s wall, 69.343750s user + 0.250000s system = 69.593750s CPU (171.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16533(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.798   |  -3.771   |   5   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.230353s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1052, peak = 1051.
+PHY-1001 : End phase 2; 43.824303s wall, 72.546875s user + 0.250000s system = 72.796875s CPU (166.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 6 pins with SWNS -1.795ns STNS -3.586ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.149389s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (104.6%)
+
+PHY-1022 : len = 2.50714e+06, over cnt = 2092(0%), over = 2096, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.414278s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.47083e+06, over cnt = 911(0%), over = 914, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.123764s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (159.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.46177e+06, over cnt = 254(0%), over = 254, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.329557s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (128.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.4619e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.784343s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (139.4%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.46214e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.308159s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (101.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.46214e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.214698s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.9%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.4622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.299377s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.2%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.4622e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.327301s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (95.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.46222e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.172059s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.46222e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.165605s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16533(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.795   |  -3.586   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.235541s wall, 3.187500s user + 0.031250s system = 3.218750s CPU (99.5%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 683 feed throughs used by 469 nets
+PHY-1001 : End commit to database; 2.266724s wall, 2.218750s user + 0.046875s system = 2.265625s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1163, peak = 1156.
+PHY-1001 : End phase 3; 12.045901s wall, 13.890625s user + 0.078125s system = 13.968750s CPU (116.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -1.795ns STNS -3.586ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.163743s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.4%)
+
+PHY-1022 : len = 2.46222e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.403369s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.795ns, -3.586ns, 4}
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16533(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.795   |  -3.586   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.302685s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 683 feed throughs used by 469 nets
+PHY-1001 : End commit to database; 2.385304s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1173, peak = 1166.
+PHY-1001 : End phase 4; 6.118543s wall, 6.125000s user + 0.000000s system = 6.125000s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.46222e+06
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1178, peak = 1170.
+PHY-1001 : End export database. 0.061810s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.1%)
+
+PHY-1001 : End detail routing;  72.070608s wall, 102.625000s user + 0.359375s system = 102.984375s CPU (142.9%)
+
+RUN-1003 : finish command "route" in  78.016227s wall, 109.640625s user + 0.406250s system = 110.046875s CPU (141.1%)
+
+RUN-1004 : used memory is 1033 MB, reserved memory is 1029 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10197   out of  19600   52.03%
+#reg                     9499   out of  19600   48.46%
+#le                     12302
+  #lut only              2803   out of  12302   22.78%
+  #reg only              2105   out of  12302   17.11%
+  #lut&reg               7394   out of  12302   60.10%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1788
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1420
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1309
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               994
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    142
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_pic_cnt/reg1_syn_371.f0                          3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             ua_lvds_rx/reg8_syn_197.f0                         3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P163       LVCMOS33           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12302  |9170    |1027    |9529    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |529    |408     |23      |444     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |89      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |27     |27      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |8       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |768    |430     |96      |578     |0       |0       |
+|    u_ADconfig                |AD_config            |188    |125     |25      |142     |0       |0       |
+|    u_gen_sp                  |gen_sp               |269    |155     |71      |125     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |754    |450     |96      |560     |0       |0       |
+|    u_ADconfig                |AD_config            |176    |118     |25      |130     |0       |0       |
+|    u_gen_sp                  |gen_sp               |276    |179     |71      |129     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2980   |2354    |306     |2135    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |3      |0       |0       |3       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |172    |120     |17      |135     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2780   |2220    |289     |1972    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |7      |2       |0       |7       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |8      |6       |0       |8       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2268   |1823    |253     |1555    |22      |0       |
+|        channelPart           |channel_part_8478    |142    |136     |3       |131     |0       |0       |
+|        fifo_adc              |fifo_adc             |52     |43      |9       |36      |0       |0       |
+|        ram_switch            |ram_switch           |1790   |1428    |197     |1187    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |229    |202     |27      |124     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |15      |0       |0       |
+|          insert              |insert               |1001   |667     |170     |705     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |560    |559     |0       |358     |0       |0       |
+|        read_ram_i            |read_ram             |264    |206     |44      |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |211    |171     |40      |142     |0       |0       |
+|          read_ram_data       |read_ram_data        |49     |31      |4       |35      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |319    |225     |36      |278     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3143   |2360    |349     |2190    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |188    |127     |17      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2927   |2207    |332     |2015    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |3      |3       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2424   |1820    |290     |1587    |22      |1       |
+|        channelPart           |channel_part_8478    |236    |232     |3       |148     |0       |0       |
+|        fifo_adc              |fifo_adc             |64     |55      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |1729   |1244    |197     |1154    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |216    |189     |27      |120     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |17      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |17      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|          insert              |insert               |1011   |560     |170     |714     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |502    |495     |0       |320     |0       |0       |
+|        read_ram_i            |read_ram_rev         |366    |264     |81      |211     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |296    |211     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |70     |53      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9861  
+    #2         2       3890  
+    #3         3       1457  
+    #4         4       645   
+    #5        5-10     1045  
+    #6       11-50     588   
+    #7       51-100     28   
+    #8        >500      1    
+  Average     2.90           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.064996s wall, 3.531250s user + 0.031250s system = 3.562500s CPU (172.5%)
+
+RUN-1004 : used memory is 1035 MB, reserved memory is 1031 MB, peak memory is 1171 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73874, tnet num: 17432, tinst num: 6748, tnode num: 96508, tedge num: 124025.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.569775s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.5%)
+
+RUN-1004 : used memory is 1040 MB, reserved memory is 1036 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.509775s wall, 1.453125s user + 0.046875s system = 1.500000s CPU (99.4%)
+
+RUN-1004 : used memory is 1086 MB, reserved memory is 1087 MB, peak memory is 1171 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6748
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17610, pip num: 176978
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 683
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3244 valid insts, and 488283 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.232320s wall, 69.703125s user + 0.187500s system = 69.890625s CPU (683.0%)
+
+RUN-1004 : used memory is 1277 MB, reserved memory is 1273 MB, peak memory is 1392 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_161244.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_162940.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_162940.log
new file mode 100644
index 0000000..9e2cdb8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_162940.log
@@ -0,0 +1,1925 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:29:40 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.104094s wall, 2.000000s user + 0.093750s system = 2.093750s CPU (99.5%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 316 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2278 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17757 instances
+RUN-0007 : 7364 luts, 9170 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20341 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13318 nets have 2 pins
+RUN-1001 : 5733 nets have [3 - 5] pins
+RUN-1001 : 877 nets have [6 - 10] pins
+RUN-1001 : 157 nets have [11 - 20] pins
+RUN-1001 : 183 nets have [21 - 99] pins
+RUN-1001 : 53 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     796     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3597     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17755 instances, 7364 luts, 9170 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1151 with 5893 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84852, tnet num: 20163, tinst num: 17755, tnode num: 115322, tedge num: 136128.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.134561s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.2%)
+
+RUN-1004 : used memory is 538 MB, reserved memory is 515 MB, peak memory is 538 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20163 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.902784s wall, 1.890625s user + 0.015625s system = 1.906250s CPU (100.2%)
+
+PHY-3001 : Found 3487 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.02446e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17755.
+PHY-3001 : Level 1 #clusters 2068.
+PHY-3001 : End clustering;  0.125501s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (137.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.26357e+06, overlap = 480.781
+PHY-3002 : Step(2): len = 1.17131e+06, overlap = 541.906
+PHY-3002 : Step(3): len = 819408, overlap = 622.062
+PHY-3002 : Step(4): len = 756945, overlap = 642.594
+PHY-3002 : Step(5): len = 585929, overlap = 800.031
+PHY-3002 : Step(6): len = 516255, overlap = 866.219
+PHY-3002 : Step(7): len = 453108, overlap = 925.781
+PHY-3002 : Step(8): len = 422365, overlap = 954.406
+PHY-3002 : Step(9): len = 378217, overlap = 1007
+PHY-3002 : Step(10): len = 355584, overlap = 1031.62
+PHY-3002 : Step(11): len = 312056, overlap = 1053.03
+PHY-3002 : Step(12): len = 289060, overlap = 1120.09
+PHY-3002 : Step(13): len = 258835, overlap = 1203.44
+PHY-3002 : Step(14): len = 250428, overlap = 1236.88
+PHY-3002 : Step(15): len = 223634, overlap = 1291.84
+PHY-3002 : Step(16): len = 215351, overlap = 1317.88
+PHY-3002 : Step(17): len = 194797, overlap = 1355.09
+PHY-3002 : Step(18): len = 181472, overlap = 1369.12
+PHY-3002 : Step(19): len = 171439, overlap = 1385.34
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.16614e-06
+PHY-3002 : Step(20): len = 172740, overlap = 1355.53
+PHY-3002 : Step(21): len = 203386, overlap = 1244.94
+PHY-3002 : Step(22): len = 201243, overlap = 1174.28
+PHY-3002 : Step(23): len = 203591, overlap = 1186.38
+PHY-3002 : Step(24): len = 200021, overlap = 1183.59
+PHY-3002 : Step(25): len = 198488, overlap = 1165.41
+PHY-3002 : Step(26): len = 196485, overlap = 1163.84
+PHY-3002 : Step(27): len = 195239, overlap = 1160.06
+PHY-3002 : Step(28): len = 191353, overlap = 1134.66
+PHY-3002 : Step(29): len = 187587, overlap = 1120.28
+PHY-3002 : Step(30): len = 184274, overlap = 1123.28
+PHY-3002 : Step(31): len = 182304, overlap = 1131.75
+PHY-3002 : Step(32): len = 181505, overlap = 1135.44
+PHY-3002 : Step(33): len = 179654, overlap = 1143.5
+PHY-3002 : Step(34): len = 179216, overlap = 1148.44
+PHY-3002 : Step(35): len = 178368, overlap = 1155.88
+PHY-3002 : Step(36): len = 177736, overlap = 1161.5
+PHY-3002 : Step(37): len = 177478, overlap = 1152.47
+PHY-3002 : Step(38): len = 177501, overlap = 1148.31
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.33227e-06
+PHY-3002 : Step(39): len = 180313, overlap = 1110.75
+PHY-3002 : Step(40): len = 191245, overlap = 1090.78
+PHY-3002 : Step(41): len = 195811, overlap = 1066.22
+PHY-3002 : Step(42): len = 202827, overlap = 1036.78
+PHY-3002 : Step(43): len = 205103, overlap = 1042.47
+PHY-3002 : Step(44): len = 206011, overlap = 1033.28
+PHY-3002 : Step(45): len = 204852, overlap = 1045.84
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.66454e-06
+PHY-3002 : Step(46): len = 211016, overlap = 1011.09
+PHY-3002 : Step(47): len = 223143, overlap = 958.219
+PHY-3002 : Step(48): len = 229959, overlap = 908.281
+PHY-3002 : Step(49): len = 237623, overlap = 888.812
+PHY-3002 : Step(50): len = 243290, overlap = 822.094
+PHY-3002 : Step(51): len = 248606, overlap = 791.625
+PHY-3002 : Step(52): len = 250321, overlap = 784.062
+PHY-3002 : Step(53): len = 251793, overlap = 781.438
+PHY-3002 : Step(54): len = 251375, overlap = 785.812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.32908e-06
+PHY-3002 : Step(55): len = 271020, overlap = 760.906
+PHY-3002 : Step(56): len = 295917, overlap = 653.062
+PHY-3002 : Step(57): len = 304094, overlap = 581.5
+PHY-3002 : Step(58): len = 307616, overlap = 548.906
+PHY-3002 : Step(59): len = 306608, overlap = 555.25
+PHY-3002 : Step(60): len = 307531, overlap = 556.781
+PHY-3002 : Step(61): len = 305717, overlap = 571.5
+PHY-3002 : Step(62): len = 305894, overlap = 584.5
+PHY-3002 : Step(63): len = 304867, overlap = 567.75
+PHY-3002 : Step(64): len = 303743, overlap = 563.969
+PHY-3002 : Step(65): len = 300959, overlap = 576.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.86582e-05
+PHY-3002 : Step(66): len = 321002, overlap = 507.656
+PHY-3002 : Step(67): len = 337224, overlap = 432.875
+PHY-3002 : Step(68): len = 340981, overlap = 415.656
+PHY-3002 : Step(69): len = 343790, overlap = 369.031
+PHY-3002 : Step(70): len = 342348, overlap = 354.031
+PHY-3002 : Step(71): len = 342051, overlap = 340.094
+PHY-3002 : Step(72): len = 341456, overlap = 344.812
+PHY-3002 : Step(73): len = 341450, overlap = 345.438
+PHY-3002 : Step(74): len = 341153, overlap = 366.094
+PHY-3002 : Step(75): len = 341586, overlap = 381.625
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.73163e-05
+PHY-3002 : Step(76): len = 361819, overlap = 306.594
+PHY-3002 : Step(77): len = 376987, overlap = 310.625
+PHY-3002 : Step(78): len = 377254, overlap = 285.656
+PHY-3002 : Step(79): len = 378928, overlap = 268.094
+PHY-3002 : Step(80): len = 380971, overlap = 248.969
+PHY-3002 : Step(81): len = 383613, overlap = 258.531
+PHY-3002 : Step(82): len = 380036, overlap = 262.969
+PHY-3002 : Step(83): len = 380535, overlap = 273.812
+PHY-3002 : Step(84): len = 382340, overlap = 271.125
+PHY-3002 : Step(85): len = 383188, overlap = 266.844
+PHY-3002 : Step(86): len = 380128, overlap = 259.406
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.42251e-05
+PHY-3002 : Step(87): len = 396910, overlap = 252.062
+PHY-3002 : Step(88): len = 411096, overlap = 245.5
+PHY-3002 : Step(89): len = 411043, overlap = 246.75
+PHY-3002 : Step(90): len = 412452, overlap = 242.094
+PHY-3002 : Step(91): len = 414385, overlap = 222.656
+PHY-3002 : Step(92): len = 418021, overlap = 221.562
+PHY-3002 : Step(93): len = 415535, overlap = 206.969
+PHY-3002 : Step(94): len = 418187, overlap = 194.938
+PHY-3002 : Step(95): len = 420091, overlap = 202.969
+PHY-3002 : Step(96): len = 421845, overlap = 198.75
+PHY-3002 : Step(97): len = 417914, overlap = 214.312
+PHY-3002 : Step(98): len = 417852, overlap = 203.469
+PHY-3002 : Step(99): len = 418726, overlap = 195.5
+PHY-3002 : Step(100): len = 419730, overlap = 205.625
+PHY-3002 : Step(101): len = 417451, overlap = 206.031
+PHY-3002 : Step(102): len = 416619, overlap = 216.875
+PHY-3002 : Step(103): len = 417678, overlap = 225.375
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00014845
+PHY-3002 : Step(104): len = 432250, overlap = 230.031
+PHY-3002 : Step(105): len = 442612, overlap = 236.531
+PHY-3002 : Step(106): len = 443342, overlap = 225.5
+PHY-3002 : Step(107): len = 445213, overlap = 207.562
+PHY-3002 : Step(108): len = 447069, overlap = 210.281
+PHY-3002 : Step(109): len = 449025, overlap = 211.781
+PHY-3002 : Step(110): len = 448231, overlap = 217.938
+PHY-3002 : Step(111): len = 449999, overlap = 207.031
+PHY-3002 : Step(112): len = 452873, overlap = 201.312
+PHY-3002 : Step(113): len = 455095, overlap = 199.25
+PHY-3002 : Step(114): len = 453249, overlap = 191.219
+PHY-3002 : Step(115): len = 453042, overlap = 193.188
+PHY-3002 : Step(116): len = 453560, overlap = 202.906
+PHY-3002 : Step(117): len = 454125, overlap = 201.812
+PHY-3002 : Step(118): len = 452729, overlap = 203.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000284548
+PHY-3002 : Step(119): len = 461641, overlap = 204.312
+PHY-3002 : Step(120): len = 469789, overlap = 215.812
+PHY-3002 : Step(121): len = 470010, overlap = 203.031
+PHY-3002 : Step(122): len = 471093, overlap = 198.719
+PHY-3002 : Step(123): len = 474588, overlap = 194.781
+PHY-3002 : Step(124): len = 477560, overlap = 187.094
+PHY-3002 : Step(125): len = 475959, overlap = 186.156
+PHY-3002 : Step(126): len = 476638, overlap = 194.938
+PHY-3002 : Step(127): len = 480144, overlap = 194.719
+PHY-3002 : Step(128): len = 483251, overlap = 192.219
+PHY-3002 : Step(129): len = 481565, overlap = 191.469
+PHY-3002 : Step(130): len = 481622, overlap = 194.344
+PHY-3002 : Step(131): len = 483730, overlap = 190.094
+PHY-3002 : Step(132): len = 485024, overlap = 198.562
+PHY-3002 : Step(133): len = 483785, overlap = 200.938
+PHY-3002 : Step(134): len = 484091, overlap = 198.062
+PHY-3002 : Step(135): len = 485451, overlap = 193.656
+PHY-3002 : Step(136): len = 485968, overlap = 190.562
+PHY-3002 : Step(137): len = 484541, overlap = 190.938
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000512244
+PHY-3002 : Step(138): len = 489794, overlap = 180.375
+PHY-3002 : Step(139): len = 495327, overlap = 176.938
+PHY-3002 : Step(140): len = 496611, overlap = 170.062
+PHY-3002 : Step(141): len = 497566, overlap = 172.344
+PHY-3002 : Step(142): len = 499061, overlap = 167
+PHY-3002 : Step(143): len = 500328, overlap = 165.375
+PHY-3002 : Step(144): len = 500436, overlap = 167.406
+PHY-3002 : Step(145): len = 501273, overlap = 160.656
+PHY-3002 : Step(146): len = 502434, overlap = 163.438
+PHY-3002 : Step(147): len = 503393, overlap = 163.875
+PHY-3002 : Step(148): len = 503824, overlap = 157.094
+PHY-3002 : Step(149): len = 504670, overlap = 154.469
+PHY-3002 : Step(150): len = 505283, overlap = 154.781
+PHY-3002 : Step(151): len = 505611, overlap = 164.5
+PHY-3002 : Step(152): len = 505151, overlap = 164.438
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000944232
+PHY-3002 : Step(153): len = 509274, overlap = 161.531
+PHY-3002 : Step(154): len = 516480, overlap = 156.562
+PHY-3002 : Step(155): len = 518311, overlap = 154.062
+PHY-3002 : Step(156): len = 520057, overlap = 155.281
+PHY-3002 : Step(157): len = 521770, overlap = 152.562
+PHY-3002 : Step(158): len = 522493, overlap = 148.562
+PHY-3002 : Step(159): len = 521786, overlap = 146.594
+PHY-3002 : Step(160): len = 522090, overlap = 150.375
+PHY-3002 : Step(161): len = 523423, overlap = 152.094
+PHY-3002 : Step(162): len = 524192, overlap = 154.438
+PHY-3002 : Step(163): len = 523838, overlap = 151.062
+PHY-3002 : Step(164): len = 524026, overlap = 144.094
+PHY-3002 : Step(165): len = 525233, overlap = 144.344
+PHY-3002 : Step(166): len = 525697, overlap = 144.688
+PHY-3002 : Step(167): len = 525201, overlap = 145.25
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00165344
+PHY-3002 : Step(168): len = 528687, overlap = 144.594
+PHY-3002 : Step(169): len = 533511, overlap = 143.156
+PHY-3002 : Step(170): len = 534044, overlap = 140.375
+PHY-3002 : Step(171): len = 534453, overlap = 139.875
+PHY-3002 : Step(172): len = 535802, overlap = 142.844
+PHY-3002 : Step(173): len = 536467, overlap = 142.781
+PHY-3002 : Step(174): len = 536320, overlap = 142.625
+PHY-3002 : Step(175): len = 536402, overlap = 139.75
+PHY-3002 : Step(176): len = 537718, overlap = 138.688
+PHY-3002 : Step(177): len = 539038, overlap = 139.375
+PHY-3002 : Step(178): len = 539118, overlap = 136.531
+PHY-3002 : Step(179): len = 539348, overlap = 137.562
+PHY-3002 : Step(180): len = 540100, overlap = 136.812
+PHY-3002 : Step(181): len = 540424, overlap = 136.375
+PHY-3002 : Step(182): len = 540406, overlap = 135.844
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015445s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (101.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20341.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710168, over cnt = 1600(4%), over = 7893, worst = 34
+PHY-1001 : End global iterations;  0.694816s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (116.9%)
+
+PHY-1001 : Congestion index: top1 = 89.96, top5 = 63.63, top10 = 53.32, top15 = 47.38.
+PHY-3001 : End congestion estimation;  0.914488s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (112.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20163 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.835745s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.21737e-05
+PHY-3002 : Step(183): len = 649389, overlap = 83.7812
+PHY-3002 : Step(184): len = 656100, overlap = 79.9062
+PHY-3002 : Step(185): len = 652214, overlap = 76.75
+PHY-3002 : Step(186): len = 649436, overlap = 76.8438
+PHY-3002 : Step(187): len = 651288, overlap = 75.9062
+PHY-3002 : Step(188): len = 660475, overlap = 77
+PHY-3002 : Step(189): len = 663106, overlap = 67.5
+PHY-3002 : Step(190): len = 668948, overlap = 67.2812
+PHY-3002 : Step(191): len = 674211, overlap = 62.3125
+PHY-3002 : Step(192): len = 677592, overlap = 58.8438
+PHY-3002 : Step(193): len = 681602, overlap = 67.25
+PHY-3002 : Step(194): len = 684979, overlap = 70.4688
+PHY-3002 : Step(195): len = 690170, overlap = 70.3125
+PHY-3002 : Step(196): len = 694859, overlap = 66.375
+PHY-3002 : Step(197): len = 697860, overlap = 58.8438
+PHY-3002 : Step(198): len = 700328, overlap = 58.9062
+PHY-3002 : Step(199): len = 705374, overlap = 48.7188
+PHY-3002 : Step(200): len = 705804, overlap = 46.0625
+PHY-3002 : Step(201): len = 707119, overlap = 46.25
+PHY-3002 : Step(202): len = 707859, overlap = 40.9688
+PHY-3002 : Step(203): len = 707485, overlap = 37.7812
+PHY-3002 : Step(204): len = 706884, overlap = 38.5
+PHY-3002 : Step(205): len = 706322, overlap = 36.3125
+PHY-3002 : Step(206): len = 705814, overlap = 34.8125
+PHY-3002 : Step(207): len = 704294, overlap = 35.2812
+PHY-3002 : Step(208): len = 703582, overlap = 33.625
+PHY-3002 : Step(209): len = 701859, overlap = 35.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000184347
+PHY-3002 : Step(210): len = 704713, overlap = 34.625
+PHY-3002 : Step(211): len = 706054, overlap = 33.6562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 65/20341.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 785280, over cnt = 2827(8%), over = 14041, worst = 39
+PHY-1001 : End global iterations;  1.376453s wall, 1.812500s user + 0.015625s system = 1.828125s CPU (132.8%)
+
+PHY-1001 : Congestion index: top1 = 105.41, top5 = 78.67, top10 = 66.93, top15 = 59.99.
+PHY-3001 : End congestion estimation;  1.666250s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (126.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20163 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.207778s wall, 1.187500s user + 0.031250s system = 1.218750s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.30908e-05
+PHY-3002 : Step(212): len = 706888, overlap = 289.594
+PHY-3002 : Step(213): len = 713327, overlap = 249.125
+PHY-3002 : Step(214): len = 709552, overlap = 234.188
+PHY-3002 : Step(215): len = 708308, overlap = 217.219
+PHY-3002 : Step(216): len = 710116, overlap = 201.375
+PHY-3002 : Step(217): len = 706617, overlap = 197.188
+PHY-3002 : Step(218): len = 706141, overlap = 189.312
+PHY-3002 : Step(219): len = 704114, overlap = 182.719
+PHY-3002 : Step(220): len = 703553, overlap = 176.406
+PHY-3002 : Step(221): len = 701843, overlap = 162.719
+PHY-3002 : Step(222): len = 699758, overlap = 160.438
+PHY-3002 : Step(223): len = 697844, overlap = 163.375
+PHY-3002 : Step(224): len = 695655, overlap = 165.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000166182
+PHY-3002 : Step(225): len = 696446, overlap = 162.844
+PHY-3002 : Step(226): len = 697835, overlap = 161.594
+PHY-3002 : Step(227): len = 703764, overlap = 150.781
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000332363
+PHY-3002 : Step(228): len = 707684, overlap = 140.531
+PHY-3002 : Step(229): len = 716572, overlap = 127.469
+PHY-3002 : Step(230): len = 724044, overlap = 123.875
+PHY-3002 : Step(231): len = 722311, overlap = 123.844
+PHY-3002 : Step(232): len = 720680, overlap = 118.031
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000650423
+PHY-3002 : Step(233): len = 726708, overlap = 109.844
+PHY-3002 : Step(234): len = 733980, overlap = 104.656
+PHY-3002 : Step(235): len = 741460, overlap = 100.688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00126807
+PHY-3002 : Step(236): len = 742163, overlap = 100.875
+PHY-3002 : Step(237): len = 743688, overlap = 99.2188
+PHY-3002 : Step(238): len = 747218, overlap = 97.9688
+PHY-3002 : Step(239): len = 753612, overlap = 93.5312
+PHY-3002 : Step(240): len = 759109, overlap = 92.5312
+PHY-3002 : Step(241): len = 761207, overlap = 91.0312
+PHY-3002 : Step(242): len = 763847, overlap = 89.4375
+PHY-3002 : Step(243): len = 766106, overlap = 91.7812
+PHY-3002 : Step(244): len = 767251, overlap = 88.7812
+PHY-3002 : Step(245): len = 768562, overlap = 89
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84852, tnet num: 20163, tinst num: 17755, tnode num: 115322, tedge num: 136128.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.395243s wall, 1.343750s user + 0.046875s system = 1.390625s CPU (99.7%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 566 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 451.19 peak overflow 4.38
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 895/20341.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862440, over cnt = 3278(9%), over = 12930, worst = 32
+PHY-1001 : End global iterations;  1.142901s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 85.86, top5 = 68.58, top10 = 60.59, top15 = 55.67.
+PHY-1001 : End incremental global routing;  1.440877s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (136.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20163 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.890984s wall, 0.828125s user + 0.062500s system = 0.890625s CPU (100.0%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17620 has valid locations, 321 needs to be replaced
+PHY-3001 : design contains 18026 instances, 7454 luts, 9351 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1151 with 6015 pins
+PHY-3001 : Found 3523 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 790293
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16969/20612.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 877840, over cnt = 3308(9%), over = 12961, worst = 32
+PHY-1001 : End global iterations;  0.235392s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (112.8%)
+
+PHY-1001 : Congestion index: top1 = 85.67, top5 = 68.71, top10 = 60.67, top15 = 55.86.
+PHY-3001 : End congestion estimation;  0.492471s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (104.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85962, tnet num: 20434, tinst num: 18026, tnode num: 117003, tedge num: 137806.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.428423s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.6%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 613 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20434 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.377339s wall, 2.343750s user + 0.031250s system = 2.375000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(246): len = 789167, overlap = 0
+PHY-3002 : Step(247): len = 788541, overlap = 0
+PHY-3002 : Step(248): len = 788276, overlap = 0
+PHY-3002 : Step(249): len = 788046, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17050/20612.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874720, over cnt = 3302(9%), over = 13059, worst = 32
+PHY-1001 : End global iterations;  0.194599s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (152.6%)
+
+PHY-1001 : Congestion index: top1 = 86.55, top5 = 69.33, top10 = 61.04, top15 = 56.16.
+PHY-3001 : End congestion estimation;  0.515248s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (118.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20434 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.990506s wall, 0.937500s user + 0.046875s system = 0.984375s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000495207
+PHY-3002 : Step(250): len = 787928, overlap = 91.8125
+PHY-3002 : Step(251): len = 788064, overlap = 91.7188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000990414
+PHY-3002 : Step(252): len = 788147, overlap = 91.2812
+PHY-3002 : Step(253): len = 788722, overlap = 91.1875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00188772
+PHY-3002 : Step(254): len = 789020, overlap = 91.4062
+PHY-3002 : Step(255): len = 789607, overlap = 90.9375
+PHY-3001 : Final: Len = 789607, Over = 90.9375
+PHY-3001 : End incremental placement;  5.149953s wall, 5.375000s user + 0.296875s system = 5.671875s CPU (110.1%)
+
+OPT-1001 : Total overflow 456.66 peak overflow 4.38
+OPT-1001 : End high-fanout net optimization;  8.021812s wall, 8.781250s user + 0.375000s system = 9.156250s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 713, peak = 742.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17005/20612.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 879176, over cnt = 3295(9%), over = 12102, worst = 32
+PHY-1002 : len = 940104, over cnt = 2422(6%), over = 6536, worst = 30
+PHY-1002 : len = 978880, over cnt = 1429(4%), over = 3491, worst = 23
+PHY-1002 : len = 1.0121e+06, over cnt = 603(1%), over = 1575, worst = 23
+PHY-1002 : len = 1.03598e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.262456s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (129.8%)
+
+PHY-1001 : Congestion index: top1 = 66.29, top5 = 58.38, top10 = 54.26, top15 = 51.63.
+OPT-1001 : End congestion update;  2.525285s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (126.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20434 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.780365s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (100.1%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 74 cells processed and 5915 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 18 cells processed and 2676 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 3 cells processed and 400 slack improved
+OPT-1001 : End global optimization;  3.348496s wall, 4.000000s user + 0.015625s system = 4.015625s CPU (119.9%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 694, peak = 742.
+OPT-1001 : End physical optimization;  13.386857s wall, 14.812500s user + 0.453125s system = 15.265625s CPU (114.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7454 LUT to BLE ...
+SYN-4008 : Packed 7454 LUT and 3132 SEQ to BLE.
+SYN-4003 : Packing 6219 remaining SEQ's ...
+SYN-4005 : Packed 3861 SEQ with LUT/SLICE
+SYN-4006 : 772 single LUT's are left
+SYN-4006 : 2358 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9812/13543 primitive instances ...
+PHY-3001 : End packing;  1.660946s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6847 instances
+RUN-1001 : 3350 mslices, 3349 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17610 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9942 nets have 2 pins
+RUN-1001 : 6004 nets have [3 - 5] pins
+RUN-1001 : 998 nets have [6 - 10] pins
+RUN-1001 : 294 nets have [11 - 20] pins
+RUN-1001 : 339 nets have [21 - 99] pins
+RUN-1001 : 13 nets have 100+ pins
+PHY-3001 : design contains 6845 instances, 6699 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1151 with 3504 pins
+PHY-3001 : Found 1575 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 787321, Over = 269
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7592/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 953504, over cnt = 2048(5%), over = 3440, worst = 9
+PHY-1002 : len = 962952, over cnt = 1259(3%), over = 1862, worst = 9
+PHY-1002 : len = 974904, over cnt = 565(1%), over = 800, worst = 7
+PHY-1002 : len = 979528, over cnt = 377(1%), over = 533, worst = 6
+PHY-1002 : len = 987520, over cnt = 53(0%), over = 75, worst = 5
+PHY-1001 : End global iterations;  1.758821s wall, 2.390625s user + 0.046875s system = 2.437500s CPU (138.6%)
+
+PHY-1001 : Congestion index: top1 = 61.44, top5 = 54.87, top10 = 50.82, top15 = 48.30.
+PHY-3001 : End congestion estimation;  2.123032s wall, 2.750000s user + 0.046875s system = 2.796875s CPU (131.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73746, tnet num: 17432, tinst num: 6845, tnode num: 96284, tedge num: 123829.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.605803s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (100.2%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 613 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.449825s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.31656e-05
+PHY-3002 : Step(256): len = 770815, overlap = 266
+PHY-3002 : Step(257): len = 761822, overlap = 269
+PHY-3002 : Step(258): len = 754270, overlap = 260.5
+PHY-3002 : Step(259): len = 747957, overlap = 263.25
+PHY-3002 : Step(260): len = 743115, overlap = 267
+PHY-3002 : Step(261): len = 738068, overlap = 272.25
+PHY-3002 : Step(262): len = 733885, overlap = 284.25
+PHY-3002 : Step(263): len = 730352, overlap = 284.5
+PHY-3002 : Step(264): len = 726980, overlap = 289
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000106331
+PHY-3002 : Step(265): len = 729765, overlap = 281.75
+PHY-3002 : Step(266): len = 733813, overlap = 271.5
+PHY-3002 : Step(267): len = 734968, overlap = 269
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000212662
+PHY-3002 : Step(268): len = 741413, overlap = 253.75
+PHY-3002 : Step(269): len = 751012, overlap = 238
+PHY-3002 : Step(270): len = 751863, overlap = 246
+PHY-3002 : Step(271): len = 752653, overlap = 242.25
+PHY-3002 : Step(272): len = 754826, overlap = 240.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.333980s wall, 0.281250s user + 0.687500s system = 0.968750s CPU (290.1%)
+
+PHY-3001 : Trial Legalized: Len = 972310
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 547/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09628e+06, over cnt = 2956(8%), over = 5231, worst = 7
+PHY-1002 : len = 1.11963e+06, over cnt = 1837(5%), over = 2669, worst = 6
+PHY-1002 : len = 1.14422e+06, over cnt = 656(1%), over = 899, worst = 6
+PHY-1002 : len = 1.15532e+06, over cnt = 181(0%), over = 240, worst = 5
+PHY-1002 : len = 1.16006e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.769950s wall, 3.968750s user + 0.062500s system = 4.031250s CPU (145.5%)
+
+PHY-1001 : Congestion index: top1 = 71.72, top5 = 63.71, top10 = 58.99, top15 = 55.91.
+PHY-3001 : End congestion estimation;  3.191701s wall, 4.406250s user + 0.062500s system = 4.468750s CPU (140.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.887153s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000176373
+PHY-3002 : Step(273): len = 922648, overlap = 84
+PHY-3002 : Step(274): len = 898175, overlap = 116.75
+PHY-3002 : Step(275): len = 881776, overlap = 140.5
+PHY-3002 : Step(276): len = 868415, overlap = 161.75
+PHY-3002 : Step(277): len = 858026, overlap = 176.75
+PHY-3002 : Step(278): len = 849906, overlap = 188
+PHY-3002 : Step(279): len = 843849, overlap = 202.75
+PHY-3002 : Step(280): len = 838559, overlap = 206.75
+PHY-3002 : Step(281): len = 833230, overlap = 210.5
+PHY-3002 : Step(282): len = 828397, overlap = 215.25
+PHY-3002 : Step(283): len = 824305, overlap = 222.25
+PHY-3002 : Step(284): len = 820284, overlap = 230
+PHY-3002 : Step(285): len = 817406, overlap = 224.75
+PHY-3002 : Step(286): len = 814418, overlap = 221
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000341774
+PHY-3002 : Step(287): len = 819438, overlap = 213
+PHY-3002 : Step(288): len = 821616, overlap = 211.5
+PHY-3002 : Step(289): len = 823737, overlap = 210.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000555361
+PHY-3002 : Step(290): len = 828173, overlap = 204.5
+PHY-3002 : Step(291): len = 831477, overlap = 196.25
+PHY-3002 : Step(292): len = 834442, overlap = 194
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.088059s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (106.5%)
+
+PHY-3001 : Legalized: Len = 924668, Over = 0
+PHY-3001 : Spreading special nets. 531 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.135816s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.0%)
+
+PHY-3001 : 818 instances has been re-located, deltaX = 418, deltaY = 566, maxDist = 12.
+PHY-3001 : Final: Len = 940567, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73746, tnet num: 17432, tinst num: 6848, tnode num: 96284, tedge num: 123829.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.810129s wall, 1.796875s user + 0.015625s system = 1.812500s CPU (100.1%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 610 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 2523/17610.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07126e+06, over cnt = 2804(7%), over = 4800, worst = 8
+PHY-1002 : len = 1.08858e+06, over cnt = 1765(5%), over = 2622, worst = 6
+PHY-1002 : len = 1.10638e+06, over cnt = 910(2%), over = 1282, worst = 6
+PHY-1002 : len = 1.1183e+06, over cnt = 351(0%), over = 499, worst = 6
+PHY-1002 : len = 1.1271e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.238155s wall, 3.203125s user + 0.015625s system = 3.218750s CPU (143.8%)
+
+PHY-1001 : Congestion index: top1 = 67.56, top5 = 60.57, top10 = 56.63, top15 = 53.79.
+PHY-1001 : End incremental global routing;  2.587196s wall, 3.562500s user + 0.015625s system = 3.578125s CPU (138.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17432 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.889104s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (98.4%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6754 has valid locations, 30 needs to be replaced
+PHY-3001 : design contains 6872 instances, 6723 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1151 with 3577 pins
+PHY-3001 : Found 1578 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 943241
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16152/17654.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12976e+06, over cnt = 77(0%), over = 88, worst = 3
+PHY-1002 : len = 1.12968e+06, over cnt = 39(0%), over = 39, worst = 1
+PHY-1002 : len = 1.13004e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.1301e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.621515s wall, 0.703125s user + 0.031250s system = 0.734375s CPU (118.2%)
+
+PHY-1001 : Congestion index: top1 = 67.56, top5 = 60.57, top10 = 56.65, top15 = 53.82.
+PHY-3001 : End congestion estimation;  0.935820s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (111.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73966, tnet num: 17476, tinst num: 6872, tnode num: 96576, tedge num: 124157.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.887754s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.3%)
+
+RUN-1004 : used memory is 675 MB, reserved memory is 676 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17476 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.765576s wall, 2.718750s user + 0.046875s system = 2.765625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(293): len = 942754, overlap = 0
+PHY-3002 : Step(294): len = 942546, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16147/17654.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12929e+06, over cnt = 52(0%), over = 59, worst = 3
+PHY-1002 : len = 1.12934e+06, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 1.12953e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.12961e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.581045s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (102.2%)
+
+PHY-1001 : Congestion index: top1 = 67.56, top5 = 60.58, top10 = 56.64, top15 = 53.79.
+PHY-3001 : End congestion estimation;  0.905284s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (101.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17476 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.846436s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000589822
+PHY-3002 : Step(295): len = 942605, overlap = 0.75
+PHY-3002 : Step(296): len = 942562, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005396s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 942640, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.056731s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (110.2%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 942706, Over = 0
+PHY-3001 : End incremental placement;  5.942892s wall, 5.968750s user + 0.203125s system = 6.171875s CPU (103.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.922835s wall, 10.875000s user + 0.234375s system = 11.109375s CPU (112.0%)
+
+OPT-1001 : Current memory(MB): used = 752, reserve = 746, peak = 756.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16129/17654.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12954e+06, over cnt = 41(0%), over = 46, worst = 2
+PHY-1002 : len = 1.12945e+06, over cnt = 24(0%), over = 25, worst = 2
+PHY-1002 : len = 1.12962e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.12967e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.12977e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.763310s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (104.4%)
+
+PHY-1001 : Congestion index: top1 = 67.61, top5 = 60.58, top10 = 56.65, top15 = 53.81.
+OPT-1001 : End congestion update;  1.068450s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (103.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17476 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.709086s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.2%)
+
+OPT-0007 : Start: WNS -1083 TNS -2047 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6784 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6872 instances, 6723 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1151 with 3577 pins
+PHY-3001 : Found 1578 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 947824, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062325s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.3%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 14, deltaY = 23, maxDist = 2.
+PHY-3001 : Final: Len = 948680, Over = 0
+PHY-3001 : End incremental legalization;  0.413525s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (98.2%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1718 NUM_FEPS 2 with 43 cells processed and 11859 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6784 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6872 instances, 6723 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1151 with 3577 pins
+PHY-3001 : Found 1578 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 951882, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061349s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.9%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 7, deltaY = 21, maxDist = 4.
+PHY-3001 : Final: Len = 952362, Over = 0
+PHY-3001 : End incremental legalization;  0.367895s wall, 0.421875s user + 0.031250s system = 0.453125s CPU (123.2%)
+
+OPT-0007 : Iter 2: improved WNS -983 TNS -1718 NUM_FEPS 2 with 20 cells processed and 4236 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6784 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6872 instances, 6723 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1151 with 3577 pins
+PHY-3001 : Found 1578 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 953162, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058988s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.0%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 9, deltaY = 10, maxDist = 4.
+PHY-3001 : Final: Len = 953342, Over = 0
+PHY-3001 : End incremental legalization;  0.405531s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.3%)
+
+OPT-0007 : Iter 3: improved WNS -983 TNS -1718 NUM_FEPS 2 with 15 cells processed and 1512 slack improved
+OPT-1001 : End path based optimization;  3.372307s wall, 3.453125s user + 0.062500s system = 3.515625s CPU (104.2%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 745, peak = 756.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17476 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.713149s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15786/17654.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.1406e+06, over cnt = 241(0%), over = 306, worst = 7
+PHY-1002 : len = 1.14053e+06, over cnt = 156(0%), over = 179, worst = 4
+PHY-1002 : len = 1.14156e+06, over cnt = 46(0%), over = 50, worst = 3
+PHY-1002 : len = 1.14212e+06, over cnt = 16(0%), over = 18, worst = 2
+PHY-1002 : len = 1.14249e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.879447s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (120.8%)
+
+PHY-1001 : Congestion index: top1 = 67.31, top5 = 60.77, top10 = 56.93, top15 = 54.17.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17476 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.703515s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1083 TNS -1818 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 66.965517
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1083ps with logic level 2 
+RUN-1001 :       #2 path slack -997ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17654 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17654 nets
+OPT-1001 : End physical optimization;  18.092989s wall, 19.250000s user + 0.359375s system = 19.609375s CPU (108.4%)
+
+RUN-1003 : finish command "place" in  60.189897s wall, 88.328125s user + 6.468750s system = 94.796875s CPU (157.5%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 623 MB, peak memory is 756 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.705704s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (174.0%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 623 MB, peak memory is 756 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6874 instances
+RUN-1001 : 3366 mslices, 3357 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17654 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9957 nets have 2 pins
+RUN-1001 : 6013 nets have [3 - 5] pins
+RUN-1001 : 1001 nets have [6 - 10] pins
+RUN-1001 : 299 nets have [11 - 20] pins
+RUN-1001 : 356 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73966, tnet num: 17476, tinst num: 6872, tnode num: 96576, tedge num: 124157.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.572482s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.4%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 599 MB, peak memory is 756 MB
+PHY-1001 : 3366 mslices, 3357 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17476 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06804e+06, over cnt = 2983(8%), over = 5116, worst = 8
+PHY-1002 : len = 1.08747e+06, over cnt = 1921(5%), over = 2913, worst = 7
+PHY-1002 : len = 1.11034e+06, over cnt = 765(2%), over = 1178, worst = 7
+PHY-1002 : len = 1.12986e+06, over cnt = 52(0%), over = 63, worst = 4
+PHY-1002 : len = 1.13108e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.026037s wall, 3.968750s user + 0.000000s system = 3.968750s CPU (131.2%)
+
+PHY-1001 : Congestion index: top1 = 67.65, top5 = 61.02, top10 = 56.95, top15 = 54.08.
+PHY-1001 : End global routing;  3.347130s wall, 4.312500s user + 0.000000s system = 4.312500s CPU (128.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 719, reserve = 719, peak = 756.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 995, reserve = 994, peak = 995.
+PHY-1001 : End build detailed router design. 3.960052s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271472, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.002823s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271528, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.459235s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.7%)
+
+PHY-1001 : Current memory(MB): used = 1030, reserve = 1030, peak = 1030.
+PHY-1001 : End phase 1; 5.474951s wall, 5.468750s user + 0.000000s system = 5.468750s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.62429e+06, over cnt = 2262(0%), over = 2274, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1048, reserve = 1045, peak = 1048.
+PHY-1001 : End initial routed; 51.229346s wall, 81.000000s user + 0.531250s system = 81.531250s CPU (159.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16576(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.166   |  -4.294   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.271598s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1062, reserve = 1059, peak = 1062.
+PHY-1001 : End phase 2; 54.501012s wall, 84.265625s user + 0.531250s system = 84.796875s CPU (155.6%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.046ns STNS -4.169ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.139929s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (89.3%)
+
+PHY-1022 : len = 2.62432e+06, over cnt = 2266(0%), over = 2279, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.400705s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.58033e+06, over cnt = 919(0%), over = 920, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.171155s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (153.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.57478e+06, over cnt = 257(0%), over = 257, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.485611s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (124.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.57627e+06, over cnt = 69(0%), over = 69, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.586221s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (119.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.57645e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.358582s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.57657e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.351932s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.57668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.255378s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (104.0%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.57668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.243988s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (102.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.5767e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.167386s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.57668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.164605s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (94.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.57668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.173848s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (107.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.57668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.207613s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (112.9%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.57668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.249061s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.57668e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.163553s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.5%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.57668e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.157563s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (119.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16576(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.046   |  -4.169   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.221628s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 731 feed throughs used by 529 nets
+PHY-1001 : End commit to database; 2.292052s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1166, peak = 1165.
+PHY-1001 : End phase 3; 13.049273s wall, 14.750000s user + 0.000000s system = 14.750000s CPU (113.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.046ns STNS -4.169ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.136331s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.1%)
+
+PHY-1022 : len = 2.57668e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.376591s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.046ns, -4.169ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16576(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.046   |  -4.169   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.199089s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 731 feed throughs used by 529 nets
+PHY-1001 : End commit to database; 2.418506s wall, 2.421875s user + 0.000000s system = 2.421875s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1174, reserve = 1175, peak = 1174.
+PHY-1001 : End phase 4; 6.020155s wall, 6.000000s user + 0.015625s system = 6.015625s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.57668e+06
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1177, peak = 1175.
+PHY-1001 : End export database. 0.068751s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.9%)
+
+PHY-1001 : End detail routing;  83.486358s wall, 114.906250s user + 0.562500s system = 115.468750s CPU (138.3%)
+
+RUN-1003 : finish command "route" in  89.472229s wall, 121.812500s user + 0.609375s system = 122.421875s CPU (136.8%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1096 MB, peak memory is 1176 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10246   out of  19600   52.28%
+#reg                     9518   out of  19600   48.56%
+#le                     12528
+  #lut only              3010   out of  12528   24.03%
+  #reg only              2282   out of  12528   18.22%
+  #lut&reg               7236   out of  12528   57.76%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1778
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1415
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1336
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               980
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    144
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         71
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg2_syn_85.f1              3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/reg6_syn_113.f0                        3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P86        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12528  |9219    |1027    |9548    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |528    |429     |23      |443     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |98     |87      |4       |88      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |23     |23      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |6      |6       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |774    |373     |96      |567     |0       |0       |
+|    u_ADconfig                |AD_config            |182    |122     |25      |134     |0       |0       |
+|    u_gen_sp                  |gen_sp               |279    |176     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |757    |463     |96      |559     |0       |0       |
+|    u_ADconfig                |AD_config            |181    |147     |25      |127     |0       |0       |
+|    u_gen_sp                  |gen_sp               |266    |163     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2960   |2363    |306     |2117    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |178    |121     |17      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_sort                    |sort                 |2748   |2230    |289     |1949    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2290   |1861    |253     |1556    |22      |0       |
+|        channelPart           |channel_part_8478    |146    |141     |3       |130     |0       |0       |
+|        fifo_adc              |fifo_adc             |55     |46      |9       |38      |0       |0       |
+|        ram_switch            |ram_switch           |1781   |1427    |197     |1170    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |227    |200     |27      |121     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |10      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |1016   |689     |170     |718     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |538    |538     |0       |331     |0       |0       |
+|        read_ram_i            |read_ram             |281    |225     |44      |193     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |216    |176     |40      |147     |0       |0       |
+|          read_ram_data       |read_ram_data        |62     |47      |4       |43      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |309    |235     |36      |271     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3410   |2577    |349     |2173    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |186    |127     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |3194   |2426    |332     |1997    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |6       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2716   |2103    |290     |1590    |22      |1       |
+|        channelPart           |channel_part_8478    |232    |226     |3       |146     |0       |0       |
+|        fifo_adc              |fifo_adc             |61     |52      |9       |42      |0       |1       |
+|        ram_switch            |ram_switch           |2028   |1539    |197     |1159    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |229    |202     |27      |109     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |7      |4       |3       |1       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |1014   |552     |170     |724     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |785    |785     |0       |326     |0       |0       |
+|        read_ram_i            |read_ram_rev         |361    |256     |81      |209     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |298    |216     |73      |163     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |63     |40      |8       |46      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9895  
+    #2         2       3902  
+    #3         3       1478  
+    #4         4       630   
+    #5        5-10     1052  
+    #6       11-50     577   
+    #7       51-100     24   
+    #8        >500      1    
+  Average     2.89           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.068075s wall, 3.562500s user + 0.031250s system = 3.593750s CPU (173.8%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1097 MB, peak memory is 1176 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73966, tnet num: 17476, tinst num: 6872, tnode num: 96576, tedge num: 124157.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.565013s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.8%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1102 MB, peak memory is 1176 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17476 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.692717s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (85.8%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1104 MB, peak memory is 1176 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6872
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17654, pip num: 179817
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 731
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3211 valid insts, and 495128 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  11.324833s wall, 71.359375s user + 0.156250s system = 71.515625s CPU (631.5%)
+
+RUN-1004 : used memory is 1274 MB, reserved memory is 1271 MB, peak memory is 1389 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_162940.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_163709.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_163709.log
new file mode 100644
index 0000000..f4dae4e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_163709.log
@@ -0,0 +1,1914 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:37:09 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.123587s wall, 2.046875s user + 0.078125s system = 2.125000s CPU (100.1%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2278 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2118 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17811 instances
+RUN-0007 : 7417 luts, 9171 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20395 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13485 nets have 2 pins
+RUN-1001 : 5461 nets have [3 - 5] pins
+RUN-1001 : 1038 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 179 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     802     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3592     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17809 instances, 7417 luts, 9171 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 5891 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85146, tnet num: 20217, tinst num: 17809, tnode num: 115613, tedge num: 136608.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.145864s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.5%)
+
+RUN-1004 : used memory is 538 MB, reserved memory is 515 MB, peak memory is 538 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20217 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.941308s wall, 1.890625s user + 0.031250s system = 1.921875s CPU (99.0%)
+
+PHY-3001 : Found 3474 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.15825e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17809.
+PHY-3001 : Level 1 #clusters 2067.
+PHY-3001 : End clustering;  0.126912s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (110.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.2637e+06, overlap = 483.625
+PHY-3002 : Step(2): len = 1.18728e+06, overlap = 529.125
+PHY-3002 : Step(3): len = 830477, overlap = 595.406
+PHY-3002 : Step(4): len = 770635, overlap = 648.562
+PHY-3002 : Step(5): len = 605337, overlap = 759.375
+PHY-3002 : Step(6): len = 527440, overlap = 830.656
+PHY-3002 : Step(7): len = 450457, overlap = 920.594
+PHY-3002 : Step(8): len = 424610, overlap = 928.5
+PHY-3002 : Step(9): len = 379904, overlap = 980.406
+PHY-3002 : Step(10): len = 354883, overlap = 1013.47
+PHY-3002 : Step(11): len = 318525, overlap = 1097.44
+PHY-3002 : Step(12): len = 290679, overlap = 1144
+PHY-3002 : Step(13): len = 263817, overlap = 1184.38
+PHY-3002 : Step(14): len = 244951, overlap = 1229.66
+PHY-3002 : Step(15): len = 225054, overlap = 1280.84
+PHY-3002 : Step(16): len = 208414, overlap = 1304.88
+PHY-3002 : Step(17): len = 192248, overlap = 1364.59
+PHY-3002 : Step(18): len = 182589, overlap = 1387.22
+PHY-3002 : Step(19): len = 163608, overlap = 1441.25
+PHY-3002 : Step(20): len = 157856, overlap = 1455.72
+PHY-3002 : Step(21): len = 149689, overlap = 1462.34
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 7.23604e-07
+PHY-3002 : Step(22): len = 148734, overlap = 1435.16
+PHY-3002 : Step(23): len = 170996, overlap = 1386
+PHY-3002 : Step(24): len = 174841, overlap = 1300.47
+PHY-3002 : Step(25): len = 178606, overlap = 1303.91
+PHY-3002 : Step(26): len = 176316, overlap = 1238.91
+PHY-3002 : Step(27): len = 175771, overlap = 1224.84
+PHY-3002 : Step(28): len = 172870, overlap = 1252.5
+PHY-3002 : Step(29): len = 173351, overlap = 1275.59
+PHY-3002 : Step(30): len = 170713, overlap = 1266.22
+PHY-3002 : Step(31): len = 169603, overlap = 1255.38
+PHY-3002 : Step(32): len = 167654, overlap = 1240.66
+PHY-3002 : Step(33): len = 167937, overlap = 1224.66
+PHY-3002 : Step(34): len = 164958, overlap = 1232.84
+PHY-3002 : Step(35): len = 165170, overlap = 1237.53
+PHY-3002 : Step(36): len = 162954, overlap = 1253.19
+PHY-3002 : Step(37): len = 163412, overlap = 1268.66
+PHY-3002 : Step(38): len = 160945, overlap = 1277.66
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.44721e-06
+PHY-3002 : Step(39): len = 163240, overlap = 1254.31
+PHY-3002 : Step(40): len = 174530, overlap = 1218.62
+PHY-3002 : Step(41): len = 178496, overlap = 1183.5
+PHY-3002 : Step(42): len = 182268, overlap = 1144.44
+PHY-3002 : Step(43): len = 183260, overlap = 1124.97
+PHY-3002 : Step(44): len = 184595, overlap = 1112.56
+PHY-3002 : Step(45): len = 183706, overlap = 1089.72
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 2.89441e-06
+PHY-3002 : Step(46): len = 189510, overlap = 1069.84
+PHY-3002 : Step(47): len = 204904, overlap = 1035.44
+PHY-3002 : Step(48): len = 215874, overlap = 984.812
+PHY-3002 : Step(49): len = 222674, overlap = 1003.75
+PHY-3002 : Step(50): len = 224199, overlap = 1007.5
+PHY-3002 : Step(51): len = 224639, overlap = 995.5
+PHY-3002 : Step(52): len = 222765, overlap = 986.906
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 5.78883e-06
+PHY-3002 : Step(53): len = 234188, overlap = 985.719
+PHY-3002 : Step(54): len = 255815, overlap = 903.438
+PHY-3002 : Step(55): len = 266272, overlap = 819.969
+PHY-3002 : Step(56): len = 275565, overlap = 777.281
+PHY-3002 : Step(57): len = 278607, overlap = 745.406
+PHY-3002 : Step(58): len = 278929, overlap = 721.844
+PHY-3002 : Step(59): len = 278119, overlap = 727.531
+PHY-3002 : Step(60): len = 276338, overlap = 729.469
+PHY-3002 : Step(61): len = 274678, overlap = 764.844
+PHY-3002 : Step(62): len = 273105, overlap = 787.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.15777e-05
+PHY-3002 : Step(63): len = 290788, overlap = 730.281
+PHY-3002 : Step(64): len = 310028, overlap = 670.188
+PHY-3002 : Step(65): len = 317017, overlap = 570.5
+PHY-3002 : Step(66): len = 321283, overlap = 534.906
+PHY-3002 : Step(67): len = 322636, overlap = 539.625
+PHY-3002 : Step(68): len = 325346, overlap = 532.125
+PHY-3002 : Step(69): len = 322080, overlap = 519.969
+PHY-3002 : Step(70): len = 322328, overlap = 517.25
+PHY-3002 : Step(71): len = 321117, overlap = 530.469
+PHY-3002 : Step(72): len = 321702, overlap = 513.719
+PHY-3002 : Step(73): len = 319415, overlap = 502.438
+PHY-3002 : Step(74): len = 318869, overlap = 499.531
+PHY-3002 : Step(75): len = 318280, overlap = 491.906
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.31553e-05
+PHY-3002 : Step(76): len = 337537, overlap = 433.438
+PHY-3002 : Step(77): len = 349595, overlap = 392.094
+PHY-3002 : Step(78): len = 350006, overlap = 384.875
+PHY-3002 : Step(79): len = 350969, overlap = 382.156
+PHY-3002 : Step(80): len = 352198, overlap = 360.031
+PHY-3002 : Step(81): len = 355138, overlap = 356.375
+PHY-3002 : Step(82): len = 355134, overlap = 380.031
+PHY-3002 : Step(83): len = 356468, overlap = 375.219
+PHY-3002 : Step(84): len = 357428, overlap = 352.719
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 4.63106e-05
+PHY-3002 : Step(85): len = 376589, overlap = 315.5
+PHY-3002 : Step(86): len = 390960, overlap = 282.5
+PHY-3002 : Step(87): len = 390433, overlap = 283.031
+PHY-3002 : Step(88): len = 392438, overlap = 288.469
+PHY-3002 : Step(89): len = 394528, overlap = 267.562
+PHY-3002 : Step(90): len = 397178, overlap = 260.219
+PHY-3002 : Step(91): len = 394517, overlap = 251.531
+PHY-3002 : Step(92): len = 395474, overlap = 236.312
+PHY-3002 : Step(93): len = 396723, overlap = 231.594
+PHY-3002 : Step(94): len = 397867, overlap = 225
+PHY-3002 : Step(95): len = 396426, overlap = 220.625
+PHY-3002 : Step(96): len = 398457, overlap = 228.594
+PHY-3002 : Step(97): len = 399486, overlap = 247.938
+PHY-3002 : Step(98): len = 399685, overlap = 254.031
+PHY-3002 : Step(99): len = 398464, overlap = 253.031
+PHY-3002 : Step(100): len = 399219, overlap = 241.656
+PHY-3002 : Step(101): len = 399172, overlap = 241.094
+PHY-3002 : Step(102): len = 399869, overlap = 241.812
+PHY-3002 : Step(103): len = 399071, overlap = 228.531
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 9.26213e-05
+PHY-3002 : Step(104): len = 416828, overlap = 235.25
+PHY-3002 : Step(105): len = 430358, overlap = 214.406
+PHY-3002 : Step(106): len = 428001, overlap = 207.688
+PHY-3002 : Step(107): len = 427428, overlap = 193.375
+PHY-3002 : Step(108): len = 428339, overlap = 204.375
+PHY-3002 : Step(109): len = 430537, overlap = 201.188
+PHY-3002 : Step(110): len = 430131, overlap = 196.125
+PHY-3002 : Step(111): len = 432658, overlap = 202.812
+PHY-3002 : Step(112): len = 433633, overlap = 223.875
+PHY-3002 : Step(113): len = 434122, overlap = 226.406
+PHY-3002 : Step(114): len = 432414, overlap = 229.031
+PHY-3002 : Step(115): len = 431457, overlap = 228.75
+PHY-3002 : Step(116): len = 431685, overlap = 236.656
+PHY-3002 : Step(117): len = 433238, overlap = 230.625
+PHY-3002 : Step(118): len = 431451, overlap = 226.406
+PHY-3002 : Step(119): len = 431416, overlap = 234.656
+PHY-3002 : Step(120): len = 432151, overlap = 227.094
+PHY-3002 : Step(121): len = 432913, overlap = 221.281
+PHY-3002 : Step(122): len = 431417, overlap = 228.938
+PHY-3002 : Step(123): len = 431235, overlap = 228.094
+PHY-3002 : Step(124): len = 431586, overlap = 227.156
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000185243
+PHY-3002 : Step(125): len = 445265, overlap = 219.406
+PHY-3002 : Step(126): len = 455630, overlap = 224.656
+PHY-3002 : Step(127): len = 454624, overlap = 218.594
+PHY-3002 : Step(128): len = 455787, overlap = 211.812
+PHY-3002 : Step(129): len = 458609, overlap = 205.188
+PHY-3002 : Step(130): len = 460260, overlap = 203.812
+PHY-3002 : Step(131): len = 459026, overlap = 205
+PHY-3002 : Step(132): len = 460248, overlap = 212.312
+PHY-3002 : Step(133): len = 462622, overlap = 199.438
+PHY-3002 : Step(134): len = 464109, overlap = 202.156
+PHY-3002 : Step(135): len = 462792, overlap = 201.031
+PHY-3002 : Step(136): len = 462270, overlap = 199.406
+PHY-3002 : Step(137): len = 463905, overlap = 188.688
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000359414
+PHY-3002 : Step(138): len = 471455, overlap = 186.031
+PHY-3002 : Step(139): len = 479189, overlap = 194.031
+PHY-3002 : Step(140): len = 480351, overlap = 185.781
+PHY-3002 : Step(141): len = 482072, overlap = 181.188
+PHY-3002 : Step(142): len = 484193, overlap = 174.812
+PHY-3002 : Step(143): len = 486073, overlap = 175.719
+PHY-3002 : Step(144): len = 486388, overlap = 169.719
+PHY-3002 : Step(145): len = 487326, overlap = 173.219
+PHY-3002 : Step(146): len = 488904, overlap = 165.469
+PHY-3002 : Step(147): len = 490161, overlap = 175.281
+PHY-3002 : Step(148): len = 490377, overlap = 173.562
+PHY-3002 : Step(149): len = 491589, overlap = 165.594
+PHY-3002 : Step(150): len = 492833, overlap = 169.438
+PHY-3002 : Step(151): len = 492920, overlap = 172.5
+PHY-3002 : Step(152): len = 492244, overlap = 163.906
+PHY-3002 : Step(153): len = 492094, overlap = 166.594
+PHY-3002 : Step(154): len = 492469, overlap = 168.281
+PHY-3002 : Step(155): len = 492811, overlap = 163.312
+PHY-3002 : Step(156): len = 491764, overlap = 163.062
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000686224
+PHY-3002 : Step(157): len = 497264, overlap = 165.156
+PHY-3002 : Step(158): len = 503733, overlap = 162.406
+PHY-3002 : Step(159): len = 504695, overlap = 146.469
+PHY-3002 : Step(160): len = 505471, overlap = 144.938
+PHY-3002 : Step(161): len = 506911, overlap = 142.75
+PHY-3002 : Step(162): len = 508520, overlap = 141.875
+PHY-3002 : Step(163): len = 508588, overlap = 139.719
+PHY-3002 : Step(164): len = 509272, overlap = 135.969
+PHY-3002 : Step(165): len = 510779, overlap = 135.25
+PHY-3002 : Step(166): len = 512188, overlap = 133.312
+PHY-3002 : Step(167): len = 511907, overlap = 129.688
+PHY-3002 : Step(168): len = 511378, overlap = 121.906
+PHY-3002 : Step(169): len = 511570, overlap = 119.688
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00131315
+PHY-3002 : Step(170): len = 514131, overlap = 121.375
+PHY-3002 : Step(171): len = 518074, overlap = 123.938
+PHY-3002 : Step(172): len = 519716, overlap = 123.844
+PHY-3002 : Step(173): len = 520785, overlap = 123.594
+PHY-3002 : Step(174): len = 521481, overlap = 127.406
+PHY-3002 : Step(175): len = 522169, overlap = 126.656
+PHY-3002 : Step(176): len = 522486, overlap = 124.219
+PHY-3002 : Step(177): len = 522805, overlap = 122.719
+PHY-3002 : Step(178): len = 523177, overlap = 123.344
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00220756
+PHY-3002 : Step(179): len = 525437, overlap = 123.406
+PHY-3002 : Step(180): len = 529875, overlap = 119.219
+PHY-3002 : Step(181): len = 530733, overlap = 118.531
+PHY-3002 : Step(182): len = 531382, overlap = 118.781
+PHY-3002 : Step(183): len = 532034, overlap = 119.719
+PHY-3002 : Step(184): len = 532348, overlap = 119.594
+PHY-3002 : Step(185): len = 532605, overlap = 117.719
+PHY-3002 : Step(186): len = 533313, overlap = 117.844
+PHY-3002 : Step(187): len = 534225, overlap = 117.875
+PHY-3002 : Step(188): len = 534685, overlap = 120.188
+PHY-3002 : Step(189): len = 534647, overlap = 120.188
+PHY-3002 : Step(190): len = 534647, overlap = 120.188
+PHY-3002 : Step(191): len = 534654, overlap = 120.188
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.012290s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (127.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20395.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 692904, over cnt = 1577(4%), over = 7286, worst = 46
+PHY-1001 : End global iterations;  0.671327s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (132.7%)
+
+PHY-1001 : Congestion index: top1 = 85.91, top5 = 61.14, top10 = 51.75, top15 = 46.21.
+PHY-3001 : End congestion estimation;  0.895954s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (123.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20217 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.126286s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.3025e-05
+PHY-3002 : Step(192): len = 631527, overlap = 65.625
+PHY-3002 : Step(193): len = 640710, overlap = 66.6562
+PHY-3002 : Step(194): len = 640645, overlap = 78.6875
+PHY-3002 : Step(195): len = 636235, overlap = 69.3438
+PHY-3002 : Step(196): len = 634366, overlap = 86.4375
+PHY-3002 : Step(197): len = 641927, overlap = 93.9375
+PHY-3002 : Step(198): len = 653762, overlap = 89.6875
+PHY-3002 : Step(199): len = 661849, overlap = 89.0625
+PHY-3002 : Step(200): len = 665094, overlap = 78.4375
+PHY-3002 : Step(201): len = 668712, overlap = 80.4062
+PHY-3002 : Step(202): len = 669118, overlap = 77.7812
+PHY-3002 : Step(203): len = 671822, overlap = 72.9688
+PHY-3002 : Step(204): len = 674559, overlap = 75.9688
+PHY-3002 : Step(205): len = 673446, overlap = 82.2188
+PHY-3002 : Step(206): len = 675451, overlap = 84.4062
+PHY-3002 : Step(207): len = 676331, overlap = 72.7188
+PHY-3002 : Step(208): len = 675861, overlap = 66.4688
+PHY-3002 : Step(209): len = 675200, overlap = 65.0312
+PHY-3002 : Step(210): len = 676506, overlap = 59.0312
+PHY-3002 : Step(211): len = 674684, overlap = 57.9062
+PHY-3002 : Step(212): len = 674393, overlap = 57.2812
+PHY-3002 : Step(213): len = 673285, overlap = 56.7188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00018605
+PHY-3002 : Step(214): len = 676752, overlap = 51.0312
+PHY-3002 : Step(215): len = 679450, overlap = 50.125
+PHY-3002 : Step(216): len = 681359, overlap = 46.5312
+PHY-3002 : Step(217): len = 683523, overlap = 46.875
+PHY-3002 : Step(218): len = 687127, overlap = 46.6875
+PHY-3002 : Step(219): len = 686337, overlap = 45.375
+PHY-3002 : Step(220): len = 686733, overlap = 44
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.0003721
+PHY-3002 : Step(221): len = 689568, overlap = 42.9062
+PHY-3002 : Step(222): len = 694924, overlap = 38.4688
+PHY-3002 : Step(223): len = 707101, overlap = 35.0625
+PHY-3002 : Step(224): len = 710624, overlap = 33.625
+PHY-3002 : Step(225): len = 713696, overlap = 36.8125
+PHY-3002 : Step(226): len = 716836, overlap = 40.0938
+PHY-3002 : Step(227): len = 719714, overlap = 40.4375
+PHY-3002 : Step(228): len = 721078, overlap = 40.1562
+PHY-3002 : Step(229): len = 723838, overlap = 37.0625
+PHY-3002 : Step(230): len = 727806, overlap = 37.5
+PHY-3002 : Step(231): len = 726701, overlap = 35.375
+PHY-3002 : Step(232): len = 726830, overlap = 36.9375
+PHY-3002 : Step(233): len = 730056, overlap = 34.4375
+PHY-3002 : Step(234): len = 727963, overlap = 34.3125
+PHY-3002 : Step(235): len = 726456, overlap = 35.6875
+PHY-3002 : Step(236): len = 725508, overlap = 37.0625
+PHY-3002 : Step(237): len = 725069, overlap = 34.8125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000714957
+PHY-3002 : Step(238): len = 728213, overlap = 34.1875
+PHY-3002 : Step(239): len = 733378, overlap = 33.625
+PHY-3002 : Step(240): len = 738735, overlap = 30.1562
+PHY-3002 : Step(241): len = 743684, overlap = 27.7188
+PHY-3002 : Step(242): len = 745361, overlap = 32.0312
+PHY-3002 : Step(243): len = 746242, overlap = 34.8438
+PHY-3002 : Step(244): len = 749334, overlap = 36.3125
+PHY-3002 : Step(245): len = 746962, overlap = 39.375
+PHY-3002 : Step(246): len = 746436, overlap = 39.5312
+PHY-3002 : Step(247): len = 745623, overlap = 38.0312
+PHY-3002 : Step(248): len = 746130, overlap = 36.9062
+PHY-3002 : Step(249): len = 746418, overlap = 33.9688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00136015
+PHY-3002 : Step(250): len = 746249, overlap = 37.0312
+PHY-3002 : Step(251): len = 749370, overlap = 35.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 27/20395.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826784, over cnt = 2709(7%), over = 13808, worst = 78
+PHY-1001 : End global iterations;  1.343052s wall, 1.843750s user + 0.046875s system = 1.890625s CPU (140.8%)
+
+PHY-1001 : Congestion index: top1 = 114.48, top5 = 79.37, top10 = 67.04, top15 = 59.78.
+PHY-3001 : End congestion estimation;  1.643016s wall, 2.156250s user + 0.046875s system = 2.203125s CPU (134.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20217 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.209744s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117883
+PHY-3002 : Step(252): len = 746032, overlap = 260.656
+PHY-3002 : Step(253): len = 748292, overlap = 212.031
+PHY-3002 : Step(254): len = 737682, overlap = 195.156
+PHY-3002 : Step(255): len = 733469, overlap = 180.5
+PHY-3002 : Step(256): len = 728116, overlap = 171.219
+PHY-3002 : Step(257): len = 726185, overlap = 154.406
+PHY-3002 : Step(258): len = 721019, overlap = 140.812
+PHY-3002 : Step(259): len = 717009, overlap = 135.781
+PHY-3002 : Step(260): len = 713666, overlap = 131.719
+PHY-3002 : Step(261): len = 709692, overlap = 122.531
+PHY-3002 : Step(262): len = 706351, overlap = 123.25
+PHY-3002 : Step(263): len = 701640, overlap = 123.812
+PHY-3002 : Step(264): len = 699440, overlap = 125.031
+PHY-3002 : Step(265): len = 695513, overlap = 130.812
+PHY-3002 : Step(266): len = 692962, overlap = 135.094
+PHY-3002 : Step(267): len = 690749, overlap = 136.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000235767
+PHY-3002 : Step(268): len = 691627, overlap = 131.531
+PHY-3002 : Step(269): len = 695200, overlap = 122.562
+PHY-3002 : Step(270): len = 698386, overlap = 121
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000471533
+PHY-3002 : Step(271): len = 702863, overlap = 109.938
+PHY-3002 : Step(272): len = 711615, overlap = 93.8438
+PHY-3002 : Step(273): len = 714985, overlap = 90.0625
+PHY-3002 : Step(274): len = 714984, overlap = 90.6875
+PHY-3002 : Step(275): len = 715698, overlap = 89.2188
+PHY-3002 : Step(276): len = 716405, overlap = 86.6562
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85146, tnet num: 20217, tinst num: 17809, tnode num: 115613, tedge num: 136608.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.397000s wall, 1.328125s user + 0.062500s system = 1.390625s CPU (99.5%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 566 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 425.31 peak overflow 5.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 582/20395.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812680, over cnt = 3173(9%), over = 12278, worst = 54
+PHY-1001 : End global iterations;  1.299500s wall, 1.703125s user + 0.125000s system = 1.828125s CPU (140.7%)
+
+PHY-1001 : Congestion index: top1 = 84.59, top5 = 64.55, top10 = 57.19, top15 = 52.60.
+PHY-1001 : End incremental global routing;  1.615765s wall, 2.031250s user + 0.125000s system = 2.156250s CPU (133.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20217 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.912441s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (99.3%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17674 has valid locations, 348 needs to be replaced
+PHY-3001 : design contains 18107 instances, 7523 luts, 9363 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 6014 pins
+PHY-3001 : Found 3508 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 738342
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16773/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 828560, over cnt = 3240(9%), over = 12504, worst = 54
+PHY-1001 : End global iterations;  0.231111s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (128.5%)
+
+PHY-1001 : Congestion index: top1 = 84.70, top5 = 64.84, top10 = 57.49, top15 = 52.94.
+PHY-3001 : End congestion estimation;  0.475120s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (111.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86368, tnet num: 20515, tinst num: 18107, tnode num: 117440, tedge num: 138456.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.435403s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (100.1%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 613 MB, peak memory is 723 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.724056s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(277): len = 737286, overlap = 0.9375
+PHY-3002 : Step(278): len = 736990, overlap = 1.125
+PHY-3002 : Step(279): len = 736693, overlap = 1.1875
+PHY-3002 : Step(280): len = 736437, overlap = 1.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16870/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825728, over cnt = 3212(9%), over = 12453, worst = 54
+PHY-1001 : End global iterations;  0.184473s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (135.5%)
+
+PHY-1001 : Congestion index: top1 = 85.65, top5 = 65.54, top10 = 57.89, top15 = 53.23.
+PHY-3001 : End congestion estimation;  0.430225s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (112.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.907870s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000342947
+PHY-3002 : Step(281): len = 736384, overlap = 90.375
+PHY-3002 : Step(282): len = 736469, overlap = 90.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000685894
+PHY-3002 : Step(283): len = 736490, overlap = 89.5938
+PHY-3002 : Step(284): len = 736760, overlap = 89.5
+PHY-3001 : Final: Len = 736760, Over = 89.5
+PHY-3001 : End incremental placement;  5.157001s wall, 5.328125s user + 0.125000s system = 5.453125s CPU (105.7%)
+
+OPT-1001 : Total overflow 430.81 peak overflow 5.00
+OPT-1001 : End high-fanout net optimization;  8.311041s wall, 8.859375s user + 0.296875s system = 9.156250s CPU (110.2%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 713, peak = 742.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16863/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 828144, over cnt = 3184(9%), over = 11613, worst = 54
+PHY-1002 : len = 892488, over cnt = 2235(6%), over = 5512, worst = 45
+PHY-1002 : len = 931160, over cnt = 1024(2%), over = 2291, worst = 20
+PHY-1002 : len = 951296, over cnt = 434(1%), over = 780, worst = 12
+PHY-1002 : len = 969120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.261670s wall, 3.078125s user + 0.000000s system = 3.078125s CPU (136.1%)
+
+PHY-1001 : Congestion index: top1 = 64.05, top5 = 56.04, top10 = 52.01, top15 = 49.54.
+OPT-1001 : End congestion update;  2.514623s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (132.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.779645s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 55 cells processed and 7000 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 34 cells processed and 1600 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 13 cells processed and 1050 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 3 cells processed and 300 slack improved
+OPT-1001 : End global optimization;  3.336680s wall, 4.140625s user + 0.015625s system = 4.156250s CPU (124.6%)
+
+OPT-1001 : Current memory(MB): used = 703, reserve = 700, peak = 742.
+OPT-1001 : End physical optimization;  13.787713s wall, 15.140625s user + 0.406250s system = 15.546875s CPU (112.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7523 LUT to BLE ...
+SYN-4008 : Packed 7523 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6230 remaining SEQ's ...
+SYN-4005 : Packed 4042 SEQ with LUT/SLICE
+SYN-4006 : 658 single LUT's are left
+SYN-4006 : 2188 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9711/13442 primitive instances ...
+PHY-3001 : End packing;  1.587489s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6744 instances
+RUN-1001 : 3298 mslices, 3298 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17690 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10165 nets have 2 pins
+RUN-1001 : 5675 nets have [3 - 5] pins
+RUN-1001 : 1164 nets have [6 - 10] pins
+RUN-1001 : 323 nets have [11 - 20] pins
+RUN-1001 : 331 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6742 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3502 pins
+PHY-3001 : Found 1545 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 746833, Over = 258.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7402/17690.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 906512, over cnt = 2074(5%), over = 3392, worst = 8
+PHY-1002 : len = 915688, over cnt = 1313(3%), over = 1846, worst = 6
+PHY-1002 : len = 929912, over cnt = 452(1%), over = 596, worst = 5
+PHY-1002 : len = 937704, over cnt = 75(0%), over = 97, worst = 4
+PHY-1002 : len = 939416, over cnt = 17(0%), over = 24, worst = 3
+PHY-1001 : End global iterations;  1.574545s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 61.49, top5 = 54.56, top10 = 50.28, top15 = 47.58.
+PHY-3001 : End congestion estimation;  1.949534s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (136.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73793, tnet num: 17512, tinst num: 6742, tnode num: 96313, tedge num: 123776.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.565837s wall, 1.531250s user + 0.031250s system = 1.562500s CPU (99.8%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 609 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17512 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.410696s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.7366e-05
+PHY-3002 : Step(285): len = 734481, overlap = 261.75
+PHY-3002 : Step(286): len = 728087, overlap = 257
+PHY-3002 : Step(287): len = 724223, overlap = 264.5
+PHY-3002 : Step(288): len = 721100, overlap = 274.5
+PHY-3002 : Step(289): len = 718110, overlap = 278.25
+PHY-3002 : Step(290): len = 714630, overlap = 278.75
+PHY-3002 : Step(291): len = 710811, overlap = 273.25
+PHY-3002 : Step(292): len = 707271, overlap = 275.5
+PHY-3002 : Step(293): len = 703950, overlap = 276.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.47319e-05
+PHY-3002 : Step(294): len = 707593, overlap = 264
+PHY-3002 : Step(295): len = 712333, overlap = 256
+PHY-3002 : Step(296): len = 712929, overlap = 253.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000189464
+PHY-3002 : Step(297): len = 723725, overlap = 241.25
+PHY-3002 : Step(298): len = 732082, overlap = 238.25
+PHY-3002 : Step(299): len = 730047, overlap = 238.5
+PHY-3002 : Step(300): len = 729137, overlap = 239.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.327767s wall, 0.281250s user + 0.687500s system = 0.968750s CPU (295.6%)
+
+PHY-3001 : Trial Legalized: Len = 895180
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 498/17690.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.01202e+06, over cnt = 2856(8%), over = 4812, worst = 7
+PHY-1002 : len = 1.03135e+06, over cnt = 1730(4%), over = 2480, worst = 7
+PHY-1002 : len = 1.05098e+06, over cnt = 788(2%), over = 1037, worst = 6
+PHY-1002 : len = 1.06013e+06, over cnt = 358(1%), over = 475, worst = 5
+PHY-1002 : len = 1.06868e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.600359s wall, 3.750000s user + 0.015625s system = 3.765625s CPU (144.8%)
+
+PHY-1001 : Congestion index: top1 = 67.48, top5 = 59.44, top10 = 55.04, top15 = 52.09.
+PHY-3001 : End congestion estimation;  3.035681s wall, 4.203125s user + 0.015625s system = 4.218750s CPU (139.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17512 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.849844s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0001554
+PHY-3002 : Step(301): len = 854538, overlap = 71.25
+PHY-3002 : Step(302): len = 831068, overlap = 98.5
+PHY-3002 : Step(303): len = 816158, overlap = 124
+PHY-3002 : Step(304): len = 805081, overlap = 142.5
+PHY-3002 : Step(305): len = 795689, overlap = 165.5
+PHY-3002 : Step(306): len = 789868, overlap = 178
+PHY-3002 : Step(307): len = 783469, overlap = 195.75
+PHY-3002 : Step(308): len = 780454, overlap = 198.5
+PHY-3002 : Step(309): len = 777689, overlap = 201
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000310801
+PHY-3002 : Step(310): len = 783507, overlap = 197
+PHY-3002 : Step(311): len = 787359, overlap = 191.75
+PHY-3002 : Step(312): len = 788994, overlap = 184.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000551895
+PHY-3002 : Step(313): len = 796781, overlap = 179.25
+PHY-3002 : Step(314): len = 799835, overlap = 175.75
+PHY-3002 : Step(315): len = 802964, overlap = 173.75
+PHY-3002 : Step(316): len = 804471, overlap = 173.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.076412s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (102.2%)
+
+PHY-3001 : Legalized: Len = 860336, Over = 0
+PHY-3001 : Spreading special nets. 438 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.109040s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (100.3%)
+
+PHY-3001 : 647 instances has been re-located, deltaX = 213, deltaY = 461, maxDist = 17.
+PHY-3001 : Final: Len = 871700, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73793, tnet num: 17512, tinst num: 6745, tnode num: 96313, tedge num: 123776.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.803373s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.6%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 656 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3150/17690.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00088e+06, over cnt = 2692(7%), over = 4442, worst = 7
+PHY-1002 : len = 1.01355e+06, over cnt = 1773(5%), over = 2638, worst = 5
+PHY-1002 : len = 1.02579e+06, over cnt = 1115(3%), over = 1602, worst = 5
+PHY-1002 : len = 1.04463e+06, over cnt = 358(1%), over = 460, worst = 5
+PHY-1002 : len = 1.05218e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.052753s wall, 3.000000s user + 0.015625s system = 3.015625s CPU (146.9%)
+
+PHY-1001 : Congestion index: top1 = 64.70, top5 = 57.16, top10 = 53.24, top15 = 50.62.
+PHY-1001 : End incremental global routing;  2.409865s wall, 3.375000s user + 0.015625s system = 3.390625s CPU (140.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17512 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.838876s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (98.7%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6651 has valid locations, 30 needs to be replaced
+PHY-3001 : design contains 6769 instances, 6620 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3567 pins
+PHY-3001 : Found 1551 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 874710
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16150/17718.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0557e+06, over cnt = 91(0%), over = 111, worst = 5
+PHY-1002 : len = 1.05594e+06, over cnt = 27(0%), over = 30, worst = 3
+PHY-1002 : len = 1.05618e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.05634e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.05636e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.732128s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (104.6%)
+
+PHY-1001 : Congestion index: top1 = 64.70, top5 = 57.16, top10 = 53.25, top15 = 50.64.
+PHY-3001 : End congestion estimation;  1.031893s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (103.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74035, tnet num: 17540, tinst num: 6769, tnode num: 96615, tedge num: 124066.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.827868s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (100.0%)
+
+RUN-1004 : used memory is 671 MB, reserved memory is 671 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.962166s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(317): len = 874331, overlap = 0
+PHY-3002 : Step(318): len = 873787, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16147/17718.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05515e+06, over cnt = 52(0%), over = 72, worst = 7
+PHY-1002 : len = 1.05546e+06, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 1.05566e+06, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 1.05576e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.05582e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.735264s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (106.3%)
+
+PHY-1001 : Congestion index: top1 = 64.70, top5 = 57.16, top10 = 53.25, top15 = 50.64.
+PHY-3001 : End congestion estimation;  1.034962s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (104.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.975214s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000921101
+PHY-3002 : Step(319): len = 873773, overlap = 2.25
+PHY-3002 : Step(320): len = 873666, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005712s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 873882, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.056159s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (83.5%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 873898, Over = 0
+PHY-3001 : End incremental placement;  6.454688s wall, 6.671875s user + 0.140625s system = 6.812500s CPU (105.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.333303s wall, 11.593750s user + 0.171875s system = 11.765625s CPU (113.9%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 748, peak = 757.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16120/17718.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05506e+06, over cnt = 65(0%), over = 80, worst = 7
+PHY-1002 : len = 1.05534e+06, over cnt = 25(0%), over = 28, worst = 3
+PHY-1002 : len = 1.05559e+06, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 1.0557e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.0557e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.740805s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (109.7%)
+
+PHY-1001 : Congestion index: top1 = 64.70, top5 = 57.16, top10 = 53.25, top15 = 50.65.
+OPT-1001 : End congestion update;  1.035718s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (105.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.698383s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.7%)
+
+OPT-0007 : Start: WNS -1233 TNS -1887 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6681 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6769 instances, 6620 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3567 pins
+PHY-3001 : Found 1551 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 877093, Over = 0
+PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062877s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.4%)
+
+PHY-3001 : 25 instances has been re-located, deltaX = 16, deltaY = 27, maxDist = 8.
+PHY-3001 : Final: Len = 877851, Over = 0
+PHY-3001 : End incremental legalization;  0.370661s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.2%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 44 cells processed and 13318 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6681 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6769 instances, 6620 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3567 pins
+PHY-3001 : Found 1551 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 880581, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058867s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.6%)
+
+PHY-3001 : 19 instances has been re-located, deltaX = 7, deltaY = 23, maxDist = 8.
+PHY-3001 : Final: Len = 881119, Over = 0
+PHY-3001 : End incremental legalization;  0.366063s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (102.4%)
+
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 23 cells processed and 3968 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6681 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6769 instances, 6620 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3567 pins
+PHY-3001 : Found 1551 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 881563, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.057880s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.0%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 2, deltaY = 15, maxDist = 8.
+PHY-3001 : Final: Len = 881917, Over = 0
+PHY-3001 : End incremental legalization;  0.359777s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.9%)
+
+OPT-0007 : Iter 3: improved WNS -983 TNS -1518 NUM_FEPS 2 with 11 cells processed and 1688 slack improved
+OPT-1001 : End path based optimization;  3.219002s wall, 3.281250s user + 0.015625s system = 3.296875s CPU (102.4%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 748, peak = 757.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.750335s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15896/17718.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06363e+06, over cnt = 144(0%), over = 185, worst = 5
+PHY-1002 : len = 1.06371e+06, over cnt = 93(0%), over = 101, worst = 3
+PHY-1002 : len = 1.06422e+06, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 1.06432e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.06441e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.833876s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (106.8%)
+
+PHY-1001 : Congestion index: top1 = 64.66, top5 = 57.07, top10 = 53.12, top15 = 50.60.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.719264s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1033 TNS -1618 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 64.275862
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1033ps with logic level 2 
+RUN-1001 :       #2 path slack -947ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17718 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17718 nets
+OPT-1001 : End physical optimization;  18.341817s wall, 19.703125s user + 0.187500s system = 19.890625s CPU (108.4%)
+
+RUN-1003 : finish command "place" in  62.226393s wall, 95.812500s user + 6.406250s system = 102.218750s CPU (164.3%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 620 MB, peak memory is 757 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.665157s wall, 2.921875s user + 0.015625s system = 2.937500s CPU (176.4%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 621 MB, peak memory is 757 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6771 instances
+RUN-1001 : 3315 mslices, 3305 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17718 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10162 nets have 2 pins
+RUN-1001 : 5678 nets have [3 - 5] pins
+RUN-1001 : 1174 nets have [6 - 10] pins
+RUN-1001 : 333 nets have [11 - 20] pins
+RUN-1001 : 341 nets have [21 - 99] pins
+RUN-1001 : 10 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74035, tnet num: 17540, tinst num: 6769, tnode num: 96615, tedge num: 124066.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.550921s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (99.7%)
+
+RUN-1004 : used memory is 606 MB, reserved memory is 592 MB, peak memory is 757 MB
+PHY-1001 : 3315 mslices, 3305 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[89] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 991520, over cnt = 2872(8%), over = 4805, worst = 7
+PHY-1002 : len = 1.00906e+06, over cnt = 1847(5%), over = 2739, worst = 7
+PHY-1002 : len = 1.03372e+06, over cnt = 573(1%), over = 802, worst = 5
+PHY-1002 : len = 1.04553e+06, over cnt = 29(0%), over = 40, worst = 4
+PHY-1002 : len = 1.04661e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.976960s wall, 3.859375s user + 0.015625s system = 3.875000s CPU (130.2%)
+
+PHY-1001 : Congestion index: top1 = 64.89, top5 = 56.90, top10 = 52.80, top15 = 50.06.
+PHY-1001 : End global routing;  3.294120s wall, 4.171875s user + 0.015625s system = 4.187500s CPU (127.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 713, peak = 757.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 991, reserve = 987, peak = 991.
+PHY-1001 : End build detailed router design. 3.946697s wall, 3.921875s user + 0.015625s system = 3.937500s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 275200, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.690527s wall, 4.687500s user + 0.000000s system = 4.687500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 275256, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.404848s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1027, reserve = 1024, peak = 1027.
+PHY-1001 : End phase 1; 5.106946s wall, 5.109375s user + 0.000000s system = 5.109375s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.53985e+06, over cnt = 1987(0%), over = 1995, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1042, peak = 1045.
+PHY-1001 : End initial routed; 45.649923s wall, 75.015625s user + 0.421875s system = 75.437500s CPU (165.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16640(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.749   |  -3.646   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.196900s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1065, reserve = 1061, peak = 1065.
+PHY-1001 : End phase 2; 48.846890s wall, 78.203125s user + 0.421875s system = 78.625000s CPU (161.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.749ns STNS -3.646ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.136141s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.3%)
+
+PHY-1022 : len = 2.53985e+06, over cnt = 1988(0%), over = 1996, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.394764s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.49864e+06, over cnt = 734(0%), over = 734, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.233566s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (153.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.49376e+06, over cnt = 114(0%), over = 114, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.103088s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (124.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.49452e+06, over cnt = 27(0%), over = 27, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.381511s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (131.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.49493e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.215468s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (108.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.49504e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.249195s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (100.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16640(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.749   |  -3.646   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.226219s wall, 3.218750s user + 0.015625s system = 3.234375s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 675 feed throughs used by 482 nets
+PHY-1001 : End commit to database; 2.330027s wall, 2.281250s user + 0.046875s system = 2.328125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1158, reserve = 1160, peak = 1158.
+PHY-1001 : End phase 3; 10.502619s wall, 12.031250s user + 0.078125s system = 12.109375s CPU (115.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.749ns STNS -3.646ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.137589s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1022 : len = 2.49504e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.373941s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.749ns, -3.646ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16640(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.749   |  -3.646   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.191543s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 675 feed throughs used by 482 nets
+PHY-1001 : End commit to database; 2.383147s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1170, peak = 1168.
+PHY-1001 : End phase 4; 5.975488s wall, 5.968750s user + 0.000000s system = 5.968750s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.49504e+06
+PHY-1001 : Current memory(MB): used = 1172, reserve = 1175, peak = 1172.
+PHY-1001 : End export database. 0.060564s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.2%)
+
+PHY-1001 : End detail routing;  74.827121s wall, 105.703125s user + 0.515625s system = 106.218750s CPU (142.0%)
+
+RUN-1003 : finish command "route" in  80.726620s wall, 112.453125s user + 0.546875s system = 113.000000s CPU (140.0%)
+
+RUN-1004 : used memory is 1045 MB, reserved memory is 1049 MB, peak memory is 1172 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10240   out of  19600   52.24%
+#reg                     9516   out of  19600   48.55%
+#le                     12366
+  #lut only              2850   out of  12366   23.05%
+  #reg only              2126   out of  12366   17.19%
+  #lut&reg               7390   out of  12366   59.76%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1806
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1413
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1308
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               973
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    139
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg2_syn_78.f1              3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg1_syn_197.f0             3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT         P3        LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P162       LVCMOS33           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12366  |9213    |1027    |9546    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |536    |458     |23      |440     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |105    |93      |4       |91      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |33     |33      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |9      |9       |0       |8       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |769    |379     |96      |574     |0       |0       |
+|    u_ADconfig                |AD_config            |192    |120     |25      |142     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |154     |71      |116     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |720    |429     |96      |536     |0       |0       |
+|    u_ADconfig                |AD_config            |168    |128     |25      |122     |0       |0       |
+|    u_gen_sp                  |gen_sp               |256    |156     |71      |118     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3032   |2376    |306     |2128    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |174    |140     |17      |135     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2832   |2225    |289     |1967    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2346   |1880    |253     |1568    |22      |0       |
+|        channelPart           |channel_part_8478    |151    |147     |3       |130     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |43      |0       |0       |
+|        ram_switch            |ram_switch           |1834   |1453    |197     |1173    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |235    |208     |27      |126     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |12      |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |980    |627     |170     |689     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |619    |618     |0       |358     |0       |0       |
+|        read_ram_i            |read_ram             |273    |215     |44      |192     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |214    |174     |40      |147     |0       |0       |
+|          read_ram_data       |read_ram_data        |54     |38      |4       |40      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |345    |230     |36      |279     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3173   |2459    |349     |2168    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |184    |118     |17      |143     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2958   |2312    |332     |1994    |25      |1       |
+|      u0_rdsoft_n             |cdc_sync             |8      |7       |0       |8       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2484   |1943    |290     |1595    |22      |1       |
+|        channelPart           |channel_part_8478    |236    |224     |3       |146     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |1792   |1376    |197     |1166    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |206    |179     |27      |117     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |8       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|          insert              |insert               |1006   |631     |170     |712     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |580    |566     |0       |337     |0       |0       |
+|        read_ram_i            |read_ram_rev         |373    |273     |81      |217     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |306    |229     |73      |167     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |67     |44      |8       |50      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets   
+    #1          1       10100  
+    #2          2       3773   
+    #3          3       1395   
+    #4          4        507   
+    #5        5-10      1226   
+    #6        11-50      596   
+    #7       51-100      24    
+    #8       101-500      1    
+    #9        >500        1    
+  Average     2.89             
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.044808s wall, 3.531250s user + 0.000000s system = 3.531250s CPU (172.7%)
+
+RUN-1004 : used memory is 1047 MB, reserved memory is 1051 MB, peak memory is 1172 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74035, tnet num: 17540, tinst num: 6769, tnode num: 96615, tedge num: 124066.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.580155s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.9%)
+
+RUN-1004 : used memory is 1051 MB, reserved memory is 1056 MB, peak memory is 1172 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17540 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.469875s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1099 MB, peak memory is 1172 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6769
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17718, pip num: 177586
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 675
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3231 valid insts, and 489801 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.374843s wall, 68.265625s user + 0.156250s system = 68.421875s CPU (659.5%)
+
+RUN-1004 : used memory is 1279 MB, reserved memory is 1276 MB, peak memory is 1395 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_163709.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_164841.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_164841.log
new file mode 100644
index 0000000..1c46909
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_164841.log
@@ -0,0 +1,1979 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:48:41 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  1.950906s wall, 1.890625s user + 0.046875s system = 1.937500s CPU (99.3%)
+
+RUN-1004 : used memory is 320 MB, reserved memory is 290 MB, peak memory is 324 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (890 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2117 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 14463 instances
+RUN-0007 : 5692 luts, 7749 seqs, 569 mslices, 306 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 16602 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10934 nets have 2 pins
+RUN-1001 : 4615 nets have [3 - 5] pins
+RUN-1001 : 690 nets have [6 - 10] pins
+RUN-1001 : 139 nets have [11 - 20] pins
+RUN-1001 : 163 nets have [21 - 99] pins
+RUN-1001 : 41 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     664     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    2850     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2131     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  68   |     52     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 131
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 14461 instances, 5692 luts, 7749 seqs, 875 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 4995 pins
+PHY-0007 : Cell area utilization is 40%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 68609, tnet num: 16468, tinst num: 14461, tnode num: 94308, tedge num: 109762.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.011254s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (98.9%)
+
+RUN-1004 : used memory is 478 MB, reserved memory is 453 MB, peak memory is 478 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 16468 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.631654s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (99.6%)
+
+PHY-3001 : Found 2354 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.31955e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 14461.
+PHY-3001 : Level 1 #clusters 1811.
+PHY-3001 : End clustering;  0.100178s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (93.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 40%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.09015e+06, overlap = 350.062
+PHY-3002 : Step(2): len = 1.01644e+06, overlap = 387.219
+PHY-3002 : Step(3): len = 772943, overlap = 444.125
+PHY-3002 : Step(4): len = 587826, overlap = 538.312
+PHY-3002 : Step(5): len = 518266, overlap = 571.844
+PHY-3002 : Step(6): len = 443761, overlap = 659.844
+PHY-3002 : Step(7): len = 374479, overlap = 692.188
+PHY-3002 : Step(8): len = 329857, overlap = 752.625
+PHY-3002 : Step(9): len = 302425, overlap = 787.469
+PHY-3002 : Step(10): len = 269721, overlap = 833.344
+PHY-3002 : Step(11): len = 253637, overlap = 877.188
+PHY-3002 : Step(12): len = 228027, overlap = 914.188
+PHY-3002 : Step(13): len = 214732, overlap = 931.688
+PHY-3002 : Step(14): len = 200358, overlap = 966.281
+PHY-3002 : Step(15): len = 178416, overlap = 1049
+PHY-3002 : Step(16): len = 162307, overlap = 1095.47
+PHY-3002 : Step(17): len = 151005, overlap = 1119.38
+PHY-3002 : Step(18): len = 137159, overlap = 1159.22
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.09317e-06
+PHY-3002 : Step(19): len = 145640, overlap = 1115
+PHY-3002 : Step(20): len = 185340, overlap = 1019.5
+PHY-3002 : Step(21): len = 185319, overlap = 983.25
+PHY-3002 : Step(22): len = 185042, overlap = 979.625
+PHY-3002 : Step(23): len = 183040, overlap = 947.969
+PHY-3002 : Step(24): len = 179847, overlap = 888.5
+PHY-3002 : Step(25): len = 174513, overlap = 875.219
+PHY-3002 : Step(26): len = 173367, overlap = 869.312
+PHY-3002 : Step(27): len = 170608, overlap = 867.906
+PHY-3002 : Step(28): len = 169923, overlap = 881.812
+PHY-3002 : Step(29): len = 167849, overlap = 865.875
+PHY-3002 : Step(30): len = 166332, overlap = 847.531
+PHY-3002 : Step(31): len = 164895, overlap = 798.5
+PHY-3002 : Step(32): len = 161568, overlap = 820.219
+PHY-3002 : Step(33): len = 159878, overlap = 820.562
+PHY-3002 : Step(34): len = 157283, overlap = 810.25
+PHY-3002 : Step(35): len = 154950, overlap = 834
+PHY-3002 : Step(36): len = 153585, overlap = 850.938
+PHY-3002 : Step(37): len = 151540, overlap = 851.469
+PHY-3002 : Step(38): len = 150815, overlap = 849.938
+PHY-3002 : Step(39): len = 148147, overlap = 845.062
+PHY-3002 : Step(40): len = 147775, overlap = 842.844
+PHY-3002 : Step(41): len = 145487, overlap = 850.438
+PHY-3002 : Step(42): len = 144754, overlap = 846.406
+PHY-3002 : Step(43): len = 144345, overlap = 848.938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.18635e-06
+PHY-3002 : Step(44): len = 145794, overlap = 837.344
+PHY-3002 : Step(45): len = 155042, overlap = 825.031
+PHY-3002 : Step(46): len = 159089, overlap = 833.656
+PHY-3002 : Step(47): len = 163831, overlap = 855.906
+PHY-3002 : Step(48): len = 166164, overlap = 852.5
+PHY-3002 : Step(49): len = 165988, overlap = 846.375
+PHY-3002 : Step(50): len = 165001, overlap = 831.531
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.3727e-06
+PHY-3002 : Step(51): len = 171153, overlap = 802.938
+PHY-3002 : Step(52): len = 187330, overlap = 670.25
+PHY-3002 : Step(53): len = 198361, overlap = 625.812
+PHY-3002 : Step(54): len = 205378, overlap = 605.375
+PHY-3002 : Step(55): len = 207131, overlap = 572.688
+PHY-3002 : Step(56): len = 207977, overlap = 545.5
+PHY-3002 : Step(57): len = 207678, overlap = 554.938
+PHY-3002 : Step(58): len = 207197, overlap = 552.844
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.74539e-06
+PHY-3002 : Step(59): len = 220179, overlap = 520.625
+PHY-3002 : Step(60): len = 237853, overlap = 463.812
+PHY-3002 : Step(61): len = 244930, overlap = 412.062
+PHY-3002 : Step(62): len = 248987, overlap = 397.031
+PHY-3002 : Step(63): len = 250988, overlap = 397.094
+PHY-3002 : Step(64): len = 251056, overlap = 390.156
+PHY-3002 : Step(65): len = 248147, overlap = 383.531
+PHY-3002 : Step(66): len = 246932, overlap = 389.688
+PHY-3002 : Step(67): len = 245335, overlap = 382.531
+PHY-3002 : Step(68): len = 244958, overlap = 382.75
+PHY-3002 : Step(69): len = 243638, overlap = 391.625
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.74908e-05
+PHY-3002 : Step(70): len = 258777, overlap = 359.344
+PHY-3002 : Step(71): len = 275021, overlap = 325.156
+PHY-3002 : Step(72): len = 281709, overlap = 328.625
+PHY-3002 : Step(73): len = 285155, overlap = 319.5
+PHY-3002 : Step(74): len = 286018, overlap = 295.031
+PHY-3002 : Step(75): len = 286919, overlap = 279.156
+PHY-3002 : Step(76): len = 287427, overlap = 265.75
+PHY-3002 : Step(77): len = 289448, overlap = 259.031
+PHY-3002 : Step(78): len = 289119, overlap = 261.312
+PHY-3002 : Step(79): len = 289180, overlap = 266.625
+PHY-3002 : Step(80): len = 288262, overlap = 270.625
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.49816e-05
+PHY-3002 : Step(81): len = 304368, overlap = 256.781
+PHY-3002 : Step(82): len = 316894, overlap = 247.438
+PHY-3002 : Step(83): len = 320547, overlap = 236
+PHY-3002 : Step(84): len = 323904, overlap = 230.938
+PHY-3002 : Step(85): len = 324788, overlap = 220.281
+PHY-3002 : Step(86): len = 326390, overlap = 220.719
+PHY-3002 : Step(87): len = 325825, overlap = 226.875
+PHY-3002 : Step(88): len = 326529, overlap = 220.062
+PHY-3002 : Step(89): len = 327398, overlap = 210.125
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.99632e-05
+PHY-3002 : Step(90): len = 340137, overlap = 187.844
+PHY-3002 : Step(91): len = 354262, overlap = 163.906
+PHY-3002 : Step(92): len = 357860, overlap = 160.688
+PHY-3002 : Step(93): len = 360780, overlap = 157.688
+PHY-3002 : Step(94): len = 362397, overlap = 151.938
+PHY-3002 : Step(95): len = 365812, overlap = 140.719
+PHY-3002 : Step(96): len = 363204, overlap = 153.688
+PHY-3002 : Step(97): len = 362291, overlap = 158.938
+PHY-3002 : Step(98): len = 362764, overlap = 144.938
+PHY-3002 : Step(99): len = 364378, overlap = 145.469
+PHY-3002 : Step(100): len = 363591, overlap = 152.062
+PHY-3002 : Step(101): len = 364813, overlap = 149.812
+PHY-3002 : Step(102): len = 366379, overlap = 153.125
+PHY-3002 : Step(103): len = 368335, overlap = 160.312
+PHY-3002 : Step(104): len = 368915, overlap = 157.094
+PHY-3002 : Step(105): len = 368729, overlap = 150.719
+PHY-3002 : Step(106): len = 368378, overlap = 136.562
+PHY-3002 : Step(107): len = 369823, overlap = 142.625
+PHY-3002 : Step(108): len = 370195, overlap = 147.656
+PHY-3002 : Step(109): len = 367185, overlap = 148.438
+PHY-3002 : Step(110): len = 367333, overlap = 141
+PHY-3002 : Step(111): len = 367138, overlap = 132.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000139926
+PHY-3002 : Step(112): len = 378915, overlap = 129.156
+PHY-3002 : Step(113): len = 387032, overlap = 118.812
+PHY-3002 : Step(114): len = 387540, overlap = 117.25
+PHY-3002 : Step(115): len = 388661, overlap = 114.781
+PHY-3002 : Step(116): len = 390840, overlap = 124.031
+PHY-3002 : Step(117): len = 392812, overlap = 115.344
+PHY-3002 : Step(118): len = 392043, overlap = 115.406
+PHY-3002 : Step(119): len = 392687, overlap = 115.75
+PHY-3002 : Step(120): len = 396432, overlap = 114.656
+PHY-3002 : Step(121): len = 400514, overlap = 122.094
+PHY-3002 : Step(122): len = 398695, overlap = 115.031
+PHY-3002 : Step(123): len = 399146, overlap = 121.75
+PHY-3002 : Step(124): len = 400016, overlap = 126.281
+PHY-3002 : Step(125): len = 401403, overlap = 125.625
+PHY-3002 : Step(126): len = 399874, overlap = 124
+PHY-3002 : Step(127): len = 400401, overlap = 117.594
+PHY-3002 : Step(128): len = 401268, overlap = 123.281
+PHY-3002 : Step(129): len = 401693, overlap = 121.5
+PHY-3002 : Step(130): len = 400216, overlap = 112.594
+PHY-3002 : Step(131): len = 399891, overlap = 112.719
+PHY-3002 : Step(132): len = 400263, overlap = 113.281
+PHY-3002 : Step(133): len = 401221, overlap = 115.438
+PHY-3002 : Step(134): len = 399396, overlap = 116.938
+PHY-3002 : Step(135): len = 399404, overlap = 112.312
+PHY-3002 : Step(136): len = 400263, overlap = 107.219
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000279853
+PHY-3002 : Step(137): len = 407853, overlap = 110.219
+PHY-3002 : Step(138): len = 414565, overlap = 110.469
+PHY-3002 : Step(139): len = 417326, overlap = 114.625
+PHY-3002 : Step(140): len = 420419, overlap = 116.25
+PHY-3002 : Step(141): len = 422411, overlap = 115.938
+PHY-3002 : Step(142): len = 424561, overlap = 116.875
+PHY-3002 : Step(143): len = 424277, overlap = 118.688
+PHY-3002 : Step(144): len = 424959, overlap = 119.812
+PHY-3002 : Step(145): len = 425235, overlap = 118.812
+PHY-3002 : Step(146): len = 425765, overlap = 118.031
+PHY-3002 : Step(147): len = 425855, overlap = 107.312
+PHY-3002 : Step(148): len = 426197, overlap = 104.969
+PHY-3002 : Step(149): len = 426180, overlap = 107.125
+PHY-3002 : Step(150): len = 426166, overlap = 107.25
+PHY-3002 : Step(151): len = 425235, overlap = 111.594
+PHY-3002 : Step(152): len = 424930, overlap = 112.062
+PHY-3002 : Step(153): len = 425443, overlap = 108
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000541276
+PHY-3002 : Step(154): len = 430713, overlap = 106.031
+PHY-3002 : Step(155): len = 436309, overlap = 110.594
+PHY-3002 : Step(156): len = 438650, overlap = 104.844
+PHY-3002 : Step(157): len = 441714, overlap = 105.594
+PHY-3002 : Step(158): len = 443850, overlap = 99.0625
+PHY-3002 : Step(159): len = 445706, overlap = 98.75
+PHY-3002 : Step(160): len = 446151, overlap = 96.9688
+PHY-3002 : Step(161): len = 446852, overlap = 98.0625
+PHY-3002 : Step(162): len = 447554, overlap = 89.0625
+PHY-3002 : Step(163): len = 447924, overlap = 87.375
+PHY-3002 : Step(164): len = 447036, overlap = 91.8125
+PHY-3002 : Step(165): len = 446772, overlap = 94.3125
+PHY-3002 : Step(166): len = 447073, overlap = 95.5
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000988672
+PHY-3002 : Step(167): len = 450058, overlap = 99.0625
+PHY-3002 : Step(168): len = 453620, overlap = 96.375
+PHY-3002 : Step(169): len = 455415, overlap = 93.5
+PHY-3002 : Step(170): len = 457094, overlap = 90.7188
+PHY-3002 : Step(171): len = 458579, overlap = 91.1562
+PHY-3002 : Step(172): len = 459655, overlap = 91.6562
+PHY-3002 : Step(173): len = 459546, overlap = 90.3438
+PHY-3002 : Step(174): len = 459854, overlap = 89.2812
+PHY-3002 : Step(175): len = 460776, overlap = 89.0938
+PHY-3002 : Step(176): len = 461233, overlap = 90.5312
+PHY-3002 : Step(177): len = 461129, overlap = 90.7812
+PHY-3002 : Step(178): len = 461161, overlap = 90.4062
+PHY-3002 : Step(179): len = 461782, overlap = 90.0312
+PHY-3002 : Step(180): len = 461961, overlap = 90.0312
+PHY-3002 : Step(181): len = 461873, overlap = 92.2188
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00182088
+PHY-3002 : Step(182): len = 464636, overlap = 92.2188
+PHY-3002 : Step(183): len = 470069, overlap = 91.7812
+PHY-3002 : Step(184): len = 471340, overlap = 89.8125
+PHY-3002 : Step(185): len = 472725, overlap = 85.4062
+PHY-3002 : Step(186): len = 474494, overlap = 85.6562
+PHY-3002 : Step(187): len = 475309, overlap = 85.7188
+PHY-3002 : Step(188): len = 475005, overlap = 87.9062
+PHY-3002 : Step(189): len = 475009, overlap = 89.3438
+PHY-3002 : Step(190): len = 476023, overlap = 84.0312
+PHY-3002 : Step(191): len = 476569, overlap = 79.6562
+PHY-3002 : Step(192): len = 476340, overlap = 84.4688
+PHY-3002 : Step(193): len = 476343, overlap = 86.7188
+PHY-3002 : Step(194): len = 476813, overlap = 78.9688
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00313602
+PHY-3002 : Step(195): len = 478267, overlap = 82.2188
+PHY-3002 : Step(196): len = 480470, overlap = 83.5312
+PHY-3002 : Step(197): len = 481081, overlap = 83.9688
+PHY-3002 : Step(198): len = 481728, overlap = 84.0625
+PHY-3002 : Step(199): len = 483706, overlap = 82.7812
+PHY-3002 : Step(200): len = 486489, overlap = 80.2188
+PHY-3002 : Step(201): len = 489211, overlap = 78.2188
+PHY-3002 : Step(202): len = 492814, overlap = 74.1875
+PHY-3002 : Step(203): len = 494348, overlap = 81.7812
+PHY-3002 : Step(204): len = 495523, overlap = 81.0938
+PHY-3002 : Step(205): len = 496029, overlap = 74.7188
+PHY-3002 : Step(206): len = 496264, overlap = 74.7188
+PHY-3002 : Step(207): len = 496312, overlap = 74.7188
+PHY-3002 : Step(208): len = 496339, overlap = 74.7188
+PHY-3002 : Step(209): len = 496484, overlap = 74.7812
+PHY-3002 : Step(210): len = 496552, overlap = 74.2188
+PHY-3002 : Step(211): len = 496590, overlap = 74.4688
+PHY-3002 : Step(212): len = 496703, overlap = 71.9688
+PHY-3002 : Step(213): len = 496994, overlap = 71.9688
+PHY-3002 : Step(214): len = 497168, overlap = 71.9688
+PHY-3002 : Step(215): len = 497049, overlap = 71.4688
+PHY-3002 : Step(216): len = 497016, overlap = 70.25
+PHY-3002 : Step(217): len = 497201, overlap = 67.5625
+PHY-3002 : Step(218): len = 497237, overlap = 68.125
+PHY-3002 : Step(219): len = 497192, overlap = 68.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.010490s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (149.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 47%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/16602.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 603200, over cnt = 1252(3%), over = 5480, worst = 35
+PHY-1001 : End global iterations;  0.583929s wall, 0.734375s user + 0.031250s system = 0.765625s CPU (131.1%)
+
+PHY-1001 : Congestion index: top1 = 78.10, top5 = 56.33, top10 = 47.27, top15 = 41.91.
+PHY-3001 : End congestion estimation;  0.784428s wall, 0.937500s user + 0.031250s system = 0.968750s CPU (123.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16468 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.670873s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000162839
+PHY-3002 : Step(220): len = 546674, overlap = 17.5
+PHY-3002 : Step(221): len = 550549, overlap = 23.0312
+PHY-3002 : Step(222): len = 544469, overlap = 21.7812
+PHY-3002 : Step(223): len = 543154, overlap = 16.5625
+PHY-3002 : Step(224): len = 541350, overlap = 16.3438
+PHY-3002 : Step(225): len = 540254, overlap = 15.875
+PHY-3002 : Step(226): len = 541303, overlap = 14.4062
+PHY-3002 : Step(227): len = 540963, overlap = 13.5938
+PHY-3002 : Step(228): len = 541059, overlap = 14.5938
+PHY-3002 : Step(229): len = 538380, overlap = 18.1875
+PHY-3002 : Step(230): len = 536812, overlap = 19.5
+PHY-3002 : Step(231): len = 534515, overlap = 19.4062
+PHY-3002 : Step(232): len = 532687, overlap = 20.5938
+PHY-3002 : Step(233): len = 529871, overlap = 21
+PHY-3002 : Step(234): len = 527543, overlap = 21.5312
+PHY-3002 : Step(235): len = 525084, overlap = 20.5312
+PHY-3002 : Step(236): len = 523458, overlap = 21
+PHY-3002 : Step(237): len = 521684, overlap = 21.1562
+PHY-3002 : Step(238): len = 520746, overlap = 21.125
+PHY-3002 : Step(239): len = 519226, overlap = 20.9062
+PHY-3002 : Step(240): len = 518546, overlap = 20.125
+PHY-3002 : Step(241): len = 517187, overlap = 19.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000325678
+PHY-3002 : Step(242): len = 520535, overlap = 20.0312
+PHY-3002 : Step(243): len = 521857, overlap = 19.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 47%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 76/16602.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 588800, over cnt = 2084(5%), over = 8758, worst = 33
+PHY-1001 : End global iterations;  1.280685s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (120.8%)
+
+PHY-1001 : Congestion index: top1 = 77.91, top5 = 58.31, top10 = 50.37, top15 = 45.48.
+PHY-3001 : End congestion estimation;  1.520134s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (117.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16468 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.773273s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000105255
+PHY-3002 : Step(244): len = 519882, overlap = 195.031
+PHY-3002 : Step(245): len = 523628, overlap = 164.281
+PHY-3002 : Step(246): len = 521090, overlap = 149.375
+PHY-3002 : Step(247): len = 520658, overlap = 130.438
+PHY-3002 : Step(248): len = 523635, overlap = 114.688
+PHY-3002 : Step(249): len = 519470, overlap = 107.469
+PHY-3002 : Step(250): len = 518458, overlap = 107.719
+PHY-3002 : Step(251): len = 516951, overlap = 104.062
+PHY-3002 : Step(252): len = 514142, overlap = 103.281
+PHY-3002 : Step(253): len = 512800, overlap = 102.656
+PHY-3002 : Step(254): len = 512622, overlap = 95.0625
+PHY-3002 : Step(255): len = 509186, overlap = 92.8125
+PHY-3002 : Step(256): len = 507256, overlap = 87
+PHY-3002 : Step(257): len = 505920, overlap = 81.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000210511
+PHY-3002 : Step(258): len = 506935, overlap = 79.375
+PHY-3002 : Step(259): len = 508302, overlap = 76.2188
+PHY-3002 : Step(260): len = 511289, overlap = 67.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000421022
+PHY-3002 : Step(261): len = 518297, overlap = 55
+PHY-3002 : Step(262): len = 524550, overlap = 49.9688
+PHY-3002 : Step(263): len = 529323, overlap = 51.0625
+PHY-3002 : Step(264): len = 530099, overlap = 51.2812
+PHY-3002 : Step(265): len = 529889, overlap = 50.9688
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 68609, tnet num: 16468, tinst num: 14461, tnode num: 94308, tedge num: 109762.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.233113s wall, 1.187500s user + 0.046875s system = 1.234375s CPU (100.1%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 499 MB, peak memory is 627 MB
+OPT-1001 : Total overflow 340.97 peak overflow 2.81
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 968/16602.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 607240, over cnt = 2364(6%), over = 8035, worst = 22
+PHY-1001 : End global iterations;  1.005367s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (136.8%)
+
+PHY-1001 : Congestion index: top1 = 70.50, top5 = 52.80, top10 = 46.06, top15 = 42.25.
+PHY-1001 : End incremental global routing;  1.271608s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (129.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16468 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.741505s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.0%)
+
+OPT-1001 : 38 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 14338 has valid locations, 241 needs to be replaced
+PHY-3001 : design contains 14664 instances, 5775 luts, 7869 seqs, 875 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 5084 pins
+PHY-3001 : Found 2376 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 545281
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 47%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13626/16805.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 617392, over cnt = 2387(6%), over = 8073, worst = 22
+PHY-1001 : End global iterations;  0.181859s wall, 0.250000s user + 0.031250s system = 0.281250s CPU (154.7%)
+
+PHY-1001 : Congestion index: top1 = 70.15, top5 = 52.73, top10 = 46.15, top15 = 42.35.
+PHY-3001 : End congestion estimation;  0.399230s wall, 0.468750s user + 0.031250s system = 0.500000s CPU (125.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 69430, tnet num: 16671, tinst num: 14664, tnode num: 95495, tedge num: 110998.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.233496s wall, 1.203125s user + 0.031250s system = 1.234375s CPU (100.1%)
+
+RUN-1004 : used memory is 559 MB, reserved memory is 550 MB, peak memory is 629 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.006449s wall, 1.953125s user + 0.046875s system = 2.000000s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(266): len = 544640, overlap = 0
+PHY-3002 : Step(267): len = 544361, overlap = 0
+PHY-3002 : Step(268): len = 544337, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 47%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 13700/16805.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 615408, over cnt = 2399(6%), over = 8095, worst = 22
+PHY-1001 : End global iterations;  0.157384s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (129.1%)
+
+PHY-1001 : Congestion index: top1 = 70.43, top5 = 52.91, top10 = 46.24, top15 = 42.42.
+PHY-3001 : End congestion estimation;  0.375791s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (112.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.746433s wall, 0.718750s user + 0.015625s system = 0.734375s CPU (98.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00060374
+PHY-3002 : Step(269): len = 544139, overlap = 52.375
+PHY-3002 : Step(270): len = 544223, overlap = 52.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00120748
+PHY-3002 : Step(271): len = 544438, overlap = 52.1562
+PHY-3002 : Step(272): len = 545032, overlap = 52
+PHY-3001 : Final: Len = 545032, Over = 52
+PHY-3001 : End incremental placement;  4.060403s wall, 4.265625s user + 0.234375s system = 4.500000s CPU (110.8%)
+
+OPT-1001 : Total overflow 344.91 peak overflow 2.81
+OPT-1001 : End high-fanout net optimization;  6.485251s wall, 7.062500s user + 0.234375s system = 7.296875s CPU (112.5%)
+
+OPT-1001 : Current memory(MB): used = 631, reserve = 615, peak = 645.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13667/16805.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 617672, over cnt = 2349(6%), over = 7523, worst = 22
+PHY-1002 : len = 649680, over cnt = 1489(4%), over = 3772, worst = 20
+PHY-1002 : len = 677600, over cnt = 508(1%), over = 1177, worst = 20
+PHY-1002 : len = 691880, over cnt = 27(0%), over = 59, worst = 16
+PHY-1002 : len = 693272, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.299306s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (134.7%)
+
+PHY-1001 : Congestion index: top1 = 53.94, top5 = 45.74, top10 = 41.92, top15 = 39.45.
+OPT-1001 : End congestion update;  1.522465s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (129.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 16671 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.625888s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 35 cells processed and 5000 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 27 cells processed and 1250 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 19 cells processed and 1582 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 26 cells processed and 1118 slack improved
+OPT-0007 : Iter 5: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 12 cells processed and 800 slack improved
+OPT-1001 : End global optimization;  2.182685s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (120.3%)
+
+OPT-1001 : Current memory(MB): used = 610, reserve = 593, peak = 645.
+OPT-1001 : End physical optimization;  10.566985s wall, 11.484375s user + 0.328125s system = 11.812500s CPU (111.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 5775 LUT to BLE ...
+SYN-4008 : Packed 5775 LUT and 2391 SEQ to BLE.
+SYN-4003 : Packing 5478 remaining SEQ's ...
+SYN-4005 : Packed 2862 SEQ with LUT/SLICE
+SYN-4006 : 735 single LUT's are left
+SYN-4006 : 2616 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 8391/11919 primitive instances ...
+PHY-3001 : End packing;  1.183177s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 5787 instances
+RUN-1001 : 2820 mslices, 2820 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 14525 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 8343 nets have 2 pins
+RUN-1001 : 4847 nets have [3 - 5] pins
+RUN-1001 : 794 nets have [6 - 10] pins
+RUN-1001 : 247 nets have [11 - 20] pins
+RUN-1001 : 264 nets have [21 - 99] pins
+RUN-1001 : 10 nets have 100+ pins
+PHY-3001 : design contains 5785 instances, 5640 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 2972 pins
+PHY-3001 : Found 1034 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 64%
+PHY-3001 : After packing: Len = 553390, Over = 175
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 64%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 6301/14525.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 666608, over cnt = 1393(3%), over = 2207, worst = 8
+PHY-1002 : len = 671248, over cnt = 905(2%), over = 1328, worst = 7
+PHY-1002 : len = 679720, over cnt = 449(1%), over = 610, worst = 7
+PHY-1002 : len = 684752, over cnt = 155(0%), over = 201, worst = 7
+PHY-1002 : len = 687784, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations;  1.242115s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (135.9%)
+
+PHY-1001 : Congestion index: top1 = 53.38, top5 = 45.50, top10 = 41.74, top15 = 39.30.
+PHY-3001 : End congestion estimation;  1.548301s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (128.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59394, tnet num: 14391, tinst num: 5785, tnode num: 78430, tedge num: 99249.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.355287s wall, 1.343750s user + 0.015625s system = 1.359375s CPU (100.3%)
+
+RUN-1004 : used memory is 550 MB, reserved memory is 539 MB, peak memory is 645 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14391 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.023022s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.12456e-05
+PHY-3002 : Step(273): len = 542520, overlap = 168.25
+PHY-3002 : Step(274): len = 537399, overlap = 163.75
+PHY-3002 : Step(275): len = 534441, overlap = 174
+PHY-3002 : Step(276): len = 532947, overlap = 177.5
+PHY-3002 : Step(277): len = 531468, overlap = 185.5
+PHY-3002 : Step(278): len = 529829, overlap = 179.25
+PHY-3002 : Step(279): len = 527823, overlap = 179.25
+PHY-3002 : Step(280): len = 526225, overlap = 187.5
+PHY-3002 : Step(281): len = 524593, overlap = 187
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000102491
+PHY-3002 : Step(282): len = 529291, overlap = 175.25
+PHY-3002 : Step(283): len = 533277, overlap = 171.75
+PHY-3002 : Step(284): len = 533095, overlap = 172.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000204983
+PHY-3002 : Step(285): len = 543592, overlap = 158
+PHY-3002 : Step(286): len = 550473, overlap = 148.75
+PHY-3002 : Step(287): len = 548456, overlap = 149.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.392854s wall, 0.375000s user + 0.718750s system = 1.093750s CPU (278.4%)
+
+PHY-3001 : Trial Legalized: Len = 618423
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 580/14525.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 706080, over cnt = 1781(5%), over = 2947, worst = 8
+PHY-1002 : len = 716592, over cnt = 993(2%), over = 1464, worst = 7
+PHY-1002 : len = 728064, over cnt = 343(0%), over = 480, worst = 5
+PHY-1002 : len = 731776, over cnt = 146(0%), over = 207, worst = 5
+PHY-1002 : len = 734408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.744924s wall, 2.546875s user + 0.062500s system = 2.609375s CPU (149.5%)
+
+PHY-1001 : Congestion index: top1 = 53.62, top5 = 46.54, top10 = 43.08, top15 = 40.78.
+PHY-3001 : End congestion estimation;  2.084513s wall, 2.890625s user + 0.062500s system = 2.953125s CPU (141.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14391 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.891915s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000146819
+PHY-3002 : Step(288): len = 597185, overlap = 29.25
+PHY-3002 : Step(289): len = 584684, overlap = 48
+PHY-3002 : Step(290): len = 573519, overlap = 72.5
+PHY-3002 : Step(291): len = 567340, overlap = 79.75
+PHY-3002 : Step(292): len = 561725, overlap = 101
+PHY-3002 : Step(293): len = 559175, overlap = 109.5
+PHY-3002 : Step(294): len = 557122, overlap = 116
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000293638
+PHY-3002 : Step(295): len = 562084, overlap = 111.5
+PHY-3002 : Step(296): len = 566015, overlap = 109
+PHY-3002 : Step(297): len = 568778, overlap = 112.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000569369
+PHY-3002 : Step(298): len = 573205, overlap = 109.5
+PHY-3002 : Step(299): len = 582694, overlap = 98.25
+PHY-3002 : Step(300): len = 587717, overlap = 94
+PHY-3002 : Step(301): len = 589660, overlap = 95.75
+PHY-3002 : Step(302): len = 590892, overlap = 97.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.044289s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (70.6%)
+
+PHY-3001 : Legalized: Len = 612770, Over = 0
+PHY-3001 : Spreading special nets. 324 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.072800s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (107.3%)
+
+PHY-3001 : 441 instances has been re-located, deltaX = 125, deltaY = 273, maxDist = 3.
+PHY-3001 : Final: Len = 619285, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59394, tnet num: 14391, tinst num: 5788, tnode num: 78430, tedge num: 99249.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.537640s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.6%)
+
+RUN-1004 : used memory is 555 MB, reserved memory is 552 MB, peak memory is 645 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 2315/14525.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 716824, over cnt = 1670(4%), over = 2684, worst = 8
+PHY-1002 : len = 724664, over cnt = 1013(2%), over = 1512, worst = 8
+PHY-1002 : len = 736704, over cnt = 295(0%), over = 454, worst = 6
+PHY-1002 : len = 741280, over cnt = 88(0%), over = 130, worst = 4
+PHY-1002 : len = 743032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.532026s wall, 2.265625s user + 0.015625s system = 2.281250s CPU (148.9%)
+
+PHY-1001 : Congestion index: top1 = 51.47, top5 = 45.49, top10 = 42.16, top15 = 39.92.
+PHY-1001 : End incremental global routing;  1.822822s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (141.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14391 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.674226s wall, 0.640625s user + 0.031250s system = 0.671875s CPU (99.7%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5696 has valid locations, 19 needs to be replaced
+PHY-3001 : design contains 5803 instances, 5655 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3032 pins
+PHY-3001 : Found 1036 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 621249
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 64%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13136/14541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 745088, over cnt = 67(0%), over = 73, worst = 3
+PHY-1002 : len = 745072, over cnt = 15(0%), over = 16, worst = 2
+PHY-1002 : len = 745224, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 745288, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 745296, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.603138s wall, 0.593750s user + 0.015625s system = 0.609375s CPU (101.0%)
+
+PHY-1001 : Congestion index: top1 = 51.59, top5 = 45.61, top10 = 42.24, top15 = 40.01.
+PHY-3001 : End congestion estimation;  0.851604s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59506, tnet num: 14407, tinst num: 5803, tnode num: 78577, tedge num: 99396.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.566977s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (99.7%)
+
+RUN-1004 : used memory is 585 MB, reserved memory is 575 MB, peak memory is 645 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.286690s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(303): len = 620870, overlap = 0
+PHY-3002 : Step(304): len = 620818, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 64%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 13137/14541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744728, over cnt = 32(0%), over = 35, worst = 2
+PHY-1002 : len = 744768, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 744864, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 744912, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.490643s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (105.1%)
+
+PHY-1001 : Congestion index: top1 = 51.68, top5 = 45.55, top10 = 42.21, top15 = 39.94.
+PHY-3001 : End congestion estimation;  0.752456s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (103.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.675848s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000217074
+PHY-3002 : Step(305): len = 620774, overlap = 0.25
+PHY-3002 : Step(306): len = 620726, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005850s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 620678, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.048030s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (97.6%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 3, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 620920, Over = 0
+PHY-3001 : End incremental placement;  4.970082s wall, 5.015625s user + 0.078125s system = 5.093750s CPU (102.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  7.836893s wall, 8.671875s user + 0.125000s system = 8.796875s CPU (112.2%)
+
+OPT-1001 : Current memory(MB): used = 651, reserve = 641, peak = 655.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13085/14541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 744960, over cnt = 49(0%), over = 59, worst = 5
+PHY-1002 : len = 745080, over cnt = 21(0%), over = 24, worst = 3
+PHY-1002 : len = 745304, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 745352, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.500824s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (109.2%)
+
+PHY-1001 : Congestion index: top1 = 51.64, top5 = 45.61, top10 = 42.26, top15 = 39.99.
+OPT-1001 : End congestion update;  0.758536s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (105.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.564233s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (99.7%)
+
+OPT-0007 : Start: WNS -990 TNS -1704 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5803 instances, 5655 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3032 pins
+PHY-3001 : Found 1036 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 64%
+PHY-3001 : Initial: Len = 624956, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.048304s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (97.0%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 2, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 625086, Over = 0
+PHY-3001 : End incremental legalization;  0.306048s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.1%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1521 NUM_FEPS 2 with 28 cells processed and 9050 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1521 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.741093s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (102.3%)
+
+OPT-1001 : Current memory(MB): used = 651, reserve = 641, peak = 655.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.576687s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13031/14541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749176, over cnt = 64(0%), over = 83, worst = 6
+PHY-1002 : len = 749280, over cnt = 37(0%), over = 38, worst = 2
+PHY-1002 : len = 749592, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 749608, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 749688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.613268s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (101.9%)
+
+PHY-1001 : Congestion index: top1 = 51.85, top5 = 45.74, top10 = 42.37, top15 = 40.11.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.564200s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (99.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -936 TNS -1521 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 51.413793
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -936ps with logic level 2 
+RUN-1001 :       #2 path slack -840ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 14541 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 14541 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5803 instances, 5655 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3032 pins
+PHY-3001 : Found 1036 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 64%
+PHY-3001 : Initial: Len = 625086, Over = 0
+PHY-3001 : End spreading;  0.047905s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (97.9%)
+
+PHY-3001 : Final: Len = 625086, Over = 0
+PHY-3001 : End incremental legalization;  0.322487s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (111.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.578231s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (100.0%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13152/14541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.100604s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (93.2%)
+
+PHY-1001 : Congestion index: top1 = 51.85, top5 = 45.74, top10 = 42.37, top15 = 40.11.
+OPT-1001 : End congestion update;  0.355489s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (101.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.557172s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (101.0%)
+
+OPT-0007 : Start: WNS -936 TNS -1521 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5715 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5803 instances, 5655 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3032 pins
+PHY-3001 : Found 1036 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 64%
+PHY-3001 : Initial: Len = 625130, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.045540s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (102.9%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 625086, Over = 0
+PHY-3001 : End incremental legalization;  0.295927s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (137.3%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1521 NUM_FEPS 2 with 2 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1521 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.297785s wall, 1.500000s user + 0.000000s system = 1.500000s CPU (115.6%)
+
+OPT-1001 : Current memory(MB): used = 651, reserve = 641, peak = 655.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13152/14541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.103192s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (90.9%)
+
+PHY-1001 : Congestion index: top1 = 51.85, top5 = 45.74, top10 = 42.37, top15 = 40.11.
+OPT-1001 : End congestion update;  0.351078s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (102.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.556993s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (98.2%)
+
+OPT-0007 : Start: WNS -936 TNS -1521 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -936 TNS -1521 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1521 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.027837s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (100.3%)
+
+OPT-1001 : Current memory(MB): used = 651, reserve = 641, peak = 655.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.555897s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (101.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 651, reserve = 641, peak = 655.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.574349s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (97.9%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13152/14541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 749688, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.110708s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (98.8%)
+
+PHY-1001 : Congestion index: top1 = 51.85, top5 = 45.74, top10 = 42.37, top15 = 40.11.
+RUN-1001 : End congestion update;  0.391466s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (95.8%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  0.968832s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (98.4%)
+
+OPT-1001 : Current memory(MB): used = 651, reserve = 641, peak = 655.
+OPT-1001 : End physical optimization;  18.285197s wall, 19.406250s user + 0.140625s system = 19.546875s CPU (106.9%)
+
+RUN-1003 : finish command "place" in  51.390231s wall, 71.562500s user + 5.796875s system = 77.359375s CPU (150.5%)
+
+RUN-1004 : used memory is 570 MB, reserved memory is 567 MB, peak memory is 655 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.493614s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (171.6%)
+
+RUN-1004 : used memory is 570 MB, reserved memory is 568 MB, peak memory is 655 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 5805 instances
+RUN-1001 : 2830 mslices, 2825 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 14541 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 8342 nets have 2 pins
+RUN-1001 : 4847 nets have [3 - 5] pins
+RUN-1001 : 802 nets have [6 - 10] pins
+RUN-1001 : 251 nets have [11 - 20] pins
+RUN-1001 : 271 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59506, tnet num: 14407, tinst num: 5803, tnode num: 78577, tedge num: 99396.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.365051s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.6%)
+
+RUN-1004 : used memory is 560 MB, reserved memory is 544 MB, peak memory is 655 MB
+PHY-1001 : 2830 mslices, 2825 lslices, 75 pads, 58 brams, 2 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 710032, over cnt = 1832(5%), over = 2946, worst = 7
+PHY-1002 : len = 720112, over cnt = 1092(3%), over = 1590, worst = 7
+PHY-1002 : len = 732240, over cnt = 386(1%), over = 552, worst = 7
+PHY-1002 : len = 739120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.007481s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (133.1%)
+
+PHY-1001 : Congestion index: top1 = 52.56, top5 = 46.07, top10 = 42.36, top15 = 40.05.
+PHY-1001 : End global routing;  2.265334s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (129.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 629, reserve = 622, peak = 655.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 904, reserve = 896, peak = 904.
+PHY-1001 : End build detailed router design. 3.868926s wall, 3.875000s user + 0.000000s system = 3.875000s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 237296, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.715575s wall, 4.687500s user + 0.015625s system = 4.703125s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 237352, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.374468s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 940, reserve = 933, peak = 940.
+PHY-1001 : End phase 1; 5.102259s wall, 5.078125s user + 0.015625s system = 5.093750s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 42% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 1.97917e+06, over cnt = 815(0%), over = 815, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 952, reserve = 944, peak = 952.
+PHY-1001 : End initial routed; 20.189646s wall, 41.375000s user + 0.453125s system = 41.828125s CPU (207.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/13649(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.735   |  -3.619   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 2.661122s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 960, reserve = 952, peak = 960.
+PHY-1001 : End phase 2; 22.850833s wall, 44.015625s user + 0.468750s system = 44.484375s CPU (194.7%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.735ns STNS -3.619ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.106356s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (88.1%)
+
+PHY-1022 : len = 1.97917e+06, over cnt = 815(0%), over = 815, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.313041s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 1.96382e+06, over cnt = 216(0%), over = 216, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.945452s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (157.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 1.96295e+06, over cnt = 31(0%), over = 31, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.443827s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (119.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 1.96273e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.175395s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (124.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 1.96282e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 4; 0.158374s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (108.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/13649(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.735   |  -3.619   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 2.658689s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 248 feed throughs used by 191 nets
+PHY-1001 : End commit to database; 1.778038s wall, 1.734375s user + 0.046875s system = 1.781250s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1039, peak = 1044.
+PHY-1001 : End phase 3; 6.821112s wall, 7.437500s user + 0.062500s system = 7.500000s CPU (110.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.634ns STNS -3.518ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.112287s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (97.4%)
+
+PHY-1022 : len = 1.9628e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.293356s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (101.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.634ns, -3.518ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/13649(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.634   |  -3.518   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 2.671936s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 249 feed throughs used by 192 nets
+PHY-1001 : End commit to database; 1.869065s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1047, peak = 1052.
+PHY-1001 : End phase 4; 4.854583s wall, 4.843750s user + 0.000000s system = 4.843750s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 1.9628e+06
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1048, peak = 1053.
+PHY-1001 : End export database. 0.053950s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (86.9%)
+
+PHY-1001 : End detail routing;  43.915126s wall, 65.656250s user + 0.546875s system = 66.203125s CPU (150.8%)
+
+RUN-1003 : finish command "route" in  48.405932s wall, 70.781250s user + 0.578125s system = 71.359375s CPU (147.4%)
+
+RUN-1004 : used memory is 991 MB, reserved memory is 982 MB, peak memory is 1053 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                     7957   out of  19600   40.60%
+#reg                     8012   out of  19600   40.88%
+#le                     10513
+  #lut only              2501   out of  10513   23.79%
+  #reg only              2556   out of  10513   24.31%
+  #lut&reg               5456   out of  10513   51.90%
+#dsp                        2   out of     29    6.90%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                   Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                     1810
+#2        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0               1330
+#3        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                     984
+#4        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                527
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/reg6_syn_49.q0    139
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1               71
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                50
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                     25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                     4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_219.f1           3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg11_syn_142.f1               3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                    1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                    1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                    1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                     1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+       paper_in            INPUT        P146       LVCMOS33          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P148       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P118       LVCMOS25           8            N/A        NONE    
+    frame_indicator       OUTPUT        P39        LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P35        LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT         P6        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |10513  |7118    |839     |8042    |58      |2       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |533    |399     |23      |441     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |102    |93      |4       |89      |4       |0       |
+|    U_ecc_gen                 |ecc_gen              |11     |11      |0       |9       |0       |0       |
+|    U_crc16_24b               |crc16_24b            |25     |25      |0       |17      |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |769    |310     |96      |580     |0       |0       |
+|    u_ADconfig                |AD_config            |190    |111     |25      |141     |0       |0       |
+|    u_gen_sp                  |gen_sp               |259    |146     |71      |119     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |408     |96      |555     |0       |0       |
+|    u_ADconfig                |AD_config            |173    |116     |25      |127     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |159     |71      |116     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |942    |741     |97      |664     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |117    |87      |17      |76      |0       |0       |
+|      u0_soft_n               |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_sort                    |sort                 |799    |640     |80      |562     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |7      |1       |0       |7       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |7      |1       |0       |7       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |303    |256     |44      |213     |22      |0       |
+|        read_ram_i            |read_ram             |279    |235     |44      |191     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |228    |188     |40      |150     |0       |0       |
+|          read_ram_data       |read_ram_data        |49     |45      |4       |39      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |357    |254     |36      |281     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3459   |2753    |373     |2150    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |182    |145     |17      |141     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |3243   |2575    |356     |1976    |25      |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2650   |2087    |314     |1542    |22      |0       |
+|        channelPart           |channel_part_8478    |139    |136     |3       |113     |0       |0       |
+|        fifo_adc              |fifo_adc             |53     |44      |9       |38      |0       |0       |
+|        ram_switch            |ram_switch           |2063   |1620    |218     |1168    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |269    |217     |48      |117     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |16     |9       |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |27     |21      |6       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |30     |24      |6       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |32     |26      |6       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |28     |22      |6       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |30     |24      |6       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |26     |20      |6       |7       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |30     |24      |6       |9       |0       |0       |
+|          insert              |insert               |984    |594     |170     |688     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |810    |809     |0       |363     |0       |0       |
+|        read_ram_i            |read_ram_rev         |359    |251     |84      |198     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |297    |209     |76      |155     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |62     |42      |8       |43      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1      |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |2      |2       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |323    |227     |42      |277     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       8280  
+    #2         2       3235  
+    #3         3       1097  
+    #4         4       512   
+    #5        5-10     832   
+    #6       11-50     475   
+    #7       51-100     14   
+    #8        >500      1    
+  Average     2.79           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  1.837440s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (169.2%)
+
+RUN-1004 : used memory is 993 MB, reserved memory is 984 MB, peak memory is 1053 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59506, tnet num: 14407, tinst num: 5803, tnode num: 78577, tedge num: 99396.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.360368s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.9%)
+
+RUN-1004 : used memory is 997 MB, reserved memory is 988 MB, peak memory is 1053 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 14407 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.213788s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (99.1%)
+
+RUN-1004 : used memory is 1001 MB, reserved memory is 993 MB, peak memory is 1053 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 5803
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 14541, pip num: 140162
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 249
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3246 valid insts, and 383029 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  8.336907s wall, 55.687500s user + 0.218750s system = 55.906250s CPU (670.6%)
+
+RUN-1004 : used memory is 1135 MB, reserved memory is 1126 MB, peak memory is 1250 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_164841.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_165913.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_165913.log
new file mode 100644
index 0000000..389121a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_165913.log
@@ -0,0 +1,1809 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:59:14 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  1.860861s wall, 1.796875s user + 0.062500s system = 1.859375s CPU (99.9%)
+
+RUN-1004 : used memory is 294 MB, reserved memory is 263 MB, peak memory is 298 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2925 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (890 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (724 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 11021 instances
+RUN-0007 : 3921 luts, 6275 seqs, 440 mslices, 238 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 12714 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 8259 nets have 2 pins
+RUN-1001 : 3833 nets have [3 - 5] pins
+RUN-1001 : 313 nets have [6 - 10] pins
+RUN-1001 : 120 nets have [11 - 20] pins
+RUN-1001 : 142 nets have [21 - 99] pins
+RUN-1001 : 27 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     521     
+RUN-1001 :   No   |  No   |  Yes  |    1957     
+RUN-1001 :   No   |  Yes  |  No   |    2092     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     62      
+RUN-1001 :   Yes  |  Yes  |  No   |    1579     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  58   |     46     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 117
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 11019 instances, 3921 luts, 6275 seqs, 678 slices, 120 macros(678 instances: 440 mslices 238 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 4086 pins
+PHY-0007 : Cell area utilization is 32%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 51633, tnet num: 12624, tinst num: 11019, tnode num: 72503, tedge num: 82120.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 12624 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.502438s wall, 1.453125s user + 0.046875s system = 1.500000s CPU (99.8%)
+
+PHY-3001 : Found 1211 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 2.54771e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 11019.
+PHY-3001 : Level 1 #clusters 1606.
+PHY-3001 : End clustering;  0.079321s wall, 0.062500s user + 0.015625s system = 0.078125s CPU (98.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 32%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 890871, overlap = 209.844
+PHY-3002 : Step(2): len = 833642, overlap = 219.25
+PHY-3002 : Step(3): len = 518839, overlap = 293.344
+PHY-3002 : Step(4): len = 455464, overlap = 319.125
+PHY-3002 : Step(5): len = 344147, overlap = 375.562
+PHY-3002 : Step(6): len = 321825, overlap = 404.844
+PHY-3002 : Step(7): len = 266571, overlap = 456.75
+PHY-3002 : Step(8): len = 227980, overlap = 504.781
+PHY-3002 : Step(9): len = 207172, overlap = 537.656
+PHY-3002 : Step(10): len = 179367, overlap = 574.156
+PHY-3002 : Step(11): len = 166704, overlap = 602.688
+PHY-3002 : Step(12): len = 150285, overlap = 617.719
+PHY-3002 : Step(13): len = 142896, overlap = 632.344
+PHY-3002 : Step(14): len = 129885, overlap = 659.688
+PHY-3002 : Step(15): len = 125731, overlap = 684.281
+PHY-3002 : Step(16): len = 115860, overlap = 722.938
+PHY-3002 : Step(17): len = 112518, overlap = 761.062
+PHY-3002 : Step(18): len = 105362, overlap = 800.031
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.13347e-06
+PHY-3002 : Step(19): len = 105802, overlap = 771.688
+PHY-3002 : Step(20): len = 122330, overlap = 739.406
+PHY-3002 : Step(21): len = 124734, overlap = 696.094
+PHY-3002 : Step(22): len = 129082, overlap = 665.75
+PHY-3002 : Step(23): len = 125748, overlap = 652.156
+PHY-3002 : Step(24): len = 126170, overlap = 639.719
+PHY-3002 : Step(25): len = 123699, overlap = 640.094
+PHY-3002 : Step(26): len = 123426, overlap = 615.781
+PHY-3002 : Step(27): len = 121953, overlap = 597.031
+PHY-3002 : Step(28): len = 121945, overlap = 596.969
+PHY-3002 : Step(29): len = 120370, overlap = 586.938
+PHY-3002 : Step(30): len = 119992, overlap = 594.031
+PHY-3002 : Step(31): len = 118284, overlap = 591.125
+PHY-3002 : Step(32): len = 118561, overlap = 593.688
+PHY-3002 : Step(33): len = 117992, overlap = 593.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.26695e-06
+PHY-3002 : Step(34): len = 121176, overlap = 577.812
+PHY-3002 : Step(35): len = 133053, overlap = 506.281
+PHY-3002 : Step(36): len = 137437, overlap = 494.625
+PHY-3002 : Step(37): len = 140746, overlap = 501.156
+PHY-3002 : Step(38): len = 142462, overlap = 485.875
+PHY-3002 : Step(39): len = 142202, overlap = 486.969
+PHY-3002 : Step(40): len = 142129, overlap = 474.812
+PHY-3002 : Step(41): len = 141099, overlap = 456.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.5339e-06
+PHY-3002 : Step(42): len = 149408, overlap = 433.906
+PHY-3002 : Step(43): len = 161912, overlap = 408.25
+PHY-3002 : Step(44): len = 165186, overlap = 385.531
+PHY-3002 : Step(45): len = 166675, overlap = 367.625
+PHY-3002 : Step(46): len = 166080, overlap = 350.75
+PHY-3002 : Step(47): len = 165516, overlap = 348.75
+PHY-3002 : Step(48): len = 163797, overlap = 345.125
+PHY-3002 : Step(49): len = 163417, overlap = 355.094
+PHY-3002 : Step(50): len = 163370, overlap = 339.344
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.06779e-06
+PHY-3002 : Step(51): len = 173298, overlap = 324.375
+PHY-3002 : Step(52): len = 183813, overlap = 298.531
+PHY-3002 : Step(53): len = 185766, overlap = 301.719
+PHY-3002 : Step(54): len = 187994, overlap = 295.344
+PHY-3002 : Step(55): len = 188963, overlap = 276.656
+PHY-3002 : Step(56): len = 188840, overlap = 279.406
+PHY-3002 : Step(57): len = 186776, overlap = 272.438
+PHY-3002 : Step(58): len = 186460, overlap = 270.469
+PHY-3002 : Step(59): len = 186496, overlap = 272.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.81356e-05
+PHY-3002 : Step(60): len = 197276, overlap = 245.406
+PHY-3002 : Step(61): len = 208933, overlap = 230.688
+PHY-3002 : Step(62): len = 211165, overlap = 220.5
+PHY-3002 : Step(63): len = 212325, overlap = 216.594
+PHY-3002 : Step(64): len = 212089, overlap = 223.719
+PHY-3002 : Step(65): len = 212039, overlap = 228.906
+PHY-3002 : Step(66): len = 210435, overlap = 235.156
+PHY-3002 : Step(67): len = 210132, overlap = 232.625
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.62712e-05
+PHY-3002 : Step(68): len = 223697, overlap = 203.688
+PHY-3002 : Step(69): len = 237857, overlap = 180
+PHY-3002 : Step(70): len = 240596, overlap = 183.406
+PHY-3002 : Step(71): len = 241207, overlap = 201.75
+PHY-3002 : Step(72): len = 239719, overlap = 198.312
+PHY-3002 : Step(73): len = 238887, overlap = 208.531
+PHY-3002 : Step(74): len = 237563, overlap = 208.125
+PHY-3002 : Step(75): len = 237592, overlap = 204.188
+PHY-3002 : Step(76): len = 236410, overlap = 208.344
+PHY-3002 : Step(77): len = 237322, overlap = 212.938
+PHY-3002 : Step(78): len = 237214, overlap = 210.938
+PHY-3002 : Step(79): len = 238064, overlap = 211.406
+PHY-3002 : Step(80): len = 237717, overlap = 209.281
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.25423e-05
+PHY-3002 : Step(81): len = 248715, overlap = 192.375
+PHY-3002 : Step(82): len = 263137, overlap = 184.844
+PHY-3002 : Step(83): len = 270828, overlap = 171.625
+PHY-3002 : Step(84): len = 278721, overlap = 159.062
+PHY-3002 : Step(85): len = 281335, overlap = 151.219
+PHY-3002 : Step(86): len = 279354, overlap = 153
+PHY-3002 : Step(87): len = 277343, overlap = 162.344
+PHY-3002 : Step(88): len = 274365, overlap = 168.219
+PHY-3002 : Step(89): len = 273727, overlap = 160.312
+PHY-3002 : Step(90): len = 273160, overlap = 163.344
+PHY-3002 : Step(91): len = 274336, overlap = 157.969
+PHY-3002 : Step(92): len = 277157, overlap = 156.75
+PHY-3002 : Step(93): len = 279524, overlap = 156.344
+PHY-3002 : Step(94): len = 278614, overlap = 155.188
+PHY-3002 : Step(95): len = 279536, overlap = 156.531
+PHY-3002 : Step(96): len = 279192, overlap = 153.125
+PHY-3002 : Step(97): len = 279218, overlap = 140.531
+PHY-3002 : Step(98): len = 277636, overlap = 148.781
+PHY-3002 : Step(99): len = 277660, overlap = 144.094
+PHY-3002 : Step(100): len = 277193, overlap = 142.312
+PHY-3002 : Step(101): len = 277288, overlap = 144.938
+PHY-3002 : Step(102): len = 275790, overlap = 147.906
+PHY-3002 : Step(103): len = 275130, overlap = 150.125
+PHY-3002 : Step(104): len = 274810, overlap = 152.781
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000144325
+PHY-3002 : Step(105): len = 285776, overlap = 153.281
+PHY-3002 : Step(106): len = 294556, overlap = 135.625
+PHY-3002 : Step(107): len = 296983, overlap = 128.375
+PHY-3002 : Step(108): len = 298651, overlap = 123.438
+PHY-3002 : Step(109): len = 298499, overlap = 124.156
+PHY-3002 : Step(110): len = 298692, overlap = 122.188
+PHY-3002 : Step(111): len = 296583, overlap = 121.469
+PHY-3002 : Step(112): len = 296219, overlap = 121.156
+PHY-3002 : Step(113): len = 296595, overlap = 117.562
+PHY-3002 : Step(114): len = 296958, overlap = 117.938
+PHY-3002 : Step(115): len = 296283, overlap = 120.594
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000273425
+PHY-3002 : Step(116): len = 303653, overlap = 114.375
+PHY-3002 : Step(117): len = 310077, overlap = 114.375
+PHY-3002 : Step(118): len = 311467, overlap = 112.062
+PHY-3002 : Step(119): len = 312260, overlap = 110.75
+PHY-3002 : Step(120): len = 312890, overlap = 108.781
+PHY-3002 : Step(121): len = 313901, overlap = 110.469
+PHY-3002 : Step(122): len = 313653, overlap = 118.188
+PHY-3002 : Step(123): len = 314702, overlap = 117.875
+PHY-3002 : Step(124): len = 315075, overlap = 123.312
+PHY-3002 : Step(125): len = 315110, overlap = 123.344
+PHY-3002 : Step(126): len = 314461, overlap = 121.656
+PHY-3002 : Step(127): len = 314650, overlap = 118.625
+PHY-3002 : Step(128): len = 315597, overlap = 119.844
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000540959
+PHY-3002 : Step(129): len = 319254, overlap = 119.125
+PHY-3002 : Step(130): len = 325024, overlap = 113.688
+PHY-3002 : Step(131): len = 327941, overlap = 114.062
+PHY-3002 : Step(132): len = 329532, overlap = 107.969
+PHY-3002 : Step(133): len = 331502, overlap = 103.25
+PHY-3002 : Step(134): len = 334014, overlap = 105.438
+PHY-3002 : Step(135): len = 336634, overlap = 107.25
+PHY-3002 : Step(136): len = 336543, overlap = 103.375
+PHY-3002 : Step(137): len = 337541, overlap = 103
+PHY-3002 : Step(138): len = 336508, overlap = 103
+PHY-3002 : Step(139): len = 336545, overlap = 102.531
+PHY-3002 : Step(140): len = 335610, overlap = 101.844
+PHY-3002 : Step(141): len = 335128, overlap = 101.344
+PHY-3002 : Step(142): len = 333212, overlap = 101.406
+PHY-3002 : Step(143): len = 332492, overlap = 102.469
+PHY-3002 : Step(144): len = 331845, overlap = 102.656
+PHY-3002 : Step(145): len = 331735, overlap = 102.656
+PHY-3002 : Step(146): len = 331234, overlap = 101.844
+PHY-3002 : Step(147): len = 331109, overlap = 101.844
+PHY-3002 : Step(148): len = 330755, overlap = 97.3438
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000971129
+PHY-3002 : Step(149): len = 332847, overlap = 97.2812
+PHY-3002 : Step(150): len = 336824, overlap = 96.25
+PHY-3002 : Step(151): len = 339326, overlap = 95
+PHY-3002 : Step(152): len = 340694, overlap = 96.8125
+PHY-3002 : Step(153): len = 344007, overlap = 94.4375
+PHY-3002 : Step(154): len = 344956, overlap = 92.9375
+PHY-3002 : Step(155): len = 344414, overlap = 97.5
+PHY-3002 : Step(156): len = 342778, overlap = 84.9062
+PHY-3002 : Step(157): len = 341026, overlap = 89.5
+PHY-3002 : Step(158): len = 339718, overlap = 91.625
+PHY-3002 : Step(159): len = 338882, overlap = 91.0625
+PHY-3002 : Step(160): len = 338361, overlap = 91.1875
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0017057
+PHY-3002 : Step(161): len = 339958, overlap = 88.9375
+PHY-3002 : Step(162): len = 341928, overlap = 88.8438
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00291453
+PHY-3002 : Step(163): len = 342690, overlap = 87.5938
+PHY-3002 : Step(164): len = 344399, overlap = 87.5938
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.009717s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (321.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 39%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/12714.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 466136, over cnt = 863(2%), over = 3425, worst = 37
+PHY-1001 : End global iterations;  0.440314s wall, 0.562500s user + 0.031250s system = 0.593750s CPU (134.8%)
+
+PHY-1001 : Congestion index: top1 = 61.72, top5 = 44.42, top10 = 37.08, top15 = 32.69.
+PHY-3001 : End congestion estimation;  0.603671s wall, 0.703125s user + 0.062500s system = 0.765625s CPU (126.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 12624 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.552235s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000285297
+PHY-3002 : Step(165): len = 429531, overlap = 16.2812
+PHY-3002 : Step(166): len = 434668, overlap = 10.6562
+PHY-3002 : Step(167): len = 431045, overlap = 7.65625
+PHY-3002 : Step(168): len = 428044, overlap = 4.40625
+PHY-3002 : Step(169): len = 427659, overlap = 2.96875
+PHY-3002 : Step(170): len = 428750, overlap = 2.46875
+PHY-3002 : Step(171): len = 428896, overlap = 1.5
+PHY-3002 : Step(172): len = 429039, overlap = 1.1875
+PHY-3002 : Step(173): len = 427808, overlap = 0.6875
+PHY-3002 : Step(174): len = 426965, overlap = 0.90625
+PHY-3002 : Step(175): len = 424989, overlap = 0.78125
+PHY-3002 : Step(176): len = 423596, overlap = 1.1875
+PHY-3002 : Step(177): len = 422138, overlap = 1.375
+PHY-3002 : Step(178): len = 420845, overlap = 1.40625
+PHY-3002 : Step(179): len = 419461, overlap = 1.78125
+PHY-3002 : Step(180): len = 418495, overlap = 2.21875
+PHY-3002 : Step(181): len = 417244, overlap = 1.53125
+PHY-3002 : Step(182): len = 416532, overlap = 1.40625
+PHY-3002 : Step(183): len = 415797, overlap = 1.65625
+PHY-3002 : Step(184): len = 415340, overlap = 1.71875
+PHY-3002 : Step(185): len = 415099, overlap = 1.65625
+PHY-3002 : Step(186): len = 414877, overlap = 2.21875
+PHY-3002 : Step(187): len = 414695, overlap = 3.1875
+PHY-3002 : Step(188): len = 413553, overlap = 2.65625
+PHY-3002 : Step(189): len = 412453, overlap = 2.65625
+PHY-3002 : Step(190): len = 411022, overlap = 2.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000570594
+PHY-3002 : Step(191): len = 413134, overlap = 1.46875
+PHY-3002 : Step(192): len = 414970, overlap = 1.375
+PHY-3002 : Step(193): len = 417060, overlap = 1.21875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 39%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 93/12714.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 472976, over cnt = 1468(4%), over = 5234, worst = 31
+PHY-1001 : End global iterations;  1.292008s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (128.2%)
+
+PHY-1001 : Congestion index: top1 = 61.31, top5 = 48.27, top10 = 41.56, top15 = 37.37.
+PHY-3001 : End congestion estimation;  1.475218s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (125.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 12624 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.705966s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000175152
+PHY-3002 : Step(194): len = 419865, overlap = 61.5312
+PHY-3002 : Step(195): len = 425154, overlap = 42.7188
+PHY-3002 : Step(196): len = 418760, overlap = 37.5938
+PHY-3002 : Step(197): len = 415355, overlap = 35.9062
+PHY-3002 : Step(198): len = 414706, overlap = 33.8125
+PHY-3002 : Step(199): len = 413395, overlap = 36.0625
+PHY-3002 : Step(200): len = 411754, overlap = 33.8438
+PHY-3002 : Step(201): len = 410058, overlap = 34.4062
+PHY-3002 : Step(202): len = 408314, overlap = 31
+PHY-3002 : Step(203): len = 406228, overlap = 33.8125
+PHY-3002 : Step(204): len = 404322, overlap = 34.6562
+PHY-3002 : Step(205): len = 401314, overlap = 35.7188
+PHY-3002 : Step(206): len = 399241, overlap = 38
+PHY-3002 : Step(207): len = 397391, overlap = 34.1875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000350303
+PHY-3002 : Step(208): len = 399355, overlap = 29.2188
+PHY-3002 : Step(209): len = 401087, overlap = 26.5938
+PHY-3002 : Step(210): len = 401607, overlap = 22.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000700607
+PHY-3002 : Step(211): len = 407926, overlap = 18.5312
+PHY-3002 : Step(212): len = 414376, overlap = 15.0625
+PHY-3002 : Step(213): len = 415831, overlap = 14.375
+PHY-3002 : Step(214): len = 416152, overlap = 15.2812
+PHY-3002 : Step(215): len = 415823, overlap = 14.2188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 51633, tnet num: 12624, tinst num: 11019, tnode num: 72503, tedge num: 82120.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.099557s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (100.9%)
+
+RUN-1004 : used memory is 454 MB, reserved memory is 431 MB, peak memory is 535 MB
+OPT-1001 : Total overflow 179.25 peak overflow 2.69
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 462/12714.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 483376, over cnt = 1474(4%), over = 4174, worst = 21
+PHY-1001 : End global iterations;  1.038081s wall, 1.375000s user + 0.000000s system = 1.375000s CPU (132.5%)
+
+PHY-1001 : Congestion index: top1 = 49.29, top5 = 41.41, top10 = 36.99, top15 = 34.22.
+PHY-1001 : End incremental global routing;  1.309410s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (125.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 12624 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.591567s wall, 0.546875s user + 0.046875s system = 0.593750s CPU (100.4%)
+
+OPT-1001 : 25 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 10909 has valid locations, 136 needs to be replaced
+PHY-3001 : design contains 11130 instances, 3970 luts, 6337 seqs, 678 slices, 120 macros(678 instances: 440 mslices 238 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 4139 pins
+PHY-3001 : Found 1220 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 424876
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 39%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 10589/12825.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 488528, over cnt = 1508(4%), over = 4249, worst = 21
+PHY-1001 : End global iterations;  0.139825s wall, 0.187500s user + 0.031250s system = 0.218750s CPU (156.4%)
+
+PHY-1001 : Congestion index: top1 = 50.22, top5 = 41.64, top10 = 37.18, top15 = 34.39.
+PHY-3001 : End congestion estimation;  0.323881s wall, 0.359375s user + 0.031250s system = 0.390625s CPU (120.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 52059, tnet num: 12735, tinst num: 11130, tnode num: 73095, tedge num: 82750.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.095297s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (101.3%)
+
+RUN-1004 : used memory is 488 MB, reserved memory is 472 MB, peak memory is 536 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 12735 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.711583s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(216): len = 424291, overlap = 0
+PHY-3002 : Step(217): len = 424184, overlap = 0
+PHY-3002 : Step(218): len = 424215, overlap = 0
+PHY-3002 : Step(219): len = 424348, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 39%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 10610/12825.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 488200, over cnt = 1514(4%), over = 4280, worst = 21
+PHY-1001 : End global iterations;  0.139266s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (112.2%)
+
+PHY-1001 : Congestion index: top1 = 50.37, top5 = 41.78, top10 = 37.36, top15 = 34.55.
+PHY-3001 : End congestion estimation;  0.322491s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (106.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 12735 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.615555s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000471119
+PHY-3002 : Step(220): len = 424319, overlap = 14.5
+PHY-3002 : Step(221): len = 424369, overlap = 14.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000942239
+PHY-3002 : Step(222): len = 424507, overlap = 14.5938
+PHY-3002 : Step(223): len = 424818, overlap = 14.4062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00188448
+PHY-3002 : Step(224): len = 424978, overlap = 14.4688
+PHY-3002 : Step(225): len = 425421, overlap = 14.375
+PHY-3001 : Final: Len = 425421, Over = 14.375
+PHY-3001 : End incremental placement;  3.541143s wall, 3.796875s user + 0.437500s system = 4.234375s CPU (119.6%)
+
+OPT-1001 : Total overflow 180.91 peak overflow 2.69
+OPT-1001 : End high-fanout net optimization;  5.748323s wall, 6.359375s user + 0.484375s system = 6.843750s CPU (119.1%)
+
+OPT-1001 : Current memory(MB): used = 537, reserve = 517, peak = 549.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 10603/12825.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 489256, over cnt = 1471(4%), over = 4029, worst = 21
+PHY-1002 : len = 503864, over cnt = 876(2%), over = 2096, worst = 13
+PHY-1002 : len = 515744, over cnt = 427(1%), over = 930, worst = 12
+PHY-1002 : len = 524776, over cnt = 66(0%), over = 121, worst = 7
+PHY-1002 : len = 525936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.773443s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (139.4%)
+
+PHY-1001 : Congestion index: top1 = 46.68, top5 = 39.32, top10 = 35.62, top15 = 33.24.
+OPT-1001 : End congestion update;  0.980062s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (130.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 12735 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.511566s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (100.8%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 32 cells processed and 2550 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 6 cells processed and 500 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 5 cells processed and 350 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 5 cells processed and 350 slack improved
+OPT-0007 : Iter 5: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 6 cells processed and 0 slack improved
+OPT-1001 : End global optimization;  1.522238s wall, 1.796875s user + 0.031250s system = 1.828125s CPU (120.1%)
+
+OPT-1001 : Current memory(MB): used = 537, reserve = 517, peak = 549.
+OPT-1001 : End physical optimization;  8.908088s wall, 9.765625s user + 0.546875s system = 10.312500s CPU (115.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 3970 LUT to BLE ...
+SYN-4008 : Packed 3970 LUT and 1647 SEQ to BLE.
+SYN-4003 : Packing 4690 remaining SEQ's ...
+SYN-4005 : Packed 2273 SEQ with LUT/SLICE
+SYN-4006 : 191 single LUT's are left
+SYN-4006 : 2417 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 6387/9718 primitive instances ...
+PHY-3001 : End packing;  0.938848s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.9%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 4504 instances
+RUN-1001 : 2179 mslices, 2178 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 11274 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 6531 nets have 2 pins
+RUN-1001 : 3934 nets have [3 - 5] pins
+RUN-1001 : 405 nets have [6 - 10] pins
+RUN-1001 : 207 nets have [11 - 20] pins
+RUN-1001 : 169 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-3001 : design contains 4502 instances, 4357 slices, 120 macros(678 instances: 440 mslices 238 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 2399 pins
+PHY-3001 : Found 472 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : After packing: Len = 431111, Over = 88.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4823/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 509016, over cnt = 858(2%), over = 1345, worst = 8
+PHY-1002 : len = 512680, over cnt = 528(1%), over = 750, worst = 6
+PHY-1002 : len = 518448, over cnt = 202(0%), over = 275, worst = 5
+PHY-1002 : len = 520864, over cnt = 57(0%), over = 77, worst = 4
+PHY-1002 : len = 521808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.010090s wall, 1.359375s user + 0.015625s system = 1.375000s CPU (136.1%)
+
+PHY-1001 : Congestion index: top1 = 49.66, top5 = 40.94, top10 = 36.66, top15 = 33.97.
+PHY-3001 : End congestion estimation;  1.274700s wall, 1.625000s user + 0.015625s system = 1.640625s CPU (128.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 44226, tnet num: 11184, tinst num: 4502, tnode num: 59531, tedge num: 73334.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.224356s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.5%)
+
+RUN-1004 : used memory is 480 MB, reserved memory is 463 MB, peak memory is 549 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.779048s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.19859e-05
+PHY-3002 : Step(226): len = 422252, overlap = 86
+PHY-3002 : Step(227): len = 417743, overlap = 90
+PHY-3002 : Step(228): len = 414777, overlap = 94
+PHY-3002 : Step(229): len = 413083, overlap = 96.5
+PHY-3002 : Step(230): len = 411712, overlap = 99
+PHY-3002 : Step(231): len = 410241, overlap = 98.75
+PHY-3002 : Step(232): len = 409245, overlap = 100.5
+PHY-3002 : Step(233): len = 407800, overlap = 100
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000123972
+PHY-3002 : Step(234): len = 411220, overlap = 94.75
+PHY-3002 : Step(235): len = 414613, overlap = 88.25
+PHY-3002 : Step(236): len = 414924, overlap = 87
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000247944
+PHY-3002 : Step(237): len = 421782, overlap = 77.25
+PHY-3002 : Step(238): len = 430558, overlap = 62.5
+PHY-3002 : Step(239): len = 429623, overlap = 60.25
+PHY-3002 : Step(240): len = 428048, overlap = 58.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.532501s wall, 0.546875s user + 0.968750s system = 1.515625s CPU (284.6%)
+
+PHY-3001 : Trial Legalized: Len = 471996
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 556/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 536120, over cnt = 1067(3%), over = 1693, worst = 6
+PHY-1002 : len = 541328, over cnt = 636(1%), over = 898, worst = 5
+PHY-1002 : len = 549176, over cnt = 162(0%), over = 221, worst = 5
+PHY-1002 : len = 550904, over cnt = 60(0%), over = 82, worst = 4
+PHY-1002 : len = 551912, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.472976s wall, 2.078125s user + 0.015625s system = 2.093750s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 48.66, top5 = 41.48, top10 = 37.39, top15 = 34.72.
+PHY-3001 : End congestion estimation;  1.799672s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (135.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.553636s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000176682
+PHY-3002 : Step(241): len = 454750, overlap = 12
+PHY-3002 : Step(242): len = 445727, overlap = 16.5
+PHY-3002 : Step(243): len = 439051, overlap = 25.5
+PHY-3002 : Step(244): len = 434563, overlap = 32.5
+PHY-3002 : Step(245): len = 431514, overlap = 40
+PHY-3002 : Step(246): len = 430668, overlap = 40
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000353365
+PHY-3002 : Step(247): len = 435363, overlap = 35.5
+PHY-3002 : Step(248): len = 439567, overlap = 31.25
+PHY-3002 : Step(249): len = 443034, overlap = 34.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000706729
+PHY-3002 : Step(250): len = 445375, overlap = 32.5
+PHY-3002 : Step(251): len = 451806, overlap = 31.5
+PHY-3002 : Step(252): len = 454779, overlap = 32.25
+PHY-3002 : Step(253): len = 456419, overlap = 34.5
+PHY-3002 : Step(254): len = 458221, overlap = 34.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.025654s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (121.8%)
+
+PHY-3001 : Legalized: Len = 469713, Over = 0
+PHY-3001 : Spreading special nets. 156 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.054638s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (85.8%)
+
+PHY-3001 : 202 instances has been re-located, deltaX = 58, deltaY = 116, maxDist = 2.
+PHY-3001 : Final: Len = 472815, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 44226, tnet num: 11184, tinst num: 4505, tnode num: 59531, tedge num: 73334.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.365130s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (99.6%)
+
+RUN-1004 : used memory is 480 MB, reserved memory is 461 MB, peak memory is 549 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1730/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 544072, over cnt = 946(2%), over = 1422, worst = 6
+PHY-1002 : len = 548120, over cnt = 538(1%), over = 769, worst = 6
+PHY-1002 : len = 554904, over cnt = 111(0%), over = 149, worst = 4
+PHY-1002 : len = 556760, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 556792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.316268s wall, 1.984375s user + 0.109375s system = 2.093750s CPU (159.1%)
+
+PHY-1001 : Congestion index: top1 = 46.40, top5 = 39.96, top10 = 36.24, top15 = 33.79.
+PHY-1001 : End incremental global routing;  1.590228s wall, 2.265625s user + 0.109375s system = 2.375000s CPU (149.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.558248s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (100.8%)
+
+OPT-1001 : 0 high-fanout net processed.
+OPT-1001 : End high-fanout net optimization;  2.452722s wall, 3.125000s user + 0.109375s system = 3.234375s CPU (131.9%)
+
+OPT-1001 : Current memory(MB): used = 527, reserve = 511, peak = 549.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 10129/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 556792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.084589s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (92.4%)
+
+PHY-1001 : Congestion index: top1 = 46.40, top5 = 39.96, top10 = 36.24, top15 = 33.79.
+OPT-1001 : End congestion update;  0.304641s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.561452s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (100.2%)
+
+OPT-0007 : Start: WNS -886 TNS -1500 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 4417 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 4505 instances, 4357 slices, 120 macros(678 instances: 440 mslices 238 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 2440 pins
+PHY-3001 : Found 472 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : Initial: Len = 477686, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.038801s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (80.5%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 477902, Over = 0
+PHY-3001 : End incremental legalization;  0.255934s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (103.8%)
+
+OPT-0007 : Iter 1: improved WNS -886 TNS -1421 NUM_FEPS 2 with 28 cells processed and 11100 slack improved
+OPT-0007 : Iter 2: improved WNS -886 TNS -1421 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.210361s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (105.9%)
+
+OPT-1001 : Current memory(MB): used = 545, reserve = 529, peak = 549.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.447577s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 9998/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 561544, over cnt = 34(0%), over = 43, worst = 3
+PHY-1002 : len = 561656, over cnt = 16(0%), over = 19, worst = 2
+PHY-1002 : len = 561808, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 561824, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 561872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.508679s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.4%)
+
+PHY-1001 : Congestion index: top1 = 46.40, top5 = 39.87, top10 = 36.20, top15 = 33.85.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.454666s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (99.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -886 TNS -1421 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 46.034483
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -886ps with logic level 2 
+RUN-1001 :       #2 path slack -840ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 11274 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 11274 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 4417 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 4505 instances, 4357 slices, 120 macros(678 instances: 440 mslices 238 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 2440 pins
+PHY-3001 : Found 472 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : Initial: Len = 477902, Over = 0
+PHY-3001 : End spreading;  0.041868s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (112.0%)
+
+PHY-3001 : Final: Len = 477902, Over = 0
+PHY-3001 : End incremental legalization;  0.263516s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.453074s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.0%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 10133/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 561872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.087021s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 46.40, top5 = 39.87, top10 = 36.20, top15 = 33.85.
+OPT-1001 : End congestion update;  0.309912s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.449827s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.3%)
+
+OPT-0007 : Start: WNS -886 TNS -1421 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -886 TNS -1421 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  0.767176s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (97.8%)
+
+OPT-1001 : Current memory(MB): used = 547, reserve = 530, peak = 549.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 10133/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 561872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.087460s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (89.3%)
+
+PHY-1001 : Congestion index: top1 = 46.40, top5 = 39.87, top10 = 36.20, top15 = 33.85.
+OPT-1001 : End congestion update;  0.301926s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (103.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.476478s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (95.1%)
+
+OPT-0007 : Start: WNS -886 TNS -1421 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -886 TNS -1421 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -886 TNS -1421 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  0.879849s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.4%)
+
+OPT-1001 : Current memory(MB): used = 547, reserve = 530, peak = 549.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.495384s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (97.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 547, reserve = 530, peak = 549.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.483923s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (100.1%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 10133/11274.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 561872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.090949s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (103.1%)
+
+PHY-1001 : Congestion index: top1 = 46.40, top5 = 39.87, top10 = 36.20, top15 = 33.85.
+RUN-1001 : End congestion update;  0.309824s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.9%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  0.796868s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 547, reserve = 530, peak = 549.
+OPT-1001 : End physical optimization;  10.636813s wall, 11.359375s user + 0.171875s system = 11.531250s CPU (108.4%)
+
+RUN-1003 : finish command "place" in  39.730841s wall, 56.671875s user + 5.531250s system = 62.203125s CPU (156.6%)
+
+RUN-1004 : used memory is 477 MB, reserved memory is 467 MB, peak memory is 549 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.383266s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (170.6%)
+
+RUN-1004 : used memory is 477 MB, reserved memory is 469 MB, peak memory is 549 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 4507 instances
+RUN-1001 : 2179 mslices, 2178 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 11274 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 6531 nets have 2 pins
+RUN-1001 : 3934 nets have [3 - 5] pins
+RUN-1001 : 405 nets have [6 - 10] pins
+RUN-1001 : 207 nets have [11 - 20] pins
+RUN-1001 : 169 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 44226, tnet num: 11184, tinst num: 4505, tnode num: 59531, tedge num: 73334.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.205327s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (99.8%)
+
+RUN-1004 : used memory is 476 MB, reserved memory is 458 MB, peak memory is 549 MB
+PHY-1001 : 2179 mslices, 2178 lslices, 75 pads, 58 brams, 2 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 539080, over cnt = 1028(2%), over = 1579, worst = 6
+PHY-1002 : len = 544208, over cnt = 567(1%), over = 795, worst = 6
+PHY-1002 : len = 548888, over cnt = 284(0%), over = 371, worst = 4
+PHY-1002 : len = 553008, over cnt = 39(0%), over = 51, worst = 3
+PHY-1002 : len = 553592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.946659s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (124.4%)
+
+PHY-1001 : Congestion index: top1 = 45.80, top5 = 39.67, top10 = 35.93, top15 = 33.53.
+PHY-1001 : End global routing;  2.172133s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (122.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 543, reserve = 524, peak = 549.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : Current memory(MB): used = 808, reserve = 793, peak = 808.
+PHY-1001 : End build detailed router design. 4.074051s wall, 4.046875s user + 0.015625s system = 4.062500s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 223648, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.417988s wall, 5.406250s user + 0.015625s system = 5.421875s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 223704, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.420502s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 843, reserve = 829, peak = 843.
+PHY-1001 : End phase 1; 5.851061s wall, 5.843750s user + 0.015625s system = 5.859375s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 40% nets.
+PHY-1001 : Routed 47% nets.
+PHY-1001 : Routed 57% nets.
+PHY-1001 : Routed 71% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 1.55424e+06, over cnt = 268(0%), over = 268, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 852, reserve = 837, peak = 852.
+PHY-1001 : End initial routed; 18.616093s wall, 32.234375s user + 0.187500s system = 32.421875s CPU (174.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/10564(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.075   |  -3.681   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 2.253764s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 861, reserve = 847, peak = 861.
+PHY-1001 : End phase 2; 20.869920s wall, 34.500000s user + 0.187500s system = 34.687500s CPU (166.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.949ns STNS -3.555ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.090338s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (103.8%)
+
+PHY-1022 : len = 1.55426e+06, over cnt = 268(0%), over = 268, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.248191s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 1.5515e+06, over cnt = 79(0%), over = 79, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.224482s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (153.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 1.55057e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.187549s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (116.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 1.55051e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 3; 0.115376s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (94.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/10564(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.949   |  -3.555   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 2.299819s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 61 feed throughs used by 57 nets
+PHY-1001 : End commit to database; 1.447452s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 927, reserve = 914, peak = 927.
+PHY-1001 : End phase 3; 4.839061s wall, 4.984375s user + 0.000000s system = 4.984375s CPU (103.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.949ns STNS -3.555ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.089932s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (104.2%)
+
+PHY-1022 : len = 1.55051e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.235042s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.7%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.949ns, -3.555ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/10564(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.949   |  -3.555   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 2.213136s wall, 2.218750s user + 0.000000s system = 2.218750s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 61 feed throughs used by 57 nets
+PHY-1001 : End commit to database; 1.513655s wall, 1.515625s user + 0.000000s system = 1.515625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 933, reserve = 920, peak = 933.
+PHY-1001 : End phase 4; 3.975640s wall, 3.984375s user + 0.000000s system = 3.984375s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 1.55051e+06
+PHY-1001 : Current memory(MB): used = 933, reserve = 921, peak = 933.
+PHY-1001 : End export database. 0.047807s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (98.1%)
+
+PHY-1001 : End detail routing;  39.982604s wall, 53.718750s user + 0.218750s system = 53.937500s CPU (134.9%)
+
+RUN-1003 : finish command "route" in  44.062212s wall, 58.234375s user + 0.265625s system = 58.500000s CPU (132.8%)
+
+RUN-1004 : used memory is 929 MB, reserved memory is 917 MB, peak memory is 933 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                     5600   out of  19600   28.57%
+#reg                     6508   out of  19600   33.20%
+#le                      7960
+  #lut only              1452   out of   7960   18.24%
+  #reg only              2360   out of   7960   29.65%
+  #lut&reg               4148   out of   7960   52.11%
+#dsp                        2   out of     29    6.90%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1789
+#2        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               971
+#3        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          514
+#4        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         432
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    138
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          50
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         50
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_a/reg1_syn_153.f1                        3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/en_adc_cfg_d2_reg_syn_8.f1             3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P143       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P19        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P118       LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P106       LVCMOS25           8            N/A        NONE    
+    frame_indicator       OUTPUT        P109       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P16        LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       scan_out           OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P140       LVCMOS33           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7960   |4946    |654     |6538    |58      |2       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |530    |397     |23      |440     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |99     |79      |4       |90      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |25     |25      |0       |18      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |778    |376     |96      |585     |0       |0       |
+|    u_ADconfig                |AD_config            |196    |140     |25      |149     |0       |0       |
+|    u_gen_sp                  |gen_sp               |264    |156     |71      |118     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |739    |408     |96      |551     |0       |0       |
+|    u_ADconfig                |AD_config            |166    |124     |25      |119     |0       |0       |
+|    u_gen_sp                  |gen_sp               |255    |167     |71      |114     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |965    |708     |139     |663     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |108    |64      |17      |74      |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |822    |621     |122     |554     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |6      |1       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |397    |307     |80      |205     |22      |0       |
+|        read_ram_i            |read_ram             |375    |289     |80      |185     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |323    |247     |76      |146     |0       |0       |
+|          read_ram_data       |read_ram_data        |48     |39      |4       |35      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |330    |231     |42      |286     |3       |0       |
+|        u0_soft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |957    |662     |146     |666     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |1       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |113    |71      |20      |82      |0       |0       |
+|      u0_soft_n               |cdc_sync             |8      |2       |0       |8       |0       |0       |
+|    u_sort                    |sort_rev             |807    |583     |126     |547     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |7      |1       |0       |7       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |7      |1       |0       |7       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1      |0       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |420    |299     |84      |228     |22      |0       |
+|        read_ram_i            |read_ram_rev         |393    |280     |84      |203     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |329    |241     |76      |156     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |64     |39      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |333    |240     |42      |277     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  scan_start_diff             |scan_start_diff      |15     |15      |0       |13      |0       |0       |
+|  u0_test_en                  |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|  u1_test_en                  |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|  u2_test_en                  |cdc_sync             |3      |0       |0       |3       |0       |0       |
+|  u_a_pclk                    |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|  u_a_sp_sampling             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|  u_a_sp_sampling_cam         |cdc_sync             |10     |2       |0       |10      |0       |0       |
+|  u_b_pclk                    |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|  u_b_sp_sampling             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|  u_b_sp_sampling_cam         |cdc_sync             |7      |3       |0       |7       |0       |0       |
+|  u_b_sp_sampling_last        |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|  u_bus_top                   |ubus_top             |1318   |1024    |22      |1236    |0       |0       |
+|    u_local_bus_slve_cis      |local_bus_slve_cis   |812    |701     |22      |730     |0       |0       |
+|      u_uart_2dsp             |uart_2dsp            |102    |88      |12      |59      |0       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       6469  
+    #2         2       2647  
+    #3         3       828   
+    #4         4       456   
+    #5        5-10     426   
+    #6       11-50     345   
+    #7       51-100     7    
+    #8        >500      1    
+  Average     2.60           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  1.695242s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (165.9%)
+
+RUN-1004 : used memory is 928 MB, reserved memory is 916 MB, peak memory is 983 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 44226, tnet num: 11184, tinst num: 4505, tnode num: 59531, tedge num: 73334.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.215874s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (100.2%)
+
+RUN-1004 : used memory is 928 MB, reserved memory is 916 MB, peak memory is 983 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 11184 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.051982s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (101.0%)
+
+RUN-1004 : used memory is 928 MB, reserved memory is 916 MB, peak memory is 983 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 4505
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 11274, pip num: 105081
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 61
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3207 valid insts, and 282063 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  7.087876s wall, 44.281250s user + 0.234375s system = 44.515625s CPU (628.1%)
+
+RUN-1004 : used memory is 985 MB, reserved memory is 970 MB, peak memory is 1100 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_165913.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_170319.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_170319.log
new file mode 100644
index 0000000..75cb59b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_170319.log
@@ -0,0 +1,2004 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 17:03:19 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.038742s wall, 1.953125s user + 0.078125s system = 2.031250s CPU (99.6%)
+
+RUN-1004 : used memory is 320 MB, reserved memory is 290 MB, peak memory is 323 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2939 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2278 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (729 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 14363 instances
+RUN-0007 : 5612 luts, 7729 seqs, 569 mslices, 306 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 16502 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10754 nets have 2 pins
+RUN-1001 : 4813 nets have [3 - 5] pins
+RUN-1001 : 575 nets have [6 - 10] pins
+RUN-1001 : 138 nets have [11 - 20] pins
+RUN-1001 : 160 nets have [21 - 99] pins
+RUN-1001 : 42 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     662     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    2842     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2121     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  67   |     52     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 129
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 14361 instances, 5612 luts, 7729 seqs, 875 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 4955 pins
+PHY-0007 : Cell area utilization is 40%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 68200, tnet num: 16368, tinst num: 14361, tnode num: 93882, tedge num: 109139.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.061225s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (100.1%)
+
+RUN-1004 : used memory is 477 MB, reserved memory is 452 MB, peak memory is 477 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 16368 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.736228s wall, 1.671875s user + 0.062500s system = 1.734375s CPU (99.9%)
+
+PHY-3001 : Found 2353 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 3.50584e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 14361.
+PHY-3001 : Level 1 #clusters 1807.
+PHY-3001 : End clustering;  0.114654s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (136.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 40%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.12103e+06, overlap = 335.156
+PHY-3002 : Step(2): len = 1.06873e+06, overlap = 402.344
+PHY-3002 : Step(3): len = 766869, overlap = 472.656
+PHY-3002 : Step(4): len = 689094, overlap = 535.312
+PHY-3002 : Step(5): len = 580022, overlap = 613.562
+PHY-3002 : Step(6): len = 473909, overlap = 658.906
+PHY-3002 : Step(7): len = 415623, overlap = 753.594
+PHY-3002 : Step(8): len = 359071, overlap = 832.406
+PHY-3002 : Step(9): len = 311222, overlap = 889.062
+PHY-3002 : Step(10): len = 281925, overlap = 932.375
+PHY-3002 : Step(11): len = 257346, overlap = 954.969
+PHY-3002 : Step(12): len = 239747, overlap = 986.406
+PHY-3002 : Step(13): len = 210524, overlap = 985.344
+PHY-3002 : Step(14): len = 200780, overlap = 1009.66
+PHY-3002 : Step(15): len = 188435, overlap = 1015.06
+PHY-3002 : Step(16): len = 172919, overlap = 1011.66
+PHY-3002 : Step(17): len = 164408, overlap = 1024.62
+PHY-3002 : Step(18): len = 153212, overlap = 1065.03
+PHY-3002 : Step(19): len = 143678, overlap = 1093.53
+PHY-3002 : Step(20): len = 135625, overlap = 1132.41
+PHY-3002 : Step(21): len = 125799, overlap = 1179.41
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.71385e-07
+PHY-3002 : Step(22): len = 127631, overlap = 1136.94
+PHY-3002 : Step(23): len = 155272, overlap = 1073.5
+PHY-3002 : Step(24): len = 161893, overlap = 1031.62
+PHY-3002 : Step(25): len = 168327, overlap = 988.188
+PHY-3002 : Step(26): len = 165201, overlap = 953.5
+PHY-3002 : Step(27): len = 165002, overlap = 931.719
+PHY-3002 : Step(28): len = 162850, overlap = 916.625
+PHY-3002 : Step(29): len = 162925, overlap = 899.312
+PHY-3002 : Step(30): len = 158438, overlap = 895.281
+PHY-3002 : Step(31): len = 157344, overlap = 897.844
+PHY-3002 : Step(32): len = 155307, overlap = 885.844
+PHY-3002 : Step(33): len = 154051, overlap = 886.094
+PHY-3002 : Step(34): len = 151812, overlap = 883.406
+PHY-3002 : Step(35): len = 151217, overlap = 875.969
+PHY-3002 : Step(36): len = 149812, overlap = 870.406
+PHY-3002 : Step(37): len = 149542, overlap = 899.125
+PHY-3002 : Step(38): len = 149051, overlap = 923.969
+PHY-3002 : Step(39): len = 148435, overlap = 922.781
+PHY-3002 : Step(40): len = 148296, overlap = 911.312
+PHY-3002 : Step(41): len = 146931, overlap = 911.75
+PHY-3002 : Step(42): len = 146408, overlap = 919.219
+PHY-3002 : Step(43): len = 145071, overlap = 900.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.94277e-06
+PHY-3002 : Step(44): len = 149077, overlap = 888.438
+PHY-3002 : Step(45): len = 160711, overlap = 855.656
+PHY-3002 : Step(46): len = 166221, overlap = 819.688
+PHY-3002 : Step(47): len = 168241, overlap = 807.844
+PHY-3002 : Step(48): len = 167565, overlap = 803.75
+PHY-3002 : Step(49): len = 167875, overlap = 795.188
+PHY-3002 : Step(50): len = 167188, overlap = 795.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.88554e-06
+PHY-3002 : Step(51): len = 173198, overlap = 779.062
+PHY-3002 : Step(52): len = 186005, overlap = 727.25
+PHY-3002 : Step(53): len = 192580, overlap = 697.219
+PHY-3002 : Step(54): len = 197955, overlap = 695.156
+PHY-3002 : Step(55): len = 201053, overlap = 690.375
+PHY-3002 : Step(56): len = 202686, overlap = 665.562
+PHY-3002 : Step(57): len = 203675, overlap = 654.312
+PHY-3002 : Step(58): len = 203314, overlap = 664.594
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.77108e-06
+PHY-3002 : Step(59): len = 216732, overlap = 629.938
+PHY-3002 : Step(60): len = 242902, overlap = 542.781
+PHY-3002 : Step(61): len = 254089, overlap = 442.656
+PHY-3002 : Step(62): len = 258253, overlap = 409.312
+PHY-3002 : Step(63): len = 257172, overlap = 407.75
+PHY-3002 : Step(64): len = 255382, overlap = 395.969
+PHY-3002 : Step(65): len = 252801, overlap = 407.75
+PHY-3002 : Step(66): len = 251377, overlap = 399.469
+PHY-3002 : Step(67): len = 248270, overlap = 421.188
+PHY-3002 : Step(68): len = 247520, overlap = 422.781
+PHY-3002 : Step(69): len = 247124, overlap = 415.844
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.55422e-05
+PHY-3002 : Step(70): len = 268193, overlap = 359.344
+PHY-3002 : Step(71): len = 283559, overlap = 318
+PHY-3002 : Step(72): len = 286900, overlap = 270.594
+PHY-3002 : Step(73): len = 289403, overlap = 282.75
+PHY-3002 : Step(74): len = 287796, overlap = 289.156
+PHY-3002 : Step(75): len = 287056, overlap = 282.812
+PHY-3002 : Step(76): len = 285801, overlap = 289.188
+PHY-3002 : Step(77): len = 285893, overlap = 291.5
+PHY-3002 : Step(78): len = 284293, overlap = 295
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.10843e-05
+PHY-3002 : Step(79): len = 303350, overlap = 260.094
+PHY-3002 : Step(80): len = 314609, overlap = 231.188
+PHY-3002 : Step(81): len = 317243, overlap = 225.031
+PHY-3002 : Step(82): len = 319105, overlap = 214.719
+PHY-3002 : Step(83): len = 319676, overlap = 200.812
+PHY-3002 : Step(84): len = 320957, overlap = 188.281
+PHY-3002 : Step(85): len = 320557, overlap = 189.344
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.21686e-05
+PHY-3002 : Step(86): len = 338814, overlap = 167.094
+PHY-3002 : Step(87): len = 352843, overlap = 162.469
+PHY-3002 : Step(88): len = 355095, overlap = 162.875
+PHY-3002 : Step(89): len = 357822, overlap = 166.594
+PHY-3002 : Step(90): len = 357653, overlap = 156.188
+PHY-3002 : Step(91): len = 358248, overlap = 156.312
+PHY-3002 : Step(92): len = 355411, overlap = 157.438
+PHY-3002 : Step(93): len = 355157, overlap = 163
+PHY-3002 : Step(94): len = 355647, overlap = 161.719
+PHY-3002 : Step(95): len = 356464, overlap = 166.438
+PHY-3002 : Step(96): len = 354751, overlap = 160.406
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000122347
+PHY-3002 : Step(97): len = 365998, overlap = 158.406
+PHY-3002 : Step(98): len = 375423, overlap = 154
+PHY-3002 : Step(99): len = 376700, overlap = 152.188
+PHY-3002 : Step(100): len = 378475, overlap = 149.688
+PHY-3002 : Step(101): len = 380096, overlap = 146.219
+PHY-3002 : Step(102): len = 381387, overlap = 147.719
+PHY-3002 : Step(103): len = 380027, overlap = 140.719
+PHY-3002 : Step(104): len = 380474, overlap = 142.969
+PHY-3002 : Step(105): len = 381941, overlap = 140.219
+PHY-3002 : Step(106): len = 383137, overlap = 143.938
+PHY-3002 : Step(107): len = 382428, overlap = 149.344
+PHY-3002 : Step(108): len = 382725, overlap = 146.031
+PHY-3002 : Step(109): len = 383995, overlap = 142.969
+PHY-3002 : Step(110): len = 384847, overlap = 138.094
+PHY-3002 : Step(111): len = 383689, overlap = 130.219
+PHY-3002 : Step(112): len = 383584, overlap = 133.156
+PHY-3002 : Step(113): len = 383832, overlap = 132.594
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000243303
+PHY-3002 : Step(114): len = 393322, overlap = 121.062
+PHY-3002 : Step(115): len = 402454, overlap = 109.812
+PHY-3002 : Step(116): len = 405481, overlap = 112.375
+PHY-3002 : Step(117): len = 407714, overlap = 110.562
+PHY-3002 : Step(118): len = 408733, overlap = 108.062
+PHY-3002 : Step(119): len = 409452, overlap = 111.719
+PHY-3002 : Step(120): len = 408735, overlap = 106.719
+PHY-3002 : Step(121): len = 409484, overlap = 103.125
+PHY-3002 : Step(122): len = 410501, overlap = 103.531
+PHY-3002 : Step(123): len = 410971, overlap = 97.4688
+PHY-3002 : Step(124): len = 409813, overlap = 99.0312
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000454953
+PHY-3002 : Step(125): len = 414742, overlap = 95.9062
+PHY-3002 : Step(126): len = 421015, overlap = 92.8125
+PHY-3002 : Step(127): len = 423034, overlap = 86.125
+PHY-3002 : Step(128): len = 424856, overlap = 88.125
+PHY-3002 : Step(129): len = 426807, overlap = 90.25
+PHY-3002 : Step(130): len = 427915, overlap = 91.7188
+PHY-3002 : Step(131): len = 427143, overlap = 94.9375
+PHY-3002 : Step(132): len = 427006, overlap = 95.7812
+PHY-3002 : Step(133): len = 428244, overlap = 92.2188
+PHY-3002 : Step(134): len = 429780, overlap = 82.5625
+PHY-3002 : Step(135): len = 429330, overlap = 90.9688
+PHY-3002 : Step(136): len = 429275, overlap = 92.7812
+PHY-3002 : Step(137): len = 429590, overlap = 87.7812
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000876508
+PHY-3002 : Step(138): len = 434041, overlap = 77.1562
+PHY-3002 : Step(139): len = 440945, overlap = 76.9062
+PHY-3002 : Step(140): len = 445231, overlap = 82.1875
+PHY-3002 : Step(141): len = 447849, overlap = 85.0312
+PHY-3002 : Step(142): len = 449610, overlap = 85.7188
+PHY-3002 : Step(143): len = 450805, overlap = 82.9062
+PHY-3002 : Step(144): len = 451470, overlap = 79.3125
+PHY-3002 : Step(145): len = 452292, overlap = 79.375
+PHY-3002 : Step(146): len = 452376, overlap = 79.8438
+PHY-3002 : Step(147): len = 452133, overlap = 79.25
+PHY-3002 : Step(148): len = 451473, overlap = 76.9375
+PHY-3002 : Step(149): len = 451135, overlap = 76.6875
+PHY-3002 : Step(150): len = 451037, overlap = 72.0312
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00162162
+PHY-3002 : Step(151): len = 452972, overlap = 69.5312
+PHY-3002 : Step(152): len = 456745, overlap = 69.5312
+PHY-3002 : Step(153): len = 459453, overlap = 62.5625
+PHY-3002 : Step(154): len = 462551, overlap = 64.75
+PHY-3002 : Step(155): len = 464199, overlap = 66.25
+PHY-3002 : Step(156): len = 465409, overlap = 68.5
+PHY-3002 : Step(157): len = 466249, overlap = 66.25
+PHY-3002 : Step(158): len = 467395, overlap = 66.0625
+PHY-3002 : Step(159): len = 468009, overlap = 59.3125
+PHY-3002 : Step(160): len = 468079, overlap = 59.3125
+PHY-3002 : Step(161): len = 467331, overlap = 61.5625
+PHY-3002 : Step(162): len = 466811, overlap = 60.4375
+PHY-3002 : Step(163): len = 466675, overlap = 60.4375
+PHY-3002 : Step(164): len = 466467, overlap = 60.6875
+PHY-3002 : Step(165): len = 466167, overlap = 65.1875
+PHY-3002 : Step(166): len = 466188, overlap = 65
+PHY-3002 : Step(167): len = 466541, overlap = 66.2812
+PHY-3002 : Step(168): len = 466779, overlap = 67.75
+PHY-3002 : Step(169): len = 466546, overlap = 67.3125
+PHY-3002 : Step(170): len = 466531, overlap = 67.375
+PHY-3002 : Step(171): len = 466807, overlap = 71.6875
+PHY-3002 : Step(172): len = 466930, overlap = 71.6875
+PHY-3002 : Step(173): len = 466792, overlap = 71.2812
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.0026735
+PHY-3002 : Step(174): len = 467762, overlap = 71.4688
+PHY-3002 : Step(175): len = 469049, overlap = 75.7812
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.013253s wall, 0.015625s user + 0.031250s system = 0.046875s CPU (353.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 47%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/16502.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 582208, over cnt = 1222(3%), over = 5065, worst = 37
+PHY-1001 : End global iterations;  0.630288s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (151.2%)
+
+PHY-1001 : Congestion index: top1 = 74.55, top5 = 54.28, top10 = 45.68, top15 = 40.49.
+PHY-3001 : End congestion estimation;  0.841992s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (139.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16368 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.734561s wall, 0.687500s user + 0.046875s system = 0.734375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000154889
+PHY-3002 : Step(176): len = 519437, overlap = 13.5
+PHY-3002 : Step(177): len = 518855, overlap = 12.625
+PHY-3002 : Step(178): len = 511568, overlap = 12.5312
+PHY-3002 : Step(179): len = 508775, overlap = 10.0938
+PHY-3002 : Step(180): len = 508295, overlap = 11.5625
+PHY-3002 : Step(181): len = 509134, overlap = 12.375
+PHY-3002 : Step(182): len = 507746, overlap = 10.6875
+PHY-3002 : Step(183): len = 507190, overlap = 11.5625
+PHY-3002 : Step(184): len = 503892, overlap = 12.9688
+PHY-3002 : Step(185): len = 502041, overlap = 13.0938
+PHY-3002 : Step(186): len = 499027, overlap = 12.4062
+PHY-3002 : Step(187): len = 496334, overlap = 13.5625
+PHY-3002 : Step(188): len = 494325, overlap = 15
+PHY-3002 : Step(189): len = 493403, overlap = 16.375
+PHY-3002 : Step(190): len = 491553, overlap = 16.9375
+PHY-3002 : Step(191): len = 489717, overlap = 20
+PHY-3002 : Step(192): len = 488839, overlap = 21.1562
+PHY-3002 : Step(193): len = 487366, overlap = 20.375
+PHY-3002 : Step(194): len = 485949, overlap = 19.0625
+PHY-3002 : Step(195): len = 485727, overlap = 19.9062
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000309779
+PHY-3002 : Step(196): len = 488951, overlap = 20.0312
+PHY-3002 : Step(197): len = 491446, overlap = 19
+PHY-3002 : Step(198): len = 494416, overlap = 12.9062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000544413
+PHY-3002 : Step(199): len = 500796, overlap = 14.1875
+PHY-3002 : Step(200): len = 513153, overlap = 14.0625
+PHY-3002 : Step(201): len = 516311, overlap = 13.25
+PHY-3002 : Step(202): len = 516152, overlap = 12.5
+PHY-3002 : Step(203): len = 517293, overlap = 13.375
+PHY-3002 : Step(204): len = 519503, overlap = 11.5
+PHY-3002 : Step(205): len = 521313, overlap = 9.8125
+PHY-3002 : Step(206): len = 524687, overlap = 10.2188
+PHY-3002 : Step(207): len = 526623, overlap = 9.4375
+PHY-3002 : Step(208): len = 525821, overlap = 9.65625
+PHY-3002 : Step(209): len = 523808, overlap = 9.65625
+PHY-3002 : Step(210): len = 522325, overlap = 9.03125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00108883
+PHY-3002 : Step(211): len = 526720, overlap = 8.28125
+PHY-3002 : Step(212): len = 530877, overlap = 9.15625
+PHY-3002 : Step(213): len = 536416, overlap = 8.0625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00179526
+PHY-3002 : Step(214): len = 538006, overlap = 8.59375
+PHY-3002 : Step(215): len = 545330, overlap = 10.2812
+PHY-3002 : Step(216): len = 555885, overlap = 9.78125
+PHY-3002 : Step(217): len = 561504, overlap = 10.7188
+PHY-3002 : Step(218): len = 563521, overlap = 11.1562
+PHY-3002 : Step(219): len = 562415, overlap = 10.7812
+PHY-3002 : Step(220): len = 560732, overlap = 10.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00290473
+PHY-3002 : Step(221): len = 561971, overlap = 10.2812
+PHY-3002 : Step(222): len = 564884, overlap = 10.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 47%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 38/16502.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 633288, over cnt = 2193(6%), over = 10234, worst = 41
+PHY-1001 : End global iterations;  1.322259s wall, 1.781250s user + 0.062500s system = 1.843750s CPU (139.4%)
+
+PHY-1001 : Congestion index: top1 = 89.22, top5 = 67.14, top10 = 57.32, top15 = 51.13.
+PHY-3001 : End congestion estimation;  1.555646s wall, 2.015625s user + 0.062500s system = 2.078125s CPU (133.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16368 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.825373s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000172466
+PHY-3002 : Step(223): len = 551415, overlap = 131.219
+PHY-3002 : Step(224): len = 546807, overlap = 95.9688
+PHY-3002 : Step(225): len = 537936, overlap = 91.0312
+PHY-3002 : Step(226): len = 530145, overlap = 80.625
+PHY-3002 : Step(227): len = 525102, overlap = 80.0625
+PHY-3002 : Step(228): len = 521292, overlap = 74.3125
+PHY-3002 : Step(229): len = 518417, overlap = 70.4688
+PHY-3002 : Step(230): len = 514740, overlap = 70.75
+PHY-3002 : Step(231): len = 510597, overlap = 71.8125
+PHY-3002 : Step(232): len = 505496, overlap = 72.75
+PHY-3002 : Step(233): len = 502127, overlap = 77.6562
+PHY-3002 : Step(234): len = 498047, overlap = 71.9062
+PHY-3002 : Step(235): len = 494857, overlap = 60.1562
+PHY-3002 : Step(236): len = 492353, overlap = 59.9688
+PHY-3002 : Step(237): len = 490684, overlap = 62.5312
+PHY-3002 : Step(238): len = 487180, overlap = 64.5938
+PHY-3002 : Step(239): len = 484573, overlap = 70.3438
+PHY-3002 : Step(240): len = 481899, overlap = 70.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000344932
+PHY-3002 : Step(241): len = 483765, overlap = 64.2188
+PHY-3002 : Step(242): len = 485983, overlap = 61.5312
+PHY-3002 : Step(243): len = 488377, overlap = 57.5625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000689863
+PHY-3002 : Step(244): len = 491830, overlap = 53.9375
+PHY-3002 : Step(245): len = 498319, overlap = 46.8125
+PHY-3002 : Step(246): len = 500525, overlap = 44.5938
+PHY-3002 : Step(247): len = 500055, overlap = 45.3125
+PHY-3002 : Step(248): len = 500010, overlap = 42.8438
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 68200, tnet num: 16368, tinst num: 14361, tnode num: 93882, tedge num: 109139.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.322298s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (99.3%)
+
+RUN-1004 : used memory is 520 MB, reserved memory is 500 MB, peak memory is 625 MB
+OPT-1001 : Total overflow 339.72 peak overflow 2.75
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 253/16502.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 582120, over cnt = 2268(6%), over = 7455, worst = 22
+PHY-1001 : End global iterations;  1.396828s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (140.9%)
+
+PHY-1001 : Congestion index: top1 = 64.48, top5 = 51.10, top10 = 45.16, top15 = 41.61.
+PHY-1001 : End incremental global routing;  1.682442s wall, 2.234375s user + 0.031250s system = 2.265625s CPU (134.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16368 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.785966s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.4%)
+
+OPT-1001 : 39 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 14237 has valid locations, 242 needs to be replaced
+PHY-3001 : design contains 14564 instances, 5679 luts, 7865 seqs, 875 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 5051 pins
+PHY-3001 : Found 2376 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 516327
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13640/16705.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 593192, over cnt = 2292(6%), over = 7563, worst = 22
+PHY-1001 : End global iterations;  0.218120s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (114.6%)
+
+PHY-1001 : Congestion index: top1 = 64.85, top5 = 51.31, top10 = 45.40, top15 = 41.91.
+PHY-3001 : End congestion estimation;  0.447193s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (108.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 69020, tnet num: 16571, tinst num: 14564, tnode num: 95115, tedge num: 110373.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.318693s wall, 1.265625s user + 0.046875s system = 1.312500s CPU (99.5%)
+
+RUN-1004 : used memory is 559 MB, reserved memory is 553 MB, peak memory is 631 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16571 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.189752s wall, 2.125000s user + 0.062500s system = 2.187500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(249): len = 515444, overlap = 0
+PHY-3002 : Step(250): len = 515030, overlap = 0
+PHY-3002 : Step(251): len = 514792, overlap = 0.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 13721/16705.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 590752, over cnt = 2295(6%), over = 7584, worst = 22
+PHY-1001 : End global iterations;  0.194806s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (96.2%)
+
+PHY-1001 : Congestion index: top1 = 65.71, top5 = 51.76, top10 = 45.67, top15 = 42.12.
+PHY-3001 : End congestion estimation;  0.432826s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (101.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 16571 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.831657s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000408466
+PHY-3002 : Step(252): len = 514612, overlap = 44.375
+PHY-3002 : Step(253): len = 514786, overlap = 43.4375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000816933
+PHY-3002 : Step(254): len = 514859, overlap = 44.3438
+PHY-3002 : Step(255): len = 515323, overlap = 44.5312
+PHY-3001 : Final: Len = 515323, Over = 44.5312
+PHY-3001 : End incremental placement;  4.466967s wall, 4.640625s user + 0.156250s system = 4.796875s CPU (107.4%)
+
+OPT-1001 : Total overflow 344.72 peak overflow 2.75
+OPT-1001 : End high-fanout net optimization;  7.421559s wall, 8.234375s user + 0.187500s system = 8.421875s CPU (113.5%)
+
+OPT-1001 : Current memory(MB): used = 632, reserve = 616, peak = 647.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13661/16705.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 592520, over cnt = 2241(6%), over = 6904, worst = 22
+PHY-1002 : len = 624968, over cnt = 1411(4%), over = 3406, worst = 18
+PHY-1002 : len = 649288, over cnt = 548(1%), over = 1247, worst = 14
+PHY-1002 : len = 660464, over cnt = 175(0%), over = 420, worst = 14
+PHY-1002 : len = 666048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.237131s wall, 1.718750s user + 0.031250s system = 1.750000s CPU (141.5%)
+
+PHY-1001 : Congestion index: top1 = 52.54, top5 = 45.36, top10 = 41.66, top15 = 39.27.
+OPT-1001 : End congestion update;  1.475317s wall, 1.953125s user + 0.031250s system = 1.984375s CPU (134.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 16571 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.681689s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (100.9%)
+
+OPT-0007 : Start: WNS -1068 TNS -1578 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 50 cells processed and 4950 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 14 cells processed and 1500 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 6 cells processed and 650 slack improved
+OPT-0007 : Iter 4: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 4 cells processed and 400 slack improved
+OPT-1001 : End global optimization;  2.196774s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (123.8%)
+
+OPT-1001 : Current memory(MB): used = 623, reserve = 607, peak = 647.
+OPT-1001 : End physical optimization;  11.570516s wall, 12.921875s user + 0.265625s system = 13.187500s CPU (114.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 5679 LUT to BLE ...
+SYN-4008 : Packed 5679 LUT and 2389 SEQ to BLE.
+SYN-4003 : Packing 5476 remaining SEQ's ...
+SYN-4005 : Packed 3080 SEQ with LUT/SLICE
+SYN-4006 : 427 single LUT's are left
+SYN-4006 : 2396 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 8075/11605 primitive instances ...
+PHY-3001 : End packing;  1.347451s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 5657 instances
+RUN-1001 : 2755 mslices, 2755 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 14432 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 8168 nets have 2 pins
+RUN-1001 : 5034 nets have [3 - 5] pins
+RUN-1001 : 696 nets have [6 - 10] pins
+RUN-1001 : 257 nets have [11 - 20] pins
+RUN-1001 : 248 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+PHY-3001 : design contains 5655 instances, 5510 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 2951 pins
+PHY-3001 : Found 1035 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : After packing: Len = 526263, Over = 166.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 6194/14432.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 642944, over cnt = 1331(3%), over = 2056, worst = 10
+PHY-1002 : len = 648368, over cnt = 756(2%), over = 1018, worst = 6
+PHY-1002 : len = 654104, over cnt = 408(1%), over = 553, worst = 5
+PHY-1002 : len = 658496, over cnt = 227(0%), over = 303, worst = 5
+PHY-1002 : len = 663112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.561838s wall, 2.171875s user + 0.031250s system = 2.203125s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 52.24, top5 = 45.65, top10 = 41.82, top15 = 39.30.
+PHY-3001 : End congestion estimation;  1.917802s wall, 2.515625s user + 0.031250s system = 2.546875s CPU (132.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59037, tnet num: 14298, tinst num: 5655, tnode num: 78055, tedge num: 98767.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.527985s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (100.2%)
+
+RUN-1004 : used memory is 550 MB, reserved memory is 536 MB, peak memory is 647 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14298 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.268213s wall, 2.250000s user + 0.015625s system = 2.265625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.0916e-05
+PHY-3002 : Step(256): len = 517111, overlap = 167
+PHY-3002 : Step(257): len = 512021, overlap = 163.25
+PHY-3002 : Step(258): len = 509185, overlap = 169.25
+PHY-3002 : Step(259): len = 507717, overlap = 169
+PHY-3002 : Step(260): len = 507276, overlap = 174
+PHY-3002 : Step(261): len = 505591, overlap = 176.25
+PHY-3002 : Step(262): len = 503086, overlap = 171
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000101832
+PHY-3002 : Step(263): len = 506650, overlap = 163.75
+PHY-3002 : Step(264): len = 510416, overlap = 156.25
+PHY-3002 : Step(265): len = 511240, overlap = 150.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000200822
+PHY-3002 : Step(266): len = 520950, overlap = 138
+PHY-3002 : Step(267): len = 530972, overlap = 126
+PHY-3002 : Step(268): len = 529355, overlap = 123.5
+PHY-3002 : Step(269): len = 527931, overlap = 123.5
+PHY-3002 : Step(270): len = 528461, overlap = 119
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.519903s wall, 0.546875s user + 0.609375s system = 1.156250s CPU (222.4%)
+
+PHY-3001 : Trial Legalized: Len = 590134
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 62%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 624/14432.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 679696, over cnt = 1778(5%), over = 2957, worst = 7
+PHY-1002 : len = 690096, over cnt = 1058(3%), over = 1585, worst = 7
+PHY-1002 : len = 700480, over cnt = 456(1%), over = 680, worst = 5
+PHY-1002 : len = 707664, over cnt = 146(0%), over = 216, worst = 3
+PHY-1002 : len = 710792, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations;  1.900531s wall, 2.812500s user + 0.015625s system = 2.828125s CPU (148.8%)
+
+PHY-1001 : Congestion index: top1 = 53.00, top5 = 46.73, top10 = 43.17, top15 = 40.78.
+PHY-3001 : End congestion estimation;  2.303796s wall, 3.203125s user + 0.031250s system = 3.234375s CPU (140.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14298 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.727725s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000150148
+PHY-3002 : Step(271): len = 566243, overlap = 34.5
+PHY-3002 : Step(272): len = 553845, overlap = 50.75
+PHY-3002 : Step(273): len = 545325, overlap = 68
+PHY-3002 : Step(274): len = 538078, overlap = 81
+PHY-3002 : Step(275): len = 534733, overlap = 88
+PHY-3002 : Step(276): len = 532722, overlap = 99.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000300295
+PHY-3002 : Step(277): len = 538536, overlap = 96.75
+PHY-3002 : Step(278): len = 543156, overlap = 98.5
+PHY-3002 : Step(279): len = 545314, overlap = 102
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00057492
+PHY-3002 : Step(280): len = 550622, overlap = 95.25
+PHY-3002 : Step(281): len = 560084, overlap = 92
+PHY-3002 : Step(282): len = 566965, overlap = 87
+PHY-3002 : Step(283): len = 567473, overlap = 88.5
+PHY-3002 : Step(284): len = 567315, overlap = 88.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.044003s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (106.5%)
+
+PHY-3001 : Legalized: Len = 586134, Over = 0
+PHY-3001 : Spreading special nets. 344 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.084418s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (92.5%)
+
+PHY-3001 : 478 instances has been re-located, deltaX = 168, deltaY = 284, maxDist = 4.
+PHY-3001 : Final: Len = 592490, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59037, tnet num: 14298, tinst num: 5658, tnode num: 78055, tedge num: 98767.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.682502s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (100.3%)
+
+RUN-1004 : used memory is 562 MB, reserved memory is 562 MB, peak memory is 647 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 2875/14432.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 692520, over cnt = 1708(4%), over = 2703, worst = 6
+PHY-1002 : len = 699480, over cnt = 1062(3%), over = 1554, worst = 6
+PHY-1002 : len = 711968, over cnt = 341(0%), over = 516, worst = 6
+PHY-1002 : len = 715696, over cnt = 140(0%), over = 215, worst = 6
+PHY-1002 : len = 718648, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.726354s wall, 2.625000s user + 0.046875s system = 2.671875s CPU (154.8%)
+
+PHY-1001 : Congestion index: top1 = 51.70, top5 = 45.26, top10 = 42.02, top15 = 39.93.
+PHY-1001 : End incremental global routing;  2.049980s wall, 2.937500s user + 0.046875s system = 2.984375s CPU (145.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14298 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.750683s wall, 0.734375s user + 0.015625s system = 0.750000s CPU (99.9%)
+
+OPT-1001 : 3 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5567 has valid locations, 13 needs to be replaced
+PHY-3001 : design contains 5668 instances, 5520 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3003 pins
+PHY-3001 : Found 1045 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 593585
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13092/14441.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719432, over cnt = 32(0%), over = 32, worst = 1
+PHY-1002 : len = 719552, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 719584, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.406601s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (99.9%)
+
+PHY-1001 : Congestion index: top1 = 51.70, top5 = 45.28, top10 = 42.06, top15 = 39.97.
+PHY-3001 : End congestion estimation;  0.711899s wall, 0.703125s user + 0.015625s system = 0.718750s CPU (101.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59095, tnet num: 14307, tinst num: 5668, tnode num: 78128, tedge num: 98834.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.678665s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (99.6%)
+
+RUN-1004 : used memory is 586 MB, reserved memory is 578 MB, peak memory is 647 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.431722s wall, 2.375000s user + 0.046875s system = 2.421875s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(285): len = 593320, overlap = 0
+PHY-3002 : Step(286): len = 593142, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 13085/14441.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719032, over cnt = 19(0%), over = 21, worst = 3
+PHY-1002 : len = 719160, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 719184, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 719216, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.548619s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (102.5%)
+
+PHY-1001 : Congestion index: top1 = 51.70, top5 = 45.30, top10 = 42.06, top15 = 39.97.
+PHY-3001 : End congestion estimation;  0.829241s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (101.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.730505s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.91573e-05
+PHY-3002 : Step(287): len = 593090, overlap = 1.25
+PHY-3002 : Step(288): len = 593090, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005920s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (263.9%)
+
+PHY-3001 : Legalized: Len = 593131, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.054810s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (114.0%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 593139, Over = 0
+PHY-3001 : End incremental placement;  5.130886s wall, 5.062500s user + 0.125000s system = 5.187500s CPU (101.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  8.412909s wall, 9.343750s user + 0.187500s system = 9.531250s CPU (113.3%)
+
+OPT-1001 : Current memory(MB): used = 652, reserve = 640, peak = 654.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13086/14441.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719120, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 719152, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 719168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.360408s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (104.0%)
+
+PHY-1001 : Congestion index: top1 = 51.68, top5 = 45.26, top10 = 42.04, top15 = 39.96.
+OPT-1001 : End congestion update;  0.635896s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (100.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.815567s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (101.5%)
+
+OPT-0007 : Start: WNS -1033 TNS -1735 NUM_FEPS 5
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5580 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5668 instances, 5520 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3003 pins
+PHY-3001 : Found 1045 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Initial: Len = 598272, Over = 0
+PHY-3001 : Spreading special nets. 26 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.052455s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (89.4%)
+
+PHY-3001 : 35 instances has been re-located, deltaX = 14, deltaY = 22, maxDist = 2.
+PHY-3001 : Final: Len = 598580, Over = 0
+PHY-3001 : End incremental legalization;  0.373713s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (100.3%)
+
+OPT-0007 : Iter 1: improved WNS -933 TNS -1468 NUM_FEPS 2 with 52 cells processed and 13890 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5580 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5668 instances, 5520 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3003 pins
+PHY-3001 : Found 1045 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Initial: Len = 605932, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.052766s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (88.8%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 9, deltaY = 16, maxDist = 4.
+PHY-3001 : Final: Len = 605544, Over = 0
+PHY-3001 : End incremental legalization;  0.330802s wall, 0.328125s user + 0.078125s system = 0.406250s CPU (122.8%)
+
+OPT-0007 : Iter 2: improved WNS -933 TNS -1468 NUM_FEPS 2 with 40 cells processed and 10840 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5580 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5668 instances, 5520 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3003 pins
+PHY-3001 : Found 1045 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Initial: Len = 605662, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.050962s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (92.0%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 2, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 605650, Over = 0
+PHY-3001 : End incremental legalization;  0.334274s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (126.2%)
+
+OPT-0007 : Iter 3: improved WNS -933 TNS -1468 NUM_FEPS 2 with 11 cells processed and 456 slack improved
+OPT-1001 : End path based optimization;  2.862302s wall, 2.953125s user + 0.093750s system = 3.046875s CPU (106.4%)
+
+OPT-1001 : Current memory(MB): used = 653, reserve = 641, peak = 655.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.616311s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (98.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 12687/14441.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731976, over cnt = 172(0%), over = 223, worst = 7
+PHY-1002 : len = 732320, over cnt = 57(0%), over = 62, worst = 2
+PHY-1002 : len = 732736, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 732992, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 733104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.761618s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (110.8%)
+
+PHY-1001 : Congestion index: top1 = 52.41, top5 = 45.86, top10 = 42.63, top15 = 40.46.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.630010s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (99.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -983 TNS -1518 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 52.000000
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -983ps with logic level 2 
+RUN-1001 :       #2 path slack -897ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 14441 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 14441 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5580 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5668 instances, 5520 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3003 pins
+PHY-3001 : Found 1045 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Initial: Len = 605650, Over = 0
+PHY-3001 : End spreading;  0.058855s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (79.6%)
+
+PHY-3001 : Final: Len = 605650, Over = 0
+PHY-3001 : End incremental legalization;  0.368184s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (123.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.621696s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (98.0%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13104/14441.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.114075s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (95.9%)
+
+PHY-1001 : Congestion index: top1 = 52.41, top5 = 45.86, top10 = 42.63, top15 = 40.46.
+OPT-1001 : End congestion update;  0.386168s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.614106s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.2%)
+
+OPT-0007 : Start: WNS -983 TNS -1518 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 5580 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 5668 instances, 5520 slices, 171 macros(875 instances: 569 mslices 306 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3003 pins
+PHY-3001 : Found 1045 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 63%
+PHY-3001 : Initial: Len = 605648, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.052776s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (118.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 605650, Over = 0
+PHY-3001 : End incremental legalization;  0.325870s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (100.7%)
+
+OPT-0007 : Iter 1: improved WNS -933 TNS -1468 NUM_FEPS 2 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS -933 TNS -1468 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.421024s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (100.1%)
+
+OPT-1001 : Current memory(MB): used = 653, reserve = 641, peak = 655.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13104/14441.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.111555s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (98.0%)
+
+PHY-1001 : Congestion index: top1 = 52.41, top5 = 45.86, top10 = 42.63, top15 = 40.46.
+OPT-1001 : End congestion update;  0.384415s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.615903s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (98.9%)
+
+OPT-0007 : Start: WNS -983 TNS -1518 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.131146s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.8%)
+
+OPT-1001 : Current memory(MB): used = 653, reserve = 641, peak = 655.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.615636s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 653, reserve = 641, peak = 655.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.614560s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.2%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 13104/14441.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.114696s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (95.4%)
+
+PHY-1001 : Congestion index: top1 = 52.41, top5 = 45.86, top10 = 42.63, top15 = 40.46.
+RUN-1001 : End congestion update;  0.385372s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.3%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.002554s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.7%)
+
+OPT-1001 : Current memory(MB): used = 653, reserve = 641, peak = 655.
+OPT-1001 : End physical optimization;  20.848442s wall, 22.015625s user + 0.281250s system = 22.296875s CPU (106.9%)
+
+RUN-1003 : finish command "place" in  58.719090s wall, 85.765625s user + 6.593750s system = 92.359375s CPU (157.3%)
+
+RUN-1004 : used memory is 568 MB, reserved memory is 560 MB, peak memory is 655 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.582061s wall, 2.734375s user + 0.046875s system = 2.781250s CPU (175.8%)
+
+RUN-1004 : used memory is 569 MB, reserved memory is 561 MB, peak memory is 655 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 5670 instances
+RUN-1001 : 2765 mslices, 2755 lslices, 75 pads, 58 brams, 2 dsps
+RUN-1001 : There are total 14441 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 8165 nets have 2 pins
+RUN-1001 : 5034 nets have [3 - 5] pins
+RUN-1001 : 701 nets have [6 - 10] pins
+RUN-1001 : 260 nets have [11 - 20] pins
+RUN-1001 : 253 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59095, tnet num: 14307, tinst num: 5668, tnode num: 78128, tedge num: 98834.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.444709s wall, 1.437500s user + 0.000000s system = 1.437500s CPU (99.5%)
+
+RUN-1004 : used memory is 579 MB, reserved memory is 578 MB, peak memory is 655 MB
+PHY-1001 : 2765 mslices, 2755 lslices, 75 pads, 58 brams, 2 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 691200, over cnt = 1874(5%), over = 3034, worst = 8
+PHY-1002 : len = 701048, over cnt = 1111(3%), over = 1626, worst = 6
+PHY-1002 : len = 715560, over cnt = 329(0%), over = 443, worst = 5
+PHY-1002 : len = 721712, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 721744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.493714s wall, 3.296875s user + 0.093750s system = 3.390625s CPU (136.0%)
+
+PHY-1001 : Congestion index: top1 = 51.96, top5 = 45.48, top10 = 42.21, top15 = 40.11.
+PHY-1001 : End global routing;  2.787028s wall, 3.609375s user + 0.093750s system = 3.703125s CPU (132.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 637, reserve = 630, peak = 655.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 906, reserve = 898, peak = 906.
+PHY-1001 : End build detailed router design. 4.167986s wall, 4.140625s user + 0.000000s system = 4.140625s CPU (99.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 239808, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.675077s wall, 5.671875s user + 0.000000s system = 5.671875s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 239864, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.470107s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 942, reserve = 935, peak = 942.
+PHY-1001 : End phase 1; 6.163519s wall, 6.156250s user + 0.000000s system = 6.156250s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 1.96682e+06, over cnt = 717(0%), over = 717, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 952, reserve = 942, peak = 952.
+PHY-1001 : End initial routed; 21.230663s wall, 49.171875s user + 0.328125s system = 49.500000s CPU (233.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/13549(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.355   |  -4.089   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.139762s wall, 3.140625s user + 0.000000s system = 3.140625s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 960, reserve = 950, peak = 960.
+PHY-1001 : End phase 2; 24.370505s wall, 52.312500s user + 0.328125s system = 52.640625s CPU (216.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.043ns STNS -3.793ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.120212s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (91.0%)
+
+PHY-1022 : len = 1.96683e+06, over cnt = 719(0%), over = 719, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.350867s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (102.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 1.95567e+06, over cnt = 228(0%), over = 228, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.763069s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (178.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 1.95498e+06, over cnt = 36(0%), over = 36, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.328994s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (133.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 1.95422e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.232684s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 1.95428e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 4; 0.169048s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/13549(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.074   |  -3.824   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 2.929843s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (99.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 195 feed throughs used by 155 nets
+PHY-1001 : End commit to database; 2.019402s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1045, reserve = 1039, peak = 1045.
+PHY-1001 : End phase 3; 7.157660s wall, 7.812500s user + 0.015625s system = 7.828125s CPU (109.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.043ns STNS -3.793ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.123112s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (88.8%)
+
+PHY-1022 : len = 1.9543e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.332944s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (103.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.043ns, -3.793ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 1.9543e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.138161s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/13549(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.043   |  -3.793   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.186112s wall, 3.187500s user + 0.000000s system = 3.187500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 194 feed throughs used by 154 nets
+PHY-1001 : End commit to database; 2.012457s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1046, peak = 1053.
+PHY-1001 : End phase 4; 5.714419s wall, 5.718750s user + 0.000000s system = 5.718750s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 1.9543e+06
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1047, peak = 1054.
+PHY-1001 : End export database. 0.058807s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.3%)
+
+PHY-1001 : End detail routing;  48.026560s wall, 76.578125s user + 0.343750s system = 76.921875s CPU (160.2%)
+
+RUN-1003 : finish command "route" in  53.187834s wall, 82.546875s user + 0.453125s system = 83.000000s CPU (156.1%)
+
+RUN-1004 : used memory is 1049 MB, reserved memory is 1043 MB, peak memory is 1054 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                     7878   out of  19600   40.19%
+#reg                     8023   out of  19600   40.93%
+#le                     10205
+  #lut only              2182   out of  10205   21.38%
+  #reg only              2327   out of  10205   22.80%
+  #lut&reg               5696   out of  10205   55.82%
+#dsp                        2   out of     29    6.90%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1801
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1417
+#3        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               996
+#4        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         427
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    138
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          76
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         49
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_eot_min/reg1_syn_305.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             exdev_ctl_b/u_ADconfig/reg1_syn_190.f1             3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+       paper_in            INPUT        P146       LVCMOS33          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P148       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P118       LVCMOS25           8            N/A        NONE    
+    frame_indicator       OUTPUT        P39        LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P168       LVCMOS33           8            N/A        NONE    
+       scan_out           OUTPUT        P107       LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |10205  |7039    |839     |8053    |58      |2       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |547    |431     |23      |450     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |109    |86      |4       |95      |4       |0       |
+|    U_ecc_gen                 |ecc_gen              |11     |11      |0       |8       |0       |0       |
+|    U_crc16_24b               |crc16_24b            |27     |27      |0       |20      |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |771    |318     |96      |585     |0       |0       |
+|    u_ADconfig                |AD_config            |192    |95      |25      |144     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |158     |71      |125     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |416     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |172    |130     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |259    |171     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3187   |2512    |327     |2162    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |4       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |184    |123     |17      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |2       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |2968   |2384    |310     |1980    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |5       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |6      |2       |0       |6       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2442   |1965    |268     |1557    |22      |0       |
+|        channelPart           |channel_part_8478    |167    |162     |3       |127     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |38      |0       |0       |
+|        ram_switch            |ram_switch           |1875   |1487    |197     |1174    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |244    |214     |27      |128     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |8       |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |17      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |15      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|          insert              |insert               |1002   |648     |170     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |629    |625     |0       |354     |0       |0       |
+|        read_ram_i            |read_ram             |316    |251     |59      |192     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |252    |197     |55      |146     |0       |0       |
+|          read_ram_data       |read_ram_data        |61     |51      |4       |43      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1      |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |304    |226     |42      |271     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |930    |630     |143     |679     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |10     |2       |0       |10      |0       |0       |
+|    u_ad_sampling             |ad_sampling          |108    |64      |17      |74      |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |782    |544     |126     |565     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |399    |286     |84      |236     |22      |0       |
+|        read_ram_i            |read_ram_rev         |375    |270     |84      |214     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |301    |221     |76      |157     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |74     |49      |8       |57      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |315    |198     |42      |278     |3       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       8103  
+    #2         2       3313  
+    #3         3       1139  
+    #4         4       579   
+    #5        5-10     733   
+    #6       11-50     463   
+    #7       51-100     15   
+    #8        >500      1    
+  Average     2.78           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  1.936644s wall, 3.265625s user + 0.062500s system = 3.328125s CPU (171.9%)
+
+RUN-1004 : used memory is 1049 MB, reserved memory is 1043 MB, peak memory is 1104 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 59095, tnet num: 14307, tinst num: 5668, tnode num: 78128, tedge num: 98834.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.462044s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (100.5%)
+
+RUN-1004 : used memory is 1051 MB, reserved memory is 1045 MB, peak memory is 1104 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 14307 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.292003s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.4%)
+
+RUN-1004 : used memory is 1052 MB, reserved memory is 1045 MB, peak memory is 1104 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 5668
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 14441, pip num: 139285
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 194
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3245 valid insts, and 380922 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  8.849553s wall, 56.640625s user + 0.250000s system = 56.890625s CPU (642.9%)
+
+RUN-1004 : used memory is 1132 MB, reserved memory is 1123 MB, peak memory is 1248 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_170319.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_171044.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_171044.log
new file mode 100644
index 0000000..3cf6769
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240311_171044.log
@@ -0,0 +1,1913 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 17:10:44 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.285962s wall, 2.156250s user + 0.125000s system = 2.281250s CPU (99.8%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 316 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2278 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2118 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17845 instances
+RUN-0007 : 7451 luts, 9171 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20429 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13486 nets have 2 pins
+RUN-1001 : 5485 nets have [3 - 5] pins
+RUN-1001 : 1046 nets have [6 - 10] pins
+RUN-1001 : 156 nets have [11 - 20] pins
+RUN-1001 : 182 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     803     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3591     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     59     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17843 instances, 7451 luts, 9171 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 5811 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85287, tnet num: 20251, tinst num: 17843, tnode num: 115752, tedge num: 136822.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.238523s wall, 1.203125s user + 0.031250s system = 1.234375s CPU (99.7%)
+
+RUN-1004 : used memory is 539 MB, reserved memory is 517 MB, peak memory is 539 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20251 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.091087s wall, 2.046875s user + 0.046875s system = 2.093750s CPU (100.1%)
+
+PHY-3001 : Found 3478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.08416e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17843.
+PHY-3001 : Level 1 #clusters 2029.
+PHY-3001 : End clustering;  0.144870s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (118.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28294e+06, overlap = 489.344
+PHY-3002 : Step(2): len = 1.18917e+06, overlap = 549.844
+PHY-3002 : Step(3): len = 849556, overlap = 570.375
+PHY-3002 : Step(4): len = 783522, overlap = 635.062
+PHY-3002 : Step(5): len = 610494, overlap = 747.656
+PHY-3002 : Step(6): len = 543050, overlap = 815.594
+PHY-3002 : Step(7): len = 463269, overlap = 892.656
+PHY-3002 : Step(8): len = 427308, overlap = 948.625
+PHY-3002 : Step(9): len = 380248, overlap = 994.375
+PHY-3002 : Step(10): len = 350366, overlap = 1080.06
+PHY-3002 : Step(11): len = 309843, overlap = 1135.5
+PHY-3002 : Step(12): len = 287682, overlap = 1184.66
+PHY-3002 : Step(13): len = 262271, overlap = 1227.44
+PHY-3002 : Step(14): len = 239828, overlap = 1272.41
+PHY-3002 : Step(15): len = 212745, overlap = 1310.66
+PHY-3002 : Step(16): len = 197605, overlap = 1332.16
+PHY-3002 : Step(17): len = 174098, overlap = 1351.91
+PHY-3002 : Step(18): len = 166886, overlap = 1382.12
+PHY-3002 : Step(19): len = 154293, overlap = 1414.41
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.79603e-07
+PHY-3002 : Step(20): len = 153197, overlap = 1397.75
+PHY-3002 : Step(21): len = 181311, overlap = 1293
+PHY-3002 : Step(22): len = 184806, overlap = 1269.12
+PHY-3002 : Step(23): len = 186806, overlap = 1257.09
+PHY-3002 : Step(24): len = 186861, overlap = 1262.25
+PHY-3002 : Step(25): len = 186082, overlap = 1215.19
+PHY-3002 : Step(26): len = 184481, overlap = 1207.09
+PHY-3002 : Step(27): len = 183781, overlap = 1185.59
+PHY-3002 : Step(28): len = 180665, overlap = 1193.22
+PHY-3002 : Step(29): len = 179598, overlap = 1196.31
+PHY-3002 : Step(30): len = 177335, overlap = 1187.38
+PHY-3002 : Step(31): len = 176046, overlap = 1167.38
+PHY-3002 : Step(32): len = 174943, overlap = 1160.78
+PHY-3002 : Step(33): len = 173392, overlap = 1148.88
+PHY-3002 : Step(34): len = 172840, overlap = 1147.59
+PHY-3002 : Step(35): len = 172899, overlap = 1150.22
+PHY-3002 : Step(36): len = 172739, overlap = 1140.72
+PHY-3002 : Step(37): len = 173132, overlap = 1150.09
+PHY-3002 : Step(38): len = 171581, overlap = 1152.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.95921e-06
+PHY-3002 : Step(39): len = 175141, overlap = 1137.19
+PHY-3002 : Step(40): len = 187140, overlap = 1128.38
+PHY-3002 : Step(41): len = 193013, overlap = 1112.81
+PHY-3002 : Step(42): len = 196471, overlap = 1102.47
+PHY-3002 : Step(43): len = 196638, overlap = 1099.38
+PHY-3002 : Step(44): len = 196565, overlap = 1073.28
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.91841e-06
+PHY-3002 : Step(45): len = 205130, overlap = 1043.25
+PHY-3002 : Step(46): len = 219300, overlap = 889.25
+PHY-3002 : Step(47): len = 228423, overlap = 866.375
+PHY-3002 : Step(48): len = 237238, overlap = 850.625
+PHY-3002 : Step(49): len = 242534, overlap = 842.219
+PHY-3002 : Step(50): len = 244699, overlap = 856.281
+PHY-3002 : Step(51): len = 244023, overlap = 863.781
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.83682e-06
+PHY-3002 : Step(52): len = 260783, overlap = 813.719
+PHY-3002 : Step(53): len = 293556, overlap = 670.125
+PHY-3002 : Step(54): len = 305913, overlap = 604.5
+PHY-3002 : Step(55): len = 310003, overlap = 584.438
+PHY-3002 : Step(56): len = 308722, overlap = 582.625
+PHY-3002 : Step(57): len = 305614, overlap = 602.281
+PHY-3002 : Step(58): len = 301312, overlap = 599.156
+PHY-3002 : Step(59): len = 299399, overlap = 593.188
+PHY-3002 : Step(60): len = 298994, overlap = 598.312
+PHY-3002 : Step(61): len = 298669, overlap = 591.281
+PHY-3002 : Step(62): len = 297534, overlap = 589.906
+PHY-3002 : Step(63): len = 294911, overlap = 614.156
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.56736e-05
+PHY-3002 : Step(64): len = 316383, overlap = 578.531
+PHY-3002 : Step(65): len = 336056, overlap = 536.906
+PHY-3002 : Step(66): len = 339161, overlap = 503.438
+PHY-3002 : Step(67): len = 340045, overlap = 496.375
+PHY-3002 : Step(68): len = 339310, overlap = 490.906
+PHY-3002 : Step(69): len = 338874, overlap = 477.469
+PHY-3002 : Step(70): len = 336601, overlap = 490.812
+PHY-3002 : Step(71): len = 336353, overlap = 479.812
+PHY-3002 : Step(72): len = 336637, overlap = 463.688
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.13473e-05
+PHY-3002 : Step(73): len = 356504, overlap = 450.75
+PHY-3002 : Step(74): len = 372354, overlap = 410.875
+PHY-3002 : Step(75): len = 374507, overlap = 398.875
+PHY-3002 : Step(76): len = 374370, overlap = 381.031
+PHY-3002 : Step(77): len = 374960, overlap = 352.25
+PHY-3002 : Step(78): len = 377186, overlap = 339.25
+PHY-3002 : Step(79): len = 376874, overlap = 344.531
+PHY-3002 : Step(80): len = 378534, overlap = 323.719
+PHY-3002 : Step(81): len = 379070, overlap = 314.562
+PHY-3002 : Step(82): len = 379522, overlap = 318.75
+PHY-3002 : Step(83): len = 378465, overlap = 324.781
+PHY-3002 : Step(84): len = 378943, overlap = 319.156
+PHY-3002 : Step(85): len = 378541, overlap = 338.375
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.26946e-05
+PHY-3002 : Step(86): len = 400180, overlap = 298.875
+PHY-3002 : Step(87): len = 411846, overlap = 287.781
+PHY-3002 : Step(88): len = 409619, overlap = 287.094
+PHY-3002 : Step(89): len = 409031, overlap = 283.875
+PHY-3002 : Step(90): len = 411197, overlap = 283.406
+PHY-3002 : Step(91): len = 412832, overlap = 269.531
+PHY-3002 : Step(92): len = 410961, overlap = 266.344
+PHY-3002 : Step(93): len = 411744, overlap = 260.812
+PHY-3002 : Step(94): len = 413395, overlap = 260.438
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000125389
+PHY-3002 : Step(95): len = 429312, overlap = 230.938
+PHY-3002 : Step(96): len = 440637, overlap = 225.219
+PHY-3002 : Step(97): len = 441127, overlap = 228.25
+PHY-3002 : Step(98): len = 443939, overlap = 212.344
+PHY-3002 : Step(99): len = 447652, overlap = 196.719
+PHY-3002 : Step(100): len = 451172, overlap = 203.156
+PHY-3002 : Step(101): len = 450301, overlap = 195.75
+PHY-3002 : Step(102): len = 451220, overlap = 202.875
+PHY-3002 : Step(103): len = 453216, overlap = 201.125
+PHY-3002 : Step(104): len = 454928, overlap = 200.531
+PHY-3002 : Step(105): len = 451371, overlap = 188.844
+PHY-3002 : Step(106): len = 451214, overlap = 194.844
+PHY-3002 : Step(107): len = 452078, overlap = 188.906
+PHY-3002 : Step(108): len = 452782, overlap = 171.062
+PHY-3002 : Step(109): len = 451670, overlap = 169.094
+PHY-3002 : Step(110): len = 452342, overlap = 171.438
+PHY-3002 : Step(111): len = 452618, overlap = 171.625
+PHY-3002 : Step(112): len = 452732, overlap = 161.062
+PHY-3002 : Step(113): len = 451532, overlap = 177.812
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000244015
+PHY-3002 : Step(114): len = 462323, overlap = 164
+PHY-3002 : Step(115): len = 470858, overlap = 160.812
+PHY-3002 : Step(116): len = 471598, overlap = 160.844
+PHY-3002 : Step(117): len = 472045, overlap = 155.5
+PHY-3002 : Step(118): len = 474162, overlap = 159.781
+PHY-3002 : Step(119): len = 475960, overlap = 161.688
+PHY-3002 : Step(120): len = 475749, overlap = 162.25
+PHY-3002 : Step(121): len = 477399, overlap = 156.719
+PHY-3002 : Step(122): len = 479488, overlap = 155.906
+PHY-3002 : Step(123): len = 481076, overlap = 155.969
+PHY-3002 : Step(124): len = 480639, overlap = 158.844
+PHY-3002 : Step(125): len = 481386, overlap = 165.812
+PHY-3002 : Step(126): len = 482578, overlap = 169.406
+PHY-3002 : Step(127): len = 482965, overlap = 165.812
+PHY-3002 : Step(128): len = 481776, overlap = 169.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000450183
+PHY-3002 : Step(129): len = 488047, overlap = 166.375
+PHY-3002 : Step(130): len = 495294, overlap = 167.219
+PHY-3002 : Step(131): len = 497361, overlap = 165.688
+PHY-3002 : Step(132): len = 499497, overlap = 173.219
+PHY-3002 : Step(133): len = 501933, overlap = 156.688
+PHY-3002 : Step(134): len = 503927, overlap = 158.125
+PHY-3002 : Step(135): len = 503234, overlap = 159.906
+PHY-3002 : Step(136): len = 503223, overlap = 158.219
+PHY-3002 : Step(137): len = 504036, overlap = 153.438
+PHY-3002 : Step(138): len = 504558, overlap = 155.156
+PHY-3002 : Step(139): len = 503991, overlap = 157.469
+PHY-3002 : Step(140): len = 504422, overlap = 161.969
+PHY-3002 : Step(141): len = 505173, overlap = 163
+PHY-3002 : Step(142): len = 505356, overlap = 158.75
+PHY-3002 : Step(143): len = 504670, overlap = 161.969
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000798429
+PHY-3002 : Step(144): len = 508977, overlap = 155
+PHY-3002 : Step(145): len = 513762, overlap = 146.156
+PHY-3002 : Step(146): len = 514553, overlap = 147.781
+PHY-3002 : Step(147): len = 515513, overlap = 149.188
+PHY-3002 : Step(148): len = 517325, overlap = 144.688
+PHY-3002 : Step(149): len = 519002, overlap = 140.844
+PHY-3002 : Step(150): len = 519574, overlap = 140.969
+PHY-3002 : Step(151): len = 522158, overlap = 133.844
+PHY-3002 : Step(152): len = 524319, overlap = 130.75
+PHY-3002 : Step(153): len = 525208, overlap = 128.375
+PHY-3002 : Step(154): len = 524358, overlap = 127.594
+PHY-3002 : Step(155): len = 524246, overlap = 127.812
+PHY-3002 : Step(156): len = 525120, overlap = 130.562
+PHY-3002 : Step(157): len = 525375, overlap = 125.312
+PHY-3002 : Step(158): len = 524395, overlap = 124.469
+PHY-3002 : Step(159): len = 524124, overlap = 122.125
+PHY-3002 : Step(160): len = 524791, overlap = 120.625
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00151696
+PHY-3002 : Step(161): len = 528248, overlap = 119.5
+PHY-3002 : Step(162): len = 536544, overlap = 108.812
+PHY-3002 : Step(163): len = 540732, overlap = 101.844
+PHY-3002 : Step(164): len = 544079, overlap = 104.406
+PHY-3002 : Step(165): len = 547003, overlap = 111.312
+PHY-3002 : Step(166): len = 549971, overlap = 100.844
+PHY-3002 : Step(167): len = 550152, overlap = 101.094
+PHY-3002 : Step(168): len = 550232, overlap = 96.9688
+PHY-3002 : Step(169): len = 550620, overlap = 97.8438
+PHY-3002 : Step(170): len = 551119, overlap = 106.312
+PHY-3002 : Step(171): len = 550788, overlap = 95.75
+PHY-3002 : Step(172): len = 550613, overlap = 94.1875
+PHY-3002 : Step(173): len = 550426, overlap = 97.6875
+PHY-3002 : Step(174): len = 550494, overlap = 97.125
+PHY-3002 : Step(175): len = 550571, overlap = 99.75
+PHY-3002 : Step(176): len = 550471, overlap = 99.375
+PHY-3002 : Step(177): len = 550199, overlap = 99.4062
+PHY-3002 : Step(178): len = 549934, overlap = 99.4688
+PHY-3002 : Step(179): len = 549710, overlap = 101.844
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00262461
+PHY-3002 : Step(180): len = 551038, overlap = 101.281
+PHY-3002 : Step(181): len = 553077, overlap = 103.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015146s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (103.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20429.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 712832, over cnt = 1597(4%), over = 7708, worst = 45
+PHY-1001 : End global iterations;  0.764933s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (143.0%)
+
+PHY-1001 : Congestion index: top1 = 84.07, top5 = 62.08, top10 = 52.41, top15 = 46.68.
+PHY-3001 : End congestion estimation;  0.992410s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (132.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20251 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.961288s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.38156e-05
+PHY-3002 : Step(182): len = 651347, overlap = 58.4688
+PHY-3002 : Step(183): len = 656227, overlap = 56.5312
+PHY-3002 : Step(184): len = 654002, overlap = 55.6875
+PHY-3002 : Step(185): len = 653324, overlap = 57.3438
+PHY-3002 : Step(186): len = 653927, overlap = 60.3438
+PHY-3002 : Step(187): len = 660833, overlap = 55.7812
+PHY-3002 : Step(188): len = 668173, overlap = 66.5625
+PHY-3002 : Step(189): len = 671616, overlap = 76.8125
+PHY-3002 : Step(190): len = 674650, overlap = 74.0938
+PHY-3002 : Step(191): len = 679996, overlap = 71.25
+PHY-3002 : Step(192): len = 682932, overlap = 79.125
+PHY-3002 : Step(193): len = 684572, overlap = 74.3438
+PHY-3002 : Step(194): len = 687479, overlap = 68.0312
+PHY-3002 : Step(195): len = 692735, overlap = 70.2812
+PHY-3002 : Step(196): len = 694567, overlap = 66.125
+PHY-3002 : Step(197): len = 695722, overlap = 62.1875
+PHY-3002 : Step(198): len = 695682, overlap = 56.875
+PHY-3002 : Step(199): len = 696687, overlap = 51.8125
+PHY-3002 : Step(200): len = 697605, overlap = 52.5
+PHY-3002 : Step(201): len = 697488, overlap = 54
+PHY-3002 : Step(202): len = 698969, overlap = 52.7188
+PHY-3002 : Step(203): len = 698491, overlap = 53.0625
+PHY-3002 : Step(204): len = 698121, overlap = 53.125
+PHY-3002 : Step(205): len = 696894, overlap = 51.125
+PHY-3002 : Step(206): len = 696327, overlap = 55.625
+PHY-3002 : Step(207): len = 695212, overlap = 56.1562
+PHY-3002 : Step(208): len = 694586, overlap = 57.3125
+PHY-3002 : Step(209): len = 693301, overlap = 58.4375
+PHY-3002 : Step(210): len = 692621, overlap = 58.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000187631
+PHY-3002 : Step(211): len = 693939, overlap = 59
+PHY-3002 : Step(212): len = 697252, overlap = 57.2188
+PHY-3002 : Step(213): len = 703980, overlap = 50.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000375262
+PHY-3002 : Step(214): len = 705023, overlap = 50.7812
+PHY-3002 : Step(215): len = 714963, overlap = 48.3125
+PHY-3002 : Step(216): len = 732209, overlap = 36.8125
+PHY-3002 : Step(217): len = 730089, overlap = 31.8125
+PHY-3002 : Step(218): len = 726937, overlap = 29.8438
+PHY-3002 : Step(219): len = 725326, overlap = 31.9062
+PHY-3002 : Step(220): len = 723657, overlap = 32.0938
+PHY-3002 : Step(221): len = 723195, overlap = 32.75
+PHY-3002 : Step(222): len = 727823, overlap = 31.9375
+PHY-3002 : Step(223): len = 733627, overlap = 34.7188
+PHY-3002 : Step(224): len = 732227, overlap = 34.3438
+PHY-3002 : Step(225): len = 730189, overlap = 36.0625
+PHY-3002 : Step(226): len = 730111, overlap = 36.0625
+PHY-3002 : Step(227): len = 733390, overlap = 35.375
+PHY-3002 : Step(228): len = 736696, overlap = 30.8438
+PHY-3002 : Step(229): len = 736816, overlap = 28.0938
+PHY-3002 : Step(230): len = 736476, overlap = 30.4375
+PHY-3002 : Step(231): len = 737884, overlap = 31.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000750525
+PHY-3002 : Step(232): len = 741509, overlap = 30.2812
+PHY-3002 : Step(233): len = 746237, overlap = 29.7812
+PHY-3002 : Step(234): len = 750560, overlap = 32.3125
+PHY-3002 : Step(235): len = 755842, overlap = 31.2812
+PHY-3002 : Step(236): len = 758858, overlap = 28.125
+PHY-3002 : Step(237): len = 763391, overlap = 28.2188
+PHY-3002 : Step(238): len = 763253, overlap = 30.5938
+PHY-3002 : Step(239): len = 762743, overlap = 30.6875
+PHY-3002 : Step(240): len = 763921, overlap = 29.5625
+PHY-3002 : Step(241): len = 763449, overlap = 30.9375
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00138179
+PHY-3002 : Step(242): len = 764718, overlap = 30.8438
+PHY-3002 : Step(243): len = 768361, overlap = 31.0938
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 49/20429.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847856, over cnt = 2752(7%), over = 14578, worst = 65
+PHY-1001 : End global iterations;  1.630148s wall, 2.093750s user + 0.062500s system = 2.156250s CPU (132.3%)
+
+PHY-1001 : Congestion index: top1 = 110.71, top5 = 79.43, top10 = 67.56, top15 = 60.63.
+PHY-3001 : End congestion estimation;  1.918053s wall, 2.375000s user + 0.062500s system = 2.437500s CPU (127.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20251 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.959112s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012354
+PHY-3002 : Step(244): len = 767565, overlap = 273.906
+PHY-3002 : Step(245): len = 767944, overlap = 217.562
+PHY-3002 : Step(246): len = 759209, overlap = 190.031
+PHY-3002 : Step(247): len = 753673, overlap = 167.719
+PHY-3002 : Step(248): len = 744713, overlap = 148.531
+PHY-3002 : Step(249): len = 741560, overlap = 143.094
+PHY-3002 : Step(250): len = 735306, overlap = 145.781
+PHY-3002 : Step(251): len = 733338, overlap = 144.5
+PHY-3002 : Step(252): len = 729316, overlap = 138.25
+PHY-3002 : Step(253): len = 725136, overlap = 134.125
+PHY-3002 : Step(254): len = 720128, overlap = 133.031
+PHY-3002 : Step(255): len = 717141, overlap = 131.906
+PHY-3002 : Step(256): len = 712810, overlap = 132.469
+PHY-3002 : Step(257): len = 710016, overlap = 135.531
+PHY-3002 : Step(258): len = 708033, overlap = 132.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000247079
+PHY-3002 : Step(259): len = 707802, overlap = 130
+PHY-3002 : Step(260): len = 710392, overlap = 126.75
+PHY-3002 : Step(261): len = 713488, overlap = 119.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000494159
+PHY-3002 : Step(262): len = 718322, overlap = 111.25
+PHY-3002 : Step(263): len = 724829, overlap = 102
+PHY-3002 : Step(264): len = 728925, overlap = 93.4375
+PHY-3002 : Step(265): len = 728082, overlap = 92.5
+PHY-3002 : Step(266): len = 728204, overlap = 89.2812
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000980339
+PHY-3002 : Step(267): len = 730991, overlap = 85.0312
+PHY-3002 : Step(268): len = 737698, overlap = 79.9062
+PHY-3002 : Step(269): len = 745959, overlap = 74.8125
+PHY-3002 : Step(270): len = 748840, overlap = 69.6875
+PHY-3002 : Step(271): len = 747516, overlap = 70.0625
+PHY-3002 : Step(272): len = 745499, overlap = 69.3438
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85287, tnet num: 20251, tinst num: 17843, tnode num: 115752, tedge num: 136822.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.534225s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (99.8%)
+
+RUN-1004 : used memory is 582 MB, reserved memory is 565 MB, peak memory is 720 MB
+OPT-1001 : Total overflow 408.47 peak overflow 3.62
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 721/20429.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838976, over cnt = 3203(9%), over = 11876, worst = 37
+PHY-1001 : End global iterations;  1.482317s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (134.9%)
+
+PHY-1001 : Congestion index: top1 = 76.92, top5 = 62.10, top10 = 55.54, top15 = 51.31.
+PHY-1001 : End incremental global routing;  1.831638s wall, 2.328125s user + 0.015625s system = 2.343750s CPU (128.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20251 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.978748s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.6%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17708 has valid locations, 327 needs to be replaced
+PHY-3001 : design contains 18120 instances, 7558 luts, 9341 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 5933 pins
+PHY-3001 : Found 3510 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 768844
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16885/20706.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855744, over cnt = 3252(9%), over = 12021, worst = 37
+PHY-1001 : End global iterations;  0.275767s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (147.3%)
+
+PHY-1001 : Congestion index: top1 = 76.92, top5 = 62.23, top10 = 55.87, top15 = 51.77.
+PHY-3001 : End congestion estimation;  0.549080s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (122.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86428, tnet num: 20528, tinst num: 18120, tnode num: 117426, tedge num: 138550.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.603643s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (100.4%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 619 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20528 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.636123s wall, 2.609375s user + 0.031250s system = 2.640625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(273): len = 767283, overlap = 0.4375
+PHY-3002 : Step(274): len = 766726, overlap = 0.3125
+PHY-3002 : Step(275): len = 766302, overlap = 0.3125
+PHY-3002 : Step(276): len = 766005, overlap = 0.375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16990/20706.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 852064, over cnt = 3278(9%), over = 12053, worst = 37
+PHY-1001 : End global iterations;  0.214822s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (123.6%)
+
+PHY-1001 : Congestion index: top1 = 77.00, top5 = 62.64, top10 = 56.07, top15 = 51.89.
+PHY-3001 : End congestion estimation;  0.489274s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (111.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20528 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.227472s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000525761
+PHY-3002 : Step(277): len = 765775, overlap = 71.7188
+PHY-3002 : Step(278): len = 765688, overlap = 71.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00105152
+PHY-3002 : Step(279): len = 765870, overlap = 71.0938
+PHY-3002 : Step(280): len = 766236, overlap = 71.4688
+PHY-3001 : Final: Len = 766236, Over = 71.4688
+PHY-3001 : End incremental placement;  5.632914s wall, 5.765625s user + 0.093750s system = 5.859375s CPU (104.0%)
+
+OPT-1001 : Total overflow 414.50 peak overflow 3.62
+OPT-1001 : End high-fanout net optimization;  9.027248s wall, 9.765625s user + 0.125000s system = 9.890625s CPU (109.6%)
+
+OPT-1001 : Current memory(MB): used = 728, reserve = 715, peak = 744.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16935/20706.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855904, over cnt = 3234(9%), over = 11050, worst = 37
+PHY-1002 : len = 910288, over cnt = 2296(6%), over = 5694, worst = 31
+PHY-1002 : len = 953240, over cnt = 1026(2%), over = 2076, worst = 13
+PHY-1002 : len = 972672, over cnt = 437(1%), over = 756, worst = 12
+PHY-1002 : len = 984520, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.282746s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 61.40, top5 = 54.46, top10 = 50.75, top15 = 48.29.
+OPT-1001 : End congestion update;  2.574070s wall, 3.484375s user + 0.000000s system = 3.484375s CPU (135.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20528 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.886422s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.5%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 72 cells processed and 5750 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 21 cells processed and 1800 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 8 cells processed and 1900 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 5 cells processed and 1100 slack improved
+OPT-0007 : Iter 5: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 1 cells processed and 400 slack improved
+OPT-1001 : End global optimization;  3.510682s wall, 4.421875s user + 0.000000s system = 4.421875s CPU (126.0%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 695, peak = 744.
+OPT-1001 : End physical optimization;  15.015583s wall, 16.734375s user + 0.156250s system = 16.890625s CPU (112.5%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7558 LUT to BLE ...
+SYN-4008 : Packed 7558 LUT and 3127 SEQ to BLE.
+SYN-4003 : Packing 6214 remaining SEQ's ...
+SYN-4005 : Packed 4178 SEQ with LUT/SLICE
+SYN-4006 : 552 single LUT's are left
+SYN-4006 : 2036 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9594/13325 primitive instances ...
+PHY-3001 : End packing;  1.770708s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (98.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6676 instances
+RUN-1001 : 3264 mslices, 3264 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17710 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10152 nets have 2 pins
+RUN-1001 : 5732 nets have [3 - 5] pins
+RUN-1001 : 1152 nets have [6 - 10] pins
+RUN-1001 : 314 nets have [11 - 20] pins
+RUN-1001 : 329 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6674 instances, 6528 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3457 pins
+PHY-3001 : Found 1541 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 775905, Over = 232.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7290/17710.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930216, over cnt = 2031(5%), over = 3279, worst = 8
+PHY-1002 : len = 937184, over cnt = 1349(3%), over = 1965, worst = 8
+PHY-1002 : len = 948952, over cnt = 652(1%), over = 926, worst = 7
+PHY-1002 : len = 960712, over cnt = 112(0%), over = 149, worst = 5
+PHY-1002 : len = 963344, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.876920s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 62.03, top5 = 54.04, top10 = 49.99, top15 = 47.19.
+PHY-3001 : End congestion estimation;  2.323823s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (129.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73924, tnet num: 17532, tinst num: 6674, tnode num: 96429, tedge num: 123969.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.783670s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (99.9%)
+
+RUN-1004 : used memory is 618 MB, reserved memory is 611 MB, peak memory is 744 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17532 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.723475s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.17157e-05
+PHY-3002 : Step(281): len = 761806, overlap = 243.5
+PHY-3002 : Step(282): len = 753755, overlap = 245
+PHY-3002 : Step(283): len = 747632, overlap = 250.75
+PHY-3002 : Step(284): len = 742915, overlap = 254.5
+PHY-3002 : Step(285): len = 739121, overlap = 265
+PHY-3002 : Step(286): len = 734920, overlap = 275
+PHY-3002 : Step(287): len = 731536, overlap = 269.75
+PHY-3002 : Step(288): len = 728036, overlap = 276.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103431
+PHY-3002 : Step(289): len = 731807, overlap = 265
+PHY-3002 : Step(290): len = 736632, overlap = 251.75
+PHY-3002 : Step(291): len = 737179, overlap = 241.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000206863
+PHY-3002 : Step(292): len = 745505, overlap = 228
+PHY-3002 : Step(293): len = 751664, overlap = 225.25
+PHY-3002 : Step(294): len = 750345, overlap = 221
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.344741s wall, 0.406250s user + 0.609375s system = 1.015625s CPU (294.6%)
+
+PHY-3001 : Trial Legalized: Len = 902855
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 71%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 600/17710.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.01691e+06, over cnt = 2763(7%), over = 4726, worst = 8
+PHY-1002 : len = 1.03398e+06, over cnt = 1818(5%), over = 2676, worst = 8
+PHY-1002 : len = 1.0542e+06, over cnt = 758(2%), over = 1077, worst = 7
+PHY-1002 : len = 1.06811e+06, over cnt = 98(0%), over = 128, worst = 4
+PHY-1002 : len = 1.07143e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.934047s wall, 4.140625s user + 0.000000s system = 4.140625s CPU (141.1%)
+
+PHY-1001 : Congestion index: top1 = 63.49, top5 = 56.45, top10 = 52.63, top15 = 50.28.
+PHY-3001 : End congestion estimation;  3.450664s wall, 4.656250s user + 0.000000s system = 4.656250s CPU (134.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17532 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.013824s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000169146
+PHY-3002 : Step(295): len = 864624, overlap = 61.25
+PHY-3002 : Step(296): len = 841462, overlap = 94.5
+PHY-3002 : Step(297): len = 825466, overlap = 118.75
+PHY-3002 : Step(298): len = 818290, overlap = 134.5
+PHY-3002 : Step(299): len = 807316, overlap = 151.25
+PHY-3002 : Step(300): len = 800189, overlap = 167.5
+PHY-3002 : Step(301): len = 795829, overlap = 173
+PHY-3002 : Step(302): len = 791850, overlap = 173.25
+PHY-3002 : Step(303): len = 788474, overlap = 183.5
+PHY-3002 : Step(304): len = 785822, overlap = 188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000338292
+PHY-3002 : Step(305): len = 790216, overlap = 179.75
+PHY-3002 : Step(306): len = 792851, overlap = 173
+PHY-3002 : Step(307): len = 794409, overlap = 170.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000580538
+PHY-3002 : Step(308): len = 799575, overlap = 165
+PHY-3002 : Step(309): len = 802439, overlap = 163.5
+PHY-3002 : Step(310): len = 804698, overlap = 165.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.089422s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (104.8%)
+
+PHY-3001 : Legalized: Len = 860812, Over = 0
+PHY-3001 : Spreading special nets. 469 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.123816s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.0%)
+
+PHY-3001 : 706 instances has been re-located, deltaX = 267, deltaY = 471, maxDist = 8.
+PHY-3001 : Final: Len = 871916, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73924, tnet num: 17532, tinst num: 6677, tnode num: 96429, tedge num: 123969.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.981548s wall, 1.953125s user + 0.031250s system = 1.984375s CPU (100.1%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 655 MB, peak memory is 744 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3363/17710.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00018e+06, over cnt = 2731(7%), over = 4558, worst = 8
+PHY-1002 : len = 1.01439e+06, over cnt = 1791(5%), over = 2643, worst = 6
+PHY-1002 : len = 1.03431e+06, over cnt = 697(1%), over = 1044, worst = 6
+PHY-1002 : len = 1.04785e+06, over cnt = 151(0%), over = 204, worst = 5
+PHY-1002 : len = 1.05152e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.434318s wall, 3.500000s user + 0.015625s system = 3.515625s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 63.10, top5 = 55.93, top10 = 52.17, top15 = 49.78.
+PHY-1001 : End incremental global routing;  2.838836s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (138.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17532 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.944525s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (99.3%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6584 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 6697 instances, 6548 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3529 pins
+PHY-3001 : Found 1548 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 874891
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16254/17731.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05486e+06, over cnt = 69(0%), over = 76, worst = 4
+PHY-1002 : len = 1.05502e+06, over cnt = 33(0%), over = 34, worst = 2
+PHY-1002 : len = 1.05534e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.05548e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.644527s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 63.10, top5 = 55.93, top10 = 52.17, top15 = 49.79.
+PHY-3001 : End congestion estimation;  1.000551s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (104.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74102, tnet num: 17553, tinst num: 6697, tnode num: 96647, tedge num: 124179.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  2.059438s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (100.1%)
+
+RUN-1004 : used memory is 673 MB, reserved memory is 670 MB, peak memory is 744 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  3.011057s wall, 2.984375s user + 0.031250s system = 3.015625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(311): len = 873503, overlap = 0.75
+PHY-3002 : Step(312): len = 873388, overlap = 1
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16235/17731.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05298e+06, over cnt = 51(0%), over = 62, worst = 3
+PHY-1002 : len = 1.05306e+06, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 1.05329e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.05338e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.629711s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (104.2%)
+
+PHY-1001 : Congestion index: top1 = 63.10, top5 = 55.93, top10 = 52.16, top15 = 49.80.
+PHY-3001 : End congestion estimation;  0.974139s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (104.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.935178s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (98.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000169273
+PHY-3002 : Step(313): len = 873150, overlap = 2.75
+PHY-3002 : Step(314): len = 873301, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005778s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (270.4%)
+
+PHY-3001 : Legalized: Len = 873444, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.065647s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.2%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 7, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 873588, Over = 0
+PHY-3001 : End incremental placement;  6.433979s wall, 6.546875s user + 0.093750s system = 6.640625s CPU (103.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.746250s wall, 11.921875s user + 0.140625s system = 12.062500s CPU (112.2%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 746, peak = 756.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16229/17731.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0535e+06, over cnt = 44(0%), over = 57, worst = 4
+PHY-1002 : len = 1.05351e+06, over cnt = 23(0%), over = 30, worst = 3
+PHY-1002 : len = 1.05358e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.05362e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.635456s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 63.10, top5 = 55.93, top10 = 52.17, top15 = 49.79.
+OPT-1001 : End congestion update;  0.977385s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.779359s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.2%)
+
+OPT-0007 : Start: WNS -1736 TNS -2321 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6609 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6697 instances, 6548 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3529 pins
+PHY-3001 : Found 1548 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 876756, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.068091s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (114.7%)
+
+PHY-3001 : 38 instances has been re-located, deltaX = 21, deltaY = 20, maxDist = 3.
+PHY-3001 : Final: Len = 877356, Over = 0
+PHY-3001 : End incremental legalization;  0.417901s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (101.0%)
+
+OPT-0007 : Iter 1: improved WNS -1190 TNS -1775 NUM_FEPS 2 with 45 cells processed and 10221 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6609 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6697 instances, 6548 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1139 with 3529 pins
+PHY-3001 : Found 1548 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Initial: Len = 877644, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064584s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.8%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 3.
+PHY-3001 : Final: Len = 877724, Over = 0
+PHY-3001 : End incremental legalization;  0.413398s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.1%)
+
+OPT-0007 : Iter 2: improved WNS -1190 TNS -1775 NUM_FEPS 2 with 12 cells processed and 1041 slack improved
+OPT-0007 : Iter 3: improved WNS -1190 TNS -1775 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.890928s wall, 3.015625s user + 0.015625s system = 3.031250s CPU (104.9%)
+
+OPT-1001 : Current memory(MB): used = 752, reserve = 746, peak = 756.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.771124s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15983/17731.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05721e+06, over cnt = 199(0%), over = 231, worst = 3
+PHY-1002 : len = 1.05739e+06, over cnt = 108(0%), over = 113, worst = 2
+PHY-1002 : len = 1.05806e+06, over cnt = 41(0%), over = 42, worst = 2
+PHY-1002 : len = 1.05849e+06, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 1.05874e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.981033s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (108.3%)
+
+PHY-1001 : Congestion index: top1 = 63.99, top5 = 56.37, top10 = 52.46, top15 = 50.01.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.802071s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1340 TNS -1975 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 63.655172
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1340ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17731 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17731 nets
+OPT-1001 : End physical optimization;  18.944595s wall, 20.265625s user + 0.203125s system = 20.468750s CPU (108.0%)
+
+RUN-1003 : finish command "place" in  69.233628s wall, 108.593750s user + 6.484375s system = 115.078125s CPU (166.2%)
+
+RUN-1004 : used memory is 591 MB, reserved memory is 575 MB, peak memory is 756 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.780965s wall, 3.109375s user + 0.015625s system = 3.125000s CPU (175.5%)
+
+RUN-1004 : used memory is 591 MB, reserved memory is 576 MB, peak memory is 756 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6699 instances
+RUN-1001 : 3270 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17731 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10148 nets have 2 pins
+RUN-1001 : 5730 nets have [3 - 5] pins
+RUN-1001 : 1162 nets have [6 - 10] pins
+RUN-1001 : 322 nets have [11 - 20] pins
+RUN-1001 : 341 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74102, tnet num: 17553, tinst num: 6697, tnode num: 96647, tedge num: 124179.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.718691s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (100.0%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 612 MB, peak memory is 756 MB
+PHY-1001 : 3270 mslices, 3278 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 985936, over cnt = 2841(8%), over = 4764, worst = 8
+PHY-1002 : len = 1.0045e+06, over cnt = 1794(5%), over = 2649, worst = 7
+PHY-1002 : len = 1.02674e+06, over cnt = 696(1%), over = 965, worst = 6
+PHY-1002 : len = 1.04077e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.04114e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.260536s wall, 4.390625s user + 0.093750s system = 4.484375s CPU (137.5%)
+
+PHY-1001 : Congestion index: top1 = 63.90, top5 = 56.01, top10 = 52.07, top15 = 49.62.
+PHY-1001 : End global routing;  3.631349s wall, 4.750000s user + 0.109375s system = 4.859375s CPU (133.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 724, reserve = 723, peak = 756.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 995, reserve = 994, peak = 995.
+PHY-1001 : End build detailed router design. 4.290328s wall, 4.250000s user + 0.046875s system = 4.296875s CPU (100.2%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 272352, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.606733s wall, 5.578125s user + 0.031250s system = 5.609375s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 272408, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.613877s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1031, peak = 1031.
+PHY-1001 : End phase 1; 6.238301s wall, 6.203125s user + 0.031250s system = 6.234375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.53793e+06, over cnt = 1960(0%), over = 1963, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1049, peak = 1050.
+PHY-1001 : End initial routed; 49.383320s wall, 83.062500s user + 0.390625s system = 83.453125s CPU (169.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16654(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.470   |  -4.514   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.528239s wall, 3.484375s user + 0.015625s system = 3.500000s CPU (99.2%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1048, peak = 1054.
+PHY-1001 : End phase 2; 52.911620s wall, 86.546875s user + 0.406250s system = 86.953125s CPU (164.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.146ns STNS -4.190ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.151242s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.3%)
+
+PHY-1022 : len = 2.53793e+06, over cnt = 1963(0%), over = 1966, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.425781s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.50166e+06, over cnt = 697(0%), over = 698, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.736095s wall, 3.890625s user + 0.000000s system = 3.890625s CPU (142.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.50062e+06, over cnt = 164(0%), over = 164, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.138988s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (130.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.50187e+06, over cnt = 34(0%), over = 34, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.489852s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (127.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.50229e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.367625s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (110.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.227283s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (123.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.260676s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.9%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.289787s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (102.4%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.50233e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.215614s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.230307s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.257172s wall, 0.265625s user + 0.031250s system = 0.296875s CPU (115.4%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.273901s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (108.4%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.313523s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.50234e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.189959s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.50233e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.172836s wall, 0.187500s user + 0.046875s system = 0.234375s CPU (135.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16654(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.146   |  -4.190   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.528281s wall, 3.500000s user + 0.015625s system = 3.515625s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 678 feed throughs used by 502 nets
+PHY-1001 : End commit to database; 2.477876s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1161, reserve = 1163, peak = 1161.
+PHY-1001 : End phase 3; 14.028888s wall, 15.703125s user + 0.125000s system = 15.828125s CPU (112.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.146ns STNS -4.190ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.155660s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.4%)
+
+PHY-1022 : len = 2.50233e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.416283s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.146ns, -4.190ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16654(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.146   |  -4.190   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.559109s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 678 feed throughs used by 502 nets
+PHY-1001 : End commit to database; 2.536387s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1173, peak = 1170.
+PHY-1001 : End phase 4; 6.537985s wall, 6.515625s user + 0.015625s system = 6.531250s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.50233e+06
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1178, peak = 1175.
+PHY-1001 : End export database. 0.067338s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (116.0%)
+
+PHY-1001 : End detail routing;  84.508933s wall, 119.734375s user + 0.625000s system = 120.359375s CPU (142.4%)
+
+RUN-1003 : finish command "route" in  91.365668s wall, 127.703125s user + 0.750000s system = 128.453125s CPU (140.6%)
+
+RUN-1004 : used memory is 1045 MB, reserved memory is 1072 MB, peak memory is 1175 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10262   out of  19600   52.36%
+#reg                     9488   out of  19600   48.41%
+#le                     12219
+  #lut only              2731   out of  12219   22.35%
+  #reg only              1957   out of  12219   16.02%
+  #lut&reg               7531   out of  12219   61.63%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                                    Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                                      1806
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                                 1418
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                                1289
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                                      987
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0           134
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                                 71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                                71
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                                      24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                                      4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             ua_lvds_rx/reg8_syn_166.f1                                3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/u_ADconfig/reg_datain_31_16_b[6]_syn_19.f1    2
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                                     1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                                     1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                                     1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                                      1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P147       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P138       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P109       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12219  |9235    |1027    |9518    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |515    |401     |23      |437     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |95     |83      |4       |85      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |25     |25      |0       |17      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |759    |429     |96      |566     |0       |0       |
+|    u_ADconfig                |AD_config            |197    |148     |25      |149     |0       |0       |
+|    u_gen_sp                  |gen_sp               |262    |170     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |757    |500     |96      |557     |0       |0       |
+|    u_ADconfig                |AD_config            |185    |142     |25      |132     |0       |0       |
+|    u_gen_sp                  |gen_sp               |264    |165     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2967   |2325    |306     |2146    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |171    |127     |17      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2762   |2189    |289     |1978    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2296   |1840    |253     |1581    |22      |0       |
+|        channelPart           |channel_part_8478    |146    |143     |3       |135     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |1782   |1402    |197     |1175    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |226    |199     |27      |116     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|          insert              |insert               |988    |635     |170     |694     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |568    |568     |0       |365     |0       |0       |
+|        read_ram_i            |read_ram             |283    |231     |44      |202     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |224    |184     |40      |157     |0       |0       |
+|          read_ram_data       |read_ram_data        |57     |45      |4       |43      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |316    |238     |36      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3137   |2347    |349     |2186    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |194    |134     |17      |151     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2910   |2199    |332     |2002    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |1       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2435   |1826    |290     |1595    |22      |1       |
+|        channelPart           |channel_part_8478    |224    |221     |3       |146     |0       |0       |
+|        fifo_adc              |fifo_adc             |66     |57      |9       |46      |0       |1       |
+|        ram_switch            |ram_switch           |1752   |1258    |197     |1167    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |209    |182     |27      |114     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|          insert              |insert               |1008   |551     |170     |717     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |535    |525     |0       |336     |0       |0       |
+|        read_ram_i            |read_ram_rev         |370    |274     |81      |213     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |301    |219     |73      |162     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |69     |55      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10086  
+    #2         2       3811   
+    #3         3       1385   
+    #4         4        531   
+    #5        5-10     1216   
+    #6       11-50      579   
+    #7       51-100     27    
+    #8        >500       1    
+  Average     2.89            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.179633s wall, 3.796875s user + 0.000000s system = 3.796875s CPU (174.2%)
+
+RUN-1004 : used memory is 1047 MB, reserved memory is 1074 MB, peak memory is 1175 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74102, tnet num: 17553, tinst num: 6697, tnode num: 96647, tedge num: 124179.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.655307s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.1%)
+
+RUN-1004 : used memory is 1050 MB, reserved memory is 1077 MB, peak memory is 1175 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.634863s wall, 1.609375s user + 0.031250s system = 1.640625s CPU (100.4%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1117 MB, peak memory is 1175 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6697
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17731, pip num: 178079
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 678
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3230 valid insts, and 490907 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.592695s wall, 70.453125s user + 0.328125s system = 70.781250s CPU (668.2%)
+
+RUN-1004 : used memory is 1278 MB, reserved memory is 1275 MB, peak memory is 1392 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240311_171044.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_093249.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_093249.log
new file mode 100644
index 0000000..39f486e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_093249.log
@@ -0,0 +1,1914 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 09:32:49 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.134390s wall, 2.031250s user + 0.093750s system = 2.125000s CPU (99.6%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 314 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2947 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17649 instances
+RUN-0007 : 7383 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20227 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13303 nets have 2 pins
+RUN-1001 : 5510 nets have [3 - 5] pins
+RUN-1001 : 1003 nets have [6 - 10] pins
+RUN-1001 : 157 nets have [11 - 20] pins
+RUN-1001 : 180 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17647 instances, 7383 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84510, tnet num: 20049, tinst num: 17647, tnode num: 114588, tedge num: 135652.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.115322s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.9%)
+
+RUN-1004 : used memory is 535 MB, reserved memory is 512 MB, peak memory is 535 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20049 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.877878s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.8%)
+
+PHY-3001 : Found 3477 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.01702e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17647.
+PHY-3001 : Level 1 #clusters 2047.
+PHY-3001 : End clustering;  0.127037s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (123.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.23777e+06, overlap = 499.406
+PHY-3002 : Step(2): len = 1.17045e+06, overlap = 525.938
+PHY-3002 : Step(3): len = 810255, overlap = 643.562
+PHY-3002 : Step(4): len = 760617, overlap = 666.75
+PHY-3002 : Step(5): len = 593683, overlap = 775.031
+PHY-3002 : Step(6): len = 517800, overlap = 833.219
+PHY-3002 : Step(7): len = 451310, overlap = 910.594
+PHY-3002 : Step(8): len = 420278, overlap = 951.812
+PHY-3002 : Step(9): len = 379388, overlap = 1001.91
+PHY-3002 : Step(10): len = 349263, overlap = 1069
+PHY-3002 : Step(11): len = 321669, overlap = 1139.53
+PHY-3002 : Step(12): len = 281924, overlap = 1209.22
+PHY-3002 : Step(13): len = 263937, overlap = 1256.38
+PHY-3002 : Step(14): len = 246217, overlap = 1263.22
+PHY-3002 : Step(15): len = 222109, overlap = 1281.16
+PHY-3002 : Step(16): len = 205869, overlap = 1304.56
+PHY-3002 : Step(17): len = 184552, overlap = 1332.09
+PHY-3002 : Step(18): len = 174706, overlap = 1362.91
+PHY-3002 : Step(19): len = 157546, overlap = 1391.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.66554e-07
+PHY-3002 : Step(20): len = 156105, overlap = 1385.84
+PHY-3002 : Step(21): len = 185599, overlap = 1345.97
+PHY-3002 : Step(22): len = 187627, overlap = 1271.12
+PHY-3002 : Step(23): len = 188027, overlap = 1268.41
+PHY-3002 : Step(24): len = 184868, overlap = 1281.69
+PHY-3002 : Step(25): len = 184495, overlap = 1257.69
+PHY-3002 : Step(26): len = 181294, overlap = 1249
+PHY-3002 : Step(27): len = 179321, overlap = 1236.97
+PHY-3002 : Step(28): len = 175040, overlap = 1233.69
+PHY-3002 : Step(29): len = 174269, overlap = 1229.31
+PHY-3002 : Step(30): len = 172872, overlap = 1213.75
+PHY-3002 : Step(31): len = 171707, overlap = 1193.56
+PHY-3002 : Step(32): len = 169731, overlap = 1162.88
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.73311e-06
+PHY-3002 : Step(33): len = 172868, overlap = 1139.38
+PHY-3002 : Step(34): len = 188486, overlap = 1088.62
+PHY-3002 : Step(35): len = 195029, overlap = 1026.28
+PHY-3002 : Step(36): len = 199498, overlap = 1029.38
+PHY-3002 : Step(37): len = 200680, overlap = 1036.59
+PHY-3002 : Step(38): len = 201095, overlap = 1017.72
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.46621e-06
+PHY-3002 : Step(39): len = 209518, overlap = 976.469
+PHY-3002 : Step(40): len = 223779, overlap = 949.125
+PHY-3002 : Step(41): len = 231095, overlap = 946.406
+PHY-3002 : Step(42): len = 235842, overlap = 933.406
+PHY-3002 : Step(43): len = 237788, overlap = 945.25
+PHY-3002 : Step(44): len = 238947, overlap = 922.062
+PHY-3002 : Step(45): len = 238854, overlap = 935.688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.93243e-06
+PHY-3002 : Step(46): len = 253599, overlap = 880.469
+PHY-3002 : Step(47): len = 281272, overlap = 752.344
+PHY-3002 : Step(48): len = 296085, overlap = 718.969
+PHY-3002 : Step(49): len = 304380, overlap = 673.312
+PHY-3002 : Step(50): len = 304001, overlap = 654.094
+PHY-3002 : Step(51): len = 303957, overlap = 651.656
+PHY-3002 : Step(52): len = 299720, overlap = 616.688
+PHY-3002 : Step(53): len = 299400, overlap = 606.938
+PHY-3002 : Step(54): len = 296093, overlap = 608.75
+PHY-3002 : Step(55): len = 296316, overlap = 604.219
+PHY-3002 : Step(56): len = 293846, overlap = 616.156
+PHY-3002 : Step(57): len = 293473, overlap = 633.188
+PHY-3002 : Step(58): len = 291612, overlap = 660.125
+PHY-3002 : Step(59): len = 290683, overlap = 666.25
+PHY-3002 : Step(60): len = 287898, overlap = 680.094
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.38649e-05
+PHY-3002 : Step(61): len = 307397, overlap = 627.531
+PHY-3002 : Step(62): len = 329350, overlap = 539.562
+PHY-3002 : Step(63): len = 337207, overlap = 485.375
+PHY-3002 : Step(64): len = 338653, overlap = 462.438
+PHY-3002 : Step(65): len = 336439, overlap = 459.438
+PHY-3002 : Step(66): len = 336339, overlap = 453.656
+PHY-3002 : Step(67): len = 333801, overlap = 459.344
+PHY-3002 : Step(68): len = 333890, overlap = 451.219
+PHY-3002 : Step(69): len = 332491, overlap = 438.312
+PHY-3002 : Step(70): len = 332760, overlap = 437.969
+PHY-3002 : Step(71): len = 332204, overlap = 452.594
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.77297e-05
+PHY-3002 : Step(72): len = 354997, overlap = 409.156
+PHY-3002 : Step(73): len = 371011, overlap = 377.812
+PHY-3002 : Step(74): len = 370480, overlap = 363.375
+PHY-3002 : Step(75): len = 371275, overlap = 337
+PHY-3002 : Step(76): len = 373898, overlap = 336
+PHY-3002 : Step(77): len = 375623, overlap = 340.344
+PHY-3002 : Step(78): len = 373614, overlap = 335.531
+PHY-3002 : Step(79): len = 373441, overlap = 350.5
+PHY-3002 : Step(80): len = 372737, overlap = 345.188
+PHY-3002 : Step(81): len = 372537, overlap = 327.969
+PHY-3002 : Step(82): len = 371131, overlap = 335.688
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.54594e-05
+PHY-3002 : Step(83): len = 389729, overlap = 314.969
+PHY-3002 : Step(84): len = 402136, overlap = 294.219
+PHY-3002 : Step(85): len = 402691, overlap = 283.969
+PHY-3002 : Step(86): len = 404425, overlap = 274.969
+PHY-3002 : Step(87): len = 408398, overlap = 263.375
+PHY-3002 : Step(88): len = 413132, overlap = 252.031
+PHY-3002 : Step(89): len = 412209, overlap = 253.812
+PHY-3002 : Step(90): len = 414693, overlap = 251.812
+PHY-3002 : Step(91): len = 416297, overlap = 249.469
+PHY-3002 : Step(92): len = 417429, overlap = 232.219
+PHY-3002 : Step(93): len = 416155, overlap = 231
+PHY-3002 : Step(94): len = 416631, overlap = 226.938
+PHY-3002 : Step(95): len = 418286, overlap = 229.531
+PHY-3002 : Step(96): len = 419393, overlap = 228.938
+PHY-3002 : Step(97): len = 417379, overlap = 233.094
+PHY-3002 : Step(98): len = 417448, overlap = 236.656
+PHY-3002 : Step(99): len = 418264, overlap = 235.844
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000110919
+PHY-3002 : Step(100): len = 434431, overlap = 226.406
+PHY-3002 : Step(101): len = 444520, overlap = 214.25
+PHY-3002 : Step(102): len = 446610, overlap = 220.219
+PHY-3002 : Step(103): len = 448528, overlap = 215.875
+PHY-3002 : Step(104): len = 450055, overlap = 209.531
+PHY-3002 : Step(105): len = 451616, overlap = 217.906
+PHY-3002 : Step(106): len = 450127, overlap = 211.375
+PHY-3002 : Step(107): len = 450794, overlap = 196.781
+PHY-3002 : Step(108): len = 452054, overlap = 208.594
+PHY-3002 : Step(109): len = 452874, overlap = 204.438
+PHY-3002 : Step(110): len = 451591, overlap = 213.875
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000219919
+PHY-3002 : Step(111): len = 461242, overlap = 201.531
+PHY-3002 : Step(112): len = 467918, overlap = 191
+PHY-3002 : Step(113): len = 468156, overlap = 190.406
+PHY-3002 : Step(114): len = 469313, overlap = 181.094
+PHY-3002 : Step(115): len = 473203, overlap = 180.125
+PHY-3002 : Step(116): len = 475709, overlap = 181.406
+PHY-3002 : Step(117): len = 474476, overlap = 182.094
+PHY-3002 : Step(118): len = 474741, overlap = 182.656
+PHY-3002 : Step(119): len = 476378, overlap = 185.438
+PHY-3002 : Step(120): len = 477262, overlap = 181.188
+PHY-3002 : Step(121): len = 476142, overlap = 179.812
+PHY-3002 : Step(122): len = 476124, overlap = 181.812
+PHY-3002 : Step(123): len = 477645, overlap = 184.438
+PHY-3002 : Step(124): len = 478298, overlap = 184.031
+PHY-3002 : Step(125): len = 477115, overlap = 186.156
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000410252
+PHY-3002 : Step(126): len = 484112, overlap = 178.844
+PHY-3002 : Step(127): len = 491263, overlap = 169.875
+PHY-3002 : Step(128): len = 492181, overlap = 168.031
+PHY-3002 : Step(129): len = 493610, overlap = 166.188
+PHY-3002 : Step(130): len = 497119, overlap = 161.625
+PHY-3002 : Step(131): len = 499529, overlap = 164.75
+PHY-3002 : Step(132): len = 498658, overlap = 163.469
+PHY-3002 : Step(133): len = 498642, overlap = 160.438
+PHY-3002 : Step(134): len = 501494, overlap = 152.562
+PHY-3002 : Step(135): len = 503700, overlap = 145.188
+PHY-3002 : Step(136): len = 502281, overlap = 147.344
+PHY-3002 : Step(137): len = 501394, overlap = 146.156
+PHY-3002 : Step(138): len = 502884, overlap = 143.25
+PHY-3002 : Step(139): len = 504297, overlap = 137.844
+PHY-3002 : Step(140): len = 503096, overlap = 140.375
+PHY-3002 : Step(141): len = 502572, overlap = 138.031
+PHY-3002 : Step(142): len = 503609, overlap = 142
+PHY-3002 : Step(143): len = 504348, overlap = 144.688
+PHY-3002 : Step(144): len = 503109, overlap = 144.156
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000747339
+PHY-3002 : Step(145): len = 507664, overlap = 140.906
+PHY-3002 : Step(146): len = 514212, overlap = 139.125
+PHY-3002 : Step(147): len = 515518, overlap = 130.062
+PHY-3002 : Step(148): len = 516711, overlap = 127.625
+PHY-3002 : Step(149): len = 518224, overlap = 128.875
+PHY-3002 : Step(150): len = 519111, overlap = 130.562
+PHY-3002 : Step(151): len = 518470, overlap = 132.562
+PHY-3002 : Step(152): len = 518470, overlap = 130.312
+PHY-3002 : Step(153): len = 519346, overlap = 135.094
+PHY-3002 : Step(154): len = 520068, overlap = 135.406
+PHY-3002 : Step(155): len = 519666, overlap = 133
+PHY-3002 : Step(156): len = 519674, overlap = 132.375
+PHY-3002 : Step(157): len = 520506, overlap = 131.25
+PHY-3002 : Step(158): len = 521020, overlap = 132.062
+PHY-3002 : Step(159): len = 520386, overlap = 135.281
+PHY-3002 : Step(160): len = 520148, overlap = 138.906
+PHY-3002 : Step(161): len = 520601, overlap = 133.625
+PHY-3002 : Step(162): len = 522030, overlap = 133.781
+PHY-3002 : Step(163): len = 521382, overlap = 135.062
+PHY-3002 : Step(164): len = 521237, overlap = 138.625
+PHY-3002 : Step(165): len = 521644, overlap = 137.094
+PHY-3002 : Step(166): len = 521821, overlap = 138.812
+PHY-3002 : Step(167): len = 521532, overlap = 135.688
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014243s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (109.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20227.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 682696, over cnt = 1509(4%), over = 7593, worst = 46
+PHY-1001 : End global iterations;  0.681627s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (151.3%)
+
+PHY-1001 : Congestion index: top1 = 86.36, top5 = 63.10, top10 = 52.72, top15 = 46.77.
+PHY-3001 : End congestion estimation;  0.904480s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (138.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20049 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868085s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.67013e-05
+PHY-3002 : Step(168): len = 619096, overlap = 80.9375
+PHY-3002 : Step(169): len = 623813, overlap = 80.1562
+PHY-3002 : Step(170): len = 619188, overlap = 81.0312
+PHY-3002 : Step(171): len = 618982, overlap = 83.8125
+PHY-3002 : Step(172): len = 627755, overlap = 79.6875
+PHY-3002 : Step(173): len = 642129, overlap = 73.375
+PHY-3002 : Step(174): len = 645657, overlap = 74.9062
+PHY-3002 : Step(175): len = 649800, overlap = 81.5312
+PHY-3002 : Step(176): len = 657492, overlap = 89.2812
+PHY-3002 : Step(177): len = 660523, overlap = 89.8125
+PHY-3002 : Step(178): len = 662138, overlap = 83.4062
+PHY-3002 : Step(179): len = 663465, overlap = 78.6875
+PHY-3002 : Step(180): len = 667638, overlap = 71.2188
+PHY-3002 : Step(181): len = 667678, overlap = 70.25
+PHY-3002 : Step(182): len = 667345, overlap = 69.3125
+PHY-3002 : Step(183): len = 670121, overlap = 66.5
+PHY-3002 : Step(184): len = 669792, overlap = 64
+PHY-3002 : Step(185): len = 668918, overlap = 59.9062
+PHY-3002 : Step(186): len = 669342, overlap = 59.3438
+PHY-3002 : Step(187): len = 668183, overlap = 60.0312
+PHY-3002 : Step(188): len = 667267, overlap = 66.9688
+PHY-3002 : Step(189): len = 667200, overlap = 70.9062
+PHY-3002 : Step(190): len = 665573, overlap = 68.1875
+PHY-3002 : Step(191): len = 665288, overlap = 69.2188
+PHY-3002 : Step(192): len = 666141, overlap = 67.5938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000193403
+PHY-3002 : Step(193): len = 668125, overlap = 65.7188
+PHY-3002 : Step(194): len = 671216, overlap = 63.6875
+PHY-3002 : Step(195): len = 672646, overlap = 63.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.0003257
+PHY-3002 : Step(196): len = 677958, overlap = 64.0312
+PHY-3002 : Step(197): len = 690954, overlap = 63.1562
+PHY-3002 : Step(198): len = 696266, overlap = 61.1562
+PHY-3002 : Step(199): len = 700220, overlap = 60.75
+PHY-3002 : Step(200): len = 701983, overlap = 62.7812
+PHY-3002 : Step(201): len = 703873, overlap = 64.9062
+PHY-3002 : Step(202): len = 704439, overlap = 66.5
+PHY-3002 : Step(203): len = 706350, overlap = 67.5625
+PHY-3002 : Step(204): len = 703653, overlap = 62.5625
+PHY-3002 : Step(205): len = 702703, overlap = 59.25
+PHY-3002 : Step(206): len = 700905, overlap = 56.5625
+PHY-3002 : Step(207): len = 700938, overlap = 56.4062
+PHY-3002 : Step(208): len = 698909, overlap = 55.1875
+PHY-3002 : Step(209): len = 698288, overlap = 54.4062
+PHY-3002 : Step(210): len = 697435, overlap = 51.0938
+PHY-3002 : Step(211): len = 698127, overlap = 51.1562
+PHY-3002 : Step(212): len = 700410, overlap = 50.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000651401
+PHY-3002 : Step(213): len = 700871, overlap = 50.5312
+PHY-3002 : Step(214): len = 710947, overlap = 47.0938
+PHY-3002 : Step(215): len = 724360, overlap = 45.2188
+PHY-3002 : Step(216): len = 729862, overlap = 47.6875
+PHY-3002 : Step(217): len = 730665, overlap = 44
+PHY-3002 : Step(218): len = 730042, overlap = 45.5625
+PHY-3002 : Step(219): len = 732850, overlap = 42.5625
+PHY-3002 : Step(220): len = 734360, overlap = 47.3438
+PHY-3002 : Step(221): len = 737628, overlap = 45.75
+PHY-3002 : Step(222): len = 737014, overlap = 44.5938
+PHY-3002 : Step(223): len = 737523, overlap = 41.5938
+PHY-3002 : Step(224): len = 739099, overlap = 36.6562
+PHY-3002 : Step(225): len = 737818, overlap = 34.8125
+PHY-3002 : Step(226): len = 738410, overlap = 33.375
+PHY-3002 : Step(227): len = 739520, overlap = 33.0312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.0012764
+PHY-3002 : Step(228): len = 741302, overlap = 32
+PHY-3002 : Step(229): len = 743943, overlap = 32.5
+PHY-3002 : Step(230): len = 748987, overlap = 31.1562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 63/20227.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 837200, over cnt = 2939(8%), over = 14819, worst = 92
+PHY-1001 : End global iterations;  1.505583s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (130.8%)
+
+PHY-1001 : Congestion index: top1 = 117.72, top5 = 79.57, top10 = 67.01, top15 = 60.04.
+PHY-3001 : End congestion estimation;  1.768646s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (126.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20049 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.881755s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000129378
+PHY-3002 : Step(231): len = 747800, overlap = 232.406
+PHY-3002 : Step(232): len = 751510, overlap = 185.688
+PHY-3002 : Step(233): len = 740762, overlap = 162.031
+PHY-3002 : Step(234): len = 735720, overlap = 147.875
+PHY-3002 : Step(235): len = 729862, overlap = 138.188
+PHY-3002 : Step(236): len = 724832, overlap = 124.656
+PHY-3002 : Step(237): len = 718701, overlap = 126.906
+PHY-3002 : Step(238): len = 714674, overlap = 120.25
+PHY-3002 : Step(239): len = 709151, overlap = 112.594
+PHY-3002 : Step(240): len = 704434, overlap = 110.281
+PHY-3002 : Step(241): len = 700381, overlap = 110.062
+PHY-3002 : Step(242): len = 695413, overlap = 111.656
+PHY-3002 : Step(243): len = 693703, overlap = 116
+PHY-3002 : Step(244): len = 689471, overlap = 116.312
+PHY-3002 : Step(245): len = 687463, overlap = 119
+PHY-3002 : Step(246): len = 685977, overlap = 120.219
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000258756
+PHY-3002 : Step(247): len = 687021, overlap = 115.844
+PHY-3002 : Step(248): len = 691394, overlap = 110.562
+PHY-3002 : Step(249): len = 695292, overlap = 105.531
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000517512
+PHY-3002 : Step(250): len = 698705, overlap = 98.5938
+PHY-3002 : Step(251): len = 706350, overlap = 86.25
+PHY-3002 : Step(252): len = 713684, overlap = 77.2812
+PHY-3002 : Step(253): len = 711376, overlap = 78.5
+PHY-3002 : Step(254): len = 710029, overlap = 77
+PHY-3002 : Step(255): len = 709418, overlap = 78.375
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84510, tnet num: 20049, tinst num: 17647, tnode num: 114588, tedge num: 135652.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.444964s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.6%)
+
+RUN-1004 : used memory is 580 MB, reserved memory is 562 MB, peak memory is 715 MB
+OPT-1001 : Total overflow 415.16 peak overflow 3.47
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 689/20227.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808328, over cnt = 3152(8%), over = 12401, worst = 67
+PHY-1001 : End global iterations;  1.275664s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 86.25, top5 = 65.00, top10 = 56.92, top15 = 52.21.
+PHY-1001 : End incremental global routing;  1.596456s wall, 2.140625s user + 0.000000s system = 2.140625s CPU (134.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20049 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.910299s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.6%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17513 has valid locations, 335 needs to be replaced
+PHY-3001 : design contains 17933 instances, 7484 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6022 pins
+PHY-3001 : Found 3512 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 732263
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16565/20513.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 823344, over cnt = 3230(9%), over = 12385, worst = 67
+PHY-1001 : End global iterations;  0.232506s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (161.3%)
+
+PHY-1001 : Congestion index: top1 = 85.93, top5 = 65.05, top10 = 57.00, top15 = 52.48.
+PHY-3001 : End congestion estimation;  0.472434s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (129.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85668, tnet num: 20335, tinst num: 17933, tnode num: 116320, tedge num: 137396.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.416958s wall, 1.375000s user + 0.046875s system = 1.421875s CPU (100.3%)
+
+RUN-1004 : used memory is 638 MB, reserved memory is 632 MB, peak memory is 720 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20335 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.354370s wall, 2.296875s user + 0.062500s system = 2.359375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(256): len = 731418, overlap = 1.1875
+PHY-3002 : Step(257): len = 730992, overlap = 1.125
+PHY-3002 : Step(258): len = 730697, overlap = 1.125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16685/20513.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 821584, over cnt = 3262(9%), over = 12519, worst = 67
+PHY-1001 : End global iterations;  0.194000s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (161.1%)
+
+PHY-1001 : Congestion index: top1 = 86.75, top5 = 65.54, top10 = 57.35, top15 = 52.79.
+PHY-3001 : End congestion estimation;  0.441440s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (127.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20335 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.314747s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000468259
+PHY-3002 : Step(259): len = 730698, overlap = 81.4375
+PHY-3002 : Step(260): len = 730711, overlap = 81.2188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000936518
+PHY-3002 : Step(261): len = 730672, overlap = 80.9375
+PHY-3002 : Step(262): len = 731239, overlap = 80.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00182446
+PHY-3002 : Step(263): len = 731480, overlap = 80.5
+PHY-3002 : Step(264): len = 732309, overlap = 80.5938
+PHY-3001 : Final: Len = 732309, Over = 80.5938
+PHY-3001 : End incremental placement;  5.262567s wall, 5.343750s user + 0.328125s system = 5.671875s CPU (107.8%)
+
+OPT-1001 : Total overflow 420.91 peak overflow 3.47
+OPT-1001 : End high-fanout net optimization;  8.289842s wall, 9.000000s user + 0.343750s system = 9.343750s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 723, reserve = 711, peak = 740.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16603/20513.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 824800, over cnt = 3191(9%), over = 11460, worst = 67
+PHY-1002 : len = 884560, over cnt = 2272(6%), over = 5894, worst = 31
+PHY-1002 : len = 924768, over cnt = 969(2%), over = 2465, worst = 20
+PHY-1002 : len = 944192, over cnt = 436(1%), over = 1066, worst = 20
+PHY-1002 : len = 959856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.024475s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (135.1%)
+
+PHY-1001 : Congestion index: top1 = 63.38, top5 = 55.65, top10 = 51.28, top15 = 48.44.
+OPT-1001 : End congestion update;  2.283574s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (130.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20335 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.781945s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1068 TNS -1578 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 72 cells processed and 5326 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 26 cells processed and 850 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 7 cells processed and 400 slack improved
+OPT-1001 : End global optimization;  3.108369s wall, 3.812500s user + 0.000000s system = 3.812500s CPU (122.7%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 694, peak = 740.
+OPT-1001 : End physical optimization;  13.447651s wall, 14.843750s user + 0.359375s system = 15.203125s CPU (113.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7484 LUT to BLE ...
+SYN-4008 : Packed 7484 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6095 remaining SEQ's ...
+SYN-4005 : Packed 3957 SEQ with LUT/SLICE
+SYN-4006 : 693 single LUT's are left
+SYN-4006 : 2138 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9622/13353 primitive instances ...
+PHY-3001 : End packing;  1.535250s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6699 instances
+RUN-1001 : 3276 mslices, 3275 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17508 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9949 nets have 2 pins
+RUN-1001 : 5768 nets have [3 - 5] pins
+RUN-1001 : 1113 nets have [6 - 10] pins
+RUN-1001 : 309 nets have [11 - 20] pins
+RUN-1001 : 338 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6697 instances, 6551 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3524 pins
+PHY-3001 : Found 1555 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : After packing: Len = 740787, Over = 244.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7360/17508.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899448, over cnt = 2015(5%), over = 3354, worst = 8
+PHY-1002 : len = 907360, over cnt = 1296(3%), over = 1846, worst = 8
+PHY-1002 : len = 917712, over cnt = 700(1%), over = 942, worst = 8
+PHY-1002 : len = 926904, over cnt = 296(0%), over = 385, worst = 4
+PHY-1002 : len = 932936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.714739s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (135.8%)
+
+PHY-1001 : Congestion index: top1 = 62.09, top5 = 54.36, top10 = 49.78, top15 = 46.96.
+PHY-3001 : End congestion estimation;  2.095048s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (129.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73452, tnet num: 17330, tinst num: 6697, tnode num: 95766, tedge num: 123337.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.596210s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (99.8%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 607 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17330 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.456932s wall, 2.437500s user + 0.015625s system = 2.453125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.74419e-05
+PHY-3002 : Step(265): len = 729315, overlap = 242.5
+PHY-3002 : Step(266): len = 722672, overlap = 238
+PHY-3002 : Step(267): len = 717684, overlap = 240.25
+PHY-3002 : Step(268): len = 713718, overlap = 254.5
+PHY-3002 : Step(269): len = 709813, overlap = 263
+PHY-3002 : Step(270): len = 706813, overlap = 269.75
+PHY-3002 : Step(271): len = 703821, overlap = 266
+PHY-3002 : Step(272): len = 700438, overlap = 264
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.48838e-05
+PHY-3002 : Step(273): len = 702642, overlap = 258.25
+PHY-3002 : Step(274): len = 707299, overlap = 247
+PHY-3002 : Step(275): len = 709359, overlap = 237.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000189768
+PHY-3002 : Step(276): len = 715375, overlap = 226.75
+PHY-3002 : Step(277): len = 722621, overlap = 214.5
+PHY-3002 : Step(278): len = 722999, overlap = 212.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.344551s wall, 0.343750s user + 0.515625s system = 0.859375s CPU (249.4%)
+
+PHY-3001 : Trial Legalized: Len = 917908
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 698/17508.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04114e+06, over cnt = 2868(8%), over = 4809, worst = 7
+PHY-1002 : len = 1.05977e+06, over cnt = 1804(5%), over = 2610, worst = 6
+PHY-1002 : len = 1.07797e+06, over cnt = 848(2%), over = 1188, worst = 5
+PHY-1002 : len = 1.08227e+06, over cnt = 651(1%), over = 908, worst = 5
+PHY-1002 : len = 1.09595e+06, over cnt = 55(0%), over = 66, worst = 3
+PHY-1001 : End global iterations;  2.809723s wall, 3.921875s user + 0.000000s system = 3.921875s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 69.48, top5 = 60.73, top10 = 55.89, top15 = 52.87.
+PHY-3001 : End congestion estimation;  3.253396s wall, 4.359375s user + 0.000000s system = 4.359375s CPU (134.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17330 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.136672s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000169607
+PHY-3002 : Step(279): len = 871148, overlap = 74.5
+PHY-3002 : Step(280): len = 847216, overlap = 94.25
+PHY-3002 : Step(281): len = 830489, overlap = 119.25
+PHY-3002 : Step(282): len = 816974, overlap = 140.5
+PHY-3002 : Step(283): len = 807356, overlap = 155
+PHY-3002 : Step(284): len = 800206, overlap = 160.5
+PHY-3002 : Step(285): len = 793344, overlap = 173.25
+PHY-3002 : Step(286): len = 789843, overlap = 178.75
+PHY-3002 : Step(287): len = 785956, overlap = 179
+PHY-3002 : Step(288): len = 781995, overlap = 184.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000339214
+PHY-3002 : Step(289): len = 787534, overlap = 177.5
+PHY-3002 : Step(290): len = 790179, overlap = 180.25
+PHY-3002 : Step(291): len = 791924, overlap = 178.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000569792
+PHY-3002 : Step(292): len = 797200, overlap = 174.5
+PHY-3002 : Step(293): len = 801090, overlap = 172.75
+PHY-3002 : Step(294): len = 803458, overlap = 168.5
+PHY-3002 : Step(295): len = 804443, overlap = 169.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.083558s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (112.2%)
+
+PHY-3001 : Legalized: Len = 860171, Over = 0
+PHY-3001 : Spreading special nets. 445 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.115220s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (108.5%)
+
+PHY-3001 : 662 instances has been re-located, deltaX = 284, deltaY = 407, maxDist = 13.
+PHY-3001 : Final: Len = 871405, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73452, tnet num: 17330, tinst num: 6700, tnode num: 95766, tedge num: 123337.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.803908s wall, 1.750000s user + 0.015625s system = 1.765625s CPU (97.9%)
+
+RUN-1004 : used memory is 635 MB, reserved memory is 644 MB, peak memory is 740 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3200/17508.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0055e+06, over cnt = 2657(7%), over = 4354, worst = 8
+PHY-1002 : len = 1.01929e+06, over cnt = 1669(4%), over = 2429, worst = 7
+PHY-1002 : len = 1.04007e+06, over cnt = 602(1%), over = 854, worst = 7
+PHY-1002 : len = 1.04916e+06, over cnt = 215(0%), over = 303, worst = 5
+PHY-1002 : len = 1.05519e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.183559s wall, 3.000000s user + 0.078125s system = 3.078125s CPU (141.0%)
+
+PHY-1001 : Congestion index: top1 = 67.48, top5 = 58.21, top10 = 53.48, top15 = 50.56.
+PHY-1001 : End incremental global routing;  2.562666s wall, 3.390625s user + 0.078125s system = 3.468750s CPU (135.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17330 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.882826s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.9%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6607 has valid locations, 24 needs to be replaced
+PHY-3001 : design contains 6719 instances, 6570 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3602 pins
+PHY-3001 : Found 1560 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 873414
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15959/17531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05686e+06, over cnt = 68(0%), over = 69, worst = 2
+PHY-1002 : len = 1.05698e+06, over cnt = 30(0%), over = 30, worst = 1
+PHY-1002 : len = 1.05722e+06, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 1.05734e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.05738e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.747445s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (102.4%)
+
+PHY-1001 : Congestion index: top1 = 67.50, top5 = 58.20, top10 = 53.50, top15 = 50.57.
+PHY-3001 : End congestion estimation;  1.052377s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (102.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73581, tnet num: 17353, tinst num: 6719, tnode num: 95940, tedge num: 123507.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.883739s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (99.5%)
+
+RUN-1004 : used memory is 669 MB, reserved memory is 668 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.746856s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(296): len = 872852, overlap = 0
+PHY-3002 : Step(297): len = 872553, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15956/17531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05604e+06, over cnt = 36(0%), over = 38, worst = 2
+PHY-1002 : len = 1.05612e+06, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 1.05633e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.411685s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.5%)
+
+PHY-1001 : Congestion index: top1 = 67.50, top5 = 58.20, top10 = 53.47, top15 = 50.55.
+PHY-3001 : End congestion estimation;  0.710951s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (103.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.988569s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000130302
+PHY-3002 : Step(298): len = 872615, overlap = 2
+PHY-3002 : Step(299): len = 872615, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005556s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 872742, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.056892s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.4%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 4, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 872708, Over = 0
+PHY-3001 : End incremental placement;  5.948035s wall, 6.031250s user + 0.078125s system = 6.109375s CPU (102.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.876967s wall, 10.765625s user + 0.171875s system = 10.937500s CPU (110.7%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 742, peak = 753.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15925/17531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05648e+06, over cnt = 53(0%), over = 59, worst = 2
+PHY-1002 : len = 1.05658e+06, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 1.05676e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.05682e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.05684e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.761647s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (110.8%)
+
+PHY-1001 : Congestion index: top1 = 67.50, top5 = 58.19, top10 = 53.48, top15 = 50.56.
+OPT-1001 : End congestion update;  1.070297s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (106.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.710479s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.2%)
+
+OPT-0007 : Start: WNS -1236 TNS -2000 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6631 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6719 instances, 6570 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3602 pins
+PHY-3001 : Found 1560 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 876076, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062676s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.7%)
+
+PHY-3001 : 27 instances has been re-located, deltaX = 10, deltaY = 17, maxDist = 2.
+PHY-3001 : Final: Len = 876438, Over = 0
+PHY-3001 : End incremental legalization;  0.660679s wall, 0.343750s user + 0.015625s system = 0.359375s CPU (54.4%)
+
+OPT-0007 : Iter 1: improved WNS -1236 TNS -1721 NUM_FEPS 2 with 43 cells processed and 11700 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6631 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6719 instances, 6570 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3602 pins
+PHY-3001 : Found 1560 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 878588, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.057995s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.8%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 8, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 878662, Over = 0
+PHY-3001 : End incremental legalization;  0.360261s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (156.1%)
+
+OPT-0007 : Iter 2: improved WNS -1236 TNS -1721 NUM_FEPS 2 with 21 cells processed and 4664 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6631 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6719 instances, 6570 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3602 pins
+PHY-3001 : Found 1560 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 878544, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.056541s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (82.9%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 8, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 878532, Over = 0
+PHY-3001 : End incremental legalization;  0.359197s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.0%)
+
+OPT-0007 : Iter 3: improved WNS -1236 TNS -1721 NUM_FEPS 2 with 10 cells processed and 100 slack improved
+OPT-1001 : End path based optimization;  3.581313s wall, 3.562500s user + 0.062500s system = 3.625000s CPU (101.2%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 742, peak = 753.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.762665s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15703/17531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06226e+06, over cnt = 172(0%), over = 215, worst = 5
+PHY-1002 : len = 1.06231e+06, over cnt = 105(0%), over = 117, worst = 5
+PHY-1002 : len = 1.06281e+06, over cnt = 49(0%), over = 53, worst = 2
+PHY-1002 : len = 1.06326e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.06346e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.812613s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (117.3%)
+
+PHY-1001 : Congestion index: top1 = 66.75, top5 = 57.82, top10 = 53.27, top15 = 50.50.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.711611s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (98.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1236 TNS -1771 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 66.344828
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1236ps with logic level 2 
+RUN-1001 :       #2 path slack -1190ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17531 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17531 nets
+OPT-1001 : End physical optimization;  18.231443s wall, 19.109375s user + 0.296875s system = 19.406250s CPU (106.4%)
+
+RUN-1003 : finish command "place" in  62.570512s wall, 98.578125s user + 5.828125s system = 104.406250s CPU (166.9%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 611 MB, peak memory is 753 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.672431s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (175.6%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 612 MB, peak memory is 753 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6721 instances
+RUN-1001 : 3290 mslices, 3280 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17531 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9954 nets have 2 pins
+RUN-1001 : 5770 nets have [3 - 5] pins
+RUN-1001 : 1114 nets have [6 - 10] pins
+RUN-1001 : 314 nets have [11 - 20] pins
+RUN-1001 : 351 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73581, tnet num: 17353, tinst num: 6719, tnode num: 95940, tedge num: 123507.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.582824s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (99.7%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 597 MB, peak memory is 753 MB
+PHY-1001 : 3290 mslices, 3280 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 991392, over cnt = 2872(8%), over = 4854, worst = 7
+PHY-1002 : len = 1.01162e+06, over cnt = 1694(4%), over = 2458, worst = 7
+PHY-1002 : len = 1.03142e+06, over cnt = 667(1%), over = 965, worst = 6
+PHY-1002 : len = 1.04241e+06, over cnt = 169(0%), over = 235, worst = 5
+PHY-1002 : len = 1.04789e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.032348s wall, 4.093750s user + 0.000000s system = 4.093750s CPU (135.0%)
+
+PHY-1001 : Congestion index: top1 = 67.20, top5 = 57.80, top10 = 53.24, top15 = 50.26.
+PHY-1001 : End global routing;  3.366348s wall, 4.406250s user + 0.015625s system = 4.421875s CPU (131.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 720, peak = 753.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 989, reserve = 990, peak = 989.
+PHY-1001 : End build detailed router design. 3.935423s wall, 3.921875s user + 0.015625s system = 3.937500s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267936, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.990861s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267992, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.417348s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (97.3%)
+
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1027, peak = 1025.
+PHY-1001 : End phase 1; 5.419842s wall, 5.421875s user + 0.000000s system = 5.421875s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.52654e+06, over cnt = 2068(0%), over = 2077, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1043, reserve = 1043, peak = 1043.
+PHY-1001 : End initial routed; 41.829279s wall, 69.421875s user + 0.453125s system = 69.875000s CPU (167.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 10/16454(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.177   |  -4.424   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.199813s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1044, peak = 1047.
+PHY-1001 : End phase 2; 45.029159s wall, 72.609375s user + 0.468750s system = 73.078125s CPU (162.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 10 pins with SWNS -2.177ns STNS -4.126ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.183723s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (93.6%)
+
+PHY-1022 : len = 2.5267e+06, over cnt = 2078(0%), over = 2087, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.431209s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.4821e+06, over cnt = 615(0%), over = 615, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.757497s wall, 3.984375s user + 0.046875s system = 4.031250s CPU (146.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.48153e+06, over cnt = 162(0%), over = 162, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.706800s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (152.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.48144e+06, over cnt = 35(0%), over = 35, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.453126s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (117.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.48189e+06, over cnt = 11(0%), over = 11, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.343054s wall, 0.328125s user + 0.015625s system = 0.343750s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.48216e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.436464s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.48222e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.329654s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.48222e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.473342s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.48224e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.172876s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.48222e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.174181s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.7%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.48222e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.230223s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (108.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.48222e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.247508s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (119.9%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.48224e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.382145s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.1%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.48224e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.180960s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.6%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.48224e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.156026s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 10/16454(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.177   |  -4.126   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.203248s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 654 feed throughs used by 451 nets
+PHY-1001 : End commit to database; 2.274571s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1155, peak = 1156.
+PHY-1001 : End phase 3; 13.346490s wall, 15.062500s user + 0.078125s system = 15.140625s CPU (113.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 9 pins with SWNS -2.177ns STNS -4.126ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.203326s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.9%)
+
+PHY-1022 : len = 2.48224e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.437958s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.177ns, -4.126ns, 4}
+PHY-1001 : Update timing.....
+PHY-1001 : 10/16454(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.177   |  -4.126   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.169843s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 654 feed throughs used by 451 nets
+PHY-1001 : End commit to database; 2.357707s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1164, peak = 1164.
+PHY-1001 : End phase 4; 5.991290s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.48224e+06
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1166, peak = 1166.
+PHY-1001 : End export database. 0.060095s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.0%)
+
+PHY-1001 : End detail routing;  74.167087s wall, 103.453125s user + 0.562500s system = 104.015625s CPU (140.2%)
+
+RUN-1003 : finish command "route" in  80.172757s wall, 110.484375s user + 0.593750s system = 111.078125s CPU (138.5%)
+
+RUN-1004 : used memory is 1091 MB, reserved memory is 1093 MB, peak memory is 1166 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10217   out of  19600   52.13%
+#reg                     9370   out of  19600   47.81%
+#le                     12279
+  #lut only              2909   out of  12279   23.69%
+  #reg only              2062   out of  12279   16.79%
+  #lut&reg               7308   out of  12279   59.52%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1800
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1385
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1300
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               967
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    144
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          67
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_a/u_ADconfig/reg0_syn_133.f1             3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_pixel_cdc/u_clk_cis_pixel_y/reg1_syn_288.f1      3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P86        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12279  |9190    |1027    |9400    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |537    |448     |23      |440     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |104    |89      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |27     |27      |0       |17      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |6      |6       |0       |5       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |759    |439     |96      |559     |0       |0       |
+|    u_ADconfig                |AD_config            |187    |129     |25      |135     |0       |0       |
+|    u_gen_sp                  |gen_sp               |268    |183     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |743    |476     |96      |550     |0       |0       |
+|    u_ADconfig                |AD_config            |170    |124     |25      |124     |0       |0       |
+|    u_gen_sp                  |gen_sp               |264    |166     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2970   |2358    |306     |2088    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |192    |146     |17      |150     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |2744   |2196    |289     |1904    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2321   |1874    |253     |1554    |22      |0       |
+|        channelPart           |channel_part_8478    |136    |128     |3       |125     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |40      |0       |0       |
+|        ram_switch            |ram_switch           |1838   |1465    |197     |1186    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |228    |201     |27      |116     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |9      |6       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |996    |650     |170     |703     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |614    |614     |0       |367     |0       |0       |
+|        read_ram_i            |read_ram             |265    |212     |44      |180     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |212    |172     |40      |141     |0       |0       |
+|          read_ram_data       |read_ram_data        |50     |37      |4       |36      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |323    |231     |36      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3206   |2464    |349     |2139    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |179    |126     |17      |145     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |2993   |2308    |332     |1961    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |3      |2       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2542   |1992    |290     |1604    |22      |1       |
+|        channelPart           |channel_part_8478    |251    |246     |3       |149     |0       |0       |
+|        fifo_adc              |fifo_adc             |63     |54      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |1840   |1409    |197     |1172    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |230    |203     |27      |110     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |16      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |6       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |9       |0       |0       |
+|          insert              |insert               |1004   |605     |170     |712     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |606    |601     |0       |350     |0       |0       |
+|        read_ram_i            |read_ram_rev         |362    |263     |81      |213     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |290    |217     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |72     |46      |8       |53      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9892  
+    #2         2       3807  
+    #3         3       1375  
+    #4         4       585   
+    #5        5-10     1168  
+    #6       11-50     586   
+    #7       51-100     22   
+    #8        >500      1    
+  Average     2.90           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.049361s wall, 3.546875s user + 0.015625s system = 3.562500s CPU (173.8%)
+
+RUN-1004 : used memory is 1092 MB, reserved memory is 1094 MB, peak memory is 1166 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73581, tnet num: 17353, tinst num: 6719, tnode num: 95940, tedge num: 123507.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.638299s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.2%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1099 MB, peak memory is 1166 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.464029s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (100.3%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1101 MB, peak memory is 1166 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6719
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17531, pip num: 176790
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 654
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3231 valid insts, and 487880 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.433143s wall, 71.343750s user + 0.218750s system = 71.562500s CPU (685.9%)
+
+RUN-1004 : used memory is 1269 MB, reserved memory is 1265 MB, peak memory is 1384 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_093249.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_101124.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_101124.log
new file mode 100644
index 0000000..7e3594a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_101124.log
@@ -0,0 +1,1913 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:11:24 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.119276s wall, 2.015625s user + 0.109375s system = 2.125000s CPU (100.3%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 315 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2972 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17719 instances
+RUN-0007 : 7428 luts, 9068 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20297 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13391 nets have 2 pins
+RUN-1001 : 5447 nets have [3 - 5] pins
+RUN-1001 : 1046 nets have [6 - 10] pins
+RUN-1001 : 161 nets have [11 - 20] pins
+RUN-1001 : 178 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3498     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     58     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 143
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17717 instances, 7428 luts, 9068 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5896 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84781, tnet num: 20119, tinst num: 17717, tnode num: 114934, tedge num: 136054.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.165832s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.2%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 514 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20119 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.956749s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (99.8%)
+
+PHY-3001 : Found 3482 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.0991e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17717.
+PHY-3001 : Level 1 #clusters 2061.
+PHY-3001 : End clustering;  0.130798s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (131.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29487e+06, overlap = 512.75
+PHY-3002 : Step(2): len = 1.2115e+06, overlap = 484.875
+PHY-3002 : Step(3): len = 794565, overlap = 652.438
+PHY-3002 : Step(4): len = 746044, overlap = 680.344
+PHY-3002 : Step(5): len = 572505, overlap = 808.406
+PHY-3002 : Step(6): len = 514748, overlap = 882.094
+PHY-3002 : Step(7): len = 430743, overlap = 929.812
+PHY-3002 : Step(8): len = 396707, overlap = 986.562
+PHY-3002 : Step(9): len = 351117, overlap = 1034.53
+PHY-3002 : Step(10): len = 332592, overlap = 1057.84
+PHY-3002 : Step(11): len = 301442, overlap = 1104.94
+PHY-3002 : Step(12): len = 277375, overlap = 1185.56
+PHY-3002 : Step(13): len = 255519, overlap = 1216
+PHY-3002 : Step(14): len = 233178, overlap = 1262.22
+PHY-3002 : Step(15): len = 210955, overlap = 1305.12
+PHY-3002 : Step(16): len = 190355, overlap = 1321.09
+PHY-3002 : Step(17): len = 176753, overlap = 1333.16
+PHY-3002 : Step(18): len = 168044, overlap = 1362.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.22981e-07
+PHY-3002 : Step(19): len = 165439, overlap = 1329.53
+PHY-3002 : Step(20): len = 189448, overlap = 1263.72
+PHY-3002 : Step(21): len = 190228, overlap = 1255
+PHY-3002 : Step(22): len = 191294, overlap = 1235.38
+PHY-3002 : Step(23): len = 188917, overlap = 1217.28
+PHY-3002 : Step(24): len = 185893, overlap = 1214.94
+PHY-3002 : Step(25): len = 182798, overlap = 1216.03
+PHY-3002 : Step(26): len = 181450, overlap = 1226.34
+PHY-3002 : Step(27): len = 178340, overlap = 1222.78
+PHY-3002 : Step(28): len = 176723, overlap = 1223.56
+PHY-3002 : Step(29): len = 174646, overlap = 1201.12
+PHY-3002 : Step(30): len = 173185, overlap = 1225.38
+PHY-3002 : Step(31): len = 170870, overlap = 1192.88
+PHY-3002 : Step(32): len = 169558, overlap = 1171.56
+PHY-3002 : Step(33): len = 169841, overlap = 1176.41
+PHY-3002 : Step(34): len = 170117, overlap = 1179.25
+PHY-3002 : Step(35): len = 170010, overlap = 1183.38
+PHY-3002 : Step(36): len = 169720, overlap = 1190.56
+PHY-3002 : Step(37): len = 170189, overlap = 1192.22
+PHY-3002 : Step(38): len = 169775, overlap = 1195.62
+PHY-3002 : Step(39): len = 169870, overlap = 1199.44
+PHY-3002 : Step(40): len = 170130, overlap = 1183.84
+PHY-3002 : Step(41): len = 169746, overlap = 1168.22
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.64596e-06
+PHY-3002 : Step(42): len = 171835, overlap = 1168
+PHY-3002 : Step(43): len = 180403, overlap = 1163.25
+PHY-3002 : Step(44): len = 183412, overlap = 1142.25
+PHY-3002 : Step(45): len = 189226, overlap = 1124.75
+PHY-3002 : Step(46): len = 190150, overlap = 1134.22
+PHY-3002 : Step(47): len = 192449, overlap = 1122.09
+PHY-3002 : Step(48): len = 191585, overlap = 1115.28
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.29192e-06
+PHY-3002 : Step(49): len = 197947, overlap = 1108.22
+PHY-3002 : Step(50): len = 214175, overlap = 1028.41
+PHY-3002 : Step(51): len = 222272, overlap = 940.156
+PHY-3002 : Step(52): len = 228902, overlap = 891.469
+PHY-3002 : Step(53): len = 231454, overlap = 873.344
+PHY-3002 : Step(54): len = 233993, overlap = 866.906
+PHY-3002 : Step(55): len = 234381, overlap = 860.438
+PHY-3002 : Step(56): len = 234080, overlap = 844.938
+PHY-3002 : Step(57): len = 232279, overlap = 852.312
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.58385e-06
+PHY-3002 : Step(58): len = 243235, overlap = 811.625
+PHY-3002 : Step(59): len = 261146, overlap = 752.781
+PHY-3002 : Step(60): len = 271088, overlap = 681.344
+PHY-3002 : Step(61): len = 281811, overlap = 644.562
+PHY-3002 : Step(62): len = 286802, overlap = 621.781
+PHY-3002 : Step(63): len = 287758, overlap = 626.062
+PHY-3002 : Step(64): len = 286969, overlap = 637.938
+PHY-3002 : Step(65): len = 284851, overlap = 659.781
+PHY-3002 : Step(66): len = 282662, overlap = 672.375
+PHY-3002 : Step(67): len = 281184, overlap = 666.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.31677e-05
+PHY-3002 : Step(68): len = 298628, overlap = 621.125
+PHY-3002 : Step(69): len = 313683, overlap = 559.5
+PHY-3002 : Step(70): len = 317191, overlap = 513.5
+PHY-3002 : Step(71): len = 320023, overlap = 477.156
+PHY-3002 : Step(72): len = 319871, overlap = 479.906
+PHY-3002 : Step(73): len = 320406, overlap = 478.719
+PHY-3002 : Step(74): len = 319594, overlap = 487.688
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.63354e-05
+PHY-3002 : Step(75): len = 340363, overlap = 428.062
+PHY-3002 : Step(76): len = 358281, overlap = 419.031
+PHY-3002 : Step(77): len = 358772, overlap = 415.656
+PHY-3002 : Step(78): len = 362148, overlap = 396.75
+PHY-3002 : Step(79): len = 363264, overlap = 382.062
+PHY-3002 : Step(80): len = 365758, overlap = 375.531
+PHY-3002 : Step(81): len = 363334, overlap = 352.406
+PHY-3002 : Step(82): len = 362835, overlap = 308.219
+PHY-3002 : Step(83): len = 361374, overlap = 314.062
+PHY-3002 : Step(84): len = 361248, overlap = 305.531
+PHY-3002 : Step(85): len = 359812, overlap = 300.812
+PHY-3002 : Step(86): len = 360152, overlap = 305.938
+PHY-3002 : Step(87): len = 358670, overlap = 310.969
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.26708e-05
+PHY-3002 : Step(88): len = 380193, overlap = 286.656
+PHY-3002 : Step(89): len = 395517, overlap = 257.844
+PHY-3002 : Step(90): len = 395630, overlap = 256.438
+PHY-3002 : Step(91): len = 397076, overlap = 257.688
+PHY-3002 : Step(92): len = 399495, overlap = 260.312
+PHY-3002 : Step(93): len = 402378, overlap = 256.594
+PHY-3002 : Step(94): len = 400040, overlap = 258.719
+PHY-3002 : Step(95): len = 402397, overlap = 258.25
+PHY-3002 : Step(96): len = 405118, overlap = 239.531
+PHY-3002 : Step(97): len = 408976, overlap = 225.094
+PHY-3002 : Step(98): len = 406166, overlap = 236.219
+PHY-3002 : Step(99): len = 406487, overlap = 237.344
+PHY-3002 : Step(100): len = 407737, overlap = 234.469
+PHY-3002 : Step(101): len = 410257, overlap = 216.906
+PHY-3002 : Step(102): len = 405652, overlap = 226.312
+PHY-3002 : Step(103): len = 406048, overlap = 222.344
+PHY-3002 : Step(104): len = 408401, overlap = 213.281
+PHY-3002 : Step(105): len = 410752, overlap = 226.219
+PHY-3002 : Step(106): len = 406957, overlap = 218.031
+PHY-3002 : Step(107): len = 406831, overlap = 216.156
+PHY-3002 : Step(108): len = 408422, overlap = 226.938
+PHY-3002 : Step(109): len = 409628, overlap = 235.562
+PHY-3002 : Step(110): len = 406751, overlap = 237.812
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000105342
+PHY-3002 : Step(111): len = 424399, overlap = 242.062
+PHY-3002 : Step(112): len = 434863, overlap = 220.844
+PHY-3002 : Step(113): len = 431914, overlap = 213.438
+PHY-3002 : Step(114): len = 432130, overlap = 203.25
+PHY-3002 : Step(115): len = 436697, overlap = 199.281
+PHY-3002 : Step(116): len = 440122, overlap = 205.781
+PHY-3002 : Step(117): len = 437256, overlap = 205.312
+PHY-3002 : Step(118): len = 437086, overlap = 211.875
+PHY-3002 : Step(119): len = 438637, overlap = 221.844
+PHY-3002 : Step(120): len = 439728, overlap = 221.344
+PHY-3002 : Step(121): len = 437761, overlap = 212.25
+PHY-3002 : Step(122): len = 437187, overlap = 214.75
+PHY-3002 : Step(123): len = 438901, overlap = 218.75
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000210683
+PHY-3002 : Step(124): len = 452352, overlap = 213.469
+PHY-3002 : Step(125): len = 463134, overlap = 210.188
+PHY-3002 : Step(126): len = 464092, overlap = 194.5
+PHY-3002 : Step(127): len = 464715, overlap = 188.75
+PHY-3002 : Step(128): len = 467874, overlap = 188.969
+PHY-3002 : Step(129): len = 470930, overlap = 162.938
+PHY-3002 : Step(130): len = 468541, overlap = 168.75
+PHY-3002 : Step(131): len = 469299, overlap = 168.781
+PHY-3002 : Step(132): len = 471829, overlap = 163.688
+PHY-3002 : Step(133): len = 473676, overlap = 174.969
+PHY-3002 : Step(134): len = 470758, overlap = 171.469
+PHY-3002 : Step(135): len = 470467, overlap = 173
+PHY-3002 : Step(136): len = 472421, overlap = 180.469
+PHY-3002 : Step(137): len = 473947, overlap = 179.062
+PHY-3002 : Step(138): len = 471801, overlap = 177.219
+PHY-3002 : Step(139): len = 471447, overlap = 174.125
+PHY-3002 : Step(140): len = 473199, overlap = 168.344
+PHY-3002 : Step(141): len = 474665, overlap = 163.406
+PHY-3002 : Step(142): len = 472141, overlap = 169.219
+PHY-3002 : Step(143): len = 471963, overlap = 167.844
+PHY-3002 : Step(144): len = 473913, overlap = 164
+PHY-3002 : Step(145): len = 474431, overlap = 163.656
+PHY-3002 : Step(146): len = 472805, overlap = 165.938
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000384986
+PHY-3002 : Step(147): len = 480350, overlap = 163.469
+PHY-3002 : Step(148): len = 488507, overlap = 168.781
+PHY-3002 : Step(149): len = 488513, overlap = 167.469
+PHY-3002 : Step(150): len = 489022, overlap = 166.438
+PHY-3002 : Step(151): len = 490484, overlap = 158.781
+PHY-3002 : Step(152): len = 491268, overlap = 156.656
+PHY-3002 : Step(153): len = 490673, overlap = 156.25
+PHY-3002 : Step(154): len = 491798, overlap = 154.781
+PHY-3002 : Step(155): len = 494119, overlap = 156.5
+PHY-3002 : Step(156): len = 495636, overlap = 155.562
+PHY-3002 : Step(157): len = 495191, overlap = 154.719
+PHY-3002 : Step(158): len = 495894, overlap = 149.312
+PHY-3002 : Step(159): len = 498083, overlap = 154.719
+PHY-3002 : Step(160): len = 499276, overlap = 158.219
+PHY-3002 : Step(161): len = 497449, overlap = 159.219
+PHY-3002 : Step(162): len = 497228, overlap = 159.094
+PHY-3002 : Step(163): len = 498339, overlap = 161.469
+PHY-3002 : Step(164): len = 498781, overlap = 161.125
+PHY-3002 : Step(165): len = 498291, overlap = 155.875
+PHY-3002 : Step(166): len = 498640, overlap = 154.125
+PHY-3002 : Step(167): len = 499897, overlap = 153.25
+PHY-3002 : Step(168): len = 500753, overlap = 153.688
+PHY-3002 : Step(169): len = 500164, overlap = 151.344
+PHY-3002 : Step(170): len = 500910, overlap = 149.562
+PHY-3002 : Step(171): len = 502342, overlap = 153.188
+PHY-3002 : Step(172): len = 502729, overlap = 153.531
+PHY-3002 : Step(173): len = 501906, overlap = 145.219
+PHY-3002 : Step(174): len = 502108, overlap = 146.656
+PHY-3002 : Step(175): len = 503422, overlap = 148.312
+PHY-3002 : Step(176): len = 504367, overlap = 148.938
+PHY-3002 : Step(177): len = 503054, overlap = 151.031
+PHY-3002 : Step(178): len = 502980, overlap = 149.281
+PHY-3002 : Step(179): len = 504151, overlap = 147.656
+PHY-3002 : Step(180): len = 504666, overlap = 146.344
+PHY-3002 : Step(181): len = 503455, overlap = 146.812
+PHY-3002 : Step(182): len = 503086, overlap = 144.094
+PHY-3002 : Step(183): len = 504336, overlap = 144.031
+PHY-3002 : Step(184): len = 504709, overlap = 143.75
+PHY-3002 : Step(185): len = 503373, overlap = 144
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000673337
+PHY-3002 : Step(186): len = 508162, overlap = 140.75
+PHY-3002 : Step(187): len = 512171, overlap = 144.969
+PHY-3002 : Step(188): len = 512217, overlap = 141.75
+PHY-3002 : Step(189): len = 512777, overlap = 139.688
+PHY-3002 : Step(190): len = 514901, overlap = 138.281
+PHY-3002 : Step(191): len = 516354, overlap = 137.594
+PHY-3002 : Step(192): len = 516317, overlap = 131.719
+PHY-3002 : Step(193): len = 517168, overlap = 126.938
+PHY-3002 : Step(194): len = 518989, overlap = 128.5
+PHY-3002 : Step(195): len = 519483, overlap = 128.5
+PHY-3002 : Step(196): len = 518434, overlap = 127.625
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00116216
+PHY-3002 : Step(197): len = 521680, overlap = 130.75
+PHY-3002 : Step(198): len = 526150, overlap = 127.438
+PHY-3002 : Step(199): len = 526949, overlap = 125.969
+PHY-3002 : Step(200): len = 527691, overlap = 121.406
+PHY-3002 : Step(201): len = 529445, overlap = 120.062
+PHY-3002 : Step(202): len = 530524, overlap = 120.812
+PHY-3002 : Step(203): len = 530295, overlap = 121.812
+PHY-3002 : Step(204): len = 530569, overlap = 118.938
+PHY-3002 : Step(205): len = 532379, overlap = 123.062
+PHY-3002 : Step(206): len = 533269, overlap = 119.188
+PHY-3002 : Step(207): len = 532595, overlap = 124.531
+PHY-3002 : Step(208): len = 532481, overlap = 124.531
+PHY-3002 : Step(209): len = 533174, overlap = 125.469
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00205812
+PHY-3002 : Step(210): len = 535907, overlap = 124.156
+PHY-3002 : Step(211): len = 541461, overlap = 118.562
+PHY-3002 : Step(212): len = 542753, overlap = 118.719
+PHY-3002 : Step(213): len = 543733, overlap = 118.469
+PHY-3002 : Step(214): len = 544707, overlap = 114.656
+PHY-3002 : Step(215): len = 545624, overlap = 111.469
+PHY-3002 : Step(216): len = 546308, overlap = 111.031
+PHY-3002 : Step(217): len = 546867, overlap = 111.031
+PHY-3002 : Step(218): len = 547111, overlap = 111.625
+PHY-3002 : Step(219): len = 547211, overlap = 112.312
+PHY-3002 : Step(220): len = 547350, overlap = 112.25
+PHY-3001 : :::14::: Try harder cell spreading with beta_ = 0.00333003
+PHY-3002 : Step(221): len = 548472, overlap = 112.25
+PHY-3002 : Step(222): len = 551744, overlap = 111.594
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.012638s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (247.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20297.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724264, over cnt = 1584(4%), over = 7465, worst = 66
+PHY-1001 : End global iterations;  0.756117s wall, 0.937500s user + 0.031250s system = 0.968750s CPU (128.1%)
+
+PHY-1001 : Congestion index: top1 = 75.71, top5 = 58.73, top10 = 50.88, top15 = 45.85.
+PHY-3001 : End congestion estimation;  0.981528s wall, 1.156250s user + 0.046875s system = 1.203125s CPU (122.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20119 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.857480s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.4147e-05
+PHY-3002 : Step(223): len = 659581, overlap = 51.3438
+PHY-3002 : Step(224): len = 664454, overlap = 54.0625
+PHY-3002 : Step(225): len = 661051, overlap = 57.8125
+PHY-3002 : Step(226): len = 658387, overlap = 50.2812
+PHY-3002 : Step(227): len = 662190, overlap = 52.6875
+PHY-3002 : Step(228): len = 667806, overlap = 45
+PHY-3002 : Step(229): len = 670272, overlap = 43.4375
+PHY-3002 : Step(230): len = 677880, overlap = 51.5938
+PHY-3002 : Step(231): len = 688394, overlap = 47.875
+PHY-3002 : Step(232): len = 691162, overlap = 53.6875
+PHY-3002 : Step(233): len = 694454, overlap = 53
+PHY-3002 : Step(234): len = 701833, overlap = 48.4062
+PHY-3002 : Step(235): len = 704287, overlap = 51.8438
+PHY-3002 : Step(236): len = 707305, overlap = 44.375
+PHY-3002 : Step(237): len = 711212, overlap = 48.5
+PHY-3002 : Step(238): len = 713105, overlap = 53.4688
+PHY-3002 : Step(239): len = 716660, overlap = 56
+PHY-3002 : Step(240): len = 717648, overlap = 50.0938
+PHY-3002 : Step(241): len = 718350, overlap = 52.3125
+PHY-3002 : Step(242): len = 718165, overlap = 51.0938
+PHY-3002 : Step(243): len = 719829, overlap = 51.2188
+PHY-3002 : Step(244): len = 720454, overlap = 51.7188
+PHY-3002 : Step(245): len = 719791, overlap = 52.6875
+PHY-3002 : Step(246): len = 720340, overlap = 48.5625
+PHY-3002 : Step(247): len = 720855, overlap = 48.0938
+PHY-3002 : Step(248): len = 719191, overlap = 47.4375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000168294
+PHY-3002 : Step(249): len = 720687, overlap = 46.25
+PHY-3002 : Step(250): len = 724129, overlap = 44.7188
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 62/20297.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 801104, over cnt = 2755(7%), over = 13382, worst = 40
+PHY-1001 : End global iterations;  1.336632s wall, 1.921875s user + 0.031250s system = 1.953125s CPU (146.1%)
+
+PHY-1001 : Congestion index: top1 = 94.27, top5 = 73.01, top10 = 63.84, top15 = 58.25.
+PHY-3001 : End congestion estimation;  1.633692s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (136.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20119 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.492944s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.30924e-05
+PHY-3002 : Step(251): len = 722486, overlap = 299.875
+PHY-3002 : Step(252): len = 728497, overlap = 248.062
+PHY-3002 : Step(253): len = 729341, overlap = 222.062
+PHY-3002 : Step(254): len = 724948, overlap = 213.438
+PHY-3002 : Step(255): len = 722904, overlap = 196.031
+PHY-3002 : Step(256): len = 723121, overlap = 186.938
+PHY-3002 : Step(257): len = 721766, overlap = 176.625
+PHY-3002 : Step(258): len = 719279, overlap = 167.438
+PHY-3002 : Step(259): len = 718738, overlap = 153.75
+PHY-3002 : Step(260): len = 717512, overlap = 152.031
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000166185
+PHY-3002 : Step(261): len = 717837, overlap = 148
+PHY-3002 : Step(262): len = 719741, overlap = 141.719
+PHY-3002 : Step(263): len = 720919, overlap = 137.969
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000324368
+PHY-3002 : Step(264): len = 728282, overlap = 131.219
+PHY-3002 : Step(265): len = 739329, overlap = 114.656
+PHY-3002 : Step(266): len = 740312, overlap = 109.469
+PHY-3002 : Step(267): len = 739067, overlap = 110.688
+PHY-3002 : Step(268): len = 739285, overlap = 111.938
+PHY-3002 : Step(269): len = 740499, overlap = 108.219
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84781, tnet num: 20119, tinst num: 17717, tnode num: 114934, tedge num: 136054.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.542695s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (98.2%)
+
+RUN-1004 : used memory is 580 MB, reserved memory is 562 MB, peak memory is 717 MB
+OPT-1001 : Total overflow 470.91 peak overflow 4.16
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1398/20297.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 826240, over cnt = 3111(8%), over = 12382, worst = 46
+PHY-1001 : End global iterations;  1.044164s wall, 1.515625s user + 0.000000s system = 1.515625s CPU (145.2%)
+
+PHY-1001 : Congestion index: top1 = 86.49, top5 = 67.95, top10 = 59.70, top15 = 54.67.
+PHY-1001 : End incremental global routing;  1.363044s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (136.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20119 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.917807s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (98.7%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17582 has valid locations, 320 needs to be replaced
+PHY-3001 : design contains 17987 instances, 7517 luts, 9249 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6011 pins
+PHY-3001 : Found 3513 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 761410
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16727/20567.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 840664, over cnt = 3148(8%), over = 12475, worst = 46
+PHY-1001 : End global iterations;  0.218474s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (100.1%)
+
+PHY-1001 : Congestion index: top1 = 86.19, top5 = 68.12, top10 = 59.99, top15 = 54.92.
+PHY-3001 : End congestion estimation;  0.494621s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (101.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85881, tnet num: 20389, tinst num: 17987, tnode num: 116591, tedge num: 137714.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.455217s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.9%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 612 MB, peak memory is 719 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20389 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.528554s wall, 2.484375s user + 0.031250s system = 2.515625s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(270): len = 760528, overlap = 2.3125
+PHY-3002 : Step(271): len = 759990, overlap = 2.125
+PHY-3002 : Step(272): len = 759742, overlap = 2.1875
+PHY-3002 : Step(273): len = 759568, overlap = 2.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16816/20567.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838344, over cnt = 3152(8%), over = 12489, worst = 46
+PHY-1001 : End global iterations;  0.187885s wall, 0.234375s user + 0.031250s system = 0.265625s CPU (141.4%)
+
+PHY-1001 : Congestion index: top1 = 86.68, top5 = 68.44, top10 = 60.23, top15 = 55.18.
+PHY-3001 : End congestion estimation;  0.435358s wall, 0.468750s user + 0.031250s system = 0.500000s CPU (114.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20389 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.931947s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000254032
+PHY-3002 : Step(274): len = 759574, overlap = 111.188
+PHY-3002 : Step(275): len = 759704, overlap = 110.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000508063
+PHY-3002 : Step(276): len = 759613, overlap = 110.156
+PHY-3002 : Step(277): len = 759788, overlap = 110.281
+PHY-3001 : Final: Len = 759788, Over = 110.281
+PHY-3001 : End incremental placement;  5.046902s wall, 5.156250s user + 0.218750s system = 5.375000s CPU (106.5%)
+
+OPT-1001 : Total overflow 476.28 peak overflow 4.16
+OPT-1001 : End high-fanout net optimization;  7.891378s wall, 8.437500s user + 0.265625s system = 8.703125s CPU (110.3%)
+
+OPT-1001 : Current memory(MB): used = 723, reserve = 711, peak = 739.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16795/20567.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841808, over cnt = 3137(8%), over = 11611, worst = 46
+PHY-1002 : len = 895560, over cnt = 2400(6%), over = 6771, worst = 34
+PHY-1002 : len = 936880, over cnt = 1436(4%), over = 3704, worst = 23
+PHY-1002 : len = 996752, over cnt = 300(0%), over = 525, worst = 14
+PHY-1002 : len = 1.00631e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.028739s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (132.5%)
+
+PHY-1001 : Congestion index: top1 = 68.38, top5 = 60.12, top10 = 55.52, top15 = 52.35.
+OPT-1001 : End congestion update;  2.301475s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (129.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20389 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.800282s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.6%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 80 cells processed and 6850 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 3 cells processed and 100 slack improved
+OPT-1001 : End global optimization;  3.145822s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (121.7%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 689, peak = 739.
+OPT-1001 : End physical optimization;  13.090721s wall, 14.296875s user + 0.296875s system = 14.593750s CPU (111.5%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7517 LUT to BLE ...
+SYN-4008 : Packed 7517 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6116 remaining SEQ's ...
+SYN-4005 : Packed 3645 SEQ with LUT/SLICE
+SYN-4006 : 1022 single LUT's are left
+SYN-4006 : 2471 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9988/13719 primitive instances ...
+PHY-3001 : End packing;  1.648087s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6871 instances
+RUN-1001 : 3362 mslices, 3361 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17539 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10026 nets have 2 pins
+RUN-1001 : 5689 nets have [3 - 5] pins
+RUN-1001 : 1141 nets have [6 - 10] pins
+RUN-1001 : 309 nets have [11 - 20] pins
+RUN-1001 : 341 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6869 instances, 6723 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3475 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 766256, Over = 312.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7619/17539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932448, over cnt = 2070(5%), over = 3517, worst = 8
+PHY-1002 : len = 942040, over cnt = 1322(3%), over = 1810, worst = 8
+PHY-1002 : len = 956184, over cnt = 377(1%), over = 484, worst = 5
+PHY-1002 : len = 960432, over cnt = 203(0%), over = 244, worst = 5
+PHY-1002 : len = 966408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.679196s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (143.3%)
+
+PHY-1001 : Congestion index: top1 = 67.80, top5 = 57.98, top10 = 53.10, top15 = 49.91.
+PHY-3001 : End congestion estimation;  2.060658s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (135.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73437, tnet num: 17361, tinst num: 6869, tnode num: 95645, tedge num: 123138.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.652437s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.2%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 612 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.513425s wall, 2.515625s user + 0.000000s system = 2.515625s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.10725e-05
+PHY-3002 : Step(278): len = 753999, overlap = 312.5
+PHY-3002 : Step(279): len = 747285, overlap = 312.25
+PHY-3002 : Step(280): len = 742414, overlap = 312.5
+PHY-3002 : Step(281): len = 738343, overlap = 305.5
+PHY-3002 : Step(282): len = 734834, overlap = 322
+PHY-3002 : Step(283): len = 731332, overlap = 323.25
+PHY-3002 : Step(284): len = 727405, overlap = 327.75
+PHY-3002 : Step(285): len = 723710, overlap = 324.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.2145e-05
+PHY-3002 : Step(286): len = 726031, overlap = 318.75
+PHY-3002 : Step(287): len = 731433, overlap = 304.5
+PHY-3002 : Step(288): len = 734010, overlap = 295.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00016429
+PHY-3002 : Step(289): len = 740445, overlap = 284.75
+PHY-3002 : Step(290): len = 748534, overlap = 272.25
+PHY-3002 : Step(291): len = 748758, overlap = 268.25
+PHY-3002 : Step(292): len = 750120, overlap = 259
+PHY-3002 : Step(293): len = 751647, overlap = 254.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.323019s wall, 0.140625s user + 0.546875s system = 0.687500s CPU (212.8%)
+
+PHY-3001 : Trial Legalized: Len = 1.04329e+06
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 682/17539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.16898e+06, over cnt = 3051(8%), over = 5380, worst = 8
+PHY-1002 : len = 1.19514e+06, over cnt = 1725(4%), over = 2457, worst = 8
+PHY-1002 : len = 1.21458e+06, over cnt = 817(2%), over = 1090, worst = 7
+PHY-1002 : len = 1.23014e+06, over cnt = 145(0%), over = 191, worst = 4
+PHY-1002 : len = 1.23348e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1001 : End global iterations;  2.634125s wall, 3.875000s user + 0.093750s system = 3.968750s CPU (150.7%)
+
+PHY-1001 : Congestion index: top1 = 75.32, top5 = 66.99, top10 = 62.21, top15 = 58.83.
+PHY-3001 : End congestion estimation;  3.055780s wall, 4.312500s user + 0.093750s system = 4.406250s CPU (144.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.853569s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000166949
+PHY-3002 : Step(294): len = 989719, overlap = 99.25
+PHY-3002 : Step(295): len = 956586, overlap = 128.5
+PHY-3002 : Step(296): len = 932579, overlap = 151
+PHY-3002 : Step(297): len = 915760, overlap = 162.25
+PHY-3002 : Step(298): len = 902309, overlap = 176.5
+PHY-3002 : Step(299): len = 892648, overlap = 184.75
+PHY-3002 : Step(300): len = 883137, overlap = 194.75
+PHY-3002 : Step(301): len = 875488, overlap = 198.25
+PHY-3002 : Step(302): len = 869754, overlap = 204.75
+PHY-3002 : Step(303): len = 864661, overlap = 206
+PHY-3002 : Step(304): len = 861195, overlap = 205.5
+PHY-3002 : Step(305): len = 857587, overlap = 207.75
+PHY-3002 : Step(306): len = 854244, overlap = 207
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00032682
+PHY-3002 : Step(307): len = 861015, overlap = 198.5
+PHY-3002 : Step(308): len = 864567, overlap = 197.25
+PHY-3002 : Step(309): len = 867420, overlap = 196
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000528794
+PHY-3002 : Step(310): len = 874373, overlap = 187.5
+PHY-3002 : Step(311): len = 879670, overlap = 188.25
+PHY-3002 : Step(312): len = 883396, overlap = 188.75
+PHY-3002 : Step(313): len = 885569, overlap = 191.5
+PHY-3002 : Step(314): len = 887161, overlap = 191.5
+PHY-3002 : Step(315): len = 888224, overlap = 188.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.096228s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (113.7%)
+
+PHY-3001 : Legalized: Len = 961939, Over = 0
+PHY-3001 : Spreading special nets. 463 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.131835s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.7%)
+
+PHY-3001 : 728 instances has been re-located, deltaX = 343, deltaY = 468, maxDist = 7.
+PHY-3001 : Final: Len = 974834, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73437, tnet num: 17361, tinst num: 6872, tnode num: 95645, tedge num: 123138.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.879809s wall, 1.843750s user + 0.031250s system = 1.875000s CPU (99.7%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 656 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 2099/17539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.10458e+06, over cnt = 2762(7%), over = 4719, worst = 7
+PHY-1002 : len = 1.1209e+06, over cnt = 1750(4%), over = 2569, worst = 7
+PHY-1002 : len = 1.13806e+06, over cnt = 887(2%), over = 1258, worst = 7
+PHY-1002 : len = 1.14732e+06, over cnt = 479(1%), over = 637, worst = 6
+PHY-1002 : len = 1.15782e+06, over cnt = 6(0%), over = 8, worst = 3
+PHY-1001 : End global iterations;  2.372361s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (142.3%)
+
+PHY-1001 : Congestion index: top1 = 71.90, top5 = 64.11, top10 = 58.96, top15 = 55.61.
+PHY-1001 : End incremental global routing;  2.728963s wall, 3.750000s user + 0.000000s system = 3.750000s CPU (137.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.868496s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (100.7%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6778 has valid locations, 32 needs to be replaced
+PHY-3001 : design contains 6898 instances, 6749 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3546 pins
+PHY-3001 : Found 1578 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 977247
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16082/17574.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.16024e+06, over cnt = 85(0%), over = 100, worst = 4
+PHY-1002 : len = 1.16031e+06, over cnt = 40(0%), over = 41, worst = 2
+PHY-1002 : len = 1.16049e+06, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 1.16074e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.16085e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.814819s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 71.90, top5 = 64.11, top10 = 58.96, top15 = 55.62.
+PHY-3001 : End congestion estimation;  1.135739s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (105.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73665, tnet num: 17396, tinst num: 6898, tnode num: 95937, tedge num: 123447.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.836376s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (100.4%)
+
+RUN-1004 : used memory is 666 MB, reserved memory is 666 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17396 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.726531s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(316): len = 976557, overlap = 0.25
+PHY-3002 : Step(317): len = 976351, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16076/17574.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.15959e+06, over cnt = 60(0%), over = 77, worst = 5
+PHY-1002 : len = 1.15975e+06, over cnt = 22(0%), over = 22, worst = 1
+PHY-1002 : len = 1.16005e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.16016e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.614131s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (101.8%)
+
+PHY-1001 : Congestion index: top1 = 71.90, top5 = 64.11, top10 = 58.97, top15 = 55.61.
+PHY-3001 : End congestion estimation;  0.949237s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (102.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17396 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.202861s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000172437
+PHY-3002 : Step(318): len = 976195, overlap = 1.5
+PHY-3002 : Step(319): len = 976312, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005954s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 976347, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059719s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 14, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 976579, Over = 0
+PHY-3001 : End incremental placement;  6.512640s wall, 6.609375s user + 0.156250s system = 6.765625s CPU (103.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.606047s wall, 11.703125s user + 0.187500s system = 11.890625s CPU (112.1%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 741, peak = 751.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16016/17574.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.15964e+06, over cnt = 76(0%), over = 87, worst = 3
+PHY-1002 : len = 1.15964e+06, over cnt = 41(0%), over = 43, worst = 2
+PHY-1002 : len = 1.15995e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.16005e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.16008e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.831241s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (109.0%)
+
+PHY-1001 : Congestion index: top1 = 71.90, top5 = 64.10, top10 = 58.96, top15 = 55.62.
+OPT-1001 : End congestion update;  1.142686s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (106.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17396 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.710487s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (101.2%)
+
+OPT-0007 : Start: WNS -1233 TNS -2047 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6810 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6898 instances, 6749 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3546 pins
+PHY-3001 : Found 1578 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 978861, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059764s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 16, deltaY = 16, maxDist = 5.
+PHY-3001 : Final: Len = 979119, Over = 0
+PHY-3001 : End incremental legalization;  0.423349s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 24 cells processed and 6700 slack improved
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.424145s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (103.1%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 741, peak = 751.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17396 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.890983s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15986/17574.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.16205e+06, over cnt = 96(0%), over = 110, worst = 3
+PHY-1002 : len = 1.16215e+06, over cnt = 69(0%), over = 69, worst = 1
+PHY-1002 : len = 1.16254e+06, over cnt = 36(0%), over = 36, worst = 1
+PHY-1002 : len = 1.16295e+06, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 1.16322e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.855674s wall, 0.859375s user + 0.046875s system = 0.906250s CPU (105.9%)
+
+PHY-1001 : Congestion index: top1 = 71.72, top5 = 64.00, top10 = 58.94, top15 = 55.66.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17396 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.726911s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.0%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1233 TNS -2018 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 71.241379
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1233ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17574 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17574 nets
+OPT-1001 : End physical optimization;  18.160601s wall, 19.296875s user + 0.281250s system = 19.578125s CPU (107.8%)
+
+RUN-1003 : finish command "place" in  60.359335s wall, 89.796875s user + 6.593750s system = 96.390625s CPU (159.7%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 606 MB, peak memory is 751 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.685144s wall, 2.937500s user + 0.031250s system = 2.968750s CPU (176.2%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 607 MB, peak memory is 751 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6900 instances
+RUN-1001 : 3381 mslices, 3368 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17574 nets
+RUN-6002 WARNING: There are 2 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10037 nets have 2 pins
+RUN-1001 : 5690 nets have [3 - 5] pins
+RUN-1001 : 1146 nets have [6 - 10] pins
+RUN-1001 : 316 nets have [11 - 20] pins
+RUN-1001 : 356 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73665, tnet num: 17396, tinst num: 6898, tnode num: 95937, tedge num: 123447.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.642942s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.9%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 631 MB, peak memory is 751 MB
+PHY-1001 : 3381 mslices, 3368 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17396 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[26] is skipped due to 0 input or output
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/adc_tail[33] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09193e+06, over cnt = 2881(8%), over = 4981, worst = 7
+PHY-1002 : len = 1.10904e+06, over cnt = 1944(5%), over = 2994, worst = 7
+PHY-1002 : len = 1.13454e+06, over cnt = 730(2%), over = 1079, worst = 7
+PHY-1002 : len = 1.15114e+06, over cnt = 29(0%), over = 30, worst = 2
+PHY-1002 : len = 1.15186e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.750202s wall, 3.921875s user + 0.000000s system = 3.921875s CPU (142.6%)
+
+PHY-1001 : Congestion index: top1 = 71.36, top5 = 63.43, top10 = 58.53, top15 = 55.16.
+PHY-1001 : End global routing;  3.086600s wall, 4.265625s user + 0.000000s system = 4.265625s CPU (138.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 716, peak = 751.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 991, reserve = 988, peak = 991.
+PHY-1001 : End build detailed router design. 3.966711s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 260008, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.441867s wall, 5.437500s user + 0.000000s system = 5.437500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 260064, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.487592s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (102.5%)
+
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1023, peak = 1025.
+PHY-1001 : End phase 1; 5.941487s wall, 5.937500s user + 0.000000s system = 5.937500s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 72% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.63398e+06, over cnt = 2338(0%), over = 2347, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1040, reserve = 1035, peak = 1040.
+PHY-1001 : End initial routed; 63.795449s wall, 94.984375s user + 0.562500s system = 95.546875s CPU (149.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16495(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.155   |  -4.467   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.320069s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1048, peak = 1051.
+PHY-1001 : End phase 2; 67.115580s wall, 98.296875s user + 0.578125s system = 98.875000s CPU (147.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 6 pins with SWNS -2.158ns STNS -4.464ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.155182s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.7%)
+
+PHY-1022 : len = 2.63398e+06, over cnt = 2346(0%), over = 2356, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.424224s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.58952e+06, over cnt = 984(0%), over = 985, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 3.041296s wall, 3.968750s user + 0.000000s system = 3.968750s CPU (130.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.58122e+06, over cnt = 287(0%), over = 287, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.796981s wall, 2.109375s user + 0.000000s system = 2.109375s CPU (117.4%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.58226e+06, over cnt = 52(0%), over = 52, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.689532s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (115.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.58321e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.477814s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.281381s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.320596s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (102.3%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.472119s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.6%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.173884s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.171517s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (109.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.229961s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.265259s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.58341e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.442476s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.9%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.58342e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.203061s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (115.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.58346e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.173328s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (108.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16495(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.158   |  -4.464   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.291049s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 671 feed throughs used by 482 nets
+PHY-1001 : End commit to database; 2.340635s wall, 2.281250s user + 0.046875s system = 2.328125s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1157, peak = 1156.
+PHY-1001 : End phase 3; 15.212695s wall, 16.609375s user + 0.046875s system = 16.656250s CPU (109.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 6 pins with SWNS -2.113ns STNS -4.419ns FEP 4.
+PHY-1001 : End OPT Iter 1; 0.234085s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.1%)
+
+PHY-1022 : len = 2.58344e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.474286s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (102.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.113ns, -4.419ns, 4}
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16495(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.113   |  -4.419   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.318000s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 672 feed throughs used by 483 nets
+PHY-1001 : End commit to database; 2.455463s wall, 2.468750s user + 0.000000s system = 2.468750s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1165, reserve = 1166, peak = 1165.
+PHY-1001 : End phase 4; 6.275500s wall, 6.281250s user + 0.000000s system = 6.281250s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.58344e+06
+PHY-1001 : Current memory(MB): used = 1167, reserve = 1168, peak = 1167.
+PHY-1001 : End export database. 0.160191s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (107.3%)
+
+PHY-1001 : End detail routing;  99.071314s wall, 131.609375s user + 0.640625s system = 132.250000s CPU (133.5%)
+
+RUN-1003 : finish command "route" in  104.888022s wall, 138.546875s user + 0.687500s system = 139.234375s CPU (132.7%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1093 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10263   out of  19600   52.36%
+#reg                     9402   out of  19600   47.97%
+#le                     12665
+  #lut only              3263   out of  12665   25.76%
+  #reg only              2402   out of  12665   18.97%
+  #lut&reg               7000   out of  12665   55.27%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1832
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1350
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1280
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               962
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    135
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg48_syn_203.f1    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/reg2_syn_162.f1                        3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12665  |9236    |1027    |9432    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |574    |482     |23      |442     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |105    |93      |4       |89      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |42     |42      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10     |10      |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |762    |375     |96      |571     |0       |0       |
+|    u_ADconfig                |AD_config            |196    |132     |25      |149     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |164     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |726    |430     |96      |541     |0       |0       |
+|    u_ADconfig                |AD_config            |169    |128     |25      |124     |0       |0       |
+|    u_gen_sp                  |gen_sp               |256    |163     |71      |116     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3011   |2341    |306     |2120    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |170    |133     |17      |132     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |2808   |2197    |289     |1955    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |3      |3       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2423   |1917    |253     |1617    |22      |0       |
+|        channelPart           |channel_part_8478    |136    |125     |3       |125     |0       |0       |
+|        fifo_adc              |fifo_adc             |61     |52      |9       |43      |0       |0       |
+|        ram_switch            |ram_switch           |1857   |1431    |197     |1192    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |233    |206     |27      |113     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |10     |7       |3       |6       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |10      |0       |0       |
+|          insert              |insert               |1003   |604     |170     |718     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |621    |621     |0       |361     |0       |0       |
+|        read_ram_i            |read_ram             |344    |293     |44      |232     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |215    |175     |40      |155     |0       |0       |
+|          read_ram_data       |read_ram_data        |127    |116     |4       |75      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |302    |210     |36      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3485   |2690    |349     |2115    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |179    |119     |17      |143     |0       |0       |
+|    u_sort                    |sort_rev             |3275   |2551    |332     |1941    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |3      |1       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2812   |2198    |290     |1600    |22      |1       |
+|        channelPart           |channel_part_8478    |244    |238     |3       |152     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |2088   |1583    |197     |1175    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |226    |199     |27      |106     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |10     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |7       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|          insert              |insert               |1028   |559     |170     |735     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |834    |825     |0       |334     |0       |0       |
+|        read_ram_i            |read_ram_rev         |389    |298     |81      |198     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |319    |242     |73      |154     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |70     |56      |8       |44      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9975  
+    #2         2       3763  
+    #3         3       1385  
+    #4         4       539   
+    #5        5-10     1207  
+    #6       11-50     592   
+    #7       51-100     16   
+    #8        >500      1    
+  Average     2.90           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.071863s wall, 3.578125s user + 0.015625s system = 3.593750s CPU (173.5%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1094 MB, peak memory is 1167 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73665, tnet num: 17396, tinst num: 6898, tnode num: 95937, tedge num: 123447.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.592833s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.1%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1099 MB, peak memory is 1167 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17396 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.456024s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.8%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1100 MB, peak memory is 1167 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6898
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17574, pip num: 179932
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 672
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3225 valid insts, and 494817 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.958011s wall, 66.281250s user + 0.171875s system = 66.453125s CPU (667.3%)
+
+RUN-1004 : used memory is 1268 MB, reserved memory is 1264 MB, peak memory is 1384 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_101124.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_103129.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_103129.log
new file mode 100644
index 0000000..e36a4d2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_103129.log
@@ -0,0 +1,2025 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:31:29 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.145038s wall, 2.015625s user + 0.125000s system = 2.140625s CPU (99.8%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 315 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2976 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17712 instances
+RUN-0007 : 7417 luts, 9072 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20290 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13382 nets have 2 pins
+RUN-1001 : 5454 nets have [3 - 5] pins
+RUN-1001 : 1038 nets have [6 - 10] pins
+RUN-1001 : 160 nets have [11 - 20] pins
+RUN-1001 : 181 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     789     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3506     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     59     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 144
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17710 instances, 7417 luts, 9072 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5893 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84787, tnet num: 20112, tinst num: 17710, tnode num: 114956, tedge num: 136080.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.165963s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (99.2%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 514 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20112 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.947394s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (99.5%)
+
+PHY-3001 : Found 3478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.05141e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17710.
+PHY-3001 : Level 1 #clusters 2077.
+PHY-3001 : End clustering;  0.127329s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (110.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.2568e+06, overlap = 496.719
+PHY-3002 : Step(2): len = 1.18977e+06, overlap = 532.625
+PHY-3002 : Step(3): len = 780802, overlap = 637.438
+PHY-3002 : Step(4): len = 735474, overlap = 658.406
+PHY-3002 : Step(5): len = 580228, overlap = 794.75
+PHY-3002 : Step(6): len = 534137, overlap = 826.562
+PHY-3002 : Step(7): len = 433319, overlap = 927.75
+PHY-3002 : Step(8): len = 400698, overlap = 968.062
+PHY-3002 : Step(9): len = 357651, overlap = 1018.97
+PHY-3002 : Step(10): len = 329900, overlap = 1091.75
+PHY-3002 : Step(11): len = 307856, overlap = 1096.44
+PHY-3002 : Step(12): len = 282788, overlap = 1161.97
+PHY-3002 : Step(13): len = 256971, overlap = 1223.5
+PHY-3002 : Step(14): len = 233960, overlap = 1271.62
+PHY-3002 : Step(15): len = 207681, overlap = 1305.44
+PHY-3002 : Step(16): len = 190039, overlap = 1338.25
+PHY-3002 : Step(17): len = 174990, overlap = 1350.78
+PHY-3002 : Step(18): len = 164951, overlap = 1369.59
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.25443e-07
+PHY-3002 : Step(19): len = 163453, overlap = 1347.88
+PHY-3002 : Step(20): len = 184725, overlap = 1276.41
+PHY-3002 : Step(21): len = 183549, overlap = 1235.44
+PHY-3002 : Step(22): len = 187494, overlap = 1208.91
+PHY-3002 : Step(23): len = 185155, overlap = 1179.44
+PHY-3002 : Step(24): len = 184782, overlap = 1166.94
+PHY-3002 : Step(25): len = 181679, overlap = 1170.62
+PHY-3002 : Step(26): len = 183020, overlap = 1159.06
+PHY-3002 : Step(27): len = 179682, overlap = 1171.06
+PHY-3002 : Step(28): len = 180298, overlap = 1178.06
+PHY-3002 : Step(29): len = 175621, overlap = 1183.53
+PHY-3002 : Step(30): len = 175648, overlap = 1181.75
+PHY-3002 : Step(31): len = 172804, overlap = 1151.66
+PHY-3002 : Step(32): len = 173493, overlap = 1148.66
+PHY-3002 : Step(33): len = 172751, overlap = 1149.38
+PHY-3002 : Step(34): len = 172482, overlap = 1158.84
+PHY-3002 : Step(35): len = 172439, overlap = 1170.19
+PHY-3002 : Step(36): len = 173434, overlap = 1182.72
+PHY-3002 : Step(37): len = 170793, overlap = 1177.84
+PHY-3002 : Step(38): len = 172146, overlap = 1168.44
+PHY-3002 : Step(39): len = 170593, overlap = 1177.25
+PHY-3002 : Step(40): len = 170382, overlap = 1168.19
+PHY-3002 : Step(41): len = 170171, overlap = 1178
+PHY-3002 : Step(42): len = 168629, overlap = 1193.59
+PHY-3002 : Step(43): len = 167817, overlap = 1215.44
+PHY-3002 : Step(44): len = 164334, overlap = 1207.47
+PHY-3002 : Step(45): len = 164094, overlap = 1219.25
+PHY-3002 : Step(46): len = 162432, overlap = 1228.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.65089e-06
+PHY-3002 : Step(47): len = 165010, overlap = 1216.91
+PHY-3002 : Step(48): len = 174738, overlap = 1200.16
+PHY-3002 : Step(49): len = 179522, overlap = 1177.56
+PHY-3002 : Step(50): len = 184657, overlap = 1135.28
+PHY-3002 : Step(51): len = 187305, overlap = 1139.72
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.30177e-06
+PHY-3002 : Step(52): len = 197414, overlap = 1130.81
+PHY-3002 : Step(53): len = 215615, overlap = 1022.5
+PHY-3002 : Step(54): len = 222581, overlap = 964.188
+PHY-3002 : Step(55): len = 229508, overlap = 919.125
+PHY-3002 : Step(56): len = 231220, overlap = 915.656
+PHY-3002 : Step(57): len = 233359, overlap = 907.25
+PHY-3002 : Step(58): len = 233422, overlap = 907.531
+PHY-3002 : Step(59): len = 232868, overlap = 932.781
+PHY-3002 : Step(60): len = 231433, overlap = 936.438
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.60354e-06
+PHY-3002 : Step(61): len = 246175, overlap = 877.344
+PHY-3002 : Step(62): len = 266193, overlap = 759.125
+PHY-3002 : Step(63): len = 277871, overlap = 684.188
+PHY-3002 : Step(64): len = 285890, overlap = 647.219
+PHY-3002 : Step(65): len = 288351, overlap = 623.625
+PHY-3002 : Step(66): len = 288814, overlap = 603.188
+PHY-3002 : Step(67): len = 285579, overlap = 612.938
+PHY-3002 : Step(68): len = 284694, overlap = 612.438
+PHY-3002 : Step(69): len = 283624, overlap = 605.594
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.32071e-05
+PHY-3002 : Step(70): len = 303936, overlap = 545.062
+PHY-3002 : Step(71): len = 323406, overlap = 468.812
+PHY-3002 : Step(72): len = 328903, overlap = 441.938
+PHY-3002 : Step(73): len = 331937, overlap = 424.656
+PHY-3002 : Step(74): len = 331402, overlap = 435
+PHY-3002 : Step(75): len = 330663, overlap = 411.375
+PHY-3002 : Step(76): len = 327912, overlap = 409.75
+PHY-3002 : Step(77): len = 327959, overlap = 413.312
+PHY-3002 : Step(78): len = 327127, overlap = 419.5
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.64142e-05
+PHY-3002 : Step(79): len = 345131, overlap = 390.312
+PHY-3002 : Step(80): len = 360718, overlap = 357.344
+PHY-3002 : Step(81): len = 365108, overlap = 328.094
+PHY-3002 : Step(82): len = 368656, overlap = 333.438
+PHY-3002 : Step(83): len = 367729, overlap = 344.562
+PHY-3002 : Step(84): len = 370025, overlap = 351.625
+PHY-3002 : Step(85): len = 369381, overlap = 347
+PHY-3002 : Step(86): len = 370685, overlap = 350.438
+PHY-3002 : Step(87): len = 367967, overlap = 345.125
+PHY-3002 : Step(88): len = 367787, overlap = 352.719
+PHY-3002 : Step(89): len = 366030, overlap = 326.812
+PHY-3002 : Step(90): len = 366035, overlap = 312.25
+PHY-3002 : Step(91): len = 365426, overlap = 299.031
+PHY-3002 : Step(92): len = 365381, overlap = 295.906
+PHY-3002 : Step(93): len = 363994, overlap = 294.625
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.28284e-05
+PHY-3002 : Step(94): len = 384703, overlap = 271.875
+PHY-3002 : Step(95): len = 398247, overlap = 263.844
+PHY-3002 : Step(96): len = 395893, overlap = 276.094
+PHY-3002 : Step(97): len = 395544, overlap = 286.156
+PHY-3002 : Step(98): len = 398175, overlap = 277.312
+PHY-3002 : Step(99): len = 401026, overlap = 263.781
+PHY-3002 : Step(100): len = 397681, overlap = 268.25
+PHY-3002 : Step(101): len = 399432, overlap = 265.625
+PHY-3002 : Step(102): len = 402044, overlap = 260.875
+PHY-3002 : Step(103): len = 404004, overlap = 258.812
+PHY-3002 : Step(104): len = 400910, overlap = 259.844
+PHY-3002 : Step(105): len = 399469, overlap = 269.844
+PHY-3002 : Step(106): len = 400229, overlap = 268.312
+PHY-3002 : Step(107): len = 401758, overlap = 259.969
+PHY-3002 : Step(108): len = 399616, overlap = 245.844
+PHY-3002 : Step(109): len = 400280, overlap = 242.906
+PHY-3002 : Step(110): len = 400917, overlap = 238.406
+PHY-3002 : Step(111): len = 401659, overlap = 228.938
+PHY-3002 : Step(112): len = 399014, overlap = 232.312
+PHY-3002 : Step(113): len = 398670, overlap = 239.688
+PHY-3002 : Step(114): len = 398726, overlap = 244.344
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000105657
+PHY-3002 : Step(115): len = 417065, overlap = 229.844
+PHY-3002 : Step(116): len = 427437, overlap = 221.031
+PHY-3002 : Step(117): len = 424444, overlap = 207.344
+PHY-3002 : Step(118): len = 424018, overlap = 214.375
+PHY-3002 : Step(119): len = 428456, overlap = 211.156
+PHY-3002 : Step(120): len = 431723, overlap = 210.5
+PHY-3002 : Step(121): len = 431013, overlap = 204.312
+PHY-3002 : Step(122): len = 432049, overlap = 210.906
+PHY-3002 : Step(123): len = 433006, overlap = 204.781
+PHY-3002 : Step(124): len = 433572, overlap = 207.094
+PHY-3002 : Step(125): len = 430881, overlap = 220.5
+PHY-3002 : Step(126): len = 431465, overlap = 228.406
+PHY-3002 : Step(127): len = 432667, overlap = 212.469
+PHY-3002 : Step(128): len = 434051, overlap = 212.406
+PHY-3002 : Step(129): len = 431761, overlap = 218.156
+PHY-3002 : Step(130): len = 431809, overlap = 211.719
+PHY-3002 : Step(131): len = 433137, overlap = 210.031
+PHY-3002 : Step(132): len = 434483, overlap = 201.312
+PHY-3002 : Step(133): len = 432512, overlap = 202.125
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000204329
+PHY-3002 : Step(134): len = 443496, overlap = 193.219
+PHY-3002 : Step(135): len = 451882, overlap = 194.344
+PHY-3002 : Step(136): len = 452510, overlap = 182.906
+PHY-3002 : Step(137): len = 454040, overlap = 184.969
+PHY-3002 : Step(138): len = 457802, overlap = 173.5
+PHY-3002 : Step(139): len = 461184, overlap = 169.344
+PHY-3002 : Step(140): len = 460353, overlap = 162.312
+PHY-3002 : Step(141): len = 461712, overlap = 167.75
+PHY-3002 : Step(142): len = 464817, overlap = 161.469
+PHY-3002 : Step(143): len = 467232, overlap = 154.25
+PHY-3002 : Step(144): len = 465011, overlap = 160
+PHY-3002 : Step(145): len = 465044, overlap = 162.75
+PHY-3002 : Step(146): len = 467314, overlap = 160.469
+PHY-3002 : Step(147): len = 469291, overlap = 161.469
+PHY-3002 : Step(148): len = 467444, overlap = 174.062
+PHY-3002 : Step(149): len = 466870, overlap = 177.812
+PHY-3002 : Step(150): len = 468028, overlap = 174.844
+PHY-3002 : Step(151): len = 468975, overlap = 173.312
+PHY-3002 : Step(152): len = 467578, overlap = 177.406
+PHY-3002 : Step(153): len = 467420, overlap = 171.406
+PHY-3002 : Step(154): len = 467997, overlap = 171.062
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000405013
+PHY-3002 : Step(155): len = 479035, overlap = 171.094
+PHY-3002 : Step(156): len = 488672, overlap = 167.188
+PHY-3002 : Step(157): len = 489432, overlap = 165.5
+PHY-3002 : Step(158): len = 491008, overlap = 158.594
+PHY-3002 : Step(159): len = 493455, overlap = 148.062
+PHY-3002 : Step(160): len = 495774, overlap = 150.031
+PHY-3002 : Step(161): len = 495055, overlap = 154.562
+PHY-3002 : Step(162): len = 495067, overlap = 144.25
+PHY-3002 : Step(163): len = 496827, overlap = 140.781
+PHY-3002 : Step(164): len = 498413, overlap = 137.5
+PHY-3002 : Step(165): len = 496852, overlap = 139.5
+PHY-3002 : Step(166): len = 496142, overlap = 132.25
+PHY-3002 : Step(167): len = 496323, overlap = 136.031
+PHY-3002 : Step(168): len = 496819, overlap = 137.719
+PHY-3002 : Step(169): len = 496394, overlap = 133.906
+PHY-3002 : Step(170): len = 496111, overlap = 135.344
+PHY-3002 : Step(171): len = 496137, overlap = 131.156
+PHY-3002 : Step(172): len = 496368, overlap = 131.625
+PHY-3002 : Step(173): len = 496064, overlap = 125.406
+PHY-3002 : Step(174): len = 496202, overlap = 126.281
+PHY-3002 : Step(175): len = 496220, overlap = 127.625
+PHY-3002 : Step(176): len = 496129, overlap = 125.938
+PHY-3002 : Step(177): len = 495975, overlap = 133.406
+PHY-3002 : Step(178): len = 495945, overlap = 129.656
+PHY-3002 : Step(179): len = 496022, overlap = 130.469
+PHY-3002 : Step(180): len = 496041, overlap = 128.406
+PHY-3002 : Step(181): len = 495478, overlap = 125.375
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000770106
+PHY-3002 : Step(182): len = 500161, overlap = 125.562
+PHY-3002 : Step(183): len = 505021, overlap = 123.156
+PHY-3002 : Step(184): len = 506396, overlap = 123.438
+PHY-3002 : Step(185): len = 507484, overlap = 119.188
+PHY-3002 : Step(186): len = 508850, overlap = 118.375
+PHY-3002 : Step(187): len = 509937, overlap = 114.156
+PHY-3002 : Step(188): len = 510113, overlap = 116.469
+PHY-3002 : Step(189): len = 510538, overlap = 117.188
+PHY-3002 : Step(190): len = 511588, overlap = 116.5
+PHY-3002 : Step(191): len = 512930, overlap = 115.219
+PHY-3002 : Step(192): len = 513299, overlap = 117.031
+PHY-3002 : Step(193): len = 513766, overlap = 118.344
+PHY-3002 : Step(194): len = 514423, overlap = 119.719
+PHY-3002 : Step(195): len = 514543, overlap = 121.344
+PHY-3002 : Step(196): len = 514167, overlap = 125.375
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00134589
+PHY-3002 : Step(197): len = 516445, overlap = 125.625
+PHY-3002 : Step(198): len = 520425, overlap = 125.969
+PHY-3002 : Step(199): len = 522950, overlap = 115.344
+PHY-3002 : Step(200): len = 524614, overlap = 113.594
+PHY-3002 : Step(201): len = 526083, overlap = 118.281
+PHY-3002 : Step(202): len = 526781, overlap = 118.156
+PHY-3002 : Step(203): len = 526769, overlap = 111.562
+PHY-3002 : Step(204): len = 527249, overlap = 114.438
+PHY-3002 : Step(205): len = 529017, overlap = 114.781
+PHY-3002 : Step(206): len = 530239, overlap = 113.438
+PHY-3002 : Step(207): len = 530113, overlap = 115.875
+PHY-3002 : Step(208): len = 530125, overlap = 116.25
+PHY-3002 : Step(209): len = 530560, overlap = 115.844
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00228195
+PHY-3002 : Step(210): len = 532705, overlap = 116.062
+PHY-3002 : Step(211): len = 535487, overlap = 115.094
+PHY-3002 : Step(212): len = 536356, overlap = 112.25
+PHY-3002 : Step(213): len = 536935, overlap = 112.375
+PHY-3002 : Step(214): len = 537632, overlap = 112.469
+PHY-3002 : Step(215): len = 538589, overlap = 112.562
+PHY-3002 : Step(216): len = 540027, overlap = 108.844
+PHY-3002 : Step(217): len = 541607, overlap = 107.625
+PHY-3002 : Step(218): len = 542240, overlap = 112.938
+PHY-3002 : Step(219): len = 542635, overlap = 112.281
+PHY-3002 : Step(220): len = 542935, overlap = 111.594
+PHY-3002 : Step(221): len = 543032, overlap = 114.438
+PHY-3002 : Step(222): len = 543024, overlap = 109.344
+PHY-3001 : :::14::: Try harder cell spreading with beta_ = 0.0036922
+PHY-3002 : Step(223): len = 544381, overlap = 107.156
+PHY-3002 : Step(224): len = 548494, overlap = 107.594
+PHY-3002 : Step(225): len = 551161, overlap = 109.469
+PHY-3002 : Step(226): len = 555581, overlap = 113.906
+PHY-3002 : Step(227): len = 558666, overlap = 107.531
+PHY-3002 : Step(228): len = 560608, overlap = 112.25
+PHY-3002 : Step(229): len = 560883, overlap = 114.781
+PHY-3002 : Step(230): len = 561123, overlap = 115.406
+PHY-3002 : Step(231): len = 561979, overlap = 116.906
+PHY-3002 : Step(232): len = 562365, overlap = 115.031
+PHY-3002 : Step(233): len = 562497, overlap = 116.062
+PHY-3002 : Step(234): len = 562227, overlap = 120.469
+PHY-3002 : Step(235): len = 561433, overlap = 118.188
+PHY-3002 : Step(236): len = 560571, overlap = 118.719
+PHY-3002 : Step(237): len = 560306, overlap = 119.719
+PHY-3002 : Step(238): len = 560094, overlap = 122.562
+PHY-3002 : Step(239): len = 559572, overlap = 125.406
+PHY-3002 : Step(240): len = 558801, overlap = 123.75
+PHY-3002 : Step(241): len = 558325, overlap = 123.438
+PHY-3002 : Step(242): len = 558167, overlap = 122.75
+PHY-3001 : :::15::: Try harder cell spreading with beta_ = 0.00622693
+PHY-3002 : Step(243): len = 558657, overlap = 121.875
+PHY-3002 : Step(244): len = 559588, overlap = 122.062
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.013272s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (117.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20290.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709576, over cnt = 1524(4%), over = 7325, worst = 40
+PHY-1001 : End global iterations;  0.719918s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 84.85, top5 = 62.56, top10 = 52.84, top15 = 47.05.
+PHY-3001 : End congestion estimation;  0.972857s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (125.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20112 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.881442s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (101.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.19583e-05
+PHY-3002 : Step(245): len = 645848, overlap = 63.7188
+PHY-3002 : Step(246): len = 651056, overlap = 57.8125
+PHY-3002 : Step(247): len = 646760, overlap = 61.6875
+PHY-3002 : Step(248): len = 644024, overlap = 65.5625
+PHY-3002 : Step(249): len = 654192, overlap = 49.7188
+PHY-3002 : Step(250): len = 679797, overlap = 66.8125
+PHY-3002 : Step(251): len = 682096, overlap = 54.4688
+PHY-3002 : Step(252): len = 680492, overlap = 40.0938
+PHY-3002 : Step(253): len = 681820, overlap = 42.125
+PHY-3002 : Step(254): len = 687988, overlap = 38
+PHY-3002 : Step(255): len = 691735, overlap = 40.5625
+PHY-3002 : Step(256): len = 694679, overlap = 40.125
+PHY-3002 : Step(257): len = 701203, overlap = 44.9688
+PHY-3002 : Step(258): len = 705426, overlap = 47.0938
+PHY-3002 : Step(259): len = 706588, overlap = 50.75
+PHY-3002 : Step(260): len = 707489, overlap = 52.125
+PHY-3002 : Step(261): len = 711114, overlap = 55.625
+PHY-3002 : Step(262): len = 715333, overlap = 52.7812
+PHY-3002 : Step(263): len = 718383, overlap = 46.5
+PHY-3002 : Step(264): len = 718766, overlap = 46.4062
+PHY-3002 : Step(265): len = 718469, overlap = 43.6875
+PHY-3002 : Step(266): len = 718646, overlap = 41.2188
+PHY-3002 : Step(267): len = 718653, overlap = 42.1875
+PHY-3002 : Step(268): len = 720500, overlap = 44.0312
+PHY-3002 : Step(269): len = 720085, overlap = 40.5312
+PHY-3002 : Step(270): len = 718583, overlap = 39.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000183917
+PHY-3002 : Step(271): len = 720159, overlap = 40.2812
+PHY-3002 : Step(272): len = 725411, overlap = 43.5
+PHY-3002 : Step(273): len = 728211, overlap = 41.375
+PHY-3002 : Step(274): len = 727180, overlap = 41.625
+PHY-3002 : Step(275): len = 726794, overlap = 41.2188
+PHY-3002 : Step(276): len = 727071, overlap = 41.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000367833
+PHY-3002 : Step(277): len = 732605, overlap = 45.125
+PHY-3002 : Step(278): len = 739669, overlap = 46.4375
+PHY-3002 : Step(279): len = 743210, overlap = 45.125
+PHY-3002 : Step(280): len = 746860, overlap = 41.75
+PHY-3002 : Step(281): len = 747461, overlap = 39.5938
+PHY-3002 : Step(282): len = 748379, overlap = 40.0312
+PHY-3002 : Step(283): len = 746864, overlap = 40.1875
+PHY-3002 : Step(284): len = 745482, overlap = 40
+PHY-3002 : Step(285): len = 744268, overlap = 40.875
+PHY-3002 : Step(286): len = 746144, overlap = 39.2188
+PHY-3002 : Step(287): len = 749118, overlap = 39.1562
+PHY-3002 : Step(288): len = 749431, overlap = 40.3125
+PHY-3002 : Step(289): len = 750129, overlap = 39.5625
+PHY-3002 : Step(290): len = 749017, overlap = 39.3125
+PHY-3002 : Step(291): len = 749046, overlap = 42.3125
+PHY-3002 : Step(292): len = 748742, overlap = 43.6562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000682212
+PHY-3002 : Step(293): len = 749332, overlap = 40.5938
+PHY-3002 : Step(294): len = 761359, overlap = 40.7812
+PHY-3002 : Step(295): len = 778867, overlap = 36.0312
+PHY-3002 : Step(296): len = 777676, overlap = 38.4375
+PHY-3002 : Step(297): len = 774420, overlap = 42.2188
+PHY-3002 : Step(298): len = 771685, overlap = 43.9688
+PHY-3002 : Step(299): len = 770869, overlap = 43.8125
+PHY-3002 : Step(300): len = 772215, overlap = 43
+PHY-3002 : Step(301): len = 772305, overlap = 42.9375
+PHY-3002 : Step(302): len = 773671, overlap = 46.6562
+PHY-3002 : Step(303): len = 775122, overlap = 41.6562
+PHY-3002 : Step(304): len = 775039, overlap = 41.6875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.0013296
+PHY-3002 : Step(305): len = 777102, overlap = 41.0312
+PHY-3002 : Step(306): len = 780420, overlap = 36.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 45/20290.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 856304, over cnt = 2765(7%), over = 14605, worst = 51
+PHY-1001 : End global iterations;  1.322822s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (139.4%)
+
+PHY-1001 : Congestion index: top1 = 120.22, top5 = 82.47, top10 = 68.63, top15 = 61.06.
+PHY-3001 : End congestion estimation;  1.595008s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (133.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20112 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.065815s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000117216
+PHY-3002 : Step(307): len = 780097, overlap = 254.75
+PHY-3002 : Step(308): len = 780846, overlap = 218.438
+PHY-3002 : Step(309): len = 773489, overlap = 203.5
+PHY-3002 : Step(310): len = 766877, overlap = 186.438
+PHY-3002 : Step(311): len = 761795, overlap = 150.219
+PHY-3002 : Step(312): len = 757061, overlap = 134.219
+PHY-3002 : Step(313): len = 751854, overlap = 133.25
+PHY-3002 : Step(314): len = 746999, overlap = 128
+PHY-3002 : Step(315): len = 743634, overlap = 127.938
+PHY-3002 : Step(316): len = 739107, overlap = 115.969
+PHY-3002 : Step(317): len = 733257, overlap = 121.188
+PHY-3002 : Step(318): len = 728082, overlap = 120.812
+PHY-3002 : Step(319): len = 723438, overlap = 117.125
+PHY-3002 : Step(320): len = 719381, overlap = 117.719
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000234432
+PHY-3002 : Step(321): len = 720861, overlap = 113.656
+PHY-3002 : Step(322): len = 724399, overlap = 111.062
+PHY-3002 : Step(323): len = 725852, overlap = 106.594
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000468865
+PHY-3002 : Step(324): len = 731583, overlap = 99.125
+PHY-3002 : Step(325): len = 739648, overlap = 91.5
+PHY-3002 : Step(326): len = 743907, overlap = 84.5938
+PHY-3002 : Step(327): len = 742628, overlap = 83.25
+PHY-3002 : Step(328): len = 741532, overlap = 79.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00093773
+PHY-3002 : Step(329): len = 743404, overlap = 76.1562
+PHY-3002 : Step(330): len = 748380, overlap = 72.2188
+PHY-3002 : Step(331): len = 755320, overlap = 66.2812
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84787, tnet num: 20112, tinst num: 17710, tnode num: 114956, tedge num: 136080.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.425663s wall, 1.406250s user + 0.015625s system = 1.421875s CPU (99.7%)
+
+RUN-1004 : used memory is 580 MB, reserved memory is 563 MB, peak memory is 717 MB
+OPT-1001 : Total overflow 408.34 peak overflow 3.88
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 703/20290.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 853640, over cnt = 3099(8%), over = 12028, worst = 74
+PHY-1001 : End global iterations;  1.288509s wall, 1.781250s user + 0.015625s system = 1.796875s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 85.09, top5 = 65.61, top10 = 57.83, top15 = 53.07.
+PHY-1001 : End incremental global routing;  1.600286s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (131.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20112 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.905314s wall, 0.843750s user + 0.062500s system = 0.906250s CPU (100.1%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17575 has valid locations, 335 needs to be replaced
+PHY-3001 : design contains 17995 instances, 7520 luts, 9254 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6017 pins
+PHY-3001 : Found 3508 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 778151
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16723/20575.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 869976, over cnt = 3157(8%), over = 12116, worst = 74
+PHY-1001 : End global iterations;  0.241191s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (149.0%)
+
+PHY-1001 : Congestion index: top1 = 84.53, top5 = 65.46, top10 = 57.96, top15 = 53.36.
+PHY-3001 : End congestion estimation;  0.490443s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (124.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85969, tnet num: 20397, tinst num: 17995, tnode num: 116728, tedge num: 137874.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.466856s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.1%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 617 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20397 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.787495s wall, 2.734375s user + 0.046875s system = 2.781250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(332): len = 776905, overlap = 0.625
+PHY-3002 : Step(333): len = 776346, overlap = 0.5625
+PHY-3002 : Step(334): len = 776314, overlap = 0.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16854/20575.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 867728, over cnt = 3146(8%), over = 12157, worst = 74
+PHY-1001 : End global iterations;  0.184110s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (135.8%)
+
+PHY-1001 : Congestion index: top1 = 85.26, top5 = 66.12, top10 = 58.39, top15 = 53.67.
+PHY-3001 : End congestion estimation;  0.439607s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (113.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20397 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.954965s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000554624
+PHY-3002 : Step(335): len = 776229, overlap = 68.6875
+PHY-3002 : Step(336): len = 776394, overlap = 68.4688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00110925
+PHY-3002 : Step(337): len = 776464, overlap = 68.25
+PHY-3002 : Step(338): len = 777142, overlap = 68.125
+PHY-3001 : Final: Len = 777142, Over = 68.125
+PHY-3001 : End incremental placement;  5.307639s wall, 5.609375s user + 0.250000s system = 5.859375s CPU (110.4%)
+
+OPT-1001 : Total overflow 413.53 peak overflow 3.88
+OPT-1001 : End high-fanout net optimization;  8.346591s wall, 9.078125s user + 0.328125s system = 9.406250s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 714, peak = 742.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16781/20575.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 871056, over cnt = 3093(8%), over = 11173, worst = 74
+PHY-1002 : len = 923992, over cnt = 2275(6%), over = 5995, worst = 59
+PHY-1002 : len = 968040, over cnt = 925(2%), over = 2235, worst = 22
+PHY-1002 : len = 987584, over cnt = 330(0%), over = 898, worst = 22
+PHY-1002 : len = 1.00152e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.073245s wall, 2.812500s user + 0.046875s system = 2.859375s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 63.04, top5 = 55.76, top10 = 51.82, top15 = 49.24.
+OPT-1001 : End congestion update;  2.345591s wall, 3.078125s user + 0.046875s system = 3.125000s CPU (133.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20397 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.874358s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (98.3%)
+
+OPT-0007 : Start: WNS -968 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1478 NUM_FEPS 2 with 60 cells processed and 7200 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1478 NUM_FEPS 2 with 28 cells processed and 1500 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1478 NUM_FEPS 2 with 11 cells processed and 900 slack improved
+OPT-0007 : Iter 4: improved WNS -968 TNS -1478 NUM_FEPS 2 with 5 cells processed and 100 slack improved
+OPT-1001 : End global optimization;  3.259823s wall, 3.968750s user + 0.046875s system = 4.015625s CPU (123.2%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 696, peak = 742.
+OPT-1001 : End physical optimization;  13.766054s wall, 15.281250s user + 0.421875s system = 15.703125s CPU (114.1%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7520 LUT to BLE ...
+SYN-4008 : Packed 7520 LUT and 3130 SEQ to BLE.
+SYN-4003 : Packing 6124 remaining SEQ's ...
+SYN-4005 : Packed 4019 SEQ with LUT/SLICE
+SYN-4006 : 666 single LUT's are left
+SYN-4006 : 2105 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9625/13372 primitive instances ...
+PHY-3001 : End packing;  1.600788s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6718 instances
+RUN-1001 : 3285 mslices, 3285 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17549 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10013 nets have 2 pins
+RUN-1001 : 5709 nets have [3 - 5] pins
+RUN-1001 : 1131 nets have [6 - 10] pins
+RUN-1001 : 320 nets have [11 - 20] pins
+RUN-1001 : 343 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6716 instances, 6570 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3501 pins
+PHY-3001 : Found 1566 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 783469, Over = 235
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7391/17549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940936, over cnt = 2015(5%), over = 3361, worst = 8
+PHY-1002 : len = 948640, over cnt = 1355(3%), over = 1964, worst = 8
+PHY-1002 : len = 963408, over cnt = 489(1%), over = 665, worst = 8
+PHY-1002 : len = 971392, over cnt = 107(0%), over = 139, worst = 4
+PHY-1002 : len = 973664, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations;  1.705541s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (142.9%)
+
+PHY-1001 : Congestion index: top1 = 61.68, top5 = 53.61, top10 = 49.68, top15 = 47.10.
+PHY-3001 : End congestion estimation;  2.106719s wall, 2.812500s user + 0.015625s system = 2.828125s CPU (134.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73586, tnet num: 17371, tinst num: 6716, tnode num: 95974, tedge num: 123404.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.672408s wall, 1.640625s user + 0.031250s system = 1.671875s CPU (100.0%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 612 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.589021s wall, 2.546875s user + 0.031250s system = 2.578125s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.19077e-05
+PHY-3002 : Step(339): len = 769365, overlap = 237.5
+PHY-3002 : Step(340): len = 762055, overlap = 234.75
+PHY-3002 : Step(341): len = 756396, overlap = 239
+PHY-3002 : Step(342): len = 752124, overlap = 238.25
+PHY-3002 : Step(343): len = 748045, overlap = 241.5
+PHY-3002 : Step(344): len = 742485, overlap = 248
+PHY-3002 : Step(345): len = 738615, overlap = 264.25
+PHY-3002 : Step(346): len = 735325, overlap = 265.25
+PHY-3002 : Step(347): len = 731722, overlap = 268.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103815
+PHY-3002 : Step(348): len = 735244, overlap = 254.75
+PHY-3002 : Step(349): len = 739836, overlap = 243.25
+PHY-3002 : Step(350): len = 739922, overlap = 242.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000207631
+PHY-3002 : Step(351): len = 750176, overlap = 231
+PHY-3002 : Step(352): len = 758990, overlap = 213
+PHY-3002 : Step(353): len = 757012, overlap = 211
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.341821s wall, 0.421875s user + 0.484375s system = 0.906250s CPU (265.1%)
+
+PHY-3001 : Trial Legalized: Len = 970648
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 604/17549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09354e+06, over cnt = 2883(8%), over = 4947, worst = 8
+PHY-1002 : len = 1.10926e+06, over cnt = 1880(5%), over = 2940, worst = 8
+PHY-1002 : len = 1.12869e+06, over cnt = 1015(2%), over = 1495, worst = 8
+PHY-1002 : len = 1.14283e+06, over cnt = 379(1%), over = 559, worst = 8
+PHY-1002 : len = 1.15181e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.494223s wall, 3.671875s user + 0.015625s system = 3.687500s CPU (147.8%)
+
+PHY-1001 : Congestion index: top1 = 67.52, top5 = 60.85, top10 = 56.43, top15 = 53.44.
+PHY-3001 : End congestion estimation;  2.946547s wall, 4.125000s user + 0.015625s system = 4.140625s CPU (140.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.876518s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000154822
+PHY-3002 : Step(354): len = 929795, overlap = 65
+PHY-3002 : Step(355): len = 909510, overlap = 88.75
+PHY-3002 : Step(356): len = 893994, overlap = 110.5
+PHY-3002 : Step(357): len = 877314, overlap = 144.25
+PHY-3002 : Step(358): len = 864861, overlap = 162.75
+PHY-3002 : Step(359): len = 854675, overlap = 171.5
+PHY-3002 : Step(360): len = 846164, overlap = 183.25
+PHY-3002 : Step(361): len = 839360, overlap = 185.25
+PHY-3002 : Step(362): len = 833355, overlap = 185.25
+PHY-3002 : Step(363): len = 828335, overlap = 188.5
+PHY-3002 : Step(364): len = 824744, overlap = 190
+PHY-3002 : Step(365): len = 820972, overlap = 189.5
+PHY-3002 : Step(366): len = 816555, overlap = 189.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000309645
+PHY-3002 : Step(367): len = 820877, overlap = 181.25
+PHY-3002 : Step(368): len = 824217, overlap = 174.75
+PHY-3002 : Step(369): len = 825830, overlap = 173
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000534738
+PHY-3002 : Step(370): len = 832425, overlap = 171.25
+PHY-3002 : Step(371): len = 835355, overlap = 166.5
+PHY-3002 : Step(372): len = 837399, overlap = 166.25
+PHY-3002 : Step(373): len = 838727, overlap = 165.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.089134s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (105.2%)
+
+PHY-3001 : Legalized: Len = 923960, Over = 0
+PHY-3001 : Spreading special nets. 451 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.121530s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (102.9%)
+
+PHY-3001 : 684 instances has been re-located, deltaX = 308, deltaY = 444, maxDist = 13.
+PHY-3001 : Final: Len = 936354, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73586, tnet num: 17371, tinst num: 6719, tnode num: 95974, tedge num: 123404.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.861468s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.9%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 644 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 2921/17549.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06987e+06, over cnt = 2717(7%), over = 4397, worst = 8
+PHY-1002 : len = 1.0853e+06, over cnt = 1521(4%), over = 2143, worst = 7
+PHY-1002 : len = 1.1005e+06, over cnt = 689(1%), over = 955, worst = 6
+PHY-1002 : len = 1.10946e+06, over cnt = 239(0%), over = 342, worst = 5
+PHY-1002 : len = 1.11462e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.422067s wall, 3.406250s user + 0.031250s system = 3.437500s CPU (141.9%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 58.72, top10 = 54.34, top15 = 51.57.
+PHY-1001 : End incremental global routing;  2.792082s wall, 3.765625s user + 0.031250s system = 3.796875s CPU (136.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17371 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.869058s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.7%)
+
+OPT-1001 : 7 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6624 has valid locations, 33 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 940305
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16082/17579.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.1189e+06, over cnt = 106(0%), over = 116, worst = 5
+PHY-1002 : len = 1.11934e+06, over cnt = 45(0%), over = 47, worst = 2
+PHY-1002 : len = 1.1197e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.11978e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.11989e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.830566s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.7%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 58.76, top10 = 54.39, top15 = 51.62.
+PHY-3001 : End congestion estimation;  1.153397s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73857, tnet num: 17401, tinst num: 6745, tnode num: 96303, tedge num: 123750.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.866778s wall, 1.812500s user + 0.046875s system = 1.859375s CPU (99.6%)
+
+RUN-1004 : used memory is 671 MB, reserved memory is 672 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17401 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.754995s wall, 2.687500s user + 0.062500s system = 2.750000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(374): len = 939649, overlap = 0
+PHY-3002 : Step(375): len = 939250, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16068/17579.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.11824e+06, over cnt = 74(0%), over = 91, worst = 5
+PHY-1002 : len = 1.11846e+06, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 1.11892e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.11899e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.11903e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.129971s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (80.2%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 58.73, top10 = 54.38, top15 = 51.61.
+PHY-3001 : End congestion estimation;  1.450684s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (85.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17401 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868432s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00142795
+PHY-3002 : Step(376): len = 939411, overlap = 1.5
+PHY-3002 : Step(377): len = 939439, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.006385s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 939624, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064025s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.6%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 4, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 939690, Over = 0
+PHY-3001 : End incremental placement;  6.715261s wall, 6.687500s user + 0.156250s system = 6.843750s CPU (101.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.867116s wall, 11.828125s user + 0.187500s system = 12.015625s CPU (110.6%)
+
+OPT-1001 : Current memory(MB): used = 750, reserve = 747, peak = 753.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16038/17579.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.11931e+06, over cnt = 99(0%), over = 125, worst = 5
+PHY-1002 : len = 1.11958e+06, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 1.11986e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.1199e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.11994e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.856744s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (113.1%)
+
+PHY-1001 : Congestion index: top1 = 65.45, top5 = 58.73, top10 = 54.36, top15 = 51.57.
+OPT-1001 : End congestion update;  1.209930s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (109.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17401 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.729701s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.5%)
+
+OPT-0007 : Start: WNS -1483 TNS -2068 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 941094, Over = 0
+PHY-3001 : Spreading special nets. 21 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060688s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.0%)
+
+PHY-3001 : 29 instances has been re-located, deltaX = 14, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 941266, Over = 0
+PHY-3001 : End incremental legalization;  0.375876s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.8%)
+
+OPT-0007 : Iter 1: improved WNS -1383 TNS -1918 NUM_FEPS 2 with 27 cells processed and 6554 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6657 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6745 instances, 6596 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3584 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 941548, Over = 0
+PHY-3001 : Spreading special nets. 15 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060237s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.8%)
+
+PHY-3001 : 20 instances has been re-located, deltaX = 7, deltaY = 16, maxDist = 2.
+PHY-3001 : Final: Len = 941862, Over = 0
+PHY-3001 : End incremental legalization;  0.378877s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.0%)
+
+OPT-0007 : Iter 2: improved WNS -1383 TNS -1918 NUM_FEPS 2 with 19 cells processed and 1493 slack improved
+OPT-0007 : Iter 3: improved WNS -1383 TNS -1918 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.956514s wall, 3.171875s user + 0.000000s system = 3.171875s CPU (107.3%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 748, peak = 754.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17401 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.717094s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15926/17579.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.12194e+06, over cnt = 137(0%), over = 160, worst = 4
+PHY-1002 : len = 1.12181e+06, over cnt = 81(0%), over = 85, worst = 2
+PHY-1002 : len = 1.12234e+06, over cnt = 23(0%), over = 25, worst = 2
+PHY-1002 : len = 1.12259e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.12273e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.923213s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (113.4%)
+
+PHY-1001 : Congestion index: top1 = 65.30, top5 = 58.57, top10 = 54.32, top15 = 51.54.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17401 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.719059s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.0%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1333 TNS -1868 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 64.896552
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1333ps with logic level 2 
+RUN-1001 :       #2 path slack -1247ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17579 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17579 nets
+OPT-1001 : End physical optimization;  18.734184s wall, 20.109375s user + 0.218750s system = 20.328125s CPU (108.5%)
+
+RUN-1003 : finish command "place" in  65.270591s wall, 103.906250s user + 7.031250s system = 110.937500s CPU (170.0%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 611 MB, peak memory is 754 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.670681s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (174.0%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 613 MB, peak memory is 754 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6747 instances
+RUN-1001 : 3299 mslices, 3297 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17579 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10011 nets have 2 pins
+RUN-1001 : 5707 nets have [3 - 5] pins
+RUN-1001 : 1145 nets have [6 - 10] pins
+RUN-1001 : 326 nets have [11 - 20] pins
+RUN-1001 : 361 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73857, tnet num: 17401, tinst num: 6745, tnode num: 96303, tedge num: 123750.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.625735s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.0%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 638 MB, peak memory is 754 MB
+PHY-1001 : 3299 mslices, 3297 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17401 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.05578e+06, over cnt = 2849(8%), over = 4704, worst = 9
+PHY-1002 : len = 1.07254e+06, over cnt = 1816(5%), over = 2650, worst = 6
+PHY-1002 : len = 1.0945e+06, over cnt = 686(1%), over = 945, worst = 5
+PHY-1002 : len = 1.10932e+06, over cnt = 10(0%), over = 16, worst = 3
+PHY-1002 : len = 1.10961e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.982006s wall, 4.062500s user + 0.046875s system = 4.109375s CPU (137.8%)
+
+PHY-1001 : Congestion index: top1 = 65.78, top5 = 58.30, top10 = 54.09, top15 = 51.30.
+PHY-1001 : End global routing;  3.330309s wall, 4.406250s user + 0.046875s system = 4.453125s CPU (133.7%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 724, reserve = 725, peak = 754.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 995, reserve = 993, peak = 995.
+PHY-1001 : End build detailed router design. 3.996704s wall, 3.984375s user + 0.015625s system = 4.000000s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271528, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.314789s wall, 5.296875s user + 0.015625s system = 5.312500s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271584, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.467965s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1030, peak = 1031.
+PHY-1001 : End phase 1; 5.796065s wall, 5.781250s user + 0.015625s system = 5.796875s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.59227e+06, over cnt = 2083(0%), over = 2098, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1049, reserve = 1046, peak = 1049.
+PHY-1001 : End initial routed; 50.179071s wall, 84.359375s user + 0.500000s system = 84.859375s CPU (169.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16501(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.175   |  -4.257   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.294024s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1059, reserve = 1056, peak = 1059.
+PHY-1001 : End phase 2; 53.473158s wall, 87.656250s user + 0.500000s system = 88.156250s CPU (164.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.052ns STNS -4.075ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.152285s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.6%)
+
+PHY-1022 : len = 2.5923e+06, over cnt = 2086(0%), over = 2101, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.418898s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.55223e+06, over cnt = 759(0%), over = 760, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 3.295927s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (119.9%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.54712e+06, over cnt = 183(0%), over = 183, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.361400s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (143.5%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.54621e+06, over cnt = 25(0%), over = 25, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.648327s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (135.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.54634e+06, over cnt = 11(0%), over = 11, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.302810s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.239246s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.0%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.257317s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (103.2%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.346984s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.166562s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.191176s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (106.3%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.215288s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (101.6%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.232503s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.307635s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.187564s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (125.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.192881s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.223830s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.235135s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.303428s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.363797s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.165741s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (94.3%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.190538s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.224577s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.229105s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (109.1%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.304937s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.351855s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.7%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.54641e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 25; 0.189277s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16501(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.052   |  -4.075   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.300907s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 666 feed throughs used by 449 nets
+PHY-1001 : End commit to database; 2.405179s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1163, reserve = 1164, peak = 1163.
+PHY-1001 : End phase 3; 17.246064s wall, 18.734375s user + 0.062500s system = 18.796875s CPU (109.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.052ns STNS -4.075ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.146744s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.5%)
+
+PHY-1022 : len = 2.54641e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.394053s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.1%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.052ns, -4.075ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16501(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.052   |  -4.075   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.356000s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 666 feed throughs used by 449 nets
+PHY-1001 : End commit to database; 2.428968s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1171, reserve = 1172, peak = 1171.
+PHY-1001 : End phase 4; 6.207815s wall, 6.203125s user + 0.000000s system = 6.203125s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.54641e+06
+PHY-1001 : Current memory(MB): used = 1174, reserve = 1175, peak = 1174.
+PHY-1001 : End export database. 0.064696s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.6%)
+
+PHY-1001 : End detail routing;  87.183492s wall, 122.828125s user + 0.593750s system = 123.421875s CPU (141.6%)
+
+RUN-1003 : finish command "route" in  93.245107s wall, 129.953125s user + 0.656250s system = 130.609375s CPU (140.1%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1104 MB, peak memory is 1174 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10252   out of  19600   52.31%
+#reg                     9404   out of  19600   47.98%
+#le                     12293
+  #lut only              2889   out of  12293   23.50%
+  #reg only              2041   out of  12293   16.60%
+  #lut&reg               7363   out of  12293   59.90%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                                                               Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                                                                 1833
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                                                            1379
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                                                           1277
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                                                                 979
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0                                      141
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                                                           71
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                                                            68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                                                                 25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                                                                 4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg3_syn_319_syn_2.f0    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg47_syn_235.f0                                      3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                                                                1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                                                                1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                                                                1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                                                                 1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P88        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12293  |9225    |1027    |9434    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |558    |486     |23      |444     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |101    |86      |4       |89      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |33     |33      |0       |23      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |760    |359     |96      |566     |0       |0       |
+|    u_ADconfig                |AD_config            |188    |124     |25      |144     |0       |0       |
+|    u_gen_sp                  |gen_sp               |262    |158     |71      |112     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |730    |462     |96      |538     |0       |0       |
+|    u_ADconfig                |AD_config            |175    |124     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |256    |170     |71      |114     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2929   |2296    |306     |2109    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |179    |144     |17      |139     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2725   |2144    |289     |1945    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |3       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2317   |1858    |253     |1602    |22      |0       |
+|        channelPart           |channel_part_8478    |140    |136     |3       |130     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |40      |0       |0       |
+|        ram_switch            |ram_switch           |1761   |1383    |197     |1179    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |200    |173     |27      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |17     |14      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|          insert              |insert               |1010   |660     |170     |714     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |551    |550     |0       |350     |0       |0       |
+|        read_ram_i            |read_ram             |325    |269     |44      |220     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |225    |185     |40      |157     |0       |0       |
+|          read_ram_data       |read_ram_data        |98     |82      |4       |61      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |318    |211     |36      |278     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3219   |2433    |349     |2131    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |173    |115     |17      |135     |0       |0       |
+|    u_sort                    |sort_rev             |3013   |2303    |332     |1963    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |5       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1      |0       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2578   |1972    |290     |1606    |22      |1       |
+|        channelPart           |channel_part_8478    |226    |222     |3       |139     |0       |0       |
+|        fifo_adc              |fifo_adc             |61     |52      |9       |40      |0       |1       |
+|        ram_switch            |ram_switch           |1889   |1406    |197     |1178    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |220    |192     |27      |104     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |7       |3       |6       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |16      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|          insert              |insert               |1001   |551     |170     |720     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |668    |663     |0       |354     |0       |0       |
+|        read_ram_i            |read_ram_rev         |363    |259     |81      |211     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |291    |207     |73      |158     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |72     |52      |8       |53      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9949  
+    #2         2       3766  
+    #3         3       1412  
+    #4         4       526   
+    #5        5-10     1204  
+    #6       11-50     603   
+    #7       51-100     22   
+    #8        >500      1    
+  Average     2.91           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.062721s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (172.0%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1105 MB, peak memory is 1174 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73857, tnet num: 17401, tinst num: 6745, tnode num: 96303, tedge num: 123750.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.597940s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.7%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1108 MB, peak memory is 1174 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17401 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.514652s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (100.1%)
+
+RUN-1004 : used memory is 1110 MB, reserved memory is 1114 MB, peak memory is 1174 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6745
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17579, pip num: 179014
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 666
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3232 valid insts, and 492858 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.348737s wall, 70.187500s user + 0.171875s system = 70.359375s CPU (679.9%)
+
+RUN-1004 : used memory is 1275 MB, reserved memory is 1272 MB, peak memory is 1390 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_103129.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_104030.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_104030.log
new file mode 100644
index 0000000..ef39221
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_104030.log
@@ -0,0 +1,1860 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:40:30 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.157666s wall, 2.078125s user + 0.078125s system = 2.156250s CPU (99.9%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2977 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2213 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17672 instances
+RUN-0007 : 7375 luts, 9074 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20250 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13213 nets have 2 pins
+RUN-1001 : 5754 nets have [3 - 5] pins
+RUN-1001 : 868 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 182 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     789     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3508     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     59     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 144
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17670 instances, 7375 luts, 9074 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5895 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84458, tnet num: 20072, tinst num: 17670, tnode num: 114633, tedge num: 135502.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.150929s wall, 1.109375s user + 0.046875s system = 1.156250s CPU (100.5%)
+
+RUN-1004 : used memory is 536 MB, reserved memory is 513 MB, peak memory is 536 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20072 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.931889s wall, 1.843750s user + 0.078125s system = 1.921875s CPU (99.5%)
+
+PHY-3001 : Found 3486 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.15513e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17670.
+PHY-3001 : Level 1 #clusters 2011.
+PHY-3001 : End clustering;  0.129533s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (132.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.26829e+06, overlap = 528.875
+PHY-3002 : Step(2): len = 1.16906e+06, overlap = 527.75
+PHY-3002 : Step(3): len = 808552, overlap = 578.625
+PHY-3002 : Step(4): len = 767603, overlap = 602.844
+PHY-3002 : Step(5): len = 586390, overlap = 734.875
+PHY-3002 : Step(6): len = 527598, overlap = 811.281
+PHY-3002 : Step(7): len = 431933, overlap = 942.844
+PHY-3002 : Step(8): len = 405867, overlap = 977.625
+PHY-3002 : Step(9): len = 356223, overlap = 1057.41
+PHY-3002 : Step(10): len = 334975, overlap = 1065.53
+PHY-3002 : Step(11): len = 303209, overlap = 1113.88
+PHY-3002 : Step(12): len = 284661, overlap = 1179.03
+PHY-3002 : Step(13): len = 257353, overlap = 1215.41
+PHY-3002 : Step(14): len = 233736, overlap = 1255.44
+PHY-3002 : Step(15): len = 208392, overlap = 1305.75
+PHY-3002 : Step(16): len = 189763, overlap = 1347.28
+PHY-3002 : Step(17): len = 173964, overlap = 1376.78
+PHY-3002 : Step(18): len = 162322, overlap = 1398.47
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.25122e-07
+PHY-3002 : Step(19): len = 159574, overlap = 1379.81
+PHY-3002 : Step(20): len = 185475, overlap = 1305.81
+PHY-3002 : Step(21): len = 189986, overlap = 1258.38
+PHY-3002 : Step(22): len = 193990, overlap = 1255.84
+PHY-3002 : Step(23): len = 190844, overlap = 1250.09
+PHY-3002 : Step(24): len = 190277, overlap = 1207.16
+PHY-3002 : Step(25): len = 187347, overlap = 1187.19
+PHY-3002 : Step(26): len = 184568, overlap = 1177.91
+PHY-3002 : Step(27): len = 182065, overlap = 1174.78
+PHY-3002 : Step(28): len = 179368, overlap = 1177.41
+PHY-3002 : Step(29): len = 177034, overlap = 1165.81
+PHY-3002 : Step(30): len = 174270, overlap = 1176.41
+PHY-3002 : Step(31): len = 174394, overlap = 1174.22
+PHY-3002 : Step(32): len = 172466, overlap = 1184.03
+PHY-3002 : Step(33): len = 173780, overlap = 1175.03
+PHY-3002 : Step(34): len = 171951, overlap = 1181.97
+PHY-3002 : Step(35): len = 172395, overlap = 1159.03
+PHY-3002 : Step(36): len = 171241, overlap = 1142.19
+PHY-3002 : Step(37): len = 171290, overlap = 1137.03
+PHY-3002 : Step(38): len = 171246, overlap = 1144
+PHY-3002 : Step(39): len = 171010, overlap = 1130.22
+PHY-3002 : Step(40): len = 169973, overlap = 1124.16
+PHY-3002 : Step(41): len = 170115, overlap = 1115.91
+PHY-3002 : Step(42): len = 167613, overlap = 1141.22
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.65024e-06
+PHY-3002 : Step(43): len = 169439, overlap = 1121.22
+PHY-3002 : Step(44): len = 178863, overlap = 1111.44
+PHY-3002 : Step(45): len = 183543, overlap = 1092.16
+PHY-3002 : Step(46): len = 188099, overlap = 1079.66
+PHY-3002 : Step(47): len = 189736, overlap = 1061.44
+PHY-3002 : Step(48): len = 190803, overlap = 1056.31
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.30049e-06
+PHY-3002 : Step(49): len = 197093, overlap = 1031.94
+PHY-3002 : Step(50): len = 213628, overlap = 999.438
+PHY-3002 : Step(51): len = 222713, overlap = 979.719
+PHY-3002 : Step(52): len = 230959, overlap = 959
+PHY-3002 : Step(53): len = 234799, overlap = 938.688
+PHY-3002 : Step(54): len = 237208, overlap = 933.281
+PHY-3002 : Step(55): len = 237799, overlap = 923.594
+PHY-3002 : Step(56): len = 237721, overlap = 898.906
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.60097e-06
+PHY-3002 : Step(57): len = 249958, overlap = 885.875
+PHY-3002 : Step(58): len = 266639, overlap = 859.375
+PHY-3002 : Step(59): len = 275348, overlap = 742.156
+PHY-3002 : Step(60): len = 282531, overlap = 708.25
+PHY-3002 : Step(61): len = 285461, overlap = 673.75
+PHY-3002 : Step(62): len = 287580, overlap = 633.656
+PHY-3002 : Step(63): len = 286678, overlap = 642.25
+PHY-3002 : Step(64): len = 285955, overlap = 644.5
+PHY-3002 : Step(65): len = 285342, overlap = 646.125
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.32019e-05
+PHY-3002 : Step(66): len = 303088, overlap = 604.406
+PHY-3002 : Step(67): len = 326269, overlap = 520.531
+PHY-3002 : Step(68): len = 332290, overlap = 501.688
+PHY-3002 : Step(69): len = 334891, overlap = 485.312
+PHY-3002 : Step(70): len = 334394, overlap = 481.781
+PHY-3002 : Step(71): len = 332696, overlap = 460.969
+PHY-3002 : Step(72): len = 330481, overlap = 456.969
+PHY-3002 : Step(73): len = 331072, overlap = 460.562
+PHY-3002 : Step(74): len = 333886, overlap = 473.844
+PHY-3002 : Step(75): len = 332911, overlap = 476.156
+PHY-3002 : Step(76): len = 331566, overlap = 467.5
+PHY-3002 : Step(77): len = 330581, overlap = 474.188
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.64039e-05
+PHY-3002 : Step(78): len = 348498, overlap = 443.312
+PHY-3002 : Step(79): len = 361894, overlap = 417.5
+PHY-3002 : Step(80): len = 363688, overlap = 404.438
+PHY-3002 : Step(81): len = 366422, overlap = 385.656
+PHY-3002 : Step(82): len = 368894, overlap = 382.719
+PHY-3002 : Step(83): len = 370469, overlap = 363.125
+PHY-3002 : Step(84): len = 367907, overlap = 347.219
+PHY-3002 : Step(85): len = 368059, overlap = 340.906
+PHY-3002 : Step(86): len = 369043, overlap = 328.125
+PHY-3002 : Step(87): len = 370335, overlap = 318.594
+PHY-3002 : Step(88): len = 368016, overlap = 319.188
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.28078e-05
+PHY-3002 : Step(89): len = 386503, overlap = 288.031
+PHY-3002 : Step(90): len = 401308, overlap = 249.5
+PHY-3002 : Step(91): len = 401830, overlap = 255.094
+PHY-3002 : Step(92): len = 402820, overlap = 248.344
+PHY-3002 : Step(93): len = 406770, overlap = 248.75
+PHY-3002 : Step(94): len = 409884, overlap = 256.25
+PHY-3002 : Step(95): len = 406635, overlap = 257.781
+PHY-3002 : Step(96): len = 408307, overlap = 249.562
+PHY-3002 : Step(97): len = 410855, overlap = 238.188
+PHY-3002 : Step(98): len = 412586, overlap = 241.219
+PHY-3002 : Step(99): len = 409479, overlap = 239.719
+PHY-3002 : Step(100): len = 408805, overlap = 244.906
+PHY-3002 : Step(101): len = 409836, overlap = 239.031
+PHY-3002 : Step(102): len = 410840, overlap = 235.906
+PHY-3002 : Step(103): len = 408556, overlap = 247.812
+PHY-3002 : Step(104): len = 408379, overlap = 254.344
+PHY-3002 : Step(105): len = 409527, overlap = 262.969
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000105322
+PHY-3002 : Step(106): len = 425802, overlap = 238.844
+PHY-3002 : Step(107): len = 440093, overlap = 221.188
+PHY-3002 : Step(108): len = 440222, overlap = 213.156
+PHY-3002 : Step(109): len = 440892, overlap = 211.031
+PHY-3002 : Step(110): len = 442842, overlap = 209.969
+PHY-3002 : Step(111): len = 444653, overlap = 220.469
+PHY-3002 : Step(112): len = 441693, overlap = 220.594
+PHY-3002 : Step(113): len = 444163, overlap = 211.844
+PHY-3002 : Step(114): len = 447800, overlap = 215.25
+PHY-3002 : Step(115): len = 450802, overlap = 213.312
+PHY-3002 : Step(116): len = 448735, overlap = 211.156
+PHY-3002 : Step(117): len = 448726, overlap = 218.25
+PHY-3002 : Step(118): len = 450130, overlap = 217.344
+PHY-3002 : Step(119): len = 450318, overlap = 207.25
+PHY-3002 : Step(120): len = 446620, overlap = 210
+PHY-3002 : Step(121): len = 446861, overlap = 213.125
+PHY-3002 : Step(122): len = 448598, overlap = 214.219
+PHY-3002 : Step(123): len = 449571, overlap = 215.188
+PHY-3002 : Step(124): len = 446862, overlap = 213.875
+PHY-3002 : Step(125): len = 446023, overlap = 213.781
+PHY-3002 : Step(126): len = 446763, overlap = 219.031
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000210644
+PHY-3002 : Step(127): len = 458603, overlap = 221.594
+PHY-3002 : Step(128): len = 466354, overlap = 210.969
+PHY-3002 : Step(129): len = 465716, overlap = 213.562
+PHY-3002 : Step(130): len = 466083, overlap = 208.531
+PHY-3002 : Step(131): len = 468332, overlap = 208.75
+PHY-3002 : Step(132): len = 470029, overlap = 199.125
+PHY-3002 : Step(133): len = 469405, overlap = 200.031
+PHY-3002 : Step(134): len = 470253, overlap = 195.719
+PHY-3002 : Step(135): len = 472866, overlap = 181.719
+PHY-3002 : Step(136): len = 475218, overlap = 174.531
+PHY-3002 : Step(137): len = 474859, overlap = 177.281
+PHY-3002 : Step(138): len = 474820, overlap = 175.594
+PHY-3002 : Step(139): len = 476003, overlap = 168.688
+PHY-3002 : Step(140): len = 477034, overlap = 170.562
+PHY-3002 : Step(141): len = 476126, overlap = 167.344
+PHY-3002 : Step(142): len = 476042, overlap = 173.469
+PHY-3002 : Step(143): len = 477668, overlap = 176.625
+PHY-3002 : Step(144): len = 479096, overlap = 175.188
+PHY-3002 : Step(145): len = 478073, overlap = 171
+PHY-3002 : Step(146): len = 477980, overlap = 168.781
+PHY-3002 : Step(147): len = 478564, overlap = 170.656
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000420963
+PHY-3002 : Step(148): len = 488739, overlap = 168.531
+PHY-3002 : Step(149): len = 496307, overlap = 163.875
+PHY-3002 : Step(150): len = 497340, overlap = 149.188
+PHY-3002 : Step(151): len = 498383, overlap = 147.438
+PHY-3002 : Step(152): len = 501074, overlap = 145.781
+PHY-3002 : Step(153): len = 502251, overlap = 149.031
+PHY-3002 : Step(154): len = 501013, overlap = 145.969
+PHY-3002 : Step(155): len = 501157, overlap = 142.969
+PHY-3002 : Step(156): len = 504965, overlap = 143.688
+PHY-3002 : Step(157): len = 509503, overlap = 135.219
+PHY-3002 : Step(158): len = 507784, overlap = 135.031
+PHY-3002 : Step(159): len = 508049, overlap = 137.156
+PHY-3002 : Step(160): len = 510253, overlap = 131.438
+PHY-3002 : Step(161): len = 511638, overlap = 132.938
+PHY-3002 : Step(162): len = 509940, overlap = 134.594
+PHY-3002 : Step(163): len = 509437, overlap = 135.438
+PHY-3002 : Step(164): len = 510416, overlap = 137.531
+PHY-3002 : Step(165): len = 510453, overlap = 141.125
+PHY-3002 : Step(166): len = 508443, overlap = 140.438
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000769166
+PHY-3002 : Step(167): len = 511765, overlap = 138.562
+PHY-3002 : Step(168): len = 514958, overlap = 136.906
+PHY-3002 : Step(169): len = 515544, overlap = 130.562
+PHY-3002 : Step(170): len = 516318, overlap = 129.656
+PHY-3002 : Step(171): len = 518106, overlap = 131.188
+PHY-3002 : Step(172): len = 518798, overlap = 131.281
+PHY-3002 : Step(173): len = 518330, overlap = 129.062
+PHY-3002 : Step(174): len = 518255, overlap = 129.5
+PHY-3002 : Step(175): len = 519983, overlap = 128.875
+PHY-3002 : Step(176): len = 521888, overlap = 133.281
+PHY-3002 : Step(177): len = 521502, overlap = 129.719
+PHY-3002 : Step(178): len = 521884, overlap = 127.969
+PHY-3002 : Step(179): len = 523860, overlap = 126.875
+PHY-3002 : Step(180): len = 524559, overlap = 126.562
+PHY-3002 : Step(181): len = 523848, overlap = 121.281
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00129721
+PHY-3002 : Step(182): len = 526753, overlap = 121.688
+PHY-3002 : Step(183): len = 530215, overlap = 115.375
+PHY-3002 : Step(184): len = 530297, overlap = 112.406
+PHY-3002 : Step(185): len = 530533, overlap = 113.25
+PHY-3002 : Step(186): len = 531909, overlap = 112.219
+PHY-3002 : Step(187): len = 532756, overlap = 110.062
+PHY-3002 : Step(188): len = 532551, overlap = 110.062
+PHY-3002 : Step(189): len = 532817, overlap = 110.625
+PHY-3002 : Step(190): len = 534312, overlap = 106.125
+PHY-3002 : Step(191): len = 534312, overlap = 106.125
+PHY-3002 : Step(192): len = 534232, overlap = 108.875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016421s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (190.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20250.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 706832, over cnt = 1566(4%), over = 7060, worst = 27
+PHY-1001 : End global iterations;  0.710684s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (129.7%)
+
+PHY-1001 : Congestion index: top1 = 73.60, top5 = 57.56, top10 = 50.15, top15 = 45.27.
+PHY-3001 : End congestion estimation;  0.968581s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (122.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20072 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.853684s wall, 0.812500s user + 0.046875s system = 0.859375s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.62732e-05
+PHY-3002 : Step(193): len = 642302, overlap = 60
+PHY-3002 : Step(194): len = 657384, overlap = 62.3125
+PHY-3002 : Step(195): len = 652090, overlap = 57.7188
+PHY-3002 : Step(196): len = 648224, overlap = 55.8438
+PHY-3002 : Step(197): len = 655323, overlap = 50.3125
+PHY-3002 : Step(198): len = 668723, overlap = 56.25
+PHY-3002 : Step(199): len = 673046, overlap = 57.7812
+PHY-3002 : Step(200): len = 675946, overlap = 60.9688
+PHY-3002 : Step(201): len = 682118, overlap = 65.875
+PHY-3002 : Step(202): len = 686259, overlap = 65.4062
+PHY-3002 : Step(203): len = 691133, overlap = 54.1562
+PHY-3002 : Step(204): len = 697350, overlap = 50.1562
+PHY-3002 : Step(205): len = 702546, overlap = 44.9688
+PHY-3002 : Step(206): len = 706416, overlap = 42.3125
+PHY-3002 : Step(207): len = 711238, overlap = 46.375
+PHY-3002 : Step(208): len = 713112, overlap = 41.5625
+PHY-3002 : Step(209): len = 716325, overlap = 42.4375
+PHY-3002 : Step(210): len = 719380, overlap = 44.7812
+PHY-3002 : Step(211): len = 724453, overlap = 46.1562
+PHY-3002 : Step(212): len = 723644, overlap = 47.4688
+PHY-3002 : Step(213): len = 723807, overlap = 55.3438
+PHY-3002 : Step(214): len = 722384, overlap = 61.2188
+PHY-3002 : Step(215): len = 720548, overlap = 62.4062
+PHY-3002 : Step(216): len = 720580, overlap = 62.5938
+PHY-3002 : Step(217): len = 717558, overlap = 61.5625
+PHY-3002 : Step(218): len = 715264, overlap = 65.6562
+PHY-3002 : Step(219): len = 714214, overlap = 66.9688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000172546
+PHY-3002 : Step(220): len = 715182, overlap = 63.7812
+PHY-3002 : Step(221): len = 718603, overlap = 60.0625
+PHY-3002 : Step(222): len = 722581, overlap = 56.6875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000324889
+PHY-3002 : Step(223): len = 727318, overlap = 54.625
+PHY-3002 : Step(224): len = 742397, overlap = 51.1562
+PHY-3002 : Step(225): len = 758062, overlap = 49.875
+PHY-3002 : Step(226): len = 757107, overlap = 50.6875
+PHY-3002 : Step(227): len = 755300, overlap = 49.3125
+PHY-3002 : Step(228): len = 754771, overlap = 52.5625
+PHY-3002 : Step(229): len = 754727, overlap = 53.9062
+PHY-3002 : Step(230): len = 756496, overlap = 53.5
+PHY-3002 : Step(231): len = 756346, overlap = 52.8438
+PHY-3002 : Step(232): len = 757778, overlap = 51.1562
+PHY-3002 : Step(233): len = 760587, overlap = 48.875
+PHY-3002 : Step(234): len = 759771, overlap = 49.125
+PHY-3002 : Step(235): len = 757690, overlap = 47.0312
+PHY-3002 : Step(236): len = 757041, overlap = 41.4375
+PHY-3002 : Step(237): len = 755942, overlap = 38.4688
+PHY-3002 : Step(238): len = 755706, overlap = 32.75
+PHY-3002 : Step(239): len = 754283, overlap = 33.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000633533
+PHY-3002 : Step(240): len = 757833, overlap = 30.1875
+PHY-3002 : Step(241): len = 766072, overlap = 35.9688
+PHY-3002 : Step(242): len = 773178, overlap = 39.4375
+PHY-3002 : Step(243): len = 772507, overlap = 33.3125
+PHY-3002 : Step(244): len = 769012, overlap = 36.2188
+PHY-3002 : Step(245): len = 768040, overlap = 40.9062
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 23/20250.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 843816, over cnt = 2668(7%), over = 14142, worst = 57
+PHY-1001 : End global iterations;  1.356499s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (138.2%)
+
+PHY-1001 : Congestion index: top1 = 115.26, top5 = 80.81, top10 = 67.93, top15 = 60.77.
+PHY-3001 : End congestion estimation;  1.641088s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (131.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20072 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.879922s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.58323e-05
+PHY-3002 : Step(246): len = 768162, overlap = 251.062
+PHY-3002 : Step(247): len = 773776, overlap = 202.688
+PHY-3002 : Step(248): len = 762860, overlap = 183.562
+PHY-3002 : Step(249): len = 759006, overlap = 167.781
+PHY-3002 : Step(250): len = 754708, overlap = 153.625
+PHY-3002 : Step(251): len = 750863, overlap = 145.188
+PHY-3002 : Step(252): len = 747482, overlap = 134.875
+PHY-3002 : Step(253): len = 743444, overlap = 138.75
+PHY-3002 : Step(254): len = 740342, overlap = 135.531
+PHY-3002 : Step(255): len = 735751, overlap = 132.969
+PHY-3002 : Step(256): len = 732771, overlap = 137.031
+PHY-3002 : Step(257): len = 728412, overlap = 135.344
+PHY-3002 : Step(258): len = 725071, overlap = 132.062
+PHY-3002 : Step(259): len = 721139, overlap = 133.219
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000191665
+PHY-3002 : Step(260): len = 724554, overlap = 123.531
+PHY-3002 : Step(261): len = 726065, overlap = 122.688
+PHY-3002 : Step(262): len = 727655, overlap = 116.75
+PHY-3002 : Step(263): len = 729120, overlap = 113.531
+PHY-3002 : Step(264): len = 729916, overlap = 110.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000383329
+PHY-3002 : Step(265): len = 732249, overlap = 106.312
+PHY-3002 : Step(266): len = 737431, overlap = 98.3125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000643604
+PHY-3002 : Step(267): len = 740267, overlap = 91
+PHY-3002 : Step(268): len = 753584, overlap = 84.9375
+PHY-3002 : Step(269): len = 760796, overlap = 83.7812
+PHY-3002 : Step(270): len = 759483, overlap = 82.75
+PHY-3002 : Step(271): len = 758469, overlap = 80.25
+PHY-3002 : Step(272): len = 757338, overlap = 78.2812
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84458, tnet num: 20072, tinst num: 17670, tnode num: 114633, tedge num: 135502.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.451828s wall, 1.390625s user + 0.062500s system = 1.453125s CPU (100.1%)
+
+RUN-1004 : used memory is 580 MB, reserved memory is 562 MB, peak memory is 715 MB
+OPT-1001 : Total overflow 402.41 peak overflow 4.31
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 710/20250.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 852792, over cnt = 3167(8%), over = 12068, worst = 34
+PHY-1001 : End global iterations;  1.315746s wall, 1.859375s user + 0.046875s system = 1.906250s CPU (144.9%)
+
+PHY-1001 : Congestion index: top1 = 80.75, top5 = 65.42, top10 = 57.37, top15 = 52.71.
+PHY-1001 : End incremental global routing;  1.644345s wall, 2.203125s user + 0.046875s system = 2.250000s CPU (136.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20072 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.905597s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.1%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17534 has valid locations, 332 needs to be replaced
+PHY-3001 : design contains 17951 instances, 7484 luts, 9246 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6020 pins
+PHY-3001 : Found 3518 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 781039
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16724/20531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 870672, over cnt = 3193(9%), over = 12136, worst = 34
+PHY-1001 : End global iterations;  0.238305s wall, 0.343750s user + 0.031250s system = 0.375000s CPU (157.4%)
+
+PHY-1001 : Congestion index: top1 = 81.06, top5 = 65.65, top10 = 57.56, top15 = 53.00.
+PHY-3001 : End congestion estimation;  0.485142s wall, 0.578125s user + 0.031250s system = 0.609375s CPU (125.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85600, tnet num: 20353, tinst num: 17951, tnode num: 116325, tedge num: 137224.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.444251s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (100.6%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 613 MB, peak memory is 720 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.761911s wall, 2.671875s user + 0.093750s system = 2.765625s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(273): len = 779870, overlap = 0
+PHY-3002 : Step(274): len = 779360, overlap = 0
+PHY-3002 : Step(275): len = 779184, overlap = 0.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16829/20531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 867320, over cnt = 3202(9%), over = 12203, worst = 34
+PHY-1001 : End global iterations;  0.199838s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (125.1%)
+
+PHY-1001 : Congestion index: top1 = 81.23, top5 = 65.79, top10 = 57.80, top15 = 53.22.
+PHY-3001 : End congestion estimation;  0.451100s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (107.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.928747s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (100.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000466327
+PHY-3002 : Step(276): len = 779022, overlap = 80.625
+PHY-3002 : Step(277): len = 779005, overlap = 80.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000932655
+PHY-3002 : Step(278): len = 779520, overlap = 81.0938
+PHY-3002 : Step(279): len = 780181, overlap = 81.2188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00178717
+PHY-3002 : Step(280): len = 780644, overlap = 80.75
+PHY-3002 : Step(281): len = 781417, overlap = 80.8438
+PHY-3001 : Final: Len = 781417, Over = 80.8438
+PHY-3001 : End incremental placement;  5.334476s wall, 5.546875s user + 0.281250s system = 5.828125s CPU (109.3%)
+
+OPT-1001 : Total overflow 409.59 peak overflow 4.31
+OPT-1001 : End high-fanout net optimization;  8.421445s wall, 9.171875s user + 0.343750s system = 9.515625s CPU (113.0%)
+
+OPT-1001 : Current memory(MB): used = 723, reserve = 711, peak = 740.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16752/20531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872872, over cnt = 3175(9%), over = 11217, worst = 34
+PHY-1002 : len = 925960, over cnt = 2296(6%), over = 5955, worst = 24
+PHY-1002 : len = 971080, over cnt = 954(2%), over = 2196, worst = 17
+PHY-1002 : len = 987760, over cnt = 415(1%), over = 804, worst = 12
+PHY-1002 : len = 1.00329e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.023061s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (129.8%)
+
+PHY-1001 : Congestion index: top1 = 64.18, top5 = 56.07, top10 = 51.81, top15 = 49.12.
+OPT-1001 : End congestion update;  2.282738s wall, 2.890625s user + 0.015625s system = 2.906250s CPU (127.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.798183s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 60 cells processed and 7650 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 9 cells processed and 584 slack improved
+OPT-1001 : End global optimization;  3.122000s wall, 3.718750s user + 0.015625s system = 3.734375s CPU (119.6%)
+
+OPT-1001 : Current memory(MB): used = 703, reserve = 696, peak = 740.
+OPT-1001 : End physical optimization;  13.498560s wall, 14.875000s user + 0.421875s system = 15.296875s CPU (113.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7484 LUT to BLE ...
+SYN-4008 : Packed 7484 LUT and 3131 SEQ to BLE.
+SYN-4003 : Packing 6115 remaining SEQ's ...
+SYN-4005 : Packed 3850 SEQ with LUT/SLICE
+SYN-4006 : 791 single LUT's are left
+SYN-4006 : 2265 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9749/13496 primitive instances ...
+PHY-3001 : End packing;  1.586715s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6774 instances
+RUN-1001 : 3313 mslices, 3313 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17506 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9797 nets have 2 pins
+RUN-1001 : 6037 nets have [3 - 5] pins
+RUN-1001 : 978 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6772 instances, 6626 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3507 pins
+PHY-3001 : Found 1570 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : After packing: Len = 786677, Over = 261.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7696/17506.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 949528, over cnt = 2005(5%), over = 3304, worst = 9
+PHY-1002 : len = 956360, over cnt = 1342(3%), over = 1992, worst = 7
+PHY-1002 : len = 968400, over cnt = 721(2%), over = 1033, worst = 6
+PHY-1002 : len = 979088, over cnt = 168(0%), over = 240, worst = 5
+PHY-1002 : len = 982648, over cnt = 4(0%), over = 4, worst = 1
+PHY-1001 : End global iterations;  1.556610s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (143.5%)
+
+PHY-1001 : Congestion index: top1 = 62.48, top5 = 54.20, top10 = 49.97, top15 = 47.31.
+PHY-3001 : End congestion estimation;  1.940647s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (135.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73347, tnet num: 17328, tinst num: 6772, tnode num: 95627, tedge num: 123038.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.617124s wall, 1.593750s user + 0.015625s system = 1.609375s CPU (99.5%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 605 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17328 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.482024s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.6596e-05
+PHY-3002 : Step(282): len = 774969, overlap = 258.25
+PHY-3002 : Step(283): len = 768175, overlap = 255
+PHY-3002 : Step(284): len = 762245, overlap = 258.25
+PHY-3002 : Step(285): len = 756784, overlap = 267.75
+PHY-3002 : Step(286): len = 752518, overlap = 275.25
+PHY-3002 : Step(287): len = 748100, overlap = 274.5
+PHY-3002 : Step(288): len = 743020, overlap = 271.75
+PHY-3002 : Step(289): len = 739230, overlap = 268.75
+PHY-3002 : Step(290): len = 735509, overlap = 262.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.3192e-05
+PHY-3002 : Step(291): len = 739642, overlap = 254.25
+PHY-3002 : Step(292): len = 743956, overlap = 246.75
+PHY-3002 : Step(293): len = 743739, overlap = 248
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000186384
+PHY-3002 : Step(294): len = 751020, overlap = 231
+PHY-3002 : Step(295): len = 761937, overlap = 218.75
+PHY-3002 : Step(296): len = 761000, overlap = 214.5
+PHY-3002 : Step(297): len = 758617, overlap = 218
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.360260s wall, 0.328125s user + 0.562500s system = 0.890625s CPU (247.2%)
+
+PHY-3001 : Trial Legalized: Len = 940972
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 72%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 652/17506.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.06214e+06, over cnt = 2787(7%), over = 4790, worst = 9
+PHY-1002 : len = 1.08258e+06, over cnt = 1664(4%), over = 2410, worst = 6
+PHY-1002 : len = 1.1065e+06, over cnt = 476(1%), over = 601, worst = 5
+PHY-1002 : len = 1.11478e+06, over cnt = 68(0%), over = 80, worst = 3
+PHY-1002 : len = 1.11659e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.513988s wall, 3.687500s user + 0.078125s system = 3.765625s CPU (149.8%)
+
+PHY-1001 : Congestion index: top1 = 65.97, top5 = 58.52, top10 = 54.72, top15 = 52.11.
+PHY-3001 : End congestion estimation;  2.950631s wall, 4.125000s user + 0.078125s system = 4.203125s CPU (142.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17328 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.852022s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000151931
+PHY-3002 : Step(298): len = 903707, overlap = 61.25
+PHY-3002 : Step(299): len = 883995, overlap = 88.75
+PHY-3002 : Step(300): len = 868616, overlap = 116.25
+PHY-3002 : Step(301): len = 855293, overlap = 148.75
+PHY-3002 : Step(302): len = 845304, overlap = 164.75
+PHY-3002 : Step(303): len = 836242, overlap = 179
+PHY-3002 : Step(304): len = 828699, overlap = 192
+PHY-3002 : Step(305): len = 823256, overlap = 191
+PHY-3002 : Step(306): len = 818965, overlap = 194.75
+PHY-3002 : Step(307): len = 815518, overlap = 192.75
+PHY-3002 : Step(308): len = 810867, overlap = 191.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000303861
+PHY-3002 : Step(309): len = 815246, overlap = 185.75
+PHY-3002 : Step(310): len = 818322, overlap = 182.25
+PHY-3002 : Step(311): len = 818666, overlap = 183
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000515697
+PHY-3002 : Step(312): len = 823534, overlap = 177.75
+PHY-3002 : Step(313): len = 828467, overlap = 174.5
+PHY-3002 : Step(314): len = 830102, overlap = 175.75
+PHY-3002 : Step(315): len = 831480, overlap = 173.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.088223s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (106.3%)
+
+PHY-3001 : Legalized: Len = 900369, Over = 0
+PHY-3001 : Spreading special nets. 460 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.114454s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (109.2%)
+
+PHY-3001 : 696 instances has been re-located, deltaX = 277, deltaY = 429, maxDist = 9.
+PHY-3001 : Final: Len = 912431, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73347, tnet num: 17328, tinst num: 6775, tnode num: 95627, tedge num: 123038.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.873025s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.1%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 651 MB, peak memory is 740 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 2618/17506.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04149e+06, over cnt = 2653(7%), over = 4348, worst = 8
+PHY-1002 : len = 1.05639e+06, over cnt = 1663(4%), over = 2439, worst = 8
+PHY-1002 : len = 1.08023e+06, over cnt = 425(1%), over = 589, worst = 6
+PHY-1002 : len = 1.08564e+06, over cnt = 188(0%), over = 265, worst = 5
+PHY-1002 : len = 1.08962e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations;  2.245473s wall, 3.375000s user + 0.015625s system = 3.390625s CPU (151.0%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 57.86, top10 = 53.43, top15 = 50.65.
+PHY-1001 : End incremental global routing;  2.606946s wall, 3.734375s user + 0.015625s system = 3.750000s CPU (143.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17328 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.160128s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (99.7%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6682 has valid locations, 29 needs to be replaced
+PHY-3001 : design contains 6799 instances, 6650 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3591 pins
+PHY-3001 : Found 1573 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 915819
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16040/17542.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09391e+06, over cnt = 83(0%), over = 99, worst = 4
+PHY-1002 : len = 1.09421e+06, over cnt = 41(0%), over = 47, worst = 4
+PHY-1002 : len = 1.09445e+06, over cnt = 7(0%), over = 8, worst = 2
+PHY-1002 : len = 1.09458e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.613849s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (112.0%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 57.86, top10 = 53.44, top15 = 50.69.
+PHY-3001 : End congestion estimation;  0.923963s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (108.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73611, tnet num: 17364, tinst num: 6799, tnode num: 95952, tedge num: 123415.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.839517s wall, 1.796875s user + 0.031250s system = 1.828125s CPU (99.4%)
+
+RUN-1004 : used memory is 668 MB, reserved memory is 668 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17364 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.725603s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(316): len = 915125, overlap = 0
+PHY-3002 : Step(317): len = 914723, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16030/17542.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09282e+06, over cnt = 62(0%), over = 85, worst = 6
+PHY-1002 : len = 1.09309e+06, over cnt = 31(0%), over = 34, worst = 3
+PHY-1002 : len = 1.0933e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.09338e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.588686s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (106.2%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 57.87, top10 = 53.49, top15 = 50.71.
+PHY-3001 : End congestion estimation;  0.897320s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (104.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17364 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.154294s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000479077
+PHY-3002 : Step(318): len = 914598, overlap = 1
+PHY-3002 : Step(319): len = 914598, overlap = 1
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005773s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 914670, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060486s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.5%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 3, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 914740, Over = 0
+PHY-3001 : End incremental placement;  6.222772s wall, 6.437500s user + 0.109375s system = 6.546875s CPU (105.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.514060s wall, 11.968750s user + 0.125000s system = 12.093750s CPU (115.0%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 745, peak = 751.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16008/17542.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0931e+06, over cnt = 64(0%), over = 82, worst = 4
+PHY-1002 : len = 1.09317e+06, over cnt = 32(0%), over = 36, worst = 3
+PHY-1002 : len = 1.09334e+06, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 1.09343e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.587024s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (109.1%)
+
+PHY-1001 : Congestion index: top1 = 65.41, top5 = 57.86, top10 = 53.47, top15 = 50.69.
+OPT-1001 : End congestion update;  0.896675s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (106.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17364 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.718846s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.0%)
+
+OPT-0007 : Start: WNS -1133 TNS -1947 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6711 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6799 instances, 6650 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3591 pins
+PHY-3001 : Found 1573 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Initial: Len = 918548, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059783s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.5%)
+
+PHY-3001 : 22 instances has been re-located, deltaX = 18, deltaY = 12, maxDist = 2.
+PHY-3001 : Final: Len = 919160, Over = 0
+PHY-3001 : End incremental legalization;  0.374911s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (100.0%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1518 NUM_FEPS 2 with 29 cells processed and 7950 slack improved
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.128634s wall, 2.171875s user + 0.015625s system = 2.187500s CPU (102.8%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 745, peak = 752.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17364 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.719173s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15886/17542.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09782e+06, over cnt = 104(0%), over = 129, worst = 4
+PHY-1002 : len = 1.09795e+06, over cnt = 50(0%), over = 53, worst = 2
+PHY-1002 : len = 1.09833e+06, over cnt = 21(0%), over = 21, worst = 1
+PHY-1002 : len = 1.09857e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.09866e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.849134s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 65.32, top5 = 57.80, top10 = 53.42, top15 = 50.73.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17364 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.714704s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.6%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1133 TNS -1718 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 64.862069
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1133ps with logic level 2 
+RUN-1001 :       #2 path slack -1047ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17542 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17542 nets
+OPT-1001 : End physical optimization;  17.476062s wall, 19.000000s user + 0.187500s system = 19.187500s CPU (109.8%)
+
+RUN-1003 : finish command "place" in  60.269814s wall, 92.671875s user + 6.250000s system = 98.921875s CPU (164.1%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 658 MB, peak memory is 752 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.671549s wall, 2.906250s user + 0.015625s system = 2.921875s CPU (174.8%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 659 MB, peak memory is 752 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6801 instances
+RUN-1001 : 3321 mslices, 3329 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17542 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9807 nets have 2 pins
+RUN-1001 : 6035 nets have [3 - 5] pins
+RUN-1001 : 991 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 351 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73611, tnet num: 17364, tinst num: 6799, tnode num: 95952, tedge num: 123415.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.593564s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (100.0%)
+
+RUN-1004 : used memory is 635 MB, reserved memory is 626 MB, peak memory is 752 MB
+PHY-1001 : 3321 mslices, 3329 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17364 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.03215e+06, over cnt = 2799(7%), over = 4659, worst = 9
+PHY-1002 : len = 1.0499e+06, over cnt = 1762(5%), over = 2572, worst = 9
+PHY-1002 : len = 1.0715e+06, over cnt = 561(1%), over = 835, worst = 9
+PHY-1002 : len = 1.08458e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.08474e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.928030s wall, 4.000000s user + 0.031250s system = 4.031250s CPU (137.7%)
+
+PHY-1001 : Congestion index: top1 = 63.58, top5 = 56.95, top10 = 52.87, top15 = 50.16.
+PHY-1001 : End global routing;  3.252236s wall, 4.328125s user + 0.031250s system = 4.359375s CPU (134.0%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 716, reserve = 715, peak = 752.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 990, reserve = 987, peak = 990.
+PHY-1001 : End build detailed router design. 3.985918s wall, 3.968750s user + 0.015625s system = 3.984375s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 268192, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.377824s wall, 5.359375s user + 0.015625s system = 5.375000s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 268248, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.424967s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1025, reserve = 1023, peak = 1025.
+PHY-1001 : End phase 1; 5.816024s wall, 5.796875s user + 0.015625s system = 5.812500s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.59654e+06, over cnt = 1742(0%), over = 1746, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1043, reserve = 1038, peak = 1043.
+PHY-1001 : End initial routed; 54.671777s wall, 84.000000s user + 0.390625s system = 84.390625s CPU (154.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16464(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.166   |  -4.352   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.270208s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1053, reserve = 1049, peak = 1053.
+PHY-1001 : End phase 2; 57.942049s wall, 87.265625s user + 0.390625s system = 87.656250s CPU (151.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.047ns STNS -4.094ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.140743s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%)
+
+PHY-1022 : len = 2.59656e+06, over cnt = 1746(0%), over = 1750, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.412057s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.56055e+06, over cnt = 575(0%), over = 575, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.454529s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (205.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.55927e+06, over cnt = 138(0%), over = 138, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.660115s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (139.7%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.56042e+06, over cnt = 11(0%), over = 11, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.634093s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (110.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.5605e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.252913s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.56052e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.190959s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16464(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.047   |  -4.094   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.302240s wall, 3.281250s user + 0.015625s system = 3.296875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 560 feed throughs used by 427 nets
+PHY-1001 : End commit to database; 2.326425s wall, 2.296875s user + 0.031250s system = 2.328125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1159, reserve = 1159, peak = 1159.
+PHY-1001 : End phase 3; 9.609300s wall, 11.406250s user + 0.046875s system = 11.453125s CPU (119.2%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.047ns STNS -4.094ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.220988s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.0%)
+
+PHY-1022 : len = 2.56052e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.459886s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.047ns, -4.094ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16464(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.047   |  -4.094   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.302803s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 560 feed throughs used by 427 nets
+PHY-1001 : End commit to database; 2.430764s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (99.0%)
+
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1167, peak = 1168.
+PHY-1001 : End phase 4; 6.219551s wall, 6.187500s user + 0.015625s system = 6.203125s CPU (99.7%)
+
+PHY-1003 : Routed, final wirelength = 2.56052e+06
+PHY-1001 : Current memory(MB): used = 1171, reserve = 1170, peak = 1171.
+PHY-1001 : End export database. 0.153039s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.1%)
+
+PHY-1001 : End detail routing;  84.122693s wall, 115.171875s user + 0.484375s system = 115.656250s CPU (137.5%)
+
+RUN-1003 : finish command "route" in  90.024936s wall, 122.109375s user + 0.546875s system = 122.656250s CPU (136.2%)
+
+RUN-1004 : used memory is 1097 MB, reserved memory is 1098 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10269   out of  19600   52.39%
+#reg                     9399   out of  19600   47.95%
+#le                     12458
+  #lut only              3059   out of  12458   24.55%
+  #reg only              2189   out of  12458   17.57%
+  #lut&reg               7210   out of  12458   57.87%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                               Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                                 1806
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                            1380
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                           1279
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                                 961
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0      148
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                            70
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                           69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                                 24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                                 4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_469.f1    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/reg0_syn_150.f1                          2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                                1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                                1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                                1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                                 1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P141       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P17        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P118       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P106       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12458  |9242    |1027    |9429    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |558    |465     |23      |442     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |84      |4       |88      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |33     |33      |0       |21      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |6      |6       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |767    |364     |96      |565     |0       |0       |
+|    u_ADconfig                |AD_config            |190    |129     |25      |137     |0       |0       |
+|    u_gen_sp                  |gen_sp               |269    |168     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |761    |434     |96      |562     |0       |0       |
+|    u_ADconfig                |AD_config            |181    |143     |25      |129     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |156     |71      |114     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2971   |2347    |306     |2105    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |178    |137     |17      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_sort                    |sort                 |2762   |2187    |289     |1940    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1      |1       |0       |1       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2366   |1908    |253     |1602    |22      |0       |
+|        channelPart           |channel_part_8478    |145    |139     |3       |130     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |42      |0       |0       |
+|        ram_switch            |ram_switch           |1781   |1408    |197     |1174    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |229    |202     |27      |120     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |10     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |15      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|          insert              |insert               |1006   |660     |170     |716     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |546    |546     |0       |338     |0       |0       |
+|        read_ram_i            |read_ram             |353    |290     |44      |228     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |212    |172     |40      |148     |0       |0       |
+|          read_ram_data       |read_ram_data        |138    |117     |4       |77      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |324    |217     |36      |277     |3       |0       |
+|        u0_soft_n             |cdc_sync             |7      |4       |0       |7       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3347   |2546    |349     |2127    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |0       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |182    |124     |17      |145     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |0       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |3131   |2407    |332     |1948    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |2       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2703   |2070    |290     |1601    |22      |1       |
+|        channelPart           |channel_part_8478    |227    |216     |3       |140     |0       |0       |
+|        fifo_adc              |fifo_adc             |61     |52      |9       |42      |0       |1       |
+|        ram_switch            |ram_switch           |2003   |1487    |197     |1169    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |225    |198     |27      |106     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |8       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |16      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|          insert              |insert               |1007   |519     |170     |719     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |771    |770     |0       |344     |0       |0       |
+|        read_ram_i            |read_ram_rev         |369    |278     |81      |207     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |304    |229     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |49      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9745  
+    #2         2       3927  
+    #3         3       1484  
+    #4         4       621   
+    #5        5-10     1048  
+    #6       11-50     596   
+    #7       51-100     24   
+    #8        >500      1    
+  Average     2.90           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.075994s wall, 3.562500s user + 0.015625s system = 3.578125s CPU (172.4%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1101 MB, peak memory is 1171 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73611, tnet num: 17364, tinst num: 6799, tnode num: 95952, tedge num: 123415.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.598567s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.7%)
+
+RUN-1004 : used memory is 1101 MB, reserved memory is 1104 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17364 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.484777s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.0%)
+
+RUN-1004 : used memory is 1107 MB, reserved memory is 1109 MB, peak memory is 1171 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6799
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17542, pip num: 178474
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 560
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3224 valid insts, and 491602 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.306201s wall, 69.296875s user + 0.187500s system = 69.484375s CPU (674.2%)
+
+RUN-1004 : used memory is 1269 MB, reserved memory is 1265 MB, peak memory is 1384 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_104030.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_105057.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_105057.log
new file mode 100644
index 0000000..71b0df1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_105057.log
@@ -0,0 +1,2036 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:50:57 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.146710s wall, 2.109375s user + 0.031250s system = 2.140625s CPU (99.7%)
+
+RUN-1004 : used memory is 348 MB, reserved memory is 318 MB, peak memory is 352 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2977 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2423 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2262 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18058 instances
+RUN-0007 : 7341 luts, 9494 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20636 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13592 nets have 2 pins
+RUN-1001 : 5760 nets have [3 - 5] pins
+RUN-1001 : 865 nets have [6 - 10] pins
+RUN-1001 : 160 nets have [11 - 20] pins
+RUN-1001 : 182 nets have [21 - 99] pins
+RUN-1001 : 56 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     789     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3928     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  78   |     59     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 144
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18056 instances, 7341 luts, 9494 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2003 with 6315 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86072, tnet num: 20458, tinst num: 18056, tnode num: 117507, tedge num: 137958.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.172616s wall, 1.125000s user + 0.046875s system = 1.171875s CPU (99.9%)
+
+RUN-1004 : used memory is 544 MB, reserved memory is 521 MB, peak memory is 544 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20458 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.996503s wall, 1.921875s user + 0.078125s system = 2.000000s CPU (100.2%)
+
+PHY-3001 : Found 3480 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.00869e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18056.
+PHY-3001 : Level 1 #clusters 2136.
+PHY-3001 : End clustering;  0.134420s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (139.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.27148e+06, overlap = 546.906
+PHY-3002 : Step(2): len = 1.21124e+06, overlap = 501.156
+PHY-3002 : Step(3): len = 802300, overlap = 613.875
+PHY-3002 : Step(4): len = 754095, overlap = 659.781
+PHY-3002 : Step(5): len = 593714, overlap = 800.156
+PHY-3002 : Step(6): len = 548585, overlap = 849.719
+PHY-3002 : Step(7): len = 438076, overlap = 930.281
+PHY-3002 : Step(8): len = 406687, overlap = 969.656
+PHY-3002 : Step(9): len = 362280, overlap = 1025.28
+PHY-3002 : Step(10): len = 340654, overlap = 1088.75
+PHY-3002 : Step(11): len = 311219, overlap = 1127.16
+PHY-3002 : Step(12): len = 288348, overlap = 1184.25
+PHY-3002 : Step(13): len = 261694, overlap = 1237.97
+PHY-3002 : Step(14): len = 235719, overlap = 1281.59
+PHY-3002 : Step(15): len = 213439, overlap = 1310.81
+PHY-3002 : Step(16): len = 194025, overlap = 1349.94
+PHY-3002 : Step(17): len = 179658, overlap = 1355.59
+PHY-3002 : Step(18): len = 169207, overlap = 1399.72
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 7.6883e-07
+PHY-3002 : Step(19): len = 166656, overlap = 1385.72
+PHY-3002 : Step(20): len = 188479, overlap = 1312.72
+PHY-3002 : Step(21): len = 188054, overlap = 1264.53
+PHY-3002 : Step(22): len = 189349, overlap = 1296.16
+PHY-3002 : Step(23): len = 187962, overlap = 1285.12
+PHY-3002 : Step(24): len = 187628, overlap = 1267.91
+PHY-3002 : Step(25): len = 185960, overlap = 1267.75
+PHY-3002 : Step(26): len = 184575, overlap = 1225.25
+PHY-3002 : Step(27): len = 183458, overlap = 1235.75
+PHY-3002 : Step(28): len = 181780, overlap = 1259.72
+PHY-3002 : Step(29): len = 181291, overlap = 1265.31
+PHY-3002 : Step(30): len = 179756, overlap = 1282.59
+PHY-3002 : Step(31): len = 178845, overlap = 1307.34
+PHY-3002 : Step(32): len = 177636, overlap = 1296.41
+PHY-3002 : Step(33): len = 177744, overlap = 1306.19
+PHY-3002 : Step(34): len = 177056, overlap = 1275.81
+PHY-3002 : Step(35): len = 174871, overlap = 1267.78
+PHY-3002 : Step(36): len = 173828, overlap = 1262.53
+PHY-3002 : Step(37): len = 172758, overlap = 1264.72
+PHY-3002 : Step(38): len = 173164, overlap = 1234.31
+PHY-3002 : Step(39): len = 173001, overlap = 1204.28
+PHY-3002 : Step(40): len = 171934, overlap = 1155.72
+PHY-3002 : Step(41): len = 170682, overlap = 1165.06
+PHY-3002 : Step(42): len = 170052, overlap = 1184.38
+PHY-3002 : Step(43): len = 168982, overlap = 1215.34
+PHY-3002 : Step(44): len = 167350, overlap = 1210.84
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.53766e-06
+PHY-3002 : Step(45): len = 171102, overlap = 1200.88
+PHY-3002 : Step(46): len = 182545, overlap = 1171.59
+PHY-3002 : Step(47): len = 187274, overlap = 1134.84
+PHY-3002 : Step(48): len = 189629, overlap = 1105.44
+PHY-3002 : Step(49): len = 189394, overlap = 1095.47
+PHY-3002 : Step(50): len = 189473, overlap = 1109.78
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.07532e-06
+PHY-3002 : Step(51): len = 197113, overlap = 1113.41
+PHY-3002 : Step(52): len = 214368, overlap = 1040.75
+PHY-3002 : Step(53): len = 222346, overlap = 1010.97
+PHY-3002 : Step(54): len = 225078, overlap = 976.688
+PHY-3002 : Step(55): len = 226948, overlap = 961.5
+PHY-3002 : Step(56): len = 227980, overlap = 957.781
+PHY-3002 : Step(57): len = 226715, overlap = 949.469
+PHY-3002 : Step(58): len = 225287, overlap = 950.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.15064e-06
+PHY-3002 : Step(59): len = 236825, overlap = 922.906
+PHY-3002 : Step(60): len = 255315, overlap = 843.75
+PHY-3002 : Step(61): len = 264908, overlap = 789.531
+PHY-3002 : Step(62): len = 272479, overlap = 735.656
+PHY-3002 : Step(63): len = 275223, overlap = 711.156
+PHY-3002 : Step(64): len = 278002, overlap = 694.438
+PHY-3002 : Step(65): len = 279209, overlap = 675.25
+PHY-3002 : Step(66): len = 279437, overlap = 682.344
+PHY-3002 : Step(67): len = 278123, overlap = 681.188
+PHY-3002 : Step(68): len = 277200, overlap = 681.938
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.23013e-05
+PHY-3002 : Step(69): len = 295885, overlap = 635.656
+PHY-3002 : Step(70): len = 314831, overlap = 567.469
+PHY-3002 : Step(71): len = 320627, overlap = 529.031
+PHY-3002 : Step(72): len = 323204, overlap = 515.938
+PHY-3002 : Step(73): len = 323615, overlap = 507.781
+PHY-3002 : Step(74): len = 326079, overlap = 504.094
+PHY-3002 : Step(75): len = 325462, overlap = 490.688
+PHY-3002 : Step(76): len = 325021, overlap = 495.969
+PHY-3002 : Step(77): len = 323591, overlap = 507.156
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.46026e-05
+PHY-3002 : Step(78): len = 341256, overlap = 445.031
+PHY-3002 : Step(79): len = 357797, overlap = 407.469
+PHY-3002 : Step(80): len = 361414, overlap = 395.531
+PHY-3002 : Step(81): len = 363997, overlap = 388
+PHY-3002 : Step(82): len = 365454, overlap = 381.219
+PHY-3002 : Step(83): len = 367759, overlap = 389.406
+PHY-3002 : Step(84): len = 366722, overlap = 387.562
+PHY-3002 : Step(85): len = 366444, overlap = 367.5
+PHY-3002 : Step(86): len = 367955, overlap = 361.781
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 4.92051e-05
+PHY-3002 : Step(87): len = 385664, overlap = 318.625
+PHY-3002 : Step(88): len = 398332, overlap = 293.625
+PHY-3002 : Step(89): len = 395331, overlap = 293.844
+PHY-3002 : Step(90): len = 395833, overlap = 285.156
+PHY-3002 : Step(91): len = 400326, overlap = 270.844
+PHY-3002 : Step(92): len = 404131, overlap = 271.031
+PHY-3002 : Step(93): len = 400501, overlap = 264.531
+PHY-3002 : Step(94): len = 400340, overlap = 267.781
+PHY-3002 : Step(95): len = 402029, overlap = 283.969
+PHY-3002 : Step(96): len = 403667, overlap = 286.906
+PHY-3002 : Step(97): len = 399886, overlap = 291.656
+PHY-3002 : Step(98): len = 399694, overlap = 291.656
+PHY-3002 : Step(99): len = 400584, overlap = 291.469
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 9.84102e-05
+PHY-3002 : Step(100): len = 416821, overlap = 279.406
+PHY-3002 : Step(101): len = 428666, overlap = 248.875
+PHY-3002 : Step(102): len = 428099, overlap = 233.75
+PHY-3002 : Step(103): len = 430358, overlap = 220.031
+PHY-3002 : Step(104): len = 435092, overlap = 228.312
+PHY-3002 : Step(105): len = 439434, overlap = 219.969
+PHY-3002 : Step(106): len = 438025, overlap = 226.969
+PHY-3002 : Step(107): len = 437846, overlap = 212.281
+PHY-3002 : Step(108): len = 439888, overlap = 196.312
+PHY-3002 : Step(109): len = 441419, overlap = 195.469
+PHY-3002 : Step(110): len = 440166, overlap = 192.781
+PHY-3002 : Step(111): len = 441752, overlap = 205.062
+PHY-3002 : Step(112): len = 444167, overlap = 200.844
+PHY-3002 : Step(113): len = 444386, overlap = 213.188
+PHY-3002 : Step(114): len = 442239, overlap = 213.594
+PHY-3002 : Step(115): len = 441964, overlap = 221.656
+PHY-3002 : Step(116): len = 441721, overlap = 236.094
+PHY-3002 : Step(117): len = 440611, overlap = 228.219
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000189955
+PHY-3002 : Step(118): len = 450970, overlap = 235.625
+PHY-3002 : Step(119): len = 458604, overlap = 215.25
+PHY-3002 : Step(120): len = 457875, overlap = 220.031
+PHY-3002 : Step(121): len = 458684, overlap = 213.125
+PHY-3002 : Step(122): len = 462177, overlap = 218.094
+PHY-3002 : Step(123): len = 465235, overlap = 207.781
+PHY-3002 : Step(124): len = 464113, overlap = 201.812
+PHY-3002 : Step(125): len = 465197, overlap = 189.844
+PHY-3002 : Step(126): len = 467487, overlap = 183.906
+PHY-3002 : Step(127): len = 469003, overlap = 181.812
+PHY-3002 : Step(128): len = 468106, overlap = 175.25
+PHY-3002 : Step(129): len = 468307, overlap = 177.875
+PHY-3002 : Step(130): len = 469973, overlap = 179.656
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.00037991
+PHY-3002 : Step(131): len = 479687, overlap = 171.812
+PHY-3002 : Step(132): len = 489167, overlap = 170.594
+PHY-3002 : Step(133): len = 492588, overlap = 168.781
+PHY-3002 : Step(134): len = 496798, overlap = 167.438
+PHY-3002 : Step(135): len = 502405, overlap = 156.844
+PHY-3002 : Step(136): len = 507401, overlap = 145.656
+PHY-3002 : Step(137): len = 506966, overlap = 142.625
+PHY-3002 : Step(138): len = 507488, overlap = 142.312
+PHY-3002 : Step(139): len = 509081, overlap = 136.531
+PHY-3002 : Step(140): len = 509523, overlap = 132.594
+PHY-3002 : Step(141): len = 507504, overlap = 128.125
+PHY-3002 : Step(142): len = 507153, overlap = 131.938
+PHY-3002 : Step(143): len = 508284, overlap = 125.25
+PHY-3002 : Step(144): len = 508894, overlap = 122.531
+PHY-3002 : Step(145): len = 507430, overlap = 125.812
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000738843
+PHY-3002 : Step(146): len = 512844, overlap = 121.812
+PHY-3002 : Step(147): len = 520954, overlap = 124.781
+PHY-3002 : Step(148): len = 522355, overlap = 120.969
+PHY-3002 : Step(149): len = 524278, overlap = 118.906
+PHY-3002 : Step(150): len = 527457, overlap = 119.594
+PHY-3002 : Step(151): len = 529727, overlap = 123.281
+PHY-3002 : Step(152): len = 529566, overlap = 114.906
+PHY-3002 : Step(153): len = 530279, overlap = 111.75
+PHY-3002 : Step(154): len = 531834, overlap = 115.594
+PHY-3002 : Step(155): len = 532503, overlap = 116.156
+PHY-3002 : Step(156): len = 531919, overlap = 109.406
+PHY-3002 : Step(157): len = 532372, overlap = 111.625
+PHY-3002 : Step(158): len = 533717, overlap = 107.562
+PHY-3002 : Step(159): len = 534690, overlap = 109.656
+PHY-3002 : Step(160): len = 534019, overlap = 108.594
+PHY-3002 : Step(161): len = 534014, overlap = 108
+PHY-3002 : Step(162): len = 534924, overlap = 111.812
+PHY-3002 : Step(163): len = 535810, overlap = 111.938
+PHY-3002 : Step(164): len = 535290, overlap = 113.25
+PHY-3002 : Step(165): len = 535488, overlap = 116.688
+PHY-3002 : Step(166): len = 536203, overlap = 110.719
+PHY-3002 : Step(167): len = 536477, overlap = 112.062
+PHY-3002 : Step(168): len = 535765, overlap = 106.438
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00130154
+PHY-3002 : Step(169): len = 539078, overlap = 110.531
+PHY-3002 : Step(170): len = 543506, overlap = 109.344
+PHY-3002 : Step(171): len = 544693, overlap = 108.312
+PHY-3002 : Step(172): len = 545604, overlap = 108.5
+PHY-3002 : Step(173): len = 546909, overlap = 108.125
+PHY-3002 : Step(174): len = 547449, overlap = 108.469
+PHY-3002 : Step(175): len = 547102, overlap = 106.562
+PHY-3002 : Step(176): len = 547291, overlap = 101.875
+PHY-3002 : Step(177): len = 548730, overlap = 107.75
+PHY-3002 : Step(178): len = 549921, overlap = 104.188
+PHY-3002 : Step(179): len = 549725, overlap = 102.969
+PHY-3002 : Step(180): len = 549962, overlap = 101.938
+PHY-3002 : Step(181): len = 550998, overlap = 104.531
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00245972
+PHY-3002 : Step(182): len = 555364, overlap = 109.031
+PHY-3002 : Step(183): len = 561279, overlap = 109.25
+PHY-3002 : Step(184): len = 566317, overlap = 96.4062
+PHY-3002 : Step(185): len = 570136, overlap = 95.125
+PHY-3002 : Step(186): len = 573177, overlap = 96.4062
+PHY-3002 : Step(187): len = 576062, overlap = 98.875
+PHY-3002 : Step(188): len = 577191, overlap = 95.0312
+PHY-3002 : Step(189): len = 577808, overlap = 101.625
+PHY-3002 : Step(190): len = 578240, overlap = 100.188
+PHY-3002 : Step(191): len = 578238, overlap = 102.719
+PHY-3002 : Step(192): len = 577488, overlap = 100.656
+PHY-3002 : Step(193): len = 577146, overlap = 99.3438
+PHY-3002 : Step(194): len = 577021, overlap = 102.188
+PHY-3001 : :::14::: Try harder cell spreading with beta_ = 0.00455
+PHY-3002 : Step(195): len = 578103, overlap = 100.812
+PHY-3002 : Step(196): len = 579760, overlap = 101.375
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014507s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (323.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20636.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 741400, over cnt = 1730(4%), over = 7767, worst = 36
+PHY-1001 : End global iterations;  0.796197s wall, 1.062500s user + 0.031250s system = 1.093750s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 84.25, top5 = 63.23, top10 = 53.55, top15 = 47.83.
+PHY-3001 : End congestion estimation;  1.029753s wall, 1.296875s user + 0.031250s system = 1.328125s CPU (129.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20458 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.865048s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.82754e-05
+PHY-3002 : Step(197): len = 670493, overlap = 62.5312
+PHY-3002 : Step(198): len = 672432, overlap = 68.375
+PHY-3002 : Step(199): len = 666736, overlap = 62.5312
+PHY-3002 : Step(200): len = 663629, overlap = 61.125
+PHY-3002 : Step(201): len = 664235, overlap = 61.4688
+PHY-3002 : Step(202): len = 670588, overlap = 58
+PHY-3002 : Step(203): len = 673185, overlap = 57.1875
+PHY-3002 : Step(204): len = 679982, overlap = 54.5
+PHY-3002 : Step(205): len = 682965, overlap = 54.0938
+PHY-3002 : Step(206): len = 687086, overlap = 49.2188
+PHY-3002 : Step(207): len = 689685, overlap = 47.7812
+PHY-3002 : Step(208): len = 689777, overlap = 47.3125
+PHY-3002 : Step(209): len = 688330, overlap = 46.5938
+PHY-3002 : Step(210): len = 689327, overlap = 45.4062
+PHY-3002 : Step(211): len = 686982, overlap = 45.5
+PHY-3002 : Step(212): len = 685803, overlap = 41.9375
+PHY-3002 : Step(213): len = 683398, overlap = 40.625
+PHY-3002 : Step(214): len = 682399, overlap = 38.9062
+PHY-3002 : Step(215): len = 683560, overlap = 42.3125
+PHY-3002 : Step(216): len = 680907, overlap = 41.2812
+PHY-3002 : Step(217): len = 678540, overlap = 40
+PHY-3002 : Step(218): len = 677211, overlap = 39.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000196551
+PHY-3002 : Step(219): len = 679022, overlap = 40.125
+PHY-3002 : Step(220): len = 682809, overlap = 40.6562
+PHY-3002 : Step(221): len = 685253, overlap = 42.5625
+PHY-3002 : Step(222): len = 689877, overlap = 45.1562
+PHY-3002 : Step(223): len = 693132, overlap = 47.0625
+PHY-3002 : Step(224): len = 694611, overlap = 47.375
+PHY-3002 : Step(225): len = 695887, overlap = 47.125
+PHY-3002 : Step(226): len = 695205, overlap = 47.9062
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000393102
+PHY-3002 : Step(227): len = 699192, overlap = 47.0938
+PHY-3002 : Step(228): len = 705113, overlap = 44.9375
+PHY-3002 : Step(229): len = 707944, overlap = 45.2188
+PHY-3002 : Step(230): len = 713361, overlap = 44.9688
+PHY-3002 : Step(231): len = 718993, overlap = 45.7812
+PHY-3002 : Step(232): len = 725494, overlap = 40.75
+PHY-3002 : Step(233): len = 732506, overlap = 35.5625
+PHY-3002 : Step(234): len = 732178, overlap = 34.4062
+PHY-3002 : Step(235): len = 730959, overlap = 35.4688
+PHY-3002 : Step(236): len = 732452, overlap = 33.5312
+PHY-3002 : Step(237): len = 734064, overlap = 35.3438
+PHY-3002 : Step(238): len = 735533, overlap = 34.8125
+PHY-3002 : Step(239): len = 736831, overlap = 36.0312
+PHY-3002 : Step(240): len = 736678, overlap = 35.9062
+PHY-3002 : Step(241): len = 737951, overlap = 35.9375
+PHY-3002 : Step(242): len = 741043, overlap = 38.4062
+PHY-3002 : Step(243): len = 739829, overlap = 35.1562
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000786203
+PHY-3002 : Step(244): len = 744373, overlap = 36.125
+PHY-3002 : Step(245): len = 754285, overlap = 41.3125
+PHY-3002 : Step(246): len = 759718, overlap = 41.4688
+PHY-3002 : Step(247): len = 761431, overlap = 39.3125
+PHY-3002 : Step(248): len = 762433, overlap = 36.4688
+PHY-3002 : Step(249): len = 764737, overlap = 36.2812
+PHY-3002 : Step(250): len = 764948, overlap = 36.4062
+PHY-3002 : Step(251): len = 765676, overlap = 36.7812
+PHY-3002 : Step(252): len = 768171, overlap = 41.1562
+PHY-3002 : Step(253): len = 770723, overlap = 41.8125
+PHY-3002 : Step(254): len = 770649, overlap = 40.8125
+PHY-3002 : Step(255): len = 770358, overlap = 42.75
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.001331
+PHY-3002 : Step(256): len = 772299, overlap = 44.1875
+PHY-3002 : Step(257): len = 777706, overlap = 40
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 23/20636.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858752, over cnt = 2877(8%), over = 14685, worst = 69
+PHY-1001 : End global iterations;  1.413341s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 113.45, top5 = 81.16, top10 = 69.21, top15 = 62.10.
+PHY-3001 : End congestion estimation;  1.699232s wall, 2.234375s user + 0.031250s system = 2.265625s CPU (133.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20458 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.413051s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000125452
+PHY-3002 : Step(258): len = 773150, overlap = 282.781
+PHY-3002 : Step(259): len = 775865, overlap = 218.875
+PHY-3002 : Step(260): len = 760251, overlap = 179.375
+PHY-3002 : Step(261): len = 753860, overlap = 164.938
+PHY-3002 : Step(262): len = 746014, overlap = 147.875
+PHY-3002 : Step(263): len = 740827, overlap = 123.062
+PHY-3002 : Step(264): len = 734236, overlap = 123.875
+PHY-3002 : Step(265): len = 730303, overlap = 124.812
+PHY-3002 : Step(266): len = 723854, overlap = 122
+PHY-3002 : Step(267): len = 719814, overlap = 116.594
+PHY-3002 : Step(268): len = 713527, overlap = 120.156
+PHY-3002 : Step(269): len = 708201, overlap = 118.969
+PHY-3002 : Step(270): len = 703394, overlap = 119.781
+PHY-3002 : Step(271): len = 698244, overlap = 122.156
+PHY-3002 : Step(272): len = 695120, overlap = 127.562
+PHY-3002 : Step(273): len = 691103, overlap = 130
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000250904
+PHY-3002 : Step(274): len = 693576, overlap = 120.375
+PHY-3002 : Step(275): len = 694878, overlap = 119.812
+PHY-3002 : Step(276): len = 696242, overlap = 115.625
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000478521
+PHY-3002 : Step(277): len = 703513, overlap = 111.844
+PHY-3002 : Step(278): len = 709395, overlap = 106.188
+PHY-3002 : Step(279): len = 712055, overlap = 100.156
+PHY-3002 : Step(280): len = 713599, overlap = 96.9688
+PHY-3002 : Step(281): len = 715016, overlap = 93.6875
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000858884
+PHY-3002 : Step(282): len = 716058, overlap = 94.5
+PHY-3002 : Step(283): len = 720516, overlap = 87.6875
+PHY-3002 : Step(284): len = 728529, overlap = 82.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.0015231
+PHY-3002 : Step(285): len = 728412, overlap = 83.375
+PHY-3002 : Step(286): len = 732192, overlap = 81.0312
+PHY-3002 : Step(287): len = 742461, overlap = 76.5625
+PHY-3002 : Step(288): len = 747859, overlap = 71.1562
+PHY-3002 : Step(289): len = 748570, overlap = 67.7812
+PHY-3002 : Step(290): len = 748999, overlap = 67.5625
+PHY-3002 : Step(291): len = 750023, overlap = 64.7188
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86072, tnet num: 20458, tinst num: 18056, tnode num: 117507, tedge num: 137958.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.443557s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (99.6%)
+
+RUN-1004 : used memory is 590 MB, reserved memory is 573 MB, peak memory is 726 MB
+OPT-1001 : Total overflow 400.19 peak overflow 3.84
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 510/20636.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 846992, over cnt = 3215(9%), over = 12016, worst = 46
+PHY-1001 : End global iterations;  1.376680s wall, 2.000000s user + 0.015625s system = 2.015625s CPU (146.4%)
+
+PHY-1001 : Congestion index: top1 = 83.62, top5 = 65.89, top10 = 57.85, top15 = 53.23.
+PHY-1001 : End incremental global routing;  1.714236s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (137.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20458 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.920888s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (100.1%)
+
+OPT-1001 : 53 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17918 has valid locations, 334 needs to be replaced
+PHY-3001 : design contains 18337 instances, 7442 luts, 9674 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2003 with 6441 pins
+PHY-3001 : Found 3515 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 772944
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17177/20917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862256, over cnt = 3266(9%), over = 12193, worst = 46
+PHY-1001 : End global iterations;  0.250561s wall, 0.328125s user + 0.031250s system = 0.359375s CPU (143.4%)
+
+PHY-1001 : Congestion index: top1 = 83.08, top5 = 65.78, top10 = 58.03, top15 = 53.53.
+PHY-3001 : End congestion estimation;  0.512273s wall, 0.593750s user + 0.031250s system = 0.625000s CPU (122.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87201, tnet num: 20739, tinst num: 18337, tnode num: 119197, tedge num: 139654.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.489368s wall, 1.390625s user + 0.093750s system = 1.484375s CPU (99.7%)
+
+RUN-1004 : used memory is 634 MB, reserved memory is 623 MB, peak memory is 731 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.887426s wall, 2.375000s user + 0.093750s system = 2.468750s CPU (85.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(292): len = 771984, overlap = 0
+PHY-3002 : Step(293): len = 771283, overlap = 0
+PHY-3002 : Step(294): len = 770925, overlap = 0
+PHY-3002 : Step(295): len = 770644, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17261/20917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859560, over cnt = 3258(9%), over = 12205, worst = 46
+PHY-1001 : End global iterations;  0.209967s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (111.6%)
+
+PHY-1001 : Congestion index: top1 = 83.58, top5 = 66.03, top10 = 58.21, top15 = 53.66.
+PHY-3001 : End congestion estimation;  0.526474s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (106.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.985459s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000471896
+PHY-3002 : Step(296): len = 770559, overlap = 66.625
+PHY-3002 : Step(297): len = 770681, overlap = 66.2812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000943792
+PHY-3002 : Step(298): len = 770765, overlap = 66.5
+PHY-3002 : Step(299): len = 771322, overlap = 67.125
+PHY-3001 : Final: Len = 771322, Over = 67.125
+PHY-3001 : End incremental placement;  5.587773s wall, 5.328125s user + 0.250000s system = 5.578125s CPU (99.8%)
+
+OPT-1001 : Total overflow 407.25 peak overflow 3.84
+OPT-1001 : End high-fanout net optimization;  8.761359s wall, 9.203125s user + 0.312500s system = 9.515625s CPU (108.6%)
+
+OPT-1001 : Current memory(MB): used = 733, reserve = 721, peak = 751.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17227/20917.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863864, over cnt = 3212(9%), over = 11216, worst = 46
+PHY-1002 : len = 925016, over cnt = 2255(6%), over = 5498, worst = 24
+PHY-1002 : len = 969152, over cnt = 896(2%), over = 1896, worst = 17
+PHY-1002 : len = 983360, over cnt = 426(1%), over = 788, worst = 17
+PHY-1002 : len = 999984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.065422s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (137.7%)
+
+PHY-1001 : Congestion index: top1 = 65.00, top5 = 56.90, top10 = 52.41, top15 = 49.49.
+OPT-1001 : End congestion update;  2.336370s wall, 3.109375s user + 0.000000s system = 3.109375s CPU (133.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20739 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.832746s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (101.3%)
+
+OPT-0007 : Start: WNS -1068 TNS -1578 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 58 cells processed and 6908 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 27 cells processed and 1092 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 10 cells processed and 1100 slack improved
+OPT-0007 : Iter 4: improved WNS -1068 TNS -1578 NUM_FEPS 2 with 16 cells processed and 626 slack improved
+OPT-1001 : End global optimization;  3.210992s wall, 3.968750s user + 0.015625s system = 3.984375s CPU (124.1%)
+
+OPT-1001 : Current memory(MB): used = 710, reserve = 701, peak = 751.
+OPT-1001 : End physical optimization;  14.166059s wall, 15.453125s user + 0.359375s system = 15.812500s CPU (111.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7442 LUT to BLE ...
+SYN-4008 : Packed 7442 LUT and 3130 SEQ to BLE.
+SYN-4003 : Packing 6544 remaining SEQ's ...
+SYN-4005 : Packed 4099 SEQ with LUT/SLICE
+SYN-4006 : 515 single LUT's are left
+SYN-4006 : 2445 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9887/13634 primitive instances ...
+PHY-3001 : End packing;  1.723971s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6905 instances
+RUN-1001 : 3379 mslices, 3378 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17892 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10139 nets have 2 pins
+RUN-1001 : 6102 nets have [3 - 5] pins
+RUN-1001 : 972 nets have [6 - 10] pins
+RUN-1001 : 309 nets have [11 - 20] pins
+RUN-1001 : 338 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6903 instances, 6757 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2003 with 3734 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 775283, Over = 269.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7742/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 937088, over cnt = 2060(5%), over = 3336, worst = 8
+PHY-1002 : len = 944968, over cnt = 1325(3%), over = 1901, worst = 6
+PHY-1002 : len = 961208, over cnt = 353(1%), over = 469, worst = 6
+PHY-1002 : len = 965672, over cnt = 143(0%), over = 187, worst = 6
+PHY-1002 : len = 969128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.819811s wall, 2.515625s user + 0.078125s system = 2.593750s CPU (142.5%)
+
+PHY-1001 : Congestion index: top1 = 61.68, top5 = 54.38, top10 = 50.58, top15 = 47.93.
+PHY-3001 : End congestion estimation;  2.217335s wall, 2.906250s user + 0.078125s system = 2.984375s CPU (134.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74766, tnet num: 17714, tinst num: 6903, tnode num: 97990, tedge num: 125263.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.645051s wall, 1.625000s user + 0.015625s system = 1.640625s CPU (99.7%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 620 MB, peak memory is 751 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.532023s wall, 2.500000s user + 0.031250s system = 2.531250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.16756e-05
+PHY-3002 : Step(300): len = 760163, overlap = 263.5
+PHY-3002 : Step(301): len = 750200, overlap = 273.5
+PHY-3002 : Step(302): len = 743186, overlap = 273.75
+PHY-3002 : Step(303): len = 737330, overlap = 283.75
+PHY-3002 : Step(304): len = 733006, overlap = 285.5
+PHY-3002 : Step(305): len = 728790, overlap = 288.75
+PHY-3002 : Step(306): len = 724641, overlap = 282.75
+PHY-3002 : Step(307): len = 721243, overlap = 290.25
+PHY-3002 : Step(308): len = 718587, overlap = 295
+PHY-3002 : Step(309): len = 715498, overlap = 298.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103351
+PHY-3002 : Step(310): len = 718592, overlap = 292.75
+PHY-3002 : Step(311): len = 723335, overlap = 282.75
+PHY-3002 : Step(312): len = 726209, overlap = 272
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000206703
+PHY-3002 : Step(313): len = 733078, overlap = 257
+PHY-3002 : Step(314): len = 743191, overlap = 242.5
+PHY-3002 : Step(315): len = 744561, overlap = 238
+PHY-3002 : Step(316): len = 745128, overlap = 235.75
+PHY-3002 : Step(317): len = 746281, overlap = 237.25
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000361716
+PHY-3002 : Step(318): len = 752386, overlap = 234.5
+PHY-3002 : Step(319): len = 760032, overlap = 222.75
+PHY-3002 : Step(320): len = 769936, overlap = 215.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.374721s wall, 0.343750s user + 0.546875s system = 0.890625s CPU (237.7%)
+
+PHY-3001 : Trial Legalized: Len = 1.01115e+06
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 464/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.14116e+06, over cnt = 2938(8%), over = 4953, worst = 8
+PHY-1002 : len = 1.15975e+06, over cnt = 1910(5%), over = 2757, worst = 6
+PHY-1002 : len = 1.18143e+06, over cnt = 780(2%), over = 1059, worst = 6
+PHY-1002 : len = 1.1954e+06, over cnt = 180(0%), over = 240, worst = 4
+PHY-1002 : len = 1.2002e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.891341s wall, 4.078125s user + 0.093750s system = 4.171875s CPU (144.3%)
+
+PHY-1001 : Congestion index: top1 = 66.94, top5 = 60.99, top10 = 57.76, top15 = 55.24.
+PHY-3001 : End congestion estimation;  3.373752s wall, 4.562500s user + 0.093750s system = 4.656250s CPU (138.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.864371s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000190001
+PHY-3002 : Step(321): len = 960786, overlap = 80
+PHY-3002 : Step(322): len = 930409, overlap = 112.25
+PHY-3002 : Step(323): len = 911463, overlap = 129.75
+PHY-3002 : Step(324): len = 894390, overlap = 155.5
+PHY-3002 : Step(325): len = 876944, overlap = 175
+PHY-3002 : Step(326): len = 860846, overlap = 198.75
+PHY-3002 : Step(327): len = 848978, overlap = 211
+PHY-3002 : Step(328): len = 841151, overlap = 207
+PHY-3002 : Step(329): len = 833394, overlap = 208.5
+PHY-3002 : Step(330): len = 826731, overlap = 209.75
+PHY-3002 : Step(331): len = 821048, overlap = 213.5
+PHY-3002 : Step(332): len = 816560, overlap = 211.5
+PHY-3002 : Step(333): len = 812190, overlap = 208.25
+PHY-3002 : Step(334): len = 808005, overlap = 209
+PHY-3002 : Step(335): len = 804084, overlap = 216.25
+PHY-3002 : Step(336): len = 801032, overlap = 211.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000376923
+PHY-3002 : Step(337): len = 806608, overlap = 216.25
+PHY-3002 : Step(338): len = 810466, overlap = 216.75
+PHY-3002 : Step(339): len = 812115, overlap = 212.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000626472
+PHY-3002 : Step(340): len = 818722, overlap = 208.75
+PHY-3002 : Step(341): len = 821100, overlap = 206.25
+PHY-3002 : Step(342): len = 823277, overlap = 205.25
+PHY-3002 : Step(343): len = 825188, overlap = 202
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.100534s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (108.8%)
+
+PHY-3001 : Legalized: Len = 940650, Over = 0
+PHY-3001 : Spreading special nets. 529 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.130709s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.6%)
+
+PHY-3001 : 804 instances has been re-located, deltaX = 400, deltaY = 479, maxDist = 7.
+PHY-3001 : Final: Len = 954460, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74766, tnet num: 17714, tinst num: 6906, tnode num: 97990, tedge num: 125263.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.887756s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.3%)
+
+RUN-1004 : used memory is 648 MB, reserved memory is 658 MB, peak memory is 751 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3206/17892.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.09315e+06, over cnt = 2729(7%), over = 4499, worst = 7
+PHY-1002 : len = 1.1109e+06, over cnt = 1544(4%), over = 2155, worst = 6
+PHY-1002 : len = 1.12766e+06, over cnt = 558(1%), over = 767, worst = 6
+PHY-1002 : len = 1.13846e+06, over cnt = 111(0%), over = 141, worst = 4
+PHY-1002 : len = 1.14078e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations;  2.634670s wall, 3.546875s user + 0.000000s system = 3.546875s CPU (134.6%)
+
+PHY-1001 : Congestion index: top1 = 66.21, top5 = 59.42, top10 = 55.79, top15 = 53.28.
+PHY-1001 : End incremental global routing;  3.009300s wall, 3.906250s user + 0.000000s system = 3.906250s CPU (129.8%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17714 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.898164s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (100.9%)
+
+OPT-1001 : 3 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6816 has valid locations, 10 needs to be replaced
+PHY-3001 : design contains 6914 instances, 6765 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2003 with 3807 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 955976
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16413/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.14217e+06, over cnt = 31(0%), over = 41, worst = 5
+PHY-1002 : len = 1.14212e+06, over cnt = 18(0%), over = 23, worst = 5
+PHY-1002 : len = 1.14226e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.14235e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.14237e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.779262s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 66.21, top5 = 59.42, top10 = 55.79, top15 = 53.29.
+PHY-3001 : End congestion estimation;  1.109603s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74860, tnet num: 17724, tinst num: 6914, tnode num: 98104, tedge num: 125378.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.895745s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.7%)
+
+RUN-1004 : used memory is 674 MB, reserved memory is 669 MB, peak memory is 751 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.806052s wall, 2.812500s user + 0.000000s system = 2.812500s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(344): len = 955574, overlap = 0
+PHY-3002 : Step(345): len = 955341, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16408/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.14162e+06, over cnt = 22(0%), over = 36, worst = 6
+PHY-1002 : len = 1.14165e+06, over cnt = 19(0%), over = 21, worst = 3
+PHY-1002 : len = 1.14186e+06, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 1.14198e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.630270s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (101.6%)
+
+PHY-1001 : Congestion index: top1 = 66.21, top5 = 59.43, top10 = 55.79, top15 = 53.29.
+PHY-3001 : End congestion estimation;  0.956033s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (101.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.255207s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00121024
+PHY-3002 : Step(346): len = 955366, overlap = 0.25
+PHY-3002 : Step(347): len = 955366, overlap = 0.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005616s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 955350, Over = 0
+PHY-3001 : End spreading;  0.057825s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (108.1%)
+
+PHY-3001 : Final: Len = 955350, Over = 0
+PHY-3001 : End incremental placement;  6.604608s wall, 6.625000s user + 0.031250s system = 6.656250s CPU (100.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  11.028663s wall, 11.906250s user + 0.062500s system = 11.968750s CPU (108.5%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 750, peak = 758.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16411/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.14195e+06, over cnt = 12(0%), over = 14, worst = 3
+PHY-1002 : len = 1.14202e+06, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 1.14206e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.428423s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (98.5%)
+
+PHY-1001 : Congestion index: top1 = 66.21, top5 = 59.43, top10 = 55.79, top15 = 53.28.
+OPT-1001 : End congestion update;  0.750521s wall, 0.734375s user + 0.015625s system = 0.750000s CPU (99.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.762440s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (98.4%)
+
+OPT-0007 : Start: WNS -936 TNS -1450 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6826 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6914 instances, 6765 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2003 with 3807 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 958660, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059823s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.5%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 9, deltaY = 6, maxDist = 3.
+PHY-3001 : Final: Len = 958658, Over = 0
+PHY-3001 : End incremental legalization;  0.422338s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1450 NUM_FEPS 3 with 26 cells processed and 8700 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1450 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.070668s wall, 2.046875s user + 0.031250s system = 2.078125s CPU (100.4%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 750, peak = 758.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.727136s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16314/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.14536e+06, over cnt = 58(0%), over = 70, worst = 4
+PHY-1002 : len = 1.14546e+06, over cnt = 34(0%), over = 36, worst = 2
+PHY-1002 : len = 1.14566e+06, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 1.14571e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.14594e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.818308s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 66.01, top5 = 59.40, top10 = 55.81, top15 = 53.30.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.726631s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -936 TNS -1450 NUM_FEPS 3
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 65.620690
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -936ps with logic level 2 
+RUN-1001 :       #2 path slack -890ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 17902 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17902 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6826 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6914 instances, 6765 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2003 with 3807 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 958658, Over = 0
+PHY-3001 : End spreading;  0.057729s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (81.2%)
+
+PHY-3001 : Final: Len = 958658, Over = 0
+PHY-3001 : End incremental legalization;  0.376808s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.735112s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.9%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16422/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.14594e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.134294s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 66.01, top5 = 59.40, top10 = 55.81, top15 = 53.30.
+OPT-1001 : End congestion update;  0.452326s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.726692s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.9%)
+
+OPT-0007 : Start: WNS -936 TNS -1450 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6826 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6914 instances, 6765 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2003 with 3807 pins
+PHY-3001 : Found 1571 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 958730, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058788s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.3%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 958776, Over = 0
+PHY-3001 : End incremental legalization;  0.384221s wall, 0.375000s user + 0.046875s system = 0.421875s CPU (109.8%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1450 NUM_FEPS 3 with 1 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1450 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.673497s wall, 1.656250s user + 0.046875s system = 1.703125s CPU (101.8%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 750, peak = 758.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16420/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.146e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.14602e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.14602e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.427824s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.3%)
+
+PHY-1001 : Congestion index: top1 = 66.01, top5 = 59.40, top10 = 55.82, top15 = 53.30.
+OPT-1001 : End congestion update;  0.745139s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.729958s wall, 0.703125s user + 0.015625s system = 0.718750s CPU (98.5%)
+
+OPT-0007 : Start: WNS -936 TNS -1450 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -936 TNS -1450 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1450 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.635329s wall, 1.625000s user + 0.015625s system = 1.640625s CPU (100.3%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 750, peak = 758.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.728739s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 754, reserve = 750, peak = 758.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.731354s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.4%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16422/17902.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.14602e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.142526s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.7%)
+
+PHY-1001 : Congestion index: top1 = 66.01, top5 = 59.40, top10 = 55.82, top15 = 53.30.
+RUN-1001 : End congestion update;  0.484666s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.9%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.219485s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (99.9%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 750, peak = 758.
+OPT-1001 : End physical optimization;  24.462040s wall, 25.531250s user + 0.171875s system = 25.703125s CPU (105.1%)
+
+RUN-1003 : finish command "place" in  73.158700s wall, 112.187500s user + 7.093750s system = 119.281250s CPU (163.0%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 656 MB, peak memory is 758 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.691997s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (172.7%)
+
+RUN-1004 : used memory is 662 MB, reserved memory is 658 MB, peak memory is 758 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6916 instances
+RUN-1001 : 3383 mslices, 3382 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17902 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10140 nets have 2 pins
+RUN-1001 : 6098 nets have [3 - 5] pins
+RUN-1001 : 977 nets have [6 - 10] pins
+RUN-1001 : 313 nets have [11 - 20] pins
+RUN-1001 : 344 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74860, tnet num: 17724, tinst num: 6914, tnode num: 98104, tedge num: 125378.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.615170s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.6%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 629 MB, peak memory is 758 MB
+PHY-1001 : 3383 mslices, 3382 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.07694e+06, over cnt = 2972(8%), over = 4898, worst = 8
+PHY-1002 : len = 1.09542e+06, over cnt = 1865(5%), over = 2734, worst = 8
+PHY-1002 : len = 1.12257e+06, over cnt = 493(1%), over = 667, worst = 6
+PHY-1002 : len = 1.13332e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.13338e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.320638s wall, 4.375000s user + 0.062500s system = 4.437500s CPU (133.6%)
+
+PHY-1001 : Congestion index: top1 = 65.71, top5 = 59.31, top10 = 55.66, top15 = 53.07.
+PHY-1001 : End global routing;  3.654607s wall, 4.703125s user + 0.078125s system = 4.781250s CPU (130.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 723, reserve = 720, peak = 758.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 997, reserve = 994, peak = 997.
+PHY-1001 : End build detailed router design. 4.051081s wall, 4.046875s user + 0.015625s system = 4.062500s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 272008, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.890219s wall, 4.890625s user + 0.000000s system = 4.890625s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 272064, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.431729s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.7%)
+
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1030, peak = 1032.
+PHY-1001 : End phase 1; 5.335194s wall, 5.328125s user + 0.000000s system = 5.328125s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 72% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.68714e+06, over cnt = 2045(0%), over = 2048, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1048, peak = 1051.
+PHY-1001 : End initial routed; 47.245084s wall, 82.218750s user + 0.328125s system = 82.546875s CPU (174.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.197   |  -4.336   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.350834s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1060, reserve = 1058, peak = 1060.
+PHY-1001 : End phase 2; 50.595982s wall, 85.562500s user + 0.328125s system = 85.890625s CPU (169.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 5 pins with SWNS -1.948ns STNS -3.981ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.156712s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.7%)
+
+PHY-1022 : len = 2.68718e+06, over cnt = 2047(0%), over = 2050, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.453042s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.64133e+06, over cnt = 850(0%), over = 852, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.879920s wall, 5.031250s user + 0.015625s system = 5.046875s CPU (175.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.63766e+06, over cnt = 279(0%), over = 279, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.379959s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (118.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.63756e+06, over cnt = 55(0%), over = 55, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.901734s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (112.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.63748e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.562340s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (100.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.63768e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.197144s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (111.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.948   |  -3.981   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.548085s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (93.4%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 689 feed throughs used by 493 nets
+PHY-1001 : End commit to database; 2.394229s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1171, peak = 1169.
+PHY-1001 : End phase 3; 12.728020s wall, 15.031250s user + 0.031250s system = 15.062500s CPU (118.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.948ns STNS -3.981ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.148076s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.5%)
+
+PHY-1022 : len = 2.63768e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.404684s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.948ns, -3.981ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.63766e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.170236s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16824(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.948   |  -3.981   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.339747s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 690 feed throughs used by 493 nets
+PHY-1001 : End commit to database; 2.472920s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (100.5%)
+
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1180, peak = 1178.
+PHY-1001 : End phase 4; 6.435742s wall, 6.437500s user + 0.000000s system = 6.437500s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.63766e+06
+PHY-1001 : Current memory(MB): used = 1179, reserve = 1182, peak = 1179.
+PHY-1001 : End export database. 0.067366s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.8%)
+
+PHY-1001 : End detail routing;  79.625685s wall, 116.875000s user + 0.375000s system = 117.250000s CPU (147.3%)
+
+RUN-1003 : finish command "route" in  85.970883s wall, 124.250000s user + 0.468750s system = 124.718750s CPU (145.1%)
+
+RUN-1004 : used memory is 1107 MB, reserved memory is 1107 MB, peak memory is 1179 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10231   out of  19600   52.20%
+#reg                     9808   out of  19600   50.04%
+#le                     12592
+  #lut only              2784   out of  12592   22.11%
+  #reg only              2361   out of  12592   18.75%
+  #lut&reg               7447   out of  12592   59.14%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1794
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1475
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1435
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               968
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    148
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         72
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_a/u_ADconfig/reg10_syn_20.f1             3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             exdev_ctl_a/reg0_syn_183.f1                        3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P141       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P110       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P82        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P69        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12592  |9204    |1027    |9838    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |522    |396     |23      |448     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |105    |91      |4       |91      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |24     |24      |0       |17      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |779    |487     |96      |561     |0       |0       |
+|    u_ADconfig                |AD_config            |191    |158     |25      |136     |0       |0       |
+|    u_gen_sp                  |gen_sp               |280    |174     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |768    |547     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |185    |154     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |272    |188     |71      |119     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3030   |2234    |306     |2285    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |10     |2       |0       |10      |0       |0       |
+|    u_ad_sampling             |ad_sampling          |171    |136     |17      |133     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1      |0       |0       |1       |0       |0       |
+|    u_sort                    |sort                 |2819   |2084    |289     |2112    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |3       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2447   |1855    |253     |1773    |22      |0       |
+|        channelPart           |channel_part_8478    |146    |132     |3       |131     |0       |0       |
+|        fifo_adc              |fifo_adc             |55     |46      |9       |40      |0       |0       |
+|        ram_switch            |ram_switch           |1829   |1324    |197     |1333    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |237    |210     |27      |128     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |16      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|          insert              |insert               |1003   |561     |170     |710     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |589    |553     |0       |495     |0       |0       |
+|        read_ram_i            |read_ram             |381    |322     |44      |237     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |223    |183     |40      |151     |0       |0       |
+|          read_ram_data       |read_ram_data        |155    |137     |4       |83      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |298    |168     |36      |274     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3420   |2625    |349     |2316    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |185    |110     |17      |143     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |3198   |2505    |332     |2136    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |3       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |3       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2780   |2209    |290     |1785    |22      |1       |
+|        channelPart           |channel_part_8478    |229    |226     |3       |134     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |2099   |1658    |197     |1369    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |235    |208     |27      |104     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |31     |28      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|          insert              |insert               |997    |608     |170     |700     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |867    |842     |0       |565     |0       |0       |
+|        read_ram_i            |read_ram_rev         |360    |252     |81      |209     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |295    |210     |73      |162     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |42      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets   
+    #1          1       10078  
+    #2          2       3952   
+    #3          3       1505   
+    #4          4        638   
+    #5        5-10      1040   
+    #6        11-50      565   
+    #7       51-100      26    
+    #8       101-500      1    
+    #9        >500        1    
+  Average     2.88             
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.100183s wall, 3.578125s user + 0.031250s system = 3.609375s CPU (171.9%)
+
+RUN-1004 : used memory is 1109 MB, reserved memory is 1108 MB, peak memory is 1179 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74860, tnet num: 17724, tinst num: 6914, tnode num: 98104, tedge num: 125378.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.644385s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.8%)
+
+RUN-1004 : used memory is 1114 MB, reserved memory is 1113 MB, peak memory is 1179 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17724 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.515140s wall, 1.500000s user + 0.015625s system = 1.515625s CPU (100.0%)
+
+RUN-1004 : used memory is 1116 MB, reserved memory is 1114 MB, peak memory is 1179 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6914
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17902, pip num: 182616
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 690
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3221 valid insts, and 501664 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.015702s wall, 67.265625s user + 0.062500s system = 67.328125s CPU (672.2%)
+
+RUN-1004 : used memory is 1287 MB, reserved memory is 1284 MB, peak memory is 1402 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_105057.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_110303.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_110303.log
new file mode 100644
index 0000000..cf85047
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_110303.log
@@ -0,0 +1,1903 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:03:03 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.135790s wall, 2.046875s user + 0.078125s system = 2.125000s CPU (99.5%)
+
+RUN-1004 : used memory is 347 MB, reserved memory is 317 MB, peak memory is 351 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2977 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2415 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2254 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17981 instances
+RUN-0007 : 7280 luts, 9478 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20559 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13596 nets have 2 pins
+RUN-1001 : 5491 nets have [3 - 5] pins
+RUN-1001 : 1061 nets have [6 - 10] pins
+RUN-1001 : 161 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 52 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     791     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3910     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     59     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 144
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17979 instances, 7280 luts, 9478 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1967 with 6299 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85854, tnet num: 20381, tinst num: 17979, tnode num: 117239, tedge num: 137676.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.153745s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (100.2%)
+
+RUN-1004 : used memory is 542 MB, reserved memory is 519 MB, peak memory is 542 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20381 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.930571s wall, 1.890625s user + 0.046875s system = 1.937500s CPU (100.4%)
+
+PHY-3001 : Found 3477 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.14588e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17979.
+PHY-3001 : Level 1 #clusters 2038.
+PHY-3001 : End clustering;  0.127123s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (98.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.31003e+06, overlap = 487.969
+PHY-3002 : Step(2): len = 1.22517e+06, overlap = 473.25
+PHY-3002 : Step(3): len = 824791, overlap = 569.312
+PHY-3002 : Step(4): len = 766612, overlap = 600.969
+PHY-3002 : Step(5): len = 590189, overlap = 744.844
+PHY-3002 : Step(6): len = 547419, overlap = 817.156
+PHY-3002 : Step(7): len = 444966, overlap = 924.031
+PHY-3002 : Step(8): len = 411183, overlap = 956.344
+PHY-3002 : Step(9): len = 370448, overlap = 994.875
+PHY-3002 : Step(10): len = 340028, overlap = 1063.81
+PHY-3002 : Step(11): len = 309722, overlap = 1107.94
+PHY-3002 : Step(12): len = 283610, overlap = 1118.66
+PHY-3002 : Step(13): len = 264787, overlap = 1203.88
+PHY-3002 : Step(14): len = 240940, overlap = 1273.84
+PHY-3002 : Step(15): len = 220629, overlap = 1316.41
+PHY-3002 : Step(16): len = 193606, overlap = 1358.19
+PHY-3002 : Step(17): len = 179988, overlap = 1378.84
+PHY-3002 : Step(18): len = 170195, overlap = 1412.06
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.25242e-07
+PHY-3002 : Step(19): len = 170212, overlap = 1379.25
+PHY-3002 : Step(20): len = 194099, overlap = 1291.53
+PHY-3002 : Step(21): len = 196163, overlap = 1292.06
+PHY-3002 : Step(22): len = 198861, overlap = 1277.38
+PHY-3002 : Step(23): len = 195717, overlap = 1278.12
+PHY-3002 : Step(24): len = 196963, overlap = 1271.25
+PHY-3002 : Step(25): len = 193675, overlap = 1208.03
+PHY-3002 : Step(26): len = 194634, overlap = 1184.31
+PHY-3002 : Step(27): len = 191505, overlap = 1188.03
+PHY-3002 : Step(28): len = 190451, overlap = 1178.84
+PHY-3002 : Step(29): len = 186870, overlap = 1166.09
+PHY-3002 : Step(30): len = 186059, overlap = 1191.78
+PHY-3002 : Step(31): len = 182981, overlap = 1231.31
+PHY-3002 : Step(32): len = 182492, overlap = 1241.56
+PHY-3002 : Step(33): len = 180594, overlap = 1236.06
+PHY-3002 : Step(34): len = 180235, overlap = 1229.88
+PHY-3002 : Step(35): len = 179279, overlap = 1235.47
+PHY-3002 : Step(36): len = 178289, overlap = 1234.47
+PHY-3002 : Step(37): len = 177264, overlap = 1237.59
+PHY-3002 : Step(38): len = 175909, overlap = 1226.91
+PHY-3002 : Step(39): len = 174249, overlap = 1231.44
+PHY-3002 : Step(40): len = 172634, overlap = 1245.59
+PHY-3002 : Step(41): len = 171374, overlap = 1244.41
+PHY-3002 : Step(42): len = 169523, overlap = 1243.81
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.65048e-06
+PHY-3002 : Step(43): len = 171409, overlap = 1227.69
+PHY-3002 : Step(44): len = 183394, overlap = 1184.34
+PHY-3002 : Step(45): len = 187287, overlap = 1127.09
+PHY-3002 : Step(46): len = 191350, overlap = 1111.72
+PHY-3002 : Step(47): len = 193865, overlap = 1111.44
+PHY-3002 : Step(48): len = 195374, overlap = 1099.31
+PHY-3002 : Step(49): len = 194656, overlap = 1104.94
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.30097e-06
+PHY-3002 : Step(50): len = 200698, overlap = 1083.44
+PHY-3002 : Step(51): len = 214238, overlap = 1043.78
+PHY-3002 : Step(52): len = 219830, overlap = 986.219
+PHY-3002 : Step(53): len = 224347, overlap = 958.312
+PHY-3002 : Step(54): len = 226944, overlap = 918.844
+PHY-3002 : Step(55): len = 230250, overlap = 917.844
+PHY-3002 : Step(56): len = 233308, overlap = 917.688
+PHY-3002 : Step(57): len = 234150, overlap = 926.344
+PHY-3002 : Step(58): len = 233994, overlap = 928.156
+PHY-3002 : Step(59): len = 232937, overlap = 918.219
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 6.60193e-06
+PHY-3002 : Step(60): len = 243503, overlap = 883.875
+PHY-3002 : Step(61): len = 264401, overlap = 807.219
+PHY-3002 : Step(62): len = 277695, overlap = 714.625
+PHY-3002 : Step(63): len = 288129, overlap = 677.719
+PHY-3002 : Step(64): len = 293485, overlap = 667
+PHY-3002 : Step(65): len = 293185, overlap = 644.5
+PHY-3002 : Step(66): len = 291600, overlap = 624.375
+PHY-3002 : Step(67): len = 289956, overlap = 624.094
+PHY-3002 : Step(68): len = 288151, overlap = 634.344
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.32039e-05
+PHY-3002 : Step(69): len = 305567, overlap = 592.281
+PHY-3002 : Step(70): len = 321514, overlap = 528.969
+PHY-3002 : Step(71): len = 329014, overlap = 459.719
+PHY-3002 : Step(72): len = 333086, overlap = 399.938
+PHY-3002 : Step(73): len = 332686, overlap = 394.062
+PHY-3002 : Step(74): len = 334792, overlap = 390.562
+PHY-3002 : Step(75): len = 332943, overlap = 391.406
+PHY-3002 : Step(76): len = 333307, overlap = 395.938
+PHY-3002 : Step(77): len = 332456, overlap = 380.469
+PHY-3002 : Step(78): len = 330857, overlap = 397.312
+PHY-3002 : Step(79): len = 328551, overlap = 408.125
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.64077e-05
+PHY-3002 : Step(80): len = 348480, overlap = 355.781
+PHY-3002 : Step(81): len = 360606, overlap = 334.281
+PHY-3002 : Step(82): len = 360092, overlap = 344.656
+PHY-3002 : Step(83): len = 361023, overlap = 360.125
+PHY-3002 : Step(84): len = 362194, overlap = 335.062
+PHY-3002 : Step(85): len = 363653, overlap = 326.5
+PHY-3002 : Step(86): len = 362126, overlap = 338.219
+PHY-3002 : Step(87): len = 362613, overlap = 336.75
+PHY-3002 : Step(88): len = 363354, overlap = 347.25
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 5.28155e-05
+PHY-3002 : Step(89): len = 380979, overlap = 300.656
+PHY-3002 : Step(90): len = 394368, overlap = 290.531
+PHY-3002 : Step(91): len = 394095, overlap = 261.656
+PHY-3002 : Step(92): len = 397949, overlap = 254.562
+PHY-3002 : Step(93): len = 401100, overlap = 232.938
+PHY-3002 : Step(94): len = 404222, overlap = 229.562
+PHY-3002 : Step(95): len = 401920, overlap = 235.062
+PHY-3002 : Step(96): len = 402973, overlap = 233.469
+PHY-3002 : Step(97): len = 404386, overlap = 228.75
+PHY-3002 : Step(98): len = 406276, overlap = 234.031
+PHY-3002 : Step(99): len = 402627, overlap = 230.656
+PHY-3002 : Step(100): len = 402362, overlap = 228.031
+PHY-3002 : Step(101): len = 403175, overlap = 222.5
+PHY-3002 : Step(102): len = 404086, overlap = 210.594
+PHY-3002 : Step(103): len = 401877, overlap = 220.375
+PHY-3002 : Step(104): len = 401590, overlap = 234.812
+PHY-3002 : Step(105): len = 403330, overlap = 248.594
+PHY-3002 : Step(106): len = 405481, overlap = 257.531
+PHY-3002 : Step(107): len = 402745, overlap = 266.812
+PHY-3002 : Step(108): len = 401994, overlap = 272.875
+PHY-3002 : Step(109): len = 402315, overlap = 261.25
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000105631
+PHY-3002 : Step(110): len = 417263, overlap = 259.312
+PHY-3002 : Step(111): len = 428636, overlap = 249.188
+PHY-3002 : Step(112): len = 428958, overlap = 249.781
+PHY-3002 : Step(113): len = 429228, overlap = 238.719
+PHY-3002 : Step(114): len = 430429, overlap = 221.688
+PHY-3002 : Step(115): len = 432162, overlap = 214.531
+PHY-3002 : Step(116): len = 431340, overlap = 216
+PHY-3002 : Step(117): len = 431212, overlap = 218.469
+PHY-3002 : Step(118): len = 434162, overlap = 211.438
+PHY-3002 : Step(119): len = 436499, overlap = 221.219
+PHY-3002 : Step(120): len = 434997, overlap = 212.812
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000209373
+PHY-3002 : Step(121): len = 443840, overlap = 211.875
+PHY-3002 : Step(122): len = 452208, overlap = 203.438
+PHY-3002 : Step(123): len = 452230, overlap = 193.188
+PHY-3002 : Step(124): len = 453269, overlap = 188.312
+PHY-3002 : Step(125): len = 457241, overlap = 180.75
+PHY-3002 : Step(126): len = 460883, overlap = 179.031
+PHY-3002 : Step(127): len = 460021, overlap = 182.25
+PHY-3002 : Step(128): len = 460318, overlap = 180.375
+PHY-3002 : Step(129): len = 461995, overlap = 183.188
+PHY-3002 : Step(130): len = 463061, overlap = 176.719
+PHY-3002 : Step(131): len = 460993, overlap = 173.188
+PHY-3002 : Step(132): len = 460472, overlap = 170.781
+PHY-3002 : Step(133): len = 461616, overlap = 164.938
+PHY-3002 : Step(134): len = 462212, overlap = 158.531
+PHY-3002 : Step(135): len = 461166, overlap = 158
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000391762
+PHY-3002 : Step(136): len = 468147, overlap = 153.406
+PHY-3002 : Step(137): len = 475481, overlap = 147.875
+PHY-3002 : Step(138): len = 475643, overlap = 153.781
+PHY-3002 : Step(139): len = 476434, overlap = 158.438
+PHY-3002 : Step(140): len = 478808, overlap = 157.062
+PHY-3002 : Step(141): len = 481445, overlap = 151
+PHY-3002 : Step(142): len = 482072, overlap = 150.281
+PHY-3002 : Step(143): len = 484227, overlap = 142.906
+PHY-3002 : Step(144): len = 486751, overlap = 141.406
+PHY-3002 : Step(145): len = 488039, overlap = 140.219
+PHY-3002 : Step(146): len = 487567, overlap = 138.562
+PHY-3002 : Step(147): len = 487946, overlap = 133.125
+PHY-3002 : Step(148): len = 489150, overlap = 131.656
+PHY-3002 : Step(149): len = 489736, overlap = 130.969
+PHY-3002 : Step(150): len = 489319, overlap = 132.344
+PHY-3002 : Step(151): len = 489712, overlap = 129.781
+PHY-3002 : Step(152): len = 490064, overlap = 129.625
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000759681
+PHY-3002 : Step(153): len = 494053, overlap = 128.031
+PHY-3002 : Step(154): len = 499671, overlap = 121.812
+PHY-3002 : Step(155): len = 501768, overlap = 122.938
+PHY-3002 : Step(156): len = 504050, overlap = 124
+PHY-3002 : Step(157): len = 505656, overlap = 122.188
+PHY-3002 : Step(158): len = 506510, overlap = 123.219
+PHY-3002 : Step(159): len = 506513, overlap = 120.562
+PHY-3002 : Step(160): len = 506762, overlap = 118.125
+PHY-3002 : Step(161): len = 507362, overlap = 116.969
+PHY-3002 : Step(162): len = 507676, overlap = 116
+PHY-3002 : Step(163): len = 507510, overlap = 112.406
+PHY-3002 : Step(164): len = 507866, overlap = 114.312
+PHY-3002 : Step(165): len = 508390, overlap = 117.75
+PHY-3002 : Step(166): len = 508743, overlap = 118.281
+PHY-3002 : Step(167): len = 508563, overlap = 115.125
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00132475
+PHY-3002 : Step(168): len = 511301, overlap = 115.25
+PHY-3002 : Step(169): len = 514498, overlap = 113.625
+PHY-3002 : Step(170): len = 515196, overlap = 114.062
+PHY-3002 : Step(171): len = 516153, overlap = 115.156
+PHY-3002 : Step(172): len = 517864, overlap = 109.094
+PHY-3002 : Step(173): len = 519192, overlap = 107.688
+PHY-3002 : Step(174): len = 519874, overlap = 105.5
+PHY-3002 : Step(175): len = 521957, overlap = 99.6562
+PHY-3002 : Step(176): len = 524154, overlap = 98.4062
+PHY-3002 : Step(177): len = 525800, overlap = 100.562
+PHY-3002 : Step(178): len = 525879, overlap = 93.9062
+PHY-3002 : Step(179): len = 526108, overlap = 89.8438
+PHY-3002 : Step(180): len = 526834, overlap = 96.625
+PHY-3002 : Step(181): len = 527201, overlap = 95.8438
+PHY-3002 : Step(182): len = 526897, overlap = 97.4062
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00226548
+PHY-3002 : Step(183): len = 528070, overlap = 96.0312
+PHY-3002 : Step(184): len = 528819, overlap = 93.5938
+PHY-3002 : Step(185): len = 529237, overlap = 94.875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.010852s wall, 0.031250s user + 0.031250s system = 0.062500s CPU (575.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20559.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 688440, over cnt = 1607(4%), over = 7228, worst = 45
+PHY-1001 : End global iterations;  0.746426s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (125.6%)
+
+PHY-1001 : Congestion index: top1 = 78.56, top5 = 58.91, top10 = 50.57, top15 = 45.40.
+PHY-3001 : End congestion estimation;  0.980056s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (119.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20381 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868670s wall, 0.843750s user + 0.031250s system = 0.875000s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.44928e-05
+PHY-3002 : Step(186): len = 622794, overlap = 46.1875
+PHY-3002 : Step(187): len = 629619, overlap = 57.4375
+PHY-3002 : Step(188): len = 625606, overlap = 62.125
+PHY-3002 : Step(189): len = 619329, overlap = 68.4062
+PHY-3002 : Step(190): len = 616526, overlap = 71.3438
+PHY-3002 : Step(191): len = 620029, overlap = 58.625
+PHY-3002 : Step(192): len = 634388, overlap = 62.2812
+PHY-3002 : Step(193): len = 638089, overlap = 60.5312
+PHY-3002 : Step(194): len = 637716, overlap = 64.0625
+PHY-3002 : Step(195): len = 640926, overlap = 70.4062
+PHY-3002 : Step(196): len = 647243, overlap = 64.9062
+PHY-3002 : Step(197): len = 650315, overlap = 64.8125
+PHY-3002 : Step(198): len = 651212, overlap = 60.4688
+PHY-3002 : Step(199): len = 650780, overlap = 60.2188
+PHY-3002 : Step(200): len = 653524, overlap = 59.2188
+PHY-3002 : Step(201): len = 657532, overlap = 53.7188
+PHY-3002 : Step(202): len = 657843, overlap = 54
+PHY-3002 : Step(203): len = 658096, overlap = 53.9062
+PHY-3002 : Step(204): len = 658462, overlap = 51.5625
+PHY-3002 : Step(205): len = 658296, overlap = 48.5938
+PHY-3002 : Step(206): len = 659237, overlap = 47.0625
+PHY-3002 : Step(207): len = 658355, overlap = 45.625
+PHY-3002 : Step(208): len = 656894, overlap = 46
+PHY-3002 : Step(209): len = 655873, overlap = 46.1562
+PHY-3002 : Step(210): len = 655700, overlap = 43.2812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000188986
+PHY-3002 : Step(211): len = 657494, overlap = 42.9688
+PHY-3002 : Step(212): len = 662265, overlap = 42.5625
+PHY-3002 : Step(213): len = 664249, overlap = 40.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000321001
+PHY-3002 : Step(214): len = 666914, overlap = 40.9375
+PHY-3002 : Step(215): len = 678660, overlap = 38.5938
+PHY-3002 : Step(216): len = 685382, overlap = 36
+PHY-3002 : Step(217): len = 687349, overlap = 35.7188
+PHY-3002 : Step(218): len = 688374, overlap = 39.0938
+PHY-3002 : Step(219): len = 691225, overlap = 40.625
+PHY-3002 : Step(220): len = 693047, overlap = 42.9375
+PHY-3002 : Step(221): len = 693897, overlap = 42.2812
+PHY-3002 : Step(222): len = 695654, overlap = 46.3125
+PHY-3002 : Step(223): len = 696790, overlap = 44.2812
+PHY-3002 : Step(224): len = 696957, overlap = 44.2812
+PHY-3002 : Step(225): len = 696582, overlap = 43.1875
+PHY-3002 : Step(226): len = 697764, overlap = 44.5
+PHY-3002 : Step(227): len = 699194, overlap = 39.3438
+PHY-3002 : Step(228): len = 699141, overlap = 39.6562
+PHY-3002 : Step(229): len = 700297, overlap = 40.0938
+PHY-3002 : Step(230): len = 703878, overlap = 39.4375
+PHY-3002 : Step(231): len = 703402, overlap = 39.5938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000642002
+PHY-3002 : Step(232): len = 704710, overlap = 38.375
+PHY-3002 : Step(233): len = 710992, overlap = 36
+PHY-3002 : Step(234): len = 714586, overlap = 34.7188
+PHY-3002 : Step(235): len = 718147, overlap = 28.6875
+PHY-3002 : Step(236): len = 725186, overlap = 26.1562
+PHY-3002 : Step(237): len = 730404, overlap = 23.3125
+PHY-3002 : Step(238): len = 730412, overlap = 22.6562
+PHY-3002 : Step(239): len = 729581, overlap = 21.5938
+PHY-3002 : Step(240): len = 729147, overlap = 21.4688
+PHY-3002 : Step(241): len = 730076, overlap = 19.9375
+PHY-3002 : Step(242): len = 729519, overlap = 17.5312
+PHY-3002 : Step(243): len = 729798, overlap = 17.8125
+PHY-3002 : Step(244): len = 731813, overlap = 17.4375
+PHY-3002 : Step(245): len = 734770, overlap = 19.5
+PHY-3002 : Step(246): len = 735440, overlap = 18.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.001284
+PHY-3002 : Step(247): len = 736717, overlap = 19.4375
+PHY-3002 : Step(248): len = 742515, overlap = 21.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 57/20559.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 818000, over cnt = 2848(8%), over = 14301, worst = 71
+PHY-1001 : End global iterations;  1.443011s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (134.3%)
+
+PHY-1001 : Congestion index: top1 = 106.36, top5 = 77.95, top10 = 66.23, top15 = 59.41.
+PHY-3001 : End congestion estimation;  1.721945s wall, 2.203125s user + 0.015625s system = 2.218750s CPU (128.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20381 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.261967s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000136961
+PHY-3002 : Step(249): len = 737451, overlap = 250.281
+PHY-3002 : Step(250): len = 738155, overlap = 197.656
+PHY-3002 : Step(251): len = 731175, overlap = 190.531
+PHY-3002 : Step(252): len = 726864, overlap = 178.719
+PHY-3002 : Step(253): len = 722050, overlap = 160.781
+PHY-3002 : Step(254): len = 720722, overlap = 148.844
+PHY-3002 : Step(255): len = 715898, overlap = 143.875
+PHY-3002 : Step(256): len = 713304, overlap = 140.719
+PHY-3002 : Step(257): len = 708586, overlap = 129.188
+PHY-3002 : Step(258): len = 707459, overlap = 127.25
+PHY-3002 : Step(259): len = 703472, overlap = 120.625
+PHY-3002 : Step(260): len = 701174, overlap = 121.156
+PHY-3002 : Step(261): len = 698386, overlap = 120.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000273922
+PHY-3002 : Step(262): len = 699303, overlap = 108.656
+PHY-3002 : Step(263): len = 702332, overlap = 102.438
+PHY-3002 : Step(264): len = 705387, overlap = 98.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000547845
+PHY-3002 : Step(265): len = 709237, overlap = 93.625
+PHY-3002 : Step(266): len = 718521, overlap = 80.25
+PHY-3002 : Step(267): len = 725945, overlap = 79.3438
+PHY-3002 : Step(268): len = 726052, overlap = 80.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00109569
+PHY-3002 : Step(269): len = 727738, overlap = 79.75
+PHY-3002 : Step(270): len = 732386, overlap = 76.875
+PHY-3002 : Step(271): len = 737073, overlap = 76.7188
+PHY-3002 : Step(272): len = 739821, overlap = 74.4688
+PHY-3002 : Step(273): len = 741317, overlap = 72.625
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85854, tnet num: 20381, tinst num: 17979, tnode num: 117239, tedge num: 137676.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.436601s wall, 1.390625s user + 0.046875s system = 1.437500s CPU (100.1%)
+
+RUN-1004 : used memory is 586 MB, reserved memory is 568 MB, peak memory is 718 MB
+OPT-1001 : Total overflow 388.56 peak overflow 4.06
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 974/20559.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 834928, over cnt = 3167(8%), over = 11768, worst = 51
+PHY-1001 : End global iterations;  1.310085s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 80.75, top5 = 62.49, top10 = 55.32, top15 = 51.00.
+PHY-1001 : End incremental global routing;  1.654515s wall, 2.156250s user + 0.000000s system = 2.156250s CPU (130.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20381 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.906342s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.0%)
+
+OPT-1001 : 49 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17845 has valid locations, 357 needs to be replaced
+PHY-3001 : design contains 18287 instances, 7395 luts, 9671 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1967 with 6428 pins
+PHY-3001 : Found 3512 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 765030
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17185/20867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 852936, over cnt = 3208(9%), over = 11817, worst = 51
+PHY-1001 : End global iterations;  0.240090s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (136.7%)
+
+PHY-1001 : Congestion index: top1 = 80.73, top5 = 62.61, top10 = 55.62, top15 = 51.41.
+PHY-3001 : End congestion estimation;  0.498016s wall, 0.578125s user + 0.015625s system = 0.593750s CPU (119.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87114, tnet num: 20689, tinst num: 18287, tnode num: 119116, tedge num: 139580.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.456339s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.8%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 620 MB, peak memory is 723 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.407701s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(274): len = 763761, overlap = 0
+PHY-3002 : Step(275): len = 763380, overlap = 0
+PHY-3002 : Step(276): len = 763230, overlap = 0
+PHY-3002 : Step(277): len = 763163, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17264/20867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 849688, over cnt = 3237(9%), over = 11927, worst = 51
+PHY-1001 : End global iterations;  0.217650s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (122.0%)
+
+PHY-1001 : Congestion index: top1 = 81.03, top5 = 63.01, top10 = 56.11, top15 = 51.76.
+PHY-3001 : End congestion estimation;  0.488691s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (111.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.956244s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000616869
+PHY-3002 : Step(278): len = 763150, overlap = 74.5
+PHY-3002 : Step(279): len = 763680, overlap = 74.9375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00123374
+PHY-3002 : Step(280): len = 764179, overlap = 75.0312
+PHY-3002 : Step(281): len = 764884, overlap = 75.125
+PHY-3001 : Final: Len = 764884, Over = 75.125
+PHY-3001 : End incremental placement;  5.008231s wall, 5.203125s user + 0.296875s system = 5.500000s CPU (109.8%)
+
+OPT-1001 : Total overflow 396.22 peak overflow 4.12
+OPT-1001 : End high-fanout net optimization;  8.217196s wall, 8.906250s user + 0.312500s system = 9.218750s CPU (112.2%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 713, peak = 741.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17222/20867.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 854376, over cnt = 3174(9%), over = 10887, worst = 51
+PHY-1002 : len = 902616, over cnt = 2273(6%), over = 6071, worst = 37
+PHY-1002 : len = 950432, over cnt = 842(2%), over = 2018, worst = 20
+PHY-1002 : len = 964432, over cnt = 460(1%), over = 949, worst = 17
+PHY-1002 : len = 978056, over cnt = 27(0%), over = 52, worst = 4
+PHY-1001 : End global iterations;  1.887877s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (136.6%)
+
+PHY-1001 : Congestion index: top1 = 63.47, top5 = 54.63, top10 = 50.33, top15 = 47.56.
+OPT-1001 : End congestion update;  2.159124s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (131.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20689 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.791810s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.7%)
+
+OPT-0007 : Start: WNS -1018 TNS -1578 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1578 NUM_FEPS 2 with 67 cells processed and 5400 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1578 NUM_FEPS 2 with 10 cells processed and 600 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1578 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+OPT-1001 : End global optimization;  2.993357s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (122.7%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 689, peak = 741.
+OPT-1001 : End physical optimization;  13.247042s wall, 14.562500s user + 0.390625s system = 14.953125s CPU (112.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7395 LUT to BLE ...
+SYN-4008 : Packed 7395 LUT and 3496 SEQ to BLE.
+SYN-4003 : Packing 6175 remaining SEQ's ...
+SYN-4005 : Packed 3711 SEQ with LUT/SLICE
+SYN-4006 : 488 single LUT's are left
+SYN-4006 : 2464 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9859/13606 primitive instances ...
+PHY-3001 : End packing;  1.640395s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6864 instances
+RUN-1001 : 3358 mslices, 3358 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17481 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9893 nets have 2 pins
+RUN-1001 : 5724 nets have [3 - 5] pins
+RUN-1001 : 1177 nets have [6 - 10] pins
+RUN-1001 : 309 nets have [11 - 20] pins
+RUN-1001 : 346 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6862 instances, 6716 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1967 with 3772 pins
+PHY-3001 : Found 1550 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 768896, Over = 243
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7374/17481.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 917544, over cnt = 1884(5%), over = 3140, worst = 8
+PHY-1002 : len = 926256, over cnt = 1121(3%), over = 1622, worst = 7
+PHY-1002 : len = 937344, over cnt = 476(1%), over = 673, worst = 7
+PHY-1002 : len = 944128, over cnt = 189(0%), over = 246, worst = 5
+PHY-1002 : len = 948632, over cnt = 4(0%), over = 5, worst = 2
+PHY-1001 : End global iterations;  1.712562s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (132.3%)
+
+PHY-1001 : Congestion index: top1 = 61.16, top5 = 52.51, top10 = 48.46, top15 = 45.68.
+PHY-3001 : End congestion estimation;  2.110306s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (126.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73666, tnet num: 17303, tinst num: 6862, tnode num: 96893, tedge num: 123953.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.638056s wall, 1.609375s user + 0.031250s system = 1.640625s CPU (100.2%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 613 MB, peak memory is 741 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17303 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.504329s wall, 2.437500s user + 0.062500s system = 2.500000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.18173e-05
+PHY-3002 : Step(282): len = 754666, overlap = 235.5
+PHY-3002 : Step(283): len = 746421, overlap = 237.75
+PHY-3002 : Step(284): len = 739951, overlap = 247
+PHY-3002 : Step(285): len = 734271, overlap = 252.75
+PHY-3002 : Step(286): len = 730107, overlap = 257
+PHY-3002 : Step(287): len = 726144, overlap = 260.75
+PHY-3002 : Step(288): len = 721792, overlap = 263.5
+PHY-3002 : Step(289): len = 717593, overlap = 266.75
+PHY-3002 : Step(290): len = 713479, overlap = 272.75
+PHY-3002 : Step(291): len = 709845, overlap = 268.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000103635
+PHY-3002 : Step(292): len = 713953, overlap = 264
+PHY-3002 : Step(293): len = 719545, overlap = 252
+PHY-3002 : Step(294): len = 719469, overlap = 251.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000207269
+PHY-3002 : Step(295): len = 727643, overlap = 236.5
+PHY-3002 : Step(296): len = 735818, overlap = 221.75
+PHY-3002 : Step(297): len = 734461, overlap = 214.5
+PHY-3002 : Step(298): len = 733250, overlap = 218
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.311142s wall, 0.218750s user + 0.312500s system = 0.531250s CPU (170.7%)
+
+PHY-3001 : Trial Legalized: Len = 904732
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 539/17481.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.02007e+06, over cnt = 2729(7%), over = 4669, worst = 8
+PHY-1002 : len = 1.03619e+06, over cnt = 1733(4%), over = 2635, worst = 8
+PHY-1002 : len = 1.05509e+06, over cnt = 832(2%), over = 1157, worst = 6
+PHY-1002 : len = 1.06468e+06, over cnt = 390(1%), over = 573, worst = 6
+PHY-1002 : len = 1.0743e+06, over cnt = 8(0%), over = 16, worst = 5
+PHY-1001 : End global iterations;  2.468672s wall, 3.484375s user + 0.015625s system = 3.500000s CPU (141.8%)
+
+PHY-1001 : Congestion index: top1 = 64.74, top5 = 57.34, top10 = 53.18, top15 = 50.57.
+PHY-3001 : End congestion estimation;  2.924867s wall, 3.937500s user + 0.015625s system = 3.953125s CPU (135.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17303 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.833434s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000149892
+PHY-3002 : Step(299): len = 867359, overlap = 69.5
+PHY-3002 : Step(300): len = 845423, overlap = 100.25
+PHY-3002 : Step(301): len = 830627, overlap = 123.5
+PHY-3002 : Step(302): len = 817429, overlap = 144
+PHY-3002 : Step(303): len = 806877, overlap = 163.75
+PHY-3002 : Step(304): len = 799053, overlap = 180.5
+PHY-3002 : Step(305): len = 792576, overlap = 194.25
+PHY-3002 : Step(306): len = 786542, overlap = 203.25
+PHY-3002 : Step(307): len = 783161, overlap = 204
+PHY-3002 : Step(308): len = 778380, overlap = 203.5
+PHY-3002 : Step(309): len = 775913, overlap = 206.25
+PHY-3002 : Step(310): len = 773324, overlap = 209
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000299784
+PHY-3002 : Step(311): len = 778295, overlap = 203.25
+PHY-3002 : Step(312): len = 780856, overlap = 203.25
+PHY-3002 : Step(313): len = 782513, overlap = 201.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000512529
+PHY-3002 : Step(314): len = 787598, overlap = 195.75
+PHY-3002 : Step(315): len = 790835, overlap = 189.75
+PHY-3002 : Step(316): len = 793087, overlap = 187.75
+PHY-3002 : Step(317): len = 794351, overlap = 189.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.083070s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (94.0%)
+
+PHY-3001 : Legalized: Len = 856983, Over = 0
+PHY-3001 : Spreading special nets. 495 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.117536s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (93.1%)
+
+PHY-3001 : 735 instances has been re-located, deltaX = 294, deltaY = 445, maxDist = 4.
+PHY-3001 : Final: Len = 869085, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73666, tnet num: 17303, tinst num: 6865, tnode num: 96893, tedge num: 123953.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.846002s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (99.9%)
+
+RUN-1004 : used memory is 634 MB, reserved memory is 647 MB, peak memory is 741 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3004/17481.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 994352, over cnt = 2572(7%), over = 4199, worst = 9
+PHY-1002 : len = 1.00658e+06, over cnt = 1684(4%), over = 2549, worst = 9
+PHY-1002 : len = 1.02612e+06, over cnt = 689(1%), over = 1043, worst = 6
+PHY-1002 : len = 1.03702e+06, over cnt = 198(0%), over = 267, worst = 5
+PHY-1002 : len = 1.04061e+06, over cnt = 14(0%), over = 18, worst = 3
+PHY-1001 : End global iterations;  1.956770s wall, 2.828125s user + 0.015625s system = 2.843750s CPU (145.3%)
+
+PHY-1001 : Congestion index: top1 = 62.59, top5 = 55.64, top10 = 51.75, top15 = 49.21.
+PHY-1001 : End incremental global routing;  2.321220s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (138.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17303 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.849705s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (101.1%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6772 has valid locations, 24 needs to be replaced
+PHY-3001 : design contains 6884 instances, 6735 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1967 with 3837 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 872552
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16000/17495.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04464e+06, over cnt = 90(0%), over = 111, worst = 4
+PHY-1002 : len = 1.04451e+06, over cnt = 72(0%), over = 81, worst = 4
+PHY-1002 : len = 1.0452e+06, over cnt = 29(0%), over = 33, worst = 3
+PHY-1002 : len = 1.04572e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.0458e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.762774s wall, 0.765625s user + 0.015625s system = 0.781250s CPU (102.4%)
+
+PHY-1001 : Congestion index: top1 = 62.59, top5 = 55.72, top10 = 51.81, top15 = 49.27.
+PHY-3001 : End congestion estimation;  1.071695s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (102.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73847, tnet num: 17317, tinst num: 6884, tnode num: 97115, tedge num: 124165.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.845702s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (99.9%)
+
+RUN-1004 : used memory is 665 MB, reserved memory is 656 MB, peak memory is 741 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17317 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.735065s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(318): len = 871561, overlap = 0
+PHY-3002 : Step(319): len = 871074, overlap = 0
+PHY-3002 : Step(320): len = 870826, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15991/17495.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04314e+06, over cnt = 57(0%), over = 75, worst = 4
+PHY-1002 : len = 1.04344e+06, over cnt = 22(0%), over = 24, worst = 2
+PHY-1002 : len = 1.04367e+06, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 1.04384e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.04389e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.782429s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (111.8%)
+
+PHY-1001 : Congestion index: top1 = 62.59, top5 = 55.65, top10 = 51.75, top15 = 49.22.
+PHY-3001 : End congestion estimation;  1.095404s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (107.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17317 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.878231s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (101.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000631675
+PHY-3002 : Step(321): len = 870803, overlap = 1.75
+PHY-3002 : Step(322): len = 870735, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005814s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (268.7%)
+
+PHY-3001 : Legalized: Len = 870897, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061156s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.2%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 1, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 870931, Over = 0
+PHY-3001 : End incremental placement;  6.270819s wall, 6.328125s user + 0.109375s system = 6.437500s CPU (102.7%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.919738s wall, 10.812500s user + 0.140625s system = 10.953125s CPU (110.4%)
+
+OPT-1001 : Current memory(MB): used = 745, reserve = 741, peak = 748.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15992/17495.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04385e+06, over cnt = 41(0%), over = 56, worst = 5
+PHY-1002 : len = 1.04394e+06, over cnt = 15(0%), over = 15, worst = 1
+PHY-1002 : len = 1.04407e+06, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 1.0441e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.04412e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.776369s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (104.7%)
+
+PHY-1001 : Congestion index: top1 = 62.61, top5 = 55.67, top10 = 51.76, top15 = 49.23.
+OPT-1001 : End congestion update;  1.114752s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (103.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17317 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.731581s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.4%)
+
+OPT-0007 : Start: WNS -1633 TNS -3106 NUM_FEPS 4
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6796 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6884 instances, 6735 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1967 with 3837 pins
+PHY-3001 : Found 1556 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 872757, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060679s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 2, deltaY = 12, maxDist = 3.
+PHY-3001 : Final: Len = 872899, Over = 0
+PHY-3001 : End incremental legalization;  0.378958s wall, 0.390625s user + 0.031250s system = 0.421875s CPU (111.3%)
+
+OPT-0007 : Iter 1: improved WNS -1583 TNS -2418 NUM_FEPS 2 with 27 cells processed and 7550 slack improved
+OPT-0007 : Iter 2: improved WNS -1583 TNS -2418 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.352914s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (106.3%)
+
+OPT-1001 : Current memory(MB): used = 744, reserve = 740, peak = 748.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17317 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.706128s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15927/17495.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.04634e+06, over cnt = 60(0%), over = 73, worst = 6
+PHY-1002 : len = 1.04632e+06, over cnt = 29(0%), over = 31, worst = 2
+PHY-1002 : len = 1.0464e+06, over cnt = 22(0%), over = 23, worst = 2
+PHY-1002 : len = 1.04654e+06, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 1.04665e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.780153s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (108.2%)
+
+PHY-1001 : Congestion index: top1 = 62.74, top5 = 55.68, top10 = 51.79, top15 = 49.26.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17317 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.760034s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.7%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1583 TNS -2418 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 62.241379
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1583ps with logic level 2 
+RUN-1001 :       #2 path slack -1547ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17495 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17495 nets
+OPT-1001 : End physical optimization;  17.043852s wall, 18.203125s user + 0.203125s system = 18.406250s CPU (108.0%)
+
+RUN-1003 : finish command "place" in  61.245843s wall, 95.890625s user + 6.343750s system = 102.234375s CPU (166.9%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 662 MB, peak memory is 748 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.699827s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (172.8%)
+
+RUN-1004 : used memory is 653 MB, reserved memory is 663 MB, peak memory is 748 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6886 instances
+RUN-1001 : 3370 mslices, 3365 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17495 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9884 nets have 2 pins
+RUN-1001 : 5716 nets have [3 - 5] pins
+RUN-1001 : 1194 nets have [6 - 10] pins
+RUN-1001 : 314 nets have [11 - 20] pins
+RUN-1001 : 357 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73847, tnet num: 17317, tinst num: 6884, tnode num: 97115, tedge num: 124165.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.616240s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.6%)
+
+RUN-1004 : used memory is 636 MB, reserved memory is 630 MB, peak memory is 748 MB
+PHY-1001 : 3370 mslices, 3365 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17317 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[47] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 978952, over cnt = 2733(7%), over = 4561, worst = 9
+PHY-1002 : len = 995832, over cnt = 1696(4%), over = 2523, worst = 8
+PHY-1002 : len = 1.01669e+06, over cnt = 674(1%), over = 948, worst = 8
+PHY-1002 : len = 1.0313e+06, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 1.03147e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.048876s wall, 4.015625s user + 0.015625s system = 4.031250s CPU (132.2%)
+
+PHY-1001 : Congestion index: top1 = 63.43, top5 = 55.45, top10 = 51.31, top15 = 48.80.
+PHY-1001 : End global routing;  3.375691s wall, 4.343750s user + 0.015625s system = 4.359375s CPU (129.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 715, peak = 748.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 992, reserve = 988, peak = 992.
+PHY-1001 : End build detailed router design. 3.955932s wall, 3.890625s user + 0.062500s system = 3.953125s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266832, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.391500s wall, 5.359375s user + 0.031250s system = 5.390625s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266888, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.422263s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1027, reserve = 1024, peak = 1027.
+PHY-1001 : End phase 1; 5.828371s wall, 5.796875s user + 0.031250s system = 5.828125s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.50001e+06, over cnt = 1695(0%), over = 1698, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1037, peak = 1042.
+PHY-1001 : End initial routed; 40.821714s wall, 71.359375s user + 0.343750s system = 71.703125s CPU (175.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16416(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.534   |  -4.650   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.222621s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1048, peak = 1052.
+PHY-1001 : End phase 2; 44.044400s wall, 74.578125s user + 0.343750s system = 74.921875s CPU (170.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.395ns STNS -4.408ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.143523s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.0%)
+
+PHY-1022 : len = 2.50003e+06, over cnt = 1699(0%), over = 1702, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.389660s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.47011e+06, over cnt = 664(0%), over = 664, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 2.003228s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (146.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.4672e+06, over cnt = 140(0%), over = 140, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.057020s wall, 1.375000s user + 0.015625s system = 1.390625s CPU (131.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.46855e+06, over cnt = 25(0%), over = 25, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.392100s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (107.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.46888e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.271338s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (97.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.46895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.219214s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.46895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.277558s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (95.7%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.46895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.462563s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.0%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.46898e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.169297s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.46895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.167656s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.5%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.46895e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.185468s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (92.7%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.46898e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 11; 0.167661s wall, 0.171875s user + 0.046875s system = 0.218750s CPU (130.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16416(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.395   |  -4.408   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.243421s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 554 feed throughs used by 427 nets
+PHY-1001 : End commit to database; 2.283747s wall, 2.250000s user + 0.031250s system = 2.281250s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1156, reserve = 1155, peak = 1156.
+PHY-1001 : End phase 3; 11.696202s wall, 12.937500s user + 0.093750s system = 13.031250s CPU (111.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.395ns STNS -4.408ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.143603s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.9%)
+
+PHY-1022 : len = 2.46898e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.375422s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (104.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.395ns, -4.408ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16416(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.395   |  -4.408   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.309945s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 554 feed throughs used by 427 nets
+PHY-1001 : End commit to database; 2.426713s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (98.5%)
+
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1164, peak = 1164.
+PHY-1001 : End phase 4; 6.139155s wall, 6.109375s user + 0.000000s system = 6.109375s CPU (99.5%)
+
+PHY-1003 : Routed, final wirelength = 2.46898e+06
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1166, peak = 1166.
+PHY-1001 : End export database. 0.083933s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (93.1%)
+
+PHY-1001 : End detail routing;  72.166635s wall, 103.812500s user + 0.531250s system = 104.343750s CPU (144.6%)
+
+RUN-1003 : finish command "route" in  78.226924s wall, 110.843750s user + 0.562500s system = 111.406250s CPU (142.4%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1092 MB, peak memory is 1166 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10128   out of  19600   51.67%
+#reg                     9808   out of  19600   50.04%
+#le                     12524
+  #lut only              2716   out of  12524   21.69%
+  #reg only              2396   out of  12524   19.13%
+  #lut&reg               7412   out of  12524   59.18%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                                                               Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                                                                 1828
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                                                            1494
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                                                           1389
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                                                                 965
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0                                      148
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                                                           71
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                                                            69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                                                                 25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                                                                 4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg4_syn_279_syn_2.f1    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_475.f1                                     2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                                                                1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                                                                1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                                                                1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                                                                 1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P141       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P110       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P82        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P69        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12524  |9101    |1027    |9838    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |535    |406     |23      |448     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |85      |4       |88      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |25     |25      |0       |18      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |6      |6       |0       |5       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |764    |378     |96      |577     |0       |0       |
+|    u_ADconfig                |AD_config            |195    |97      |25      |148     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |149     |71      |118     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |751    |402     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |172    |116     |25      |119     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |154     |71      |119     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3102   |2344    |306     |2295    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |180    |122     |17      |139     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |5       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |2893   |2203    |289     |2127    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |6      |6       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2517   |1979    |253     |1790    |22      |0       |
+|        channelPart           |channel_part_8478    |131    |120     |3       |118     |0       |0       |
+|        fifo_adc              |fifo_adc             |57     |48      |9       |42      |0       |0       |
+|        ram_switch            |ram_switch           |1947   |1494    |197     |1370    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |225    |193     |27      |125     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |6       |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |16      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |1001   |588     |170     |712     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |515    |513     |0       |342     |0       |0       |
+|        read_ram_i            |read_ram             |348    |294     |44      |226     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |213    |173     |40      |150     |0       |0       |
+|          read_ram_data       |read_ram_data        |133    |120     |4       |74      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |303    |168     |36      |273     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3271   |2501    |349     |2319    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |192    |110     |17      |150     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|    u_sort                    |sort_rev             |3045   |2360    |332     |2135    |25      |1       |
+|      u0_rdsoft_n             |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2614   |2008    |290     |1778    |22      |1       |
+|        channelPart           |channel_part_8478    |215    |201     |3       |139     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |1938   |1469    |197     |1356    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |208    |177     |27      |118     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |4       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |8       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |17     |14      |3       |8       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|          insert              |insert               |1010   |577     |170     |709     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |480    |475     |0       |327     |0       |0       |
+|        read_ram_i            |read_ram_rev         |370    |261     |81      |211     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |297    |216     |73      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |73     |45      |8       |51      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets  
+    #1          1       9822  
+    #2          2       3768  
+    #3          3       1424  
+    #4          4       521   
+    #5        5-10      1244  
+    #6        11-50     600   
+    #7       51-100      18   
+    #8       101-500     1    
+    #9        >500       1    
+  Average     2.91            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.095725s wall, 3.578125s user + 0.015625s system = 3.593750s CPU (171.5%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1093 MB, peak memory is 1166 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73847, tnet num: 17317, tinst num: 6884, tnode num: 97115, tedge num: 124165.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.623073s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.1%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1098 MB, peak memory is 1166 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17317 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.490226s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (99.6%)
+
+RUN-1004 : used memory is 1101 MB, reserved memory is 1099 MB, peak memory is 1166 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6884
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17495, pip num: 176244
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 554
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3240 valid insts, and 487655 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.454709s wall, 64.218750s user + 0.078125s system = 64.296875s CPU (680.1%)
+
+RUN-1004 : used memory is 1268 MB, reserved memory is 1265 MB, peak memory is 1384 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_110303.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_111230.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_111230.log
new file mode 100644
index 0000000..c88c509
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_111230.log
@@ -0,0 +1,1845 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:12:30 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.165557s wall, 2.109375s user + 0.046875s system = 2.156250s CPU (99.6%)
+
+RUN-1004 : used memory is 350 MB, reserved memory is 321 MB, peak memory is 354 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2977 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2624 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2463 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18413 instances
+RUN-0007 : 7294 luts, 9896 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20991 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 14036 nets have 2 pins
+RUN-1001 : 5471 nets have [3 - 5] pins
+RUN-1001 : 1074 nets have [6 - 10] pins
+RUN-1001 : 160 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 53 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     791     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4328     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     59     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 144
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18411 instances, 7294 luts, 9896 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 6717 pins
+PHY-0007 : Cell area utilization is 51%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87531, tnet num: 20813, tinst num: 18411, tnode num: 120170, tedge num: 140166.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.188065s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (100.0%)
+
+RUN-1004 : used memory is 550 MB, reserved memory is 528 MB, peak memory is 550 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.980021s wall, 1.890625s user + 0.093750s system = 1.984375s CPU (100.2%)
+
+PHY-3001 : Found 3478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.1698e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18411.
+PHY-3001 : Level 1 #clusters 2232.
+PHY-3001 : End clustering;  0.125973s wall, 0.109375s user + 0.015625s system = 0.125000s CPU (99.2%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.32357e+06, overlap = 509.188
+PHY-3002 : Step(2): len = 1.21588e+06, overlap = 511.125
+PHY-3002 : Step(3): len = 833070, overlap = 606.594
+PHY-3002 : Step(4): len = 783935, overlap = 657.469
+PHY-3002 : Step(5): len = 595311, overlap = 789.312
+PHY-3002 : Step(6): len = 539396, overlap = 865.406
+PHY-3002 : Step(7): len = 451681, overlap = 946.5
+PHY-3002 : Step(8): len = 413978, overlap = 997.906
+PHY-3002 : Step(9): len = 373110, overlap = 1045.16
+PHY-3002 : Step(10): len = 347283, overlap = 1086.56
+PHY-3002 : Step(11): len = 317911, overlap = 1144.72
+PHY-3002 : Step(12): len = 293339, overlap = 1182.84
+PHY-3002 : Step(13): len = 267988, overlap = 1215.59
+PHY-3002 : Step(14): len = 244321, overlap = 1263.16
+PHY-3002 : Step(15): len = 221298, overlap = 1321.91
+PHY-3002 : Step(16): len = 204071, overlap = 1364.62
+PHY-3002 : Step(17): len = 189601, overlap = 1401.28
+PHY-3002 : Step(18): len = 176546, overlap = 1432.69
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 6.31634e-07
+PHY-3002 : Step(19): len = 177170, overlap = 1410.81
+PHY-3002 : Step(20): len = 195764, overlap = 1379.34
+PHY-3002 : Step(21): len = 195501, overlap = 1319.34
+PHY-3002 : Step(22): len = 198190, overlap = 1322.5
+PHY-3002 : Step(23): len = 196871, overlap = 1303.38
+PHY-3002 : Step(24): len = 197190, overlap = 1292.31
+PHY-3002 : Step(25): len = 195395, overlap = 1271.59
+PHY-3002 : Step(26): len = 195563, overlap = 1230.38
+PHY-3002 : Step(27): len = 191185, overlap = 1256.88
+PHY-3002 : Step(28): len = 190933, overlap = 1264.78
+PHY-3002 : Step(29): len = 187566, overlap = 1264.16
+PHY-3002 : Step(30): len = 186664, overlap = 1273.06
+PHY-3002 : Step(31): len = 182962, overlap = 1299.78
+PHY-3002 : Step(32): len = 182319, overlap = 1307.41
+PHY-3002 : Step(33): len = 180192, overlap = 1308.31
+PHY-3002 : Step(34): len = 181155, overlap = 1313.16
+PHY-3002 : Step(35): len = 179360, overlap = 1310.06
+PHY-3002 : Step(36): len = 178331, overlap = 1315.62
+PHY-3002 : Step(37): len = 176758, overlap = 1306.34
+PHY-3002 : Step(38): len = 177506, overlap = 1281.12
+PHY-3002 : Step(39): len = 175455, overlap = 1259
+PHY-3002 : Step(40): len = 176781, overlap = 1230.72
+PHY-3002 : Step(41): len = 173721, overlap = 1224.5
+PHY-3002 : Step(42): len = 173064, overlap = 1226.28
+PHY-3002 : Step(43): len = 172052, overlap = 1232.81
+PHY-3002 : Step(44): len = 171737, overlap = 1245.66
+PHY-3002 : Step(45): len = 169652, overlap = 1267.94
+PHY-3002 : Step(46): len = 168755, overlap = 1277.56
+PHY-3002 : Step(47): len = 165728, overlap = 1292.66
+PHY-3002 : Step(48): len = 164843, overlap = 1293.53
+PHY-3002 : Step(49): len = 163772, overlap = 1307.09
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.26327e-06
+PHY-3002 : Step(50): len = 165822, overlap = 1297.09
+PHY-3002 : Step(51): len = 174370, overlap = 1232.03
+PHY-3002 : Step(52): len = 177850, overlap = 1213.5
+PHY-3002 : Step(53): len = 182756, overlap = 1212.41
+PHY-3002 : Step(54): len = 185089, overlap = 1198.22
+PHY-3002 : Step(55): len = 185796, overlap = 1193.94
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 2.52654e-06
+PHY-3002 : Step(56): len = 191403, overlap = 1167.47
+PHY-3002 : Step(57): len = 205112, overlap = 1123.53
+PHY-3002 : Step(58): len = 212313, overlap = 1067.03
+PHY-3002 : Step(59): len = 217087, overlap = 1037.88
+PHY-3002 : Step(60): len = 218338, overlap = 1028.53
+PHY-3002 : Step(61): len = 218723, overlap = 1037
+PHY-3002 : Step(62): len = 218199, overlap = 1036.88
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 5.05307e-06
+PHY-3002 : Step(63): len = 226946, overlap = 1005.16
+PHY-3002 : Step(64): len = 246061, overlap = 936.562
+PHY-3002 : Step(65): len = 258092, overlap = 842.812
+PHY-3002 : Step(66): len = 271818, overlap = 752.594
+PHY-3002 : Step(67): len = 276766, overlap = 728.031
+PHY-3002 : Step(68): len = 276089, overlap = 733.281
+PHY-3002 : Step(69): len = 275367, overlap = 741.219
+PHY-3002 : Step(70): len = 272456, overlap = 744.031
+PHY-3002 : Step(71): len = 269469, overlap = 756.156
+PHY-3002 : Step(72): len = 267393, overlap = 752.25
+PHY-3002 : Step(73): len = 266127, overlap = 738.5
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.01061e-05
+PHY-3002 : Step(74): len = 281881, overlap = 703.375
+PHY-3002 : Step(75): len = 299960, overlap = 602.594
+PHY-3002 : Step(76): len = 306657, overlap = 551.125
+PHY-3002 : Step(77): len = 311230, overlap = 536.438
+PHY-3002 : Step(78): len = 311499, overlap = 536.125
+PHY-3002 : Step(79): len = 309253, overlap = 541.438
+PHY-3002 : Step(80): len = 308153, overlap = 538.844
+PHY-3002 : Step(81): len = 308312, overlap = 534.156
+PHY-3002 : Step(82): len = 308508, overlap = 532.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 2.02123e-05
+PHY-3002 : Step(83): len = 325251, overlap = 495.938
+PHY-3002 : Step(84): len = 341444, overlap = 470.281
+PHY-3002 : Step(85): len = 344592, overlap = 453.688
+PHY-3002 : Step(86): len = 345969, overlap = 436.156
+PHY-3002 : Step(87): len = 347420, overlap = 439.75
+PHY-3002 : Step(88): len = 348839, overlap = 422.094
+PHY-3002 : Step(89): len = 350647, overlap = 394.625
+PHY-3002 : Step(90): len = 349283, overlap = 392.031
+PHY-3002 : Step(91): len = 348184, overlap = 392.531
+PHY-3002 : Step(92): len = 347015, overlap = 392.75
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 4.04246e-05
+PHY-3002 : Step(93): len = 362422, overlap = 358.375
+PHY-3002 : Step(94): len = 374685, overlap = 336.344
+PHY-3002 : Step(95): len = 375608, overlap = 305.844
+PHY-3002 : Step(96): len = 378127, overlap = 294.781
+PHY-3002 : Step(97): len = 382880, overlap = 291.406
+PHY-3002 : Step(98): len = 386156, overlap = 274.469
+PHY-3002 : Step(99): len = 382594, overlap = 297.281
+PHY-3002 : Step(100): len = 383026, overlap = 297.5
+PHY-3002 : Step(101): len = 383981, overlap = 281.812
+PHY-3002 : Step(102): len = 385422, overlap = 273.469
+PHY-3002 : Step(103): len = 382638, overlap = 286.75
+PHY-3002 : Step(104): len = 382802, overlap = 292.812
+PHY-3002 : Step(105): len = 383297, overlap = 287.312
+PHY-3002 : Step(106): len = 383442, overlap = 281.25
+PHY-3002 : Step(107): len = 381640, overlap = 283
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 7.88058e-05
+PHY-3002 : Step(108): len = 396543, overlap = 252.625
+PHY-3002 : Step(109): len = 406803, overlap = 229.156
+PHY-3002 : Step(110): len = 405263, overlap = 239.25
+PHY-3002 : Step(111): len = 406389, overlap = 243.188
+PHY-3002 : Step(112): len = 411152, overlap = 244.156
+PHY-3002 : Step(113): len = 415699, overlap = 245.094
+PHY-3002 : Step(114): len = 413379, overlap = 247
+PHY-3002 : Step(115): len = 413446, overlap = 247.344
+PHY-3002 : Step(116): len = 415624, overlap = 254.594
+PHY-3002 : Step(117): len = 417226, overlap = 251.344
+PHY-3002 : Step(118): len = 413050, overlap = 240.75
+PHY-3002 : Step(119): len = 412628, overlap = 229.594
+PHY-3002 : Step(120): len = 414687, overlap = 229.875
+PHY-3002 : Step(121): len = 416116, overlap = 227.938
+PHY-3002 : Step(122): len = 413193, overlap = 232.781
+PHY-3002 : Step(123): len = 412669, overlap = 226.438
+PHY-3002 : Step(124): len = 414075, overlap = 213.75
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000157612
+PHY-3002 : Step(125): len = 426291, overlap = 216.281
+PHY-3002 : Step(126): len = 433410, overlap = 220.406
+PHY-3002 : Step(127): len = 431392, overlap = 207.188
+PHY-3002 : Step(128): len = 432032, overlap = 195
+PHY-3002 : Step(129): len = 437719, overlap = 207.438
+PHY-3002 : Step(130): len = 442196, overlap = 208.625
+PHY-3002 : Step(131): len = 441558, overlap = 214.469
+PHY-3002 : Step(132): len = 443300, overlap = 211.688
+PHY-3002 : Step(133): len = 445261, overlap = 210.5
+PHY-3002 : Step(134): len = 445556, overlap = 191.906
+PHY-3002 : Step(135): len = 442781, overlap = 184.688
+PHY-3002 : Step(136): len = 442659, overlap = 186.531
+PHY-3002 : Step(137): len = 443877, overlap = 193.094
+PHY-3002 : Step(138): len = 445113, overlap = 192
+PHY-3002 : Step(139): len = 442756, overlap = 188.062
+PHY-3002 : Step(140): len = 442177, overlap = 174.594
+PHY-3002 : Step(141): len = 442694, overlap = 161.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000315223
+PHY-3002 : Step(142): len = 449724, overlap = 159.406
+PHY-3002 : Step(143): len = 455444, overlap = 153.781
+PHY-3002 : Step(144): len = 455569, overlap = 166.25
+PHY-3002 : Step(145): len = 457062, overlap = 167.312
+PHY-3002 : Step(146): len = 461496, overlap = 159.219
+PHY-3002 : Step(147): len = 465991, overlap = 170.5
+PHY-3002 : Step(148): len = 464319, overlap = 161.062
+PHY-3002 : Step(149): len = 464509, overlap = 167.906
+PHY-3002 : Step(150): len = 466601, overlap = 176.969
+PHY-3002 : Step(151): len = 468076, overlap = 178.844
+PHY-3002 : Step(152): len = 466318, overlap = 180.562
+PHY-3002 : Step(153): len = 466044, overlap = 187.531
+PHY-3002 : Step(154): len = 467614, overlap = 182.812
+PHY-3002 : Step(155): len = 468292, overlap = 178.188
+PHY-3002 : Step(156): len = 466618, overlap = 173.844
+PHY-3002 : Step(157): len = 466033, overlap = 180.094
+PHY-3002 : Step(158): len = 467139, overlap = 173.656
+PHY-3002 : Step(159): len = 468165, overlap = 171.281
+PHY-3002 : Step(160): len = 466956, overlap = 161.219
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00058585
+PHY-3002 : Step(161): len = 471157, overlap = 163.875
+PHY-3002 : Step(162): len = 475000, overlap = 167.125
+PHY-3002 : Step(163): len = 475338, overlap = 167
+PHY-3002 : Step(164): len = 476807, overlap = 170.344
+PHY-3002 : Step(165): len = 479427, overlap = 160.031
+PHY-3002 : Step(166): len = 482676, overlap = 161.875
+PHY-3002 : Step(167): len = 482589, overlap = 150.875
+PHY-3002 : Step(168): len = 483177, overlap = 149.219
+PHY-3002 : Step(169): len = 484547, overlap = 149.719
+PHY-3002 : Step(170): len = 485514, overlap = 157.719
+PHY-3002 : Step(171): len = 484760, overlap = 152.094
+PHY-3002 : Step(172): len = 484936, overlap = 157.156
+PHY-3002 : Step(173): len = 486414, overlap = 156.094
+PHY-3002 : Step(174): len = 487169, overlap = 156.656
+PHY-3002 : Step(175): len = 486248, overlap = 154.844
+PHY-3002 : Step(176): len = 486121, overlap = 153.781
+PHY-3002 : Step(177): len = 486897, overlap = 156.062
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00112814
+PHY-3002 : Step(178): len = 489809, overlap = 151.281
+PHY-3002 : Step(179): len = 495616, overlap = 145.344
+PHY-3002 : Step(180): len = 497043, overlap = 145.031
+PHY-3002 : Step(181): len = 498756, overlap = 142.219
+PHY-3002 : Step(182): len = 500561, overlap = 137.781
+PHY-3002 : Step(183): len = 502220, overlap = 139.125
+PHY-3002 : Step(184): len = 501555, overlap = 145.656
+PHY-3002 : Step(185): len = 501265, overlap = 140.094
+PHY-3002 : Step(186): len = 501634, overlap = 140.469
+PHY-3002 : Step(187): len = 501898, overlap = 142.969
+PHY-3002 : Step(188): len = 501397, overlap = 134.781
+PHY-3002 : Step(189): len = 501275, overlap = 134.906
+PHY-3002 : Step(190): len = 502079, overlap = 130.844
+PHY-3002 : Step(191): len = 502608, overlap = 137.719
+PHY-3002 : Step(192): len = 502187, overlap = 138.812
+PHY-3002 : Step(193): len = 501945, overlap = 136.844
+PHY-3002 : Step(194): len = 502733, overlap = 127.875
+PHY-3002 : Step(195): len = 503125, overlap = 126
+PHY-3002 : Step(196): len = 502540, overlap = 126.5
+PHY-3002 : Step(197): len = 502355, overlap = 134.844
+PHY-3002 : Step(198): len = 502863, overlap = 131.875
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00212523
+PHY-3002 : Step(199): len = 504808, overlap = 128.031
+PHY-3002 : Step(200): len = 508165, overlap = 125.719
+PHY-3002 : Step(201): len = 509273, overlap = 123.75
+PHY-3002 : Step(202): len = 510189, overlap = 123.125
+PHY-3002 : Step(203): len = 511007, overlap = 125.531
+PHY-3002 : Step(204): len = 511656, overlap = 127.156
+PHY-3002 : Step(205): len = 511796, overlap = 128.594
+PHY-3002 : Step(206): len = 512144, overlap = 127.312
+PHY-3002 : Step(207): len = 512741, overlap = 128.75
+PHY-3002 : Step(208): len = 513048, overlap = 128.75
+PHY-3002 : Step(209): len = 513521, overlap = 131.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015520s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (201.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 643280, over cnt = 1550(4%), over = 7030, worst = 47
+PHY-1001 : End global iterations;  0.775435s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (141.0%)
+
+PHY-1001 : Congestion index: top1 = 80.60, top5 = 60.52, top10 = 51.56, top15 = 46.07.
+PHY-3001 : End congestion estimation;  1.017950s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (130.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.859612s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000104719
+PHY-3002 : Step(210): len = 587545, overlap = 79.4062
+PHY-3002 : Step(211): len = 599614, overlap = 76.875
+PHY-3002 : Step(212): len = 597968, overlap = 68.8125
+PHY-3002 : Step(213): len = 597392, overlap = 63.6562
+PHY-3002 : Step(214): len = 594211, overlap = 56.375
+PHY-3002 : Step(215): len = 595259, overlap = 57.5938
+PHY-3002 : Step(216): len = 606540, overlap = 51.8438
+PHY-3002 : Step(217): len = 613514, overlap = 45.9375
+PHY-3002 : Step(218): len = 611867, overlap = 48.7188
+PHY-3002 : Step(219): len = 609174, overlap = 47.6875
+PHY-3002 : Step(220): len = 607974, overlap = 50.625
+PHY-3002 : Step(221): len = 610548, overlap = 54.9375
+PHY-3002 : Step(222): len = 608541, overlap = 58.8125
+PHY-3002 : Step(223): len = 605105, overlap = 62.9688
+PHY-3002 : Step(224): len = 604394, overlap = 62.6875
+PHY-3002 : Step(225): len = 603010, overlap = 65.3438
+PHY-3002 : Step(226): len = 601121, overlap = 68.875
+PHY-3002 : Step(227): len = 599213, overlap = 73
+PHY-3002 : Step(228): len = 598419, overlap = 77.1562
+PHY-3002 : Step(229): len = 597068, overlap = 79.7188
+PHY-3002 : Step(230): len = 596896, overlap = 78.3438
+PHY-3002 : Step(231): len = 596612, overlap = 77.5
+PHY-3002 : Step(232): len = 596023, overlap = 74.5312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000209437
+PHY-3002 : Step(233): len = 597629, overlap = 74.9375
+PHY-3002 : Step(234): len = 603200, overlap = 74.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00034382
+PHY-3002 : Step(235): len = 604692, overlap = 69.6562
+PHY-3002 : Step(236): len = 616902, overlap = 62.125
+PHY-3002 : Step(237): len = 629956, overlap = 58.6875
+PHY-3002 : Step(238): len = 628618, overlap = 55.625
+PHY-3002 : Step(239): len = 628324, overlap = 51.9375
+PHY-3002 : Step(240): len = 628820, overlap = 47.7188
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 122/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 702120, over cnt = 2766(7%), over = 12458, worst = 35
+PHY-1001 : End global iterations;  1.587675s wall, 2.031250s user + 0.046875s system = 2.078125s CPU (130.9%)
+
+PHY-1001 : Congestion index: top1 = 86.55, top5 = 68.09, top10 = 59.00, top15 = 53.55.
+PHY-3001 : End congestion estimation;  1.869772s wall, 2.328125s user + 0.046875s system = 2.375000s CPU (127.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.269084s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000110119
+PHY-3002 : Step(241): len = 624620, overlap = 293.406
+PHY-3002 : Step(242): len = 625664, overlap = 243.594
+PHY-3002 : Step(243): len = 623657, overlap = 201.5
+PHY-3002 : Step(244): len = 620345, overlap = 183.781
+PHY-3002 : Step(245): len = 616246, overlap = 171.625
+PHY-3002 : Step(246): len = 615603, overlap = 164.719
+PHY-3002 : Step(247): len = 612746, overlap = 156.312
+PHY-3002 : Step(248): len = 609999, overlap = 146.219
+PHY-3002 : Step(249): len = 607175, overlap = 143.562
+PHY-3002 : Step(250): len = 605440, overlap = 142.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000220239
+PHY-3002 : Step(251): len = 606576, overlap = 137.688
+PHY-3002 : Step(252): len = 610241, overlap = 133.812
+PHY-3002 : Step(253): len = 614517, overlap = 124.594
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000440477
+PHY-3002 : Step(254): len = 616526, overlap = 120.094
+PHY-3002 : Step(255): len = 621935, overlap = 114.906
+PHY-3002 : Step(256): len = 625202, overlap = 108.094
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87531, tnet num: 20813, tinst num: 18411, tnode num: 120170, tedge num: 140166.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.463328s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.4%)
+
+RUN-1004 : used memory is 592 MB, reserved memory is 575 MB, peak memory is 728 MB
+OPT-1001 : Total overflow 464.84 peak overflow 5.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1378/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 708808, over cnt = 3012(8%), over = 11414, worst = 33
+PHY-1001 : End global iterations;  1.086150s wall, 1.671875s user + 0.125000s system = 1.796875s CPU (165.4%)
+
+PHY-1001 : Congestion index: top1 = 74.66, top5 = 58.92, top10 = 52.53, top15 = 48.79.
+PHY-1001 : End incremental global routing;  1.404869s wall, 1.984375s user + 0.125000s system = 2.109375s CPU (150.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.466968s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.1%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18278 has valid locations, 309 needs to be replaced
+PHY-3001 : design contains 18672 instances, 7392 luts, 10059 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 6824 pins
+PHY-3001 : Found 3516 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 646543
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16986/21252.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 722912, over cnt = 3093(8%), over = 11437, worst = 33
+PHY-1001 : End global iterations;  0.211584s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (96.0%)
+
+PHY-1001 : Congestion index: top1 = 74.38, top5 = 58.91, top10 = 52.70, top15 = 49.04.
+PHY-3001 : End congestion estimation;  0.467119s wall, 0.437500s user + 0.031250s system = 0.468750s CPU (100.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88604, tnet num: 21074, tinst num: 18672, tnode num: 121763, tedge num: 141790.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.476209s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.5%)
+
+RUN-1004 : used memory is 635 MB, reserved memory is 624 MB, peak memory is 729 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21074 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.435391s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(257): len = 645601, overlap = 0.1875
+PHY-3002 : Step(258): len = 645188, overlap = 0.1875
+PHY-3002 : Step(259): len = 645181, overlap = 0.25
+PHY-3002 : Step(260): len = 645160, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17072/21252.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720824, over cnt = 3079(8%), over = 11516, worst = 33
+PHY-1001 : End global iterations;  0.193058s wall, 0.328125s user + 0.031250s system = 0.359375s CPU (186.1%)
+
+PHY-1001 : Congestion index: top1 = 75.19, top5 = 59.47, top10 = 53.05, top15 = 49.32.
+PHY-3001 : End congestion estimation;  0.528002s wall, 0.640625s user + 0.031250s system = 0.671875s CPU (127.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21074 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.546282s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000482435
+PHY-3002 : Step(261): len = 645100, overlap = 110.938
+PHY-3002 : Step(262): len = 645339, overlap = 111.094
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00096487
+PHY-3002 : Step(263): len = 645936, overlap = 110.938
+PHY-3002 : Step(264): len = 646707, overlap = 110.031
+PHY-3001 : Final: Len = 646707, Over = 110.031
+PHY-3001 : End incremental placement;  5.643457s wall, 5.765625s user + 0.250000s system = 6.015625s CPU (106.6%)
+
+OPT-1001 : Total overflow 469.78 peak overflow 5.78
+OPT-1001 : End high-fanout net optimization;  9.106417s wall, 9.828125s user + 0.421875s system = 10.250000s CPU (112.6%)
+
+OPT-1001 : Current memory(MB): used = 732, reserve = 720, peak = 750.
+OPT-1001 : Start global optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17029/21252.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725096, over cnt = 3039(8%), over = 10615, worst = 32
+PHY-1002 : len = 780960, over cnt = 2253(6%), over = 5720, worst = 21
+PHY-1002 : len = 821608, over cnt = 1205(3%), over = 2663, worst = 19
+PHY-1002 : len = 850944, over cnt = 452(1%), over = 862, worst = 17
+PHY-1002 : len = 867048, over cnt = 88(0%), over = 141, worst = 10
+PHY-1001 : End global iterations;  1.858884s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 58.28, top5 = 51.37, top10 = 48.00, top15 = 45.85.
+OPT-1001 : End congestion update;  2.114539s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (135.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21074 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.797276s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1118 TNS -1628 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1118 TNS -1628 NUM_FEPS 2 with 67 cells processed and 9600 slack improved
+OPT-0007 : Iter 2: improved WNS -1118 TNS -1628 NUM_FEPS 2 with 27 cells processed and 1434 slack improved
+OPT-0007 : Iter 3: improved WNS -1118 TNS -1628 NUM_FEPS 2 with 25 cells processed and 900 slack improved
+OPT-1001 : End global optimization;  2.957136s wall, 3.703125s user + 0.000000s system = 3.703125s CPU (125.2%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 750.
+OPT-1001 : End physical optimization;  14.164751s wall, 15.578125s user + 0.468750s system = 16.046875s CPU (113.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7392 LUT to BLE ...
+SYN-4008 : Packed 7392 LUT and 3496 SEQ to BLE.
+SYN-4003 : Packing 6563 remaining SEQ's ...
+SYN-4005 : Packed 3402 SEQ with LUT/SLICE
+SYN-4006 : 807 single LUT's are left
+SYN-4006 : 3161 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10553/14300 primitive instances ...
+PHY-3001 : End packing;  1.815311s wall, 1.812500s user + 0.015625s system = 1.828125s CPU (100.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7197 instances
+RUN-1001 : 3525 mslices, 3524 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17865 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10321 nets have 2 pins
+RUN-1001 : 5708 nets have [3 - 5] pins
+RUN-1001 : 1157 nets have [6 - 10] pins
+RUN-1001 : 295 nets have [11 - 20] pins
+RUN-1001 : 352 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7195 instances, 7049 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 3957 pins
+PHY-3001 : Found 1597 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : After packing: Len = 652206, Over = 316.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7480/17865.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 799376, over cnt = 1900(5%), over = 3224, worst = 8
+PHY-1002 : len = 807536, over cnt = 1206(3%), over = 1768, worst = 7
+PHY-1002 : len = 818328, over cnt = 667(1%), over = 893, worst = 6
+PHY-1002 : len = 824880, over cnt = 401(1%), over = 546, worst = 6
+PHY-1002 : len = 834408, over cnt = 56(0%), over = 91, worst = 6
+PHY-1001 : End global iterations;  1.537072s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (141.3%)
+
+PHY-1001 : Congestion index: top1 = 57.87, top5 = 50.39, top10 = 46.72, top15 = 44.37.
+PHY-3001 : End congestion estimation;  1.908469s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (132.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74722, tnet num: 17687, tinst num: 7195, tnode num: 98734, tedge num: 125479.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.651210s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.3%)
+
+RUN-1004 : used memory is 631 MB, reserved memory is 629 MB, peak memory is 750 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17687 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.667485s wall, 2.656250s user + 0.015625s system = 2.671875s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.06909e-05
+PHY-3002 : Step(265): len = 641206, overlap = 311.75
+PHY-3002 : Step(266): len = 635473, overlap = 317
+PHY-3002 : Step(267): len = 630864, overlap = 312
+PHY-3002 : Step(268): len = 627467, overlap = 315.75
+PHY-3002 : Step(269): len = 625253, overlap = 329.5
+PHY-3002 : Step(270): len = 622931, overlap = 330.5
+PHY-3002 : Step(271): len = 620224, overlap = 337.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.13819e-05
+PHY-3002 : Step(272): len = 622206, overlap = 331.25
+PHY-3002 : Step(273): len = 625121, overlap = 319
+PHY-3002 : Step(274): len = 625075, overlap = 315.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000162764
+PHY-3002 : Step(275): len = 634141, overlap = 295.5
+PHY-3002 : Step(276): len = 642395, overlap = 279.75
+PHY-3002 : Step(277): len = 640723, overlap = 276
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.338795s wall, 0.281250s user + 0.531250s system = 0.812500s CPU (239.8%)
+
+PHY-3001 : Trial Legalized: Len = 867750
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 767/17865.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 983240, over cnt = 2823(8%), over = 4632, worst = 8
+PHY-1002 : len = 999312, over cnt = 1811(5%), over = 2634, worst = 6
+PHY-1002 : len = 1.02138e+06, over cnt = 726(2%), over = 1020, worst = 6
+PHY-1002 : len = 1.03132e+06, over cnt = 287(0%), over = 391, worst = 6
+PHY-1002 : len = 1.03723e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.560835s wall, 3.703125s user + 0.015625s system = 3.718750s CPU (145.2%)
+
+PHY-1001 : Congestion index: top1 = 62.67, top5 = 55.94, top10 = 52.36, top15 = 50.00.
+PHY-3001 : End congestion estimation;  3.018007s wall, 4.156250s user + 0.015625s system = 4.171875s CPU (138.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17687 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.886240s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00016704
+PHY-3002 : Step(278): len = 826608, overlap = 86.75
+PHY-3002 : Step(279): len = 802368, overlap = 116.5
+PHY-3002 : Step(280): len = 785215, overlap = 144.75
+PHY-3002 : Step(281): len = 771307, overlap = 172.75
+PHY-3002 : Step(282): len = 758437, overlap = 199.5
+PHY-3002 : Step(283): len = 748087, overlap = 218.5
+PHY-3002 : Step(284): len = 740068, overlap = 227
+PHY-3002 : Step(285): len = 733689, overlap = 237
+PHY-3002 : Step(286): len = 727615, overlap = 242.5
+PHY-3002 : Step(287): len = 723769, overlap = 246.25
+PHY-3002 : Step(288): len = 719255, overlap = 254.25
+PHY-3002 : Step(289): len = 715666, overlap = 251.5
+PHY-3002 : Step(290): len = 711223, overlap = 251
+PHY-3002 : Step(291): len = 707475, overlap = 247.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000334081
+PHY-3002 : Step(292): len = 713020, overlap = 246.25
+PHY-3002 : Step(293): len = 716486, overlap = 240.25
+PHY-3002 : Step(294): len = 720248, overlap = 235.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000580277
+PHY-3002 : Step(295): len = 725954, overlap = 227
+PHY-3002 : Step(296): len = 733045, overlap = 216
+PHY-3002 : Step(297): len = 738767, overlap = 216.5
+PHY-3002 : Step(298): len = 741082, overlap = 217
+PHY-3002 : Step(299): len = 742631, overlap = 216.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.094945s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (98.7%)
+
+PHY-3001 : Legalized: Len = 818297, Over = 0
+PHY-3001 : Spreading special nets. 498 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.146595s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.9%)
+
+PHY-3001 : 792 instances has been re-located, deltaX = 379, deltaY = 580, maxDist = 21.
+PHY-3001 : Final: Len = 833890, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74722, tnet num: 17687, tinst num: 7198, tnode num: 98734, tedge num: 125479.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.963512s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (100.3%)
+
+RUN-1004 : used memory is 648 MB, reserved memory is 666 MB, peak memory is 750 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 2336/17865.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 956152, over cnt = 2693(7%), over = 4296, worst = 7
+PHY-1002 : len = 971248, over cnt = 1613(4%), over = 2292, worst = 6
+PHY-1002 : len = 987864, over cnt = 741(2%), over = 1048, worst = 6
+PHY-1002 : len = 999864, over cnt = 252(0%), over = 345, worst = 6
+PHY-1002 : len = 1.00605e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.076582s wall, 3.140625s user + 0.031250s system = 3.171875s CPU (152.7%)
+
+PHY-1001 : Congestion index: top1 = 59.59, top5 = 53.96, top10 = 50.74, top15 = 48.62.
+PHY-1001 : End incremental global routing;  2.448041s wall, 3.515625s user + 0.031250s system = 3.546875s CPU (144.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17687 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.920920s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (100.1%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7105 has valid locations, 24 needs to be replaced
+PHY-3001 : design contains 7217 instances, 7068 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4019 pins
+PHY-3001 : Found 1601 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 836928
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16371/17887.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00975e+06, over cnt = 61(0%), over = 68, worst = 3
+PHY-1002 : len = 1.0097e+06, over cnt = 28(0%), over = 31, worst = 3
+PHY-1002 : len = 1.00994e+06, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 1.00998e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.01002e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.815539s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (109.2%)
+
+PHY-1001 : Congestion index: top1 = 59.59, top5 = 54.03, top10 = 50.80, top15 = 48.67.
+PHY-3001 : End congestion estimation;  1.128007s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (106.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74898, tnet num: 17709, tinst num: 7217, tnode num: 98969, tedge num: 125711.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.885326s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.3%)
+
+RUN-1004 : used memory is 677 MB, reserved memory is 679 MB, peak memory is 750 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17709 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.780085s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(300): len = 835326, overlap = 0.25
+PHY-3002 : Step(301): len = 834996, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16360/17887.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.0068e+06, over cnt = 46(0%), over = 59, worst = 5
+PHY-1002 : len = 1.00692e+06, over cnt = 13(0%), over = 14, worst = 2
+PHY-1002 : len = 1.00704e+06, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 1.00707e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.649508s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (110.7%)
+
+PHY-1001 : Congestion index: top1 = 59.55, top5 = 53.93, top10 = 50.72, top15 = 48.59.
+PHY-3001 : End congestion estimation;  0.997118s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (106.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17709 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.861609s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165912
+PHY-3002 : Step(302): len = 835064, overlap = 1.5
+PHY-3002 : Step(303): len = 835111, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005971s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (261.7%)
+
+PHY-3001 : Legalized: Len = 835272, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062488s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.0%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 6, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 835436, Over = 0
+PHY-3001 : End incremental placement;  6.241257s wall, 6.437500s user + 0.062500s system = 6.500000s CPU (104.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.102384s wall, 11.468750s user + 0.093750s system = 11.562500s CPU (114.5%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 746, peak = 756.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16331/17887.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00754e+06, over cnt = 65(0%), over = 83, worst = 6
+PHY-1002 : len = 1.00758e+06, over cnt = 38(0%), over = 43, worst = 3
+PHY-1002 : len = 1.00785e+06, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 1.00802e+06, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 1.00809e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.792125s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 59.55, top5 = 53.96, top10 = 50.71, top15 = 48.58.
+OPT-1001 : End congestion update;  1.102101s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (99.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17709 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.716104s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+OPT-0007 : Start: WNS -1536 TNS -2600 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7129 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7217 instances, 7068 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4019 pins
+PHY-3001 : Found 1601 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Initial: Len = 836920, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061308s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.9%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 1, deltaY = 17, maxDist = 2.
+PHY-3001 : Final: Len = 837070, Over = 0
+PHY-3001 : End incremental legalization;  0.387600s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.8%)
+
+OPT-0007 : Iter 1: improved WNS -1436 TNS -2600 NUM_FEPS 3 with 19 cells processed and 5150 slack improved
+OPT-0007 : Iter 2: improved WNS -1436 TNS -2600 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.330942s wall, 2.312500s user + 0.015625s system = 2.328125s CPU (99.9%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 746, peak = 756.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17709 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.715737s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16286/17887.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 1.00952e+06, over cnt = 82(0%), over = 96, worst = 5
+PHY-1002 : len = 1.00951e+06, over cnt = 58(0%), over = 61, worst = 2
+PHY-1002 : len = 1.00985e+06, over cnt = 26(0%), over = 27, worst = 2
+PHY-1002 : len = 1.0104e+06, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.643174s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (102.0%)
+
+PHY-1001 : Congestion index: top1 = 59.35, top5 = 54.03, top10 = 50.74, top15 = 48.62.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17709 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.735684s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1436 TNS -2600 NUM_FEPS 3
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 58.931034
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1436ps with logic level 2 
+RUN-1001 :       #2 path slack -1390ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17887 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17887 nets
+OPT-1001 : End physical optimization;  17.189354s wall, 18.546875s user + 0.109375s system = 18.656250s CPU (108.5%)
+
+RUN-1003 : finish command "place" in  61.275672s wall, 90.718750s user + 6.250000s system = 96.968750s CPU (158.2%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 652 MB, peak memory is 756 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.710759s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (172.6%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 653 MB, peak memory is 756 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7219 instances
+RUN-1001 : 3538 mslices, 3530 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17887 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10323 nets have 2 pins
+RUN-1001 : 5710 nets have [3 - 5] pins
+RUN-1001 : 1161 nets have [6 - 10] pins
+RUN-1001 : 299 nets have [11 - 20] pins
+RUN-1001 : 364 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74898, tnet num: 17709, tinst num: 7217, tnode num: 98969, tedge num: 125711.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.633672s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.4%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 626 MB, peak memory is 756 MB
+PHY-1001 : 3538 mslices, 3530 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17709 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 942072, over cnt = 2850(8%), over = 4577, worst = 7
+PHY-1002 : len = 958712, over cnt = 1842(5%), over = 2651, worst = 7
+PHY-1002 : len = 985080, over cnt = 514(1%), over = 674, worst = 7
+PHY-1002 : len = 995784, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 995976, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.161828s wall, 4.109375s user + 0.015625s system = 4.125000s CPU (130.5%)
+
+PHY-1001 : Congestion index: top1 = 59.38, top5 = 53.44, top10 = 50.11, top15 = 48.04.
+PHY-1001 : End global routing;  3.494160s wall, 4.406250s user + 0.046875s system = 4.453125s CPU (127.4%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 720, reserve = 718, peak = 756.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 997, reserve = 995, peak = 997.
+PHY-1001 : End build detailed router design. 4.003356s wall, 3.953125s user + 0.046875s system = 4.000000s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 265568, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.897572s wall, 4.906250s user + 0.000000s system = 4.906250s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 265624, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.438564s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1031, reserve = 1030, peak = 1031.
+PHY-1001 : End phase 1; 5.349486s wall, 5.343750s user + 0.000000s system = 5.343750s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.44512e+06, over cnt = 2006(0%), over = 2014, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1051, reserve = 1048, peak = 1051.
+PHY-1001 : End initial routed; 25.729412s wall, 55.359375s user + 0.390625s system = 55.750000s CPU (216.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16809(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.316   |  -5.008   |   4   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.335760s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1061, reserve = 1059, peak = 1061.
+PHY-1001 : End phase 2; 29.065245s wall, 58.703125s user + 0.390625s system = 59.093750s CPU (203.3%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.311ns STNS -4.788ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.152511s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (92.2%)
+
+PHY-1022 : len = 2.44514e+06, over cnt = 2012(0%), over = 2020, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.847048s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (49.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.4078e+06, over cnt = 772(0%), over = 773, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.595534s wall, 3.843750s user + 0.000000s system = 3.843750s CPU (148.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.40573e+06, over cnt = 234(0%), over = 234, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.909324s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (134.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.40667e+06, over cnt = 58(0%), over = 58, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.577448s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (113.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.40737e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.299475s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (114.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.40766e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.222191s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16809(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.311   |  -4.778   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.308320s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 656 feed throughs used by 479 nets
+PHY-1001 : End commit to database; 2.292684s wall, 2.250000s user + 0.031250s system = 2.281250s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1168, peak = 1166.
+PHY-1001 : End phase 3; 11.595910s wall, 12.703125s user + 0.031250s system = 12.734375s CPU (109.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.311ns STNS -4.778ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.155325s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (100.6%)
+
+PHY-1022 : len = 2.40766e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.406861s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.311ns, -4.778ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16809(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.311   |  -4.778   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.423679s wall, 3.421875s user + 0.000000s system = 3.421875s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 656 feed throughs used by 479 nets
+PHY-1001 : End commit to database; 2.435965s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1176, reserve = 1178, peak = 1176.
+PHY-1001 : End phase 4; 6.296371s wall, 6.296875s user + 0.000000s system = 6.296875s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.40766e+06
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1180, peak = 1178.
+PHY-1001 : End export database. 0.063308s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.7%)
+
+PHY-1001 : End detail routing;  56.772998s wall, 87.453125s user + 0.484375s system = 87.937500s CPU (154.9%)
+
+RUN-1003 : finish command "route" in  62.968093s wall, 94.562500s user + 0.531250s system = 95.093750s CPU (151.0%)
+
+RUN-1004 : used memory is 1105 MB, reserved memory is 1103 MB, peak memory is 1178 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10106   out of  19600   51.56%
+#reg                    10202   out of  19600   52.05%
+#le                     13177
+  #lut only              2975   out of  13177   22.58%
+  #reg only              3071   out of  13177   23.31%
+  #lut&reg               7131   out of  13177   54.12%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1771
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1587
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1545
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               967
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    138
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_a/u_ADconfig/reg0_syn_174.f0             3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_b/reg2_syn_215.f0                        3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P165       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P70        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |13177  |9079    |1027    |10232   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |540    |385     |23      |456     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |104    |87      |4       |93      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |28     |28      |0       |20      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |760    |385     |96      |559     |0       |0       |
+|    u_ADconfig                |AD_config            |194    |143     |25      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |259    |158     |71      |114     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |748    |458     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |172    |135     |25      |126     |0       |0       |
+|    u_gen_sp                  |gen_sp               |271    |150     |71      |123     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3306   |2420    |306     |2501    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |176    |99      |17      |142     |0       |0       |
+|      u0_soft_n               |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|    u_sort                    |sort                 |3094   |2319    |289     |2323    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |6      |1       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2717   |2083    |253     |1983    |22      |0       |
+|        channelPart           |channel_part_8478    |110    |99      |3       |99      |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |43      |0       |0       |
+|        ram_switch            |ram_switch           |2158   |1620    |197     |1577    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |210    |179     |27      |127     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |16     |9       |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17     |14      |3       |9       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|          insert              |insert               |1008   |613     |170     |721     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |550    |550     |0       |339     |0       |0       |
+|        read_ram_i            |read_ram             |356    |297     |44      |229     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |214    |174     |40      |151     |0       |0       |
+|          read_ram_data       |read_ram_data        |141    |122     |4       |77      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |303    |190     |36      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3733   |2857    |349     |2441    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |6      |2       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |178    |113     |17      |138     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |3526   |2729    |332     |2274    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |1       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |3030   |2366    |290     |1910    |22      |1       |
+|        channelPart           |channel_part_8478    |223    |210     |3       |139     |0       |0       |
+|        fifo_adc              |fifo_adc             |61     |52      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |2365   |1828    |197     |1495    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |225    |198     |27      |113     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |8       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |18      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|          insert              |insert               |972    |508     |170     |686     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |773    |773     |0       |336     |0       |0       |
+|        read_ram_i            |read_ram_rev         |352    |249     |81      |205     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |290    |206     |73      |159     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |62     |43      |8       |46      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout     Nets   
+    #1          1       10261  
+    #2          2       3779   
+    #3          3       1411   
+    #4          4        517   
+    #5        5-10      1216   
+    #6        11-50      586   
+    #7       51-100      19    
+    #8       101-500      1    
+    #9        >500        1    
+  Average     2.88             
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.126800s wall, 3.671875s user + 0.000000s system = 3.671875s CPU (172.6%)
+
+RUN-1004 : used memory is 1107 MB, reserved memory is 1105 MB, peak memory is 1178 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74898, tnet num: 17709, tinst num: 7217, tnode num: 98969, tedge num: 125711.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.632997s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.5%)
+
+RUN-1004 : used memory is 1113 MB, reserved memory is 1111 MB, peak memory is 1178 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17709 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.534638s wall, 1.531250s user + 0.000000s system = 1.531250s CPU (99.8%)
+
+RUN-1004 : used memory is 1116 MB, reserved memory is 1114 MB, peak memory is 1178 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7217
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17887, pip num: 177453
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 656
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3229 valid insts, and 490950 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.109443s wall, 68.859375s user + 0.140625s system = 69.000000s CPU (682.5%)
+
+RUN-1004 : used memory is 1286 MB, reserved memory is 1283 MB, peak memory is 1402 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_111230.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_111825.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_111825.log
new file mode 100644
index 0000000..192af23
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_111825.log
@@ -0,0 +1,2150 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:18:25 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.305992s wall, 2.234375s user + 0.031250s system = 2.265625s CPU (98.2%)
+
+RUN-1004 : used memory is 352 MB, reserved memory is 321 MB, peak memory is 356 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing ultra"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   ultra    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2977 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2624 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2463 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18413 instances
+RUN-0007 : 7294 luts, 9896 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20991 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 14036 nets have 2 pins
+RUN-1001 : 5471 nets have [3 - 5] pins
+RUN-1001 : 1074 nets have [6 - 10] pins
+RUN-1001 : 160 nets have [11 - 20] pins
+RUN-1001 : 176 nets have [21 - 99] pins
+RUN-1001 : 53 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     791     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    4328     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     59     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 144
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18411 instances, 7294 luts, 9896 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 6717 pins
+PHY-0007 : Cell area utilization is 51%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87531, tnet num: 20813, tinst num: 18411, tnode num: 120170, tedge num: 140166.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.233986s wall, 1.187500s user + 0.046875s system = 1.234375s CPU (100.0%)
+
+RUN-1004 : used memory is 551 MB, reserved memory is 527 MB, peak memory is 551 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.111104s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (99.9%)
+
+PHY-3001 : Found 3478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.1698e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18411.
+PHY-3001 : Level 1 #clusters 2246.
+PHY-3001 : End clustering;  0.138206s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (158.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 51%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.30045e+06, overlap = 516
+PHY-3002 : Step(2): len = 1.18736e+06, overlap = 516.375
+PHY-3002 : Step(3): len = 806039, overlap = 622.781
+PHY-3002 : Step(4): len = 753838, overlap = 671.125
+PHY-3002 : Step(5): len = 563549, overlap = 817.562
+PHY-3002 : Step(6): len = 506708, overlap = 852
+PHY-3002 : Step(7): len = 427034, overlap = 961.375
+PHY-3002 : Step(8): len = 395856, overlap = 1019.5
+PHY-3002 : Step(9): len = 347062, overlap = 1085.16
+PHY-3002 : Step(10): len = 323714, overlap = 1108.75
+PHY-3002 : Step(11): len = 291406, overlap = 1178.25
+PHY-3002 : Step(12): len = 268389, overlap = 1210.25
+PHY-3002 : Step(13): len = 244812, overlap = 1248.09
+PHY-3002 : Step(14): len = 222506, overlap = 1307.62
+PHY-3002 : Step(15): len = 203894, overlap = 1336.62
+PHY-3002 : Step(16): len = 188721, overlap = 1372.56
+PHY-3002 : Step(17): len = 178860, overlap = 1408.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.0714e-06
+PHY-3002 : Step(18): len = 179885, overlap = 1377.31
+PHY-3002 : Step(19): len = 202576, overlap = 1330.84
+PHY-3002 : Step(20): len = 203111, overlap = 1298.44
+PHY-3002 : Step(21): len = 205707, overlap = 1302.94
+PHY-3002 : Step(22): len = 204630, overlap = 1258.38
+PHY-3002 : Step(23): len = 203860, overlap = 1240.94
+PHY-3002 : Step(24): len = 203582, overlap = 1214.56
+PHY-3002 : Step(25): len = 203751, overlap = 1218.56
+PHY-3002 : Step(26): len = 201669, overlap = 1232.88
+PHY-3002 : Step(27): len = 201941, overlap = 1246.75
+PHY-3002 : Step(28): len = 199807, overlap = 1257.69
+PHY-3002 : Step(29): len = 199087, overlap = 1270.94
+PHY-3002 : Step(30): len = 197381, overlap = 1284.03
+PHY-3002 : Step(31): len = 195982, overlap = 1274.88
+PHY-3002 : Step(32): len = 194719, overlap = 1264.75
+PHY-3002 : Step(33): len = 193846, overlap = 1267.75
+PHY-3002 : Step(34): len = 193360, overlap = 1262.72
+PHY-3002 : Step(35): len = 192873, overlap = 1258.56
+PHY-3002 : Step(36): len = 193331, overlap = 1242.41
+PHY-3002 : Step(37): len = 191350, overlap = 1255.06
+PHY-3002 : Step(38): len = 190728, overlap = 1262.22
+PHY-3002 : Step(39): len = 189835, overlap = 1247.34
+PHY-3002 : Step(40): len = 189299, overlap = 1257.06
+PHY-3002 : Step(41): len = 188642, overlap = 1247.44
+PHY-3002 : Step(42): len = 188657, overlap = 1242.22
+PHY-3002 : Step(43): len = 187071, overlap = 1264.78
+PHY-3002 : Step(44): len = 186607, overlap = 1248.97
+PHY-3002 : Step(45): len = 185547, overlap = 1222.41
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.1428e-06
+PHY-3002 : Step(46): len = 187990, overlap = 1201.97
+PHY-3002 : Step(47): len = 199189, overlap = 1146.16
+PHY-3002 : Step(48): len = 204113, overlap = 1163.78
+PHY-3002 : Step(49): len = 209953, overlap = 1164.97
+PHY-3002 : Step(50): len = 212805, overlap = 1126.5
+PHY-3002 : Step(51): len = 215944, overlap = 1110.81
+PHY-3002 : Step(52): len = 216492, overlap = 1111.72
+PHY-3002 : Step(53): len = 216526, overlap = 1116.91
+PHY-3002 : Step(54): len = 214697, overlap = 1112.12
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.28561e-06
+PHY-3002 : Step(55): len = 221342, overlap = 1109.97
+PHY-3002 : Step(56): len = 236439, overlap = 1004.31
+PHY-3002 : Step(57): len = 244871, overlap = 922.688
+PHY-3002 : Step(58): len = 255141, overlap = 872.531
+PHY-3002 : Step(59): len = 260569, overlap = 836.25
+PHY-3002 : Step(60): len = 261014, overlap = 829.75
+PHY-3002 : Step(61): len = 260775, overlap = 819.938
+PHY-3002 : Step(62): len = 259385, overlap = 806.469
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.57121e-06
+PHY-3002 : Step(63): len = 273080, overlap = 769.031
+PHY-3002 : Step(64): len = 294630, overlap = 669.094
+PHY-3002 : Step(65): len = 301445, overlap = 625.375
+PHY-3002 : Step(66): len = 305330, overlap = 603.375
+PHY-3002 : Step(67): len = 304573, overlap = 601.406
+PHY-3002 : Step(68): len = 304005, overlap = 594.406
+PHY-3002 : Step(69): len = 301496, overlap = 581.938
+PHY-3002 : Step(70): len = 300473, overlap = 574.25
+PHY-3002 : Step(71): len = 298843, overlap = 588.094
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.71424e-05
+PHY-3002 : Step(72): len = 317152, overlap = 571.562
+PHY-3002 : Step(73): len = 338717, overlap = 522.906
+PHY-3002 : Step(74): len = 343109, overlap = 502.156
+PHY-3002 : Step(75): len = 342881, overlap = 452.375
+PHY-3002 : Step(76): len = 343082, overlap = 440.531
+PHY-3002 : Step(77): len = 344211, overlap = 437.781
+PHY-3002 : Step(78): len = 344690, overlap = 427.812
+PHY-3002 : Step(79): len = 343514, overlap = 427.531
+PHY-3002 : Step(80): len = 341833, overlap = 409.281
+PHY-3002 : Step(81): len = 340518, overlap = 409.594
+PHY-3002 : Step(82): len = 340408, overlap = 392.75
+PHY-3002 : Step(83): len = 339214, overlap = 403.031
+PHY-3002 : Step(84): len = 338826, overlap = 389.5
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.42848e-05
+PHY-3002 : Step(85): len = 353362, overlap = 365.281
+PHY-3002 : Step(86): len = 365567, overlap = 358.75
+PHY-3002 : Step(87): len = 366846, overlap = 333.031
+PHY-3002 : Step(88): len = 369183, overlap = 317.156
+PHY-3002 : Step(89): len = 372023, overlap = 293.781
+PHY-3002 : Step(90): len = 375183, overlap = 314.5
+PHY-3002 : Step(91): len = 374513, overlap = 328.875
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.85697e-05
+PHY-3002 : Step(92): len = 388739, overlap = 313.438
+PHY-3002 : Step(93): len = 401737, overlap = 302
+PHY-3002 : Step(94): len = 401593, overlap = 287.188
+PHY-3002 : Step(95): len = 403908, overlap = 277.812
+PHY-3002 : Step(96): len = 407869, overlap = 266.531
+PHY-3002 : Step(97): len = 410013, overlap = 259.25
+PHY-3002 : Step(98): len = 406138, overlap = 259.281
+PHY-3002 : Step(99): len = 406359, overlap = 262.875
+PHY-3002 : Step(100): len = 408785, overlap = 256.5
+PHY-3002 : Step(101): len = 410252, overlap = 241.5
+PHY-3002 : Step(102): len = 407242, overlap = 243.406
+PHY-3002 : Step(103): len = 406985, overlap = 246.219
+PHY-3002 : Step(104): len = 407728, overlap = 264.062
+PHY-3002 : Step(105): len = 408691, overlap = 263.75
+PHY-3002 : Step(106): len = 406514, overlap = 247.969
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000136083
+PHY-3002 : Step(107): len = 418412, overlap = 233.219
+PHY-3002 : Step(108): len = 425865, overlap = 214.844
+PHY-3002 : Step(109): len = 423928, overlap = 216.875
+PHY-3002 : Step(110): len = 426196, overlap = 216.531
+PHY-3002 : Step(111): len = 431102, overlap = 206.562
+PHY-3002 : Step(112): len = 435202, overlap = 194.062
+PHY-3002 : Step(113): len = 432013, overlap = 189.344
+PHY-3002 : Step(114): len = 431946, overlap = 191.219
+PHY-3002 : Step(115): len = 436041, overlap = 181.969
+PHY-3002 : Step(116): len = 439706, overlap = 172.969
+PHY-3002 : Step(117): len = 436815, overlap = 158.438
+PHY-3002 : Step(118): len = 436618, overlap = 177.969
+PHY-3002 : Step(119): len = 439261, overlap = 167.969
+PHY-3002 : Step(120): len = 440833, overlap = 164.188
+PHY-3002 : Step(121): len = 437565, overlap = 171.656
+PHY-3002 : Step(122): len = 437038, overlap = 171.25
+PHY-3002 : Step(123): len = 438032, overlap = 176
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000272167
+PHY-3002 : Step(124): len = 446313, overlap = 161.469
+PHY-3002 : Step(125): len = 452844, overlap = 151.781
+PHY-3002 : Step(126): len = 453032, overlap = 155
+PHY-3002 : Step(127): len = 454717, overlap = 146.656
+PHY-3002 : Step(128): len = 457484, overlap = 137.562
+PHY-3002 : Step(129): len = 459882, overlap = 143.938
+PHY-3002 : Step(130): len = 458675, overlap = 143.406
+PHY-3002 : Step(131): len = 459006, overlap = 143.719
+PHY-3002 : Step(132): len = 460684, overlap = 140.688
+PHY-3002 : Step(133): len = 461703, overlap = 141.062
+PHY-3002 : Step(134): len = 459758, overlap = 140.156
+PHY-3002 : Step(135): len = 459819, overlap = 135.719
+PHY-3002 : Step(136): len = 461846, overlap = 132.844
+PHY-3002 : Step(137): len = 463010, overlap = 138.156
+PHY-3002 : Step(138): len = 460939, overlap = 136.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000486918
+PHY-3002 : Step(139): len = 466840, overlap = 138.125
+PHY-3002 : Step(140): len = 469988, overlap = 138.375
+PHY-3002 : Step(141): len = 469064, overlap = 141.531
+PHY-3002 : Step(142): len = 469866, overlap = 139.75
+PHY-3002 : Step(143): len = 473062, overlap = 136.219
+PHY-3002 : Step(144): len = 475830, overlap = 128.219
+PHY-3002 : Step(145): len = 474727, overlap = 119.469
+PHY-3002 : Step(146): len = 475565, overlap = 120.219
+PHY-3002 : Step(147): len = 478014, overlap = 126.156
+PHY-3002 : Step(148): len = 479768, overlap = 125.812
+PHY-3002 : Step(149): len = 478414, overlap = 119.25
+PHY-3002 : Step(150): len = 478266, overlap = 119.406
+PHY-3002 : Step(151): len = 479342, overlap = 121.75
+PHY-3002 : Step(152): len = 480167, overlap = 120.719
+PHY-3002 : Step(153): len = 479180, overlap = 115
+PHY-3002 : Step(154): len = 479470, overlap = 110.312
+PHY-3002 : Step(155): len = 480685, overlap = 118.062
+PHY-3002 : Step(156): len = 481320, overlap = 119
+PHY-3002 : Step(157): len = 480059, overlap = 120.188
+PHY-3002 : Step(158): len = 479845, overlap = 119.125
+PHY-3002 : Step(159): len = 480982, overlap = 119.469
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000973836
+PHY-3002 : Step(160): len = 484588, overlap = 119.812
+PHY-3002 : Step(161): len = 489417, overlap = 117.094
+PHY-3002 : Step(162): len = 490842, overlap = 115
+PHY-3002 : Step(163): len = 492698, overlap = 110.969
+PHY-3002 : Step(164): len = 493697, overlap = 115.906
+PHY-3002 : Step(165): len = 494865, overlap = 111.5
+PHY-3002 : Step(166): len = 495428, overlap = 106.062
+PHY-3002 : Step(167): len = 496152, overlap = 109.281
+PHY-3002 : Step(168): len = 497113, overlap = 112.438
+PHY-3002 : Step(169): len = 497560, overlap = 109.719
+PHY-3002 : Step(170): len = 497537, overlap = 106.375
+PHY-3002 : Step(171): len = 497807, overlap = 105.594
+PHY-3002 : Step(172): len = 498272, overlap = 105.406
+PHY-3002 : Step(173): len = 498646, overlap = 103.938
+PHY-3002 : Step(174): len = 498563, overlap = 105.531
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00157567
+PHY-3002 : Step(175): len = 500451, overlap = 103.438
+PHY-3002 : Step(176): len = 502589, overlap = 104.844
+PHY-3002 : Step(177): len = 503314, overlap = 103.156
+PHY-3002 : Step(178): len = 504166, overlap = 103.406
+PHY-3002 : Step(179): len = 505432, overlap = 106.094
+PHY-3002 : Step(180): len = 506746, overlap = 106.031
+PHY-3002 : Step(181): len = 506845, overlap = 103.906
+PHY-3002 : Step(182): len = 507193, overlap = 101.125
+PHY-3002 : Step(183): len = 507856, overlap = 103.531
+PHY-3002 : Step(184): len = 508437, overlap = 98.0625
+PHY-3002 : Step(185): len = 508324, overlap = 97.125
+PHY-3002 : Step(186): len = 508415, overlap = 100.281
+PHY-3002 : Step(187): len = 508919, overlap = 98.7812
+PHY-3002 : Step(188): len = 509023, overlap = 97.5312
+PHY-3002 : Step(189): len = 508843, overlap = 96.8125
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.0027467
+PHY-3002 : Step(190): len = 510597, overlap = 93.4375
+PHY-3002 : Step(191): len = 513672, overlap = 92.4375
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014966s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (104.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 665688, over cnt = 1643(4%), over = 7165, worst = 35
+PHY-1001 : End global iterations;  0.883041s wall, 1.296875s user + 0.031250s system = 1.328125s CPU (150.4%)
+
+PHY-1001 : Congestion index: top1 = 72.48, top5 = 57.27, top10 = 49.69, top15 = 44.77.
+PHY-3001 : End congestion estimation;  1.131860s wall, 1.546875s user + 0.031250s system = 1.578125s CPU (139.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.916670s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000123807
+PHY-3002 : Step(192): len = 601731, overlap = 47.6562
+PHY-3002 : Step(193): len = 598207, overlap = 44.7188
+PHY-3002 : Step(194): len = 598149, overlap = 49.5625
+PHY-3002 : Step(195): len = 603198, overlap = 48.5625
+PHY-3002 : Step(196): len = 606139, overlap = 52.7812
+PHY-3002 : Step(197): len = 611326, overlap = 54.1875
+PHY-3002 : Step(198): len = 622720, overlap = 50.0938
+PHY-3002 : Step(199): len = 629481, overlap = 48.2812
+PHY-3002 : Step(200): len = 625945, overlap = 48.3125
+PHY-3002 : Step(201): len = 623497, overlap = 47.5625
+PHY-3002 : Step(202): len = 621468, overlap = 47.625
+PHY-3002 : Step(203): len = 620306, overlap = 50.9688
+PHY-3002 : Step(204): len = 618092, overlap = 54.1562
+PHY-3002 : Step(205): len = 615368, overlap = 56.625
+PHY-3002 : Step(206): len = 613556, overlap = 59.2188
+PHY-3002 : Step(207): len = 613393, overlap = 55.0625
+PHY-3002 : Step(208): len = 612897, overlap = 56.3438
+PHY-3002 : Step(209): len = 610685, overlap = 55.6875
+PHY-3002 : Step(210): len = 608189, overlap = 57.9375
+PHY-3002 : Step(211): len = 606498, overlap = 57.7188
+PHY-3002 : Step(212): len = 605194, overlap = 57.3438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000247614
+PHY-3002 : Step(213): len = 606242, overlap = 56.0625
+PHY-3002 : Step(214): len = 611821, overlap = 57.125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000406603
+PHY-3002 : Step(215): len = 612844, overlap = 56.2188
+PHY-3002 : Step(216): len = 629257, overlap = 55.4062
+PHY-3002 : Step(217): len = 641481, overlap = 56.8125
+PHY-3002 : Step(218): len = 638888, overlap = 56.7812
+PHY-3002 : Step(219): len = 637182, overlap = 56.5625
+PHY-3002 : Step(220): len = 634942, overlap = 57.5938
+PHY-3002 : Step(221): len = 633679, overlap = 57.25
+PHY-3002 : Step(222): len = 635362, overlap = 56.0312
+PHY-3002 : Step(223): len = 640294, overlap = 55.125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000813207
+PHY-3002 : Step(224): len = 644927, overlap = 55.8438
+PHY-3002 : Step(225): len = 654248, overlap = 53.625
+PHY-3002 : Step(226): len = 664780, overlap = 50.0625
+PHY-3002 : Step(227): len = 669728, overlap = 53.0625
+PHY-3002 : Step(228): len = 672519, overlap = 54.7812
+PHY-3002 : Step(229): len = 672450, overlap = 59.4062
+PHY-3002 : Step(230): len = 673585, overlap = 60.625
+PHY-3002 : Step(231): len = 674153, overlap = 59.875
+PHY-3002 : Step(232): len = 673856, overlap = 60.875
+PHY-3002 : Step(233): len = 673968, overlap = 54.9688
+PHY-3002 : Step(234): len = 675432, overlap = 52.3125
+PHY-3002 : Step(235): len = 682390, overlap = 50.5625
+PHY-3002 : Step(236): len = 682097, overlap = 51.0625
+PHY-3002 : Step(237): len = 680383, overlap = 49.3438
+PHY-3002 : Step(238): len = 678072, overlap = 44.2812
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00140461
+PHY-3002 : Step(239): len = 679764, overlap = 45.6562
+PHY-3002 : Step(240): len = 685086, overlap = 44.5938
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 58%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 76/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 758824, over cnt = 2679(7%), over = 13765, worst = 72
+PHY-1001 : End global iterations;  1.496553s wall, 2.093750s user + 0.015625s system = 2.109375s CPU (140.9%)
+
+PHY-1001 : Congestion index: top1 = 99.87, top5 = 75.86, top10 = 64.84, top15 = 58.31.
+PHY-3001 : End congestion estimation;  1.810601s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (132.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.124527s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000129943
+PHY-3002 : Step(241): len = 681873, overlap = 278.219
+PHY-3002 : Step(242): len = 676247, overlap = 242.281
+PHY-3002 : Step(243): len = 667975, overlap = 231.219
+PHY-3002 : Step(244): len = 661968, overlap = 214.219
+PHY-3002 : Step(245): len = 656719, overlap = 187
+PHY-3002 : Step(246): len = 651853, overlap = 181.094
+PHY-3002 : Step(247): len = 646529, overlap = 173.406
+PHY-3002 : Step(248): len = 642036, overlap = 156.594
+PHY-3002 : Step(249): len = 636195, overlap = 144.875
+PHY-3002 : Step(250): len = 632755, overlap = 138.469
+PHY-3002 : Step(251): len = 627591, overlap = 140.031
+PHY-3002 : Step(252): len = 624125, overlap = 134.531
+PHY-3002 : Step(253): len = 620458, overlap = 130.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000259887
+PHY-3002 : Step(254): len = 620529, overlap = 126.156
+PHY-3002 : Step(255): len = 624335, overlap = 117.5
+PHY-3002 : Step(256): len = 625817, overlap = 112.25
+PHY-3002 : Step(257): len = 626164, overlap = 103.656
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000519774
+PHY-3002 : Step(258): len = 628410, overlap = 99.25
+PHY-3002 : Step(259): len = 634123, overlap = 91.375
+PHY-3002 : Step(260): len = 639655, overlap = 86.125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00103955
+PHY-3002 : Step(261): len = 640272, overlap = 85.0625
+PHY-3002 : Step(262): len = 642978, overlap = 82.9062
+PHY-3002 : Step(263): len = 650883, overlap = 77.7812
+PHY-3002 : Step(264): len = 655430, overlap = 74.9375
+PHY-3002 : Step(265): len = 655972, overlap = 73
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87531, tnet num: 20813, tinst num: 18411, tnode num: 120170, tedge num: 140166.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.509558s wall, 1.453125s user + 0.062500s system = 1.515625s CPU (100.4%)
+
+RUN-1004 : used memory is 593 MB, reserved memory is 576 MB, peak memory is 729 MB
+OPT-1001 : Total overflow 413.03 peak overflow 3.94
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 660/20991.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 746856, over cnt = 3001(8%), over = 11104, worst = 22
+PHY-1001 : End global iterations;  1.482357s wall, 2.093750s user + 0.000000s system = 2.093750s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 70.65, top5 = 57.69, top10 = 51.54, top15 = 47.74.
+PHY-1001 : End incremental global routing;  1.848599s wall, 2.453125s user + 0.000000s system = 2.453125s CPU (132.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20813 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.993397s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (100.7%)
+
+OPT-1001 : 48 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18278 has valid locations, 317 needs to be replaced
+PHY-3001 : design contains 18680 instances, 7395 luts, 10064 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 6828 pins
+PHY-3001 : Found 3513 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 679405
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17186/21260.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 762600, over cnt = 3078(8%), over = 11268, worst = 22
+PHY-1001 : End global iterations;  0.243973s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (134.5%)
+
+PHY-1001 : Congestion index: top1 = 70.71, top5 = 58.06, top10 = 51.88, top15 = 48.09.
+PHY-3001 : End congestion estimation;  0.517797s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (114.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88635, tnet num: 21082, tinst num: 18680, tnode num: 121812, tedge num: 141836.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.576095s wall, 1.531250s user + 0.046875s system = 1.578125s CPU (100.1%)
+
+RUN-1004 : used memory is 641 MB, reserved memory is 629 MB, peak memory is 734 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21082 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.601678s wall, 2.546875s user + 0.062500s system = 2.609375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(266): len = 678151, overlap = 0
+PHY-3002 : Step(267): len = 677810, overlap = 0
+PHY-3002 : Step(268): len = 677871, overlap = 0
+PHY-3002 : Step(269): len = 677766, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 59%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17265/21260.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 760496, over cnt = 3076(8%), over = 11314, worst = 23
+PHY-1001 : End global iterations;  0.198281s wall, 0.281250s user + 0.031250s system = 0.312500s CPU (157.6%)
+
+PHY-1001 : Congestion index: top1 = 71.70, top5 = 58.62, top10 = 52.28, top15 = 48.36.
+PHY-3001 : End congestion estimation;  0.503646s wall, 0.593750s user + 0.031250s system = 0.625000s CPU (124.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 21082 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.994143s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000469176
+PHY-3002 : Step(270): len = 677714, overlap = 76.25
+PHY-3002 : Step(271): len = 677886, overlap = 75.7188
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000938352
+PHY-3002 : Step(272): len = 678292, overlap = 75.5625
+PHY-3002 : Step(273): len = 678903, overlap = 75.5
+PHY-3001 : Final: Len = 678903, Over = 75.5
+PHY-3001 : End incremental placement;  5.366885s wall, 5.703125s user + 0.265625s system = 5.968750s CPU (111.2%)
+
+OPT-1001 : Total overflow 419.91 peak overflow 3.94
+OPT-1001 : End high-fanout net optimization;  8.790586s wall, 9.812500s user + 0.281250s system = 10.093750s CPU (114.8%)
+
+OPT-1001 : Current memory(MB): used = 736, reserve = 724, peak = 754.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17239/21260.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 764424, over cnt = 3015(8%), over = 10271, worst = 22
+PHY-1002 : len = 822176, over cnt = 1943(5%), over = 4732, worst = 22
+PHY-1002 : len = 854480, over cnt = 944(2%), over = 2123, worst = 22
+PHY-1002 : len = 873928, over cnt = 399(1%), over = 880, worst = 16
+PHY-1002 : len = 893416, over cnt = 10(0%), over = 10, worst = 1
+PHY-1001 : End global iterations;  1.882546s wall, 2.640625s user + 0.000000s system = 2.640625s CPU (140.3%)
+
+PHY-1001 : Congestion index: top1 = 56.44, top5 = 50.17, top10 = 46.94, top15 = 44.72.
+OPT-1001 : End congestion update;  2.160539s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (135.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21082 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.845194s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1118 TNS -1757 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -968 TNS -1528 NUM_FEPS 2 with 128 cells processed and 16200 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1528 NUM_FEPS 2 with 36 cells processed and 5950 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1528 NUM_FEPS 2 with 14 cells processed and 1600 slack improved
+OPT-0007 : Iter 4: improved WNS -968 TNS -1528 NUM_FEPS 2 with 3 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization;  3.464859s wall, 4.203125s user + 0.015625s system = 4.218750s CPU (121.8%)
+
+OPT-1001 : Current memory(MB): used = 711, reserve = 699, peak = 754.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17242/21268.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 894840, over cnt = 129(0%), over = 151, worst = 3
+PHY-1002 : len = 894472, over cnt = 64(0%), over = 66, worst = 2
+PHY-1002 : len = 894928, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 895048, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 895216, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.825738s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (111.6%)
+
+PHY-1001 : Congestion index: top1 = 56.38, top5 = 50.25, top10 = 46.96, top15 = 44.74.
+OPT-1001 : End congestion update;  1.135893s wall, 1.218750s user + 0.015625s system = 1.234375s CPU (108.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21090 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.868116s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.8%)
+
+OPT-0007 : Start: WNS -968 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1478 NUM_FEPS 2 with 17 cells processed and 2550 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1478 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.132104s wall, 2.218750s user + 0.015625s system = 2.234375s CPU (104.8%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 714, peak = 754.
+OPT-1001 : End physical optimization;  16.236088s wall, 18.015625s user + 0.390625s system = 18.406250s CPU (113.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7395 LUT to BLE ...
+SYN-4008 : Packed 7395 LUT and 3497 SEQ to BLE.
+SYN-4003 : Packing 6575 remaining SEQ's ...
+SYN-4005 : Packed 3546 SEQ with LUT/SLICE
+SYN-4006 : 655 single LUT's are left
+SYN-4006 : 3029 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10424/14171 primitive instances ...
+PHY-3001 : End packing;  1.950691s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7131 instances
+RUN-1001 : 3491 mslices, 3492 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17883 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 10324 nets have 2 pins
+RUN-1001 : 5720 nets have [3 - 5] pins
+RUN-1001 : 1161 nets have [6 - 10] pins
+RUN-1001 : 290 nets have [11 - 20] pins
+RUN-1001 : 354 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 7129 instances, 6983 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 3953 pins
+PHY-3001 : Found 1577 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : After packing: Len = 685947, Over = 267
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7392/17883.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 833704, over cnt = 1955(5%), over = 3207, worst = 8
+PHY-1002 : len = 839720, over cnt = 1345(3%), over = 2022, worst = 7
+PHY-1002 : len = 852768, over cnt = 621(1%), over = 907, worst = 6
+PHY-1002 : len = 861728, over cnt = 223(0%), over = 339, worst = 6
+PHY-1002 : len = 866984, over cnt = 2(0%), over = 11, worst = 6
+PHY-1001 : End global iterations;  2.565802s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (106.0%)
+
+PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.18, top10 = 45.86, top15 = 43.62.
+PHY-3001 : End congestion estimation;  3.073866s wall, 3.156250s user + 0.031250s system = 3.187500s CPU (103.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74820, tnet num: 17705, tinst num: 7129, tnode num: 98862, tedge num: 125677.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.944391s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (94.8%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 627 MB, peak memory is 754 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17705 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.970881s wall, 2.828125s user + 0.046875s system = 2.875000s CPU (96.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 6.21669e-05
+PHY-3002 : Step(274): len = 674694, overlap = 265.5
+PHY-3002 : Step(275): len = 668740, overlap = 252.25
+PHY-3002 : Step(276): len = 663929, overlap = 256.75
+PHY-3002 : Step(277): len = 660317, overlap = 273.5
+PHY-3002 : Step(278): len = 656717, overlap = 282.5
+PHY-3002 : Step(279): len = 654008, overlap = 280.5
+PHY-3002 : Step(280): len = 651057, overlap = 279.25
+PHY-3002 : Step(281): len = 648080, overlap = 280.75
+PHY-3002 : Step(282): len = 645391, overlap = 285.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000124334
+PHY-3002 : Step(283): len = 649183, overlap = 274
+PHY-3002 : Step(284): len = 653087, overlap = 272.25
+PHY-3002 : Step(285): len = 652979, overlap = 268.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000248668
+PHY-3002 : Step(286): len = 659862, overlap = 257
+PHY-3002 : Step(287): len = 664549, overlap = 255.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.366466s wall, 0.375000s user + 0.546875s system = 0.921875s CPU (251.6%)
+
+PHY-3001 : Trial Legalized: Len = 817605
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 733/17883.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934112, over cnt = 2689(7%), over = 4352, worst = 7
+PHY-1002 : len = 951976, over cnt = 1353(3%), over = 1900, worst = 5
+PHY-1002 : len = 968560, over cnt = 495(1%), over = 671, worst = 5
+PHY-1002 : len = 976496, over cnt = 176(0%), over = 220, worst = 5
+PHY-1002 : len = 980056, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.635595s wall, 3.765625s user + 0.015625s system = 3.781250s CPU (143.5%)
+
+PHY-1001 : Congestion index: top1 = 56.29, top5 = 50.64, top10 = 47.67, top15 = 45.75.
+PHY-3001 : End congestion estimation;  3.151840s wall, 4.265625s user + 0.015625s system = 4.281250s CPU (135.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17705 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.911447s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (101.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000188337
+PHY-3002 : Step(288): len = 779288, overlap = 71.5
+PHY-3002 : Step(289): len = 758482, overlap = 106.75
+PHY-3002 : Step(290): len = 742969, overlap = 124.5
+PHY-3002 : Step(291): len = 732823, overlap = 147.75
+PHY-3002 : Step(292): len = 725472, overlap = 165.75
+PHY-3002 : Step(293): len = 717975, overlap = 173.5
+PHY-3002 : Step(294): len = 711364, overlap = 183.75
+PHY-3002 : Step(295): len = 707434, overlap = 199.75
+PHY-3002 : Step(296): len = 703122, overlap = 197.5
+PHY-3002 : Step(297): len = 699628, overlap = 202.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000376674
+PHY-3002 : Step(298): len = 704560, overlap = 196
+PHY-3002 : Step(299): len = 706957, overlap = 193.5
+PHY-3002 : Step(300): len = 707879, overlap = 189.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000649377
+PHY-3002 : Step(301): len = 712297, overlap = 184.5
+PHY-3002 : Step(302): len = 718689, overlap = 183.25
+PHY-3002 : Step(303): len = 722495, overlap = 181
+PHY-3002 : Step(304): len = 722607, overlap = 181.25
+PHY-3002 : Step(305): len = 723410, overlap = 174.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.086996s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (107.8%)
+
+PHY-3001 : Legalized: Len = 771985, Over = 0
+PHY-3001 : Spreading special nets. 462 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.125079s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (99.9%)
+
+PHY-3001 : 709 instances has been re-located, deltaX = 263, deltaY = 451, maxDist = 3.
+PHY-3001 : Final: Len = 782163, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74820, tnet num: 17705, tinst num: 7132, tnode num: 98862, tedge num: 125677.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  2.042472s wall, 2.031250s user + 0.015625s system = 2.046875s CPU (100.2%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 661 MB, peak memory is 754 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3056/17883.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 905160, over cnt = 2557(7%), over = 4084, worst = 7
+PHY-1002 : len = 919160, over cnt = 1511(4%), over = 2133, worst = 6
+PHY-1002 : len = 931800, over cnt = 855(2%), over = 1178, worst = 5
+PHY-1002 : len = 946024, over cnt = 175(0%), over = 227, worst = 5
+PHY-1002 : len = 950104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.210332s wall, 3.296875s user + 0.015625s system = 3.312500s CPU (149.9%)
+
+PHY-1001 : Congestion index: top1 = 53.25, top5 = 48.64, top10 = 46.18, top15 = 44.44.
+PHY-1001 : End incremental global routing;  2.667760s wall, 3.750000s user + 0.015625s system = 3.765625s CPU (141.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17705 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.108407s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.1%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7039 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 7153 instances, 7004 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4023 pins
+PHY-3001 : Found 1580 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 784981
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16325/17905.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 953224, over cnt = 88(0%), over = 100, worst = 3
+PHY-1002 : len = 953472, over cnt = 31(0%), over = 32, worst = 2
+PHY-1002 : len = 953696, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 953824, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 953872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.895450s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (103.0%)
+
+PHY-1001 : Congestion index: top1 = 53.36, top5 = 48.69, top10 = 46.22, top15 = 44.48.
+PHY-3001 : End congestion estimation;  1.276783s wall, 1.312500s user + 0.000000s system = 1.312500s CPU (102.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75010, tnet num: 17727, tinst num: 7153, tnode num: 99110, tedge num: 125916.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  2.010927s wall, 2.015625s user + 0.000000s system = 2.015625s CPU (100.2%)
+
+RUN-1004 : used memory is 698 MB, reserved memory is 695 MB, peak memory is 754 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17727 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.987426s wall, 2.984375s user + 0.000000s system = 2.984375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(306): len = 784001, overlap = 0
+PHY-3002 : Step(307): len = 783621, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16309/17905.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 951560, over cnt = 67(0%), over = 79, worst = 3
+PHY-1002 : len = 951744, over cnt = 23(0%), over = 24, worst = 2
+PHY-1002 : len = 951944, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 952032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.681573s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (112.3%)
+
+PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.61, top10 = 46.19, top15 = 44.44.
+PHY-3001 : End congestion estimation;  1.063949s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (107.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17727 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.051535s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000444905
+PHY-3002 : Step(308): len = 783665, overlap = 0.5
+PHY-3002 : Step(309): len = 783676, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005952s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (262.5%)
+
+PHY-3001 : Legalized: Len = 783741, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.068344s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (114.3%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 4, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 783863, Over = 0
+PHY-3001 : End incremental placement;  6.929175s wall, 7.250000s user + 0.078125s system = 7.328125s CPU (105.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  11.316399s wall, 12.703125s user + 0.093750s system = 12.796875s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 750, reserve = 740, peak = 754.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16304/17905.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 952200, over cnt = 59(0%), over = 74, worst = 4
+PHY-1002 : len = 952552, over cnt = 21(0%), over = 22, worst = 2
+PHY-1002 : len = 952624, over cnt = 9(0%), over = 9, worst = 1
+PHY-1002 : len = 952696, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 952720, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.841442s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 53.45, top5 = 48.66, top10 = 46.23, top15 = 44.47.
+OPT-1001 : End congestion update;  1.193618s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (104.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17727 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.772056s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.2%)
+
+OPT-0007 : Start: WNS -1086 TNS -2050 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7065 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7153 instances, 7004 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4023 pins
+PHY-3001 : Found 1580 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 790821, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.072465s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (107.8%)
+
+PHY-3001 : 42 instances has been re-located, deltaX = 13, deltaY = 49, maxDist = 5.
+PHY-3001 : Final: Len = 791731, Over = 0
+PHY-3001 : End incremental legalization;  0.439200s wall, 0.515625s user + 0.015625s system = 0.531250s CPU (121.0%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1600 NUM_FEPS 3 with 56 cells processed and 16920 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7065 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7153 instances, 7004 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4023 pins
+PHY-3001 : Found 1580 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 792085, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.069875s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.8%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 9, deltaY = 20, maxDist = 3.
+PHY-3001 : Final: Len = 792395, Over = 0
+PHY-3001 : End incremental legalization;  0.440061s wall, 0.437500s user + 0.031250s system = 0.468750s CPU (106.5%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1600 NUM_FEPS 3 with 22 cells processed and 2320 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7065 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7153 instances, 7004 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4023 pins
+PHY-3001 : Found 1580 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 791709, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.069569s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (112.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 4, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 791891, Over = 0
+PHY-3001 : End incremental legalization;  0.441173s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.2%)
+
+OPT-0007 : Iter 3: improved WNS -936 TNS -1600 NUM_FEPS 3 with 11 cells processed and 682 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7075 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7163 instances, 7014 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4027 pins
+PHY-3001 : Found 1586 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Initial: Len = 793182, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.069867s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.8%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 3, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 793268, Over = 0
+PHY-3001 : End incremental legalization;  0.438702s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.7%)
+
+OPT-0007 : Iter 4: improved WNS -936 TNS -1600 NUM_FEPS 3 with 9 cells processed and 1460 slack improved
+OPT-1001 : End bottleneck based optimization;  4.399430s wall, 4.593750s user + 0.046875s system = 4.640625s CPU (105.5%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 740, peak = 754.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15887/17909.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 961672, over cnt = 262(0%), over = 334, worst = 4
+PHY-1002 : len = 962216, over cnt = 126(0%), over = 143, worst = 4
+PHY-1002 : len = 963024, over cnt = 65(0%), over = 71, worst = 3
+PHY-1002 : len = 963736, over cnt = 15(0%), over = 16, worst = 2
+PHY-1002 : len = 963952, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.971881s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (114.1%)
+
+PHY-1001 : Congestion index: top1 = 53.32, top5 = 48.42, top10 = 46.12, top15 = 44.49.
+OPT-1001 : End congestion update;  1.326111s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (110.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.794444s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.3%)
+
+OPT-0007 : Start: WNS -936 TNS -1600 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7075 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7163 instances, 7014 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4027 pins
+PHY-3001 : Found 1586 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Initial: Len = 793858, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.071934s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (86.9%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 1, deltaY = 10, maxDist = 3.
+PHY-3001 : Final: Len = 793898, Over = 0
+PHY-3001 : End incremental legalization;  0.449115s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.9%)
+
+OPT-0007 : Iter 1: improved WNS -886 TNS -1500 NUM_FEPS 3 with 12 cells processed and 900 slack improved
+OPT-0007 : Iter 2: improved WNS -886 TNS -1500 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.719048s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (108.0%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 740, peak = 754.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.795248s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16311/17909.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 964440, over cnt = 23(0%), over = 28, worst = 2
+PHY-1002 : len = 964448, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 964560, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 964576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.664527s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.40, top10 = 46.10, top15 = 44.46.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.826839s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -936 TNS -1600 NUM_FEPS 3
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 52.620690
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -936ps with logic level 2 
+RUN-1001 :       #2 path slack -890ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 17909 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17909 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7075 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7163 instances, 7014 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4027 pins
+PHY-3001 : Found 1586 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Initial: Len = 793898, Over = 0
+PHY-3001 : End spreading;  0.070859s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (110.3%)
+
+PHY-3001 : Final: Len = 793898, Over = 0
+PHY-3001 : End incremental legalization;  0.445347s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.794197s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.3%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16353/17909.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 964576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.144104s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.6%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.40, top10 = 46.10, top15 = 44.46.
+OPT-1001 : End congestion update;  0.509094s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (101.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.796828s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.0%)
+
+OPT-0007 : Start: WNS -936 TNS -1600 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7075 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7163 instances, 7014 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_2803 with 4027 pins
+PHY-3001 : Found 1586 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 77%
+PHY-3001 : Initial: Len = 793918, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.069622s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (89.8%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 793898, Over = 0
+PHY-3001 : End incremental legalization;  0.452654s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (117.4%)
+
+OPT-0007 : Iter 1: improved WNS -886 TNS -1500 NUM_FEPS 3 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS -886 TNS -1500 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.886437s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (107.7%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 740, peak = 754.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16353/17909.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 964576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.145575s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.6%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.40, top10 = 46.10, top15 = 44.46.
+OPT-1001 : End congestion update;  0.501050s wall, 0.468750s user + 0.015625s system = 0.484375s CPU (96.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.788371s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (101.1%)
+
+OPT-0007 : Start: WNS -936 TNS -1600 NUM_FEPS 3
+OPT-0007 : Iter 1: improved WNS -936 TNS -1600 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -936 TNS -1600 NUM_FEPS 3 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.454742s wall, 1.421875s user + 0.015625s system = 1.437500s CPU (98.8%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 740, peak = 754.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.782385s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 751, reserve = 740, peak = 754.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.782031s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (99.9%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16353/17909.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 964576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.144358s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.4%)
+
+PHY-1001 : Congestion index: top1 = 53.10, top5 = 48.40, top10 = 46.10, top15 = 44.46.
+RUN-1001 : End congestion update;  0.500740s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (103.0%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.286901s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (100.8%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 740, peak = 754.
+OPT-1001 : End physical optimization;  30.336006s wall, 32.203125s user + 0.203125s system = 32.406250s CPU (106.8%)
+
+RUN-1003 : finish command "place" in  83.029145s wall, 119.906250s user + 6.546875s system = 126.453125s CPU (152.3%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 646 MB, peak memory is 754 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.776712s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (175.0%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 647 MB, peak memory is 754 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7165 instances
+RUN-1001 : 3510 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17909 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 10308 nets have 2 pins
+RUN-1001 : 5740 nets have [3 - 5] pins
+RUN-1001 : 1168 nets have [6 - 10] pins
+RUN-1001 : 292 nets have [11 - 20] pins
+RUN-1001 : 371 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75103, tnet num: 17731, tinst num: 7163, tnode num: 99239, tedge num: 126041.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.756714s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (100.5%)
+
+RUN-1004 : used memory is 674 MB, reserved memory is 674 MB, peak memory is 754 MB
+PHY-1001 : 3510 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 899464, over cnt = 2745(7%), over = 4374, worst = 7
+PHY-1002 : len = 915376, over cnt = 1671(4%), over = 2372, worst = 7
+PHY-1002 : len = 934328, over cnt = 681(1%), over = 925, worst = 6
+PHY-1002 : len = 947896, over cnt = 83(0%), over = 117, worst = 5
+PHY-1002 : len = 949648, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.330957s wall, 4.375000s user + 0.031250s system = 4.406250s CPU (132.3%)
+
+PHY-1001 : Congestion index: top1 = 53.47, top5 = 48.58, top10 = 45.95, top15 = 44.26.
+PHY-1001 : End global routing;  3.679136s wall, 4.718750s user + 0.031250s system = 4.750000s CPU (129.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 729, reserve = 726, peak = 754.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1006, reserve = 1002, peak = 1006.
+PHY-1001 : End build detailed router design. 4.144540s wall, 4.140625s user + 0.000000s system = 4.140625s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267704, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.932710s wall, 5.843750s user + 0.015625s system = 5.859375s CPU (98.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267760, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.812715s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (67.3%)
+
+PHY-1001 : Current memory(MB): used = 1042, reserve = 1039, peak = 1042.
+PHY-1001 : End phase 1; 6.759607s wall, 6.406250s user + 0.015625s system = 6.421875s CPU (95.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.4231e+06, over cnt = 1795(0%), over = 1798, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1058, reserve = 1055, peak = 1058.
+PHY-1001 : End initial routed; 30.387234s wall, 56.609375s user + 0.203125s system = 56.812500s CPU (187.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16830(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.021   |  -4.081   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.332232s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1071, reserve = 1069, peak = 1071.
+PHY-1001 : End phase 2; 33.719530s wall, 59.937500s user + 0.203125s system = 60.140625s CPU (178.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.884ns STNS -3.944ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.143012s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.3%)
+
+PHY-1022 : len = 2.4231e+06, over cnt = 1797(0%), over = 1800, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.414684s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.39273e+06, over cnt = 601(0%), over = 602, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.552764s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (169.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.39177e+06, over cnt = 135(0%), over = 135, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.593872s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (131.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.39244e+06, over cnt = 18(0%), over = 18, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.353466s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (114.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.39281e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.262911s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.3929e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.189707s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16830(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.884   |  -3.944   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.321067s wall, 3.281250s user + 0.031250s system = 3.312500s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 542 feed throughs used by 440 nets
+PHY-1001 : End commit to database; 2.282105s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1173, reserve = 1174, peak = 1173.
+PHY-1001 : End phase 3; 9.375397s wall, 10.640625s user + 0.031250s system = 10.671875s CPU (113.8%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.884ns STNS -3.944ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.151066s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.4%)
+
+PHY-1022 : len = 2.3929e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.400490s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.884ns, -3.944ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3929e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.165923s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (94.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.3929e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.165878s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (103.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16830(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.884   |  -3.944   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.305680s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.7%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 542 feed throughs used by 440 nets
+PHY-1001 : End commit to database; 2.365837s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1183, reserve = 1184, peak = 1183.
+PHY-1001 : End phase 4; 6.459852s wall, 6.468750s user + 0.000000s system = 6.468750s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.3929e+06
+PHY-1001 : Current memory(MB): used = 1187, reserve = 1188, peak = 1187.
+PHY-1001 : End export database. 0.064194s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.4%)
+
+PHY-1001 : End detail routing;  60.928694s wall, 88.062500s user + 0.250000s system = 88.312500s CPU (144.9%)
+
+RUN-1003 : finish command "route" in  67.487693s wall, 95.625000s user + 0.312500s system = 95.937500s CPU (142.2%)
+
+RUN-1004 : used memory is 1107 MB, reserved memory is 1105 MB, peak memory is 1187 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10140   out of  19600   51.73%
+#reg                    10217   out of  19600   52.13%
+#le                     13052
+  #lut only              2835   out of  13052   21.72%
+  #reg only              2912   out of  13052   22.31%
+  #lut&reg               7305   out of  13052   55.97%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1810
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1597
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1513
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               968
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    138
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg1_syn_192.f1                          3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg47_syn_193.f1    3
+#12       a_lvds_clk_p_dup_1                                 GeneralRouting     io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P165       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P70        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |13052  |9113    |1027    |10247   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |522    |406     |23      |446     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |99     |90      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |24     |24      |0       |17      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |754    |461     |96      |555     |0       |0       |
+|    u_ADconfig                |AD_config            |193    |144     |25      |148     |0       |0       |
+|    u_gen_sp                  |gen_sp               |266    |163     |71      |112     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |737    |373     |96      |556     |0       |0       |
+|    u_ADconfig                |AD_config            |167    |107     |25      |124     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |159     |71      |120     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3316   |2453    |306     |2519    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |187    |96      |17      |150     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |3093   |2340    |289     |2333    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2713   |2087    |253     |1990    |22      |0       |
+|        channelPart           |channel_part_8478    |131    |128     |3       |119     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |44      |0       |0       |
+|        ram_switch            |ram_switch           |2129   |1575    |197     |1559    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |220    |193     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |15      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |16      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |11      |0       |0       |
+|          insert              |insert               |1021   |605     |170     |735     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |514    |509     |0       |331     |0       |0       |
+|        read_ram_i            |read_ram             |354    |306     |44      |230     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |215    |175     |40      |149     |0       |0       |
+|          read_ram_data       |read_ram_data        |136    |128     |4       |78      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |305    |208     |36      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3610   |2669    |349     |2482    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |8      |1       |0       |8       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |183    |121     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |0       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |3389   |2546    |332     |2296    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2945   |2242    |290     |1929    |22      |1       |
+|        channelPart           |channel_part_8478    |217    |205     |3       |136     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |2289   |1716    |197     |1526    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |211    |178     |27      |122     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |5       |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |19      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |9       |0       |0       |
+|          insert              |insert               |995    |528     |170     |704     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |686    |684     |0       |332     |0       |0       |
+|        read_ram_i            |read_ram_rev         |358    |250     |81      |202     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |295    |212     |73      |156     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |63     |38      |8       |46      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10246  
+    #2         2       3809   
+    #3         3       1414   
+    #4         4        514   
+    #5        5-10     1224   
+    #6       11-50      585   
+    #7       51-100     19    
+    #8        >500       1    
+  Average     2.88            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.115411s wall, 3.625000s user + 0.031250s system = 3.656250s CPU (172.8%)
+
+RUN-1004 : used memory is 1108 MB, reserved memory is 1106 MB, peak memory is 1187 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75103, tnet num: 17731, tinst num: 7163, tnode num: 99239, tedge num: 126041.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.652633s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.2%)
+
+RUN-1004 : used memory is 1113 MB, reserved memory is 1111 MB, peak memory is 1187 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17731 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.499508s wall, 1.484375s user + 0.015625s system = 1.500000s CPU (100.0%)
+
+RUN-1004 : used memory is 1120 MB, reserved memory is 1118 MB, peak memory is 1187 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7163
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17909, pip num: 176056
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 542
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3238 valid insts, and 488083 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.583947s wall, 63.203125s user + 0.171875s system = 63.375000s CPU (661.3%)
+
+RUN-1004 : used memory is 1291 MB, reserved memory is 1288 MB, peak memory is 1406 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_111825.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_112841.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_112841.log
new file mode 100644
index 0000000..53f0a63
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_112841.log
@@ -0,0 +1,1059 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:28:41 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.134391s wall, 2.078125s user + 0.046875s system = 2.125000s CPU (99.6%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 315 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing ultra"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   ultra    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2213 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17801 instances
+RUN-0007 : 7499 luts, 9079 seqs, 702 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20376 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13426 nets have 2 pins
+RUN-1001 : 5469 nets have [3 - 5] pins
+RUN-1001 : 1069 nets have [6 - 10] pins
+RUN-1001 : 167 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     789     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3483     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     58     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 143
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17799 instances, 7499 luts, 9079 seqs, 1075 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5931 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85409, tnet num: 20198, tinst num: 17799, tnode num: 115599, tedge num: 137148.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.162978s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (99.4%)
+
+RUN-1004 : used memory is 540 MB, reserved memory is 516 MB, peak memory is 540 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.987452s wall, 1.921875s user + 0.062500s system = 1.984375s CPU (99.8%)
+
+PHY-3001 : Found 3478 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.04955e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17799.
+PHY-3001 : Level 1 #clusters 2339.
+PHY-3001 : End clustering;  0.137614s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (113.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35927e+06, overlap = 476.344
+PHY-3002 : Step(2): len = 1.10735e+06, overlap = 571
+PHY-3002 : Step(3): len = 890263, overlap = 653.656
+PHY-3002 : Step(4): len = 788016, overlap = 694
+PHY-3002 : Step(5): len = 628789, overlap = 844.812
+PHY-3002 : Step(6): len = 556318, overlap = 899.5
+PHY-3002 : Step(7): len = 463227, overlap = 1005.22
+PHY-3002 : Step(8): len = 424180, overlap = 1049.5
+PHY-3002 : Step(9): len = 377138, overlap = 1116.44
+PHY-3002 : Step(10): len = 343300, overlap = 1168.75
+PHY-3002 : Step(11): len = 317073, overlap = 1234.22
+PHY-3002 : Step(12): len = 288564, overlap = 1282.97
+PHY-3002 : Step(13): len = 269318, overlap = 1327.28
+PHY-3002 : Step(14): len = 245741, overlap = 1325.66
+PHY-3002 : Step(15): len = 229601, overlap = 1343.84
+PHY-3002 : Step(16): len = 214176, overlap = 1406.25
+PHY-3002 : Step(17): len = 203014, overlap = 1403.19
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.22648e-06
+PHY-3002 : Step(18): len = 208157, overlap = 1358.84
+PHY-3002 : Step(19): len = 243816, overlap = 1281.5
+PHY-3002 : Step(20): len = 249457, overlap = 1214.44
+PHY-3002 : Step(21): len = 252589, overlap = 1143.75
+PHY-3002 : Step(22): len = 244934, overlap = 1109.47
+PHY-3002 : Step(23): len = 243747, overlap = 1090.94
+PHY-3002 : Step(24): len = 236902, overlap = 1096.56
+PHY-3002 : Step(25): len = 233288, overlap = 1091.69
+PHY-3002 : Step(26): len = 227597, overlap = 1077.03
+PHY-3002 : Step(27): len = 225507, overlap = 1068.97
+PHY-3002 : Step(28): len = 223415, overlap = 1067.97
+PHY-3002 : Step(29): len = 222385, overlap = 1065.12
+PHY-3002 : Step(30): len = 219737, overlap = 1045.47
+PHY-3002 : Step(31): len = 218956, overlap = 1042.28
+PHY-3002 : Step(32): len = 216908, overlap = 1045.56
+PHY-3002 : Step(33): len = 215371, overlap = 1042.09
+PHY-3002 : Step(34): len = 214190, overlap = 1029.12
+PHY-3002 : Step(35): len = 213915, overlap = 1029.59
+PHY-3002 : Step(36): len = 212060, overlap = 1035.66
+PHY-3002 : Step(37): len = 210685, overlap = 1042.47
+PHY-3002 : Step(38): len = 208117, overlap = 1047.53
+PHY-3002 : Step(39): len = 208030, overlap = 1060.28
+PHY-3002 : Step(40): len = 205948, overlap = 1056.81
+PHY-3002 : Step(41): len = 205706, overlap = 1062.59
+PHY-3002 : Step(42): len = 203457, overlap = 1056.84
+PHY-3002 : Step(43): len = 202612, overlap = 1069.19
+PHY-3002 : Step(44): len = 201278, overlap = 1067.56
+PHY-3002 : Step(45): len = 199756, overlap = 1074.56
+PHY-3002 : Step(46): len = 198619, overlap = 1067.38
+PHY-3002 : Step(47): len = 198074, overlap = 1077.16
+PHY-3002 : Step(48): len = 197228, overlap = 1083.12
+PHY-3002 : Step(49): len = 196149, overlap = 1078.69
+PHY-3002 : Step(50): len = 194899, overlap = 1094.47
+PHY-3002 : Step(51): len = 194187, overlap = 1086.5
+PHY-3002 : Step(52): len = 193464, overlap = 1084.94
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.45297e-06
+PHY-3002 : Step(53): len = 197207, overlap = 1094.94
+PHY-3002 : Step(54): len = 212737, overlap = 1061.12
+PHY-3002 : Step(55): len = 219902, overlap = 1003.31
+PHY-3002 : Step(56): len = 224185, overlap = 1001.97
+PHY-3002 : Step(57): len = 225884, overlap = 993.438
+PHY-3002 : Step(58): len = 226730, overlap = 974.375
+PHY-3002 : Step(59): len = 224814, overlap = 970.938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.90594e-06
+PHY-3002 : Step(60): len = 237137, overlap = 939.812
+PHY-3002 : Step(61): len = 259457, overlap = 847.469
+PHY-3002 : Step(62): len = 266262, overlap = 810.406
+PHY-3002 : Step(63): len = 269941, overlap = 781.25
+PHY-3002 : Step(64): len = 270155, overlap = 769.125
+PHY-3002 : Step(65): len = 268776, overlap = 759.344
+PHY-3002 : Step(66): len = 267336, overlap = 761.719
+PHY-3002 : Step(67): len = 266282, overlap = 759.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.81188e-06
+PHY-3002 : Step(68): len = 285003, overlap = 712.875
+PHY-3002 : Step(69): len = 309633, overlap = 670.969
+PHY-3002 : Step(70): len = 317660, overlap = 619.781
+PHY-3002 : Step(71): len = 318886, overlap = 603
+PHY-3002 : Step(72): len = 316971, overlap = 604
+PHY-3002 : Step(73): len = 315676, overlap = 595.844
+PHY-3002 : Step(74): len = 314724, overlap = 603.906
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.96238e-05
+PHY-3002 : Step(75): len = 341050, overlap = 542.875
+PHY-3002 : Step(76): len = 362778, overlap = 468.344
+PHY-3002 : Step(77): len = 367922, overlap = 458.625
+PHY-3002 : Step(78): len = 369554, overlap = 437.438
+PHY-3002 : Step(79): len = 368275, overlap = 416.594
+PHY-3002 : Step(80): len = 369287, overlap = 415.188
+PHY-3002 : Step(81): len = 368839, overlap = 406.5
+PHY-3002 : Step(82): len = 370035, overlap = 385.344
+PHY-3002 : Step(83): len = 369013, overlap = 377.719
+PHY-3002 : Step(84): len = 369323, overlap = 377
+PHY-3002 : Step(85): len = 368996, overlap = 365.719
+PHY-3002 : Step(86): len = 369873, overlap = 355.344
+PHY-3002 : Step(87): len = 368234, overlap = 355.688
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.92475e-05
+PHY-3002 : Step(88): len = 394158, overlap = 303.25
+PHY-3002 : Step(89): len = 411248, overlap = 280.031
+PHY-3002 : Step(90): len = 411205, overlap = 274.875
+PHY-3002 : Step(91): len = 411829, overlap = 257.781
+PHY-3002 : Step(92): len = 414401, overlap = 277.625
+PHY-3002 : Step(93): len = 418565, overlap = 283.094
+PHY-3002 : Step(94): len = 417737, overlap = 294.969
+PHY-3002 : Step(95): len = 417589, overlap = 295.125
+PHY-3002 : Step(96): len = 414913, overlap = 316.906
+PHY-3002 : Step(97): len = 415386, overlap = 311.062
+PHY-3002 : Step(98): len = 414382, overlap = 301.656
+PHY-3002 : Step(99): len = 416215, overlap = 299.906
+PHY-3002 : Step(100): len = 415113, overlap = 302.344
+PHY-3002 : Step(101): len = 416677, overlap = 290.125
+PHY-3002 : Step(102): len = 415518, overlap = 269.281
+PHY-3002 : Step(103): len = 417349, overlap = 244.875
+PHY-3002 : Step(104): len = 416870, overlap = 232.625
+PHY-3002 : Step(105): len = 418289, overlap = 237.656
+PHY-3002 : Step(106): len = 416541, overlap = 235.781
+PHY-3002 : Step(107): len = 417181, overlap = 247.562
+PHY-3002 : Step(108): len = 415667, overlap = 246.906
+PHY-3002 : Step(109): len = 416477, overlap = 241.094
+PHY-3002 : Step(110): len = 414944, overlap = 238.406
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.8495e-05
+PHY-3002 : Step(111): len = 433777, overlap = 228.156
+PHY-3002 : Step(112): len = 445918, overlap = 221.656
+PHY-3002 : Step(113): len = 445010, overlap = 212.188
+PHY-3002 : Step(114): len = 445274, overlap = 212.938
+PHY-3002 : Step(115): len = 447086, overlap = 201.438
+PHY-3002 : Step(116): len = 450228, overlap = 210.125
+PHY-3002 : Step(117): len = 449760, overlap = 199.312
+PHY-3002 : Step(118): len = 449974, overlap = 183.25
+PHY-3002 : Step(119): len = 451015, overlap = 183.312
+PHY-3002 : Step(120): len = 451112, overlap = 184.594
+PHY-3002 : Step(121): len = 451460, overlap = 192.844
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00015699
+PHY-3002 : Step(122): len = 463796, overlap = 194.312
+PHY-3002 : Step(123): len = 472366, overlap = 193.125
+PHY-3002 : Step(124): len = 471709, overlap = 202.188
+PHY-3002 : Step(125): len = 472971, overlap = 196.906
+PHY-3002 : Step(126): len = 474631, overlap = 184.719
+PHY-3002 : Step(127): len = 476408, overlap = 182.719
+PHY-3002 : Step(128): len = 475716, overlap = 180.531
+PHY-3002 : Step(129): len = 477959, overlap = 175.031
+PHY-3002 : Step(130): len = 479832, overlap = 171.906
+PHY-3002 : Step(131): len = 482054, overlap = 166.031
+PHY-3002 : Step(132): len = 480814, overlap = 170.594
+PHY-3002 : Step(133): len = 481389, overlap = 173.406
+PHY-3002 : Step(134): len = 482100, overlap = 163.531
+PHY-3002 : Step(135): len = 482420, overlap = 163.5
+PHY-3002 : Step(136): len = 480278, overlap = 163
+PHY-3002 : Step(137): len = 479836, overlap = 162.156
+PHY-3002 : Step(138): len = 479772, overlap = 159.281
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.00031398
+PHY-3002 : Step(139): len = 488301, overlap = 154.969
+PHY-3002 : Step(140): len = 497074, overlap = 138.125
+PHY-3002 : Step(141): len = 499730, overlap = 133.156
+PHY-3002 : Step(142): len = 502622, overlap = 125.562
+PHY-3002 : Step(143): len = 505297, overlap = 135.406
+PHY-3002 : Step(144): len = 506722, overlap = 134.594
+PHY-3002 : Step(145): len = 506509, overlap = 134.75
+PHY-3002 : Step(146): len = 507767, overlap = 141.156
+PHY-3002 : Step(147): len = 508594, overlap = 145
+PHY-3002 : Step(148): len = 509249, overlap = 131.844
+PHY-3002 : Step(149): len = 508910, overlap = 127.094
+PHY-3002 : Step(150): len = 508086, overlap = 140
+PHY-3002 : Step(151): len = 507568, overlap = 140.5
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000603832
+PHY-3002 : Step(152): len = 512576, overlap = 132.531
+PHY-3002 : Step(153): len = 516775, overlap = 132.938
+PHY-3002 : Step(154): len = 517743, overlap = 129.875
+PHY-3002 : Step(155): len = 518975, overlap = 126.5
+PHY-3002 : Step(156): len = 520798, overlap = 116.625
+PHY-3002 : Step(157): len = 522453, overlap = 120.5
+PHY-3002 : Step(158): len = 522116, overlap = 117.125
+PHY-3002 : Step(159): len = 522245, overlap = 113.438
+PHY-3002 : Step(160): len = 523708, overlap = 104.625
+PHY-3002 : Step(161): len = 525186, overlap = 99.4375
+PHY-3002 : Step(162): len = 524720, overlap = 103.531
+PHY-3002 : Step(163): len = 524790, overlap = 108.969
+PHY-3002 : Step(164): len = 525783, overlap = 108.594
+PHY-3002 : Step(165): len = 526195, overlap = 105.25
+PHY-3002 : Step(166): len = 525345, overlap = 104.5
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109199
+PHY-3002 : Step(167): len = 528017, overlap = 105.344
+PHY-3002 : Step(168): len = 531248, overlap = 99.9062
+PHY-3002 : Step(169): len = 532155, overlap = 99.1875
+PHY-3002 : Step(170): len = 533124, overlap = 101.156
+PHY-3002 : Step(171): len = 534345, overlap = 96.3438
+PHY-3002 : Step(172): len = 534791, overlap = 95.0625
+PHY-3002 : Step(173): len = 534321, overlap = 99.1875
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016695s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (93.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20376.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 674224, over cnt = 1414(4%), over = 6068, worst = 44
+PHY-1001 : End global iterations;  0.696541s wall, 0.796875s user + 0.031250s system = 0.828125s CPU (118.9%)
+
+PHY-1001 : Congestion index: top1 = 74.42, top5 = 56.98, top10 = 48.63, top15 = 43.51.
+PHY-3001 : End congestion estimation;  0.934540s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (115.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.111200s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.68539e-05
+PHY-3002 : Step(174): len = 630535, overlap = 56.2812
+PHY-3002 : Step(175): len = 664041, overlap = 66.0312
+PHY-3002 : Step(176): len = 658280, overlap = 68.1562
+PHY-3002 : Step(177): len = 655284, overlap = 68.9375
+PHY-3002 : Step(178): len = 653443, overlap = 70.125
+PHY-3002 : Step(179): len = 659309, overlap = 56.0625
+PHY-3002 : Step(180): len = 668471, overlap = 56.9062
+PHY-3002 : Step(181): len = 673343, overlap = 51.5312
+PHY-3002 : Step(182): len = 674702, overlap = 51.25
+PHY-3002 : Step(183): len = 682134, overlap = 58.0938
+PHY-3002 : Step(184): len = 679309, overlap = 61.125
+PHY-3002 : Step(185): len = 680020, overlap = 59.125
+PHY-3002 : Step(186): len = 676237, overlap = 61.9062
+PHY-3002 : Step(187): len = 673393, overlap = 67.0938
+PHY-3002 : Step(188): len = 670036, overlap = 72.5312
+PHY-3002 : Step(189): len = 667274, overlap = 75.875
+PHY-3002 : Step(190): len = 663925, overlap = 75.2812
+PHY-3002 : Step(191): len = 662377, overlap = 75.4062
+PHY-3002 : Step(192): len = 658065, overlap = 78.7812
+PHY-3002 : Step(193): len = 655793, overlap = 78.125
+PHY-3002 : Step(194): len = 653138, overlap = 78.6875
+PHY-3002 : Step(195): len = 651803, overlap = 80.0938
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000153708
+PHY-3002 : Step(196): len = 653163, overlap = 75.875
+PHY-3002 : Step(197): len = 656024, overlap = 74.1562
+PHY-3002 : Step(198): len = 662631, overlap = 70.375
+PHY-3002 : Step(199): len = 668278, overlap = 66.0625
+PHY-3002 : Step(200): len = 665722, overlap = 65.7188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000307416
+PHY-3002 : Step(201): len = 669902, overlap = 64.9062
+PHY-3002 : Step(202): len = 683661, overlap = 63
+PHY-3002 : Step(203): len = 687832, overlap = 62.0625
+PHY-3002 : Step(204): len = 692009, overlap = 62.25
+PHY-3002 : Step(205): len = 694333, overlap = 68.6562
+PHY-3002 : Step(206): len = 699202, overlap = 72.6562
+PHY-3002 : Step(207): len = 698326, overlap = 74.375
+PHY-3002 : Step(208): len = 699108, overlap = 71.3125
+PHY-3002 : Step(209): len = 697724, overlap = 67.5
+PHY-3002 : Step(210): len = 700422, overlap = 65.5625
+PHY-3002 : Step(211): len = 700142, overlap = 65.6875
+PHY-3002 : Step(212): len = 700366, overlap = 66.75
+PHY-3002 : Step(213): len = 700499, overlap = 64.0625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000544287
+PHY-3002 : Step(214): len = 703312, overlap = 65.7812
+PHY-3002 : Step(215): len = 705244, overlap = 63.8438
+PHY-3002 : Step(216): len = 716154, overlap = 65.6875
+PHY-3002 : Step(217): len = 726590, overlap = 64.8438
+PHY-3002 : Step(218): len = 731085, overlap = 66.125
+PHY-3002 : Step(219): len = 727562, overlap = 64.7812
+PHY-3002 : Step(220): len = 728760, overlap = 66.0938
+PHY-3002 : Step(221): len = 728583, overlap = 63.2812
+PHY-3002 : Step(222): len = 730813, overlap = 59.3125
+PHY-3002 : Step(223): len = 733684, overlap = 58.9062
+PHY-3002 : Step(224): len = 734748, overlap = 55.75
+PHY-3002 : Step(225): len = 739698, overlap = 58.0625
+PHY-3002 : Step(226): len = 742980, overlap = 59.8125
+PHY-3002 : Step(227): len = 746606, overlap = 57.625
+PHY-3002 : Step(228): len = 747032, overlap = 56.5625
+PHY-3002 : Step(229): len = 746338, overlap = 56.4375
+PHY-3002 : Step(230): len = 746798, overlap = 57.0312
+PHY-3002 : Step(231): len = 749780, overlap = 53.375
+PHY-3002 : Step(232): len = 750597, overlap = 55.875
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.000893488
+PHY-3002 : Step(233): len = 751369, overlap = 54.3125
+PHY-3002 : Step(234): len = 756707, overlap = 56.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 48/20376.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 818840, over cnt = 2467(7%), over = 13057, worst = 61
+PHY-1001 : End global iterations;  1.089055s wall, 1.546875s user + 0.000000s system = 1.546875s CPU (142.0%)
+
+PHY-1001 : Congestion index: top1 = 117.76, top5 = 80.63, top10 = 66.64, top15 = 58.71.
+PHY-3001 : End congestion estimation;  1.400223s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (133.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.896456s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.17101e-05
+PHY-3002 : Step(235): len = 757221, overlap = 305.562
+PHY-3002 : Step(236): len = 763042, overlap = 274.531
+PHY-3002 : Step(237): len = 750335, overlap = 233.312
+PHY-3002 : Step(238): len = 748777, overlap = 223.531
+PHY-3002 : Step(239): len = 736671, overlap = 215.531
+PHY-3002 : Step(240): len = 733943, overlap = 208.438
+PHY-3002 : Step(241): len = 726881, overlap = 212.906
+PHY-3002 : Step(242): len = 722813, overlap = 205.625
+PHY-3002 : Step(243): len = 718588, overlap = 200.938
+PHY-3002 : Step(244): len = 714053, overlap = 199.562
+PHY-3002 : Step(245): len = 711375, overlap = 201.25
+PHY-3002 : Step(246): len = 705603, overlap = 194.938
+PHY-3002 : Step(247): len = 702058, overlap = 195.906
+PHY-3002 : Step(248): len = 697450, overlap = 203.75
+PHY-3002 : Step(249): len = 694729, overlap = 222.562
+PHY-3002 : Step(250): len = 689099, overlap = 232.125
+PHY-3002 : Step(251): len = 685902, overlap = 235.344
+PHY-3002 : Step(252): len = 681853, overlap = 232.406
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00018342
+PHY-3002 : Step(253): len = 684255, overlap = 230.219
+PHY-3002 : Step(254): len = 685686, overlap = 227.125
+PHY-3002 : Step(255): len = 689093, overlap = 222.906
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000366841
+PHY-3002 : Step(256): len = 694473, overlap = 212.875
+PHY-3002 : Step(257): len = 705831, overlap = 197.312
+PHY-3002 : Step(258): len = 712265, overlap = 185.438
+PHY-3002 : Step(259): len = 710125, overlap = 188.906
+PHY-3002 : Step(260): len = 707754, overlap = 186.938
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000664255
+PHY-3002 : Step(261): len = 710457, overlap = 181.219
+PHY-3002 : Step(262): len = 714623, overlap = 177.281
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85409, tnet num: 20198, tinst num: 17799, tnode num: 115599, tedge num: 137148.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.477028s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.5%)
+
+RUN-1004 : used memory is 581 MB, reserved memory is 563 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 567.97 peak overflow 5.81
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 443/20376.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 791360, over cnt = 2859(8%), over = 11809, worst = 38
+PHY-1001 : End global iterations;  1.181647s wall, 1.671875s user + 0.015625s system = 1.687500s CPU (142.8%)
+
+PHY-1001 : Congestion index: top1 = 84.31, top5 = 66.36, top10 = 58.27, top15 = 53.19.
+PHY-1001 : End incremental global routing;  1.465932s wall, 1.953125s user + 0.015625s system = 1.968750s CPU (134.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.264327s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (100.1%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17668 has valid locations, 328 needs to be replaced
+PHY-3001 : design contains 18081 instances, 7576 luts, 9284 seqs, 1075 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6061 pins
+PHY-3001 : Found 3511 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735726
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15714/20658.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 806040, over cnt = 2910(8%), over = 11911, worst = 38
+PHY-1001 : End global iterations;  0.211561s wall, 0.296875s user + 0.031250s system = 0.328125s CPU (155.1%)
+
+PHY-1001 : Congestion index: top1 = 84.31, top5 = 66.35, top10 = 58.43, top15 = 53.39.
+PHY-3001 : End congestion estimation;  0.448261s wall, 0.546875s user + 0.031250s system = 0.578125s CPU (129.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86581, tnet num: 20480, tinst num: 18081, tnode num: 117421, tedge num: 138928.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.458706s wall, 1.390625s user + 0.062500s system = 1.453125s CPU (99.6%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 612 MB, peak memory is 721 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20480 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.405236s wall, 2.343750s user + 0.062500s system = 2.406250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(263): len = 734913, overlap = 3.78125
+PHY-3002 : Step(264): len = 734613, overlap = 4.21875
+PHY-3002 : Step(265): len = 734716, overlap = 4.65625
+PHY-3002 : Step(266): len = 735054, overlap = 4.65625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15757/20658.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 803664, over cnt = 2909(8%), over = 11894, worst = 38
+PHY-1001 : End global iterations;  0.198554s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (133.8%)
+
+PHY-1001 : Congestion index: top1 = 84.83, top5 = 66.74, top10 = 58.62, top15 = 53.50.
+PHY-3001 : End congestion estimation;  0.440099s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (113.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20480 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.105855s wall, 1.093750s user + 0.015625s system = 1.109375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000399943
+PHY-3002 : Step(267): len = 735035, overlap = 181.188
+PHY-3002 : Step(268): len = 735431, overlap = 180.625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000799886
+PHY-3002 : Step(269): len = 735753, overlap = 180.5
+PHY-3002 : Step(270): len = 736199, overlap = 180.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00126594
+PHY-3002 : Step(271): len = 736284, overlap = 181.25
+PHY-3002 : Step(272): len = 736631, overlap = 181.125
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00179003
+PHY-3002 : Step(273): len = 736988, overlap = 180.562
+PHY-3002 : Step(274): len = 737842, overlap = 180.469
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00289353
+PHY-3002 : Step(275): len = 738051, overlap = 180.656
+PHY-3002 : Step(276): len = 738536, overlap = 180.469
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 0.00409145
+PHY-3002 : Step(277): len = 738825, overlap = 180.125
+PHY-3002 : Step(278): len = 739374, overlap = 180.625
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 0.0057853
+PHY-3002 : Step(279): len = 739608, overlap = 180.781
+PHY-3002 : Step(280): len = 739955, overlap = 180.875
+PHY-3001 : Final: Len = 739955, Over = 180.875
+PHY-3001 : End incremental placement;  5.425432s wall, 5.656250s user + 0.328125s system = 5.984375s CPU (110.3%)
+
+OPT-1001 : Total overflow 575.50 peak overflow 5.81
+OPT-1001 : End high-fanout net optimization;  8.686524s wall, 9.515625s user + 0.343750s system = 9.859375s CPU (113.5%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15737/20658.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 810568, over cnt = 2858(8%), over = 11224, worst = 38
+PHY-1002 : len = 865224, over cnt = 2204(6%), over = 6263, worst = 38
+PHY-1002 : len = 911504, over cnt = 1040(2%), over = 2544, worst = 23
+PHY-1002 : len = 941632, over cnt = 265(0%), over = 564, worst = 19
+PHY-1002 : len = 951848, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.115760s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (126.3%)
+
+PHY-1001 : Congestion index: top1 = 64.27, top5 = 57.09, top10 = 53.05, top15 = 50.22.
+OPT-1001 : End congestion update;  2.363169s wall, 2.921875s user + 0.000000s system = 2.921875s CPU (123.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20480 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.797883s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS -4919 TNS -2642890 NUM_FEPS 1054
+OPT-0007 : Iter 1: improved WNS -4369 TNS -2557206 NUM_FEPS 1054 with 26 cells processed and 1300 slack improved
+OPT-0007 : Iter 2: improved WNS -4319 TNS -2544176 NUM_FEPS 1054 with 122 cells processed and 2500 slack improved
+OPT-0007 : Iter 3: improved WNS -4269 TNS -2538810 NUM_FEPS 1054 with 40 cells processed and 1200 slack improved
+OPT-0007 : Iter 4: improved WNS -4269 TNS -2538310 NUM_FEPS 1054 with 28 cells processed and 300 slack improved
+OPT-0007 : Iter 5: improved WNS -4069 TNS -2494592 NUM_FEPS 1054 with 2 cells processed and 400 slack improved
+OPT-0007 : Iter 6: improved WNS -4069 TNS -2493380 NUM_FEPS 1054 with 1 cells processed and 100 slack improved
+OPT-1001 : End bottleneck based optimization;  3.912879s wall, 4.468750s user + 0.000000s system = 4.468750s CPU (114.2%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 690, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15926/20661.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 954600, over cnt = 155(0%), over = 329, worst = 7
+PHY-1002 : len = 956016, over cnt = 105(0%), over = 144, worst = 5
+PHY-1002 : len = 957336, over cnt = 31(0%), over = 33, worst = 2
+PHY-1002 : len = 957712, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 958296, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.717101s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (106.8%)
+
+PHY-1001 : Congestion index: top1 = 64.35, top5 = 57.19, top10 = 53.17, top15 = 50.36.
+OPT-1001 : End congestion update;  0.969032s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (104.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20483 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.798312s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.8%)
+
+OPT-0007 : Start: WNS -4069 TNS -2493380 NUM_FEPS 1054
+OPT-0007 : Iter 1: improved WNS -4069 TNS -2493252 NUM_FEPS 1054 with 52 cells processed and 2350 slack improved
+OPT-0007 : Iter 2: improved WNS -4069 TNS -2493252 NUM_FEPS 1054 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.917119s wall, 1.953125s user + 0.000000s system = 1.953125s CPU (101.9%)
+
+OPT-1001 : Current memory(MB): used = 709, reserve = 696, peak = 743.
+OPT-1001 : End physical optimization;  16.293259s wall, 17.703125s user + 0.359375s system = 18.062500s CPU (110.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7576 LUT to BLE ...
+SYN-4008 : Packed 7576 LUT and 3126 SEQ to BLE.
+SYN-4003 : Packing 6161 remaining SEQ's ...
+SYN-4005 : Packed 3503 SEQ with LUT/SLICE
+SYN-4006 : 1255 single LUT's are left
+SYN-4006 : 2658 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10234/13981 primitive instances ...
+PHY-3001 : End packing;  1.635001s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.3%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6963 instances
+RUN-1001 : 3408 mslices, 3407 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17650 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 10034 nets have 2 pins
+RUN-1001 : 5748 nets have [3 - 5] pins
+RUN-1001 : 1170 nets have [6 - 10] pins
+RUN-1001 : 320 nets have [11 - 20] pins
+RUN-1001 : 345 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6961 instances, 6815 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3513 pins
+PHY-3001 : Found 1547 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 748314, Over = 382.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/I_fifo_wr_data[6] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7696/17650.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 897280, over cnt = 1845(5%), over = 3305, worst = 10
+PHY-1002 : len = 905016, over cnt = 1357(3%), over = 2037, worst = 10
+PHY-1002 : len = 923496, over cnt = 446(1%), over = 596, worst = 8
+PHY-1002 : len = 930696, over cnt = 138(0%), over = 162, worst = 3
+PHY-1002 : len = 935560, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.754625s wall, 2.156250s user + 0.062500s system = 2.218750s CPU (126.5%)
+
+PHY-1001 : Congestion index: top1 = 65.71, top5 = 56.86, top10 = 52.31, top15 = 49.36.
+PHY-3001 : End congestion estimation;  2.115855s wall, 2.500000s user + 0.062500s system = 2.562500s CPU (121.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74280, tnet num: 17472, tinst num: 6961, tnode num: 96627, tedge num: 124765.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.681216s wall, 1.671875s user + 0.015625s system = 1.687500s CPU (100.4%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 616 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17472 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.556275s wall, 2.531250s user + 0.031250s system = 2.562500s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.45619e-05
+PHY-3002 : Step(281): len = 734866, overlap = 377.75
+PHY-3002 : Step(282): len = 725806, overlap = 382.25
+PHY-3002 : Step(283): len = 719634, overlap = 383.75
+PHY-3002 : Step(284): len = 715367, overlap = 392.25
+PHY-3002 : Step(285): len = 710425, overlap = 397.5
+PHY-3002 : Step(286): len = 705331, overlap = 393.25
+PHY-3002 : Step(287): len = 701525, overlap = 392
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.91239e-05
+PHY-3002 : Step(288): len = 707236, overlap = 379.25
+PHY-3002 : Step(289): len = 711713, overlap = 374
+PHY-3002 : Step(290): len = 709550, overlap = 374.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000178248
+PHY-3002 : Step(291): len = 722931, overlap = 362
+PHY-3002 : Step(292): len = 735522, overlap = 339.5
+PHY-3002 : Step(293): len = 732224, overlap = 336.25
+PHY-3002 : Step(294): len = 730232, overlap = 337.75
+PHY-3002 : Step(295): len = 731149, overlap = 337.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000304517
+PHY-3002 : Step(296): len = 740122, overlap = 328
+PHY-3002 : Step(297): len = 746812, overlap = 318.75
+PHY-3002 : Step(298): len = 755146, overlap = 303.25
+PHY-3001 : Legalization ...
+PHY-9048 ERROR: Legalize hard bound bound3 failed due to insufficient space.
+PHY-9042 ERROR: Legalize MSLICE failed.
+RUN-1003 : finish command "place" in  42.443374s wall, 71.656250s user + 5.390625s system = 77.046875s CPU (181.5%)
+
+RUN-1004 : used memory is 551 MB, reserved memory is 556 MB, peak memory is 743 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_112841.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_113113.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_113113.log
new file mode 100644
index 0000000..a40f11c
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_113113.log
@@ -0,0 +1,2156 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:31:13 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.157536s wall, 2.046875s user + 0.109375s system = 2.156250s CPU (99.9%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 315 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing ultra"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   ultra    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2213 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17801 instances
+RUN-0007 : 7499 luts, 9079 seqs, 702 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20376 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13426 nets have 2 pins
+RUN-1001 : 5469 nets have [3 - 5] pins
+RUN-1001 : 1069 nets have [6 - 10] pins
+RUN-1001 : 167 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     789     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3483     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     58     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 143
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17799 instances, 7499 luts, 9079 seqs, 1075 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5931 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85409, tnet num: 20198, tinst num: 17799, tnode num: 115599, tedge num: 137148.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.147534s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (100.8%)
+
+RUN-1004 : used memory is 539 MB, reserved memory is 515 MB, peak memory is 539 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.935851s wall, 1.890625s user + 0.046875s system = 1.937500s CPU (100.1%)
+
+PHY-3001 : Found 1224 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.04955e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17799.
+PHY-3001 : Level 1 #clusters 2339.
+PHY-3001 : End clustering;  0.125581s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (124.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35768e+06, overlap = 476.625
+PHY-3002 : Step(2): len = 1.10868e+06, overlap = 552.719
+PHY-3002 : Step(3): len = 893871, overlap = 634.031
+PHY-3002 : Step(4): len = 804745, overlap = 650.375
+PHY-3002 : Step(5): len = 628334, overlap = 831.812
+PHY-3002 : Step(6): len = 559094, overlap = 870.312
+PHY-3002 : Step(7): len = 458178, overlap = 950.562
+PHY-3002 : Step(8): len = 422259, overlap = 991.406
+PHY-3002 : Step(9): len = 375575, overlap = 1058.53
+PHY-3002 : Step(10): len = 341933, overlap = 1105.72
+PHY-3002 : Step(11): len = 313396, overlap = 1141.28
+PHY-3002 : Step(12): len = 283820, overlap = 1203.66
+PHY-3002 : Step(13): len = 264693, overlap = 1246.16
+PHY-3002 : Step(14): len = 240674, overlap = 1302.97
+PHY-3002 : Step(15): len = 225358, overlap = 1309.5
+PHY-3002 : Step(16): len = 208553, overlap = 1347.44
+PHY-3002 : Step(17): len = 195786, overlap = 1369.28
+PHY-3002 : Step(18): len = 185351, overlap = 1410.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.61073e-07
+PHY-3002 : Step(19): len = 186879, overlap = 1366.09
+PHY-3002 : Step(20): len = 215082, overlap = 1306.91
+PHY-3002 : Step(21): len = 219582, overlap = 1262.81
+PHY-3002 : Step(22): len = 225190, overlap = 1224.22
+PHY-3002 : Step(23): len = 219802, overlap = 1225.81
+PHY-3002 : Step(24): len = 217854, overlap = 1195.69
+PHY-3002 : Step(25): len = 211914, overlap = 1180.91
+PHY-3002 : Step(26): len = 210031, overlap = 1160.62
+PHY-3002 : Step(27): len = 204368, overlap = 1131.09
+PHY-3002 : Step(28): len = 203167, overlap = 1118.31
+PHY-3002 : Step(29): len = 197595, overlap = 1111.03
+PHY-3002 : Step(30): len = 197391, overlap = 1113.84
+PHY-3002 : Step(31): len = 194025, overlap = 1113.56
+PHY-3002 : Step(32): len = 194079, overlap = 1102.88
+PHY-3002 : Step(33): len = 191574, overlap = 1114.81
+PHY-3002 : Step(34): len = 191025, overlap = 1107.91
+PHY-3002 : Step(35): len = 188622, overlap = 1121
+PHY-3002 : Step(36): len = 189344, overlap = 1135.28
+PHY-3002 : Step(37): len = 188147, overlap = 1128.06
+PHY-3002 : Step(38): len = 188324, overlap = 1115.38
+PHY-3002 : Step(39): len = 185036, overlap = 1126.22
+PHY-3002 : Step(40): len = 185238, overlap = 1123.72
+PHY-3002 : Step(41): len = 182928, overlap = 1124.91
+PHY-3002 : Step(42): len = 183704, overlap = 1117.56
+PHY-3002 : Step(43): len = 181203, overlap = 1118.06
+PHY-3002 : Step(44): len = 181612, overlap = 1088.16
+PHY-3002 : Step(45): len = 179888, overlap = 1099.53
+PHY-3002 : Step(46): len = 180181, overlap = 1088.56
+PHY-3002 : Step(47): len = 176939, overlap = 1075.31
+PHY-3002 : Step(48): len = 176292, overlap = 1087.75
+PHY-3002 : Step(49): len = 174197, overlap = 1096.12
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.92215e-06
+PHY-3002 : Step(50): len = 177113, overlap = 1084.16
+PHY-3002 : Step(51): len = 189655, overlap = 1043.38
+PHY-3002 : Step(52): len = 197256, overlap = 977.969
+PHY-3002 : Step(53): len = 202184, overlap = 930.406
+PHY-3002 : Step(54): len = 203129, overlap = 912.344
+PHY-3002 : Step(55): len = 204410, overlap = 905.281
+PHY-3002 : Step(56): len = 203207, overlap = 908.781
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.84429e-06
+PHY-3002 : Step(57): len = 212660, overlap = 897.469
+PHY-3002 : Step(58): len = 234427, overlap = 859.594
+PHY-3002 : Step(59): len = 243584, overlap = 813.781
+PHY-3002 : Step(60): len = 247810, overlap = 747.156
+PHY-3002 : Step(61): len = 246675, overlap = 732.688
+PHY-3002 : Step(62): len = 247151, overlap = 749.281
+PHY-3002 : Step(63): len = 245021, overlap = 741.125
+PHY-3002 : Step(64): len = 244214, overlap = 741.312
+PHY-3002 : Step(65): len = 241523, overlap = 744.688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.68858e-06
+PHY-3002 : Step(66): len = 257519, overlap = 709.531
+PHY-3002 : Step(67): len = 275098, overlap = 635.25
+PHY-3002 : Step(68): len = 281782, overlap = 615.375
+PHY-3002 : Step(69): len = 284468, overlap = 612.375
+PHY-3002 : Step(70): len = 285401, overlap = 613.781
+PHY-3002 : Step(71): len = 285824, overlap = 613.812
+PHY-3002 : Step(72): len = 284999, overlap = 617.438
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.53772e-05
+PHY-3002 : Step(73): len = 305069, overlap = 570.312
+PHY-3002 : Step(74): len = 323626, overlap = 539.281
+PHY-3002 : Step(75): len = 330895, overlap = 504.625
+PHY-3002 : Step(76): len = 333063, overlap = 486.219
+PHY-3002 : Step(77): len = 333037, overlap = 477.094
+PHY-3002 : Step(78): len = 332612, overlap = 480.656
+PHY-3002 : Step(79): len = 332486, overlap = 479.375
+PHY-3002 : Step(80): len = 334709, overlap = 466.469
+PHY-3002 : Step(81): len = 335106, overlap = 458.312
+PHY-3002 : Step(82): len = 335450, overlap = 445.938
+PHY-3002 : Step(83): len = 335499, overlap = 429
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.07543e-05
+PHY-3002 : Step(84): len = 354274, overlap = 396.031
+PHY-3002 : Step(85): len = 369459, overlap = 360.188
+PHY-3002 : Step(86): len = 375144, overlap = 327.75
+PHY-3002 : Step(87): len = 378581, overlap = 314.438
+PHY-3002 : Step(88): len = 379042, overlap = 291.781
+PHY-3002 : Step(89): len = 382427, overlap = 286.75
+PHY-3002 : Step(90): len = 381542, overlap = 274.875
+PHY-3002 : Step(91): len = 383368, overlap = 278.031
+PHY-3002 : Step(92): len = 383780, overlap = 288.562
+PHY-3002 : Step(93): len = 383722, overlap = 287.25
+PHY-3002 : Step(94): len = 382846, overlap = 293.094
+PHY-3002 : Step(95): len = 384308, overlap = 289.188
+PHY-3002 : Step(96): len = 384391, overlap = 292.188
+PHY-3002 : Step(97): len = 385365, overlap = 290.406
+PHY-3002 : Step(98): len = 383551, overlap = 295.156
+PHY-3002 : Step(99): len = 383774, overlap = 291.156
+PHY-3002 : Step(100): len = 382987, overlap = 293.188
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.15087e-05
+PHY-3002 : Step(101): len = 403417, overlap = 288.562
+PHY-3002 : Step(102): len = 417090, overlap = 259.25
+PHY-3002 : Step(103): len = 417531, overlap = 238.406
+PHY-3002 : Step(104): len = 418668, overlap = 228.25
+PHY-3002 : Step(105): len = 420647, overlap = 199.75
+PHY-3002 : Step(106): len = 424140, overlap = 198.625
+PHY-3002 : Step(107): len = 424244, overlap = 210.781
+PHY-3002 : Step(108): len = 426696, overlap = 212.656
+PHY-3002 : Step(109): len = 426898, overlap = 214.5
+PHY-3002 : Step(110): len = 427846, overlap = 208.406
+PHY-3002 : Step(111): len = 426632, overlap = 207.562
+PHY-3002 : Step(112): len = 426247, overlap = 206.844
+PHY-3002 : Step(113): len = 425976, overlap = 210.531
+PHY-3002 : Step(114): len = 426017, overlap = 219
+PHY-3002 : Step(115): len = 424546, overlap = 210.656
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000123017
+PHY-3002 : Step(116): len = 439604, overlap = 214.25
+PHY-3002 : Step(117): len = 450020, overlap = 196.5
+PHY-3002 : Step(118): len = 449676, overlap = 189.469
+PHY-3002 : Step(119): len = 450763, overlap = 178.844
+PHY-3002 : Step(120): len = 452436, overlap = 188.875
+PHY-3002 : Step(121): len = 455497, overlap = 179.906
+PHY-3002 : Step(122): len = 455234, overlap = 175.969
+PHY-3002 : Step(123): len = 457905, overlap = 160.75
+PHY-3002 : Step(124): len = 459436, overlap = 155.594
+PHY-3002 : Step(125): len = 461005, overlap = 149.094
+PHY-3002 : Step(126): len = 458554, overlap = 149.688
+PHY-3002 : Step(127): len = 458676, overlap = 154.75
+PHY-3002 : Step(128): len = 459159, overlap = 164.594
+PHY-3002 : Step(129): len = 460743, overlap = 165.938
+PHY-3002 : Step(130): len = 458323, overlap = 163.188
+PHY-3002 : Step(131): len = 458592, overlap = 166.5
+PHY-3002 : Step(132): len = 459659, overlap = 165.438
+PHY-3002 : Step(133): len = 460624, overlap = 162.156
+PHY-3002 : Step(134): len = 459269, overlap = 164.125
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000234577
+PHY-3002 : Step(135): len = 468618, overlap = 170.219
+PHY-3002 : Step(136): len = 477598, overlap = 166.812
+PHY-3002 : Step(137): len = 479400, overlap = 163.094
+PHY-3002 : Step(138): len = 480424, overlap = 151.062
+PHY-3002 : Step(139): len = 482002, overlap = 150.656
+PHY-3002 : Step(140): len = 483284, overlap = 152.594
+PHY-3002 : Step(141): len = 483029, overlap = 150.656
+PHY-3002 : Step(142): len = 484751, overlap = 154.156
+PHY-3002 : Step(143): len = 485882, overlap = 156.594
+PHY-3002 : Step(144): len = 486801, overlap = 157.25
+PHY-3002 : Step(145): len = 486118, overlap = 155.031
+PHY-3002 : Step(146): len = 486237, overlap = 156.25
+PHY-3002 : Step(147): len = 486923, overlap = 158.969
+PHY-3002 : Step(148): len = 488261, overlap = 159.531
+PHY-3002 : Step(149): len = 487645, overlap = 158.219
+PHY-3002 : Step(150): len = 488003, overlap = 156.719
+PHY-3002 : Step(151): len = 488481, overlap = 157.375
+PHY-3002 : Step(152): len = 489167, overlap = 155.625
+PHY-3002 : Step(153): len = 488628, overlap = 152.156
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000419978
+PHY-3002 : Step(154): len = 495043, overlap = 151.125
+PHY-3002 : Step(155): len = 502875, overlap = 147.844
+PHY-3002 : Step(156): len = 505306, overlap = 144.125
+PHY-3002 : Step(157): len = 506978, overlap = 138.844
+PHY-3002 : Step(158): len = 509241, overlap = 135.469
+PHY-3002 : Step(159): len = 510566, overlap = 132.781
+PHY-3002 : Step(160): len = 509484, overlap = 131.781
+PHY-3002 : Step(161): len = 509498, overlap = 132.281
+PHY-3002 : Step(162): len = 511261, overlap = 126.406
+PHY-3002 : Step(163): len = 511729, overlap = 126.094
+PHY-3002 : Step(164): len = 511032, overlap = 126.219
+PHY-3002 : Step(165): len = 510889, overlap = 123.031
+PHY-3002 : Step(166): len = 512565, overlap = 117.812
+PHY-3002 : Step(167): len = 515366, overlap = 125.062
+PHY-3002 : Step(168): len = 514143, overlap = 129.5
+PHY-3002 : Step(169): len = 513803, overlap = 136.281
+PHY-3002 : Step(170): len = 514339, overlap = 137.656
+PHY-3002 : Step(171): len = 515095, overlap = 136.188
+PHY-3002 : Step(172): len = 514414, overlap = 136.5
+PHY-3002 : Step(173): len = 514335, overlap = 134.219
+PHY-3002 : Step(174): len = 515672, overlap = 128.594
+PHY-3002 : Step(175): len = 516941, overlap = 125.5
+PHY-3002 : Step(176): len = 515797, overlap = 126.656
+PHY-3002 : Step(177): len = 515392, overlap = 127.969
+PHY-3002 : Step(178): len = 516075, overlap = 126.188
+PHY-3002 : Step(179): len = 516886, overlap = 127.906
+PHY-3002 : Step(180): len = 515937, overlap = 128.5
+PHY-3002 : Step(181): len = 515795, overlap = 129.281
+PHY-3002 : Step(182): len = 516163, overlap = 122.656
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000824874
+PHY-3002 : Step(183): len = 521737, overlap = 116.438
+PHY-3002 : Step(184): len = 529537, overlap = 112.562
+PHY-3002 : Step(185): len = 532365, overlap = 113.562
+PHY-3002 : Step(186): len = 534536, overlap = 114.125
+PHY-3002 : Step(187): len = 536443, overlap = 114.844
+PHY-3002 : Step(188): len = 537532, overlap = 116.344
+PHY-3002 : Step(189): len = 537374, overlap = 116.812
+PHY-3002 : Step(190): len = 537509, overlap = 112.344
+PHY-3002 : Step(191): len = 537558, overlap = 111.438
+PHY-3002 : Step(192): len = 537400, overlap = 114.719
+PHY-3002 : Step(193): len = 536776, overlap = 113.844
+PHY-3002 : Step(194): len = 536562, overlap = 112.969
+PHY-3002 : Step(195): len = 536802, overlap = 114.688
+PHY-3002 : Step(196): len = 536980, overlap = 114.844
+PHY-3002 : Step(197): len = 536859, overlap = 115.312
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00152144
+PHY-3002 : Step(198): len = 540334, overlap = 113.656
+PHY-3002 : Step(199): len = 547293, overlap = 112.688
+PHY-3002 : Step(200): len = 549554, overlap = 107.656
+PHY-3002 : Step(201): len = 551295, overlap = 105.531
+PHY-3002 : Step(202): len = 552767, overlap = 109.156
+PHY-3002 : Step(203): len = 553871, overlap = 113.031
+PHY-3002 : Step(204): len = 554187, overlap = 103.594
+PHY-3002 : Step(205): len = 554508, overlap = 100.344
+PHY-3002 : Step(206): len = 555396, overlap = 105.094
+PHY-3002 : Step(207): len = 555961, overlap = 101.594
+PHY-3002 : Step(208): len = 555626, overlap = 101.156
+PHY-3002 : Step(209): len = 555431, overlap = 100.906
+PHY-3002 : Step(210): len = 555458, overlap = 100.594
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00284126
+PHY-3002 : Step(211): len = 557273, overlap = 100.688
+PHY-3002 : Step(212): len = 561671, overlap = 99.6562
+PHY-3002 : Step(213): len = 563603, overlap = 98.0625
+PHY-3002 : Step(214): len = 565841, overlap = 97.5312
+PHY-3002 : Step(215): len = 567161, overlap = 96.0312
+PHY-3002 : Step(216): len = 568185, overlap = 96.0312
+PHY-3002 : Step(217): len = 568680, overlap = 96.375
+PHY-3002 : Step(218): len = 568866, overlap = 96.6875
+PHY-3002 : Step(219): len = 569040, overlap = 95.375
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016875s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (92.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20376.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724112, over cnt = 1466(4%), over = 6273, worst = 41
+PHY-1001 : End global iterations;  0.758018s wall, 0.921875s user + 0.046875s system = 0.968750s CPU (127.8%)
+
+PHY-1001 : Congestion index: top1 = 75.09, top5 = 56.95, top10 = 48.97, top15 = 44.04.
+PHY-3001 : End congestion estimation;  0.988898s wall, 1.140625s user + 0.046875s system = 1.187500s CPU (120.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.895358s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (101.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000127071
+PHY-3002 : Step(220): len = 653075, overlap = 56.625
+PHY-3002 : Step(221): len = 659190, overlap = 42.0938
+PHY-3002 : Step(222): len = 644589, overlap = 36.2188
+PHY-3002 : Step(223): len = 637712, overlap = 39.3125
+PHY-3002 : Step(224): len = 634039, overlap = 38.5625
+PHY-3002 : Step(225): len = 632376, overlap = 36.6562
+PHY-3002 : Step(226): len = 625725, overlap = 39.6875
+PHY-3002 : Step(227): len = 617761, overlap = 38.6562
+PHY-3002 : Step(228): len = 613545, overlap = 34.875
+PHY-3002 : Step(229): len = 610165, overlap = 32.9375
+PHY-3002 : Step(230): len = 605496, overlap = 36.5625
+PHY-3002 : Step(231): len = 603271, overlap = 41.25
+PHY-3002 : Step(232): len = 600182, overlap = 39.5938
+PHY-3002 : Step(233): len = 596667, overlap = 38.7188
+PHY-3002 : Step(234): len = 593771, overlap = 37.625
+PHY-3002 : Step(235): len = 592648, overlap = 39.5
+PHY-3002 : Step(236): len = 589548, overlap = 38.75
+PHY-3002 : Step(237): len = 589045, overlap = 38.7812
+PHY-3002 : Step(238): len = 585581, overlap = 40.0625
+PHY-3002 : Step(239): len = 584275, overlap = 40.6562
+PHY-3002 : Step(240): len = 582845, overlap = 44.8438
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000254142
+PHY-3002 : Step(241): len = 583977, overlap = 45.5312
+PHY-3002 : Step(242): len = 586957, overlap = 45.5312
+PHY-3002 : Step(243): len = 594107, overlap = 46.0938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000508284
+PHY-3002 : Step(244): len = 604520, overlap = 40.3438
+PHY-3002 : Step(245): len = 617191, overlap = 30.6875
+PHY-3002 : Step(246): len = 630304, overlap = 31.3125
+PHY-3002 : Step(247): len = 628708, overlap = 32.4062
+PHY-3002 : Step(248): len = 626101, overlap = 32.7188
+PHY-3002 : Step(249): len = 625574, overlap = 37.875
+PHY-3002 : Step(250): len = 625116, overlap = 42.6562
+PHY-3002 : Step(251): len = 626148, overlap = 39.7812
+PHY-3002 : Step(252): len = 627858, overlap = 40.5312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00101657
+PHY-3002 : Step(253): len = 634758, overlap = 40.7812
+PHY-3002 : Step(254): len = 646366, overlap = 42.8438
+PHY-3002 : Step(255): len = 651269, overlap = 43
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00166892
+PHY-3002 : Step(256): len = 653668, overlap = 43.1875
+PHY-3002 : Step(257): len = 664513, overlap = 41.9688
+PHY-3002 : Step(258): len = 675403, overlap = 45.9688
+PHY-3002 : Step(259): len = 680971, overlap = 46.7188
+PHY-3002 : Step(260): len = 682711, overlap = 44.625
+PHY-3002 : Step(261): len = 684701, overlap = 40.1875
+PHY-3002 : Step(262): len = 684911, overlap = 35.125
+PHY-3002 : Step(263): len = 683198, overlap = 32.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 61/20376.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 761728, over cnt = 2579(7%), over = 11988, worst = 49
+PHY-1001 : End global iterations;  1.374300s wall, 1.953125s user + 0.031250s system = 1.984375s CPU (144.4%)
+
+PHY-1001 : Congestion index: top1 = 94.70, top5 = 70.88, top10 = 61.20, top15 = 55.39.
+PHY-3001 : End congestion estimation;  1.654932s wall, 2.234375s user + 0.031250s system = 2.265625s CPU (136.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.443842s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000132141
+PHY-3002 : Step(264): len = 666352, overlap = 260.562
+PHY-3002 : Step(265): len = 658395, overlap = 208.875
+PHY-3002 : Step(266): len = 639184, overlap = 180.312
+PHY-3002 : Step(267): len = 628915, overlap = 165.219
+PHY-3002 : Step(268): len = 616639, overlap = 164.031
+PHY-3002 : Step(269): len = 611078, overlap = 164.344
+PHY-3002 : Step(270): len = 602072, overlap = 172.969
+PHY-3002 : Step(271): len = 598299, overlap = 171
+PHY-3002 : Step(272): len = 593984, overlap = 169.531
+PHY-3002 : Step(273): len = 587875, overlap = 174.5
+PHY-3002 : Step(274): len = 584566, overlap = 176.625
+PHY-3002 : Step(275): len = 582968, overlap = 177.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000264283
+PHY-3002 : Step(276): len = 581808, overlap = 171.375
+PHY-3002 : Step(277): len = 585068, overlap = 167.094
+PHY-3002 : Step(278): len = 587974, overlap = 160.406
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000528566
+PHY-3002 : Step(279): len = 590047, overlap = 151.594
+PHY-3002 : Step(280): len = 596028, overlap = 141.938
+PHY-3002 : Step(281): len = 601530, overlap = 139.719
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00105713
+PHY-3002 : Step(282): len = 604081, overlap = 133.625
+PHY-3002 : Step(283): len = 611916, overlap = 128.75
+PHY-3002 : Step(284): len = 617631, overlap = 126.438
+PHY-3002 : Step(285): len = 621711, overlap = 122.969
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00175153
+PHY-3002 : Step(286): len = 623440, overlap = 121.688
+PHY-3002 : Step(287): len = 625961, overlap = 121.469
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85409, tnet num: 20198, tinst num: 17799, tnode num: 115599, tedge num: 137148.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.552623s wall, 1.531250s user + 0.031250s system = 1.562500s CPU (100.6%)
+
+RUN-1004 : used memory is 584 MB, reserved memory is 565 MB, peak memory is 720 MB
+OPT-1001 : Total overflow 496.41 peak overflow 4.81
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 429/20376.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 717896, over cnt = 2834(8%), over = 10497, worst = 27
+PHY-1001 : End global iterations;  1.271502s wall, 1.890625s user + 0.015625s system = 1.906250s CPU (149.9%)
+
+PHY-1001 : Congestion index: top1 = 70.02, top5 = 56.85, top10 = 50.74, top15 = 46.95.
+PHY-1001 : End incremental global routing;  1.588130s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (138.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20198 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.906880s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.9%)
+
+OPT-1001 : 46 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17668 has valid locations, 363 needs to be replaced
+PHY-3001 : design contains 18116 instances, 7581 luts, 9314 seqs, 1075 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6049 pins
+PHY-3001 : Found 1234 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 650580
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16196/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736752, over cnt = 2889(8%), over = 10616, worst = 26
+PHY-1001 : End global iterations;  0.227458s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (116.8%)
+
+PHY-1001 : Congestion index: top1 = 69.44, top5 = 56.96, top10 = 50.89, top15 = 47.19.
+PHY-3001 : End congestion estimation;  0.478673s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (111.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86728, tnet num: 20515, tinst num: 18116, tnode num: 117662, tedge num: 139152.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.470326s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 628 MB, reserved memory is 615 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.427803s wall, 2.375000s user + 0.046875s system = 2.421875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(288): len = 649543, overlap = 0.375
+PHY-3002 : Step(289): len = 649994, overlap = 0.375
+PHY-3002 : Step(290): len = 650040, overlap = 0.3125
+PHY-3002 : Step(291): len = 650179, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16265/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733408, over cnt = 2896(8%), over = 10666, worst = 26
+PHY-1001 : End global iterations;  0.204755s wall, 0.234375s user + 0.046875s system = 0.281250s CPU (137.4%)
+
+PHY-1001 : Congestion index: top1 = 69.70, top5 = 57.26, top10 = 51.16, top15 = 47.45.
+PHY-3001 : End congestion estimation;  0.469256s wall, 0.500000s user + 0.046875s system = 0.546875s CPU (116.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.952884s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000382199
+PHY-3002 : Step(292): len = 650303, overlap = 124.844
+PHY-3002 : Step(293): len = 650730, overlap = 125.031
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000764398
+PHY-3002 : Step(294): len = 651035, overlap = 124.375
+PHY-3002 : Step(295): len = 651421, overlap = 124.375
+PHY-3001 : Final: Len = 651421, Over = 124.375
+PHY-3001 : End incremental placement;  5.006260s wall, 5.328125s user + 0.156250s system = 5.484375s CPU (109.6%)
+
+OPT-1001 : Total overflow 503.22 peak overflow 4.94
+OPT-1001 : End high-fanout net optimization;  8.034588s wall, 9.046875s user + 0.203125s system = 9.250000s CPU (115.1%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 745.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16252/20693.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736944, over cnt = 2848(8%), over = 9747, worst = 26
+PHY-1002 : len = 772952, over cnt = 2155(6%), over = 6029, worst = 19
+PHY-1002 : len = 818984, over cnt = 1054(2%), over = 2599, worst = 19
+PHY-1002 : len = 849936, over cnt = 228(0%), over = 472, worst = 13
+PHY-1002 : len = 857472, over cnt = 4(0%), over = 4, worst = 1
+PHY-1001 : End global iterations;  1.963974s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (120.1%)
+
+PHY-1001 : Congestion index: top1 = 56.68, top5 = 49.85, top10 = 46.18, top15 = 43.73.
+OPT-1001 : End congestion update;  2.225335s wall, 2.609375s user + 0.000000s system = 2.609375s CPU (117.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20515 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.799379s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.7%)
+
+OPT-0007 : Start: WNS -4319 TNS -2490228 NUM_FEPS 1060
+OPT-0007 : Iter 1: improved WNS -4219 TNS -2482204 NUM_FEPS 1060 with 123 cells processed and 2924 slack improved
+OPT-0007 : Iter 2: improved WNS -4193 TNS -2479808 NUM_FEPS 1060 with 50 cells processed and 726 slack improved
+OPT-0007 : Iter 3: improved WNS -4169 TNS -2479372 NUM_FEPS 1060 with 27 cells processed and 498 slack improved
+OPT-0007 : Iter 4: improved WNS -4169 TNS -2479152 NUM_FEPS 1060 with 24 cells processed and 426 slack improved
+OPT-0007 : Iter 5: improved WNS -4169 TNS -2479152 NUM_FEPS 1060 with 3 cells processed and 0 slack improved
+OPT-0007 : Iter 6: improved WNS -3969 TNS -2452202 NUM_FEPS 1060 with 1 cells processed and 200 slack improved
+OPT-0007 : Iter 7: improved WNS -3969 TNS -2449838 NUM_FEPS 1060 with 2 cells processed and 350 slack improved
+OPT-1001 : End bottleneck based optimization;  3.864305s wall, 4.250000s user + 0.000000s system = 4.250000s CPU (110.0%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 697, peak = 745.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16465/20696.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861080, over cnt = 186(0%), over = 300, worst = 7
+PHY-1002 : len = 861816, over cnt = 119(0%), over = 145, worst = 4
+PHY-1002 : len = 862696, over cnt = 70(0%), over = 82, worst = 3
+PHY-1002 : len = 863616, over cnt = 22(0%), over = 22, worst = 1
+PHY-1002 : len = 864264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.718345s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (117.5%)
+
+PHY-1001 : Congestion index: top1 = 56.90, top5 = 49.89, top10 = 46.30, top15 = 43.85.
+OPT-1001 : End congestion update;  0.982261s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (112.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20518 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.797825s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS -3969 TNS -2449838 NUM_FEPS 1060
+OPT-0007 : Iter 1: improved WNS -3919 TNS -2446852 NUM_FEPS 1060 with 46 cells processed and 2450 slack improved
+OPT-0007 : Iter 2: improved WNS -3919 TNS -2446852 NUM_FEPS 1060 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.922623s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (106.5%)
+
+OPT-1001 : Current memory(MB): used = 716, reserve = 702, peak = 745.
+OPT-1001 : End physical optimization;  15.676996s wall, 17.156250s user + 0.281250s system = 17.437500s CPU (111.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7581 LUT to BLE ...
+SYN-4008 : Packed 7581 LUT and 3128 SEQ to BLE.
+SYN-4003 : Packing 6189 remaining SEQ's ...
+SYN-4005 : Packed 3887 SEQ with LUT/SLICE
+SYN-4006 : 887 single LUT's are left
+SYN-4006 : 2302 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9883/13630 primitive instances ...
+PHY-3001 : End packing;  1.624704s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6889 instances
+RUN-1001 : 3371 mslices, 3370 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17685 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9995 nets have 2 pins
+RUN-1001 : 5771 nets have [3 - 5] pins
+RUN-1001 : 1193 nets have [6 - 10] pins
+RUN-1001 : 371 nets have [11 - 20] pins
+RUN-1001 : 322 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6887 instances, 6741 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3601 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 657677, Over = 301.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7532/17685.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808040, over cnt = 1851(5%), over = 3114, worst = 9
+PHY-1002 : len = 816864, over cnt = 1149(3%), over = 1658, worst = 9
+PHY-1002 : len = 832408, over cnt = 338(0%), over = 457, worst = 7
+PHY-1002 : len = 838968, over cnt = 75(0%), over = 93, worst = 5
+PHY-1002 : len = 841736, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations;  1.598696s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (144.6%)
+
+PHY-1001 : Congestion index: top1 = 58.62, top5 = 50.46, top10 = 46.40, top15 = 43.79.
+PHY-3001 : End congestion estimation;  1.994534s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (135.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74849, tnet num: 17507, tinst num: 6887, tnode num: 97605, tedge num: 125692.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.662483s wall, 1.625000s user + 0.046875s system = 1.671875s CPU (100.6%)
+
+RUN-1004 : used memory is 625 MB, reserved memory is 618 MB, peak memory is 745 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17507 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.553708s wall, 2.500000s user + 0.046875s system = 2.546875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.85456e-05
+PHY-3002 : Step(296): len = 639075, overlap = 309
+PHY-3002 : Step(297): len = 628066, overlap = 314.75
+PHY-3002 : Step(298): len = 621550, overlap = 317
+PHY-3002 : Step(299): len = 617892, overlap = 333
+PHY-3002 : Step(300): len = 615697, overlap = 341.75
+PHY-3002 : Step(301): len = 612645, overlap = 331.5
+PHY-3002 : Step(302): len = 610219, overlap = 331.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000117091
+PHY-3002 : Step(303): len = 614982, overlap = 323
+PHY-3002 : Step(304): len = 619127, overlap = 314.25
+PHY-3002 : Step(305): len = 618267, overlap = 315
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000234183
+PHY-3002 : Step(306): len = 626628, overlap = 298.75
+PHY-3002 : Step(307): len = 636591, overlap = 297.25
+PHY-3002 : Step(308): len = 637209, overlap = 296.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.306986s wall, 0.281250s user + 0.515625s system = 0.796875s CPU (259.6%)
+
+PHY-3001 : Trial Legalized: Len = 740449
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 654/17685.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855648, over cnt = 2712(7%), over = 4643, worst = 7
+PHY-1002 : len = 870056, over cnt = 1794(5%), over = 2788, worst = 7
+PHY-1002 : len = 889128, over cnt = 870(2%), over = 1304, worst = 6
+PHY-1002 : len = 903608, over cnt = 279(0%), over = 397, worst = 6
+PHY-1002 : len = 910408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.483617s wall, 3.781250s user + 0.031250s system = 3.812500s CPU (153.5%)
+
+PHY-1001 : Congestion index: top1 = 53.88, top5 = 48.97, top10 = 46.18, top15 = 44.35.
+PHY-3001 : End congestion estimation;  2.954468s wall, 4.250000s user + 0.031250s system = 4.281250s CPU (144.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17507 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.887695s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000233722
+PHY-3002 : Step(309): len = 688779, overlap = 102
+PHY-3002 : Step(310): len = 670227, overlap = 150.5
+PHY-3002 : Step(311): len = 658906, overlap = 190.25
+PHY-3002 : Step(312): len = 651246, overlap = 221.5
+PHY-3002 : Step(313): len = 647722, overlap = 244
+PHY-3002 : Step(314): len = 646379, overlap = 248.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000467445
+PHY-3002 : Step(315): len = 652605, overlap = 238
+PHY-3002 : Step(316): len = 659181, overlap = 234.25
+PHY-3002 : Step(317): len = 663809, overlap = 227.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00093489
+PHY-3002 : Step(318): len = 667785, overlap = 224
+PHY-3002 : Step(319): len = 674894, overlap = 221.5
+PHY-3002 : Step(320): len = 682795, overlap = 219.5
+PHY-3002 : Step(321): len = 684295, overlap = 218.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.033927s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (92.1%)
+
+PHY-3001 : Legalized: Len = 725180, Over = 0
+PHY-3001 : Spreading special nets. 497 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.109430s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.9%)
+
+PHY-3001 : 738 instances has been re-located, deltaX = 238, deltaY = 418, maxDist = 2.
+PHY-3001 : Final: Len = 735717, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74849, tnet num: 17507, tinst num: 6890, tnode num: 97605, tedge num: 125692.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.873576s wall, 1.828125s user + 0.046875s system = 1.875000s CPU (100.1%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 610 MB, peak memory is 745 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3307/17685.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862224, over cnt = 2517(7%), over = 4198, worst = 7
+PHY-1002 : len = 873536, over cnt = 1670(4%), over = 2548, worst = 7
+PHY-1002 : len = 893984, over cnt = 633(1%), over = 932, worst = 5
+PHY-1002 : len = 904656, over cnt = 178(0%), over = 236, worst = 5
+PHY-1002 : len = 908216, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.106410s wall, 3.031250s user + 0.031250s system = 3.062500s CPU (145.4%)
+
+PHY-1001 : Congestion index: top1 = 52.52, top5 = 47.85, top10 = 45.34, top15 = 43.69.
+PHY-1001 : End incremental global routing;  2.485894s wall, 3.421875s user + 0.031250s system = 3.453125s CPU (138.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17507 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.873650s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (100.2%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6797 has valid locations, 31 needs to be replaced
+PHY-3001 : design contains 6916 instances, 6767 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3678 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 740763
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16049/17706.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915504, over cnt = 92(0%), over = 108, worst = 5
+PHY-1002 : len = 915736, over cnt = 41(0%), over = 43, worst = 2
+PHY-1002 : len = 916024, over cnt = 11(0%), over = 13, worst = 2
+PHY-1002 : len = 916144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.609550s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (102.5%)
+
+PHY-1001 : Congestion index: top1 = 52.74, top5 = 48.07, top10 = 45.50, top15 = 43.86.
+PHY-3001 : End congestion estimation;  0.921814s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (101.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75081, tnet num: 17528, tinst num: 6916, tnode num: 97902, tedge num: 125981.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.895069s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.8%)
+
+RUN-1004 : used memory is 671 MB, reserved memory is 668 MB, peak memory is 745 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17528 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.789136s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(322): len = 739484, overlap = 0.25
+PHY-3002 : Step(323): len = 739135, overlap = 0.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16049/17706.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913488, over cnt = 86(0%), over = 115, worst = 7
+PHY-1002 : len = 913704, over cnt = 38(0%), over = 44, worst = 4
+PHY-1002 : len = 914096, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 914144, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 914176, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.796966s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (105.9%)
+
+PHY-1001 : Congestion index: top1 = 52.65, top5 = 48.01, top10 = 45.47, top15 = 43.83.
+PHY-3001 : End congestion estimation;  1.129545s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (103.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17528 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.038409s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (100.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000189401
+PHY-3002 : Step(324): len = 739078, overlap = 1.5
+PHY-3002 : Step(325): len = 738919, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005483s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 738971, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062610s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 6, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 739263, Over = 0
+PHY-3001 : End incremental placement;  6.357009s wall, 6.546875s user + 0.078125s system = 6.625000s CPU (104.2%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.207979s wall, 11.312500s user + 0.125000s system = 11.437500s CPU (112.0%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 746, peak = 757.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16010/17706.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913224, over cnt = 70(0%), over = 83, worst = 3
+PHY-1002 : len = 913256, over cnt = 34(0%), over = 34, worst = 1
+PHY-1002 : len = 913392, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 913488, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 913496, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.847186s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 52.59, top5 = 47.95, top10 = 45.49, top15 = 43.82.
+OPT-1001 : End congestion update;  1.172391s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (102.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17528 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.756550s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.2%)
+
+OPT-0007 : Start: WNS -3972 TNS -2287036 NUM_FEPS 995
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6828 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6916 instances, 6767 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3678 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 739523, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063726s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.1%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 2, deltaY = 7, maxDist = 3.
+PHY-3001 : Final: Len = 739661, Over = 0
+PHY-3001 : End incremental legalization;  0.447178s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.3%)
+
+OPT-0007 : Iter 1: improved WNS -3732 TNS -2268265 NUM_FEPS 995 with 26 cells processed and 4241 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6828 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6916 instances, 6767 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3678 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740277, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.066692s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.1%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 2, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 740301, Over = 0
+PHY-3001 : End incremental legalization;  0.420659s wall, 0.406250s user + 0.015625s system = 0.421875s CPU (100.3%)
+
+OPT-0007 : Iter 2: improved WNS -3732 TNS -2267491 NUM_FEPS 995 with 22 cells processed and 2817 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6828 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6916 instances, 6767 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3678 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740469, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064291s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.2%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 5, deltaY = 8, maxDist = 2.
+PHY-3001 : Final: Len = 740675, Over = 0
+PHY-3001 : End incremental legalization;  0.441545s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (102.6%)
+
+OPT-0007 : Iter 3: improved WNS -3732 TNS -2260525 NUM_FEPS 995 with 29 cells processed and 3637 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6828 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6916 instances, 6767 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3678 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740559, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060128s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.9%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 740581, Over = 0
+PHY-3001 : End incremental legalization;  0.390521s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.0%)
+
+OPT-0007 : Iter 4: improved WNS -3732 TNS -2258131 NUM_FEPS 995 with 16 cells processed and 1604 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6828 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6916 instances, 6767 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3678 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740673, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061813s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.1%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 1, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 740685, Over = 0
+PHY-3001 : End incremental legalization;  0.412109s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.6%)
+
+OPT-0007 : Iter 5: improved WNS -3732 TNS -2260911 NUM_FEPS 995 with 18 cells processed and 1308 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6828 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6916 instances, 6767 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3678 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740695, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062524s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.0%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 1, deltaY = 5, maxDist = 1.
+PHY-3001 : Final: Len = 740783, Over = 0
+PHY-3001 : End incremental legalization;  0.396488s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.5%)
+
+OPT-0007 : Iter 6: improved WNS -3732 TNS -2258988 NUM_FEPS 995 with 10 cells processed and 388 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6831 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6919 instances, 6770 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740965, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063929s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (122.2%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 4, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 741155, Over = 0
+PHY-3001 : End incremental legalization;  0.443502s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (91.6%)
+
+OPT-0007 : Iter 7: improved WNS -3638 TNS -2258598 NUM_FEPS 995 with 3 cells processed and 343 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6833 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6921 instances, 6772 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3682 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 741161, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060349s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.7%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 741255, Over = 0
+PHY-3001 : End incremental legalization;  0.378602s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (119.7%)
+
+OPT-0007 : Iter 8: improved WNS -3638 TNS -2258963 NUM_FEPS 995 with 2 cells processed and 300 slack improved
+OPT-1001 : End bottleneck based optimization;  6.544768s wall, 6.953125s user + 0.046875s system = 7.000000s CPU (107.0%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 746, peak = 757.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15614/17707.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 914192, over cnt = 393(1%), over = 527, worst = 6
+PHY-1002 : len = 915144, over cnt = 244(0%), over = 290, worst = 4
+PHY-1002 : len = 917240, over cnt = 97(0%), over = 101, worst = 2
+PHY-1002 : len = 918624, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 919096, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations;  0.872741s wall, 0.984375s user + 0.031250s system = 1.015625s CPU (116.4%)
+
+PHY-1001 : Congestion index: top1 = 52.80, top5 = 48.19, top10 = 45.65, top15 = 44.01.
+OPT-1001 : End congestion update;  1.189562s wall, 1.296875s user + 0.031250s system = 1.328125s CPU (111.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17529 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.745004s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.7%)
+
+OPT-0007 : Start: WNS -3638 TNS -2266147 NUM_FEPS 995
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6833 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6921 instances, 6772 slices, 223 macros(1075 instances: 702 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3682 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 742393, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061498s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.6%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 8, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 742247, Over = 0
+PHY-3001 : End incremental legalization;  0.392003s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%)
+
+OPT-0007 : Iter 1: improved WNS -3606 TNS -2263540 NUM_FEPS 995 with 31 cells processed and 2238 slack improved
+OPT-0007 : Iter 2: improved WNS -3606 TNS -2263540 NUM_FEPS 995 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.488643s wall, 2.593750s user + 0.031250s system = 2.625000s CPU (105.5%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 746, peak = 757.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17529 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.742848s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15919/17707.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919176, over cnt = 113(0%), over = 157, worst = 4
+PHY-1002 : len = 919000, over cnt = 81(0%), over = 94, worst = 4
+PHY-1002 : len = 919768, over cnt = 25(0%), over = 26, worst = 2
+PHY-1002 : len = 920064, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 920344, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.835330s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 52.87, top5 = 48.10, top10 = 45.60, top15 = 43.99.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17529 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.747249s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -3639 TNS -2264592 NUM_FEPS 995
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 52.413793
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -3639ps with logic level 6 
+RUN-1001 :       #2 path slack -3615ps with logic level 5 
+RUN-1001 :       #3 path slack -3606ps with logic level 5 
+RUN-1001 :       #4 path slack -3601ps with logic level 6 
+RUN-1001 :       #5 path slack -3601ps with logic level 6 
+RUN-1001 :       #6 path slack -3590ps with logic level 5 
+RUN-1001 :       #7 path slack -3588ps with logic level 5 
+RUN-1001 :       #8 path slack -3566ps with logic level 5 
+RUN-1001 :       #9 path slack -3562ps with logic level 5 
+RUN-1001 :       #10 path slack -3557ps with logic level 5 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17707 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17707 nets
+OPT-1001 : End physical optimization;  24.155211s wall, 25.796875s user + 0.265625s system = 26.062500s CPU (107.9%)
+
+RUN-1003 : finish command "place" in  69.710605s wall, 103.109375s user + 6.359375s system = 109.468750s CPU (157.0%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 604 MB, peak memory is 757 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.705030s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (173.2%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 605 MB, peak memory is 757 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6923 instances
+RUN-1001 : 3385 mslices, 3387 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17707 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 5778 nets have [3 - 5] pins
+RUN-1001 : 1208 nets have [6 - 10] pins
+RUN-1001 : 373 nets have [11 - 20] pins
+RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75132, tnet num: 17529, tinst num: 6921, tnode num: 97971, tedge num: 126045.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.633420s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.5%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 595 MB, peak memory is 757 MB
+PHY-1001 : 3385 mslices, 3387 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17529 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[2] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 848608, over cnt = 2697(7%), over = 4560, worst = 8
+PHY-1002 : len = 869168, over cnt = 1593(4%), over = 2251, worst = 7
+PHY-1002 : len = 881832, over cnt = 878(2%), over = 1200, worst = 6
+PHY-1002 : len = 894016, over cnt = 314(0%), over = 438, worst = 6
+PHY-1002 : len = 901152, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.875044s wall, 4.031250s user + 0.000000s system = 4.031250s CPU (140.2%)
+
+PHY-1001 : Congestion index: top1 = 51.94, top5 = 47.67, top10 = 45.16, top15 = 43.46.
+PHY-1001 : End global routing;  3.214483s wall, 4.375000s user + 0.000000s system = 4.375000s CPU (136.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 723, reserve = 725, peak = 757.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 994, reserve = 994, peak = 994.
+PHY-1001 : End build detailed router design. 4.041347s wall, 4.046875s user + 0.000000s system = 4.046875s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271296, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.003884s wall, 5.000000s user + 0.000000s system = 5.000000s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271352, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.423299s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1029, reserve = 1030, peak = 1029.
+PHY-1001 : End phase 1; 5.441284s wall, 5.437500s user + 0.000000s system = 5.437500s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 37% nets.
+PHY-1001 : Routed 43% nets.
+PHY-1001 : Routed 54% nets.
+PHY-1001 : Routed 70% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.40658e+06, over cnt = 1576(0%), over = 1587, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1049, peak = 1050.
+PHY-1001 : End initial routed; 23.839066s wall, 55.796875s user + 0.234375s system = 56.031250s CPU (235.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1982/16629(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.399   |  -3558.198  |  995  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.308797s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1071, reserve = 1071, peak = 1071.
+PHY-1001 : End phase 2; 27.147932s wall, 59.093750s user + 0.234375s system = 59.328125s CPU (218.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 75 pins with SWNS -5.994ns STNS -3546.121ns FEP 995.
+PHY-1001 : End OPT Iter 1; 0.369813s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (101.4%)
+
+PHY-1022 : len = 2.40703e+06, over cnt = 1637(0%), over = 1649, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.640730s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.369e+06, over cnt = 553(0%), over = 556, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.439012s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (192.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.36736e+06, over cnt = 159(0%), over = 159, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.645524s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (145.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.36799e+06, over cnt = 30(0%), over = 30, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.530543s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (129.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.36834e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.354837s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (110.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.36842e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.254389s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (104.4%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.36842e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.441948s wall, 0.437500s user + 0.015625s system = 0.453125s CPU (102.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.36842e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.632394s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.36842e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.181664s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.36841e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.191270s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (98.0%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.36842e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.222815s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.36842e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.239616s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (97.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.36842e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.298337s wall, 0.312500s user + 0.015625s system = 0.328125s CPU (110.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.36846e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.181746s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (86.0%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.36842e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.171563s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.36846e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 15; 0.189273s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1982/16629(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.217   |  -3550.322  |  995  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.300572s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 548 feed throughs used by 426 nets
+PHY-1001 : End commit to database; 2.267926s wall, 2.218750s user + 0.046875s system = 2.265625s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1178, peak = 1175.
+PHY-1001 : End phase 3; 12.608725s wall, 14.359375s user + 0.078125s system = 14.437500s CPU (114.5%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 31 pins with SWNS -5.854ns STNS -3546.385ns FEP 995.
+PHY-1001 : End OPT Iter 1; 0.241134s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (97.2%)
+
+PHY-1022 : len = 2.36845e+06, over cnt = 12(0%), over = 12, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.487754s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.854ns, -3546.385ns, 995}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.36823e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.198019s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (110.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.36818e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.181027s wall, 0.187500s user + 0.031250s system = 0.218750s CPU (120.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1982/16629(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -5.956   |  -3548.707  |  995  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.313567s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 557 feed throughs used by 432 nets
+PHY-1001 : End commit to database; 2.371460s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1186, reserve = 1190, peak = 1186.
+PHY-1001 : End phase 4; 6.607231s wall, 6.625000s user + 0.031250s system = 6.656250s CPU (100.7%)
+
+PHY-1003 : Routed, final wirelength = 2.36818e+06
+PHY-1001 : Current memory(MB): used = 1191, reserve = 1195, peak = 1191.
+PHY-1001 : End export database. 0.151780s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.9%)
+
+PHY-1001 : End detail routing;  56.403285s wall, 90.109375s user + 0.343750s system = 90.453125s CPU (160.4%)
+
+RUN-1003 : finish command "route" in  62.367811s wall, 97.156250s user + 0.390625s system = 97.546875s CPU (156.4%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1112 MB, peak memory is 1191 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10384   out of  19600   52.98%
+#reg                     9455   out of  19600   48.24%
+#le                     12608
+  #lut only              3153   out of  12608   25.01%
+  #reg only              2224   out of  12608   17.64%
+  #lut&reg               7231   out of  12608   57.35%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1805
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1441
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1411
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               966
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    137
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         73
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          72
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             exdev_ctl_a/reg2_syn_160.f1                        3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_185.f1    3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P138       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P168       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P70        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12608  |9357    |1027    |9485    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |537    |453     |23      |444     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |103    |98      |4       |91      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |39     |39      |0       |25      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |780    |369     |96      |574     |0       |0       |
+|    u_ADconfig                |AD_config            |190    |132     |25      |141     |0       |0       |
+|    u_gen_sp                  |gen_sp               |273    |174     |71      |116     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |747    |479     |96      |557     |0       |0       |
+|    u_ADconfig                |AD_config            |175    |134     |25      |126     |0       |0       |
+|    u_gen_sp                  |gen_sp               |255    |182     |71      |114     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3072   |2419    |306     |2122    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |183    |98      |17      |145     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|    u_sort                    |sort                 |2855   |2310    |289     |1943    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |4      |4       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2477   |2024    |253     |1615    |22      |0       |
+|        channelPart           |channel_part_8478    |169    |155     |3       |135     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |42      |0       |0       |
+|        ram_switch            |ram_switch           |1939   |1575    |197     |1207    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |250    |215     |27      |133     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |16     |6       |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |32     |29      |3       |16      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |14      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |10      |0       |0       |
+|          insert              |insert               |973    |654     |170     |661     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |716    |706     |0       |413     |0       |0       |
+|        read_ram_i            |read_ram             |260    |204     |44      |184     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |215    |175     |40      |152     |0       |0       |
+|          read_ram_data       |read_ram_data        |45     |29      |4       |32      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |309    |231     |36      |270     |3       |0       |
+|        u0_soft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3426   |2700    |343     |2149    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |187    |111     |17      |150     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |3205   |2574    |326     |1965    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |4      |1       |0       |4       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2778   |2266    |284     |1619    |22      |1       |
+|        channelPart           |channel_part_8478    |234    |225     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |42      |0       |1       |
+|        ram_switch            |ram_switch           |2105   |1728    |197     |1193    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |268    |238     |27      |125     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |8       |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |8       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |17      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |36     |33      |3       |14      |0       |0       |
+|          insert              |insert               |939    |598     |170     |640     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |898    |892     |0       |428     |0       |0       |
+|        read_ram_i            |read_ram_rev         |340    |233     |75      |201     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |283    |204     |67      |163     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |57     |29      |8       |38      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9916  
+    #2         2       3822  
+    #3         3       1437  
+    #4         4       516   
+    #5        5-10     1257  
+    #6       11-50     633   
+    #7       51-100     28   
+    #8        >500      1    
+  Average     2.94           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.085179s wall, 3.593750s user + 0.000000s system = 3.593750s CPU (172.3%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1112 MB, peak memory is 1191 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75132, tnet num: 17529, tinst num: 6921, tnode num: 97971, tedge num: 126045.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.610362s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.9%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1116 MB, peak memory is 1191 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17529 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.526291s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (100.3%)
+
+RUN-1004 : used memory is 1124 MB, reserved memory is 1133 MB, peak memory is 1191 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6921
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17707, pip num: 176180
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 557
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 487039 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.201586s wall, 70.281250s user + 0.140625s system = 70.421875s CPU (690.3%)
+
+RUN-1004 : used memory is 1283 MB, reserved memory is 1278 MB, peak memory is 1398 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_113113.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_114530.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_114530.log
new file mode 100644
index 0000000..53775d2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_114530.log
@@ -0,0 +1,2140 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:45:30 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.125967s wall, 2.062500s user + 0.062500s system = 2.125000s CPU (100.0%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing ultra"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   ultra    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17813 instances
+RUN-0007 : 7512 luts, 9084 seqs, 696 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20378 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13402 nets have 2 pins
+RUN-1001 : 5491 nets have [3 - 5] pins
+RUN-1001 : 1080 nets have [6 - 10] pins
+RUN-1001 : 159 nets have [11 - 20] pins
+RUN-1001 : 171 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17811 instances, 7512 luts, 9084 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5972 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85485, tnet num: 20200, tinst num: 17811, tnode num: 115679, tedge num: 137258.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.174705s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (99.8%)
+
+RUN-1004 : used memory is 540 MB, reserved memory is 516 MB, peak memory is 540 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.967702s wall, 1.937500s user + 0.031250s system = 1.968750s CPU (100.1%)
+
+PHY-3001 : Found 1236 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.07337e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17811.
+PHY-3001 : Level 1 #clusters 2318.
+PHY-3001 : End clustering;  0.125093s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (112.4%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.38264e+06, overlap = 475.625
+PHY-3002 : Step(2): len = 1.11557e+06, overlap = 509.656
+PHY-3002 : Step(3): len = 881469, overlap = 645.594
+PHY-3002 : Step(4): len = 778007, overlap = 711.031
+PHY-3002 : Step(5): len = 615019, overlap = 820.406
+PHY-3002 : Step(6): len = 543824, overlap = 868.562
+PHY-3002 : Step(7): len = 457698, overlap = 938.781
+PHY-3002 : Step(8): len = 414400, overlap = 1004.59
+PHY-3002 : Step(9): len = 372382, overlap = 1044.62
+PHY-3002 : Step(10): len = 340592, overlap = 1095.69
+PHY-3002 : Step(11): len = 311244, overlap = 1131.53
+PHY-3002 : Step(12): len = 286514, overlap = 1189.81
+PHY-3002 : Step(13): len = 264532, overlap = 1227.22
+PHY-3002 : Step(14): len = 248257, overlap = 1264.09
+PHY-3002 : Step(15): len = 230607, overlap = 1270.16
+PHY-3002 : Step(16): len = 216092, overlap = 1299.91
+PHY-3002 : Step(17): len = 203757, overlap = 1342.91
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.08653e-06
+PHY-3002 : Step(18): len = 203617, overlap = 1320.53
+PHY-3002 : Step(19): len = 231889, overlap = 1227.56
+PHY-3002 : Step(20): len = 234962, overlap = 1195.66
+PHY-3002 : Step(21): len = 235119, overlap = 1144.69
+PHY-3002 : Step(22): len = 232004, overlap = 1135.38
+PHY-3002 : Step(23): len = 230007, overlap = 1132.31
+PHY-3002 : Step(24): len = 227413, overlap = 1124.62
+PHY-3002 : Step(25): len = 224491, overlap = 1114.5
+PHY-3002 : Step(26): len = 221442, overlap = 1102.47
+PHY-3002 : Step(27): len = 216684, overlap = 1107.19
+PHY-3002 : Step(28): len = 214238, overlap = 1098.91
+PHY-3002 : Step(29): len = 210810, overlap = 1095.28
+PHY-3002 : Step(30): len = 205945, overlap = 1087.75
+PHY-3002 : Step(31): len = 203563, overlap = 1076.88
+PHY-3002 : Step(32): len = 200530, overlap = 1052.75
+PHY-3002 : Step(33): len = 199400, overlap = 1044.81
+PHY-3002 : Step(34): len = 196590, overlap = 1058.66
+PHY-3002 : Step(35): len = 196040, overlap = 1061.5
+PHY-3002 : Step(36): len = 194978, overlap = 1064.16
+PHY-3002 : Step(37): len = 193316, overlap = 1061.25
+PHY-3002 : Step(38): len = 191977, overlap = 1062.47
+PHY-3002 : Step(39): len = 190433, overlap = 1055.84
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.17305e-06
+PHY-3002 : Step(40): len = 194949, overlap = 1042.59
+PHY-3002 : Step(41): len = 208798, overlap = 1009.25
+PHY-3002 : Step(42): len = 214277, overlap = 982.031
+PHY-3002 : Step(43): len = 221104, overlap = 956.906
+PHY-3002 : Step(44): len = 222816, overlap = 932.562
+PHY-3002 : Step(45): len = 224775, overlap = 885.906
+PHY-3002 : Step(46): len = 225261, overlap = 874.656
+PHY-3002 : Step(47): len = 224690, overlap = 886.594
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.3461e-06
+PHY-3002 : Step(48): len = 234654, overlap = 868.969
+PHY-3002 : Step(49): len = 256990, overlap = 793.938
+PHY-3002 : Step(50): len = 262941, overlap = 749.938
+PHY-3002 : Step(51): len = 265877, overlap = 736.406
+PHY-3002 : Step(52): len = 266150, overlap = 715.594
+PHY-3002 : Step(53): len = 265265, overlap = 711.312
+PHY-3002 : Step(54): len = 262976, overlap = 695.688
+PHY-3002 : Step(55): len = 262680, overlap = 680.906
+PHY-3002 : Step(56): len = 261554, overlap = 679.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.69221e-06
+PHY-3002 : Step(57): len = 279596, overlap = 671.25
+PHY-3002 : Step(58): len = 296830, overlap = 596.125
+PHY-3002 : Step(59): len = 302407, overlap = 554.719
+PHY-3002 : Step(60): len = 303153, overlap = 538.094
+PHY-3002 : Step(61): len = 301790, overlap = 533.188
+PHY-3002 : Step(62): len = 301859, overlap = 521.5
+PHY-3002 : Step(63): len = 301735, overlap = 515.562
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.73844e-05
+PHY-3002 : Step(64): len = 321812, overlap = 478.969
+PHY-3002 : Step(65): len = 339877, overlap = 430.219
+PHY-3002 : Step(66): len = 344822, overlap = 392.562
+PHY-3002 : Step(67): len = 346870, overlap = 358.656
+PHY-3002 : Step(68): len = 346011, overlap = 361.625
+PHY-3002 : Step(69): len = 347719, overlap = 355.25
+PHY-3002 : Step(70): len = 347854, overlap = 350.531
+PHY-3002 : Step(71): len = 349546, overlap = 354.844
+PHY-3002 : Step(72): len = 351005, overlap = 346.594
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.47688e-05
+PHY-3002 : Step(73): len = 370614, overlap = 308.344
+PHY-3002 : Step(74): len = 385817, overlap = 288.844
+PHY-3002 : Step(75): len = 386035, overlap = 290.562
+PHY-3002 : Step(76): len = 388915, overlap = 283.656
+PHY-3002 : Step(77): len = 390878, overlap = 274.469
+PHY-3002 : Step(78): len = 394839, overlap = 258.688
+PHY-3002 : Step(79): len = 393835, overlap = 262.344
+PHY-3002 : Step(80): len = 396362, overlap = 270.938
+PHY-3002 : Step(81): len = 395985, overlap = 269.406
+PHY-3002 : Step(82): len = 397833, overlap = 257.312
+PHY-3002 : Step(83): len = 397314, overlap = 265.469
+PHY-3002 : Step(84): len = 396678, overlap = 274.688
+PHY-3002 : Step(85): len = 396626, overlap = 270.469
+PHY-3002 : Step(86): len = 397220, overlap = 250.25
+PHY-3002 : Step(87): len = 396314, overlap = 242.812
+PHY-3002 : Step(88): len = 397167, overlap = 237.75
+PHY-3002 : Step(89): len = 396319, overlap = 251.406
+PHY-3002 : Step(90): len = 395523, overlap = 246.312
+PHY-3002 : Step(91): len = 394305, overlap = 251.969
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.95377e-05
+PHY-3002 : Step(92): len = 411627, overlap = 240.469
+PHY-3002 : Step(93): len = 425954, overlap = 226.5
+PHY-3002 : Step(94): len = 427059, overlap = 218.5
+PHY-3002 : Step(95): len = 427700, overlap = 225.312
+PHY-3002 : Step(96): len = 428673, overlap = 218.25
+PHY-3002 : Step(97): len = 430256, overlap = 216.25
+PHY-3002 : Step(98): len = 430141, overlap = 214.438
+PHY-3002 : Step(99): len = 432657, overlap = 212.281
+PHY-3002 : Step(100): len = 433266, overlap = 205.625
+PHY-3002 : Step(101): len = 434631, overlap = 208.094
+PHY-3002 : Step(102): len = 432907, overlap = 211.125
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000133564
+PHY-3002 : Step(103): len = 445764, overlap = 205.875
+PHY-3002 : Step(104): len = 458819, overlap = 199.25
+PHY-3002 : Step(105): len = 462074, overlap = 199.594
+PHY-3002 : Step(106): len = 465356, overlap = 195.875
+PHY-3002 : Step(107): len = 469686, overlap = 186.281
+PHY-3002 : Step(108): len = 472586, overlap = 178.5
+PHY-3002 : Step(109): len = 469584, overlap = 175.656
+PHY-3002 : Step(110): len = 470399, overlap = 178.688
+PHY-3002 : Step(111): len = 471258, overlap = 177.938
+PHY-3002 : Step(112): len = 473150, overlap = 176
+PHY-3002 : Step(113): len = 472489, overlap = 176.781
+PHY-3002 : Step(114): len = 474062, overlap = 169.812
+PHY-3002 : Step(115): len = 476086, overlap = 151.719
+PHY-3002 : Step(116): len = 478032, overlap = 154.562
+PHY-3002 : Step(117): len = 475707, overlap = 161.219
+PHY-3002 : Step(118): len = 476168, overlap = 160.656
+PHY-3002 : Step(119): len = 477352, overlap = 162.969
+PHY-3002 : Step(120): len = 478274, overlap = 157.812
+PHY-3002 : Step(121): len = 476832, overlap = 163.406
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000257702
+PHY-3002 : Step(122): len = 485853, overlap = 158.594
+PHY-3002 : Step(123): len = 497139, overlap = 155.688
+PHY-3002 : Step(124): len = 499632, overlap = 144.375
+PHY-3002 : Step(125): len = 501704, overlap = 140.094
+PHY-3002 : Step(126): len = 503953, overlap = 146.25
+PHY-3002 : Step(127): len = 506198, overlap = 145.188
+PHY-3002 : Step(128): len = 504880, overlap = 142.406
+PHY-3002 : Step(129): len = 505179, overlap = 144.906
+PHY-3002 : Step(130): len = 506724, overlap = 144.562
+PHY-3002 : Step(131): len = 508389, overlap = 143.094
+PHY-3002 : Step(132): len = 506540, overlap = 149.844
+PHY-3002 : Step(133): len = 506495, overlap = 147.719
+PHY-3002 : Step(134): len = 507445, overlap = 146.625
+PHY-3002 : Step(135): len = 508189, overlap = 148.281
+PHY-3002 : Step(136): len = 507320, overlap = 148.406
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000435406
+PHY-3002 : Step(137): len = 511416, overlap = 147.531
+PHY-3002 : Step(138): len = 515421, overlap = 147.938
+PHY-3002 : Step(139): len = 516671, overlap = 154.469
+PHY-3002 : Step(140): len = 518454, overlap = 149.406
+PHY-3002 : Step(141): len = 520383, overlap = 144.781
+PHY-3002 : Step(142): len = 521482, overlap = 142.594
+PHY-3002 : Step(143): len = 520903, overlap = 142.25
+PHY-3002 : Step(144): len = 521769, overlap = 141.094
+PHY-3002 : Step(145): len = 524365, overlap = 128.531
+PHY-3002 : Step(146): len = 525874, overlap = 127.875
+PHY-3002 : Step(147): len = 525115, overlap = 135.031
+PHY-3002 : Step(148): len = 524952, overlap = 132.781
+PHY-3002 : Step(149): len = 528387, overlap = 123.281
+PHY-3002 : Step(150): len = 532135, overlap = 126.75
+PHY-3002 : Step(151): len = 530702, overlap = 131.219
+PHY-3002 : Step(152): len = 530127, overlap = 131.75
+PHY-3002 : Step(153): len = 530649, overlap = 129.594
+PHY-3002 : Step(154): len = 531127, overlap = 131.031
+PHY-3002 : Step(155): len = 530663, overlap = 127.312
+PHY-3002 : Step(156): len = 530577, overlap = 128.656
+PHY-3002 : Step(157): len = 531125, overlap = 128.219
+PHY-3002 : Step(158): len = 531741, overlap = 129.594
+PHY-3002 : Step(159): len = 531285, overlap = 118.938
+PHY-3002 : Step(160): len = 531336, overlap = 122
+PHY-3002 : Step(161): len = 532033, overlap = 124.344
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000797416
+PHY-3002 : Step(162): len = 536082, overlap = 121.031
+PHY-3002 : Step(163): len = 542791, overlap = 112.375
+PHY-3002 : Step(164): len = 544496, overlap = 110.5
+PHY-3002 : Step(165): len = 545608, overlap = 107.781
+PHY-3002 : Step(166): len = 546472, overlap = 108.406
+PHY-3002 : Step(167): len = 546880, overlap = 104.25
+PHY-3002 : Step(168): len = 546875, overlap = 109.531
+PHY-3002 : Step(169): len = 547626, overlap = 102.344
+PHY-3002 : Step(170): len = 548731, overlap = 94.3438
+PHY-3002 : Step(171): len = 549134, overlap = 93.0312
+PHY-3002 : Step(172): len = 549499, overlap = 95.0938
+PHY-3002 : Step(173): len = 549879, overlap = 97.4688
+PHY-3002 : Step(174): len = 550338, overlap = 91.9688
+PHY-3002 : Step(175): len = 550552, overlap = 91.8438
+PHY-3002 : Step(176): len = 550634, overlap = 90.2812
+PHY-3002 : Step(177): len = 550944, overlap = 89.5625
+PHY-3002 : Step(178): len = 551396, overlap = 87.25
+PHY-3002 : Step(179): len = 551539, overlap = 87.25
+PHY-3002 : Step(180): len = 551666, overlap = 85.5938
+PHY-3002 : Step(181): len = 551949, overlap = 86.0938
+PHY-3002 : Step(182): len = 552216, overlap = 85.6562
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00139367
+PHY-3002 : Step(183): len = 555699, overlap = 87.5312
+PHY-3002 : Step(184): len = 563282, overlap = 88.5938
+PHY-3002 : Step(185): len = 565463, overlap = 83.75
+PHY-3002 : Step(186): len = 567164, overlap = 81.375
+PHY-3002 : Step(187): len = 569163, overlap = 80.7812
+PHY-3002 : Step(188): len = 570623, overlap = 81.125
+PHY-3002 : Step(189): len = 571300, overlap = 85.4062
+PHY-3002 : Step(190): len = 571882, overlap = 87.0312
+PHY-3002 : Step(191): len = 571871, overlap = 83.9375
+PHY-3002 : Step(192): len = 571683, overlap = 79.25
+PHY-3002 : Step(193): len = 571041, overlap = 78.4688
+PHY-3002 : Step(194): len = 570844, overlap = 78.3125
+PHY-3002 : Step(195): len = 571057, overlap = 79.0312
+PHY-3002 : Step(196): len = 571025, overlap = 79.0312
+PHY-3002 : Step(197): len = 570498, overlap = 76.4688
+PHY-3002 : Step(198): len = 570262, overlap = 76.9688
+PHY-3002 : Step(199): len = 570154, overlap = 76.9688
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.0022904
+PHY-3002 : Step(200): len = 571167, overlap = 76.9688
+PHY-3002 : Step(201): len = 573155, overlap = 75.4688
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016452s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (189.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20378.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 734896, over cnt = 1472(4%), over = 6196, worst = 54
+PHY-1001 : End global iterations;  0.757870s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (121.6%)
+
+PHY-1001 : Congestion index: top1 = 70.37, top5 = 56.05, top10 = 48.65, top15 = 43.95.
+PHY-3001 : End congestion estimation;  1.007650s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (114.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.864716s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (101.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000106048
+PHY-3002 : Step(202): len = 674830, overlap = 34.0938
+PHY-3002 : Step(203): len = 676233, overlap = 34.0625
+PHY-3002 : Step(204): len = 661285, overlap = 33
+PHY-3002 : Step(205): len = 653512, overlap = 35.7188
+PHY-3002 : Step(206): len = 649196, overlap = 38.75
+PHY-3002 : Step(207): len = 645262, overlap = 35.875
+PHY-3002 : Step(208): len = 639422, overlap = 37.3438
+PHY-3002 : Step(209): len = 637739, overlap = 39.0938
+PHY-3002 : Step(210): len = 634736, overlap = 43.2188
+PHY-3002 : Step(211): len = 631084, overlap = 50.7188
+PHY-3002 : Step(212): len = 629467, overlap = 55.625
+PHY-3002 : Step(213): len = 626957, overlap = 64
+PHY-3002 : Step(214): len = 622881, overlap = 66.0625
+PHY-3002 : Step(215): len = 621528, overlap = 66.8125
+PHY-3002 : Step(216): len = 619784, overlap = 67.6562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000212096
+PHY-3002 : Step(217): len = 621165, overlap = 64.0312
+PHY-3002 : Step(218): len = 625101, overlap = 61.1875
+PHY-3002 : Step(219): len = 626849, overlap = 61.2188
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000393231
+PHY-3002 : Step(220): len = 638177, overlap = 52.375
+PHY-3002 : Step(221): len = 657824, overlap = 48.4375
+PHY-3002 : Step(222): len = 660931, overlap = 48.6562
+PHY-3002 : Step(223): len = 658547, overlap = 48.5312
+PHY-3002 : Step(224): len = 657797, overlap = 48.0312
+PHY-3002 : Step(225): len = 655734, overlap = 49.4688
+PHY-3002 : Step(226): len = 654288, overlap = 48.8125
+PHY-3002 : Step(227): len = 654674, overlap = 48.0312
+PHY-3002 : Step(228): len = 654459, overlap = 49.5625
+PHY-3002 : Step(229): len = 655009, overlap = 50.75
+PHY-3002 : Step(230): len = 654431, overlap = 52.9375
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000777689
+PHY-3002 : Step(231): len = 659764, overlap = 50.9688
+PHY-3002 : Step(232): len = 668307, overlap = 51.125
+PHY-3002 : Step(233): len = 673347, overlap = 52.9062
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.0012583
+PHY-3002 : Step(234): len = 676544, overlap = 53.0312
+PHY-3002 : Step(235): len = 687843, overlap = 52.9688
+PHY-3002 : Step(236): len = 698455, overlap = 50.5625
+PHY-3002 : Step(237): len = 703469, overlap = 52.4062
+PHY-3002 : Step(238): len = 706195, overlap = 52.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 57/20378.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 786272, over cnt = 2491(7%), over = 11895, worst = 45
+PHY-1001 : End global iterations;  1.535508s wall, 2.015625s user + 0.031250s system = 2.046875s CPU (133.3%)
+
+PHY-1001 : Congestion index: top1 = 91.77, top5 = 70.44, top10 = 61.31, top15 = 55.55.
+PHY-3001 : End congestion estimation;  1.869951s wall, 2.328125s user + 0.031250s system = 2.359375s CPU (126.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.474756s wall, 1.468750s user + 0.000000s system = 1.468750s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000128627
+PHY-3002 : Step(239): len = 687507, overlap = 268.75
+PHY-3002 : Step(240): len = 678707, overlap = 206.375
+PHY-3002 : Step(241): len = 660844, overlap = 187.812
+PHY-3002 : Step(242): len = 649368, overlap = 179.656
+PHY-3002 : Step(243): len = 640891, overlap = 177.062
+PHY-3002 : Step(244): len = 632794, overlap = 178
+PHY-3002 : Step(245): len = 627088, overlap = 169.5
+PHY-3002 : Step(246): len = 622243, overlap = 175.844
+PHY-3002 : Step(247): len = 615422, overlap = 174.844
+PHY-3002 : Step(248): len = 612249, overlap = 176.312
+PHY-3002 : Step(249): len = 606950, overlap = 183.406
+PHY-3002 : Step(250): len = 604099, overlap = 183.5
+PHY-3002 : Step(251): len = 600695, overlap = 188.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000257253
+PHY-3002 : Step(252): len = 601400, overlap = 182.938
+PHY-3002 : Step(253): len = 605430, overlap = 176.344
+PHY-3002 : Step(254): len = 608881, overlap = 171.875
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000514506
+PHY-3002 : Step(255): len = 610847, overlap = 164.688
+PHY-3002 : Step(256): len = 616160, overlap = 156
+PHY-3002 : Step(257): len = 621958, overlap = 149
+PHY-3002 : Step(258): len = 624129, overlap = 146.812
+PHY-3002 : Step(259): len = 625943, overlap = 144
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00102901
+PHY-3002 : Step(260): len = 628504, overlap = 137.844
+PHY-3002 : Step(261): len = 633265, overlap = 134.25
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85485, tnet num: 20200, tinst num: 17811, tnode num: 115679, tedge num: 137258.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.442692s wall, 1.406250s user + 0.031250s system = 1.437500s CPU (99.6%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 564 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 488.38 peak overflow 4.88
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 344/20378.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 725856, over cnt = 2676(7%), over = 9714, worst = 23
+PHY-1001 : End global iterations;  1.316525s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (130.6%)
+
+PHY-1001 : Congestion index: top1 = 67.41, top5 = 55.77, top10 = 50.35, top15 = 46.98.
+PHY-1001 : End incremental global routing;  1.649082s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (124.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20200 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.130908s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (100.9%)
+
+OPT-1001 : 44 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17682 has valid locations, 295 needs to be replaced
+PHY-3001 : design contains 18062 instances, 7578 luts, 9269 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6097 pins
+PHY-3001 : Found 1244 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 656751
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15951/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 740864, over cnt = 2701(7%), over = 9766, worst = 23
+PHY-1001 : End global iterations;  0.218107s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (114.6%)
+
+PHY-1001 : Congestion index: top1 = 67.56, top5 = 55.90, top10 = 50.42, top15 = 47.05.
+PHY-3001 : End congestion estimation;  0.464873s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (104.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86499, tnet num: 20451, tinst num: 18062, tnode num: 117265, tedge num: 138784.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.522097s wall, 1.468750s user + 0.062500s system = 1.531250s CPU (100.6%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 614 MB, peak memory is 723 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.838017s wall, 2.750000s user + 0.093750s system = 2.843750s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(262): len = 655490, overlap = 2.625
+PHY-3002 : Step(263): len = 655443, overlap = 2.5
+PHY-3002 : Step(264): len = 655303, overlap = 2.5
+PHY-3002 : Step(265): len = 655499, overlap = 2.5625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16007/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737792, over cnt = 2700(7%), over = 9821, worst = 23
+PHY-1001 : End global iterations;  0.194532s wall, 0.234375s user + 0.015625s system = 0.250000s CPU (128.5%)
+
+PHY-1001 : Congestion index: top1 = 67.95, top5 = 56.34, top10 = 50.86, top15 = 47.41.
+PHY-3001 : End congestion estimation;  0.438038s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (114.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.922325s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000434584
+PHY-3002 : Step(266): len = 655447, overlap = 136.281
+PHY-3002 : Step(267): len = 655708, overlap = 136.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000869168
+PHY-3002 : Step(268): len = 656052, overlap = 136.625
+PHY-3002 : Step(269): len = 656750, overlap = 136.281
+PHY-3001 : Final: Len = 656750, Over = 136.281
+PHY-3001 : End incremental placement;  5.312892s wall, 5.421875s user + 0.296875s system = 5.718750s CPU (107.6%)
+
+OPT-1001 : Total overflow 493.28 peak overflow 4.88
+OPT-1001 : End high-fanout net optimization;  8.618397s wall, 9.109375s user + 0.312500s system = 9.421875s CPU (109.3%)
+
+OPT-1001 : Current memory(MB): used = 724, reserve = 710, peak = 741.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15987/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 742016, over cnt = 2654(7%), over = 9011, worst = 23
+PHY-1002 : len = 779248, over cnt = 1948(5%), over = 5404, worst = 19
+PHY-1002 : len = 818408, over cnt = 921(2%), over = 2374, worst = 13
+PHY-1002 : len = 842240, over cnt = 282(0%), over = 714, worst = 13
+PHY-1002 : len = 851168, over cnt = 18(0%), over = 38, worst = 7
+PHY-1001 : End global iterations;  1.550537s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (140.1%)
+
+PHY-1001 : Congestion index: top1 = 57.56, top5 = 50.36, top10 = 46.85, top15 = 44.49.
+OPT-1001 : End congestion update;  1.798581s wall, 2.406250s user + 0.015625s system = 2.421875s CPU (134.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.797514s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS -4869 TNS -2636496 NUM_FEPS 1054
+OPT-0007 : Iter 1: improved WNS -4143 TNS -2492614 NUM_FEPS 1054 with 30 cells processed and 1508 slack improved
+OPT-0007 : Iter 2: improved WNS -4119 TNS -2511646 NUM_FEPS 1054 with 103 cells processed and 1698 slack improved
+OPT-0007 : Iter 3: improved WNS -4119 TNS -2511496 NUM_FEPS 1054 with 64 cells processed and 850 slack improved
+OPT-0007 : Iter 4: improved WNS -4119 TNS -2505500 NUM_FEPS 1054 with 31 cells processed and 600 slack improved
+OPT-0007 : Iter 5: improved WNS -4093 TNS -2504186 NUM_FEPS 1054 with 9 cells processed and 124 slack improved
+OPT-0007 : Iter 6: improved WNS -4093 TNS -2504236 NUM_FEPS 1054 with 4 cells processed and 450 slack improved
+OPT-0007 : Iter 7: improved WNS -4093 TNS -2504236 NUM_FEPS 1054 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  3.414202s wall, 4.000000s user + 0.031250s system = 4.031250s CPU (118.1%)
+
+OPT-1001 : Current memory(MB): used = 701, reserve = 690, peak = 741.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16162/20629.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855920, over cnt = 208(0%), over = 401, worst = 9
+PHY-1002 : len = 857520, over cnt = 125(0%), over = 177, worst = 7
+PHY-1002 : len = 859200, over cnt = 39(0%), over = 43, worst = 2
+PHY-1002 : len = 859656, over cnt = 22(0%), over = 23, worst = 2
+PHY-1002 : len = 860280, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.821920s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (114.1%)
+
+PHY-1001 : Congestion index: top1 = 57.52, top5 = 50.53, top10 = 47.11, top15 = 44.79.
+OPT-1001 : End congestion update;  1.089568s wall, 1.171875s user + 0.031250s system = 1.203125s CPU (110.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20451 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.833639s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (99.3%)
+
+OPT-0007 : Start: WNS -4093 TNS -2504236 NUM_FEPS 1054
+OPT-0007 : Iter 1: improved WNS -4093 TNS -2500136 NUM_FEPS 1054 with 63 cells processed and 4100 slack improved
+OPT-0007 : Iter 2: improved WNS -4093 TNS -2500136 NUM_FEPS 1054 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.071146s wall, 2.140625s user + 0.031250s system = 2.171875s CPU (104.9%)
+
+OPT-1001 : Current memory(MB): used = 713, reserve = 700, peak = 741.
+OPT-1001 : End physical optimization;  15.853590s wall, 17.078125s user + 0.406250s system = 17.484375s CPU (110.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7578 LUT to BLE ...
+SYN-4008 : Packed 7578 LUT and 3144 SEQ to BLE.
+SYN-4003 : Packing 6125 remaining SEQ's ...
+SYN-4005 : Packed 3655 SEQ with LUT/SLICE
+SYN-4006 : 1078 single LUT's are left
+SYN-4006 : 2470 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10048/13789 primitive instances ...
+PHY-3001 : End packing;  1.646510s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.6%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6950 instances
+RUN-1001 : 3401 mslices, 3401 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17616 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10045 nets have 2 pins
+RUN-1001 : 5716 nets have [3 - 5] pins
+RUN-1001 : 1177 nets have [6 - 10] pins
+RUN-1001 : 289 nets have [11 - 20] pins
+RUN-1001 : 357 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6948 instances, 6802 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3622 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 666282, Over = 313.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7398/17616.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808016, over cnt = 1746(4%), over = 3038, worst = 9
+PHY-1002 : len = 816560, over cnt = 1066(3%), over = 1602, worst = 8
+PHY-1002 : len = 828864, over cnt = 454(1%), over = 634, worst = 8
+PHY-1002 : len = 833376, over cnt = 223(0%), over = 298, worst = 5
+PHY-1002 : len = 839616, over cnt = 6(0%), over = 7, worst = 2
+PHY-1001 : End global iterations;  1.481613s wall, 2.171875s user + 0.000000s system = 2.171875s CPU (146.6%)
+
+PHY-1001 : Congestion index: top1 = 58.34, top5 = 50.77, top10 = 46.77, top15 = 44.17.
+PHY-3001 : End congestion estimation;  1.864121s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (136.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74701, tnet num: 17438, tinst num: 6948, tnode num: 97301, tedge num: 125597.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.635009s wall, 1.609375s user + 0.031250s system = 1.640625s CPU (100.3%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 619 MB, peak memory is 741 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17438 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.511800s wall, 2.484375s user + 0.031250s system = 2.515625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.28175e-05
+PHY-3002 : Step(270): len = 651631, overlap = 322.25
+PHY-3002 : Step(271): len = 643227, overlap = 332.5
+PHY-3002 : Step(272): len = 639059, overlap = 335
+PHY-3002 : Step(273): len = 637289, overlap = 337
+PHY-3002 : Step(274): len = 634454, overlap = 340.5
+PHY-3002 : Step(275): len = 632681, overlap = 342.25
+PHY-3002 : Step(276): len = 629409, overlap = 350
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000105635
+PHY-3002 : Step(277): len = 632937, overlap = 343
+PHY-3002 : Step(278): len = 639368, overlap = 338.75
+PHY-3002 : Step(279): len = 639209, overlap = 339.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00021127
+PHY-3002 : Step(280): len = 648564, overlap = 330
+PHY-3002 : Step(281): len = 659205, overlap = 314.25
+PHY-3002 : Step(282): len = 657113, overlap = 318.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.307515s wall, 0.359375s user + 0.546875s system = 0.906250s CPU (294.7%)
+
+PHY-3001 : Trial Legalized: Len = 761418
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 632/17616.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 878328, over cnt = 2769(7%), over = 4893, worst = 9
+PHY-1002 : len = 899040, over cnt = 1638(4%), over = 2413, worst = 7
+PHY-1002 : len = 915640, over cnt = 733(2%), over = 1070, worst = 7
+PHY-1002 : len = 924976, over cnt = 339(0%), over = 468, worst = 7
+PHY-1002 : len = 935520, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.346656s wall, 3.484375s user + 0.015625s system = 3.500000s CPU (149.1%)
+
+PHY-1001 : Congestion index: top1 = 55.82, top5 = 50.46, top10 = 47.61, top15 = 45.61.
+PHY-3001 : End congestion estimation;  2.813496s wall, 3.937500s user + 0.031250s system = 3.968750s CPU (141.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17438 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.875429s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000226167
+PHY-3002 : Step(283): len = 713612, overlap = 103.75
+PHY-3002 : Step(284): len = 695132, overlap = 148.25
+PHY-3002 : Step(285): len = 683721, overlap = 186.25
+PHY-3002 : Step(286): len = 676599, overlap = 218.75
+PHY-3002 : Step(287): len = 672585, overlap = 235.5
+PHY-3002 : Step(288): len = 671131, overlap = 249
+PHY-3002 : Step(289): len = 669482, overlap = 248.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000452334
+PHY-3002 : Step(290): len = 675268, overlap = 245.5
+PHY-3002 : Step(291): len = 680070, overlap = 243.75
+PHY-3002 : Step(292): len = 681351, overlap = 242.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000827434
+PHY-3002 : Step(293): len = 685521, overlap = 236.25
+PHY-3002 : Step(294): len = 691695, overlap = 226
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.038722s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (121.1%)
+
+PHY-3001 : Legalized: Len = 735051, Over = 0
+PHY-3001 : Spreading special nets. 545 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.118449s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (92.3%)
+
+PHY-3001 : 807 instances has been re-located, deltaX = 279, deltaY = 520, maxDist = 3.
+PHY-3001 : Final: Len = 748803, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74701, tnet num: 17438, tinst num: 6951, tnode num: 97301, tedge num: 125597.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.866841s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.4%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 653 MB, peak memory is 741 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3598/17616.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 876320, over cnt = 2524(7%), over = 4288, worst = 7
+PHY-1002 : len = 892904, over cnt = 1434(4%), over = 2057, worst = 7
+PHY-1002 : len = 908184, over cnt = 582(1%), over = 836, worst = 7
+PHY-1002 : len = 918600, over cnt = 70(0%), over = 79, worst = 3
+PHY-1002 : len = 920160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.188071s wall, 3.140625s user + 0.015625s system = 3.156250s CPU (144.2%)
+
+PHY-1001 : Congestion index: top1 = 54.94, top5 = 49.32, top10 = 46.67, top15 = 44.75.
+PHY-1001 : End incremental global routing;  2.565881s wall, 3.500000s user + 0.015625s system = 3.515625s CPU (137.0%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17438 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.878166s wall, 0.796875s user + 0.078125s system = 0.875000s CPU (99.6%)
+
+OPT-1001 : 7 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6856 has valid locations, 37 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 755742
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16018/17643.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929240, over cnt = 119(0%), over = 142, worst = 4
+PHY-1002 : len = 929320, over cnt = 53(0%), over = 54, worst = 2
+PHY-1002 : len = 929584, over cnt = 25(0%), over = 25, worst = 1
+PHY-1002 : len = 929896, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 930120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.830862s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (107.2%)
+
+PHY-1001 : Congestion index: top1 = 55.13, top5 = 49.58, top10 = 46.89, top15 = 44.99.
+PHY-3001 : End congestion estimation;  1.154562s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (105.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75008, tnet num: 17465, tinst num: 6981, tnode num: 97690, tedge num: 125984.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.879835s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.7%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 671 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.764229s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(295): len = 753681, overlap = 0
+PHY-3002 : Step(296): len = 752939, overlap = 0
+PHY-3002 : Step(297): len = 752495, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15999/17643.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 925328, over cnt = 119(0%), over = 149, worst = 7
+PHY-1002 : len = 925488, over cnt = 74(0%), over = 81, worst = 3
+PHY-1002 : len = 926128, over cnt = 13(0%), over = 14, worst = 2
+PHY-1002 : len = 926472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.636409s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 54.91, top5 = 49.56, top10 = 46.86, top15 = 44.95.
+PHY-3001 : End congestion estimation;  0.947520s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (105.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.860580s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000812637
+PHY-3002 : Step(298): len = 752327, overlap = 2
+PHY-3002 : Step(299): len = 752394, overlap = 2
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005407s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 752616, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061862s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.0%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 10, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 752768, Over = 0
+PHY-3001 : End incremental placement;  6.247285s wall, 6.453125s user + 0.125000s system = 6.578125s CPU (105.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.192184s wall, 11.265625s user + 0.218750s system = 11.484375s CPU (112.7%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 744, peak = 756.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15959/17643.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926368, over cnt = 92(0%), over = 129, worst = 7
+PHY-1002 : len = 926584, over cnt = 46(0%), over = 57, worst = 6
+PHY-1002 : len = 927056, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 927048, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 927096, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.826572s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (102.1%)
+
+PHY-1001 : Congestion index: top1 = 55.22, top5 = 49.59, top10 = 46.88, top15 = 44.94.
+OPT-1001 : End congestion update;  1.137177s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (103.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17465 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.734046s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.0%)
+
+OPT-0007 : Start: WNS -4235 TNS -2297252 NUM_FEPS 979
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 753392, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.068099s wall, 0.046875s user + 0.015625s system = 0.062500s CPU (91.8%)
+
+PHY-3001 : 17 instances has been re-located, deltaX = 3, deltaY = 16, maxDist = 2.
+PHY-3001 : Final: Len = 753860, Over = 0
+PHY-3001 : End incremental legalization;  0.415899s wall, 0.421875s user + 0.046875s system = 0.468750s CPU (112.7%)
+
+OPT-0007 : Iter 1: improved WNS -3845 TNS -2265529 NUM_FEPS 979 with 26 cells processed and 3712 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 754484, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.065241s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.7%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 754920, Over = 0
+PHY-3001 : End incremental legalization;  0.390333s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.1%)
+
+OPT-0007 : Iter 2: improved WNS -3845 TNS -2259525 NUM_FEPS 979 with 26 cells processed and 2994 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 755526, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062178s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 2, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 755820, Over = 0
+PHY-3001 : End incremental legalization;  0.382782s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.0%)
+
+OPT-0007 : Iter 3: improved WNS -3795 TNS -2251133 NUM_FEPS 979 with 22 cells processed and 2278 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 755462, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.065494s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.4%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 755622, Over = 0
+PHY-3001 : End incremental legalization;  0.400301s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (124.9%)
+
+OPT-0007 : Iter 4: improved WNS -3795 TNS -2250934 NUM_FEPS 979 with 12 cells processed and 1359 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 755580, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063743s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.0%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 2, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 755804, Over = 0
+PHY-3001 : End incremental legalization;  0.424789s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.3%)
+
+OPT-0007 : Iter 5: improved WNS -3795 TNS -2248793 NUM_FEPS 979 with 15 cells processed and 1434 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 755920, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060645s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.1%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 756050, Over = 0
+PHY-3001 : End incremental legalization;  0.384208s wall, 0.421875s user + 0.031250s system = 0.453125s CPU (117.9%)
+
+OPT-0007 : Iter 6: improved WNS -3795 TNS -2246890 NUM_FEPS 979 with 12 cells processed and 1332 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6981 instances, 6832 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3703 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 755850, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060489s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 1, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 756006, Over = 0
+PHY-3001 : End incremental legalization;  0.394780s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.9%)
+
+OPT-0007 : Iter 7: improved WNS -3795 TNS -2244496 NUM_FEPS 979 with 14 cells processed and 1241 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6901 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6989 instances, 6840 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 756589, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061009s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.4%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 6, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 756597, Over = 0
+PHY-3001 : End incremental legalization;  0.383559s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.8%)
+
+OPT-0007 : Iter 8: improved WNS -3795 TNS -2240568 NUM_FEPS 979 with 8 cells processed and 853 slack improved
+OPT-1001 : End bottleneck based optimization;  6.378564s wall, 6.703125s user + 0.109375s system = 6.812500s CPU (106.8%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 745, peak = 756.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15488/17647.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930600, over cnt = 434(1%), over = 570, worst = 5
+PHY-1002 : len = 931192, over cnt = 270(0%), over = 314, worst = 3
+PHY-1002 : len = 932920, over cnt = 127(0%), over = 149, worst = 3
+PHY-1002 : len = 934536, over cnt = 37(0%), over = 38, worst = 2
+PHY-1002 : len = 935544, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.893343s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (115.4%)
+
+PHY-1001 : Congestion index: top1 = 55.34, top5 = 50.09, top10 = 47.43, top15 = 45.45.
+OPT-1001 : End congestion update;  1.216135s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (110.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17468 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.743404s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.9%)
+
+OPT-0007 : Start: WNS -3775 TNS -2244880 NUM_FEPS 979
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6901 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6989 instances, 6840 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 757543, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064954s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.2%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 8, deltaY = 25, maxDist = 3.
+PHY-3001 : Final: Len = 758311, Over = 0
+PHY-3001 : End incremental legalization;  0.397930s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (117.8%)
+
+OPT-0007 : Iter 1: improved WNS -3745 TNS -2239978 NUM_FEPS 979 with 43 cells processed and 2929 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6901 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6989 instances, 6840 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3710 pins
+PHY-3001 : Found 488 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 758373, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064013s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.6%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 2, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 758339, Over = 0
+PHY-3001 : End incremental legalization;  0.399791s wall, 0.437500s user + 0.046875s system = 0.484375s CPU (121.2%)
+
+OPT-0007 : Iter 2: improved WNS -3745 TNS -2239620 NUM_FEPS 979 with 10 cells processed and 310 slack improved
+OPT-0007 : Iter 3: improved WNS -3745 TNS -2239620 NUM_FEPS 979 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  3.075445s wall, 3.312500s user + 0.046875s system = 3.359375s CPU (109.2%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 745, peak = 756.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17468 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.758040s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15811/17647.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 937000, over cnt = 171(0%), over = 247, worst = 5
+PHY-1002 : len = 937064, over cnt = 108(0%), over = 123, worst = 3
+PHY-1002 : len = 937976, over cnt = 33(0%), over = 38, worst = 3
+PHY-1002 : len = 938576, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 938912, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.861440s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (108.8%)
+
+PHY-1001 : Congestion index: top1 = 55.93, top5 = 50.36, top10 = 47.61, top15 = 45.66.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17468 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.734265s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.0%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -3745 TNS -2242788 NUM_FEPS 979
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 55.517241
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -3745ps with logic level 6 
+RUN-1001 :       #2 path slack -3725ps with logic level 5 
+RUN-1001 :       #3 path slack -3723ps with logic level 6 
+RUN-1001 :       #4 path slack -3701ps with logic level 5 
+RUN-1001 :       #5 path slack -3689ps with logic level 6 
+RUN-1001 :       #6 path slack -3689ps with logic level 6 
+RUN-1001 :       #7 path slack -3679ps with logic level 4 
+RUN-1001 :       #8 path slack -3675ps with logic level 5 
+RUN-1001 :       #9 path slack -3661ps with logic level 4 
+RUN-1001 :       #10 path slack -3661ps with logic level 4 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17647 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17647 nets
+OPT-1001 : End physical optimization;  24.563006s wall, 26.218750s user + 0.437500s system = 26.656250s CPU (108.5%)
+
+RUN-1003 : finish command "place" in  70.160946s wall, 102.437500s user + 6.578125s system = 109.015625s CPU (155.4%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 608 MB, peak memory is 756 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.711809s wall, 3.000000s user + 0.000000s system = 3.000000s CPU (175.3%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 610 MB, peak memory is 756 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6991 instances
+RUN-1001 : 3422 mslices, 3418 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17647 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10035 nets have 2 pins
+RUN-1001 : 5720 nets have [3 - 5] pins
+RUN-1001 : 1193 nets have [6 - 10] pins
+RUN-1001 : 298 nets have [11 - 20] pins
+RUN-1001 : 372 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75099, tnet num: 17469, tinst num: 6989, tnode num: 97809, tedge num: 126105.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.629146s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (98.8%)
+
+RUN-1004 : used memory is 609 MB, reserved memory is 592 MB, peak memory is 756 MB
+PHY-1001 : 3422 mslices, 3418 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17469 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[5] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 866704, over cnt = 2787(7%), over = 4774, worst = 8
+PHY-1002 : len = 884728, over cnt = 1776(5%), over = 2648, worst = 8
+PHY-1002 : len = 909456, over cnt = 527(1%), over = 786, worst = 8
+PHY-1002 : len = 921424, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 921824, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.877192s wall, 3.984375s user + 0.046875s system = 4.031250s CPU (140.1%)
+
+PHY-1001 : Congestion index: top1 = 55.30, top5 = 50.30, top10 = 47.40, top15 = 45.28.
+PHY-1001 : End global routing;  3.207824s wall, 4.312500s user + 0.046875s system = 4.359375s CPU (135.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 722, reserve = 723, peak = 756.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 996, reserve = 995, peak = 996.
+PHY-1001 : End build detailed router design. 3.974801s wall, 3.937500s user + 0.031250s system = 3.968750s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 272432, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.029994s wall, 5.015625s user + 0.015625s system = 5.031250s CPU (100.0%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 272488, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.432424s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.2%)
+
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1032, peak = 1032.
+PHY-1001 : End phase 1; 5.475283s wall, 5.453125s user + 0.015625s system = 5.468750s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 38% nets.
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 55% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.43348e+06, over cnt = 1690(0%), over = 1700, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1049, peak = 1050.
+PHY-1001 : End initial routed; 28.091038s wall, 63.031250s user + 0.343750s system = 63.375000s CPU (225.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1977/16574(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.225   |  -3488.147  |  982  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.298532s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1070, reserve = 1069, peak = 1070.
+PHY-1001 : End phase 2; 31.389632s wall, 66.328125s user + 0.343750s system = 66.671875s CPU (212.4%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 69 pins with SWNS -5.998ns STNS -3479.701ns FEP 982.
+PHY-1001 : End OPT Iter 1; 0.390495s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.0%)
+
+PHY-1022 : len = 2.43392e+06, over cnt = 1747(0%), over = 1757, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.653229s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (100.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.40295e+06, over cnt = 630(0%), over = 632, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.526237s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (175.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.39933e+06, over cnt = 149(0%), over = 149, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.077236s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (137.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.39985e+06, over cnt = 36(0%), over = 36, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.494297s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (117.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.40011e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.347006s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (117.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.40046e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.397736s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.40046e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.491471s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.40046e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.867054s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.40045e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.178795s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (113.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.4005e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.203481s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.4005e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.181152s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.5%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.4005e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.191666s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.8%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.40049e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.354230s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (97.0%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.40049e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.172287s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.40052e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 14; 0.163989s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (95.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1977/16574(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -5.998   |  -3482.198  |  982  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.305679s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 573 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.291167s wall, 2.281250s user + 0.015625s system = 2.296875s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1173, reserve = 1175, peak = 1173.
+PHY-1001 : End phase 3; 13.324983s wall, 15.031250s user + 0.015625s system = 15.046875s CPU (112.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 22 pins with SWNS -5.998ns STNS -3481.485ns FEP 982.
+PHY-1001 : End OPT Iter 1; 0.240429s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (104.0%)
+
+PHY-1022 : len = 2.40058e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.503318s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (99.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.998ns, -3481.485ns, 982}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.40046e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.169960s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1977/16574(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -5.998   |  -3482.066  |  982  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.325194s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 573 feed throughs used by 421 nets
+PHY-1001 : End commit to database; 2.378113s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1183, reserve = 1186, peak = 1183.
+PHY-1001 : End phase 4; 6.425760s wall, 6.406250s user + 0.000000s system = 6.406250s CPU (99.7%)
+
+PHY-1003 : Routed, final wirelength = 2.40046e+06
+PHY-1001 : Current memory(MB): used = 1188, reserve = 1191, peak = 1188.
+PHY-1001 : End export database. 0.063957s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.7%)
+
+PHY-1001 : End detail routing;  61.044782s wall, 97.625000s user + 0.406250s system = 98.031250s CPU (160.6%)
+
+RUN-1003 : finish command "route" in  67.002641s wall, 104.640625s user + 0.500000s system = 105.140625s CPU (156.9%)
+
+RUN-1004 : used memory is 1050 MB, reserved memory is 1056 MB, peak memory is 1188 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10415   out of  19600   53.14%
+#reg                     9410   out of  19600   48.01%
+#le                     12802
+  #lut only              3392   out of  12802   26.50%
+  #reg only              2387   out of  12802   18.65%
+  #lut&reg               7023   out of  12802   54.86%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                    Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                      1781
+#2        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                1428
+#3        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                 1407
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                      968
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/reg6_syn_49.q0     136
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                 73
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                72
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                      25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                      4
+#10       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_330.f1            3
+#11       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             exdev_ctl_a/u_ADconfig/reg0_syn_177.f0    2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                     1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                     1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                     1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                      1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P147       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P109       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P104       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12802  |9394    |1021    |9440    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |523    |416     |23      |435     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |102    |90      |4       |89      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |33     |33      |0       |22      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10     |10      |0       |8       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |761    |376     |96      |572     |0       |0       |
+|    u_ADconfig                |AD_config            |185    |133     |25      |137     |0       |0       |
+|    u_gen_sp                  |gen_sp               |257    |166     |71      |116     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |755    |447     |96      |563     |0       |0       |
+|    u_ADconfig                |AD_config            |172    |129     |25      |126     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |171     |71      |117     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3123   |2356    |303     |2116    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |162    |96      |14      |131     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|    u_sort                    |sort                 |2945   |2249    |289     |1969    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |3      |3       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |0       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2534   |1976    |253     |1624    |22      |1       |
+|        channelPart           |channel_part_8478    |175    |161     |3       |143     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
+|        ram_switch            |ram_switch           |1976   |1497    |197     |1220    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |249    |219     |27      |132     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |9       |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|          insert              |insert               |989    |546     |170     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |738    |732     |0       |396     |0       |0       |
+|        read_ram_i            |read_ram             |288    |244     |44      |183     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |231    |191     |40      |151     |0       |0       |
+|          read_ram_data       |read_ram_data        |57     |53      |4       |32      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |337    |223     |36      |282     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3520   |2857    |340     |2051    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |1       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |166    |104     |17      |132     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |3318   |2748    |323     |1883    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |3      |3       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2887   |2405    |281     |1550    |22      |0       |
+|        channelPart           |channel_part_8478    |254    |249     |3       |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |42      |0       |0       |
+|        ram_switch            |ram_switch           |2188   |1817    |197     |1133    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |244    |217     |27      |126     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |10     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |17      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |14      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|          insert              |insert               |944    |600     |170     |635     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1000   |1000    |0       |372     |0       |0       |
+|        read_ram_i            |read_ram_rev         |345    |253     |72      |194     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |291    |216     |64      |157     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |54     |37      |8       |37      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9973  
+    #2         2       3729  
+    #3         3       1430  
+    #4         4       558   
+    #5        5-10     1260  
+    #6       11-50     576   
+    #7       51-100     24   
+    #8        >500      1    
+  Average     2.96           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.093348s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (172.4%)
+
+RUN-1004 : used memory is 1052 MB, reserved memory is 1058 MB, peak memory is 1188 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75099, tnet num: 17469, tinst num: 6989, tnode num: 97809, tedge num: 126105.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.645376s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.7%)
+
+RUN-1004 : used memory is 1056 MB, reserved memory is 1062 MB, peak memory is 1188 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17469 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.521773s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (100.6%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1103 MB, peak memory is 1188 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6989
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17647, pip num: 177098
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 573
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3246 valid insts, and 489338 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.065204s wall, 67.156250s user + 0.062500s system = 67.218750s CPU (667.8%)
+
+RUN-1004 : used memory is 1282 MB, reserved memory is 1277 MB, peak memory is 1397 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_114530.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_115302.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_115302.log
new file mode 100644
index 0000000..bbeab1a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_115302.log
@@ -0,0 +1,3363 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:53:02 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.212464s wall, 2.156250s user + 0.062500s system = 2.218750s CPU (100.3%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing ultra"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   ultra    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17833 instances
+RUN-0007 : 7532 luts, 9084 seqs, 696 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20398 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13452 nets have 2 pins
+RUN-1001 : 5463 nets have [3 - 5] pins
+RUN-1001 : 1067 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17831 instances, 7532 luts, 9084 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5973 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.143676s wall, 1.093750s user + 0.046875s system = 1.140625s CPU (99.7%)
+
+RUN-1004 : used memory is 540 MB, reserved memory is 516 MB, peak memory is 540 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.928589s wall, 1.875000s user + 0.062500s system = 1.937500s CPU (100.5%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.07528e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17831.
+PHY-3001 : Level 1 #clusters 2310.
+PHY-3001 : End clustering;  0.122451s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (153.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35102e+06, overlap = 477.938
+PHY-3002 : Step(2): len = 1.09932e+06, overlap = 531.031
+PHY-3002 : Step(3): len = 883253, overlap = 639.719
+PHY-3002 : Step(4): len = 790097, overlap = 689.688
+PHY-3002 : Step(5): len = 625432, overlap = 819.562
+PHY-3002 : Step(6): len = 550274, overlap = 873.188
+PHY-3002 : Step(7): len = 466520, overlap = 967.344
+PHY-3002 : Step(8): len = 427561, overlap = 1013.62
+PHY-3002 : Step(9): len = 376653, overlap = 1054
+PHY-3002 : Step(10): len = 338540, overlap = 1114.16
+PHY-3002 : Step(11): len = 310322, overlap = 1201.41
+PHY-3002 : Step(12): len = 282549, overlap = 1247.91
+PHY-3002 : Step(13): len = 257828, overlap = 1280.44
+PHY-3002 : Step(14): len = 234472, overlap = 1320.06
+PHY-3002 : Step(15): len = 218404, overlap = 1344.53
+PHY-3002 : Step(16): len = 202627, overlap = 1351.53
+PHY-3002 : Step(17): len = 192029, overlap = 1408.31
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.29871e-06
+PHY-3002 : Step(18): len = 194314, overlap = 1322.66
+PHY-3002 : Step(19): len = 227766, overlap = 1257.75
+PHY-3002 : Step(20): len = 231119, overlap = 1217.62
+PHY-3002 : Step(21): len = 235885, overlap = 1168.19
+PHY-3002 : Step(22): len = 232706, overlap = 1175.44
+PHY-3002 : Step(23): len = 232933, overlap = 1153.75
+PHY-3002 : Step(24): len = 226991, overlap = 1149.75
+PHY-3002 : Step(25): len = 226856, overlap = 1120.03
+PHY-3002 : Step(26): len = 223113, overlap = 1101.16
+PHY-3002 : Step(27): len = 223003, overlap = 1098.41
+PHY-3002 : Step(28): len = 220113, overlap = 1092.41
+PHY-3002 : Step(29): len = 220523, overlap = 1091.88
+PHY-3002 : Step(30): len = 217573, overlap = 1063.34
+PHY-3002 : Step(31): len = 215932, overlap = 1054.72
+PHY-3002 : Step(32): len = 211862, overlap = 1037.91
+PHY-3002 : Step(33): len = 210610, overlap = 1023.72
+PHY-3002 : Step(34): len = 206603, overlap = 1016.22
+PHY-3002 : Step(35): len = 205555, overlap = 1018.91
+PHY-3002 : Step(36): len = 202761, overlap = 1018.09
+PHY-3002 : Step(37): len = 201939, overlap = 1023.34
+PHY-3002 : Step(38): len = 199776, overlap = 1033.09
+PHY-3002 : Step(39): len = 197931, overlap = 1047.38
+PHY-3002 : Step(40): len = 196355, overlap = 1050.38
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.59743e-06
+PHY-3002 : Step(41): len = 201833, overlap = 1034.97
+PHY-3002 : Step(42): len = 214926, overlap = 991.344
+PHY-3002 : Step(43): len = 219847, overlap = 936.406
+PHY-3002 : Step(44): len = 224027, overlap = 926.875
+PHY-3002 : Step(45): len = 226582, overlap = 904.625
+PHY-3002 : Step(46): len = 228720, overlap = 901.594
+PHY-3002 : Step(47): len = 226618, overlap = 901.719
+PHY-3002 : Step(48): len = 226367, overlap = 900.188
+PHY-3002 : Step(49): len = 225338, overlap = 894.219
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.19486e-06
+PHY-3002 : Step(50): len = 235684, overlap = 894.969
+PHY-3002 : Step(51): len = 255509, overlap = 841.312
+PHY-3002 : Step(52): len = 264304, overlap = 795.625
+PHY-3002 : Step(53): len = 267386, overlap = 784.094
+PHY-3002 : Step(54): len = 267588, overlap = 773.062
+PHY-3002 : Step(55): len = 267980, overlap = 768.812
+PHY-3002 : Step(56): len = 268387, overlap = 766.125
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.03897e-05
+PHY-3002 : Step(57): len = 288676, overlap = 731.469
+PHY-3002 : Step(58): len = 313788, overlap = 626.938
+PHY-3002 : Step(59): len = 321306, overlap = 586.719
+PHY-3002 : Step(60): len = 322627, overlap = 564.875
+PHY-3002 : Step(61): len = 319961, overlap = 577.281
+PHY-3002 : Step(62): len = 319051, overlap = 568.875
+PHY-3002 : Step(63): len = 318351, overlap = 558.781
+PHY-3002 : Step(64): len = 318169, overlap = 557.219
+PHY-3002 : Step(65): len = 316569, overlap = 566.312
+PHY-3002 : Step(66): len = 316488, overlap = 566.562
+PHY-3002 : Step(67): len = 315453, overlap = 575.875
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.07794e-05
+PHY-3002 : Step(68): len = 337835, overlap = 490.938
+PHY-3002 : Step(69): len = 354444, overlap = 409.062
+PHY-3002 : Step(70): len = 359997, overlap = 394.562
+PHY-3002 : Step(71): len = 362434, overlap = 385.188
+PHY-3002 : Step(72): len = 363292, overlap = 392.219
+PHY-3002 : Step(73): len = 365476, overlap = 395.469
+PHY-3002 : Step(74): len = 366194, overlap = 388.969
+PHY-3002 : Step(75): len = 366070, overlap = 394.188
+PHY-3002 : Step(76): len = 366701, overlap = 377.438
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.15588e-05
+PHY-3002 : Step(77): len = 388358, overlap = 334.594
+PHY-3002 : Step(78): len = 405913, overlap = 304.031
+PHY-3002 : Step(79): len = 407409, overlap = 290.312
+PHY-3002 : Step(80): len = 410625, overlap = 281.812
+PHY-3002 : Step(81): len = 413301, overlap = 275.25
+PHY-3002 : Step(82): len = 417831, overlap = 250.719
+PHY-3002 : Step(83): len = 414765, overlap = 249.969
+PHY-3002 : Step(84): len = 414176, overlap = 253.562
+PHY-3002 : Step(85): len = 414039, overlap = 260.875
+PHY-3002 : Step(86): len = 414658, overlap = 266.344
+PHY-3002 : Step(87): len = 413132, overlap = 266.562
+PHY-3002 : Step(88): len = 413487, overlap = 250.781
+PHY-3002 : Step(89): len = 412700, overlap = 255.75
+PHY-3002 : Step(90): len = 413892, overlap = 252.719
+PHY-3002 : Step(91): len = 412847, overlap = 261.438
+PHY-3002 : Step(92): len = 413771, overlap = 249.969
+PHY-3002 : Step(93): len = 415217, overlap = 241.188
+PHY-3002 : Step(94): len = 417816, overlap = 221.094
+PHY-3002 : Step(95): len = 415137, overlap = 205.781
+PHY-3002 : Step(96): len = 415812, overlap = 205.719
+PHY-3002 : Step(97): len = 415635, overlap = 199.188
+PHY-3002 : Step(98): len = 416417, overlap = 207.219
+PHY-3002 : Step(99): len = 413401, overlap = 214.656
+PHY-3002 : Step(100): len = 413828, overlap = 232.969
+PHY-3002 : Step(101): len = 413525, overlap = 237.594
+PHY-3002 : Step(102): len = 414253, overlap = 233.688
+PHY-3002 : Step(103): len = 412302, overlap = 222.156
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.31177e-05
+PHY-3002 : Step(104): len = 429849, overlap = 228.031
+PHY-3002 : Step(105): len = 439939, overlap = 231.656
+PHY-3002 : Step(106): len = 440016, overlap = 205.406
+PHY-3002 : Step(107): len = 441217, overlap = 196.688
+PHY-3002 : Step(108): len = 443931, overlap = 191.812
+PHY-3002 : Step(109): len = 447755, overlap = 197.594
+PHY-3002 : Step(110): len = 446388, overlap = 194.938
+PHY-3002 : Step(111): len = 447981, overlap = 189.938
+PHY-3002 : Step(112): len = 446756, overlap = 187
+PHY-3002 : Step(113): len = 447476, overlap = 180.906
+PHY-3002 : Step(114): len = 445484, overlap = 176.406
+PHY-3002 : Step(115): len = 446114, overlap = 173.594
+PHY-3002 : Step(116): len = 445627, overlap = 169.625
+PHY-3002 : Step(117): len = 446702, overlap = 165.938
+PHY-3002 : Step(118): len = 445686, overlap = 172.906
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000166235
+PHY-3002 : Step(119): len = 458068, overlap = 170.031
+PHY-3002 : Step(120): len = 465015, overlap = 168.312
+PHY-3002 : Step(121): len = 465550, overlap = 167.656
+PHY-3002 : Step(122): len = 466642, overlap = 159.688
+PHY-3002 : Step(123): len = 469200, overlap = 163.188
+PHY-3002 : Step(124): len = 471486, overlap = 161.5
+PHY-3002 : Step(125): len = 471104, overlap = 157.25
+PHY-3002 : Step(126): len = 472151, overlap = 157.688
+PHY-3002 : Step(127): len = 473433, overlap = 161.062
+PHY-3002 : Step(128): len = 474772, overlap = 155.719
+PHY-3002 : Step(129): len = 473928, overlap = 153.688
+PHY-3002 : Step(130): len = 474784, overlap = 161.5
+PHY-3002 : Step(131): len = 475838, overlap = 160.062
+PHY-3002 : Step(132): len = 476978, overlap = 156.562
+PHY-3002 : Step(133): len = 475822, overlap = 158.969
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000314511
+PHY-3002 : Step(134): len = 483264, overlap = 162.969
+PHY-3002 : Step(135): len = 490353, overlap = 159.781
+PHY-3002 : Step(136): len = 492485, overlap = 160.281
+PHY-3002 : Step(137): len = 494376, overlap = 159.5
+PHY-3002 : Step(138): len = 497258, overlap = 155.938
+PHY-3002 : Step(139): len = 499111, overlap = 157.031
+PHY-3002 : Step(140): len = 497298, overlap = 157.438
+PHY-3002 : Step(141): len = 496889, overlap = 154.469
+PHY-3002 : Step(142): len = 498371, overlap = 158.844
+PHY-3002 : Step(143): len = 499391, overlap = 156.219
+PHY-3002 : Step(144): len = 498163, overlap = 154.062
+PHY-3002 : Step(145): len = 498170, overlap = 158.125
+PHY-3002 : Step(146): len = 499779, overlap = 159.781
+PHY-3002 : Step(147): len = 500515, overlap = 154.844
+PHY-3002 : Step(148): len = 499163, overlap = 159.156
+PHY-3002 : Step(149): len = 498858, overlap = 158.562
+PHY-3002 : Step(150): len = 499438, overlap = 156.719
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000623498
+PHY-3002 : Step(151): len = 505269, overlap = 154.188
+PHY-3002 : Step(152): len = 513133, overlap = 151.188
+PHY-3002 : Step(153): len = 514438, overlap = 142.156
+PHY-3002 : Step(154): len = 516020, overlap = 135.375
+PHY-3002 : Step(155): len = 518270, overlap = 141.188
+PHY-3002 : Step(156): len = 520480, overlap = 141.844
+PHY-3002 : Step(157): len = 519830, overlap = 135.344
+PHY-3002 : Step(158): len = 519992, overlap = 136.594
+PHY-3002 : Step(159): len = 521016, overlap = 137.938
+PHY-3002 : Step(160): len = 521266, overlap = 138.031
+PHY-3002 : Step(161): len = 520104, overlap = 135.188
+PHY-3002 : Step(162): len = 519624, overlap = 131.938
+PHY-3002 : Step(163): len = 520207, overlap = 137.656
+PHY-3002 : Step(164): len = 520399, overlap = 138.75
+PHY-3002 : Step(165): len = 519104, overlap = 140.781
+PHY-3002 : Step(166): len = 518571, overlap = 137.719
+PHY-3002 : Step(167): len = 519428, overlap = 135.75
+PHY-3002 : Step(168): len = 519928, overlap = 131.938
+PHY-3002 : Step(169): len = 518993, overlap = 133.656
+PHY-3002 : Step(170): len = 518549, overlap = 135.219
+PHY-3002 : Step(171): len = 519593, overlap = 131.625
+PHY-3002 : Step(172): len = 520202, overlap = 127.031
+PHY-3002 : Step(173): len = 519173, overlap = 130.031
+PHY-3002 : Step(174): len = 518967, overlap = 130
+PHY-3002 : Step(175): len = 519280, overlap = 132
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00118544
+PHY-3002 : Step(176): len = 522728, overlap = 128.312
+PHY-3002 : Step(177): len = 527056, overlap = 124.906
+PHY-3002 : Step(178): len = 527910, overlap = 123.156
+PHY-3002 : Step(179): len = 528376, overlap = 124.5
+PHY-3002 : Step(180): len = 529088, overlap = 119.219
+PHY-3002 : Step(181): len = 529726, overlap = 116.25
+PHY-3002 : Step(182): len = 529709, overlap = 122
+PHY-3002 : Step(183): len = 529986, overlap = 120.719
+PHY-3002 : Step(184): len = 530585, overlap = 119.125
+PHY-3002 : Step(185): len = 530930, overlap = 118.406
+PHY-3002 : Step(186): len = 531228, overlap = 117.594
+PHY-3002 : Step(187): len = 531357, overlap = 118.531
+PHY-3002 : Step(188): len = 531293, overlap = 115.719
+PHY-3002 : Step(189): len = 531172, overlap = 114.031
+PHY-3002 : Step(190): len = 530781, overlap = 111.906
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00191805
+PHY-3002 : Step(191): len = 531720, overlap = 114.25
+PHY-3002 : Step(192): len = 533057, overlap = 109.656
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.013413s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (116.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 680352, over cnt = 1344(3%), over = 5801, worst = 47
+PHY-1001 : End global iterations;  0.691523s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (149.1%)
+
+PHY-1001 : Congestion index: top1 = 73.51, top5 = 56.05, top10 = 48.07, top15 = 43.18.
+PHY-3001 : End congestion estimation;  0.890362s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (138.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.114924s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000142626
+PHY-3002 : Step(193): len = 621062, overlap = 63.125
+PHY-3002 : Step(194): len = 623082, overlap = 55.3125
+PHY-3002 : Step(195): len = 613061, overlap = 53.3125
+PHY-3002 : Step(196): len = 610779, overlap = 46.1562
+PHY-3002 : Step(197): len = 606560, overlap = 41.9688
+PHY-3002 : Step(198): len = 602724, overlap = 42.9375
+PHY-3002 : Step(199): len = 598435, overlap = 46.2812
+PHY-3002 : Step(200): len = 597710, overlap = 46.9062
+PHY-3002 : Step(201): len = 592769, overlap = 49.125
+PHY-3002 : Step(202): len = 589986, overlap = 50.625
+PHY-3002 : Step(203): len = 588162, overlap = 49.9375
+PHY-3002 : Step(204): len = 584816, overlap = 46.5312
+PHY-3002 : Step(205): len = 582523, overlap = 46.75
+PHY-3002 : Step(206): len = 580427, overlap = 48.9062
+PHY-3002 : Step(207): len = 579916, overlap = 51.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000285251
+PHY-3002 : Step(208): len = 580637, overlap = 50.2812
+PHY-3002 : Step(209): len = 583985, overlap = 46.875
+PHY-3002 : Step(210): len = 587431, overlap = 46.4688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000570503
+PHY-3002 : Step(211): len = 593264, overlap = 45.0625
+PHY-3002 : Step(212): len = 603955, overlap = 43.7188
+PHY-3002 : Step(213): len = 613173, overlap = 42.5625
+PHY-3002 : Step(214): len = 609843, overlap = 44
+PHY-3002 : Step(215): len = 607828, overlap = 45.2188
+PHY-3002 : Step(216): len = 605336, overlap = 47.4062
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 129/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 689400, over cnt = 2441(6%), over = 10137, worst = 45
+PHY-1001 : End global iterations;  1.463656s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (136.6%)
+
+PHY-1001 : Congestion index: top1 = 80.32, top5 = 62.73, top10 = 54.44, top15 = 49.43.
+PHY-3001 : End congestion estimation;  1.756873s wall, 2.250000s user + 0.031250s system = 2.281250s CPU (129.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.916522s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000113231
+PHY-3002 : Step(217): len = 602205, overlap = 279.781
+PHY-3002 : Step(218): len = 607325, overlap = 232.5
+PHY-3002 : Step(219): len = 599389, overlap = 200.188
+PHY-3002 : Step(220): len = 595133, overlap = 189.062
+PHY-3002 : Step(221): len = 591140, overlap = 182.844
+PHY-3002 : Step(222): len = 586915, overlap = 175.594
+PHY-3002 : Step(223): len = 583760, overlap = 176.219
+PHY-3002 : Step(224): len = 580389, overlap = 167.688
+PHY-3002 : Step(225): len = 578280, overlap = 163.469
+PHY-3002 : Step(226): len = 578178, overlap = 166.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000226462
+PHY-3002 : Step(227): len = 576562, overlap = 160.562
+PHY-3002 : Step(228): len = 577932, overlap = 156.5
+PHY-3002 : Step(229): len = 578272, overlap = 155.219
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000452925
+PHY-3002 : Step(230): len = 585584, overlap = 147.375
+PHY-3002 : Step(231): len = 594281, overlap = 141.75
+PHY-3002 : Step(232): len = 597320, overlap = 134.156
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000905849
+PHY-3002 : Step(233): len = 599989, overlap = 124.906
+PHY-3002 : Step(234): len = 604965, overlap = 122.625
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.477494s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (99.4%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 564 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 479.97 peak overflow 4.84
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 714/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 699272, over cnt = 2678(7%), over = 9528, worst = 32
+PHY-1001 : End global iterations;  1.111863s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (150.4%)
+
+PHY-1001 : Congestion index: top1 = 68.32, top5 = 54.55, top10 = 49.05, top15 = 45.61.
+PHY-1001 : End incremental global routing;  1.416716s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (140.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.903003s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.4%)
+
+OPT-1001 : 45 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17701 has valid locations, 402 needs to be replaced
+PHY-3001 : design contains 18188 instances, 7629 luts, 9344 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6126 pins
+PHY-3001 : Found 1239 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 628670
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15836/20755.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 718440, over cnt = 2739(7%), over = 9654, worst = 31
+PHY-1001 : End global iterations;  0.246986s wall, 0.359375s user + 0.015625s system = 0.375000s CPU (151.8%)
+
+PHY-1001 : Congestion index: top1 = 67.97, top5 = 54.61, top10 = 49.09, top15 = 45.67.
+PHY-3001 : End congestion estimation;  0.499591s wall, 0.609375s user + 0.015625s system = 0.625000s CPU (125.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87029, tnet num: 20577, tinst num: 18188, tnode num: 118041, tedge num: 139592.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.476718s wall, 1.437500s user + 0.046875s system = 1.484375s CPU (100.5%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 622 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20577 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.427411s wall, 2.375000s user + 0.046875s system = 2.421875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(235): len = 627986, overlap = 0.25
+PHY-3002 : Step(236): len = 628360, overlap = 0.25
+PHY-3002 : Step(237): len = 628475, overlap = 0.25
+PHY-3002 : Step(238): len = 628466, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15906/20755.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 715088, over cnt = 2741(7%), over = 9728, worst = 31
+PHY-1001 : End global iterations;  0.226723s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (117.2%)
+
+PHY-1001 : Congestion index: top1 = 69.07, top5 = 55.17, top10 = 49.60, top15 = 46.05.
+PHY-3001 : End congestion estimation;  0.475932s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (108.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20577 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.920971s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000372304
+PHY-3002 : Step(239): len = 628789, overlap = 125.406
+PHY-3002 : Step(240): len = 629080, overlap = 125.562
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000744608
+PHY-3002 : Step(241): len = 629257, overlap = 125.656
+PHY-3002 : Step(242): len = 629703, overlap = 125.969
+PHY-3001 : Final: Len = 629703, Over = 125.969
+PHY-3001 : End incremental placement;  4.959776s wall, 5.328125s user + 0.187500s system = 5.515625s CPU (111.2%)
+
+OPT-1001 : Total overflow 486.97 peak overflow 4.91
+OPT-1001 : End high-fanout net optimization;  7.813212s wall, 8.828125s user + 0.218750s system = 9.046875s CPU (115.8%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 711, peak = 742.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15920/20755.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 717848, over cnt = 2682(7%), over = 9013, worst = 31
+PHY-1002 : len = 757688, over cnt = 1916(5%), over = 5037, worst = 18
+PHY-1002 : len = 794952, over cnt = 865(2%), over = 1958, worst = 16
+PHY-1002 : len = 813936, over cnt = 370(1%), over = 708, worst = 14
+PHY-1002 : len = 823408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.595972s wall, 2.078125s user + 0.000000s system = 2.078125s CPU (130.2%)
+
+PHY-1001 : Congestion index: top1 = 56.01, top5 = 48.50, top10 = 45.10, top15 = 42.94.
+OPT-1001 : End congestion update;  1.854969s wall, 2.343750s user + 0.000000s system = 2.343750s CPU (126.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20577 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.813947s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.8%)
+
+OPT-0007 : Start: WNS -5019 TNS -2584415 NUM_FEPS 1051
+OPT-0007 : Iter 1: improved WNS -4519 TNS -2542261 NUM_FEPS 1051 with 47 cells processed and 1200 slack improved
+OPT-0007 : Iter 2: improved WNS -4519 TNS -2538005 NUM_FEPS 1051 with 92 cells processed and 1066 slack improved
+OPT-0007 : Iter 3: improved WNS -4519 TNS -2537505 NUM_FEPS 1051 with 39 cells processed and 250 slack improved
+OPT-0007 : Iter 4: improved WNS -4519 TNS -2537505 NUM_FEPS 1051 with 14 cells processed and 50 slack improved
+OPT-0007 : Iter 5: improved WNS -4369 TNS -2487963 NUM_FEPS 1051 with 1 cells processed and 150 slack improved
+OPT-0007 : Iter 6: improved WNS -4369 TNS -2487963 NUM_FEPS 1051 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  3.338819s wall, 3.828125s user + 0.000000s system = 3.828125s CPU (114.7%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 689, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16164/20756.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 827080, over cnt = 137(0%), over = 255, worst = 8
+PHY-1002 : len = 827824, over cnt = 80(0%), over = 104, worst = 5
+PHY-1002 : len = 828912, over cnt = 20(0%), over = 22, worst = 2
+PHY-1002 : len = 829368, over cnt = 4(0%), over = 5, worst = 2
+PHY-1002 : len = 829512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.718810s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (108.7%)
+
+PHY-1001 : Congestion index: top1 = 56.10, top5 = 48.64, top10 = 45.24, top15 = 43.11.
+OPT-1001 : End congestion update;  0.982189s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (106.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20578 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.808506s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.5%)
+
+OPT-0007 : Start: WNS -4369 TNS -2487963 NUM_FEPS 1051
+OPT-0007 : Iter 1: improved WNS -4269 TNS -2488715 NUM_FEPS 1051 with 44 cells processed and 2350 slack improved
+OPT-0007 : Iter 2: improved WNS -4269 TNS -2488715 NUM_FEPS 1051 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.929634s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (102.8%)
+
+OPT-1001 : Current memory(MB): used = 701, reserve = 689, peak = 742.
+OPT-1001 : End physical optimization;  14.864057s wall, 16.453125s user + 0.281250s system = 16.734375s CPU (112.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7629 LUT to BLE ...
+SYN-4008 : Packed 7629 LUT and 3144 SEQ to BLE.
+SYN-4003 : Packing 6201 remaining SEQ's ...
+SYN-4005 : Packed 3737 SEQ with LUT/SLICE
+SYN-4006 : 1050 single LUT's are left
+SYN-4006 : 2464 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10093/13906 primitive instances ...
+PHY-3001 : End packing;  1.701100s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (100.1%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7001 instances
+RUN-1001 : 3426 mslices, 3427 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17731 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10047 nets have 2 pins
+RUN-1001 : 5752 nets have [3 - 5] pins
+RUN-1001 : 1189 nets have [6 - 10] pins
+RUN-1001 : 378 nets have [11 - 20] pins
+RUN-1001 : 333 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6999 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3648 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 640391, Over = 326.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7402/17731.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 782464, over cnt = 1827(5%), over = 3029, worst = 8
+PHY-1002 : len = 788360, over cnt = 1397(3%), over = 2090, worst = 7
+PHY-1002 : len = 803968, over cnt = 577(1%), over = 834, worst = 7
+PHY-1002 : len = 815624, over cnt = 127(0%), over = 172, worst = 4
+PHY-1002 : len = 818744, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.445148s wall, 2.000000s user + 0.031250s system = 2.031250s CPU (140.6%)
+
+PHY-1001 : Congestion index: top1 = 58.92, top5 = 50.53, top10 = 46.58, top15 = 44.01.
+PHY-3001 : End congestion estimation;  1.836541s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (132.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75094, tnet num: 17553, tinst num: 6999, tnode num: 97895, tedge num: 126073.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.641989s wall, 1.609375s user + 0.031250s system = 1.640625s CPU (99.9%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 614 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.576256s wall, 2.515625s user + 0.062500s system = 2.578125s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.0051e-05
+PHY-3002 : Step(243): len = 624986, overlap = 319.5
+PHY-3002 : Step(244): len = 616541, overlap = 331.25
+PHY-3002 : Step(245): len = 612124, overlap = 342.5
+PHY-3002 : Step(246): len = 609476, overlap = 346.75
+PHY-3002 : Step(247): len = 608588, overlap = 363.5
+PHY-3002 : Step(248): len = 606209, overlap = 365.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000100102
+PHY-3002 : Step(249): len = 609671, overlap = 362
+PHY-3002 : Step(250): len = 615273, overlap = 348.5
+PHY-3002 : Step(251): len = 614791, overlap = 342.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000200204
+PHY-3002 : Step(252): len = 622861, overlap = 335.75
+PHY-3002 : Step(253): len = 632014, overlap = 319.75
+PHY-3002 : Step(254): len = 631178, overlap = 312.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.331390s wall, 0.359375s user + 0.562500s system = 0.921875s CPU (278.2%)
+
+PHY-3001 : Trial Legalized: Len = 739787
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 817/17731.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 858920, over cnt = 2700(7%), over = 4707, worst = 8
+PHY-1002 : len = 875808, over cnt = 1731(4%), over = 2624, worst = 7
+PHY-1002 : len = 904680, over cnt = 383(1%), over = 542, worst = 5
+PHY-1002 : len = 911032, over cnt = 109(0%), over = 144, worst = 5
+PHY-1002 : len = 913592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.444417s wall, 3.437500s user + 0.078125s system = 3.515625s CPU (143.8%)
+
+PHY-1001 : Congestion index: top1 = 54.18, top5 = 49.70, top10 = 46.97, top15 = 45.11.
+PHY-3001 : End congestion estimation;  2.915625s wall, 3.921875s user + 0.078125s system = 4.000000s CPU (137.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.911016s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000219533
+PHY-3002 : Step(255): len = 687486, overlap = 97.75
+PHY-3002 : Step(256): len = 668641, overlap = 153
+PHY-3002 : Step(257): len = 656846, overlap = 196.5
+PHY-3002 : Step(258): len = 650869, overlap = 229.5
+PHY-3002 : Step(259): len = 648357, overlap = 253.5
+PHY-3002 : Step(260): len = 646263, overlap = 254.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000439065
+PHY-3002 : Step(261): len = 653493, overlap = 251.25
+PHY-3002 : Step(262): len = 660407, overlap = 246.75
+PHY-3002 : Step(263): len = 665288, overlap = 239
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00087813
+PHY-3002 : Step(264): len = 668785, overlap = 235
+PHY-3002 : Step(265): len = 674761, overlap = 230.75
+PHY-3002 : Step(266): len = 683295, overlap = 215.75
+PHY-3002 : Step(267): len = 684460, overlap = 215.75
+PHY-3002 : Step(268): len = 684805, overlap = 219
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.035132s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (88.9%)
+
+PHY-3001 : Legalized: Len = 731610, Over = 0
+PHY-3001 : Spreading special nets. 598 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.201487s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.8%)
+
+PHY-3001 : 887 instances has been re-located, deltaX = 334, deltaY = 565, maxDist = 4.
+PHY-3001 : Final: Len = 745737, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75094, tnet num: 17553, tinst num: 7002, tnode num: 97895, tedge num: 126073.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.936733s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (100.0%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 616 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 2911/17731.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872152, over cnt = 2540(7%), over = 4377, worst = 9
+PHY-1002 : len = 887328, over cnt = 1592(4%), over = 2376, worst = 7
+PHY-1002 : len = 900176, over cnt = 954(2%), over = 1369, worst = 6
+PHY-1002 : len = 915536, over cnt = 299(0%), over = 406, worst = 6
+PHY-1002 : len = 922128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.091076s wall, 3.187500s user + 0.015625s system = 3.203125s CPU (153.2%)
+
+PHY-1001 : Congestion index: top1 = 53.53, top5 = 48.50, top10 = 45.98, top15 = 44.17.
+PHY-1001 : End incremental global routing;  2.514119s wall, 3.609375s user + 0.015625s system = 3.625000s CPU (144.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17553 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.899802s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.0%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6909 has valid locations, 31 needs to be replaced
+PHY-3001 : design contains 7028 instances, 6879 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3744 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 751072
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16125/17756.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 929496, over cnt = 85(0%), over = 119, worst = 9
+PHY-1002 : len = 929656, over cnt = 46(0%), over = 53, worst = 2
+PHY-1002 : len = 929864, over cnt = 10(0%), over = 14, worst = 2
+PHY-1002 : len = 930000, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 930048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.841128s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (104.0%)
+
+PHY-1001 : Congestion index: top1 = 53.58, top5 = 48.62, top10 = 46.16, top15 = 44.35.
+PHY-3001 : End congestion estimation;  1.158834s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (102.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75383, tnet num: 17578, tinst num: 7028, tnode num: 98257, tedge num: 126429.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.919647s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (100.1%)
+
+RUN-1004 : used memory is 676 MB, reserved memory is 673 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17578 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.815209s wall, 2.796875s user + 0.015625s system = 2.812500s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(269): len = 750220, overlap = 1
+PHY-3002 : Step(270): len = 749756, overlap = 1.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16113/17756.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 927624, over cnt = 79(0%), over = 105, worst = 5
+PHY-1002 : len = 927736, over cnt = 45(0%), over = 47, worst = 2
+PHY-1002 : len = 928088, over cnt = 9(0%), over = 10, worst = 2
+PHY-1002 : len = 928224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.673967s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (113.6%)
+
+PHY-1001 : Congestion index: top1 = 53.84, top5 = 48.69, top10 = 46.16, top15 = 44.34.
+PHY-3001 : End congestion estimation;  1.033246s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (108.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17578 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.996475s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000587
+PHY-3002 : Step(271): len = 749606, overlap = 2.25
+PHY-3002 : Step(272): len = 749334, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005757s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 749574, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.103390s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (90.7%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 15, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 749856, Over = 0
+PHY-3001 : End incremental placement;  6.553894s wall, 6.640625s user + 0.062500s system = 6.703125s CPU (102.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.638956s wall, 11.906250s user + 0.093750s system = 12.000000s CPU (112.8%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 746, peak = 758.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16058/17756.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 928320, over cnt = 113(0%), over = 151, worst = 6
+PHY-1002 : len = 928464, over cnt = 53(0%), over = 53, worst = 1
+PHY-1002 : len = 928880, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 929040, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 929144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.853206s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (102.6%)
+
+PHY-1001 : Congestion index: top1 = 53.99, top5 = 48.63, top10 = 46.18, top15 = 44.38.
+OPT-1001 : End congestion update;  1.208819s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (100.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17578 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.796839s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.0%)
+
+OPT-0007 : Start: WNS -4309 TNS -2296684 NUM_FEPS 977
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6940 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7028 instances, 6879 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3744 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 749893, Over = 0
+PHY-3001 : Spreading special nets. 14 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062031s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.8%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 12, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 750589, Over = 0
+PHY-3001 : End incremental legalization;  0.406221s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (126.9%)
+
+OPT-0007 : Iter 1: improved WNS -4093 TNS -2275745 NUM_FEPS 977 with 41 cells processed and 5092 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6940 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7028 instances, 6879 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3744 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 750247, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.096479s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (113.4%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 8, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 750705, Over = 0
+PHY-3001 : End incremental legalization;  0.437199s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+OPT-0007 : Iter 2: improved WNS -4074 TNS -2270076 NUM_FEPS 977 with 29 cells processed and 2946 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6940 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7028 instances, 6879 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3744 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 750615, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.097569s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (96.1%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 8, deltaY = 6, maxDist = 2.
+PHY-3001 : Final: Len = 750969, Over = 0
+PHY-3001 : End incremental legalization;  0.427950s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (124.1%)
+
+OPT-0007 : Iter 3: improved WNS -4024 TNS -2269710 NUM_FEPS 977 with 25 cells processed and 2013 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6940 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7028 instances, 6879 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3744 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 750901, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.076400s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (102.3%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 5, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 751239, Over = 0
+PHY-3001 : End incremental legalization;  0.414127s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.9%)
+
+OPT-0007 : Iter 4: improved WNS -4024 TNS -2269554 NUM_FEPS 977 with 16 cells processed and 1573 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6940 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7028 instances, 6879 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3744 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 751063, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.094915s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (98.8%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 4, deltaY = 6, maxDist = 1.
+PHY-3001 : Final: Len = 751295, Over = 0
+PHY-3001 : End incremental legalization;  0.428202s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (94.9%)
+
+OPT-0007 : Iter 5: improved WNS -4024 TNS -2267220 NUM_FEPS 977 with 15 cells processed and 1484 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6940 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7028 instances, 6879 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3744 pins
+PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 750961, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.100429s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (108.9%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 9, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 751419, Over = 0
+PHY-3001 : End incremental legalization;  0.449346s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.8%)
+
+OPT-0007 : Iter 6: improved WNS -4024 TNS -2265417 NUM_FEPS 977 with 14 cells processed and 1198 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6945 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7033 instances, 6884 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3746 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 751839, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060187s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.8%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 0, deltaY = 3, maxDist = 1.
+PHY-3001 : Final: Len = 751919, Over = 0
+PHY-3001 : End incremental legalization;  0.415053s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (124.2%)
+
+OPT-0007 : Iter 7: improved WNS -3803 TNS -2261143 NUM_FEPS 977 with 5 cells processed and 771 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6953 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7041 instances, 6892 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3753 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 752870, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062206s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.5%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 9, deltaY = 6, maxDist = 3.
+PHY-3001 : Final: Len = 752848, Over = 0
+PHY-3001 : End incremental legalization;  0.393261s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.3%)
+
+OPT-0007 : Iter 8: improved WNS -3803 TNS -2259330 NUM_FEPS 977 with 8 cells processed and 1384 slack improved
+OPT-1001 : End bottleneck based optimization;  7.079818s wall, 7.484375s user + 0.031250s system = 7.515625s CPU (106.2%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 744, peak = 758.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15635/17759.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932104, over cnt = 356(1%), over = 472, worst = 4
+PHY-1002 : len = 932376, over cnt = 222(0%), over = 263, worst = 4
+PHY-1002 : len = 934760, over cnt = 53(0%), over = 64, worst = 4
+PHY-1002 : len = 935912, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 935984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.958599s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (112.5%)
+
+PHY-1001 : Congestion index: top1 = 53.79, top5 = 48.99, top10 = 46.41, top15 = 44.59.
+OPT-1001 : End congestion update;  1.284120s wall, 1.406250s user + 0.000000s system = 1.406250s CPU (109.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17581 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.740133s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.3%)
+
+OPT-0007 : Start: WNS -3893 TNS -2263377 NUM_FEPS 977
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6953 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7041 instances, 6892 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3753 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 754072, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061327s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.9%)
+
+PHY-3001 : 28 instances has been re-located, deltaX = 7, deltaY = 23, maxDist = 2.
+PHY-3001 : Final: Len = 754596, Over = 0
+PHY-3001 : End incremental legalization;  0.390381s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (128.1%)
+
+OPT-0007 : Iter 1: improved WNS -3824 TNS -2256521 NUM_FEPS 977 with 33 cells processed and 2431 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6953 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7041 instances, 6892 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3753 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 754612, Over = 0
+PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059859s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.4%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 1, deltaY = 13, maxDist = 2.
+PHY-3001 : Final: Len = 754764, Over = 0
+PHY-3001 : End incremental legalization;  0.425601s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (102.8%)
+
+OPT-0007 : Iter 2: improved WNS -3793 TNS -2259052 NUM_FEPS 977 with 17 cells processed and 990 slack improved
+OPT-0007 : Iter 3: improved WNS -3793 TNS -2259052 NUM_FEPS 977 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  3.159412s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (107.3%)
+
+OPT-1001 : Current memory(MB): used = 751, reserve = 744, peak = 758.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17581 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.738082s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.5%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15893/17759.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 936984, over cnt = 178(0%), over = 250, worst = 4
+PHY-1002 : len = 937144, over cnt = 110(0%), over = 134, worst = 4
+PHY-1002 : len = 938600, over cnt = 21(0%), over = 23, worst = 2
+PHY-1002 : len = 938904, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 938992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.869757s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (115.0%)
+
+PHY-1001 : Congestion index: top1 = 54.25, top5 = 49.14, top10 = 46.56, top15 = 44.75.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17581 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.742354s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.9%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -3774 TNS -2263993 NUM_FEPS 977
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.862069
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -3774ps with logic level 5 
+RUN-1001 :       #2 path slack -3768ps with logic level 5 
+RUN-1001 :       #3 path slack -3753ps with logic level 5 
+RUN-1001 :       #4 path slack -3743ps with logic level 5 
+RUN-1001 :       #5 path slack -3743ps with logic level 5 
+RUN-1001 :       #6 path slack -3743ps with logic level 5 
+RUN-1001 :       #7 path slack -3732ps with logic level 6 
+RUN-1001 :       #8 path slack -3716ps with logic level 5 
+RUN-1001 :       #9 path slack -3707ps with logic level 5 
+RUN-1001 :       #10 path slack -3691ps with logic level 5 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17759 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17759 nets
+OPT-1001 : End physical optimization;  25.870073s wall, 27.859375s user + 0.156250s system = 28.015625s CPU (108.3%)
+
+RUN-1003 : finish command "place" in  67.816945s wall, 93.734375s user + 5.468750s system = 99.203125s CPU (146.3%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 603 MB, peak memory is 758 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.704468s wall, 2.953125s user + 0.000000s system = 2.953125s CPU (173.3%)
+
+RUN-1004 : used memory is 620 MB, reserved memory is 604 MB, peak memory is 758 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7043 instances
+RUN-1001 : 3429 mslices, 3463 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17759 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10026 nets have 2 pins
+RUN-1001 : 5764 nets have [3 - 5] pins
+RUN-1001 : 1206 nets have [6 - 10] pins
+RUN-1001 : 386 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75514, tnet num: 17581, tinst num: 7041, tnode num: 98426, tedge num: 126591.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.670561s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.1%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 630 MB, peak memory is 758 MB
+PHY-1001 : 3429 mslices, 3463 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17581 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 865920, over cnt = 2702(7%), over = 4700, worst = 8
+PHY-1002 : len = 887208, over cnt = 1577(4%), over = 2303, worst = 6
+PHY-1002 : len = 903296, over cnt = 782(2%), over = 1082, worst = 6
+PHY-1002 : len = 921048, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 921224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.994391s wall, 4.078125s user + 0.015625s system = 4.093750s CPU (136.7%)
+
+PHY-1001 : Congestion index: top1 = 53.75, top5 = 48.62, top10 = 45.96, top15 = 44.24.
+PHY-1001 : End global routing;  3.329972s wall, 4.406250s user + 0.015625s system = 4.421875s CPU (132.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 729, reserve = 724, peak = 758.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1000, reserve = 995, peak = 1000.
+PHY-1001 : End build detailed router design. 3.996947s wall, 3.968750s user + 0.015625s system = 3.984375s CPU (99.7%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 270304, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.941736s wall, 4.937500s user + 0.000000s system = 4.937500s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 270360, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.422051s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1032, peak = 1036.
+PHY-1001 : End phase 1; 5.377216s wall, 5.375000s user + 0.000000s system = 5.375000s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 37% nets.
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 54% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37022e+06, over cnt = 1748(0%), over = 1756, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1049, peak = 1054.
+PHY-1001 : End initial routed; 28.413773s wall, 57.734375s user + 0.234375s system = 57.968750s CPU (204.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1991/16687(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.130   |  -3543.463  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.324454s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1060, reserve = 1060, peak = 1060.
+PHY-1001 : End phase 2; 31.738292s wall, 61.062500s user + 0.234375s system = 61.296875s CPU (193.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 196 pins with SWNS -5.702ns STNS -3514.974ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.839294s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.5%)
+
+PHY-1022 : len = 2.37162e+06, over cnt = 1903(0%), over = 1917, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 1.105072s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (100.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34902e+06, over cnt = 810(0%), over = 814, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.372330s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (162.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34486e+06, over cnt = 240(0%), over = 240, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.809106s wall, 1.390625s user + 0.000000s system = 1.390625s CPU (171.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34429e+06, over cnt = 44(0%), over = 44, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.761727s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (116.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34487e+06, over cnt = 18(0%), over = 18, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.433933s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (104.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34523e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.397693s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.34531e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.580193s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (99.6%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.34527e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.981798s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (98.7%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.34526e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.200237s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (93.6%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.249512s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.259912s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.287225s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (103.4%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.357004s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.7%)
+
+PHY-1001 : ===== DR Iter 13 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.167863s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.1%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.179059s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.205394s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.221852s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.6%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.309732s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.366050s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.4%)
+
+PHY-1001 : ===== DR Iter 19 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.172333s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.180030s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.1%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.224982s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.247887s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (100.9%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.300184s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (98.9%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.362783s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 1.006915s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.9%)
+
+PHY-1001 : ===== DR Iter 26 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.168065s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.0%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.179242s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.204070s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.221306s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (105.9%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.309703s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.402971s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 1.181700s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.997349s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 34 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.167874s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (93.1%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.178672s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.2%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.202822s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.218702s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.304496s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.358611s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (95.9%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.998817s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (103.2%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.999415s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 1.001739s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 43 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.168177s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.177175s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.204393s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.222081s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.5%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.305519s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.362075s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.012849s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 1.076811s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 1.127998s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 1.014816s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 53 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.167999s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.177672s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.7%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.202449s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.218485s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.307063s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (101.8%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.360229s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.005555s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.005068s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 1.002162s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 1.003135s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 1.006748s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 64 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.168054s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (102.3%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.178468s wall, 0.203125s user + 0.031250s system = 0.234375s CPU (131.3%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.202401s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (108.1%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.220202s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.3%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.314501s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.432725s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 1.086623s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 1.005249s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (101.0%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 1.001673s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.994070s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.999348s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.1%)
+
+PHY-1001 : ==== DR Iter 75 ====
+PHY-1022 : len = 2.34534e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 75; 1.000066s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1991/16687(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -5.801   |  -3524.836  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.329228s wall, 3.296875s user + 0.031250s system = 3.328125s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1066, reserve = 1068, peak = 1067.
+PHY-1001 : End phase 3; 43.360084s wall, 44.968750s user + 0.093750s system = 45.062500s CPU (103.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 70 pins with SWNS -5.690ns STNS -3516.161ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.466106s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (100.6%)
+
+PHY-1022 : len = 2.34542e+06, over cnt = 34(0%), over = 34, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.733193s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.2%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.690ns, -3516.161ns, 984}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34534e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.238585s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (98.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.211969s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (95.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.253124s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.379634s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.170919s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.6%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.179011s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 7 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.204109s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.224817s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.306279s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.0%)
+
+PHY-1001 : ===== DR Iter 10 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.168645s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.9%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.181670s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.6%)
+
+PHY-1001 : ==== DR Iter 12 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.336049s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (69.7%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.224674s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.309217s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (101.1%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.358948s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.1%)
+
+PHY-1001 : ===== DR Iter 16 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.169525s wall, 0.187500s user + 0.046875s system = 0.234375s CPU (138.3%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.181314s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (120.6%)
+
+PHY-1001 : ==== DR Iter 18 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.204697s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.220140s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.304033s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (102.8%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.362544s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.993461s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 23 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.169266s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.178416s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.3%)
+
+PHY-1001 : ==== DR Iter 25 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.209398s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.0%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.222617s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (133.4%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.305384s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.361517s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.4%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 1.012624s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 1.089740s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (100.4%)
+
+PHY-1001 : ===== DR Iter 31 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.180409s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (86.6%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.187554s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (100.0%)
+
+PHY-1001 : ==== DR Iter 33 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.206507s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.224400s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (97.5%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.316139s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.969688s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (37.1%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.994745s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.0%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 1.010942s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (100.5%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 1.001733s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (99.8%)
+
+PHY-1001 : ===== DR Iter 40 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.171364s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.180221s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (138.7%)
+
+PHY-1001 : ==== DR Iter 42 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.205594s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.8%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.222266s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (98.4%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.310026s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.361319s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 1.059495s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 1.067509s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (99.5%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 1.077817s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 1.159968s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (101.0%)
+
+PHY-1001 : ===== DR Iter 50 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.170549s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.180880s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 52 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.208921s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (97.2%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.227169s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.3%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.309280s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.363676s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.1%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 1.040680s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (99.1%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 1.016548s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (99.9%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.997869s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.2%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 1.001537s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (98.3%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 1.040737s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (100.6%)
+
+PHY-1001 : ===== DR Iter 61 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.169764s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (101.2%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.179451s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.8%)
+
+PHY-1001 : ==== DR Iter 63 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.205056s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (114.3%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.228583s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (95.7%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.313510s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (99.7%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.365378s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.6%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 1.118028s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.2%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 1.176261s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.6%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 1.016488s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (103.0%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.996731s wall, 0.984375s user + 0.015625s system = 1.000000s CPU (100.3%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.976657s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (100.8%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.998262s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1991/16687(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -5.690   |  -3521.438  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.335567s wall, 3.312500s user + 0.015625s system = 3.328125s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1066, reserve = 1066, peak = 1071.
+PHY-1001 : End phase 4; 39.121343s wall, 38.421875s user + 0.203125s system = 38.625000s CPU (98.7%)
+
+PHY-1003 : Routed, final wirelength = 2.34535e+06
+PHY-1001 : 579 feed throughs used by 442 nets
+PHY-1001 : Current memory(MB): used = 1174, reserve = 1179, peak = 1174.
+PHY-1001 : End export database. 2.376772s wall, 2.359375s user + 0.015625s system = 2.375000s CPU (99.9%)
+
+PHY-1001 : Fixing routing violation through ECO...
+RUN-1002 : start command "place -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing ultra"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |   ultra    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7043 instances
+RUN-1001 : 3429 mslices, 3463 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17759 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10026 nets have 2 pins
+RUN-1001 : 5764 nets have [3 - 5] pins
+RUN-1001 : 1206 nets have [6 - 10] pins
+RUN-1001 : 386 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |      0      
+RUN-1001 :   No   |  No   |  Yes  |      0      
+RUN-1001 :   No   |  Yes  |  No   |      0      
+RUN-1001 :   Yes  |  No   |  No   |      0      
+RUN-1001 :   Yes  |  No   |  Yes  |      0      
+RUN-1001 :   Yes  |  Yes  |  No   |      0      
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    10   |   1   |     1      
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 0
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: (1 60 2) is for feedthrough
+PHY-3001 : eco cells: (1 67 2) is for feedthrough
+PHY-3001 : eco cells: (2 13 0) is for feedthrough
+PHY-3001 : eco cells: (2 26 1) is for feedthrough
+PHY-3001 : eco cells: (2 27 3) is for feedthrough
+PHY-3001 : eco cells: (2 36 1) is for feedthrough
+PHY-3001 : eco cells: (3 4 2) is for feedthrough
+PHY-3001 : eco cells: (3 15 0) is for feedthrough
+PHY-3001 : eco cells: (3 26 3) is for feedthrough
+PHY-3001 : eco cells: (3 33 1) is for feedthrough
+PHY-3001 : eco cells: (3 39 2) is for feedthrough
+PHY-3001 : eco cells: (3 56 0) is for feedthrough
+PHY-3001 : eco cells: (3 56 1) is for feedthrough
+PHY-3001 : eco cells: (3 59 0) is for feedthrough
+PHY-3001 : eco cells: (3 60 0) is for feedthrough
+PHY-3001 : eco cells: (3 61 1) is for feedthrough
+PHY-3001 : eco cells: (3 62 2) is for feedthrough
+PHY-3001 : eco cells: (3 65 0) is for feedthrough
+PHY-3001 : eco cells: (3 67 1) is for feedthrough
+PHY-3001 : eco cells: (4 8 2) is for feedthrough
+PHY-3001 : eco cells: (4 15 2) is for feedthrough
+PHY-3001 : eco cells: (4 17 1) is for feedthrough
+PHY-3001 : eco cells: (4 25 0) is for feedthrough
+PHY-3001 : eco cells: (4 25 3) is for feedthrough
+PHY-3001 : eco cells: (4 26 3) is for feedthrough
+PHY-3001 : eco cells: (4 27 0) is for feedthrough
+PHY-3001 : eco cells: (4 27 3) is for feedthrough
+PHY-3001 : eco cells: (4 28 3) is for feedthrough
+PHY-3001 : eco cells: (4 29 3) is for feedthrough
+PHY-3001 : eco cells: (4 32 1) is for feedthrough
+PHY-3001 : eco cells: (4 38 0) is for feedthrough
+PHY-3001 : eco cells: (4 39 2) is for feedthrough
+PHY-3001 : eco cells: (4 39 3) is for feedthrough
+PHY-3001 : eco cells: (4 40 1) is for feedthrough
+PHY-3001 : eco cells: (4 45 0) is for feedthrough
+PHY-3001 : eco cells: (4 49 2) is for feedthrough
+PHY-3001 : eco cells: (4 54 2) is for feedthrough
+PHY-3001 : eco cells: (4 66 3) is for feedthrough
+PHY-3001 : eco cells: (5 2 0) is for feedthrough
+PHY-3001 : eco cells: (5 5 3) is for feedthrough
+PHY-3001 : eco cells: (5 6 2) is for feedthrough
+PHY-3001 : eco cells: (5 27 0) is for feedthrough
+PHY-3001 : eco cells: (5 29 1) is for feedthrough
+PHY-3001 : eco cells: (5 29 3) is for feedthrough
+PHY-3001 : eco cells: (5 30 1) is for feedthrough
+PHY-3001 : eco cells: (5 33 2) is for feedthrough
+PHY-3001 : eco cells: (5 34 2) is for feedthrough
+PHY-3001 : eco cells: (5 38 1) is for feedthrough
+PHY-3001 : eco cells: (5 40 2) is for feedthrough
+PHY-3001 : eco cells: (5 52 0) is for feedthrough
+PHY-3001 : eco cells: (5 59 3) is for feedthrough
+PHY-3001 : eco cells: (6 6 1) is for feedthrough
+PHY-3001 : eco cells: (6 8 0) is for feedthrough
+PHY-3001 : eco cells: (6 11 0) is for feedthrough
+PHY-3001 : eco cells: (6 15 3) is for feedthrough
+PHY-3001 : eco cells: (6 16 2) is for feedthrough
+PHY-3001 : eco cells: (6 26 0) is for feedthrough
+PHY-3001 : eco cells: (6 28 2) is for feedthrough
+PHY-3001 : eco cells: (6 28 3) is for feedthrough
+PHY-3001 : eco cells: (6 29 3) is for feedthrough
+PHY-3001 : eco cells: (6 35 2) is for feedthrough
+PHY-3001 : eco cells: (6 37 3) is for feedthrough
+PHY-3001 : eco cells: (6 41 3) is for feedthrough
+PHY-3001 : eco cells: (6 46 3) is for feedthrough
+PHY-3001 : eco cells: (6 54 2) is for feedthrough
+PHY-3001 : eco cells: (6 55 0) is for feedthrough
+PHY-3001 : eco cells: (6 55 1) is for feedthrough
+PHY-3001 : eco cells: (6 57 3) is for feedthrough
+PHY-3001 : eco cells: (7 1 0) is for feedthrough
+PHY-3001 : eco cells: (7 3 0) is for feedthrough
+PHY-3001 : eco cells: (7 7 3) is for feedthrough
+PHY-3001 : eco cells: (7 12 0) is for feedthrough
+PHY-3001 : eco cells: (7 15 2) is for feedthrough
+PHY-3001 : eco cells: (7 17 3) is for feedthrough
+PHY-3001 : eco cells: (7 20 2) is for feedthrough
+PHY-3001 : eco cells: (7 21 2) is for feedthrough
+PHY-3001 : eco cells: (7 28 2) is for feedthrough
+PHY-3001 : eco cells: (7 29 2) is for feedthrough
+PHY-3001 : eco cells: (7 29 3) is for feedthrough
+PHY-3001 : eco cells: (7 30 3) is for feedthrough
+PHY-3001 : eco cells: (7 31 2) is for feedthrough
+PHY-3001 : eco cells: (7 32 2) is for feedthrough
+PHY-3001 : eco cells: (7 35 2) is for feedthrough
+PHY-3001 : eco cells: (7 38 1) is for feedthrough
+PHY-3001 : eco cells: (7 38 2) is for feedthrough
+PHY-3001 : eco cells: (7 45 3) is for feedthrough
+PHY-3001 : eco cells: (7 53 1) is for feedthrough
+PHY-3001 : eco cells: (7 54 2) is for feedthrough
+PHY-3001 : eco cells: (7 55 3) is for feedthrough
+PHY-3001 : eco cells: (7 57 0) is for feedthrough
+PHY-3001 : eco cells: (9 4 1) is for feedthrough
+PHY-3001 : eco cells: (9 27 2) is for feedthrough
+PHY-3001 : eco cells: (9 31 0) is for feedthrough
+PHY-3001 : eco cells: (9 32 3) is for feedthrough
+PHY-3001 : eco cells: (9 34 0) is for feedthrough
+PHY-3001 : eco cells: (9 35 3) is for feedthrough
+PHY-3001 : eco cells: (9 41 3) is for feedthrough
+PHY-3001 : eco cells: (9 53 0) is for feedthrough
+PHY-3001 : eco cells: (9 60 3) is for feedthrough
+PHY-3001 : eco cells: (10 1 1) is for feedthrough
+PHY-3001 : eco cells: (10 5 2) is for feedthrough
+PHY-3001 : eco cells: (10 5 3) is for feedthrough
+PHY-3001 : eco cells: (10 10 3) is for feedthrough
+PHY-3001 : eco cells: (10 18 2) is for feedthrough
+PHY-3001 : eco cells: (10 20 2) is for feedthrough
+PHY-3001 : eco cells: (10 20 3) is for feedthrough
+PHY-3001 : eco cells: (10 21 2) is for feedthrough
+PHY-3001 : eco cells: (10 27 3) is for feedthrough
+PHY-3001 : eco cells: (10 29 1) is for feedthrough
+PHY-3001 : eco cells: (10 30 2) is for feedthrough
+PHY-3001 : eco cells: (10 32 1) is for feedthrough
+PHY-3001 : eco cells: (10 34 0) is for feedthrough
+PHY-3001 : eco cells: (10 34 1) is for feedthrough
+PHY-3001 : eco cells: (10 37 3) is for feedthrough
+PHY-3001 : eco cells: (10 40 3) is for feedthrough
+PHY-3001 : eco cells: (10 41 2) is for feedthrough
+PHY-3001 : eco cells: (10 44 2) is for feedthrough
+PHY-3001 : eco cells: (10 46 1) is for feedthrough
+PHY-3001 : eco cells: (10 47 2) is for feedthrough
+PHY-3001 : eco cells: (10 52 0) is for feedthrough
+PHY-3001 : eco cells: (10 53 1) is for feedthrough
+PHY-3001 : eco cells: (10 56 2) is for feedthrough
+PHY-3001 : eco cells: (10 57 0) is for feedthrough
+PHY-3001 : eco cells: (10 60 0) is for feedthrough
+PHY-3001 : eco cells: (10 61 3) is for feedthrough
+PHY-3001 : eco cells: (10 67 0) is for feedthrough
+PHY-3001 : eco cells: (11 7 2) is for feedthrough
+PHY-3001 : eco cells: (11 10 2) is for feedthrough
+PHY-3001 : eco cells: (11 11 0) is for feedthrough
+PHY-3001 : eco cells: (11 15 3) is for feedthrough
+PHY-3001 : eco cells: (11 16 2) is for feedthrough
+PHY-3001 : eco cells: (11 21 3) is for feedthrough
+PHY-3001 : eco cells: (11 22 3) is for feedthrough
+PHY-3001 : eco cells: (11 35 2) is for feedthrough
+PHY-3001 : eco cells: (11 36 1) is for feedthrough
+PHY-3001 : eco cells: (11 37 2) is for feedthrough
+PHY-3001 : eco cells: (11 42 2) is for feedthrough
+PHY-3001 : eco cells: (11 42 3) is for feedthrough
+PHY-3001 : eco cells: (11 55 2) is for feedthrough
+PHY-3001 : eco cells: (11 57 3) is for feedthrough
+PHY-3001 : eco cells: (11 58 0) is for feedthrough
+PHY-3001 : eco cells: (11 64 1) is for feedthrough
+PHY-3001 : eco cells: (11 64 2) is for feedthrough
+PHY-3001 : eco cells: (12 4 0) is for feedthrough
+PHY-3001 : eco cells: (12 5 0) is for feedthrough
+PHY-3001 : eco cells: (12 21 1) is for feedthrough
+PHY-3001 : eco cells: (12 22 3) is for feedthrough
+PHY-3001 : eco cells: (12 23 3) is for feedthrough
+PHY-3001 : eco cells: (12 32 2) is for feedthrough
+PHY-3001 : eco cells: (12 33 1) is for feedthrough
+PHY-3001 : eco cells: (12 34 2) is for feedthrough
+PHY-3001 : eco cells: (12 34 3) is for feedthrough
+PHY-3001 : eco cells: (12 40 3) is for feedthrough
+PHY-3001 : eco cells: (12 41 0) is for feedthrough
+PHY-3001 : eco cells: (12 43 2) is for feedthrough
+PHY-3001 : eco cells: (12 43 3) is for feedthrough
+PHY-3001 : eco cells: (12 46 3) is for feedthrough
+PHY-3001 : eco cells: (12 49 0) is for feedthrough
+PHY-3001 : eco cells: (12 52 2) is for feedthrough
+PHY-3001 : eco cells: (12 58 0) is for feedthrough
+PHY-3001 : eco cells: (12 59 3) is for feedthrough
+PHY-3001 : eco cells: (12 61 3) is for feedthrough
+PHY-3001 : eco cells: (12 64 2) is for feedthrough
+PHY-3001 : eco cells: (12 68 0) is for feedthrough
+PHY-3001 : eco cells: (13 3 0) is for feedthrough
+PHY-3001 : eco cells: (13 4 1) is for feedthrough
+PHY-3001 : eco cells: (13 7 0) is for feedthrough
+PHY-3001 : eco cells: (13 7 1) is for feedthrough
+PHY-3001 : eco cells: (13 15 0) is for feedthrough
+PHY-3001 : eco cells: (13 33 3) is for feedthrough
+PHY-3001 : eco cells: (13 34 3) is for feedthrough
+PHY-3001 : eco cells: (13 36 2) is for feedthrough
+PHY-3001 : eco cells: (13 38 0) is for feedthrough
+PHY-3001 : eco cells: (13 43 3) is for feedthrough
+PHY-3001 : eco cells: (13 61 3) is for feedthrough
+PHY-3001 : eco cells: (13 67 1) is for feedthrough
+PHY-3001 : eco cells: (14 1 0) is for feedthrough
+PHY-3001 : eco cells: (14 9 3) is for feedthrough
+PHY-3001 : eco cells: (14 19 3) is for feedthrough
+PHY-3001 : eco cells: (14 20 0) is for feedthrough
+PHY-3001 : eco cells: (14 22 2) is for feedthrough
+PHY-3001 : eco cells: (14 42 2) is for feedthrough
+PHY-3001 : eco cells: (14 59 3) is for feedthrough
+PHY-3001 : eco cells: (14 60 0) is for feedthrough
+PHY-3001 : eco cells: (14 60 1) is for feedthrough
+PHY-3001 : eco cells: (14 61 3) is for feedthrough
+PHY-3001 : eco cells: (14 65 3) is for feedthrough
+PHY-3001 : eco cells: (15 5 0) is for feedthrough
+PHY-3001 : eco cells: (15 6 0) is for feedthrough
+PHY-3001 : eco cells: (15 9 0) is for feedthrough
+PHY-3001 : eco cells: (15 23 0) is for feedthrough
+PHY-3001 : eco cells: (15 26 1) is for feedthrough
+PHY-3001 : eco cells: (15 37 1) is for feedthrough
+PHY-3001 : eco cells: (15 37 2) is for feedthrough
+PHY-3001 : eco cells: (15 37 3) is for feedthrough
+PHY-3001 : eco cells: (15 41 1) is for feedthrough
+PHY-3001 : eco cells: (15 61 2) is for feedthrough
+PHY-3001 : eco cells: (15 68 0) is for feedthrough
+PHY-3001 : eco cells: (15 69 0) is for feedthrough
+PHY-3001 : eco cells: (17 6 0) is for feedthrough
+PHY-3001 : eco cells: (17 10 1) is for feedthrough
+PHY-3001 : eco cells: (17 16 0) is for feedthrough
+PHY-3001 : eco cells: (17 22 0) is for feedthrough
+PHY-3001 : eco cells: (17 22 1) is for feedthrough
+PHY-3001 : eco cells: (17 23 0) is for feedthrough
+PHY-3001 : eco cells: (17 24 0) is for feedthrough
+PHY-3001 : eco cells: (17 24 2) is for feedthrough
+PHY-3001 : eco cells: (17 29 0) is for feedthrough
+PHY-3001 : eco cells: (17 30 1) is for feedthrough
+PHY-3001 : eco cells: (17 37 1) is for feedthrough
+PHY-3001 : eco cells: (17 41 0) is for feedthrough
+PHY-3001 : eco cells: (17 44 2) is for feedthrough
+PHY-3001 : eco cells: (17 59 0) is for feedthrough
+PHY-3001 : eco cells: (17 66 1) is for feedthrough
+PHY-3001 : eco cells: (18 4 3) is for feedthrough
+PHY-3001 : eco cells: (18 12 1) is for feedthrough
+PHY-3001 : eco cells: (18 22 0) is for feedthrough
+PHY-3001 : eco cells: (18 22 1) is for feedthrough
+PHY-3001 : eco cells: (18 23 2) is for feedthrough
+PHY-3001 : eco cells: (18 25 0) is for feedthrough
+PHY-3001 : eco cells: (18 25 3) is for feedthrough
+PHY-3001 : eco cells: (18 29 1) is for feedthrough
+PHY-3001 : eco cells: (18 34 1) is for feedthrough
+PHY-3001 : eco cells: (18 36 0) is for feedthrough
+PHY-3001 : eco cells: (18 37 0) is for feedthrough
+PHY-3001 : eco cells: (18 37 1) is for feedthrough
+PHY-3001 : eco cells: (18 42 0) is for feedthrough
+PHY-3001 : eco cells: (18 42 2) is for feedthrough
+PHY-3001 : eco cells: (18 44 0) is for feedthrough
+PHY-3001 : eco cells: (18 46 1) is for feedthrough
+PHY-3001 : eco cells: (18 55 3) is for feedthrough
+PHY-3001 : eco cells: (18 58 2) is for feedthrough
+PHY-3001 : eco cells: (18 58 3) is for feedthrough
+PHY-3001 : eco cells: (18 59 2) is for feedthrough
+PHY-3001 : eco cells: (18 66 3) is for feedthrough
+PHY-3001 : eco cells: (18 68 2) is for feedthrough
+PHY-3001 : eco cells: (19 1 1) is for feedthrough
+PHY-3001 : eco cells: (19 13 1) is for feedthrough
+PHY-3001 : eco cells: (19 18 1) is for feedthrough
+PHY-3001 : eco cells: (19 22 3) is for feedthrough
+PHY-3001 : eco cells: (19 23 2) is for feedthrough
+PHY-3001 : eco cells: (19 24 3) is for feedthrough
+PHY-3001 : eco cells: (19 27 2) is for feedthrough
+PHY-3001 : eco cells: (19 28 3) is for feedthrough
+PHY-3001 : eco cells: (19 30 1) is for feedthrough
+PHY-3001 : eco cells: (19 31 1) is for feedthrough
+PHY-3001 : eco cells: (19 32 0) is for feedthrough
+PHY-3001 : eco cells: (19 33 1) is for feedthrough
+PHY-3001 : eco cells: (19 37 1) is for feedthrough
+PHY-3001 : eco cells: (19 42 3) is for feedthrough
+PHY-3001 : eco cells: (19 44 0) is for feedthrough
+PHY-3001 : eco cells: (19 51 3) is for feedthrough
+PHY-3001 : eco cells: (19 56 3) is for feedthrough
+PHY-3001 : eco cells: (19 60 0) is for feedthrough
+PHY-3001 : eco cells: (19 62 3) is for feedthrough
+PHY-3001 : eco cells: (19 67 1) is for feedthrough
+PHY-3001 : eco cells: (19 67 3) is for feedthrough
+PHY-3001 : eco cells: (20 1 2) is for feedthrough
+PHY-3001 : eco cells: (20 12 2) is for feedthrough
+PHY-3001 : eco cells: (20 15 1) is for feedthrough
+PHY-3001 : eco cells: (20 17 3) is for feedthrough
+PHY-3001 : eco cells: (20 20 0) is for feedthrough
+PHY-3001 : eco cells: (20 23 0) is for feedthrough
+PHY-3001 : eco cells: (20 23 1) is for feedthrough
+PHY-3001 : eco cells: (20 30 0) is for feedthrough
+PHY-3001 : eco cells: (20 31 0) is for feedthrough
+PHY-3001 : eco cells: (20 38 3) is for feedthrough
+PHY-3001 : eco cells: (20 44 0) is for feedthrough
+PHY-3001 : eco cells: (20 45 1) is for feedthrough
+PHY-3001 : eco cells: (20 48 0) is for feedthrough
+PHY-3001 : eco cells: (20 48 2) is for feedthrough
+PHY-3001 : eco cells: (20 50 2) is for feedthrough
+PHY-3001 : eco cells: (20 57 0) is for feedthrough
+PHY-3001 : eco cells: (20 67 1) is for feedthrough
+PHY-3001 : eco cells: (20 69 3) is for feedthrough
+PHY-3001 : eco cells: (21 1 2) is for feedthrough
+PHY-3001 : eco cells: (21 10 0) is for feedthrough
+PHY-3001 : eco cells: (21 12 2) is for feedthrough
+PHY-3001 : eco cells: (21 13 1) is for feedthrough
+PHY-3001 : eco cells: (21 14 0) is for feedthrough
+PHY-3001 : eco cells: (21 14 2) is for feedthrough
+PHY-3001 : eco cells: (21 15 0) is for feedthrough
+PHY-3001 : eco cells: (21 15 2) is for feedthrough
+PHY-3001 : eco cells: (21 16 0) is for feedthrough
+PHY-3001 : eco cells: (21 16 1) is for feedthrough
+PHY-3001 : eco cells: (21 18 3) is for feedthrough
+PHY-3001 : eco cells: (21 24 0) is for feedthrough
+PHY-3001 : eco cells: (21 29 1) is for feedthrough
+PHY-3001 : eco cells: (21 30 0) is for feedthrough
+PHY-3001 : eco cells: (21 31 1) is for feedthrough
+PHY-3001 : eco cells: (21 34 0) is for feedthrough
+PHY-3001 : eco cells: (21 35 2) is for feedthrough
+PHY-3001 : eco cells: (21 40 0) is for feedthrough
+PHY-3001 : eco cells: (21 43 3) is for feedthrough
+PHY-3001 : eco cells: (21 44 3) is for feedthrough
+PHY-3001 : eco cells: (21 50 2) is for feedthrough
+PHY-3001 : eco cells: (21 51 3) is for feedthrough
+PHY-3001 : eco cells: (21 56 0) is for feedthrough
+PHY-3001 : eco cells: (21 57 3) is for feedthrough
+PHY-3001 : eco cells: (21 58 3) is for feedthrough
+PHY-3001 : eco cells: (21 67 2) is for feedthrough
+PHY-3001 : eco cells: (21 69 1) is for feedthrough
+PHY-3001 : eco cells: (22 11 2) is for feedthrough
+PHY-3001 : eco cells: (22 15 2) is for feedthrough
+PHY-3001 : eco cells: (22 22 1) is for feedthrough
+PHY-3001 : eco cells: (22 24 1) is for feedthrough
+PHY-3001 : eco cells: (22 25 1) is for feedthrough
+PHY-3001 : eco cells: (22 29 0) is for feedthrough
+PHY-3001 : eco cells: (22 30 1) is for feedthrough
+PHY-3001 : eco cells: (22 31 0) is for feedthrough
+PHY-3001 : eco cells: (22 33 1) is for feedthrough
+PHY-3001 : eco cells: (22 34 0) is for feedthrough
+PHY-3001 : eco cells: (22 43 0) is for feedthrough
+PHY-3001 : eco cells: (22 49 2) is for feedthrough
+PHY-3001 : eco cells: (22 59 3) is for feedthrough
+PHY-3001 : eco cells: (23 12 1) is for feedthrough
+PHY-3001 : eco cells: (23 17 1) is for feedthrough
+PHY-3001 : eco cells: (23 24 1) is for feedthrough
+PHY-3001 : eco cells: (23 25 0) is for feedthrough
+PHY-3001 : eco cells: (23 26 0) is for feedthrough
+PHY-3001 : eco cells: (23 26 1) is for feedthrough
+PHY-3001 : eco cells: (23 28 1) is for feedthrough
+PHY-3001 : eco cells: (23 29 2) is for feedthrough
+PHY-3001 : eco cells: (23 31 0) is for feedthrough
+PHY-3001 : eco cells: (23 34 3) is for feedthrough
+PHY-3001 : eco cells: (23 35 0) is for feedthrough
+PHY-3001 : eco cells: (23 36 1) is for feedthrough
+PHY-3001 : eco cells: (23 45 3) is for feedthrough
+PHY-3001 : eco cells: (25 3 3) is for feedthrough
+PHY-3001 : eco cells: (25 6 0) is for feedthrough
+PHY-3001 : eco cells: (25 8 1) is for feedthrough
+PHY-3001 : eco cells: (25 10 1) is for feedthrough
+PHY-3001 : eco cells: (25 10 2) is for feedthrough
+PHY-3001 : eco cells: (25 13 2) is for feedthrough
+PHY-3001 : eco cells: (25 16 0) is for feedthrough
+PHY-3001 : eco cells: (25 17 0) is for feedthrough
+PHY-3001 : eco cells: (25 26 1) is for feedthrough
+PHY-3001 : eco cells: (25 27 0) is for feedthrough
+PHY-3001 : eco cells: (25 34 1) is for feedthrough
+PHY-3001 : eco cells: (25 34 2) is for feedthrough
+PHY-3001 : eco cells: (25 54 3) is for feedthrough
+PHY-3001 : eco cells: (25 55 2) is for feedthrough
+PHY-3001 : eco cells: (25 56 0) is for feedthrough
+PHY-3001 : eco cells: (25 57 1) is for feedthrough
+PHY-3001 : eco cells: (25 61 3) is for feedthrough
+PHY-3001 : eco cells: (26 6 1) is for feedthrough
+PHY-3001 : eco cells: (26 10 1) is for feedthrough
+PHY-3001 : eco cells: (26 11 1) is for feedthrough
+PHY-3001 : eco cells: (26 17 3) is for feedthrough
+PHY-3001 : eco cells: (26 24 3) is for feedthrough
+PHY-3001 : eco cells: (26 26 0) is for feedthrough
+PHY-3001 : eco cells: (26 27 1) is for feedthrough
+PHY-3001 : eco cells: (26 37 0) is for feedthrough
+PHY-3001 : eco cells: (26 38 1) is for feedthrough
+PHY-3001 : eco cells: (26 43 0) is for feedthrough
+PHY-3001 : eco cells: (26 52 1) is for feedthrough
+PHY-3001 : eco cells: (26 61 1) is for feedthrough
+PHY-3001 : eco cells: (26 68 0) is for feedthrough
+PHY-3001 : eco cells: (27 2 2) is for feedthrough
+PHY-3001 : eco cells: (27 10 0) is for feedthrough
+PHY-3001 : eco cells: (27 13 0) is for feedthrough
+PHY-3001 : eco cells: (27 18 3) is for feedthrough
+PHY-3001 : eco cells: (27 24 0) is for feedthrough
+PHY-3001 : eco cells: (27 27 1) is for feedthrough
+PHY-3001 : eco cells: (27 30 2) is for feedthrough
+PHY-3001 : eco cells: (27 52 3) is for feedthrough
+PHY-3001 : eco cells: (27 53 3) is for feedthrough
+PHY-3001 : eco cells: (27 54 2) is for feedthrough
+PHY-3001 : eco cells: (27 54 3) is for feedthrough
+PHY-3001 : eco cells: (27 60 0) is for feedthrough
+PHY-3001 : eco cells: (27 61 3) is for feedthrough
+PHY-3001 : eco cells: (27 66 2) is for feedthrough
+PHY-3001 : eco cells: (27 70 3) is for feedthrough
+PHY-3001 : eco cells: (28 3 3) is for feedthrough
+PHY-3001 : eco cells: (28 13 2) is for feedthrough
+PHY-3001 : eco cells: (28 13 3) is for feedthrough
+PHY-3001 : eco cells: (28 16 3) is for feedthrough
+PHY-3001 : eco cells: (28 18 0) is for feedthrough
+PHY-3001 : eco cells: (28 25 2) is for feedthrough
+PHY-3001 : eco cells: (28 31 1) is for feedthrough
+PHY-3001 : eco cells: (28 32 1) is for feedthrough
+PHY-3001 : eco cells: (28 53 3) is for feedthrough
+PHY-3001 : eco cells: (28 54 0) is for feedthrough
+PHY-3001 : eco cells: (28 57 3) is for feedthrough
+PHY-3001 : eco cells: (28 61 2) is for feedthrough
+PHY-3001 : eco cells: (28 63 2) is for feedthrough
+PHY-3001 : eco cells: (28 67 0) is for feedthrough
+PHY-3001 : eco cells: (29 10 0) is for feedthrough
+PHY-3001 : eco cells: (29 13 3) is for feedthrough
+PHY-3001 : eco cells: (29 14 1) is for feedthrough
+PHY-3001 : eco cells: (29 19 3) is for feedthrough
+PHY-3001 : eco cells: (29 23 2) is for feedthrough
+PHY-3001 : eco cells: (29 25 1) is for feedthrough
+PHY-3001 : eco cells: (29 26 2) is for feedthrough
+PHY-3001 : eco cells: (29 28 1) is for feedthrough
+PHY-3001 : eco cells: (29 30 0) is for feedthrough
+PHY-3001 : eco cells: (29 31 1) is for feedthrough
+PHY-3001 : eco cells: (29 33 0) is for feedthrough
+PHY-3001 : eco cells: (29 34 0) is for feedthrough
+PHY-3001 : eco cells: (29 48 3) is for feedthrough
+PHY-3001 : eco cells: (29 51 0) is for feedthrough
+PHY-3001 : eco cells: (29 60 3) is for feedthrough
+PHY-3001 : eco cells: (29 68 0) is for feedthrough
+PHY-3001 : eco cells: (30 14 1) is for feedthrough
+PHY-3001 : eco cells: (30 15 1) is for feedthrough
+PHY-3001 : eco cells: (30 19 1) is for feedthrough
+PHY-3001 : eco cells: (30 30 0) is for feedthrough
+PHY-3001 : eco cells: (30 30 2) is for feedthrough
+PHY-3001 : eco cells: (30 57 1) is for feedthrough
+PHY-3001 : eco cells: (31 10 1) is for feedthrough
+PHY-3001 : eco cells: (31 24 1) is for feedthrough
+PHY-3001 : eco cells: (31 25 2) is for feedthrough
+PHY-3001 : eco cells: (31 29 3) is for feedthrough
+PHY-3001 : eco cells: (31 30 3) is for feedthrough
+PHY-3001 : eco cells: (33 16 0) is for feedthrough
+PHY-3001 : eco cells: (33 23 3) is for feedthrough
+PHY-3001 : eco cells: (33 26 0) is for feedthrough
+PHY-3001 : eco cells: (33 28 0) is for feedthrough
+PHY-3001 : eco cells: (33 28 1) is for feedthrough
+PHY-3001 : eco cells: (33 29 0) is for feedthrough
+PHY-3001 : eco cells: (33 37 2) is for feedthrough
+PHY-3001 : eco cells: (34 10 3) is for feedthrough
+PHY-3001 : eco cells: (34 15 0) is for feedthrough
+PHY-3001 : eco cells: (34 15 1) is for feedthrough
+PHY-3001 : eco cells: (34 16 0) is for feedthrough
+PHY-3001 : eco cells: (34 19 3) is for feedthrough
+PHY-3001 : eco cells: (34 21 0) is for feedthrough
+PHY-3001 : eco cells: (34 22 1) is for feedthrough
+PHY-3001 : eco cells: (34 23 0) is for feedthrough
+PHY-3001 : eco cells: (34 24 0) is for feedthrough
+PHY-3001 : eco cells: (34 25 1) is for feedthrough
+PHY-3001 : eco cells: (34 25 3) is for feedthrough
+PHY-3001 : eco cells: (34 26 0) is for feedthrough
+PHY-3001 : eco cells: (34 26 1) is for feedthrough
+PHY-3001 : eco cells: (34 29 0) is for feedthrough
+PHY-3001 : eco cells: (34 30 0) is for feedthrough
+PHY-3001 : eco cells: (34 30 3) is for feedthrough
+PHY-3001 : eco cells: (34 34 3) is for feedthrough
+PHY-3001 : eco cells: (34 35 2) is for feedthrough
+PHY-3001 : eco cells: (35 9 1) is for feedthrough
+PHY-3001 : eco cells: (35 14 3) is for feedthrough
+PHY-3001 : eco cells: (35 18 1) is for feedthrough
+PHY-3001 : eco cells: (35 18 2) is for feedthrough
+PHY-3001 : eco cells: (35 19 1) is for feedthrough
+PHY-3001 : eco cells: (35 20 1) is for feedthrough
+PHY-3001 : eco cells: (35 22 0) is for feedthrough
+PHY-3001 : eco cells: (35 22 3) is for feedthrough
+PHY-3001 : eco cells: (35 23 1) is for feedthrough
+PHY-3001 : eco cells: (35 24 1) is for feedthrough
+PHY-3001 : eco cells: (35 26 0) is for feedthrough
+PHY-3001 : eco cells: (35 27 2) is for feedthrough
+PHY-3001 : eco cells: (35 28 2) is for feedthrough
+PHY-3001 : eco cells: (35 29 1) is for feedthrough
+PHY-3001 : eco cells: (35 31 2) is for feedthrough
+PHY-3001 : eco cells: (35 32 2) is for feedthrough
+PHY-3001 : eco cells: (35 39 0) is for feedthrough
+PHY-3001 : eco cells: (35 42 0) is for feedthrough
+PHY-3001 : eco cells: (35 68 1) is for feedthrough
+PHY-3001 : eco cells: (36 7 2) is for feedthrough
+PHY-3001 : eco cells: (36 9 1) is for feedthrough
+PHY-3001 : eco cells: (36 11 0) is for feedthrough
+PHY-3001 : eco cells: (36 18 2) is for feedthrough
+PHY-3001 : eco cells: (36 18 3) is for feedthrough
+PHY-3001 : eco cells: (36 19 2) is for feedthrough
+PHY-3001 : eco cells: (36 22 3) is for feedthrough
+PHY-3001 : eco cells: (36 24 1) is for feedthrough
+PHY-3001 : eco cells: (36 25 0) is for feedthrough
+PHY-3001 : eco cells: (36 25 1) is for feedthrough
+PHY-3001 : eco cells: (36 26 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 0) is for feedthrough
+PHY-3001 : eco cells: (36 28 3) is for feedthrough
+PHY-3001 : eco cells: (36 29 1) is for feedthrough
+PHY-3001 : eco cells: (36 34 3) is for feedthrough
+PHY-3001 : eco cells: (36 36 2) is for feedthrough
+PHY-3001 : eco cells: (36 37 1) is for feedthrough
+PHY-3001 : eco cells: (36 39 1) is for feedthrough
+PHY-3001 : eco cells: (36 40 2) is for feedthrough
+PHY-3001 : eco cells: (36 41 1) is for feedthrough
+PHY-3001 : eco cells: (36 44 2) is for feedthrough
+PHY-3001 : eco cells: (36 46 2) is for feedthrough
+PHY-3001 : eco cells: (36 55 1) is for feedthrough
+PHY-3001 : eco cells: (37 4 0) is for feedthrough
+PHY-3001 : eco cells: (37 18 3) is for feedthrough
+PHY-3001 : eco cells: (37 21 0) is for feedthrough
+PHY-3001 : eco cells: (37 25 0) is for feedthrough
+PHY-3001 : eco cells: (37 25 3) is for feedthrough
+PHY-3001 : eco cells: (37 26 3) is for feedthrough
+PHY-3001 : eco cells: (37 34 3) is for feedthrough
+PHY-3001 : eco cells: (37 37 0) is for feedthrough
+PHY-3001 : eco cells: (37 37 1) is for feedthrough
+PHY-3001 : eco cells: (37 39 0) is for feedthrough
+PHY-3001 : eco cells: (37 44 0) is for feedthrough
+PHY-3001 : eco cells: (37 44 1) is for feedthrough
+PHY-3001 : eco cells: (37 46 1) is for feedthrough
+PHY-3001 : eco cells: (37 49 0) is for feedthrough
+PHY-3001 : eco cells: (38 18 0) is for feedthrough
+PHY-3001 : eco cells: (38 20 0) is for feedthrough
+PHY-3001 : eco cells: (38 20 1) is for feedthrough
+PHY-3001 : eco cells: (38 25 1) is for feedthrough
+PHY-3001 : eco cells: (38 27 1) is for feedthrough
+PHY-3001 : eco cells: (38 28 0) is for feedthrough
+PHY-3001 : eco cells: (38 28 1) is for feedthrough
+PHY-3001 : eco cells: (38 29 3) is for feedthrough
+PHY-3001 : eco cells: (38 43 3) is for feedthrough
+PHY-3001 : eco cells: (38 44 3) is for feedthrough
+PHY-3001 : eco cells: (39 1 1) is for feedthrough
+PHY-3001 : eco cells: (39 4 2) is for feedthrough
+PHY-3001 : eco cells: (39 5 3) is for feedthrough
+PHY-3001 : eco cells: (39 26 2) is for feedthrough
+PHY-3001 : eco cells: 6953 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7041 instances, 6892 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3753 pins
+PHY-3001 : Start timing update ...
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 17581 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.801613s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.4%)
+
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : End placement; No cells to be placed.
+RUN-1003 : finish command "place -eco" in  1.240432s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.8%)
+
+RUN-1004 : used memory is 1156 MB, reserved memory is 1160 MB, peak memory is 1174 MB
+RUN-1001 : Eco place succeeded
+RUN-1002 : start command "route -eco"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7043 instances
+RUN-1001 : 3429 mslices, 3463 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17759 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 10026 nets have 2 pins
+RUN-1001 : 5764 nets have [3 - 5] pins
+RUN-1001 : 1206 nets have [6 - 10] pins
+RUN-1001 : 386 nets have [11 - 20] pins
+RUN-1001 : 348 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+PHY-1001 : 3429 mslices, 3463 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17581 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 1153, reserve = 1157, peak = 1174.
+PHY-1001 : Detailed router is running in eco mode.
+PHY-1001 : Refresh detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1173, peak = 1174.
+PHY-1001 : End build detailed router design. 1.888874s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 0.021711s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (143.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.030418s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (102.7%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.030593s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.030381s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (102.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.031183s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.031550s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (99.0%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1173, peak = 1174.
+PHY-1001 : End phase 1; 0.216890s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (100.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1173, peak = 1174.
+PHY-1001 : End initial routed; 0.146058s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (107.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1991/16687(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -5.690   |  -3521.438  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.287582s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1177, reserve = 1182, peak = 1177.
+PHY-1001 : End phase 2; 3.433695s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 15 pins with SWNS -5.690ns STNS -3521.438ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.130845s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.5%)
+
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.358842s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.134791s wall, 0.156250s user + 0.015625s system = 0.171875s CPU (127.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.136561s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.138593s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.138728s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.4%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.140262s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.3%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.141531s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.4%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.143067s wall, 0.187500s user + 0.015625s system = 0.203125s CPU (142.0%)
+
+PHY-1001 : ==== DR Iter 8 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.134525s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.9%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 9; 0.134041s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 10 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 10; 0.132884s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.1%)
+
+PHY-1001 : ==== DR Iter 11 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 11; 0.134384s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.0%)
+
+PHY-1001 : ===== DR Iter 12 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 12; 0.137910s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.0%)
+
+PHY-1001 : ==== DR Iter 13 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 13; 0.134674s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.4%)
+
+PHY-1001 : ==== DR Iter 14 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 14; 0.132169s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.6%)
+
+PHY-1001 : ==== DR Iter 15 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 15; 0.134387s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.6%)
+
+PHY-1001 : ==== DR Iter 16 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 16; 0.134913s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.7%)
+
+PHY-1001 : ==== DR Iter 17 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 17; 0.133744s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.1%)
+
+PHY-1001 : ===== DR Iter 18 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 18; 0.137582s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 19 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 19; 0.133764s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.1%)
+
+PHY-1001 : ==== DR Iter 20 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 20; 0.132935s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.0%)
+
+PHY-1001 : ==== DR Iter 21 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 21; 0.132412s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.2%)
+
+PHY-1001 : ==== DR Iter 22 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 22; 0.134010s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.3%)
+
+PHY-1001 : ==== DR Iter 23 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 23; 0.134223s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.8%)
+
+PHY-1001 : ==== DR Iter 24 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 24; 0.134225s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.1%)
+
+PHY-1001 : ===== DR Iter 25 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 25; 0.136115s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.3%)
+
+PHY-1001 : ==== DR Iter 26 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 26; 0.133318s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (117.2%)
+
+PHY-1001 : ==== DR Iter 27 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 27; 0.132846s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.9%)
+
+PHY-1001 : ==== DR Iter 28 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 28; 0.133196s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 29 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 29; 0.135411s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.9%)
+
+PHY-1001 : ==== DR Iter 30 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 30; 0.133225s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 31 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 31; 0.132979s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.8%)
+
+PHY-1001 : ==== DR Iter 32 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 32; 0.162242s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (96.3%)
+
+PHY-1001 : ===== DR Iter 33 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 33; 0.137342s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (125.1%)
+
+PHY-1001 : ==== DR Iter 34 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 34; 0.133623s wall, 0.125000s user + 0.015625s system = 0.140625s CPU (105.2%)
+
+PHY-1001 : ==== DR Iter 35 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 35; 0.135617s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.7%)
+
+PHY-1001 : ==== DR Iter 36 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 36; 0.133055s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.9%)
+
+PHY-1001 : ==== DR Iter 37 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 37; 0.134488s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.6%)
+
+PHY-1001 : ==== DR Iter 38 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 38; 0.134791s wall, 0.109375s user + 0.015625s system = 0.125000s CPU (92.7%)
+
+PHY-1001 : ==== DR Iter 39 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 39; 0.134892s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.2%)
+
+PHY-1001 : ==== DR Iter 40 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 40; 0.133734s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.5%)
+
+PHY-1001 : ==== DR Iter 41 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 41; 0.135076s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.1%)
+
+PHY-1001 : ===== DR Iter 42 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 42; 0.137612s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (113.5%)
+
+PHY-1001 : ==== DR Iter 43 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 43; 0.132687s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 44 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 44; 0.134009s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.3%)
+
+PHY-1001 : ==== DR Iter 45 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 45; 0.133547s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.3%)
+
+PHY-1001 : ==== DR Iter 46 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 46; 0.134088s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.2%)
+
+PHY-1001 : ==== DR Iter 47 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 47; 0.134903s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.2%)
+
+PHY-1001 : ==== DR Iter 48 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 48; 0.133553s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.3%)
+
+PHY-1001 : ==== DR Iter 49 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 49; 0.137412s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (91.0%)
+
+PHY-1001 : ==== DR Iter 50 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 50; 0.134346s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 51 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 51; 0.132696s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.0%)
+
+PHY-1001 : ===== DR Iter 52 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 52; 0.138490s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (90.3%)
+
+PHY-1001 : ==== DR Iter 53 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 53; 0.132652s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.2%)
+
+PHY-1001 : ==== DR Iter 54 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 54; 0.133998s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.9%)
+
+PHY-1001 : ==== DR Iter 55 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 55; 0.133424s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.7%)
+
+PHY-1001 : ==== DR Iter 56 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 56; 0.135884s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (138.0%)
+
+PHY-1001 : ==== DR Iter 57 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 57; 0.133236s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.5%)
+
+PHY-1001 : ==== DR Iter 58 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 58; 0.134251s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.1%)
+
+PHY-1001 : ==== DR Iter 59 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 59; 0.134624s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.5%)
+
+PHY-1001 : ==== DR Iter 60 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 60; 0.133194s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.8%)
+
+PHY-1001 : ==== DR Iter 61 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 61; 0.135143s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.1%)
+
+PHY-1001 : ==== DR Iter 62 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 62; 0.133047s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.0%)
+
+PHY-1001 : ===== DR Iter 63 =====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 63; 0.138503s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (101.5%)
+
+PHY-1001 : ==== DR Iter 64 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 64; 0.133848s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.4%)
+
+PHY-1001 : ==== DR Iter 65 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 65; 0.132615s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (106.0%)
+
+PHY-1001 : ==== DR Iter 66 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 66; 0.134483s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.9%)
+
+PHY-1001 : ==== DR Iter 67 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 67; 0.133685s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.2%)
+
+PHY-1001 : ==== DR Iter 68 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 68; 0.132507s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.3%)
+
+PHY-1001 : ==== DR Iter 69 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 69; 0.133482s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.4%)
+
+PHY-1001 : ==== DR Iter 70 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 70; 0.133136s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (93.9%)
+
+PHY-1001 : ==== DR Iter 71 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 71; 0.134949s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.2%)
+
+PHY-1001 : ==== DR Iter 72 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 72; 0.133597s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.3%)
+
+PHY-1001 : ==== DR Iter 73 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 73; 0.135473s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (92.3%)
+
+PHY-1001 : ==== DR Iter 74 ====
+PHY-1022 : len = 2.34535e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 74; 0.133996s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1991/16687(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -5.690   |  -3521.438  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.325453s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1179, reserve = 1184, peak = 1179.
+PHY-1001 : End phase 3; 13.797797s wall, 13.890625s user + 0.093750s system = 13.984375s CPU (101.4%)
+
+PHY-1001 : 579 feed throughs used by 442 nets
+PHY-1001 : Current memory(MB): used = 1185, reserve = 1190, peak = 1185.
+PHY-1001 : End export database. 2.492147s wall, 2.484375s user + 0.000000s system = 2.484375s CPU (99.7%)
+
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x13y43_e2beg4), nets: sampling_fe_b/u_sort/u_transfer_300_to_200/mux11_syn_103 sampling_fe_b/u_sort/u_transfer_300_to_200/data_tmp_b2_n
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route -eco" in  22.986864s wall, 23.078125s user + 0.093750s system = 23.171875s CPU (100.8%)
+
+RUN-1004 : used memory is 1182 MB, reserved memory is 1187 MB, peak memory is 1185 MB
+RUN-8102 ERROR: Incremental route failed
+PHY-1001 : Routing violations:
+PHY-8023 ERROR: Location: (x13y43_e2beg4), nets: sampling_fe_b/u_sort/u_transfer_300_to_200/mux11_syn_103 sampling_fe_b/u_sort/u_transfer_300_to_200/data_tmp_b2_n
+PHY-1001 : End of Routing Violations.
+RUN-1003 : finish command "route" in  156.438525s wall, 187.734375s user + 0.718750s system = 188.453125s CPU (120.5%)
+
+RUN-1004 : used memory is 1182 MB, reserved memory is 1187 MB, peak memory is 1185 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_115302.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_115806.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_115806.log
new file mode 100644
index 0000000..1506c08
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_115806.log
@@ -0,0 +1,1980 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:58:06 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.218493s wall, 2.140625s user + 0.078125s system = 2.218750s CPU (100.0%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17833 instances
+RUN-0007 : 7532 luts, 9084 seqs, 696 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20398 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13452 nets have 2 pins
+RUN-1001 : 5463 nets have [3 - 5] pins
+RUN-1001 : 1067 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17831 instances, 7532 luts, 9084 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5973 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.150803s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.1%)
+
+RUN-1004 : used memory is 540 MB, reserved memory is 516 MB, peak memory is 540 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.938122s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (100.0%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.07528e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17831.
+PHY-3001 : Level 1 #clusters 2336.
+PHY-3001 : End clustering;  0.126379s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (111.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.34206e+06, overlap = 478.25
+PHY-3002 : Step(2): len = 1.03976e+06, overlap = 534.469
+PHY-3002 : Step(3): len = 841044, overlap = 621.094
+PHY-3002 : Step(4): len = 711929, overlap = 682.5
+PHY-3002 : Step(5): len = 556822, overlap = 807.438
+PHY-3002 : Step(6): len = 477796, overlap = 909.281
+PHY-3002 : Step(7): len = 406909, overlap = 949.688
+PHY-3002 : Step(8): len = 365407, overlap = 990.625
+PHY-3002 : Step(9): len = 329994, overlap = 1059.88
+PHY-3002 : Step(10): len = 293384, overlap = 1117.53
+PHY-3002 : Step(11): len = 266294, overlap = 1164.62
+PHY-3002 : Step(12): len = 252222, overlap = 1199.88
+PHY-3002 : Step(13): len = 229564, overlap = 1234.44
+PHY-3002 : Step(14): len = 214493, overlap = 1267.16
+PHY-3002 : Step(15): len = 198624, overlap = 1306.41
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.46297e-07
+PHY-3002 : Step(16): len = 199686, overlap = 1290.28
+PHY-3002 : Step(17): len = 223974, overlap = 1233.69
+PHY-3002 : Step(18): len = 230968, overlap = 1190.5
+PHY-3002 : Step(19): len = 233607, overlap = 1182.31
+PHY-3002 : Step(20): len = 231127, overlap = 1165
+PHY-3002 : Step(21): len = 229662, overlap = 1165.88
+PHY-3002 : Step(22): len = 225326, overlap = 1148.53
+PHY-3002 : Step(23): len = 223613, overlap = 1125.41
+PHY-3002 : Step(24): len = 218275, overlap = 1126.25
+PHY-3002 : Step(25): len = 215032, overlap = 1138.78
+PHY-3002 : Step(26): len = 209156, overlap = 1126.78
+PHY-3002 : Step(27): len = 204843, overlap = 1122.41
+PHY-3002 : Step(28): len = 198950, overlap = 1139.78
+PHY-3002 : Step(29): len = 195587, overlap = 1156.72
+PHY-3002 : Step(30): len = 192350, overlap = 1158.03
+PHY-3002 : Step(31): len = 191154, overlap = 1160.31
+PHY-3002 : Step(32): len = 188922, overlap = 1153.84
+PHY-3002 : Step(33): len = 186718, overlap = 1147.28
+PHY-3002 : Step(34): len = 184798, overlap = 1146.5
+PHY-3002 : Step(35): len = 183870, overlap = 1141.97
+PHY-3002 : Step(36): len = 181912, overlap = 1145.28
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.89259e-06
+PHY-3002 : Step(37): len = 185784, overlap = 1125.12
+PHY-3002 : Step(38): len = 198635, overlap = 1055.47
+PHY-3002 : Step(39): len = 206073, overlap = 996.688
+PHY-3002 : Step(40): len = 212064, overlap = 956.875
+PHY-3002 : Step(41): len = 215587, overlap = 928.531
+PHY-3002 : Step(42): len = 215911, overlap = 919.625
+PHY-3002 : Step(43): len = 215206, overlap = 902.875
+PHY-3002 : Step(44): len = 214903, overlap = 899.031
+PHY-3002 : Step(45): len = 214966, overlap = 899.344
+PHY-3002 : Step(46): len = 213102, overlap = 903.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.78519e-06
+PHY-3002 : Step(47): len = 222500, overlap = 879.375
+PHY-3002 : Step(48): len = 239824, overlap = 821.25
+PHY-3002 : Step(49): len = 247632, overlap = 766.938
+PHY-3002 : Step(50): len = 250250, overlap = 717.312
+PHY-3002 : Step(51): len = 250858, overlap = 720.781
+PHY-3002 : Step(52): len = 251337, overlap = 718.625
+PHY-3002 : Step(53): len = 250346, overlap = 719.281
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.57038e-06
+PHY-3002 : Step(54): len = 266497, overlap = 687.438
+PHY-3002 : Step(55): len = 284766, overlap = 618.844
+PHY-3002 : Step(56): len = 290612, overlap = 598.312
+PHY-3002 : Step(57): len = 292779, overlap = 562.969
+PHY-3002 : Step(58): len = 291367, overlap = 555
+PHY-3002 : Step(59): len = 290725, overlap = 546.062
+PHY-3002 : Step(60): len = 289615, overlap = 544.031
+PHY-3002 : Step(61): len = 289732, overlap = 546.625
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.51408e-05
+PHY-3002 : Step(62): len = 311431, overlap = 490.062
+PHY-3002 : Step(63): len = 328168, overlap = 445.906
+PHY-3002 : Step(64): len = 333733, overlap = 411.562
+PHY-3002 : Step(65): len = 337088, overlap = 390.094
+PHY-3002 : Step(66): len = 337200, overlap = 386.688
+PHY-3002 : Step(67): len = 338667, overlap = 383.906
+PHY-3002 : Step(68): len = 337565, overlap = 391.031
+PHY-3002 : Step(69): len = 338510, overlap = 393.688
+PHY-3002 : Step(70): len = 338766, overlap = 395.562
+PHY-3002 : Step(71): len = 338962, overlap = 397.438
+PHY-3002 : Step(72): len = 337619, overlap = 379.688
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.02815e-05
+PHY-3002 : Step(73): len = 358389, overlap = 348.469
+PHY-3002 : Step(74): len = 373279, overlap = 321.438
+PHY-3002 : Step(75): len = 374154, overlap = 287.562
+PHY-3002 : Step(76): len = 376036, overlap = 282.312
+PHY-3002 : Step(77): len = 378003, overlap = 269.906
+PHY-3002 : Step(78): len = 381357, overlap = 256.188
+PHY-3002 : Step(79): len = 378037, overlap = 261.531
+PHY-3002 : Step(80): len = 377895, overlap = 253.75
+PHY-3002 : Step(81): len = 379194, overlap = 249.562
+PHY-3002 : Step(82): len = 381755, overlap = 259.25
+PHY-3002 : Step(83): len = 380590, overlap = 260.938
+PHY-3002 : Step(84): len = 381300, overlap = 246.469
+PHY-3002 : Step(85): len = 381392, overlap = 250.938
+PHY-3002 : Step(86): len = 382724, overlap = 255.375
+PHY-3002 : Step(87): len = 380159, overlap = 259.75
+PHY-3002 : Step(88): len = 381474, overlap = 259.5
+PHY-3002 : Step(89): len = 381443, overlap = 256.438
+PHY-3002 : Step(90): len = 383150, overlap = 249.406
+PHY-3002 : Step(91): len = 381557, overlap = 255
+PHY-3002 : Step(92): len = 381708, overlap = 255.312
+PHY-3002 : Step(93): len = 380201, overlap = 244.406
+PHY-3002 : Step(94): len = 379918, overlap = 249.031
+PHY-3002 : Step(95): len = 379378, overlap = 252.625
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.0563e-05
+PHY-3002 : Step(96): len = 394401, overlap = 233.5
+PHY-3002 : Step(97): len = 405346, overlap = 204.938
+PHY-3002 : Step(98): len = 406774, overlap = 193.406
+PHY-3002 : Step(99): len = 408226, overlap = 193.719
+PHY-3002 : Step(100): len = 410163, overlap = 193.562
+PHY-3002 : Step(101): len = 413635, overlap = 197.125
+PHY-3002 : Step(102): len = 411632, overlap = 196.375
+PHY-3002 : Step(103): len = 412063, overlap = 185.188
+PHY-3002 : Step(104): len = 413243, overlap = 192.312
+PHY-3002 : Step(105): len = 414945, overlap = 185.188
+PHY-3002 : Step(106): len = 412023, overlap = 179.125
+PHY-3002 : Step(107): len = 412289, overlap = 186.031
+PHY-3002 : Step(108): len = 413249, overlap = 179.906
+PHY-3002 : Step(109): len = 415200, overlap = 176.469
+PHY-3002 : Step(110): len = 412147, overlap = 177.812
+PHY-3002 : Step(111): len = 412396, overlap = 178.656
+PHY-3002 : Step(112): len = 412948, overlap = 180.438
+PHY-3002 : Step(113): len = 413896, overlap = 176
+PHY-3002 : Step(114): len = 411642, overlap = 183.219
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000117109
+PHY-3002 : Step(115): len = 424606, overlap = 162.656
+PHY-3002 : Step(116): len = 433290, overlap = 163.062
+PHY-3002 : Step(117): len = 433161, overlap = 164.844
+PHY-3002 : Step(118): len = 434060, overlap = 157.625
+PHY-3002 : Step(119): len = 436988, overlap = 158.906
+PHY-3002 : Step(120): len = 440198, overlap = 159.438
+PHY-3002 : Step(121): len = 438514, overlap = 156.125
+PHY-3002 : Step(122): len = 439372, overlap = 168.781
+PHY-3002 : Step(123): len = 442030, overlap = 171.906
+PHY-3002 : Step(124): len = 443718, overlap = 171.219
+PHY-3002 : Step(125): len = 441411, overlap = 172.719
+PHY-3002 : Step(126): len = 441647, overlap = 172.562
+PHY-3002 : Step(127): len = 442833, overlap = 175.031
+PHY-3002 : Step(128): len = 444153, overlap = 186.281
+PHY-3002 : Step(129): len = 441868, overlap = 176.312
+PHY-3002 : Step(130): len = 441510, overlap = 181.469
+PHY-3002 : Step(131): len = 442613, overlap = 180.094
+PHY-3002 : Step(132): len = 443792, overlap = 168.219
+PHY-3002 : Step(133): len = 441703, overlap = 171
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000220907
+PHY-3002 : Step(134): len = 450612, overlap = 162.625
+PHY-3002 : Step(135): len = 457561, overlap = 166.406
+PHY-3002 : Step(136): len = 457913, overlap = 161.875
+PHY-3002 : Step(137): len = 458814, overlap = 154.031
+PHY-3002 : Step(138): len = 462082, overlap = 145.906
+PHY-3002 : Step(139): len = 464189, overlap = 137.125
+PHY-3002 : Step(140): len = 462771, overlap = 143.062
+PHY-3002 : Step(141): len = 463112, overlap = 141.531
+PHY-3002 : Step(142): len = 466165, overlap = 125.125
+PHY-3002 : Step(143): len = 468540, overlap = 123.875
+PHY-3002 : Step(144): len = 466144, overlap = 124.375
+PHY-3002 : Step(145): len = 465953, overlap = 126.469
+PHY-3002 : Step(146): len = 467174, overlap = 122.781
+PHY-3002 : Step(147): len = 468001, overlap = 122.969
+PHY-3002 : Step(148): len = 466754, overlap = 121.438
+PHY-3002 : Step(149): len = 466617, overlap = 119.594
+PHY-3002 : Step(150): len = 467420, overlap = 121.281
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000441815
+PHY-3002 : Step(151): len = 473295, overlap = 118.5
+PHY-3002 : Step(152): len = 481360, overlap = 123.125
+PHY-3002 : Step(153): len = 486416, overlap = 121.906
+PHY-3002 : Step(154): len = 488078, overlap = 115.812
+PHY-3002 : Step(155): len = 488869, overlap = 121.906
+PHY-3002 : Step(156): len = 489870, overlap = 118.781
+PHY-3002 : Step(157): len = 489830, overlap = 120.531
+PHY-3002 : Step(158): len = 489986, overlap = 122.031
+PHY-3002 : Step(159): len = 489706, overlap = 113.312
+PHY-3002 : Step(160): len = 489555, overlap = 105.938
+PHY-3002 : Step(161): len = 490104, overlap = 101.281
+PHY-3002 : Step(162): len = 491500, overlap = 104.844
+PHY-3002 : Step(163): len = 492932, overlap = 100.094
+PHY-3002 : Step(164): len = 493951, overlap = 97.875
+PHY-3002 : Step(165): len = 494337, overlap = 98.25
+PHY-3002 : Step(166): len = 495377, overlap = 98.7188
+PHY-3002 : Step(167): len = 495218, overlap = 96.625
+PHY-3002 : Step(168): len = 495815, overlap = 100
+PHY-3002 : Step(169): len = 495138, overlap = 103.844
+PHY-3002 : Step(170): len = 494697, overlap = 97.7812
+PHY-3002 : Step(171): len = 494348, overlap = 103.719
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000833566
+PHY-3002 : Step(172): len = 496802, overlap = 96.125
+PHY-3002 : Step(173): len = 500170, overlap = 94.3438
+PHY-3002 : Step(174): len = 501536, overlap = 93.8125
+PHY-3002 : Step(175): len = 502062, overlap = 93.5625
+PHY-3002 : Step(176): len = 502293, overlap = 86.7812
+PHY-3002 : Step(177): len = 502359, overlap = 88.0312
+PHY-3002 : Step(178): len = 502499, overlap = 90.0625
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015007s wall, 0.031250s user + 0.031250s system = 0.062500s CPU (416.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 670088, over cnt = 1369(3%), over = 5856, worst = 25
+PHY-1001 : End global iterations;  0.774533s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (133.1%)
+
+PHY-1001 : Congestion index: top1 = 74.35, top5 = 55.08, top10 = 47.06, top15 = 42.50.
+PHY-3001 : End congestion estimation;  1.003353s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (124.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.855872s wall, 0.828125s user + 0.031250s system = 0.859375s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.87269e-05
+PHY-3002 : Step(179): len = 611094, overlap = 36.7812
+PHY-3002 : Step(180): len = 629498, overlap = 29.875
+PHY-3002 : Step(181): len = 617273, overlap = 25.8438
+PHY-3002 : Step(182): len = 612122, overlap = 29.4062
+PHY-3002 : Step(183): len = 603530, overlap = 27.4062
+PHY-3002 : Step(184): len = 600128, overlap = 31.7188
+PHY-3002 : Step(185): len = 598912, overlap = 35.125
+PHY-3002 : Step(186): len = 591598, overlap = 39.6875
+PHY-3002 : Step(187): len = 588955, overlap = 40.75
+PHY-3002 : Step(188): len = 587415, overlap = 42.9062
+PHY-3002 : Step(189): len = 584589, overlap = 43.9688
+PHY-3002 : Step(190): len = 583403, overlap = 40.2812
+PHY-3002 : Step(191): len = 582336, overlap = 41.875
+PHY-3002 : Step(192): len = 579818, overlap = 40.4062
+PHY-3002 : Step(193): len = 579688, overlap = 40.4688
+PHY-3002 : Step(194): len = 578791, overlap = 39.6562
+PHY-3002 : Step(195): len = 578211, overlap = 41.8438
+PHY-3002 : Step(196): len = 576508, overlap = 42.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000177454
+PHY-3002 : Step(197): len = 578960, overlap = 42.3125
+PHY-3002 : Step(198): len = 582750, overlap = 40.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00033251
+PHY-3002 : Step(199): len = 589819, overlap = 40.0312
+PHY-3002 : Step(200): len = 599950, overlap = 39.5625
+PHY-3002 : Step(201): len = 610813, overlap = 40.7812
+PHY-3002 : Step(202): len = 609601, overlap = 38.375
+PHY-3002 : Step(203): len = 609605, overlap = 42.125
+PHY-3002 : Step(204): len = 606844, overlap = 42.1875
+PHY-3002 : Step(205): len = 608246, overlap = 40.5312
+PHY-3002 : Step(206): len = 610102, overlap = 42.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 81/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700840, over cnt = 2513(7%), over = 10808, worst = 39
+PHY-1001 : End global iterations;  1.612394s wall, 2.031250s user + 0.000000s system = 2.031250s CPU (126.0%)
+
+PHY-1001 : Congestion index: top1 = 78.38, top5 = 62.45, top10 = 54.94, top15 = 50.21.
+PHY-3001 : End congestion estimation;  1.890544s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (122.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.921748s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.76412e-05
+PHY-3002 : Step(207): len = 607916, overlap = 243.156
+PHY-3002 : Step(208): len = 614129, overlap = 201.344
+PHY-3002 : Step(209): len = 604854, overlap = 190.406
+PHY-3002 : Step(210): len = 600997, overlap = 164.438
+PHY-3002 : Step(211): len = 599911, overlap = 150.625
+PHY-3002 : Step(212): len = 592757, overlap = 151.875
+PHY-3002 : Step(213): len = 589373, overlap = 147.062
+PHY-3002 : Step(214): len = 586562, overlap = 148.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000195282
+PHY-3002 : Step(215): len = 586411, overlap = 142.344
+PHY-3002 : Step(216): len = 589367, overlap = 136.5
+PHY-3002 : Step(217): len = 593452, overlap = 139
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000390565
+PHY-3002 : Step(218): len = 597222, overlap = 136.312
+PHY-3002 : Step(219): len = 605582, overlap = 129.281
+PHY-3002 : Step(220): len = 610957, overlap = 126.594
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.471612s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (99.8%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 565 MB, peak memory is 720 MB
+OPT-1001 : Total overflow 483.00 peak overflow 4.50
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 927/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709096, over cnt = 2790(7%), over = 9868, worst = 32
+PHY-1001 : End global iterations;  1.129917s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 65.97, top5 = 55.56, top10 = 50.03, top15 = 46.28.
+PHY-1001 : End incremental global routing;  1.452565s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (129.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.924118s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.8%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17699 has valid locations, 336 needs to be replaced
+PHY-3001 : design contains 18120 instances, 7611 luts, 9294 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6106 pins
+PHY-3001 : Found 1235 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 635943
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16069/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 726368, over cnt = 2806(7%), over = 10011, worst = 32
+PHY-1001 : End global iterations;  0.244867s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (140.4%)
+
+PHY-1001 : Congestion index: top1 = 66.06, top5 = 56.06, top10 = 50.50, top15 = 46.76.
+PHY-3001 : End congestion estimation;  0.498066s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (116.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86724, tnet num: 20509, tinst num: 18120, tnode num: 117570, tedge num: 139118.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.476712s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (100.5%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 620 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.447703s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(221): len = 634898, overlap = 0.0625
+PHY-3002 : Step(222): len = 634748, overlap = 0.0625
+PHY-3002 : Step(223): len = 634259, overlap = 0.0625
+PHY-3002 : Step(224): len = 634212, overlap = 0.0625
+PHY-3002 : Step(225): len = 634443, overlap = 0.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16115/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720960, over cnt = 2817(8%), over = 10052, worst = 32
+PHY-1001 : End global iterations;  0.226861s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (130.9%)
+
+PHY-1001 : Congestion index: top1 = 66.66, top5 = 56.13, top10 = 50.65, top15 = 46.95.
+PHY-3001 : End congestion estimation;  0.477119s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (117.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.935133s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000368783
+PHY-3002 : Step(226): len = 634901, overlap = 128.969
+PHY-3002 : Step(227): len = 635133, overlap = 129.406
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000737566
+PHY-3002 : Step(228): len = 635100, overlap = 129
+PHY-3002 : Step(229): len = 635452, overlap = 129.156
+PHY-3001 : Final: Len = 635452, Over = 129.156
+PHY-3001 : End incremental placement;  5.033011s wall, 5.375000s user + 0.140625s system = 5.515625s CPU (109.6%)
+
+OPT-1001 : Total overflow 488.25 peak overflow 4.50
+OPT-1001 : End high-fanout net optimization;  8.024009s wall, 8.859375s user + 0.171875s system = 9.031250s CPU (112.6%)
+
+OPT-1001 : Current memory(MB): used = 725, reserve = 711, peak = 742.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16129/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724912, over cnt = 2776(7%), over = 9260, worst = 32
+PHY-1002 : len = 771056, over cnt = 1914(5%), over = 4806, worst = 20
+PHY-1002 : len = 811472, over cnt = 854(2%), over = 1834, worst = 20
+PHY-1002 : len = 836944, over cnt = 75(0%), over = 88, worst = 5
+PHY-1002 : len = 838664, over cnt = 4(0%), over = 7, worst = 4
+PHY-1001 : End global iterations;  1.944954s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (131.8%)
+
+PHY-1001 : Congestion index: top1 = 58.21, top5 = 50.55, top10 = 46.61, top15 = 44.11.
+OPT-1001 : End congestion update;  2.208756s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (128.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.811295s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (100.1%)
+
+OPT-0007 : Start: WNS -5085 TNS -2609047 NUM_FEPS 1053
+OPT-0007 : Iter 1: improved WNS -4519 TNS -2534293 NUM_FEPS 1053 with 70 cells processed and 1666 slack improved
+OPT-0007 : Iter 2: improved WNS -4519 TNS -2532645 NUM_FEPS 1053 with 93 cells processed and 1400 slack improved
+OPT-0007 : Iter 3: improved WNS -4519 TNS -2532045 NUM_FEPS 1053 with 38 cells processed and 700 slack improved
+OPT-0007 : Iter 4: improved WNS -4469 TNS -2533115 NUM_FEPS 1053 with 11 cells processed and 150 slack improved
+OPT-0007 : Iter 5: improved WNS -4469 TNS -2531639 NUM_FEPS 1053 with 23 cells processed and 400 slack improved
+OPT-0007 : Iter 6: improved WNS -4469 TNS -2531539 NUM_FEPS 1053 with 8 cells processed and 200 slack improved
+OPT-0007 : Iter 7: improved WNS -4269 TNS -2466901 NUM_FEPS 1053 with 1 cells processed and 484 slack improved
+OPT-0007 : Iter 8: improved WNS -4269 TNS -2465323 NUM_FEPS 1053 with 1 cells processed and 250 slack improved
+OPT-1001 : End bottleneck based optimization;  3.906654s wall, 4.531250s user + 0.000000s system = 4.531250s CPU (116.0%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 691, peak = 742.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16289/20689.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842512, over cnt = 169(0%), over = 315, worst = 10
+PHY-1002 : len = 843544, over cnt = 100(0%), over = 127, worst = 4
+PHY-1002 : len = 844216, over cnt = 48(0%), over = 55, worst = 3
+PHY-1002 : len = 844824, over cnt = 20(0%), over = 22, worst = 2
+PHY-1002 : len = 845256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.771965s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (109.3%)
+
+PHY-1001 : Congestion index: top1 = 57.97, top5 = 50.51, top10 = 46.63, top15 = 44.17.
+OPT-1001 : End congestion update;  1.063156s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (107.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20511 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.815659s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (101.5%)
+
+OPT-0007 : Start: WNS -4269 TNS -2465323 NUM_FEPS 1053
+OPT-0007 : Iter 1: improved WNS -4269 TNS -2461823 NUM_FEPS 1053 with 53 cells processed and 3650 slack improved
+OPT-0007 : Iter 2: improved WNS -4269 TNS -2461823 NUM_FEPS 1053 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.020709s wall, 2.109375s user + 0.000000s system = 2.109375s CPU (104.4%)
+
+OPT-1001 : Current memory(MB): used = 700, reserve = 687, peak = 742.
+OPT-1001 : End physical optimization;  15.730130s wall, 17.328125s user + 0.203125s system = 17.531250s CPU (111.5%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7611 LUT to BLE ...
+SYN-4008 : Packed 7611 LUT and 3144 SEQ to BLE.
+SYN-4003 : Packing 6152 remaining SEQ's ...
+SYN-4005 : Packed 3681 SEQ with LUT/SLICE
+SYN-4006 : 1091 single LUT's are left
+SYN-4006 : 2471 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10082/13895 primitive instances ...
+PHY-3001 : End packing;  1.640372s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6984 instances
+RUN-1001 : 3418 mslices, 3418 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17664 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 5811 nets have [3 - 5] pins
+RUN-1001 : 1182 nets have [6 - 10] pins
+RUN-1001 : 302 nets have [11 - 20] pins
+RUN-1001 : 358 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6982 instances, 6836 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3611 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 645206, Over = 319
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7494/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 796520, over cnt = 1812(5%), over = 3089, worst = 9
+PHY-1002 : len = 803552, over cnt = 1296(3%), over = 1991, worst = 9
+PHY-1002 : len = 816024, over cnt = 628(1%), over = 965, worst = 7
+PHY-1002 : len = 825936, over cnt = 268(0%), over = 396, worst = 7
+PHY-1002 : len = 831400, over cnt = 39(0%), over = 58, worst = 4
+PHY-1001 : End global iterations;  1.491400s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (138.3%)
+
+PHY-1001 : Congestion index: top1 = 58.36, top5 = 51.00, top10 = 46.93, top15 = 44.43.
+PHY-3001 : End congestion estimation;  1.882520s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74904, tnet num: 17486, tinst num: 6982, tnode num: 97547, tedge num: 125845.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.670698s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.1%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 616 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.560870s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 3.9602e-05
+PHY-3002 : Step(230): len = 631584, overlap = 332.25
+PHY-3002 : Step(231): len = 623648, overlap = 336.5
+PHY-3002 : Step(232): len = 618967, overlap = 344
+PHY-3002 : Step(233): len = 615592, overlap = 337.75
+PHY-3002 : Step(234): len = 613049, overlap = 342.5
+PHY-3002 : Step(235): len = 610060, overlap = 344.75
+PHY-3002 : Step(236): len = 607237, overlap = 346
+PHY-3002 : Step(237): len = 604218, overlap = 350
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 7.9204e-05
+PHY-3002 : Step(238): len = 608379, overlap = 349
+PHY-3002 : Step(239): len = 614345, overlap = 336.75
+PHY-3002 : Step(240): len = 614925, overlap = 333
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000158408
+PHY-3002 : Step(241): len = 625426, overlap = 312
+PHY-3002 : Step(242): len = 631858, overlap = 307.25
+PHY-3002 : Step(243): len = 629581, overlap = 304
+PHY-3002 : Step(244): len = 628797, overlap = 304
+PHY-3002 : Step(245): len = 628888, overlap = 302
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.343246s wall, 0.328125s user + 0.640625s system = 0.968750s CPU (282.2%)
+
+PHY-3001 : Trial Legalized: Len = 742267
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 543/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859264, over cnt = 2760(7%), over = 4945, worst = 9
+PHY-1002 : len = 879648, over cnt = 1784(5%), over = 2628, worst = 8
+PHY-1002 : len = 899120, over cnt = 840(2%), over = 1167, worst = 5
+PHY-1002 : len = 905776, over cnt = 562(1%), over = 741, worst = 5
+PHY-1002 : len = 920296, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.488363s wall, 3.531250s user + 0.031250s system = 3.562500s CPU (143.2%)
+
+PHY-1001 : Congestion index: top1 = 57.13, top5 = 51.95, top10 = 48.89, top15 = 46.76.
+PHY-3001 : End congestion estimation;  2.946147s wall, 3.984375s user + 0.031250s system = 4.015625s CPU (136.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.874429s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000181197
+PHY-3002 : Step(246): len = 696735, overlap = 92.25
+PHY-3002 : Step(247): len = 676996, overlap = 144.25
+PHY-3002 : Step(248): len = 663105, overlap = 191.5
+PHY-3002 : Step(249): len = 656074, overlap = 219.25
+PHY-3002 : Step(250): len = 652221, overlap = 225.5
+PHY-3002 : Step(251): len = 650028, overlap = 230.25
+PHY-3002 : Step(252): len = 648434, overlap = 236.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000362394
+PHY-3002 : Step(253): len = 654148, overlap = 231.5
+PHY-3002 : Step(254): len = 660001, overlap = 234.25
+PHY-3002 : Step(255): len = 662805, overlap = 239
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000724789
+PHY-3002 : Step(256): len = 665647, overlap = 235.5
+PHY-3002 : Step(257): len = 675016, overlap = 225.25
+PHY-3002 : Step(258): len = 681280, overlap = 229.75
+PHY-3002 : Step(259): len = 680141, overlap = 227.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.036571s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (85.4%)
+
+PHY-3001 : Legalized: Len = 724353, Over = 0
+PHY-3001 : Spreading special nets. 566 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.117844s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (92.8%)
+
+PHY-3001 : 829 instances has been re-located, deltaX = 290, deltaY = 488, maxDist = 4.
+PHY-3001 : Final: Len = 736209, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74904, tnet num: 17486, tinst num: 6985, tnode num: 97547, tedge num: 125845.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.897325s wall, 1.859375s user + 0.046875s system = 1.906250s CPU (100.5%)
+
+RUN-1004 : used memory is 623 MB, reserved memory is 612 MB, peak memory is 742 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3013/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862248, over cnt = 2584(7%), over = 4345, worst = 7
+PHY-1002 : len = 877656, over cnt = 1607(4%), over = 2376, worst = 6
+PHY-1002 : len = 900920, over cnt = 397(1%), over = 552, worst = 6
+PHY-1002 : len = 908152, over cnt = 104(0%), over = 149, worst = 4
+PHY-1002 : len = 911608, over cnt = 16(0%), over = 18, worst = 3
+PHY-1001 : End global iterations;  2.187939s wall, 3.062500s user + 0.078125s system = 3.140625s CPU (143.5%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.44, top10 = 47.41, top15 = 45.31.
+PHY-1001 : End incremental global routing;  2.553210s wall, 3.437500s user + 0.078125s system = 3.515625s CPU (137.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.886306s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (98.7%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 739843
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16050/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915144, over cnt = 69(0%), over = 77, worst = 3
+PHY-1002 : len = 915248, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 915496, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 915536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.593770s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (107.9%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.45, top10 = 47.44, top15 = 45.36.
+PHY-3001 : End congestion estimation;  0.906044s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (105.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75067, tnet num: 17503, tinst num: 7002, tnode num: 97741, tedge num: 126046.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.898532s wall, 1.875000s user + 0.015625s system = 1.890625s CPU (99.6%)
+
+RUN-1004 : used memory is 673 MB, reserved memory is 669 MB, peak memory is 742 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.802102s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(260): len = 738594, overlap = 0
+PHY-3002 : Step(261): len = 738218, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16041/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913312, over cnt = 54(0%), over = 63, worst = 3
+PHY-1002 : len = 913488, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 913672, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 913792, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 913840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.767960s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (103.8%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.47, top10 = 47.43, top15 = 45.34.
+PHY-3001 : End congestion estimation;  1.171346s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (102.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.895833s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000332748
+PHY-3002 : Step(262): len = 738049, overlap = 1.25
+PHY-3002 : Step(263): len = 738003, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005994s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 738084, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059977s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.2%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 738104, Over = 0
+PHY-3001 : End incremental placement;  6.258814s wall, 6.546875s user + 0.125000s system = 6.671875s CPU (106.6%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.341289s wall, 11.500000s user + 0.218750s system = 11.718750s CPU (113.3%)
+
+OPT-1001 : Current memory(MB): used = 752, reserve = 744, peak = 758.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16037/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913704, over cnt = 34(0%), over = 43, worst = 4
+PHY-1002 : len = 913840, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 913928, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 913992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.614098s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (99.2%)
+
+PHY-1001 : Congestion index: top1 = 56.08, top5 = 50.44, top10 = 47.42, top15 = 45.33.
+OPT-1001 : End congestion update;  1.018298s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (99.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.837109s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (100.8%)
+
+OPT-0007 : Start: WNS -4188 TNS -2273902 NUM_FEPS 978
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6914 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 738352, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.115901s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (107.9%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 7, deltaY = 18, maxDist = 2.
+PHY-3001 : Final: Len = 738926, Over = 0
+PHY-3001 : End incremental legalization;  0.458480s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.8%)
+
+OPT-0007 : Iter 1: improved WNS -3888 TNS -2268531 NUM_FEPS 978 with 40 cells processed and 4886 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6914 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 739072, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.107360s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (101.9%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 6, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 739464, Over = 0
+PHY-3001 : End incremental legalization;  0.436121s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (125.4%)
+
+OPT-0007 : Iter 2: improved WNS -3988 TNS -2257868 NUM_FEPS 978 with 30 cells processed and 2801 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 739802, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062528s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.0%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 739900, Over = 0
+PHY-3001 : End incremental legalization;  0.391549s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.8%)
+
+OPT-0007 : Iter 3: improved WNS -3988 TNS -2256151 NUM_FEPS 978 with 12 cells processed and 1350 slack improved
+OPT-1001 : End bottleneck based optimization;  3.877599s wall, 4.078125s user + 0.000000s system = 4.078125s CPU (105.2%)
+
+OPT-1001 : Current memory(MB): used = 752, reserve = 744, peak = 758.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15737/17682.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915280, over cnt = 287(0%), over = 358, worst = 4
+PHY-1002 : len = 915312, over cnt = 149(0%), over = 172, worst = 3
+PHY-1002 : len = 916400, over cnt = 66(0%), over = 67, worst = 2
+PHY-1002 : len = 917584, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 917800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.907697s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (111.9%)
+
+PHY-1001 : Congestion index: top1 = 56.10, top5 = 50.39, top10 = 47.44, top15 = 45.35.
+OPT-1001 : End congestion update;  1.223720s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (108.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.751346s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.9%)
+
+OPT-0007 : Start: WNS -3988 TNS -2259553 NUM_FEPS 978
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 740816, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061641s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.4%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 7, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 740954, Over = 0
+PHY-3001 : End incremental legalization;  0.393954s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.2%)
+
+OPT-0007 : Iter 1: improved WNS -3888 TNS -2258287 NUM_FEPS 978 with 32 cells processed and 2246 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 740886, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061020s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.4%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 740890, Over = 0
+PHY-3001 : End incremental legalization;  0.393401s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.3%)
+
+OPT-0007 : Iter 2: improved WNS -3888 TNS -2257363 NUM_FEPS 978 with 10 cells processed and 507 slack improved
+OPT-0007 : Iter 3: improved WNS -3888 TNS -2257363 NUM_FEPS 978 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  3.039279s wall, 3.265625s user + 0.000000s system = 3.265625s CPU (107.4%)
+
+OPT-1001 : Current memory(MB): used = 752, reserve = 744, peak = 758.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.735248s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15907/17682.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 918448, over cnt = 97(0%), over = 128, worst = 4
+PHY-1002 : len = 918688, over cnt = 54(0%), over = 57, worst = 2
+PHY-1002 : len = 919064, over cnt = 25(0%), over = 28, worst = 2
+PHY-1002 : len = 919320, over cnt = 12(0%), over = 14, worst = 2
+PHY-1002 : len = 919512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.805100s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (112.6%)
+
+PHY-1001 : Congestion index: top1 = 56.14, top5 = 50.29, top10 = 47.40, top15 = 45.37.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.735500s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -3954 TNS -2257372 NUM_FEPS 978
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 55.758621
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -3954ps with logic level 5 
+RUN-1001 :       #2 path slack -3954ps with logic level 5 
+RUN-1001 :       #3 path slack -3938ps with logic level 5 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17682 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17682 nets
+OPT-1001 : End physical optimization;  22.146878s wall, 23.781250s user + 0.265625s system = 24.046875s CPU (108.6%)
+
+RUN-1003 : finish command "place" in  64.988785s wall, 89.843750s user + 5.031250s system = 94.875000s CPU (146.0%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 608 MB, peak memory is 758 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.732728s wall, 3.015625s user + 0.000000s system = 3.015625s CPU (174.0%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 609 MB, peak memory is 758 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7016 instances
+RUN-1001 : 3433 mslices, 3432 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17682 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9960 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1191 nets have [6 - 10] pins
+RUN-1001 : 316 nets have [11 - 20] pins
+RUN-1001 : 367 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75197, tnet num: 17504, tinst num: 7014, tnode num: 97908, tedge num: 126206.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.625929s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.9%)
+
+RUN-1004 : used memory is 633 MB, reserved memory is 634 MB, peak memory is 758 MB
+PHY-1001 : 3433 mslices, 3432 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847168, over cnt = 2727(7%), over = 4656, worst = 8
+PHY-1002 : len = 864896, over cnt = 1772(5%), over = 2611, worst = 6
+PHY-1002 : len = 884752, over cnt = 823(2%), over = 1152, worst = 6
+PHY-1002 : len = 903456, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 903768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.916146s wall, 3.890625s user + 0.078125s system = 3.968750s CPU (136.1%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 50.02, top10 = 47.07, top15 = 45.07.
+PHY-1001 : End global routing;  3.252556s wall, 4.203125s user + 0.093750s system = 4.296875s CPU (132.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 729, reserve = 725, peak = 758.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1002, reserve = 997, peak = 1002.
+PHY-1001 : End build detailed router design. 4.092364s wall, 4.046875s user + 0.046875s system = 4.093750s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 262784, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.857693s wall, 4.843750s user + 0.000000s system = 4.843750s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 262840, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.436075s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.3%)
+
+PHY-1001 : Current memory(MB): used = 1038, reserve = 1034, peak = 1038.
+PHY-1001 : End phase 1; 5.307318s wall, 5.296875s user + 0.000000s system = 5.296875s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 38% nets.
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 54% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37434e+06, over cnt = 1762(0%), over = 1778, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1050, peak = 1054.
+PHY-1001 : End initial routed; 24.682358s wall, 53.296875s user + 0.187500s system = 53.484375s CPU (216.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.332   |  -3468.333  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.331671s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1074, reserve = 1071, peak = 1074.
+PHY-1001 : End phase 2; 28.014099s wall, 56.625000s user + 0.187500s system = 56.812500s CPU (202.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 66 pins with SWNS -6.129ns STNS -3457.538ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.499574s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (100.1%)
+
+PHY-1022 : len = 2.37478e+06, over cnt = 1816(0%), over = 1833, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.766401s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33911e+06, over cnt = 592(0%), over = 593, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.110229s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (151.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33632e+06, over cnt = 148(0%), over = 148, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.916905s wall, 1.218750s user + 0.000000s system = 1.218750s CPU (132.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33726e+06, over cnt = 33(0%), over = 33, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.393024s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (135.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33777e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.309565s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (106.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33786e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.289817s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (118.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33792e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.348100s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (103.2%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33792e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.561259s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33791e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.198868s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (110.0%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33793e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.227048s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (103.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.129   |  -3462.818  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.319571s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 573 feed throughs used by 410 nets
+PHY-1001 : End commit to database; 2.322334s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1178, peak = 1178.
+PHY-1001 : End phase 3; 12.191231s wall, 13.812500s user + 0.015625s system = 13.828125s CPU (113.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 40 pins with SWNS -6.000ns STNS -3458.118ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.427759s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.6%)
+
+PHY-1022 : len = 2.33809e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.668805s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (100.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-6.000ns, -3458.118ns, 984}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3377e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.191956s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (105.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.255220s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (104.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.347697s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (98.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.514875s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (97.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33763e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.176615s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (97.3%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.33765e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 6; 0.196410s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (103.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.226   |  -3463.404  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.380689s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1180, reserve = 1180, peak = 1183.
+PHY-1001 : End phase 4; 5.807513s wall, 5.812500s user + 0.015625s system = 5.828125s CPU (100.4%)
+
+PHY-1003 : Routed, final wirelength = 2.33765e+06
+PHY-1001 : Current memory(MB): used = 1185, reserve = 1185, peak = 1185.
+PHY-1001 : End export database. 0.147811s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (105.7%)
+
+PHY-1001 : End detail routing;  55.956486s wall, 86.140625s user + 0.281250s system = 86.421875s CPU (154.4%)
+
+RUN-1003 : finish command "route" in  61.941371s wall, 93.046875s user + 0.406250s system = 93.453125s CPU (150.9%)
+
+RUN-1004 : used memory is 1040 MB, reserved memory is 1036 MB, peak memory is 1185 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10440   out of  19600   53.27%
+#reg                     9429   out of  19600   48.11%
+#le                     12814
+  #lut only              3385   out of  12814   26.42%
+  #reg only              2374   out of  12814   18.53%
+  #lut&reg               7055   out of  12814   55.06%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1820
+#2        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1391
+#3        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1386
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               971
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    136
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          76
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             exdev_ctl_a/reg1_syn_162.f1                        3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg48_syn_235.f0    2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12814  |9419    |1021    |9459    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |542    |471     |23      |440     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |103    |97      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |44     |44      |0       |24      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |771    |368     |96      |579     |0       |0       |
+|    u_ADconfig                |AD_config            |190    |115     |25      |146     |0       |0       |
+|    u_gen_sp                  |gen_sp               |268    |167     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |745    |425     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |135     |25      |126     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |167     |71      |118     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3074   |2350    |303     |2137    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |8      |4       |0       |8       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |166    |85      |14      |136     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |2891   |2252    |289     |1984    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2444   |1953    |253     |1628    |22      |1       |
+|        channelPart           |channel_part_8478    |168    |157     |3       |142     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |46      |0       |1       |
+|        ram_switch            |ram_switch           |1908   |1507    |197     |1216    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |244    |208     |27      |136     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |18     |8       |3       |13      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |17      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |982    |623     |170     |688     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |682    |676     |0       |392     |0       |0       |
+|        read_ram_i            |read_ram             |265    |212     |44      |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |212    |172     |40      |149     |0       |0       |
+|          read_ram_data       |read_ram_data        |52     |39      |4       |31      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |340    |223     |36      |282     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3572   |2883    |340     |2052    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |185    |103     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |3355   |2759    |323     |1872    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2933   |2416    |281     |1529    |22      |0       |
+|        channelPart           |channel_part_8478    |251    |244     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |41      |0       |0       |
+|        ram_switch            |ram_switch           |2239   |1853    |197     |1093    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |258    |230     |27      |121     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |32     |29      |3       |19      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|          insert              |insert               |930    |575     |170     |632     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051   |1048    |0       |340     |0       |0       |
+|        read_ram_i            |read_ram_rev         |337    |238     |72      |203     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |275    |200     |64      |158     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |62     |38      |8       |45      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9898  
+    #2         2       3828  
+    #3         3       1432  
+    #4         4       555   
+    #5        5-10     1252  
+    #6       11-50     588   
+    #7       51-100     31   
+    #8        >500      1    
+  Average     2.96           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.080588s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (173.5%)
+
+RUN-1004 : used memory is 1041 MB, reserved memory is 1038 MB, peak memory is 1185 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75197, tnet num: 17504, tinst num: 7014, tnode num: 97908, tedge num: 126206.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.619241s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (100.4%)
+
+RUN-1004 : used memory is 1045 MB, reserved memory is 1041 MB, peak memory is 1185 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.500490s wall, 1.484375s user + 0.015625s system = 1.500000s CPU (100.0%)
+
+RUN-1004 : used memory is 1090 MB, reserved memory is 1090 MB, peak memory is 1185 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_115806.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_120219.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_120219.log
new file mode 100644
index 0000000..bc2f81b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_120219.log
@@ -0,0 +1,1999 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 12:02:19 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.184878s wall, 2.078125s user + 0.109375s system = 2.187500s CPU (100.1%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17833 instances
+RUN-0007 : 7532 luts, 9084 seqs, 696 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20398 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13452 nets have 2 pins
+RUN-1001 : 5463 nets have [3 - 5] pins
+RUN-1001 : 1067 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17831 instances, 7532 luts, 9084 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5973 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.146835s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (99.5%)
+
+RUN-1004 : used memory is 541 MB, reserved memory is 517 MB, peak memory is 541 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.934501s wall, 1.921875s user + 0.015625s system = 1.937500s CPU (100.2%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.07528e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17831.
+PHY-3001 : Level 1 #clusters 2336.
+PHY-3001 : End clustering;  0.132949s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (129.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.34206e+06, overlap = 478.25
+PHY-3002 : Step(2): len = 1.03976e+06, overlap = 534.469
+PHY-3002 : Step(3): len = 841044, overlap = 621.094
+PHY-3002 : Step(4): len = 711929, overlap = 682.5
+PHY-3002 : Step(5): len = 556822, overlap = 807.438
+PHY-3002 : Step(6): len = 477796, overlap = 909.281
+PHY-3002 : Step(7): len = 406909, overlap = 949.688
+PHY-3002 : Step(8): len = 365407, overlap = 990.625
+PHY-3002 : Step(9): len = 329994, overlap = 1059.88
+PHY-3002 : Step(10): len = 293384, overlap = 1117.53
+PHY-3002 : Step(11): len = 266294, overlap = 1164.62
+PHY-3002 : Step(12): len = 252222, overlap = 1199.88
+PHY-3002 : Step(13): len = 229564, overlap = 1234.44
+PHY-3002 : Step(14): len = 214493, overlap = 1267.16
+PHY-3002 : Step(15): len = 198624, overlap = 1306.41
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.46297e-07
+PHY-3002 : Step(16): len = 199686, overlap = 1290.28
+PHY-3002 : Step(17): len = 223974, overlap = 1233.69
+PHY-3002 : Step(18): len = 230968, overlap = 1190.5
+PHY-3002 : Step(19): len = 233607, overlap = 1182.31
+PHY-3002 : Step(20): len = 231127, overlap = 1165
+PHY-3002 : Step(21): len = 229662, overlap = 1165.88
+PHY-3002 : Step(22): len = 225326, overlap = 1148.53
+PHY-3002 : Step(23): len = 223613, overlap = 1125.41
+PHY-3002 : Step(24): len = 218275, overlap = 1126.25
+PHY-3002 : Step(25): len = 215032, overlap = 1138.78
+PHY-3002 : Step(26): len = 209156, overlap = 1126.78
+PHY-3002 : Step(27): len = 204843, overlap = 1122.41
+PHY-3002 : Step(28): len = 198950, overlap = 1139.78
+PHY-3002 : Step(29): len = 195587, overlap = 1156.72
+PHY-3002 : Step(30): len = 192350, overlap = 1158.03
+PHY-3002 : Step(31): len = 191154, overlap = 1160.31
+PHY-3002 : Step(32): len = 188922, overlap = 1153.84
+PHY-3002 : Step(33): len = 186718, overlap = 1147.28
+PHY-3002 : Step(34): len = 184798, overlap = 1146.5
+PHY-3002 : Step(35): len = 183870, overlap = 1141.97
+PHY-3002 : Step(36): len = 181912, overlap = 1145.28
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.89259e-06
+PHY-3002 : Step(37): len = 185784, overlap = 1125.12
+PHY-3002 : Step(38): len = 198635, overlap = 1055.47
+PHY-3002 : Step(39): len = 206073, overlap = 996.688
+PHY-3002 : Step(40): len = 212064, overlap = 956.875
+PHY-3002 : Step(41): len = 215587, overlap = 928.531
+PHY-3002 : Step(42): len = 215911, overlap = 919.625
+PHY-3002 : Step(43): len = 215206, overlap = 902.875
+PHY-3002 : Step(44): len = 214903, overlap = 899.031
+PHY-3002 : Step(45): len = 214966, overlap = 899.344
+PHY-3002 : Step(46): len = 213102, overlap = 903.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.78519e-06
+PHY-3002 : Step(47): len = 222500, overlap = 879.375
+PHY-3002 : Step(48): len = 239824, overlap = 821.25
+PHY-3002 : Step(49): len = 247632, overlap = 766.938
+PHY-3002 : Step(50): len = 250250, overlap = 717.312
+PHY-3002 : Step(51): len = 250858, overlap = 720.781
+PHY-3002 : Step(52): len = 251337, overlap = 718.625
+PHY-3002 : Step(53): len = 250346, overlap = 719.281
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.57038e-06
+PHY-3002 : Step(54): len = 266497, overlap = 687.438
+PHY-3002 : Step(55): len = 284766, overlap = 618.844
+PHY-3002 : Step(56): len = 290612, overlap = 598.312
+PHY-3002 : Step(57): len = 292779, overlap = 562.969
+PHY-3002 : Step(58): len = 291367, overlap = 555
+PHY-3002 : Step(59): len = 290725, overlap = 546.062
+PHY-3002 : Step(60): len = 289615, overlap = 544.031
+PHY-3002 : Step(61): len = 289732, overlap = 546.625
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.51408e-05
+PHY-3002 : Step(62): len = 311431, overlap = 490.062
+PHY-3002 : Step(63): len = 328168, overlap = 445.906
+PHY-3002 : Step(64): len = 333733, overlap = 411.562
+PHY-3002 : Step(65): len = 337088, overlap = 390.094
+PHY-3002 : Step(66): len = 337200, overlap = 386.688
+PHY-3002 : Step(67): len = 338667, overlap = 383.906
+PHY-3002 : Step(68): len = 337565, overlap = 391.031
+PHY-3002 : Step(69): len = 338510, overlap = 393.688
+PHY-3002 : Step(70): len = 338766, overlap = 395.562
+PHY-3002 : Step(71): len = 338962, overlap = 397.438
+PHY-3002 : Step(72): len = 337619, overlap = 379.688
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.02815e-05
+PHY-3002 : Step(73): len = 358389, overlap = 348.469
+PHY-3002 : Step(74): len = 373279, overlap = 321.438
+PHY-3002 : Step(75): len = 374154, overlap = 287.562
+PHY-3002 : Step(76): len = 376036, overlap = 282.312
+PHY-3002 : Step(77): len = 378003, overlap = 269.906
+PHY-3002 : Step(78): len = 381357, overlap = 256.188
+PHY-3002 : Step(79): len = 378037, overlap = 261.531
+PHY-3002 : Step(80): len = 377895, overlap = 253.75
+PHY-3002 : Step(81): len = 379194, overlap = 249.562
+PHY-3002 : Step(82): len = 381755, overlap = 259.25
+PHY-3002 : Step(83): len = 380590, overlap = 260.938
+PHY-3002 : Step(84): len = 381300, overlap = 246.469
+PHY-3002 : Step(85): len = 381392, overlap = 250.938
+PHY-3002 : Step(86): len = 382724, overlap = 255.375
+PHY-3002 : Step(87): len = 380159, overlap = 259.75
+PHY-3002 : Step(88): len = 381474, overlap = 259.5
+PHY-3002 : Step(89): len = 381443, overlap = 256.438
+PHY-3002 : Step(90): len = 383150, overlap = 249.406
+PHY-3002 : Step(91): len = 381557, overlap = 255
+PHY-3002 : Step(92): len = 381708, overlap = 255.312
+PHY-3002 : Step(93): len = 380201, overlap = 244.406
+PHY-3002 : Step(94): len = 379918, overlap = 249.031
+PHY-3002 : Step(95): len = 379378, overlap = 252.625
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.0563e-05
+PHY-3002 : Step(96): len = 394401, overlap = 233.5
+PHY-3002 : Step(97): len = 405346, overlap = 204.938
+PHY-3002 : Step(98): len = 406774, overlap = 193.406
+PHY-3002 : Step(99): len = 408226, overlap = 193.719
+PHY-3002 : Step(100): len = 410163, overlap = 193.562
+PHY-3002 : Step(101): len = 413635, overlap = 197.125
+PHY-3002 : Step(102): len = 411632, overlap = 196.375
+PHY-3002 : Step(103): len = 412063, overlap = 185.188
+PHY-3002 : Step(104): len = 413243, overlap = 192.312
+PHY-3002 : Step(105): len = 414945, overlap = 185.188
+PHY-3002 : Step(106): len = 412023, overlap = 179.125
+PHY-3002 : Step(107): len = 412289, overlap = 186.031
+PHY-3002 : Step(108): len = 413249, overlap = 179.906
+PHY-3002 : Step(109): len = 415200, overlap = 176.469
+PHY-3002 : Step(110): len = 412147, overlap = 177.812
+PHY-3002 : Step(111): len = 412396, overlap = 178.656
+PHY-3002 : Step(112): len = 412948, overlap = 180.438
+PHY-3002 : Step(113): len = 413896, overlap = 176
+PHY-3002 : Step(114): len = 411642, overlap = 183.219
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000117109
+PHY-3002 : Step(115): len = 424606, overlap = 162.656
+PHY-3002 : Step(116): len = 433290, overlap = 163.062
+PHY-3002 : Step(117): len = 433161, overlap = 164.844
+PHY-3002 : Step(118): len = 434060, overlap = 157.625
+PHY-3002 : Step(119): len = 436988, overlap = 158.906
+PHY-3002 : Step(120): len = 440198, overlap = 159.438
+PHY-3002 : Step(121): len = 438514, overlap = 156.125
+PHY-3002 : Step(122): len = 439372, overlap = 168.781
+PHY-3002 : Step(123): len = 442030, overlap = 171.906
+PHY-3002 : Step(124): len = 443718, overlap = 171.219
+PHY-3002 : Step(125): len = 441411, overlap = 172.719
+PHY-3002 : Step(126): len = 441647, overlap = 172.562
+PHY-3002 : Step(127): len = 442833, overlap = 175.031
+PHY-3002 : Step(128): len = 444153, overlap = 186.281
+PHY-3002 : Step(129): len = 441868, overlap = 176.312
+PHY-3002 : Step(130): len = 441510, overlap = 181.469
+PHY-3002 : Step(131): len = 442613, overlap = 180.094
+PHY-3002 : Step(132): len = 443792, overlap = 168.219
+PHY-3002 : Step(133): len = 441703, overlap = 171
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000220907
+PHY-3002 : Step(134): len = 450612, overlap = 162.625
+PHY-3002 : Step(135): len = 457561, overlap = 166.406
+PHY-3002 : Step(136): len = 457913, overlap = 161.875
+PHY-3002 : Step(137): len = 458814, overlap = 154.031
+PHY-3002 : Step(138): len = 462082, overlap = 145.906
+PHY-3002 : Step(139): len = 464189, overlap = 137.125
+PHY-3002 : Step(140): len = 462771, overlap = 143.062
+PHY-3002 : Step(141): len = 463112, overlap = 141.531
+PHY-3002 : Step(142): len = 466165, overlap = 125.125
+PHY-3002 : Step(143): len = 468540, overlap = 123.875
+PHY-3002 : Step(144): len = 466144, overlap = 124.375
+PHY-3002 : Step(145): len = 465953, overlap = 126.469
+PHY-3002 : Step(146): len = 467174, overlap = 122.781
+PHY-3002 : Step(147): len = 468001, overlap = 122.969
+PHY-3002 : Step(148): len = 466754, overlap = 121.438
+PHY-3002 : Step(149): len = 466617, overlap = 119.594
+PHY-3002 : Step(150): len = 467420, overlap = 121.281
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000441815
+PHY-3002 : Step(151): len = 473295, overlap = 118.5
+PHY-3002 : Step(152): len = 481360, overlap = 123.125
+PHY-3002 : Step(153): len = 486416, overlap = 121.906
+PHY-3002 : Step(154): len = 488078, overlap = 115.812
+PHY-3002 : Step(155): len = 488869, overlap = 121.906
+PHY-3002 : Step(156): len = 489870, overlap = 118.781
+PHY-3002 : Step(157): len = 489830, overlap = 120.531
+PHY-3002 : Step(158): len = 489986, overlap = 122.031
+PHY-3002 : Step(159): len = 489706, overlap = 113.312
+PHY-3002 : Step(160): len = 489555, overlap = 105.938
+PHY-3002 : Step(161): len = 490104, overlap = 101.281
+PHY-3002 : Step(162): len = 491500, overlap = 104.844
+PHY-3002 : Step(163): len = 492932, overlap = 100.094
+PHY-3002 : Step(164): len = 493951, overlap = 97.875
+PHY-3002 : Step(165): len = 494337, overlap = 98.25
+PHY-3002 : Step(166): len = 495377, overlap = 98.7188
+PHY-3002 : Step(167): len = 495218, overlap = 96.625
+PHY-3002 : Step(168): len = 495815, overlap = 100
+PHY-3002 : Step(169): len = 495138, overlap = 103.844
+PHY-3002 : Step(170): len = 494697, overlap = 97.7812
+PHY-3002 : Step(171): len = 494348, overlap = 103.719
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000833566
+PHY-3002 : Step(172): len = 496802, overlap = 96.125
+PHY-3002 : Step(173): len = 500170, overlap = 94.3438
+PHY-3002 : Step(174): len = 501536, overlap = 93.8125
+PHY-3002 : Step(175): len = 502062, overlap = 93.5625
+PHY-3002 : Step(176): len = 502293, overlap = 86.7812
+PHY-3002 : Step(177): len = 502359, overlap = 88.0312
+PHY-3002 : Step(178): len = 502499, overlap = 90.0625
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014675s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (106.5%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 670088, over cnt = 1369(3%), over = 5856, worst = 25
+PHY-1001 : End global iterations;  0.750742s wall, 1.093750s user + 0.031250s system = 1.125000s CPU (149.9%)
+
+PHY-1001 : Congestion index: top1 = 74.35, top5 = 55.08, top10 = 47.06, top15 = 42.50.
+PHY-3001 : End congestion estimation;  0.964252s wall, 1.296875s user + 0.046875s system = 1.343750s CPU (139.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.859150s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.87269e-05
+PHY-3002 : Step(179): len = 611094, overlap = 36.7812
+PHY-3002 : Step(180): len = 629498, overlap = 29.875
+PHY-3002 : Step(181): len = 617273, overlap = 25.8438
+PHY-3002 : Step(182): len = 612122, overlap = 29.4062
+PHY-3002 : Step(183): len = 603530, overlap = 27.4062
+PHY-3002 : Step(184): len = 600128, overlap = 31.7188
+PHY-3002 : Step(185): len = 598912, overlap = 35.125
+PHY-3002 : Step(186): len = 591598, overlap = 39.6875
+PHY-3002 : Step(187): len = 588955, overlap = 40.75
+PHY-3002 : Step(188): len = 587415, overlap = 42.9062
+PHY-3002 : Step(189): len = 584589, overlap = 43.9688
+PHY-3002 : Step(190): len = 583403, overlap = 40.2812
+PHY-3002 : Step(191): len = 582336, overlap = 41.875
+PHY-3002 : Step(192): len = 579818, overlap = 40.4062
+PHY-3002 : Step(193): len = 579688, overlap = 40.4688
+PHY-3002 : Step(194): len = 578791, overlap = 39.6562
+PHY-3002 : Step(195): len = 578211, overlap = 41.8438
+PHY-3002 : Step(196): len = 576508, overlap = 42.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000177454
+PHY-3002 : Step(197): len = 578960, overlap = 42.3125
+PHY-3002 : Step(198): len = 582750, overlap = 40.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00033251
+PHY-3002 : Step(199): len = 589819, overlap = 40.0312
+PHY-3002 : Step(200): len = 599950, overlap = 39.5625
+PHY-3002 : Step(201): len = 610813, overlap = 40.7812
+PHY-3002 : Step(202): len = 609601, overlap = 38.375
+PHY-3002 : Step(203): len = 609605, overlap = 42.125
+PHY-3002 : Step(204): len = 606844, overlap = 42.1875
+PHY-3002 : Step(205): len = 608246, overlap = 40.5312
+PHY-3002 : Step(206): len = 610102, overlap = 42.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 81/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700840, over cnt = 2513(7%), over = 10808, worst = 39
+PHY-1001 : End global iterations;  1.622494s wall, 2.171875s user + 0.046875s system = 2.218750s CPU (136.7%)
+
+PHY-1001 : Congestion index: top1 = 78.38, top5 = 62.45, top10 = 54.94, top15 = 50.21.
+PHY-3001 : End congestion estimation;  1.897321s wall, 2.437500s user + 0.062500s system = 2.500000s CPU (131.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.923647s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.76412e-05
+PHY-3002 : Step(207): len = 607916, overlap = 243.156
+PHY-3002 : Step(208): len = 614129, overlap = 201.344
+PHY-3002 : Step(209): len = 604854, overlap = 190.406
+PHY-3002 : Step(210): len = 600997, overlap = 164.438
+PHY-3002 : Step(211): len = 599911, overlap = 150.625
+PHY-3002 : Step(212): len = 592757, overlap = 151.875
+PHY-3002 : Step(213): len = 589373, overlap = 147.062
+PHY-3002 : Step(214): len = 586562, overlap = 148.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000195282
+PHY-3002 : Step(215): len = 586411, overlap = 142.344
+PHY-3002 : Step(216): len = 589367, overlap = 136.5
+PHY-3002 : Step(217): len = 593452, overlap = 139
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000390565
+PHY-3002 : Step(218): len = 597222, overlap = 136.312
+PHY-3002 : Step(219): len = 605582, overlap = 129.281
+PHY-3002 : Step(220): len = 610957, overlap = 126.594
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.414674s wall, 1.390625s user + 0.015625s system = 1.406250s CPU (99.4%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 564 MB, peak memory is 720 MB
+OPT-1001 : Total overflow 483.00 peak overflow 4.50
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 927/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709096, over cnt = 2790(7%), over = 9868, worst = 32
+PHY-1001 : End global iterations;  1.129049s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (141.2%)
+
+PHY-1001 : Congestion index: top1 = 65.97, top5 = 55.56, top10 = 50.03, top15 = 46.28.
+PHY-1001 : End incremental global routing;  1.450504s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (132.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.905756s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.1%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17699 has valid locations, 336 needs to be replaced
+PHY-3001 : design contains 18120 instances, 7611 luts, 9294 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6106 pins
+PHY-3001 : Found 1235 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 635943
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16069/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 726368, over cnt = 2806(7%), over = 10011, worst = 32
+PHY-1001 : End global iterations;  0.235703s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (145.8%)
+
+PHY-1001 : Congestion index: top1 = 66.06, top5 = 56.06, top10 = 50.50, top15 = 46.76.
+PHY-3001 : End congestion estimation;  0.489615s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (124.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86724, tnet num: 20509, tinst num: 18120, tnode num: 117570, tedge num: 139118.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.456997s wall, 1.390625s user + 0.062500s system = 1.453125s CPU (99.7%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 623 MB, peak memory is 722 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.406802s wall, 2.328125s user + 0.078125s system = 2.406250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(221): len = 634898, overlap = 0.0625
+PHY-3002 : Step(222): len = 634748, overlap = 0.0625
+PHY-3002 : Step(223): len = 634259, overlap = 0.0625
+PHY-3002 : Step(224): len = 634212, overlap = 0.0625
+PHY-3002 : Step(225): len = 634443, overlap = 0.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16115/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720960, over cnt = 2817(8%), over = 10052, worst = 32
+PHY-1001 : End global iterations;  0.219844s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (113.7%)
+
+PHY-1001 : Congestion index: top1 = 66.66, top5 = 56.13, top10 = 50.65, top15 = 46.95.
+PHY-3001 : End congestion estimation;  0.465911s wall, 0.468750s user + 0.031250s system = 0.500000s CPU (107.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.950547s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000368783
+PHY-3002 : Step(226): len = 634901, overlap = 128.969
+PHY-3002 : Step(227): len = 635133, overlap = 129.406
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000737566
+PHY-3002 : Step(228): len = 635100, overlap = 129
+PHY-3002 : Step(229): len = 635452, overlap = 129.156
+PHY-3001 : Final: Len = 635452, Over = 129.156
+PHY-3001 : End incremental placement;  5.005115s wall, 5.062500s user + 0.250000s system = 5.312500s CPU (106.1%)
+
+OPT-1001 : Total overflow 488.25 peak overflow 4.50
+OPT-1001 : End high-fanout net optimization;  7.916944s wall, 8.421875s user + 0.281250s system = 8.703125s CPU (109.9%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16129/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724912, over cnt = 2776(7%), over = 9260, worst = 32
+PHY-1002 : len = 771056, over cnt = 1914(5%), over = 4806, worst = 20
+PHY-1002 : len = 811472, over cnt = 854(2%), over = 1834, worst = 20
+PHY-1002 : len = 836944, over cnt = 75(0%), over = 88, worst = 5
+PHY-1002 : len = 838664, over cnt = 4(0%), over = 7, worst = 4
+PHY-1001 : End global iterations;  1.866909s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (135.6%)
+
+PHY-1001 : Congestion index: top1 = 58.21, top5 = 50.55, top10 = 46.61, top15 = 44.11.
+OPT-1001 : End congestion update;  2.120223s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (131.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.803024s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (101.2%)
+
+OPT-0007 : Start: WNS -5085 TNS -2609047 NUM_FEPS 1053
+OPT-0007 : Iter 1: improved WNS -4519 TNS -2534293 NUM_FEPS 1053 with 70 cells processed and 1666 slack improved
+OPT-0007 : Iter 2: improved WNS -4519 TNS -2532645 NUM_FEPS 1053 with 93 cells processed and 1400 slack improved
+OPT-0007 : Iter 3: improved WNS -4519 TNS -2532045 NUM_FEPS 1053 with 38 cells processed and 700 slack improved
+OPT-0007 : Iter 4: improved WNS -4469 TNS -2533115 NUM_FEPS 1053 with 11 cells processed and 150 slack improved
+OPT-0007 : Iter 5: improved WNS -4469 TNS -2531639 NUM_FEPS 1053 with 23 cells processed and 400 slack improved
+OPT-0007 : Iter 6: improved WNS -4469 TNS -2531539 NUM_FEPS 1053 with 8 cells processed and 200 slack improved
+OPT-0007 : Iter 7: improved WNS -4269 TNS -2466901 NUM_FEPS 1053 with 1 cells processed and 484 slack improved
+OPT-0007 : Iter 8: improved WNS -4269 TNS -2465323 NUM_FEPS 1053 with 1 cells processed and 250 slack improved
+OPT-1001 : End bottleneck based optimization;  3.806495s wall, 4.453125s user + 0.015625s system = 4.468750s CPU (117.4%)
+
+OPT-1001 : Current memory(MB): used = 705, reserve = 695, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16289/20689.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842512, over cnt = 169(0%), over = 315, worst = 10
+PHY-1002 : len = 843544, over cnt = 100(0%), over = 127, worst = 4
+PHY-1002 : len = 844216, over cnt = 48(0%), over = 55, worst = 3
+PHY-1002 : len = 844824, over cnt = 20(0%), over = 22, worst = 2
+PHY-1002 : len = 845256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.777897s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (116.5%)
+
+PHY-1001 : Congestion index: top1 = 57.97, top5 = 50.51, top10 = 46.63, top15 = 44.17.
+OPT-1001 : End congestion update;  1.039434s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (112.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20511 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.805737s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (98.9%)
+
+OPT-0007 : Start: WNS -4269 TNS -2465323 NUM_FEPS 1053
+OPT-0007 : Iter 1: improved WNS -4269 TNS -2461823 NUM_FEPS 1053 with 53 cells processed and 3650 slack improved
+OPT-0007 : Iter 2: improved WNS -4269 TNS -2461823 NUM_FEPS 1053 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.987693s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (106.9%)
+
+OPT-1001 : Current memory(MB): used = 700, reserve = 688, peak = 743.
+OPT-1001 : End physical optimization;  15.429895s wall, 16.765625s user + 0.343750s system = 17.109375s CPU (110.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7611 LUT to BLE ...
+SYN-4008 : Packed 7611 LUT and 3144 SEQ to BLE.
+SYN-4003 : Packing 6152 remaining SEQ's ...
+SYN-4005 : Packed 3681 SEQ with LUT/SLICE
+SYN-4006 : 1091 single LUT's are left
+SYN-4006 : 2471 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10082/13895 primitive instances ...
+PHY-3001 : End packing;  1.644192s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.8%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6984 instances
+RUN-1001 : 3418 mslices, 3418 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17664 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 5811 nets have [3 - 5] pins
+RUN-1001 : 1182 nets have [6 - 10] pins
+RUN-1001 : 302 nets have [11 - 20] pins
+RUN-1001 : 358 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6982 instances, 6836 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3611 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 645206, Over = 319
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7494/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 796520, over cnt = 1812(5%), over = 3089, worst = 9
+PHY-1002 : len = 803552, over cnt = 1296(3%), over = 1991, worst = 9
+PHY-1002 : len = 816024, over cnt = 628(1%), over = 965, worst = 7
+PHY-1002 : len = 825936, over cnt = 268(0%), over = 396, worst = 7
+PHY-1002 : len = 831400, over cnt = 39(0%), over = 58, worst = 4
+PHY-1001 : End global iterations;  1.552717s wall, 2.125000s user + 0.000000s system = 2.125000s CPU (136.9%)
+
+PHY-1001 : Congestion index: top1 = 58.36, top5 = 51.00, top10 = 46.93, top15 = 44.43.
+PHY-3001 : End congestion estimation;  1.955039s wall, 2.531250s user + 0.000000s system = 2.531250s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74904, tnet num: 17486, tinst num: 6982, tnode num: 97547, tedge num: 125845.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.647556s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.6%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 618 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.520316s wall, 2.500000s user + 0.015625s system = 2.515625s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 3.9602e-05
+PHY-3002 : Step(230): len = 631584, overlap = 332.25
+PHY-3002 : Step(231): len = 623648, overlap = 336.5
+PHY-3002 : Step(232): len = 618967, overlap = 344
+PHY-3002 : Step(233): len = 615592, overlap = 337.75
+PHY-3002 : Step(234): len = 613049, overlap = 342.5
+PHY-3002 : Step(235): len = 610060, overlap = 344.75
+PHY-3002 : Step(236): len = 607237, overlap = 346
+PHY-3002 : Step(237): len = 604218, overlap = 350
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 7.9204e-05
+PHY-3002 : Step(238): len = 608379, overlap = 349
+PHY-3002 : Step(239): len = 614345, overlap = 336.75
+PHY-3002 : Step(240): len = 614925, overlap = 333
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000158408
+PHY-3002 : Step(241): len = 625426, overlap = 312
+PHY-3002 : Step(242): len = 631858, overlap = 307.25
+PHY-3002 : Step(243): len = 629581, overlap = 304
+PHY-3002 : Step(244): len = 628797, overlap = 304
+PHY-3002 : Step(245): len = 628888, overlap = 302
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.345147s wall, 0.312500s user + 0.468750s system = 0.781250s CPU (226.4%)
+
+PHY-3001 : Trial Legalized: Len = 742267
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 543/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859264, over cnt = 2760(7%), over = 4945, worst = 9
+PHY-1002 : len = 879648, over cnt = 1784(5%), over = 2628, worst = 8
+PHY-1002 : len = 899120, over cnt = 840(2%), over = 1167, worst = 5
+PHY-1002 : len = 905776, over cnt = 562(1%), over = 741, worst = 5
+PHY-1002 : len = 920296, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.424400s wall, 3.562500s user + 0.000000s system = 3.562500s CPU (146.9%)
+
+PHY-1001 : Congestion index: top1 = 57.13, top5 = 51.95, top10 = 48.89, top15 = 46.76.
+PHY-3001 : End congestion estimation;  2.875170s wall, 4.015625s user + 0.000000s system = 4.015625s CPU (139.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.870123s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000181197
+PHY-3002 : Step(246): len = 696735, overlap = 92.25
+PHY-3002 : Step(247): len = 676996, overlap = 144.25
+PHY-3002 : Step(248): len = 663105, overlap = 191.5
+PHY-3002 : Step(249): len = 656074, overlap = 219.25
+PHY-3002 : Step(250): len = 652221, overlap = 225.5
+PHY-3002 : Step(251): len = 650028, overlap = 230.25
+PHY-3002 : Step(252): len = 648434, overlap = 236.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000362394
+PHY-3002 : Step(253): len = 654148, overlap = 231.5
+PHY-3002 : Step(254): len = 660001, overlap = 234.25
+PHY-3002 : Step(255): len = 662805, overlap = 239
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000724789
+PHY-3002 : Step(256): len = 665647, overlap = 235.5
+PHY-3002 : Step(257): len = 675016, overlap = 225.25
+PHY-3002 : Step(258): len = 681280, overlap = 229.75
+PHY-3002 : Step(259): len = 680141, overlap = 227.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.039067s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (80.0%)
+
+PHY-3001 : Legalized: Len = 724353, Over = 0
+PHY-3001 : Spreading special nets. 566 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.116098s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (94.2%)
+
+PHY-3001 : 829 instances has been re-located, deltaX = 290, deltaY = 488, maxDist = 4.
+PHY-3001 : Final: Len = 736209, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74904, tnet num: 17486, tinst num: 6985, tnode num: 97547, tedge num: 125845.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.911453s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (100.5%)
+
+RUN-1004 : used memory is 638 MB, reserved memory is 649 MB, peak memory is 743 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3013/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862248, over cnt = 2584(7%), over = 4345, worst = 7
+PHY-1002 : len = 877656, over cnt = 1607(4%), over = 2376, worst = 6
+PHY-1002 : len = 900920, over cnt = 397(1%), over = 552, worst = 6
+PHY-1002 : len = 908152, over cnt = 104(0%), over = 149, worst = 4
+PHY-1002 : len = 911608, over cnt = 16(0%), over = 18, worst = 3
+PHY-1001 : End global iterations;  2.080950s wall, 3.031250s user + 0.062500s system = 3.093750s CPU (148.7%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.44, top10 = 47.41, top15 = 45.31.
+PHY-1001 : End incremental global routing;  2.430808s wall, 3.390625s user + 0.062500s system = 3.453125s CPU (142.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.875409s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.0%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 739843
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16050/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915144, over cnt = 69(0%), over = 77, worst = 3
+PHY-1002 : len = 915248, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 915496, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 915536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.571335s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (112.1%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.45, top10 = 47.44, top15 = 45.36.
+PHY-3001 : End congestion estimation;  0.877477s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (106.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75067, tnet num: 17503, tinst num: 7002, tnode num: 97741, tedge num: 126046.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.873455s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.1%)
+
+RUN-1004 : used memory is 667 MB, reserved memory is 658 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.769858s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(260): len = 738594, overlap = 0
+PHY-3002 : Step(261): len = 738218, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16041/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913312, over cnt = 54(0%), over = 63, worst = 3
+PHY-1002 : len = 913488, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 913672, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 913792, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 913840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.731177s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (109.0%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.47, top10 = 47.43, top15 = 45.34.
+PHY-3001 : End congestion estimation;  1.096795s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (106.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.897286s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000332748
+PHY-3002 : Step(262): len = 738049, overlap = 1.25
+PHY-3002 : Step(263): len = 738003, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005726s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 738084, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.065931s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.8%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 738104, Over = 0
+PHY-3001 : End incremental placement;  6.134312s wall, 6.375000s user + 0.062500s system = 6.437500s CPU (104.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.927609s wall, 11.109375s user + 0.125000s system = 11.234375s CPU (113.2%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 743, peak = 752.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16037/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913704, over cnt = 34(0%), over = 43, worst = 4
+PHY-1002 : len = 913840, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 913928, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 913992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.565004s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (99.6%)
+
+PHY-1001 : Congestion index: top1 = 56.08, top5 = 50.44, top10 = 47.42, top15 = 45.33.
+OPT-1001 : End congestion update;  0.936180s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (100.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.727641s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.9%)
+
+OPT-0007 : Start: WNS -4188 TNS -2273902 NUM_FEPS 978
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6914 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 738352, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061260s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.0%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 7, deltaY = 18, maxDist = 2.
+PHY-3001 : Final: Len = 738926, Over = 0
+PHY-3001 : End incremental legalization;  0.397776s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (102.1%)
+
+OPT-0007 : Iter 1: improved WNS -3888 TNS -2268531 NUM_FEPS 978 with 40 cells processed and 4886 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6914 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 739072, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059687s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.7%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 6, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 739464, Over = 0
+PHY-3001 : End incremental legalization;  0.386648s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.0%)
+
+OPT-0007 : Iter 2: improved WNS -3988 TNS -2257868 NUM_FEPS 978 with 30 cells processed and 2801 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 739802, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061850s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.1%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 739900, Over = 0
+PHY-3001 : End incremental legalization;  0.428749s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.4%)
+
+OPT-0007 : Iter 3: improved WNS -3988 TNS -2256151 NUM_FEPS 978 with 12 cells processed and 1350 slack improved
+OPT-1001 : End bottleneck based optimization;  3.626477s wall, 3.734375s user + 0.000000s system = 3.734375s CPU (103.0%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 743, peak = 752.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15737/17682.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915280, over cnt = 287(0%), over = 358, worst = 4
+PHY-1002 : len = 915312, over cnt = 149(0%), over = 172, worst = 3
+PHY-1002 : len = 916400, over cnt = 66(0%), over = 67, worst = 2
+PHY-1002 : len = 917584, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 917800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.886681s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (111.0%)
+
+PHY-1001 : Congestion index: top1 = 56.10, top5 = 50.39, top10 = 47.44, top15 = 45.35.
+OPT-1001 : End congestion update;  1.199062s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (106.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.739793s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.4%)
+
+OPT-0007 : Start: WNS -3988 TNS -2259553 NUM_FEPS 978
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 740816, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061603s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.5%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 7, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 740954, Over = 0
+PHY-3001 : End incremental legalization;  0.383629s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.8%)
+
+OPT-0007 : Iter 1: improved WNS -3888 TNS -2258287 NUM_FEPS 978 with 32 cells processed and 2246 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 740886, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060376s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.5%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 740890, Over = 0
+PHY-3001 : End incremental legalization;  0.380651s wall, 0.406250s user + 0.031250s system = 0.437500s CPU (114.9%)
+
+OPT-0007 : Iter 2: improved WNS -3888 TNS -2257363 NUM_FEPS 978 with 10 cells processed and 507 slack improved
+OPT-0007 : Iter 3: improved WNS -3888 TNS -2257363 NUM_FEPS 978 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.975506s wall, 3.078125s user + 0.046875s system = 3.125000s CPU (105.0%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 743, peak = 752.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.737438s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15907/17682.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 918448, over cnt = 97(0%), over = 128, worst = 4
+PHY-1002 : len = 918688, over cnt = 54(0%), over = 57, worst = 2
+PHY-1002 : len = 919064, over cnt = 25(0%), over = 28, worst = 2
+PHY-1002 : len = 919320, over cnt = 12(0%), over = 14, worst = 2
+PHY-1002 : len = 919512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.793041s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (104.4%)
+
+PHY-1001 : Congestion index: top1 = 56.14, top5 = 50.29, top10 = 47.40, top15 = 45.37.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.876284s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (83.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -3954 TNS -2257372 NUM_FEPS 978
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 55.758621
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -3954ps with logic level 5 
+RUN-1001 :       #2 path slack -3954ps with logic level 5 
+RUN-1001 :       #3 path slack -3938ps with logic level 5 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17682 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17682 nets
+OPT-1001 : End physical optimization;  21.554149s wall, 22.781250s user + 0.234375s system = 23.015625s CPU (106.8%)
+
+RUN-1003 : finish command "place" in  63.851367s wall, 88.593750s user + 5.546875s system = 94.140625s CPU (147.4%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 606 MB, peak memory is 752 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.690037s wall, 2.968750s user + 0.000000s system = 2.968750s CPU (175.7%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 607 MB, peak memory is 752 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7016 instances
+RUN-1001 : 3433 mslices, 3432 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17682 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9960 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1191 nets have [6 - 10] pins
+RUN-1001 : 316 nets have [11 - 20] pins
+RUN-1001 : 367 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75197, tnet num: 17504, tinst num: 7014, tnode num: 97908, tedge num: 126206.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.623118s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (100.1%)
+
+RUN-1004 : used memory is 637 MB, reserved memory is 634 MB, peak memory is 752 MB
+PHY-1001 : 3433 mslices, 3432 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847168, over cnt = 2727(7%), over = 4656, worst = 8
+PHY-1002 : len = 864896, over cnt = 1772(5%), over = 2611, worst = 6
+PHY-1002 : len = 884752, over cnt = 823(2%), over = 1152, worst = 6
+PHY-1002 : len = 903456, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 903768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.006904s wall, 3.890625s user + 0.031250s system = 3.921875s CPU (130.4%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 50.02, top10 = 47.07, top15 = 45.07.
+PHY-1001 : End global routing;  3.331690s wall, 4.171875s user + 0.062500s system = 4.234375s CPU (127.1%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 728, reserve = 725, peak = 752.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1000, reserve = 998, peak = 1000.
+PHY-1001 : End build detailed router design. 3.987507s wall, 3.984375s user + 0.015625s system = 4.000000s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 262784, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 4.705721s wall, 4.703125s user + 0.000000s system = 4.703125s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 262840, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.428952s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.4%)
+
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1034, peak = 1036.
+PHY-1001 : End phase 1; 5.148098s wall, 5.140625s user + 0.000000s system = 5.140625s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 38% nets.
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 54% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37434e+06, over cnt = 1762(0%), over = 1778, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1048, peak = 1052.
+PHY-1001 : End initial routed; 23.366014s wall, 50.921875s user + 0.296875s system = 51.218750s CPU (219.2%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.332   |  -3468.333  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.286161s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1063, reserve = 1059, peak = 1063.
+PHY-1001 : End phase 2; 26.652240s wall, 54.203125s user + 0.296875s system = 54.500000s CPU (204.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 66 pins with SWNS -6.129ns STNS -3457.538ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.470426s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.6%)
+
+PHY-1022 : len = 2.37478e+06, over cnt = 1816(0%), over = 1833, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.732039s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.3%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33911e+06, over cnt = 592(0%), over = 593, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.062149s wall, 3.109375s user + 0.000000s system = 3.109375s CPU (150.8%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33632e+06, over cnt = 148(0%), over = 148, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.869015s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (131.3%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33726e+06, over cnt = 33(0%), over = 33, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.397491s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (129.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33777e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.302371s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (113.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33786e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.286075s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (120.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33792e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.333499s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (103.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33792e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.469150s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33791e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.179130s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (104.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33793e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.205558s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (98.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.129   |  -3462.818  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.312861s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 573 feed throughs used by 410 nets
+PHY-1001 : End commit to database; 2.256355s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1169, peak = 1169.
+PHY-1001 : End phase 3; 11.834197s wall, 13.375000s user + 0.000000s system = 13.375000s CPU (113.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 40 pins with SWNS -6.000ns STNS -3458.118ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.419192s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.6%)
+
+PHY-1022 : len = 2.33809e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.654339s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (100.3%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-6.000ns, -3458.118ns, 984}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3377e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.194343s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (112.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.252686s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (105.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.332119s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (98.8%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.461387s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (101.6%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33763e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.176209s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (106.4%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.33765e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 6; 0.191430s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (97.9%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.226   |  -3463.404  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.330720s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1179, peak = 1178.
+PHY-1001 : End phase 4; 5.664646s wall, 5.703125s user + 0.000000s system = 5.703125s CPU (100.7%)
+
+PHY-1003 : Routed, final wirelength = 2.33765e+06
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1179, peak = 1178.
+PHY-1001 : End export database. 0.150722s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (103.7%)
+
+PHY-1001 : End detail routing;  53.830361s wall, 82.937500s user + 0.312500s system = 83.250000s CPU (154.7%)
+
+RUN-1003 : finish command "route" in  59.865218s wall, 89.796875s user + 0.390625s system = 90.187500s CPU (150.7%)
+
+RUN-1004 : used memory is 1101 MB, reserved memory is 1105 MB, peak memory is 1178 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10440   out of  19600   53.27%
+#reg                     9429   out of  19600   48.11%
+#le                     12814
+  #lut only              3385   out of  12814   26.42%
+  #reg only              2374   out of  12814   18.53%
+  #lut&reg               7055   out of  12814   55.06%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1820
+#2        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1391
+#3        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1386
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               971
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    136
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          76
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             exdev_ctl_a/reg1_syn_162.f1                        3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg48_syn_235.f0    2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12814  |9419    |1021    |9459    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |542    |471     |23      |440     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |103    |97      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |44     |44      |0       |24      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |771    |368     |96      |579     |0       |0       |
+|    u_ADconfig                |AD_config            |190    |115     |25      |146     |0       |0       |
+|    u_gen_sp                  |gen_sp               |268    |167     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |745    |425     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |135     |25      |126     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |167     |71      |118     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3074   |2350    |303     |2137    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |8      |4       |0       |8       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |166    |85      |14      |136     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |2891   |2252    |289     |1984    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2444   |1953    |253     |1628    |22      |1       |
+|        channelPart           |channel_part_8478    |168    |157     |3       |142     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |46      |0       |1       |
+|        ram_switch            |ram_switch           |1908   |1507    |197     |1216    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |244    |208     |27      |136     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |18     |8       |3       |13      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |17      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |982    |623     |170     |688     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |682    |676     |0       |392     |0       |0       |
+|        read_ram_i            |read_ram             |265    |212     |44      |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |212    |172     |40      |149     |0       |0       |
+|          read_ram_data       |read_ram_data        |52     |39      |4       |31      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |340    |223     |36      |282     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3572   |2883    |340     |2052    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |185    |103     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |3355   |2759    |323     |1872    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2933   |2416    |281     |1529    |22      |0       |
+|        channelPart           |channel_part_8478    |251    |244     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |41      |0       |0       |
+|        ram_switch            |ram_switch           |2239   |1853    |197     |1093    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |258    |230     |27      |121     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |32     |29      |3       |19      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|          insert              |insert               |930    |575     |170     |632     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051   |1048    |0       |340     |0       |0       |
+|        read_ram_i            |read_ram_rev         |337    |238     |72      |203     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |275    |200     |64      |158     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |62     |38      |8       |45      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9898  
+    #2         2       3828  
+    #3         3       1432  
+    #4         4       555   
+    #5        5-10     1252  
+    #6       11-50     588   
+    #7       51-100     31   
+    #8        >500      1    
+  Average     2.96           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.081704s wall, 3.593750s user + 0.000000s system = 3.593750s CPU (172.6%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1106 MB, peak memory is 1178 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75197, tnet num: 17504, tinst num: 7014, tnode num: 97908, tedge num: 126206.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.615351s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.6%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1110 MB, peak memory is 1178 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.470742s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (100.9%)
+
+RUN-1004 : used memory is 1112 MB, reserved memory is 1115 MB, peak memory is 1178 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7014
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17682, pip num: 175905
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 573
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 487263 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.071765s wall, 69.812500s user + 0.046875s system = 69.859375s CPU (693.6%)
+
+RUN-1004 : used memory is 1276 MB, reserved memory is 1271 MB, peak memory is 1391 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_120219.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_133926.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_133926.log
new file mode 100644
index 0000000..2440c91
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_133926.log
@@ -0,0 +1,1999 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:39:26 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.205444s wall, 2.140625s user + 0.062500s system = 2.203125s CPU (99.9%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17833 instances
+RUN-0007 : 7532 luts, 9084 seqs, 696 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20398 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13452 nets have 2 pins
+RUN-1001 : 5463 nets have [3 - 5] pins
+RUN-1001 : 1067 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17831 instances, 7532 luts, 9084 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5973 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.176279s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (99.6%)
+
+RUN-1004 : used memory is 541 MB, reserved memory is 517 MB, peak memory is 541 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.968910s wall, 1.968750s user + 0.000000s system = 1.968750s CPU (100.0%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.07528e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17831.
+PHY-3001 : Level 1 #clusters 2336.
+PHY-3001 : End clustering;  0.124280s wall, 0.171875s user + 0.015625s system = 0.187500s CPU (150.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.34206e+06, overlap = 478.25
+PHY-3002 : Step(2): len = 1.03976e+06, overlap = 534.469
+PHY-3002 : Step(3): len = 841044, overlap = 621.094
+PHY-3002 : Step(4): len = 711929, overlap = 682.5
+PHY-3002 : Step(5): len = 556822, overlap = 807.438
+PHY-3002 : Step(6): len = 477796, overlap = 909.281
+PHY-3002 : Step(7): len = 406909, overlap = 949.688
+PHY-3002 : Step(8): len = 365407, overlap = 990.625
+PHY-3002 : Step(9): len = 329994, overlap = 1059.88
+PHY-3002 : Step(10): len = 293384, overlap = 1117.53
+PHY-3002 : Step(11): len = 266294, overlap = 1164.62
+PHY-3002 : Step(12): len = 252222, overlap = 1199.88
+PHY-3002 : Step(13): len = 229564, overlap = 1234.44
+PHY-3002 : Step(14): len = 214493, overlap = 1267.16
+PHY-3002 : Step(15): len = 198624, overlap = 1306.41
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.46297e-07
+PHY-3002 : Step(16): len = 199686, overlap = 1290.28
+PHY-3002 : Step(17): len = 223974, overlap = 1233.69
+PHY-3002 : Step(18): len = 230968, overlap = 1190.5
+PHY-3002 : Step(19): len = 233607, overlap = 1182.31
+PHY-3002 : Step(20): len = 231127, overlap = 1165
+PHY-3002 : Step(21): len = 229662, overlap = 1165.88
+PHY-3002 : Step(22): len = 225326, overlap = 1148.53
+PHY-3002 : Step(23): len = 223613, overlap = 1125.41
+PHY-3002 : Step(24): len = 218275, overlap = 1126.25
+PHY-3002 : Step(25): len = 215032, overlap = 1138.78
+PHY-3002 : Step(26): len = 209156, overlap = 1126.78
+PHY-3002 : Step(27): len = 204843, overlap = 1122.41
+PHY-3002 : Step(28): len = 198950, overlap = 1139.78
+PHY-3002 : Step(29): len = 195587, overlap = 1156.72
+PHY-3002 : Step(30): len = 192350, overlap = 1158.03
+PHY-3002 : Step(31): len = 191154, overlap = 1160.31
+PHY-3002 : Step(32): len = 188922, overlap = 1153.84
+PHY-3002 : Step(33): len = 186718, overlap = 1147.28
+PHY-3002 : Step(34): len = 184798, overlap = 1146.5
+PHY-3002 : Step(35): len = 183870, overlap = 1141.97
+PHY-3002 : Step(36): len = 181912, overlap = 1145.28
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 1.89259e-06
+PHY-3002 : Step(37): len = 185784, overlap = 1125.12
+PHY-3002 : Step(38): len = 198635, overlap = 1055.47
+PHY-3002 : Step(39): len = 206073, overlap = 996.688
+PHY-3002 : Step(40): len = 212064, overlap = 956.875
+PHY-3002 : Step(41): len = 215587, overlap = 928.531
+PHY-3002 : Step(42): len = 215911, overlap = 919.625
+PHY-3002 : Step(43): len = 215206, overlap = 902.875
+PHY-3002 : Step(44): len = 214903, overlap = 899.031
+PHY-3002 : Step(45): len = 214966, overlap = 899.344
+PHY-3002 : Step(46): len = 213102, overlap = 903.625
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 3.78519e-06
+PHY-3002 : Step(47): len = 222500, overlap = 879.375
+PHY-3002 : Step(48): len = 239824, overlap = 821.25
+PHY-3002 : Step(49): len = 247632, overlap = 766.938
+PHY-3002 : Step(50): len = 250250, overlap = 717.312
+PHY-3002 : Step(51): len = 250858, overlap = 720.781
+PHY-3002 : Step(52): len = 251337, overlap = 718.625
+PHY-3002 : Step(53): len = 250346, overlap = 719.281
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 7.57038e-06
+PHY-3002 : Step(54): len = 266497, overlap = 687.438
+PHY-3002 : Step(55): len = 284766, overlap = 618.844
+PHY-3002 : Step(56): len = 290612, overlap = 598.312
+PHY-3002 : Step(57): len = 292779, overlap = 562.969
+PHY-3002 : Step(58): len = 291367, overlap = 555
+PHY-3002 : Step(59): len = 290725, overlap = 546.062
+PHY-3002 : Step(60): len = 289615, overlap = 544.031
+PHY-3002 : Step(61): len = 289732, overlap = 546.625
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.51408e-05
+PHY-3002 : Step(62): len = 311431, overlap = 490.062
+PHY-3002 : Step(63): len = 328168, overlap = 445.906
+PHY-3002 : Step(64): len = 333733, overlap = 411.562
+PHY-3002 : Step(65): len = 337088, overlap = 390.094
+PHY-3002 : Step(66): len = 337200, overlap = 386.688
+PHY-3002 : Step(67): len = 338667, overlap = 383.906
+PHY-3002 : Step(68): len = 337565, overlap = 391.031
+PHY-3002 : Step(69): len = 338510, overlap = 393.688
+PHY-3002 : Step(70): len = 338766, overlap = 395.562
+PHY-3002 : Step(71): len = 338962, overlap = 397.438
+PHY-3002 : Step(72): len = 337619, overlap = 379.688
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.02815e-05
+PHY-3002 : Step(73): len = 358389, overlap = 348.469
+PHY-3002 : Step(74): len = 373279, overlap = 321.438
+PHY-3002 : Step(75): len = 374154, overlap = 287.562
+PHY-3002 : Step(76): len = 376036, overlap = 282.312
+PHY-3002 : Step(77): len = 378003, overlap = 269.906
+PHY-3002 : Step(78): len = 381357, overlap = 256.188
+PHY-3002 : Step(79): len = 378037, overlap = 261.531
+PHY-3002 : Step(80): len = 377895, overlap = 253.75
+PHY-3002 : Step(81): len = 379194, overlap = 249.562
+PHY-3002 : Step(82): len = 381755, overlap = 259.25
+PHY-3002 : Step(83): len = 380590, overlap = 260.938
+PHY-3002 : Step(84): len = 381300, overlap = 246.469
+PHY-3002 : Step(85): len = 381392, overlap = 250.938
+PHY-3002 : Step(86): len = 382724, overlap = 255.375
+PHY-3002 : Step(87): len = 380159, overlap = 259.75
+PHY-3002 : Step(88): len = 381474, overlap = 259.5
+PHY-3002 : Step(89): len = 381443, overlap = 256.438
+PHY-3002 : Step(90): len = 383150, overlap = 249.406
+PHY-3002 : Step(91): len = 381557, overlap = 255
+PHY-3002 : Step(92): len = 381708, overlap = 255.312
+PHY-3002 : Step(93): len = 380201, overlap = 244.406
+PHY-3002 : Step(94): len = 379918, overlap = 249.031
+PHY-3002 : Step(95): len = 379378, overlap = 252.625
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.0563e-05
+PHY-3002 : Step(96): len = 394401, overlap = 233.5
+PHY-3002 : Step(97): len = 405346, overlap = 204.938
+PHY-3002 : Step(98): len = 406774, overlap = 193.406
+PHY-3002 : Step(99): len = 408226, overlap = 193.719
+PHY-3002 : Step(100): len = 410163, overlap = 193.562
+PHY-3002 : Step(101): len = 413635, overlap = 197.125
+PHY-3002 : Step(102): len = 411632, overlap = 196.375
+PHY-3002 : Step(103): len = 412063, overlap = 185.188
+PHY-3002 : Step(104): len = 413243, overlap = 192.312
+PHY-3002 : Step(105): len = 414945, overlap = 185.188
+PHY-3002 : Step(106): len = 412023, overlap = 179.125
+PHY-3002 : Step(107): len = 412289, overlap = 186.031
+PHY-3002 : Step(108): len = 413249, overlap = 179.906
+PHY-3002 : Step(109): len = 415200, overlap = 176.469
+PHY-3002 : Step(110): len = 412147, overlap = 177.812
+PHY-3002 : Step(111): len = 412396, overlap = 178.656
+PHY-3002 : Step(112): len = 412948, overlap = 180.438
+PHY-3002 : Step(113): len = 413896, overlap = 176
+PHY-3002 : Step(114): len = 411642, overlap = 183.219
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000117109
+PHY-3002 : Step(115): len = 424606, overlap = 162.656
+PHY-3002 : Step(116): len = 433290, overlap = 163.062
+PHY-3002 : Step(117): len = 433161, overlap = 164.844
+PHY-3002 : Step(118): len = 434060, overlap = 157.625
+PHY-3002 : Step(119): len = 436988, overlap = 158.906
+PHY-3002 : Step(120): len = 440198, overlap = 159.438
+PHY-3002 : Step(121): len = 438514, overlap = 156.125
+PHY-3002 : Step(122): len = 439372, overlap = 168.781
+PHY-3002 : Step(123): len = 442030, overlap = 171.906
+PHY-3002 : Step(124): len = 443718, overlap = 171.219
+PHY-3002 : Step(125): len = 441411, overlap = 172.719
+PHY-3002 : Step(126): len = 441647, overlap = 172.562
+PHY-3002 : Step(127): len = 442833, overlap = 175.031
+PHY-3002 : Step(128): len = 444153, overlap = 186.281
+PHY-3002 : Step(129): len = 441868, overlap = 176.312
+PHY-3002 : Step(130): len = 441510, overlap = 181.469
+PHY-3002 : Step(131): len = 442613, overlap = 180.094
+PHY-3002 : Step(132): len = 443792, overlap = 168.219
+PHY-3002 : Step(133): len = 441703, overlap = 171
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000220907
+PHY-3002 : Step(134): len = 450612, overlap = 162.625
+PHY-3002 : Step(135): len = 457561, overlap = 166.406
+PHY-3002 : Step(136): len = 457913, overlap = 161.875
+PHY-3002 : Step(137): len = 458814, overlap = 154.031
+PHY-3002 : Step(138): len = 462082, overlap = 145.906
+PHY-3002 : Step(139): len = 464189, overlap = 137.125
+PHY-3002 : Step(140): len = 462771, overlap = 143.062
+PHY-3002 : Step(141): len = 463112, overlap = 141.531
+PHY-3002 : Step(142): len = 466165, overlap = 125.125
+PHY-3002 : Step(143): len = 468540, overlap = 123.875
+PHY-3002 : Step(144): len = 466144, overlap = 124.375
+PHY-3002 : Step(145): len = 465953, overlap = 126.469
+PHY-3002 : Step(146): len = 467174, overlap = 122.781
+PHY-3002 : Step(147): len = 468001, overlap = 122.969
+PHY-3002 : Step(148): len = 466754, overlap = 121.438
+PHY-3002 : Step(149): len = 466617, overlap = 119.594
+PHY-3002 : Step(150): len = 467420, overlap = 121.281
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000441815
+PHY-3002 : Step(151): len = 473295, overlap = 118.5
+PHY-3002 : Step(152): len = 481360, overlap = 123.125
+PHY-3002 : Step(153): len = 486416, overlap = 121.906
+PHY-3002 : Step(154): len = 488078, overlap = 115.812
+PHY-3002 : Step(155): len = 488869, overlap = 121.906
+PHY-3002 : Step(156): len = 489870, overlap = 118.781
+PHY-3002 : Step(157): len = 489830, overlap = 120.531
+PHY-3002 : Step(158): len = 489986, overlap = 122.031
+PHY-3002 : Step(159): len = 489706, overlap = 113.312
+PHY-3002 : Step(160): len = 489555, overlap = 105.938
+PHY-3002 : Step(161): len = 490104, overlap = 101.281
+PHY-3002 : Step(162): len = 491500, overlap = 104.844
+PHY-3002 : Step(163): len = 492932, overlap = 100.094
+PHY-3002 : Step(164): len = 493951, overlap = 97.875
+PHY-3002 : Step(165): len = 494337, overlap = 98.25
+PHY-3002 : Step(166): len = 495377, overlap = 98.7188
+PHY-3002 : Step(167): len = 495218, overlap = 96.625
+PHY-3002 : Step(168): len = 495815, overlap = 100
+PHY-3002 : Step(169): len = 495138, overlap = 103.844
+PHY-3002 : Step(170): len = 494697, overlap = 97.7812
+PHY-3002 : Step(171): len = 494348, overlap = 103.719
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000833566
+PHY-3002 : Step(172): len = 496802, overlap = 96.125
+PHY-3002 : Step(173): len = 500170, overlap = 94.3438
+PHY-3002 : Step(174): len = 501536, overlap = 93.8125
+PHY-3002 : Step(175): len = 502062, overlap = 93.5625
+PHY-3002 : Step(176): len = 502293, overlap = 86.7812
+PHY-3002 : Step(177): len = 502359, overlap = 88.0312
+PHY-3002 : Step(178): len = 502499, overlap = 90.0625
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.013245s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (118.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 670088, over cnt = 1369(3%), over = 5856, worst = 25
+PHY-1001 : End global iterations;  0.757191s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (134.1%)
+
+PHY-1001 : Congestion index: top1 = 74.35, top5 = 55.08, top10 = 47.06, top15 = 42.50.
+PHY-3001 : End congestion estimation;  0.974326s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (128.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.852871s wall, 0.812500s user + 0.031250s system = 0.843750s CPU (98.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.87269e-05
+PHY-3002 : Step(179): len = 611094, overlap = 36.7812
+PHY-3002 : Step(180): len = 629498, overlap = 29.875
+PHY-3002 : Step(181): len = 617273, overlap = 25.8438
+PHY-3002 : Step(182): len = 612122, overlap = 29.4062
+PHY-3002 : Step(183): len = 603530, overlap = 27.4062
+PHY-3002 : Step(184): len = 600128, overlap = 31.7188
+PHY-3002 : Step(185): len = 598912, overlap = 35.125
+PHY-3002 : Step(186): len = 591598, overlap = 39.6875
+PHY-3002 : Step(187): len = 588955, overlap = 40.75
+PHY-3002 : Step(188): len = 587415, overlap = 42.9062
+PHY-3002 : Step(189): len = 584589, overlap = 43.9688
+PHY-3002 : Step(190): len = 583403, overlap = 40.2812
+PHY-3002 : Step(191): len = 582336, overlap = 41.875
+PHY-3002 : Step(192): len = 579818, overlap = 40.4062
+PHY-3002 : Step(193): len = 579688, overlap = 40.4688
+PHY-3002 : Step(194): len = 578791, overlap = 39.6562
+PHY-3002 : Step(195): len = 578211, overlap = 41.8438
+PHY-3002 : Step(196): len = 576508, overlap = 42.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000177454
+PHY-3002 : Step(197): len = 578960, overlap = 42.3125
+PHY-3002 : Step(198): len = 582750, overlap = 40.375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00033251
+PHY-3002 : Step(199): len = 589819, overlap = 40.0312
+PHY-3002 : Step(200): len = 599950, overlap = 39.5625
+PHY-3002 : Step(201): len = 610813, overlap = 40.7812
+PHY-3002 : Step(202): len = 609601, overlap = 38.375
+PHY-3002 : Step(203): len = 609605, overlap = 42.125
+PHY-3002 : Step(204): len = 606844, overlap = 42.1875
+PHY-3002 : Step(205): len = 608246, overlap = 40.5312
+PHY-3002 : Step(206): len = 610102, overlap = 42.8125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 81/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 700840, over cnt = 2513(7%), over = 10808, worst = 39
+PHY-1001 : End global iterations;  1.634011s wall, 2.156250s user + 0.015625s system = 2.171875s CPU (132.9%)
+
+PHY-1001 : Congestion index: top1 = 78.38, top5 = 62.45, top10 = 54.94, top15 = 50.21.
+PHY-3001 : End congestion estimation;  1.907292s wall, 2.421875s user + 0.015625s system = 2.437500s CPU (127.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.886692s wall, 0.828125s user + 0.031250s system = 0.859375s CPU (96.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.76412e-05
+PHY-3002 : Step(207): len = 607916, overlap = 243.156
+PHY-3002 : Step(208): len = 614129, overlap = 201.344
+PHY-3002 : Step(209): len = 604854, overlap = 190.406
+PHY-3002 : Step(210): len = 600997, overlap = 164.438
+PHY-3002 : Step(211): len = 599911, overlap = 150.625
+PHY-3002 : Step(212): len = 592757, overlap = 151.875
+PHY-3002 : Step(213): len = 589373, overlap = 147.062
+PHY-3002 : Step(214): len = 586562, overlap = 148.344
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000195282
+PHY-3002 : Step(215): len = 586411, overlap = 142.344
+PHY-3002 : Step(216): len = 589367, overlap = 136.5
+PHY-3002 : Step(217): len = 593452, overlap = 139
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000390565
+PHY-3002 : Step(218): len = 597222, overlap = 136.312
+PHY-3002 : Step(219): len = 605582, overlap = 129.281
+PHY-3002 : Step(220): len = 610957, overlap = 126.594
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.470402s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 583 MB, reserved memory is 565 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 483.00 peak overflow 4.50
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 927/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709096, over cnt = 2790(7%), over = 9868, worst = 32
+PHY-1001 : End global iterations;  1.134073s wall, 1.640625s user + 0.031250s system = 1.671875s CPU (147.4%)
+
+PHY-1001 : Congestion index: top1 = 65.97, top5 = 55.56, top10 = 50.03, top15 = 46.28.
+PHY-1001 : End incremental global routing;  1.466157s wall, 1.968750s user + 0.031250s system = 2.000000s CPU (136.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.913467s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (99.2%)
+
+OPT-1001 : 47 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17699 has valid locations, 336 needs to be replaced
+PHY-3001 : design contains 18120 instances, 7611 luts, 9294 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6106 pins
+PHY-3001 : Found 1235 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 635943
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16069/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 726368, over cnt = 2806(7%), over = 10011, worst = 32
+PHY-1001 : End global iterations;  0.238840s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (130.8%)
+
+PHY-1001 : Congestion index: top1 = 66.06, top5 = 56.06, top10 = 50.50, top15 = 46.76.
+PHY-3001 : End congestion estimation;  0.484187s wall, 0.546875s user + 0.015625s system = 0.562500s CPU (116.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86724, tnet num: 20509, tinst num: 18120, tnode num: 117570, tedge num: 139118.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.489176s wall, 1.421875s user + 0.062500s system = 1.484375s CPU (99.7%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 618 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_nets {u_bus_top/start_sp_b_tmp[*]} ] -to [ get_regs {u_bus_top/start_sp_b_sync1d_48m[*]} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.469274s wall, 2.359375s user + 0.109375s system = 2.468750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(221): len = 634898, overlap = 0.0625
+PHY-3002 : Step(222): len = 634748, overlap = 0.0625
+PHY-3002 : Step(223): len = 634259, overlap = 0.0625
+PHY-3002 : Step(224): len = 634212, overlap = 0.0625
+PHY-3002 : Step(225): len = 634443, overlap = 0.0625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16115/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720960, over cnt = 2817(8%), over = 10052, worst = 32
+PHY-1001 : End global iterations;  0.224005s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.6%)
+
+PHY-1001 : Congestion index: top1 = 66.66, top5 = 56.13, top10 = 50.65, top15 = 46.95.
+PHY-3001 : End congestion estimation;  0.479390s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (104.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.092245s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000368783
+PHY-3002 : Step(226): len = 634901, overlap = 128.969
+PHY-3002 : Step(227): len = 635133, overlap = 129.406
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000737566
+PHY-3002 : Step(228): len = 635100, overlap = 129
+PHY-3002 : Step(229): len = 635452, overlap = 129.156
+PHY-3001 : Final: Len = 635452, Over = 129.156
+PHY-3001 : End incremental placement;  5.222189s wall, 5.421875s user + 0.328125s system = 5.750000s CPU (110.1%)
+
+OPT-1001 : Total overflow 488.25 peak overflow 4.50
+OPT-1001 : End high-fanout net optimization;  8.132275s wall, 8.906250s user + 0.375000s system = 9.281250s CPU (114.1%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16129/20687.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 724912, over cnt = 2776(7%), over = 9260, worst = 32
+PHY-1002 : len = 771056, over cnt = 1914(5%), over = 4806, worst = 20
+PHY-1002 : len = 811472, over cnt = 854(2%), over = 1834, worst = 20
+PHY-1002 : len = 836944, over cnt = 75(0%), over = 88, worst = 5
+PHY-1002 : len = 838664, over cnt = 4(0%), over = 7, worst = 4
+PHY-1001 : End global iterations;  1.863448s wall, 2.468750s user + 0.015625s system = 2.484375s CPU (133.3%)
+
+PHY-1001 : Congestion index: top1 = 58.21, top5 = 50.55, top10 = 46.61, top15 = 44.11.
+OPT-1001 : End congestion update;  2.120382s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (129.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20509 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.812943s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.9%)
+
+OPT-0007 : Start: WNS -5085 TNS -2609047 NUM_FEPS 1053
+OPT-0007 : Iter 1: improved WNS -4519 TNS -2534293 NUM_FEPS 1053 with 70 cells processed and 1666 slack improved
+OPT-0007 : Iter 2: improved WNS -4519 TNS -2532645 NUM_FEPS 1053 with 93 cells processed and 1400 slack improved
+OPT-0007 : Iter 3: improved WNS -4519 TNS -2532045 NUM_FEPS 1053 with 38 cells processed and 700 slack improved
+OPT-0007 : Iter 4: improved WNS -4469 TNS -2533115 NUM_FEPS 1053 with 11 cells processed and 150 slack improved
+OPT-0007 : Iter 5: improved WNS -4469 TNS -2531639 NUM_FEPS 1053 with 23 cells processed and 400 slack improved
+OPT-0007 : Iter 6: improved WNS -4469 TNS -2531539 NUM_FEPS 1053 with 8 cells processed and 200 slack improved
+OPT-0007 : Iter 7: improved WNS -4269 TNS -2466901 NUM_FEPS 1053 with 1 cells processed and 484 slack improved
+OPT-0007 : Iter 8: improved WNS -4269 TNS -2465323 NUM_FEPS 1053 with 1 cells processed and 250 slack improved
+OPT-1001 : End bottleneck based optimization;  3.905920s wall, 4.500000s user + 0.015625s system = 4.515625s CPU (115.6%)
+
+OPT-1001 : Current memory(MB): used = 704, reserve = 695, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16289/20689.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842512, over cnt = 169(0%), over = 315, worst = 10
+PHY-1002 : len = 843544, over cnt = 100(0%), over = 127, worst = 4
+PHY-1002 : len = 844216, over cnt = 48(0%), over = 55, worst = 3
+PHY-1002 : len = 844824, over cnt = 20(0%), over = 22, worst = 2
+PHY-1002 : len = 845256, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.736967s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (112.4%)
+
+PHY-1001 : Congestion index: top1 = 57.97, top5 = 50.51, top10 = 46.63, top15 = 44.17.
+OPT-1001 : End congestion update;  1.002240s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (109.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20511 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.802034s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.4%)
+
+OPT-0007 : Start: WNS -4269 TNS -2465323 NUM_FEPS 1053
+OPT-0007 : Iter 1: improved WNS -4269 TNS -2461823 NUM_FEPS 1053 with 53 cells processed and 3650 slack improved
+OPT-0007 : Iter 2: improved WNS -4269 TNS -2461823 NUM_FEPS 1053 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.947250s wall, 2.046875s user + 0.000000s system = 2.046875s CPU (105.1%)
+
+OPT-1001 : Current memory(MB): used = 714, reserve = 700, peak = 743.
+OPT-1001 : End physical optimization;  15.757167s wall, 17.171875s user + 0.453125s system = 17.625000s CPU (111.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7611 LUT to BLE ...
+SYN-4008 : Packed 7611 LUT and 3144 SEQ to BLE.
+SYN-4003 : Packing 6152 remaining SEQ's ...
+SYN-4005 : Packed 3681 SEQ with LUT/SLICE
+SYN-4006 : 1091 single LUT's are left
+SYN-4006 : 2471 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10082/13895 primitive instances ...
+PHY-3001 : End packing;  1.728325s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6984 instances
+RUN-1001 : 3418 mslices, 3418 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17664 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9978 nets have 2 pins
+RUN-1001 : 5811 nets have [3 - 5] pins
+RUN-1001 : 1182 nets have [6 - 10] pins
+RUN-1001 : 302 nets have [11 - 20] pins
+RUN-1001 : 358 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6982 instances, 6836 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3611 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 645206, Over = 319
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7494/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 796520, over cnt = 1812(5%), over = 3089, worst = 9
+PHY-1002 : len = 803552, over cnt = 1296(3%), over = 1991, worst = 9
+PHY-1002 : len = 816024, over cnt = 628(1%), over = 965, worst = 7
+PHY-1002 : len = 825936, over cnt = 268(0%), over = 396, worst = 7
+PHY-1002 : len = 831400, over cnt = 39(0%), over = 58, worst = 4
+PHY-1001 : End global iterations;  1.529572s wall, 2.078125s user + 0.031250s system = 2.109375s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 58.36, top5 = 51.00, top10 = 46.93, top15 = 44.43.
+PHY-3001 : End congestion estimation;  1.930411s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74904, tnet num: 17486, tinst num: 6982, tnode num: 97547, tedge num: 125845.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.737518s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (98.9%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 623 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.624663s wall, 2.593750s user + 0.000000s system = 2.593750s CPU (98.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 3.9602e-05
+PHY-3002 : Step(230): len = 631584, overlap = 332.25
+PHY-3002 : Step(231): len = 623648, overlap = 336.5
+PHY-3002 : Step(232): len = 618967, overlap = 344
+PHY-3002 : Step(233): len = 615592, overlap = 337.75
+PHY-3002 : Step(234): len = 613049, overlap = 342.5
+PHY-3002 : Step(235): len = 610060, overlap = 344.75
+PHY-3002 : Step(236): len = 607237, overlap = 346
+PHY-3002 : Step(237): len = 604218, overlap = 350
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 7.9204e-05
+PHY-3002 : Step(238): len = 608379, overlap = 349
+PHY-3002 : Step(239): len = 614345, overlap = 336.75
+PHY-3002 : Step(240): len = 614925, overlap = 333
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000158408
+PHY-3002 : Step(241): len = 625426, overlap = 312
+PHY-3002 : Step(242): len = 631858, overlap = 307.25
+PHY-3002 : Step(243): len = 629581, overlap = 304
+PHY-3002 : Step(244): len = 628797, overlap = 304
+PHY-3002 : Step(245): len = 628888, overlap = 302
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.346908s wall, 0.296875s user + 0.593750s system = 0.890625s CPU (256.7%)
+
+PHY-3001 : Trial Legalized: Len = 742267
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 543/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859264, over cnt = 2760(7%), over = 4945, worst = 9
+PHY-1002 : len = 879648, over cnt = 1784(5%), over = 2628, worst = 8
+PHY-1002 : len = 899120, over cnt = 840(2%), over = 1167, worst = 5
+PHY-1002 : len = 905776, over cnt = 562(1%), over = 741, worst = 5
+PHY-1002 : len = 920296, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.425882s wall, 3.609375s user + 0.000000s system = 3.609375s CPU (148.8%)
+
+PHY-1001 : Congestion index: top1 = 57.13, top5 = 51.95, top10 = 48.89, top15 = 46.76.
+PHY-3001 : End congestion estimation;  2.878688s wall, 4.078125s user + 0.000000s system = 4.078125s CPU (141.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.896832s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000181197
+PHY-3002 : Step(246): len = 696735, overlap = 92.25
+PHY-3002 : Step(247): len = 676996, overlap = 144.25
+PHY-3002 : Step(248): len = 663105, overlap = 191.5
+PHY-3002 : Step(249): len = 656074, overlap = 219.25
+PHY-3002 : Step(250): len = 652221, overlap = 225.5
+PHY-3002 : Step(251): len = 650028, overlap = 230.25
+PHY-3002 : Step(252): len = 648434, overlap = 236.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000362394
+PHY-3002 : Step(253): len = 654148, overlap = 231.5
+PHY-3002 : Step(254): len = 660001, overlap = 234.25
+PHY-3002 : Step(255): len = 662805, overlap = 239
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000724789
+PHY-3002 : Step(256): len = 665647, overlap = 235.5
+PHY-3002 : Step(257): len = 675016, overlap = 225.25
+PHY-3002 : Step(258): len = 681280, overlap = 229.75
+PHY-3002 : Step(259): len = 680141, overlap = 227.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.037321s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (83.7%)
+
+PHY-3001 : Legalized: Len = 724353, Over = 0
+PHY-3001 : Spreading special nets. 566 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.123336s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.3%)
+
+PHY-3001 : 829 instances has been re-located, deltaX = 290, deltaY = 488, maxDist = 4.
+PHY-3001 : Final: Len = 736209, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74904, tnet num: 17486, tinst num: 6985, tnode num: 97547, tedge num: 125845.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.910107s wall, 1.875000s user + 0.031250s system = 1.906250s CPU (99.8%)
+
+RUN-1004 : used memory is 632 MB, reserved memory is 637 MB, peak memory is 743 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3013/17664.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 862248, over cnt = 2584(7%), over = 4345, worst = 7
+PHY-1002 : len = 877656, over cnt = 1607(4%), over = 2376, worst = 6
+PHY-1002 : len = 900920, over cnt = 397(1%), over = 552, worst = 6
+PHY-1002 : len = 908152, over cnt = 104(0%), over = 149, worst = 4
+PHY-1002 : len = 911608, over cnt = 16(0%), over = 18, worst = 3
+PHY-1001 : End global iterations;  2.081539s wall, 3.000000s user + 0.031250s system = 3.031250s CPU (145.6%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.44, top10 = 47.41, top15 = 45.31.
+PHY-1001 : End incremental global routing;  2.450389s wall, 3.359375s user + 0.031250s system = 3.390625s CPU (138.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17486 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.880710s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (101.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6893 has valid locations, 21 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 739843
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16050/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915144, over cnt = 69(0%), over = 77, worst = 3
+PHY-1002 : len = 915248, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 915496, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 915536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.577112s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.45, top10 = 47.44, top15 = 45.36.
+PHY-3001 : End congestion estimation;  0.895428s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (104.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75067, tnet num: 17503, tinst num: 7002, tnode num: 97741, tedge num: 126046.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.932858s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (99.4%)
+
+RUN-1004 : used memory is 700 MB, reserved memory is 701 MB, peak memory is 745 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.879810s wall, 2.843750s user + 0.031250s system = 2.875000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(260): len = 738594, overlap = 0
+PHY-3002 : Step(261): len = 738218, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16041/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913312, over cnt = 54(0%), over = 63, worst = 3
+PHY-1002 : len = 913488, over cnt = 24(0%), over = 24, worst = 1
+PHY-1002 : len = 913672, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 913792, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 913840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.773786s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (111.1%)
+
+PHY-1001 : Congestion index: top1 = 56.03, top5 = 50.47, top10 = 47.43, top15 = 45.34.
+PHY-3001 : End congestion estimation;  1.107758s wall, 1.156250s user + 0.015625s system = 1.171875s CPU (105.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.872107s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (98.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000332748
+PHY-3002 : Step(262): len = 738049, overlap = 1.25
+PHY-3002 : Step(263): len = 738003, overlap = 1.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005824s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (268.3%)
+
+PHY-3001 : Legalized: Len = 738084, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061009s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.4%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 738104, Over = 0
+PHY-3001 : End incremental placement;  6.245190s wall, 6.312500s user + 0.062500s system = 6.375000s CPU (102.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.075165s wall, 11.031250s user + 0.109375s system = 11.140625s CPU (110.6%)
+
+OPT-1001 : Current memory(MB): used = 753, reserve = 744, peak = 756.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16037/17681.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913704, over cnt = 34(0%), over = 43, worst = 4
+PHY-1002 : len = 913840, over cnt = 16(0%), over = 16, worst = 1
+PHY-1002 : len = 913928, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 913992, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.579314s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (105.2%)
+
+PHY-1001 : Congestion index: top1 = 56.08, top5 = 50.44, top10 = 47.42, top15 = 45.33.
+OPT-1001 : End congestion update;  0.891768s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (105.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17503 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.735566s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.8%)
+
+OPT-0007 : Start: WNS -4188 TNS -2273902 NUM_FEPS 978
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6914 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 738352, Over = 0
+PHY-3001 : Spreading special nets. 18 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061226s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.1%)
+
+PHY-3001 : 24 instances has been re-located, deltaX = 7, deltaY = 18, maxDist = 2.
+PHY-3001 : Final: Len = 738926, Over = 0
+PHY-3001 : End incremental legalization;  0.393124s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.4%)
+
+OPT-0007 : Iter 1: improved WNS -3888 TNS -2268531 NUM_FEPS 978 with 40 cells processed and 4886 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6914 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7002 instances, 6853 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3675 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 739072, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062792s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%)
+
+PHY-3001 : 18 instances has been re-located, deltaX = 6, deltaY = 15, maxDist = 2.
+PHY-3001 : Final: Len = 739464, Over = 0
+PHY-3001 : End incremental legalization;  0.395688s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.7%)
+
+OPT-0007 : Iter 2: improved WNS -3988 TNS -2257868 NUM_FEPS 978 with 30 cells processed and 2801 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 739802, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062384s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.2%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 739900, Over = 0
+PHY-3001 : End incremental legalization;  0.392472s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (139.3%)
+
+OPT-0007 : Iter 3: improved WNS -3988 TNS -2256151 NUM_FEPS 978 with 12 cells processed and 1350 slack improved
+OPT-1001 : End bottleneck based optimization;  3.458324s wall, 3.750000s user + 0.015625s system = 3.765625s CPU (108.9%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 745, peak = 757.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15737/17682.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 915280, over cnt = 287(0%), over = 358, worst = 4
+PHY-1002 : len = 915312, over cnt = 149(0%), over = 172, worst = 3
+PHY-1002 : len = 916400, over cnt = 66(0%), over = 67, worst = 2
+PHY-1002 : len = 917584, over cnt = 13(0%), over = 13, worst = 1
+PHY-1002 : len = 917800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.925213s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (109.8%)
+
+PHY-1001 : Congestion index: top1 = 56.10, top5 = 50.39, top10 = 47.44, top15 = 45.35.
+OPT-1001 : End congestion update;  1.251994s wall, 1.343750s user + 0.000000s system = 1.343750s CPU (107.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.771351s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.3%)
+
+OPT-0007 : Start: WNS -3988 TNS -2259553 NUM_FEPS 978
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 740816, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062629s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 7, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 740954, Over = 0
+PHY-3001 : End incremental legalization;  0.404954s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.5%)
+
+OPT-0007 : Iter 1: improved WNS -3888 TNS -2258287 NUM_FEPS 978 with 32 cells processed and 2246 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6926 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7014 instances, 6865 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3681 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 740886, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061741s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 5, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 740890, Over = 0
+PHY-3001 : End incremental legalization;  0.393035s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (103.4%)
+
+OPT-0007 : Iter 2: improved WNS -3888 TNS -2257363 NUM_FEPS 978 with 10 cells processed and 507 slack improved
+OPT-0007 : Iter 3: improved WNS -3888 TNS -2257363 NUM_FEPS 978 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  3.105720s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (103.1%)
+
+OPT-1001 : Current memory(MB): used = 754, reserve = 745, peak = 757.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.781615s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.0%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15907/17682.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 918448, over cnt = 97(0%), over = 128, worst = 4
+PHY-1002 : len = 918688, over cnt = 54(0%), over = 57, worst = 2
+PHY-1002 : len = 919064, over cnt = 25(0%), over = 28, worst = 2
+PHY-1002 : len = 919320, over cnt = 12(0%), over = 14, worst = 2
+PHY-1002 : len = 919512, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.792916s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (116.3%)
+
+PHY-1001 : Congestion index: top1 = 56.14, top5 = 50.29, top10 = 47.40, top15 = 45.37.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.770173s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (101.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -3954 TNS -2257372 NUM_FEPS 978
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 55.758621
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -3954ps with logic level 5 
+RUN-1001 :       #2 path slack -3954ps with logic level 5 
+RUN-1001 :       #3 path slack -3938ps with logic level 5 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17682 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17682 nets
+OPT-1001 : End physical optimization;  21.583922s wall, 22.984375s user + 0.187500s system = 23.171875s CPU (107.4%)
+
+RUN-1003 : finish command "place" in  64.474297s wall, 88.937500s user + 5.062500s system = 94.000000s CPU (145.8%)
+
+RUN-1004 : used memory is 657 MB, reserved memory is 657 MB, peak memory is 757 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.693673s wall, 2.937500s user + 0.046875s system = 2.984375s CPU (176.2%)
+
+RUN-1004 : used memory is 658 MB, reserved memory is 658 MB, peak memory is 757 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7016 instances
+RUN-1001 : 3433 mslices, 3432 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17682 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 9960 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1191 nets have [6 - 10] pins
+RUN-1001 : 316 nets have [11 - 20] pins
+RUN-1001 : 367 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75197, tnet num: 17504, tinst num: 7014, tnode num: 97908, tedge num: 126206.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.631395s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (100.6%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 625 MB, peak memory is 757 MB
+PHY-1001 : 3433 mslices, 3432 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[5] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847168, over cnt = 2727(7%), over = 4656, worst = 8
+PHY-1002 : len = 864896, over cnt = 1772(5%), over = 2611, worst = 6
+PHY-1002 : len = 884752, over cnt = 823(2%), over = 1152, worst = 6
+PHY-1002 : len = 903456, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 903768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.939726s wall, 3.875000s user + 0.015625s system = 3.890625s CPU (132.3%)
+
+PHY-1001 : Congestion index: top1 = 55.37, top5 = 50.02, top10 = 47.07, top15 = 45.07.
+PHY-1001 : End global routing;  3.278280s wall, 4.218750s user + 0.015625s system = 4.234375s CPU (129.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 722, reserve = 719, peak = 757.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 996, reserve = 992, peak = 996.
+PHY-1001 : End build detailed router design. 4.019375s wall, 3.968750s user + 0.031250s system = 4.000000s CPU (99.5%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 262784, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.040112s wall, 5.031250s user + 0.000000s system = 5.031250s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 262840, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.508483s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (98.3%)
+
+PHY-1001 : Current memory(MB): used = 1032, reserve = 1029, peak = 1032.
+PHY-1001 : End phase 1; 5.563411s wall, 5.546875s user + 0.000000s system = 5.546875s CPU (99.7%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 38% nets.
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 54% nets.
+PHY-1001 : Routed 69% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.37434e+06, over cnt = 1762(0%), over = 1778, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1045, peak = 1050.
+PHY-1001 : End initial routed; 25.972895s wall, 56.031250s user + 0.359375s system = 56.390625s CPU (217.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.332   |  -3468.333  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.326384s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1063, reserve = 1060, peak = 1063.
+PHY-1001 : End phase 2; 29.299352s wall, 59.343750s user + 0.359375s system = 59.703125s CPU (203.8%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 66 pins with SWNS -6.129ns STNS -3457.538ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.495542s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (100.9%)
+
+PHY-1022 : len = 2.37478e+06, over cnt = 1816(0%), over = 1833, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.790830s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (98.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33911e+06, over cnt = 592(0%), over = 593, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.123893s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (158.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33632e+06, over cnt = 148(0%), over = 148, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.859895s wall, 1.125000s user + 0.000000s system = 1.125000s CPU (130.8%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33726e+06, over cnt = 33(0%), over = 33, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.390881s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (127.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33777e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.300312s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (114.5%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33786e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.277899s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (123.7%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.33792e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.360964s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.9%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.33792e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.497290s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (100.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.33791e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.180499s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (95.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33793e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.189111s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.1%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.129   |  -3462.818  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.357880s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 573 feed throughs used by 410 nets
+PHY-1001 : End commit to database; 2.312876s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1168, peak = 1168.
+PHY-1001 : End phase 3; 12.075352s wall, 13.781250s user + 0.015625s system = 13.796875s CPU (114.3%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 40 pins with SWNS -6.000ns STNS -3458.118ns FEP 984.
+PHY-1001 : End OPT Iter 1; 0.452271s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.2%)
+
+PHY-1022 : len = 2.33809e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.700027s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (100.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-6.000ns, -3458.118ns, 984}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3377e+06, over cnt = 9(0%), over = 9, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.193303s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (121.2%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.250774s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (105.9%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.337503s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (101.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33765e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.470181s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.33763e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.178990s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (96.0%)
+
+PHY-1001 : ==== DR Iter 6 ====
+PHY-1022 : len = 2.33765e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 6; 0.196508s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (95.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1990/16609(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.226   |  -3463.404  |  984  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.300349s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1177, reserve = 1177, peak = 1177.
+PHY-1001 : End phase 4; 5.698694s wall, 5.734375s user + 0.000000s system = 5.734375s CPU (100.6%)
+
+PHY-1003 : Routed, final wirelength = 2.33765e+06
+PHY-1001 : Current memory(MB): used = 1177, reserve = 1177, peak = 1177.
+PHY-1001 : End export database. 0.060207s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.8%)
+
+PHY-1001 : End detail routing;  57.119733s wall, 88.843750s user + 0.406250s system = 89.250000s CPU (156.3%)
+
+RUN-1003 : finish command "route" in  63.114962s wall, 95.734375s user + 0.453125s system = 96.187500s CPU (152.4%)
+
+RUN-1004 : used memory is 1101 MB, reserved memory is 1101 MB, peak memory is 1177 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10440   out of  19600   53.27%
+#reg                     9429   out of  19600   48.11%
+#le                     12814
+  #lut only              3385   out of  12814   26.42%
+  #reg only              2374   out of  12814   18.53%
+  #lut&reg               7055   out of  12814   55.06%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1820
+#2        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1391
+#3        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1386
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               971
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    136
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          76
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               23
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             exdev_ctl_a/reg1_syn_162.f1                        3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg48_syn_235.f0    2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12814  |9419    |1021    |9459    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |542    |471     |23      |440     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |103    |97      |4       |92      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |44     |44      |0       |24      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |771    |368     |96      |579     |0       |0       |
+|    u_ADconfig                |AD_config            |190    |115     |25      |146     |0       |0       |
+|    u_gen_sp                  |gen_sp               |268    |167     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |745    |425     |96      |554     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |135     |25      |126     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |167     |71      |118     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3074   |2350    |303     |2137    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |8      |4       |0       |8       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |166    |85      |14      |136     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |2891   |2252    |289     |1984    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |5      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2444   |1953    |253     |1628    |22      |1       |
+|        channelPart           |channel_part_8478    |168    |157     |3       |142     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |46      |0       |1       |
+|        ram_switch            |ram_switch           |1908   |1507    |197     |1216    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |244    |208     |27      |136     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |18     |8       |3       |13      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |17      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |982    |623     |170     |688     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |682    |676     |0       |392     |0       |0       |
+|        read_ram_i            |read_ram             |265    |212     |44      |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |212    |172     |40      |149     |0       |0       |
+|          read_ram_data       |read_ram_data        |52     |39      |4       |31      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |340    |223     |36      |282     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3572   |2883    |340     |2052    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |185    |103     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |3355   |2759    |323     |1872    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2933   |2416    |281     |1529    |22      |0       |
+|        channelPart           |channel_part_8478    |251    |244     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |41      |0       |0       |
+|        ram_switch            |ram_switch           |2239   |1853    |197     |1093    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |258    |230     |27      |121     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |11      |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |32     |29      |3       |19      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |15      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
+|          insert              |insert               |930    |575     |170     |632     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051   |1048    |0       |340     |0       |0       |
+|        read_ram_i            |read_ram_rev         |337    |238     |72      |203     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |275    |200     |64      |158     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |62     |38      |8       |45      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9898  
+    #2         2       3828  
+    #3         3       1432  
+    #4         4       555   
+    #5        5-10     1252  
+    #6       11-50     588   
+    #7       51-100     31   
+    #8        >500      1    
+  Average     2.96           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.106032s wall, 3.625000s user + 0.031250s system = 3.656250s CPU (173.6%)
+
+RUN-1004 : used memory is 1102 MB, reserved memory is 1102 MB, peak memory is 1177 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75197, tnet num: 17504, tinst num: 7014, tnode num: 97908, tedge num: 126206.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.655000s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.1%)
+
+RUN-1004 : used memory is 1107 MB, reserved memory is 1107 MB, peak memory is 1177 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17504 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.487395s wall, 1.484375s user + 0.000000s system = 1.484375s CPU (99.8%)
+
+RUN-1004 : used memory is 1109 MB, reserved memory is 1109 MB, peak memory is 1177 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7014
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17682, pip num: 175905
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 573
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3248 valid insts, and 487263 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.613749s wall, 63.093750s user + 0.187500s system = 63.281250s CPU (658.2%)
+
+RUN-1004 : used memory is 1278 MB, reserved memory is 1274 MB, peak memory is 1394 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_133926.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_134954.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_134954.log
new file mode 100644
index 0000000..e2a93b6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_134954.log
@@ -0,0 +1,2040 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:49:54 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.425153s wall, 2.265625s user + 0.156250s system = 2.421875s CPU (99.9%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 350 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17833 instances
+RUN-0007 : 7532 luts, 9084 seqs, 696 mslices, 373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20398 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13443 nets have 2 pins
+RUN-1001 : 5472 nets have [3 - 5] pins
+RUN-1001 : 1067 nets have [6 - 10] pins
+RUN-1001 : 171 nets have [11 - 20] pins
+RUN-1001 : 170 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1998     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17831 instances, 7532 luts, 9084 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5973 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.154641s wall, 1.093750s user + 0.062500s system = 1.156250s CPU (100.1%)
+
+RUN-1004 : used memory is 540 MB, reserved memory is 516 MB, peak memory is 540 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.997694s wall, 1.921875s user + 0.078125s system = 2.000000s CPU (100.1%)
+
+PHY-3001 : Found 1228 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.07565e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17831.
+PHY-3001 : Level 1 #clusters 2356.
+PHY-3001 : End clustering;  0.136272s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (114.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.35078e+06, overlap = 469.094
+PHY-3002 : Step(2): len = 1.03404e+06, overlap = 543.5
+PHY-3002 : Step(3): len = 830693, overlap = 635.781
+PHY-3002 : Step(4): len = 695790, overlap = 706.25
+PHY-3002 : Step(5): len = 552155, overlap = 812.5
+PHY-3002 : Step(6): len = 469807, overlap = 882.406
+PHY-3002 : Step(7): len = 409365, overlap = 943.25
+PHY-3002 : Step(8): len = 363453, overlap = 993.719
+PHY-3002 : Step(9): len = 328140, overlap = 1042.12
+PHY-3002 : Step(10): len = 289061, overlap = 1090.69
+PHY-3002 : Step(11): len = 266226, overlap = 1158.31
+PHY-3002 : Step(12): len = 247163, overlap = 1189
+PHY-3002 : Step(13): len = 225726, overlap = 1246.53
+PHY-3002 : Step(14): len = 215540, overlap = 1279.38
+PHY-3002 : Step(15): len = 202030, overlap = 1302
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.03682e-06
+PHY-3002 : Step(16): len = 201180, overlap = 1291.84
+PHY-3002 : Step(17): len = 226393, overlap = 1213.59
+PHY-3002 : Step(18): len = 231048, overlap = 1187.94
+PHY-3002 : Step(19): len = 230495, overlap = 1162.19
+PHY-3002 : Step(20): len = 225435, overlap = 1154.22
+PHY-3002 : Step(21): len = 224802, overlap = 1144.69
+PHY-3002 : Step(22): len = 221424, overlap = 1149.97
+PHY-3002 : Step(23): len = 220959, overlap = 1131.59
+PHY-3002 : Step(24): len = 216455, overlap = 1129.66
+PHY-3002 : Step(25): len = 212573, overlap = 1121.62
+PHY-3002 : Step(26): len = 206886, overlap = 1110.25
+PHY-3002 : Step(27): len = 201604, overlap = 1092.81
+PHY-3002 : Step(28): len = 196287, overlap = 1090.84
+PHY-3002 : Step(29): len = 192845, overlap = 1085.84
+PHY-3002 : Step(30): len = 189817, overlap = 1100.59
+PHY-3002 : Step(31): len = 187477, overlap = 1093.22
+PHY-3002 : Step(32): len = 186056, overlap = 1105.28
+PHY-3002 : Step(33): len = 184096, overlap = 1087.88
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.07364e-06
+PHY-3002 : Step(34): len = 188211, overlap = 1054.16
+PHY-3002 : Step(35): len = 202071, overlap = 1015.25
+PHY-3002 : Step(36): len = 211757, overlap = 932.562
+PHY-3002 : Step(37): len = 218944, overlap = 892.219
+PHY-3002 : Step(38): len = 221756, overlap = 881.156
+PHY-3002 : Step(39): len = 222225, overlap = 870.812
+PHY-3002 : Step(40): len = 220892, overlap = 865.969
+PHY-3002 : Step(41): len = 220230, overlap = 870.219
+PHY-3002 : Step(42): len = 219489, overlap = 860.031
+PHY-3002 : Step(43): len = 218250, overlap = 844.188
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.14728e-06
+PHY-3002 : Step(44): len = 229746, overlap = 822.719
+PHY-3002 : Step(45): len = 249521, overlap = 788.156
+PHY-3002 : Step(46): len = 256841, overlap = 708
+PHY-3002 : Step(47): len = 259635, overlap = 680.094
+PHY-3002 : Step(48): len = 257691, overlap = 658.969
+PHY-3002 : Step(49): len = 255895, overlap = 638.031
+PHY-3002 : Step(50): len = 253729, overlap = 651.719
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 8.29456e-06
+PHY-3002 : Step(51): len = 269001, overlap = 620.375
+PHY-3002 : Step(52): len = 289194, overlap = 570.594
+PHY-3002 : Step(53): len = 296899, overlap = 547.062
+PHY-3002 : Step(54): len = 299245, overlap = 533.812
+PHY-3002 : Step(55): len = 296503, overlap = 535.719
+PHY-3002 : Step(56): len = 294287, overlap = 533.125
+PHY-3002 : Step(57): len = 291658, overlap = 533.125
+PHY-3002 : Step(58): len = 292115, overlap = 541.281
+PHY-3002 : Step(59): len = 291944, overlap = 522.344
+PHY-3002 : Step(60): len = 292936, overlap = 515.344
+PHY-3002 : Step(61): len = 293017, overlap = 495.875
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.65891e-05
+PHY-3002 : Step(62): len = 310159, overlap = 468.312
+PHY-3002 : Step(63): len = 325052, overlap = 441.25
+PHY-3002 : Step(64): len = 331006, overlap = 387.844
+PHY-3002 : Step(65): len = 335253, overlap = 368.688
+PHY-3002 : Step(66): len = 336138, overlap = 340
+PHY-3002 : Step(67): len = 338166, overlap = 327.25
+PHY-3002 : Step(68): len = 335374, overlap = 334.438
+PHY-3002 : Step(69): len = 336182, overlap = 341.562
+PHY-3002 : Step(70): len = 335446, overlap = 347.094
+PHY-3002 : Step(71): len = 336716, overlap = 343.656
+PHY-3002 : Step(72): len = 334950, overlap = 345.219
+PHY-3002 : Step(73): len = 335382, overlap = 333.312
+PHY-3002 : Step(74): len = 335112, overlap = 342.969
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.31782e-05
+PHY-3002 : Step(75): len = 353073, overlap = 317.812
+PHY-3002 : Step(76): len = 364950, overlap = 311.375
+PHY-3002 : Step(77): len = 367681, overlap = 298.469
+PHY-3002 : Step(78): len = 369129, overlap = 286.156
+PHY-3002 : Step(79): len = 369981, overlap = 291.469
+PHY-3002 : Step(80): len = 371997, overlap = 282.094
+PHY-3002 : Step(81): len = 371796, overlap = 268.125
+PHY-3002 : Step(82): len = 372560, overlap = 259.531
+PHY-3002 : Step(83): len = 374474, overlap = 258.594
+PHY-3002 : Step(84): len = 375362, overlap = 235.219
+PHY-3002 : Step(85): len = 375784, overlap = 253.625
+PHY-3002 : Step(86): len = 378351, overlap = 275.156
+PHY-3002 : Step(87): len = 379116, overlap = 252.25
+PHY-3002 : Step(88): len = 378273, overlap = 244.812
+PHY-3002 : Step(89): len = 376686, overlap = 245.875
+PHY-3002 : Step(90): len = 377234, overlap = 241.562
+PHY-3002 : Step(91): len = 376981, overlap = 232.688
+PHY-3002 : Step(92): len = 376721, overlap = 222.125
+PHY-3002 : Step(93): len = 376741, overlap = 224.531
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 6.63565e-05
+PHY-3002 : Step(94): len = 390935, overlap = 224.062
+PHY-3002 : Step(95): len = 400173, overlap = 205.438
+PHY-3002 : Step(96): len = 398988, overlap = 199.031
+PHY-3002 : Step(97): len = 399304, overlap = 210.312
+PHY-3002 : Step(98): len = 400409, overlap = 206.938
+PHY-3002 : Step(99): len = 401839, overlap = 206.188
+PHY-3002 : Step(100): len = 400989, overlap = 211.188
+PHY-3002 : Step(101): len = 402581, overlap = 211.344
+PHY-3002 : Step(102): len = 404215, overlap = 223.906
+PHY-3002 : Step(103): len = 405389, overlap = 215.5
+PHY-3002 : Step(104): len = 403520, overlap = 220.094
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000132046
+PHY-3002 : Step(105): len = 414037, overlap = 220.406
+PHY-3002 : Step(106): len = 421794, overlap = 203.906
+PHY-3002 : Step(107): len = 422757, overlap = 199.906
+PHY-3002 : Step(108): len = 424480, overlap = 190.969
+PHY-3002 : Step(109): len = 428842, overlap = 167
+PHY-3002 : Step(110): len = 431732, overlap = 160.656
+PHY-3002 : Step(111): len = 431120, overlap = 164.094
+PHY-3002 : Step(112): len = 431782, overlap = 150.75
+PHY-3002 : Step(113): len = 432824, overlap = 156.844
+PHY-3002 : Step(114): len = 433385, overlap = 162.062
+PHY-3002 : Step(115): len = 431819, overlap = 160.094
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000244364
+PHY-3002 : Step(116): len = 439418, overlap = 154.094
+PHY-3002 : Step(117): len = 445827, overlap = 141
+PHY-3002 : Step(118): len = 447261, overlap = 138.344
+PHY-3002 : Step(119): len = 449680, overlap = 135.031
+PHY-3002 : Step(120): len = 454080, overlap = 134.031
+PHY-3002 : Step(121): len = 456894, overlap = 140.031
+PHY-3002 : Step(122): len = 455301, overlap = 136.312
+PHY-3002 : Step(123): len = 454427, overlap = 127.219
+PHY-3002 : Step(124): len = 455042, overlap = 124.625
+PHY-3002 : Step(125): len = 455683, overlap = 129.094
+PHY-3002 : Step(126): len = 454827, overlap = 135.125
+PHY-3002 : Step(127): len = 455571, overlap = 134.625
+PHY-3002 : Step(128): len = 457596, overlap = 126.906
+PHY-3002 : Step(129): len = 459854, overlap = 119.156
+PHY-3002 : Step(130): len = 459853, overlap = 124.844
+PHY-3002 : Step(131): len = 460439, overlap = 115.812
+PHY-3002 : Step(132): len = 462476, overlap = 107.625
+PHY-3002 : Step(133): len = 465549, overlap = 107.625
+PHY-3002 : Step(134): len = 466516, overlap = 110.531
+PHY-3002 : Step(135): len = 467838, overlap = 114.312
+PHY-3002 : Step(136): len = 468773, overlap = 120.344
+PHY-3002 : Step(137): len = 468613, overlap = 118.812
+PHY-3002 : Step(138): len = 468478, overlap = 121.656
+PHY-3002 : Step(139): len = 468214, overlap = 111.812
+PHY-3002 : Step(140): len = 467323, overlap = 109.312
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000488728
+PHY-3002 : Step(141): len = 470415, overlap = 103.188
+PHY-3002 : Step(142): len = 473836, overlap = 104.906
+PHY-3002 : Step(143): len = 475460, overlap = 106.031
+PHY-3002 : Step(144): len = 476663, overlap = 107.219
+PHY-3002 : Step(145): len = 477719, overlap = 109.562
+PHY-3002 : Step(146): len = 478098, overlap = 107.188
+PHY-3002 : Step(147): len = 477551, overlap = 108.094
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000838173
+PHY-3002 : Step(148): len = 480542, overlap = 104.844
+PHY-3002 : Step(149): len = 484668, overlap = 99.625
+PHY-3002 : Step(150): len = 485870, overlap = 101.562
+PHY-3002 : Step(151): len = 487013, overlap = 103.969
+PHY-3002 : Step(152): len = 489538, overlap = 104.25
+PHY-3002 : Step(153): len = 491719, overlap = 112.188
+PHY-3002 : Step(154): len = 491241, overlap = 110.031
+PHY-3002 : Step(155): len = 491255, overlap = 110.625
+PHY-3002 : Step(156): len = 492356, overlap = 109.031
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.011496s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (135.9%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 653072, over cnt = 1435(4%), over = 5959, worst = 27
+PHY-1001 : End global iterations;  0.806463s wall, 0.984375s user + 0.062500s system = 1.046875s CPU (129.8%)
+
+PHY-1001 : Congestion index: top1 = 71.96, top5 = 54.97, top10 = 47.32, top15 = 42.67.
+PHY-3001 : End congestion estimation;  1.007942s wall, 1.171875s user + 0.078125s system = 1.250000s CPU (124.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.864550s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.37076e-05
+PHY-3002 : Step(157): len = 589556, overlap = 53.375
+PHY-3002 : Step(158): len = 605939, overlap = 50.125
+PHY-3002 : Step(159): len = 589094, overlap = 49.3125
+PHY-3002 : Step(160): len = 582002, overlap = 47.75
+PHY-3002 : Step(161): len = 578806, overlap = 45.375
+PHY-3002 : Step(162): len = 571946, overlap = 46.25
+PHY-3002 : Step(163): len = 570428, overlap = 42.5625
+PHY-3002 : Step(164): len = 565957, overlap = 38.875
+PHY-3002 : Step(165): len = 562761, overlap = 35.9062
+PHY-3002 : Step(166): len = 559228, overlap = 32.5938
+PHY-3002 : Step(167): len = 557229, overlap = 31.7812
+PHY-3002 : Step(168): len = 554764, overlap = 32.5938
+PHY-3002 : Step(169): len = 552917, overlap = 30.6875
+PHY-3002 : Step(170): len = 551461, overlap = 28.4688
+PHY-3002 : Step(171): len = 550620, overlap = 31.3125
+PHY-3002 : Step(172): len = 548677, overlap = 33.5
+PHY-3002 : Step(173): len = 548135, overlap = 32.125
+PHY-3002 : Step(174): len = 546129, overlap = 33.9688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000187415
+PHY-3002 : Step(175): len = 550573, overlap = 32.1875
+PHY-3002 : Step(176): len = 552391, overlap = 31.7812
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000365946
+PHY-3002 : Step(177): len = 560881, overlap = 27.9688
+PHY-3002 : Step(178): len = 571799, overlap = 27.6875
+PHY-3002 : Step(179): len = 583255, overlap = 27.4688
+PHY-3002 : Step(180): len = 585864, overlap = 27.8438
+PHY-3002 : Step(181): len = 587586, overlap = 30.3438
+PHY-3002 : Step(182): len = 585371, overlap = 32.1562
+PHY-3002 : Step(183): len = 585811, overlap = 34.125
+PHY-3002 : Step(184): len = 585684, overlap = 34.1562
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 93/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 676392, over cnt = 2507(7%), over = 10316, worst = 35
+PHY-1001 : End global iterations;  1.544961s wall, 2.109375s user + 0.031250s system = 2.140625s CPU (138.6%)
+
+PHY-1001 : Congestion index: top1 = 70.82, top5 = 59.66, top10 = 53.61, top15 = 49.30.
+PHY-3001 : End congestion estimation;  1.815080s wall, 2.375000s user + 0.031250s system = 2.406250s CPU (132.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.906248s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.74689e-05
+PHY-3002 : Step(185): len = 581976, overlap = 247.844
+PHY-3002 : Step(186): len = 585602, overlap = 212.656
+PHY-3002 : Step(187): len = 575962, overlap = 192.281
+PHY-3002 : Step(188): len = 572852, overlap = 179.312
+PHY-3002 : Step(189): len = 566489, overlap = 169.719
+PHY-3002 : Step(190): len = 562779, overlap = 160.656
+PHY-3002 : Step(191): len = 559253, overlap = 162.438
+PHY-3002 : Step(192): len = 556871, overlap = 155.219
+PHY-3002 : Step(193): len = 553244, overlap = 159.906
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000174938
+PHY-3002 : Step(194): len = 554685, overlap = 153.5
+PHY-3002 : Step(195): len = 556218, overlap = 147.938
+PHY-3002 : Step(196): len = 560449, overlap = 142.719
+PHY-3002 : Step(197): len = 562462, overlap = 140.625
+PHY-3002 : Step(198): len = 561120, overlap = 144.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000349876
+PHY-3002 : Step(199): len = 567210, overlap = 138.281
+PHY-3002 : Step(200): len = 571179, overlap = 134.781
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85541, tnet num: 20220, tinst num: 17831, tnode num: 115735, tedge num: 137330.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.453633s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (100.0%)
+
+RUN-1004 : used memory is 582 MB, reserved memory is 564 MB, peak memory is 719 MB
+OPT-1001 : Total overflow 495.47 peak overflow 4.53
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1015/20398.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 667072, over cnt = 2764(7%), over = 9761, worst = 28
+PHY-1001 : End global iterations;  1.094669s wall, 1.546875s user + 0.062500s system = 1.609375s CPU (147.0%)
+
+PHY-1001 : Congestion index: top1 = 66.06, top5 = 54.46, top10 = 49.07, top15 = 45.54.
+PHY-1001 : End incremental global routing;  1.419213s wall, 1.875000s user + 0.062500s system = 1.937500s CPU (136.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20220 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.944403s wall, 0.937500s user + 0.015625s system = 0.953125s CPU (100.9%)
+
+OPT-1001 : 45 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17701 has valid locations, 370 needs to be replaced
+PHY-3001 : design contains 18156 instances, 7623 luts, 9318 seqs, 1069 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6102 pins
+PHY-3001 : Found 1235 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 594632
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16052/20723.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 684184, over cnt = 2833(8%), over = 9925, worst = 25
+PHY-1001 : End global iterations;  0.250282s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (118.6%)
+
+PHY-1001 : Congestion index: top1 = 66.53, top5 = 54.77, top10 = 49.34, top15 = 45.89.
+PHY-3001 : End congestion estimation;  0.507252s wall, 0.562500s user + 0.000000s system = 0.562500s CPU (110.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 86929, tnet num: 20545, tinst num: 18156, tnode num: 117863, tedge num: 139456.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.469156s wall, 1.390625s user + 0.078125s system = 1.468750s CPU (100.0%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 616 MB, peak memory is 724 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20545 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.459218s wall, 2.359375s user + 0.093750s system = 2.453125s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(201): len = 593740, overlap = 0.1875
+PHY-3002 : Step(202): len = 593826, overlap = 0.1875
+PHY-3002 : Step(203): len = 593568, overlap = 0.25
+PHY-3002 : Step(204): len = 593734, overlap = 0.25
+PHY-3002 : Step(205): len = 594039, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16087/20723.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 678968, over cnt = 2824(8%), over = 10062, worst = 26
+PHY-1001 : End global iterations;  0.213709s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (117.0%)
+
+PHY-1001 : Congestion index: top1 = 67.28, top5 = 55.43, top10 = 49.82, top15 = 46.26.
+PHY-3001 : End congestion estimation;  0.467013s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (107.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20545 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.981819s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000182908
+PHY-3002 : Step(206): len = 593923, overlap = 138.438
+PHY-3002 : Step(207): len = 594189, overlap = 138
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000352942
+PHY-3002 : Step(208): len = 594306, overlap = 138.844
+PHY-3002 : Step(209): len = 595046, overlap = 138.844
+PHY-3001 : Final: Len = 595046, Over = 138.844
+PHY-3001 : End incremental placement;  5.109924s wall, 5.250000s user + 0.312500s system = 5.562500s CPU (108.9%)
+
+OPT-1001 : Total overflow 503.50 peak overflow 4.53
+OPT-1001 : End high-fanout net optimization;  8.036400s wall, 8.687500s user + 0.390625s system = 9.078125s CPU (113.0%)
+
+OPT-1001 : Current memory(MB): used = 727, reserve = 713, peak = 743.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16127/20723.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 682552, over cnt = 2790(7%), over = 9261, worst = 24
+PHY-1002 : len = 721168, over cnt = 2120(6%), over = 5532, worst = 22
+PHY-1002 : len = 769416, over cnt = 794(2%), over = 1798, worst = 21
+PHY-1002 : len = 787464, over cnt = 368(1%), over = 690, worst = 15
+PHY-1002 : len = 800088, over cnt = 16(0%), over = 18, worst = 2
+PHY-1001 : End global iterations;  1.672840s wall, 2.250000s user + 0.015625s system = 2.265625s CPU (135.4%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 49.37, top10 = 45.97, top15 = 43.74.
+OPT-1001 : End congestion update;  1.946905s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (130.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20545 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.826813s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (100.2%)
+
+OPT-0007 : Start: WNS -4469 TNS -2413131 NUM_FEPS 963
+OPT-0007 : Iter 1: improved WNS -4369 TNS -2414033 NUM_FEPS 963 with 130 cells processed and 2500 slack improved
+OPT-0007 : Iter 2: improved WNS -4319 TNS -2409091 NUM_FEPS 963 with 45 cells processed and 700 slack improved
+OPT-0007 : Iter 3: improved WNS -4319 TNS -2408991 NUM_FEPS 963 with 22 cells processed and 416 slack improved
+OPT-0007 : Iter 4: improved WNS -4319 TNS -2406433 NUM_FEPS 963 with 4 cells processed and 150 slack improved
+OPT-0007 : Iter 5: improved WNS -4319 TNS -2377149 NUM_FEPS 963 with 1 cells processed and 350 slack improved
+OPT-1001 : End bottleneck based optimization;  3.407527s wall, 3.968750s user + 0.031250s system = 4.000000s CPU (117.4%)
+
+OPT-1001 : Current memory(MB): used = 702, reserve = 687, peak = 743.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16321/20724.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 803176, over cnt = 185(0%), over = 352, worst = 8
+PHY-1002 : len = 804528, over cnt = 121(0%), over = 168, worst = 6
+PHY-1002 : len = 805696, over cnt = 65(0%), over = 83, worst = 4
+PHY-1002 : len = 806104, over cnt = 53(0%), over = 60, worst = 3
+PHY-1002 : len = 807544, over cnt = 7(0%), over = 9, worst = 2
+PHY-1001 : End global iterations;  0.731938s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (113.1%)
+
+PHY-1001 : Congestion index: top1 = 56.96, top5 = 49.47, top10 = 46.18, top15 = 43.99.
+OPT-1001 : End congestion update;  0.993371s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (108.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20546 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.813318s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.9%)
+
+OPT-0007 : Start: WNS -4319 TNS -2377149 NUM_FEPS 963
+OPT-0007 : Iter 1: improved WNS -4219 TNS -2379279 NUM_FEPS 963 with 54 cells processed and 3000 slack improved
+OPT-0007 : Iter 2: improved WNS -4219 TNS -2379279 NUM_FEPS 963 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.981538s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (104.9%)
+
+OPT-1001 : Current memory(MB): used = 709, reserve = 695, peak = 743.
+OPT-1001 : End physical optimization;  15.189874s wall, 16.468750s user + 0.453125s system = 16.921875s CPU (111.4%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7623 LUT to BLE ...
+SYN-4008 : Packed 7623 LUT and 3145 SEQ to BLE.
+SYN-4003 : Packing 6174 remaining SEQ's ...
+SYN-4005 : Packed 3575 SEQ with LUT/SLICE
+SYN-4006 : 1200 single LUT's are left
+SYN-4006 : 2599 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10222/14035 primitive instances ...
+PHY-3001 : End packing;  1.656585s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7004 instances
+RUN-1001 : 3428 mslices, 3428 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17699 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 10004 nets have 2 pins
+RUN-1001 : 5787 nets have [3 - 5] pins
+RUN-1001 : 1180 nets have [6 - 10] pins
+RUN-1001 : 354 nets have [11 - 20] pins
+RUN-1001 : 341 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 7002 instances, 6856 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3612 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : After packing: Len = 606029, Over = 322.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7593/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 756208, over cnt = 1794(5%), over = 2930, worst = 9
+PHY-1002 : len = 763704, over cnt = 1121(3%), over = 1565, worst = 7
+PHY-1002 : len = 775168, over cnt = 424(1%), over = 579, worst = 6
+PHY-1002 : len = 781536, over cnt = 125(0%), over = 160, worst = 6
+PHY-1002 : len = 784472, over cnt = 10(0%), over = 13, worst = 2
+PHY-1001 : End global iterations;  1.561049s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (138.1%)
+
+PHY-1001 : Congestion index: top1 = 59.27, top5 = 50.70, top10 = 46.35, top15 = 43.61.
+PHY-3001 : End congestion estimation;  1.949049s wall, 2.515625s user + 0.015625s system = 2.531250s CPU (129.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75033, tnet num: 17521, tinst num: 7002, tnode num: 97782, tedge num: 126034.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.668295s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.2%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 616 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.546917s wall, 2.500000s user + 0.046875s system = 2.546875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 3.90452e-05
+PHY-3002 : Step(210): len = 592648, overlap = 321.5
+PHY-3002 : Step(211): len = 585869, overlap = 316.75
+PHY-3002 : Step(212): len = 582312, overlap = 324.25
+PHY-3002 : Step(213): len = 578831, overlap = 339.5
+PHY-3002 : Step(214): len = 577343, overlap = 342.25
+PHY-3002 : Step(215): len = 574892, overlap = 341.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 7.80905e-05
+PHY-3002 : Step(216): len = 578598, overlap = 332
+PHY-3002 : Step(217): len = 583728, overlap = 323
+PHY-3002 : Step(218): len = 583362, overlap = 322
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000156181
+PHY-3002 : Step(219): len = 593148, overlap = 313
+PHY-3002 : Step(220): len = 600888, overlap = 311.25
+PHY-3002 : Step(221): len = 599677, overlap = 311.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000312362
+PHY-3002 : Step(222): len = 607289, overlap = 306.25
+PHY-3002 : Step(223): len = 617874, overlap = 292.5
+PHY-3002 : Step(224): len = 618147, overlap = 283.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.368711s wall, 0.390625s user + 0.531250s system = 0.921875s CPU (250.0%)
+
+PHY-3001 : Trial Legalized: Len = 722164
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 738/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 841064, over cnt = 2741(7%), over = 4739, worst = 7
+PHY-1002 : len = 858088, over cnt = 1788(5%), over = 2686, worst = 7
+PHY-1002 : len = 875048, over cnt = 909(2%), over = 1321, worst = 6
+PHY-1002 : len = 884320, over cnt = 512(1%), over = 749, worst = 6
+PHY-1002 : len = 898072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.001166s wall, 4.140625s user + 0.046875s system = 4.187500s CPU (139.5%)
+
+PHY-1001 : Congestion index: top1 = 55.65, top5 = 50.19, top10 = 47.21, top15 = 45.22.
+PHY-3001 : End congestion estimation;  3.476277s wall, 4.609375s user + 0.062500s system = 4.671875s CPU (134.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.884199s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000194022
+PHY-3002 : Step(225): len = 675959, overlap = 83.25
+PHY-3002 : Step(226): len = 652337, overlap = 126.5
+PHY-3002 : Step(227): len = 635803, overlap = 171.75
+PHY-3002 : Step(228): len = 628106, overlap = 199.25
+PHY-3002 : Step(229): len = 623246, overlap = 217
+PHY-3002 : Step(230): len = 620945, overlap = 227.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000388045
+PHY-3002 : Step(231): len = 625635, overlap = 227.75
+PHY-3002 : Step(232): len = 631101, overlap = 225
+PHY-3002 : Step(233): len = 630985, overlap = 224.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000725071
+PHY-3002 : Step(234): len = 635137, overlap = 223.75
+PHY-3002 : Step(235): len = 645320, overlap = 220.5
+PHY-3002 : Step(236): len = 649222, overlap = 221.25
+PHY-3002 : Step(237): len = 650620, overlap = 216.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.036233s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (129.4%)
+
+PHY-3001 : Legalized: Len = 695788, Over = 0
+PHY-3001 : Spreading special nets. 517 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.122069s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (102.4%)
+
+PHY-3001 : 764 instances has been re-located, deltaX = 322, deltaY = 457, maxDist = 4.
+PHY-3001 : Final: Len = 708232, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75033, tnet num: 17521, tinst num: 7005, tnode num: 97782, tedge num: 126034.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  2.046354s wall, 2.031250s user + 0.015625s system = 2.046875s CPU (100.0%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 614 MB, peak memory is 743 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3817/17699.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 838152, over cnt = 2488(7%), over = 4153, worst = 7
+PHY-1002 : len = 852320, over cnt = 1525(4%), over = 2246, worst = 6
+PHY-1002 : len = 864976, over cnt = 891(2%), over = 1286, worst = 6
+PHY-1002 : len = 873496, over cnt = 460(1%), over = 726, worst = 6
+PHY-1002 : len = 884968, over cnt = 48(0%), over = 87, worst = 6
+PHY-1001 : End global iterations;  1.850168s wall, 2.921875s user + 0.078125s system = 3.000000s CPU (162.1%)
+
+PHY-1001 : Congestion index: top1 = 55.78, top5 = 49.46, top10 = 46.49, top15 = 44.51.
+PHY-1001 : End incremental global routing;  2.247192s wall, 3.296875s user + 0.078125s system = 3.375000s CPU (150.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17521 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.912424s wall, 0.890625s user + 0.031250s system = 0.921875s CPU (101.0%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6911 has valid locations, 33 needs to be replaced
+PHY-3001 : design contains 7032 instances, 6883 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3696 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 713491
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16035/17730.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 892472, over cnt = 147(0%), over = 205, worst = 6
+PHY-1002 : len = 893064, over cnt = 79(0%), over = 85, worst = 2
+PHY-1002 : len = 893648, over cnt = 30(0%), over = 31, worst = 2
+PHY-1002 : len = 894072, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 894104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.858388s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (109.2%)
+
+PHY-1001 : Congestion index: top1 = 55.82, top5 = 49.63, top10 = 46.63, top15 = 44.65.
+PHY-3001 : End congestion estimation;  1.170701s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (106.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75327, tnet num: 17552, tinst num: 7032, tnode num: 98161, tedge num: 126407.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.908533s wall, 1.875000s user + 0.031250s system = 1.906250s CPU (99.9%)
+
+RUN-1004 : used memory is 677 MB, reserved memory is 676 MB, peak memory is 743 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17552 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.837977s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(238): len = 712038, overlap = 0
+PHY-3002 : Step(239): len = 711401, overlap = 0.25
+PHY-3002 : Step(240): len = 711136, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16017/17730.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 889256, over cnt = 95(0%), over = 126, worst = 6
+PHY-1002 : len = 889608, over cnt = 40(0%), over = 42, worst = 2
+PHY-1002 : len = 890016, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 890112, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 890144, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.838940s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (104.3%)
+
+PHY-1001 : Congestion index: top1 = 55.88, top5 = 49.49, top10 = 46.59, top15 = 44.64.
+PHY-3001 : End congestion estimation;  1.154330s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (101.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17552 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.888333s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171639
+PHY-3002 : Step(241): len = 711098, overlap = 1.75
+PHY-3002 : Step(242): len = 711094, overlap = 3.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.006034s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 711191, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.065832s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.9%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 4, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 711151, Over = 0
+PHY-3001 : End incremental placement;  6.600275s wall, 6.859375s user + 0.093750s system = 6.953125s CPU (105.3%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.265698s wall, 11.656250s user + 0.203125s system = 11.859375s CPU (115.5%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 743, peak = 754.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16005/17730.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 890184, over cnt = 78(0%), over = 108, worst = 5
+PHY-1002 : len = 890392, over cnt = 31(0%), over = 31, worst = 1
+PHY-1002 : len = 890568, over cnt = 14(0%), over = 14, worst = 1
+PHY-1002 : len = 890584, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 890776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.789146s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (104.9%)
+
+PHY-1001 : Congestion index: top1 = 55.91, top5 = 49.54, top10 = 46.55, top15 = 44.59.
+OPT-1001 : End congestion update;  1.110128s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17552 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.735647s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.8%)
+
+OPT-0007 : Start: WNS -4045 TNS -2205762 NUM_FEPS 894
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6944 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7032 instances, 6883 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3696 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 711138, Over = 0
+PHY-3001 : Spreading special nets. 7 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061113s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.3%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 1, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 711386, Over = 0
+PHY-3001 : End incremental legalization;  0.389392s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.3%)
+
+OPT-0007 : Iter 1: improved WNS -3845 TNS -2186865 NUM_FEPS 894 with 29 cells processed and 4398 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6944 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7032 instances, 6883 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3696 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 711216, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060141s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.9%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 5, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 711638, Over = 0
+PHY-3001 : End incremental legalization;  0.383757s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (101.8%)
+
+OPT-0007 : Iter 2: improved WNS -3722 TNS -2181349 NUM_FEPS 894 with 29 cells processed and 3333 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6944 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7032 instances, 6883 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3696 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 711250, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062618s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 6, deltaY = 14, maxDist = 2.
+PHY-3001 : Final: Len = 711996, Over = 0
+PHY-3001 : End incremental legalization;  0.398110s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.1%)
+
+OPT-0007 : Iter 3: improved WNS -3722 TNS -2177014 NUM_FEPS 894 with 26 cells processed and 1961 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6944 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7032 instances, 6883 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3696 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 711890, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.066680s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (117.2%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 3, deltaY = 9, maxDist = 2.
+PHY-3001 : Final: Len = 712336, Over = 0
+PHY-3001 : End incremental legalization;  0.405152s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (96.4%)
+
+OPT-0007 : Iter 4: improved WNS -3722 TNS -2178893 NUM_FEPS 894 with 23 cells processed and 1641 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6944 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7032 instances, 6883 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3696 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 711854, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059276s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.4%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 3, deltaY = 10, maxDist = 2.
+PHY-3001 : Final: Len = 712236, Over = 0
+PHY-3001 : End incremental legalization;  0.420244s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.4%)
+
+OPT-0007 : Iter 5: improved WNS -3722 TNS -2176792 NUM_FEPS 894 with 17 cells processed and 844 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6950 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7038 instances, 6889 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3699 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 712582, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062740s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.6%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 0, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 712608, Over = 0
+PHY-3001 : End incremental legalization;  0.389196s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (124.5%)
+
+OPT-0007 : Iter 6: improved WNS -3795 TNS -2179038 NUM_FEPS 894 with 6 cells processed and 616 slack improved
+OPT-1001 : End bottleneck based optimization;  5.412788s wall, 5.750000s user + 0.000000s system = 5.750000s CPU (106.2%)
+
+OPT-1001 : Current memory(MB): used = 750, reserve = 743, peak = 754.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15642/17732.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 891312, over cnt = 340(0%), over = 458, worst = 5
+PHY-1002 : len = 891880, over cnt = 198(0%), over = 228, worst = 3
+PHY-1002 : len = 893408, over cnt = 98(0%), over = 108, worst = 3
+PHY-1002 : len = 894272, over cnt = 53(0%), over = 58, worst = 3
+PHY-1002 : len = 895032, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations;  0.880800s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (106.4%)
+
+PHY-1001 : Congestion index: top1 = 56.10, top5 = 49.90, top10 = 46.81, top15 = 44.83.
+OPT-1001 : End congestion update;  1.214230s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (105.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17552 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.752352s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.7%)
+
+OPT-0007 : Start: WNS -3945 TNS -2186244 NUM_FEPS 894
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6950 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7038 instances, 6889 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3699 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 713632, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062114s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.6%)
+
+PHY-3001 : 16 instances has been re-located, deltaX = 11, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 713950, Over = 0
+PHY-3001 : End incremental legalization;  0.416448s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.3%)
+
+OPT-0007 : Iter 1: improved WNS -3845 TNS -2180059 NUM_FEPS 894 with 41 cells processed and 3006 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6950 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7038 instances, 6889 slices, 222 macros(1069 instances: 696 mslices 373 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3699 pins
+PHY-3001 : Found 494 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 714184, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.067022s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (93.3%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 5, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 714322, Over = 0
+PHY-3001 : End incremental legalization;  0.424469s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.4%)
+
+OPT-0007 : Iter 2: improved WNS -3845 TNS -2177583 NUM_FEPS 894 with 20 cells processed and 1449 slack improved
+OPT-0007 : Iter 3: improved WNS -3845 TNS -2177583 NUM_FEPS 894 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  3.140912s wall, 3.203125s user + 0.000000s system = 3.203125s CPU (102.0%)
+
+OPT-1001 : Current memory(MB): used = 750, reserve = 744, peak = 754.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17552 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.769957s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15783/17732.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 896256, over cnt = 189(0%), over = 256, worst = 5
+PHY-1002 : len = 895856, over cnt = 125(0%), over = 139, worst = 4
+PHY-1002 : len = 897080, over cnt = 25(0%), over = 27, worst = 2
+PHY-1002 : len = 897448, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 897552, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.875619s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (108.9%)
+
+PHY-1001 : Congestion index: top1 = 55.73, top5 = 49.74, top10 = 46.75, top15 = 44.79.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17552 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.746562s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -3845 TNS -2181547 NUM_FEPS 894
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 55.241379
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -3845ps with logic level 6 
+RUN-1001 :       #2 path slack -3793ps with logic level 5 
+RUN-1001 :       #3 path slack -3793ps with logic level 5 
+RUN-1001 :       #4 path slack -3772ps with logic level 5 
+RUN-1001 :       #5 path slack -3767ps with logic level 6 
+RUN-1001 :       #6 path slack -3767ps with logic level 6 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17732 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17732 nets
+OPT-1001 : End physical optimization;  23.958819s wall, 25.890625s user + 0.250000s system = 26.140625s CPU (109.1%)
+
+RUN-1003 : finish command "place" in  66.635432s wall, 91.468750s user + 5.250000s system = 96.718750s CPU (145.1%)
+
+RUN-1004 : used memory is 616 MB, reserved memory is 613 MB, peak memory is 754 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.715059s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (174.0%)
+
+RUN-1004 : used memory is 617 MB, reserved memory is 615 MB, peak memory is 754 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7040 instances
+RUN-1001 : 3441 mslices, 3448 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17732 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 22 nets with only 1 pin.
+RUN-1001 : 10002 nets have 2 pins
+RUN-1001 : 5792 nets have [3 - 5] pins
+RUN-1001 : 1185 nets have [6 - 10] pins
+RUN-1001 : 362 nets have [11 - 20] pins
+RUN-1001 : 361 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75401, tnet num: 17554, tinst num: 7038, tnode num: 98255, tedge num: 126496.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.652639s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.3%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 598 MB, peak memory is 754 MB
+PHY-1001 : 3441 mslices, 3448 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17554 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_tx_data_1d[3] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 821408, over cnt = 2638(7%), over = 4587, worst = 8
+PHY-1002 : len = 838280, over cnt = 1731(4%), over = 2683, worst = 8
+PHY-1002 : len = 861096, over cnt = 635(1%), over = 961, worst = 6
+PHY-1002 : len = 876264, over cnt = 10(0%), over = 12, worst = 2
+PHY-1002 : len = 876896, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.058400s wall, 4.046875s user + 0.046875s system = 4.093750s CPU (133.9%)
+
+PHY-1001 : Congestion index: top1 = 54.68, top5 = 48.98, top10 = 46.01, top15 = 44.09.
+PHY-1001 : End global routing;  3.393165s wall, 4.375000s user + 0.062500s system = 4.437500s CPU (130.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 725, reserve = 723, peak = 754.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1001, reserve = 997, peak = 1001.
+PHY-1001 : End build detailed router design. 3.981471s wall, 3.937500s user + 0.046875s system = 3.984375s CPU (100.1%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267336, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.057557s wall, 5.046875s user + 0.000000s system = 5.046875s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267392, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.487905s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.3%)
+
+PHY-1001 : Current memory(MB): used = 1037, reserve = 1033, peak = 1037.
+PHY-1001 : End phase 1; 5.557530s wall, 5.546875s user + 0.000000s system = 5.546875s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 39% nets.
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 55% nets.
+PHY-1001 : Routed 70% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.3367e+06, over cnt = 1944(0%), over = 1951, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1054, reserve = 1050, peak = 1054.
+PHY-1001 : End initial routed; 26.710772s wall, 55.875000s user + 0.171875s system = 56.046875s CPU (209.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1916/16659(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.134   |  -3406.722  |  900  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.353303s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1068, reserve = 1065, peak = 1068.
+PHY-1001 : End phase 2; 30.064153s wall, 59.218750s user + 0.171875s system = 59.390625s CPU (197.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 135 pins with SWNS -5.876ns STNS -3386.362ns FEP 898.
+PHY-1001 : End OPT Iter 1; 0.725702s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.0%)
+
+PHY-1022 : len = 2.33732e+06, over cnt = 2063(0%), over = 2071, worst = 2, crit = 1
+PHY-1001 : End optimize timing; 0.985514s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.30002e+06, over cnt = 787(0%), over = 789, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 2.030007s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (166.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.29454e+06, over cnt = 160(0%), over = 160, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 1.120462s wall, 1.531250s user + 0.015625s system = 1.546875s CPU (138.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.29513e+06, over cnt = 37(0%), over = 37, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.641887s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (121.7%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.29554e+06, over cnt = 11(0%), over = 11, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.361965s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (120.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.29567e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.404736s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (104.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.2957e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.596985s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (99.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.2957e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.748823s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.29566e+06, over cnt = 3(0%), over = 3, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.181456s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.7%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.29571e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.182007s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (94.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1916/16659(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.055   |  -3397.067  |  898  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.388537s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 670 feed throughs used by 501 nets
+PHY-1001 : End commit to database; 2.275605s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1172, reserve = 1171, peak = 1172.
+PHY-1001 : End phase 3; 13.337003s wall, 15.312500s user + 0.031250s system = 15.343750s CPU (115.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 61 pins with SWNS -5.864ns STNS -3389.463ns FEP 898.
+PHY-1001 : End OPT Iter 1; 0.498690s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (100.3%)
+
+PHY-1022 : len = 2.29578e+06, over cnt = 30(0%), over = 30, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.736491s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.8%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-5.864ns, -3389.463ns, 898}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29554e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 0.189429s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (99.0%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.29552e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 2; 0.171819s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (100.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1916/16659(11%) critical/total net(s).
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |   TNS(ns)   |  FEP  
+RUN-1001 : ----------------------------------------
+RUN-1001 :   Setup  |  -6.094   |  -3395.686  |  898  
+RUN-1001 :   Hold   |   0.067   |    0.000    |   0   
+RUN-1001 : ----------------------------------------
+PHY-1001 : End update timing; 3.345825s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (100.4%)
+
+PHY-1001 : Current memory(MB): used = 1180, reserve = 1180, peak = 1180.
+PHY-1001 : End phase 4; 4.493139s wall, 4.500000s user + 0.000000s system = 4.500000s CPU (100.2%)
+
+PHY-1003 : Routed, final wirelength = 2.29552e+06
+PHY-1001 : Current memory(MB): used = 1180, reserve = 1180, peak = 1180.
+PHY-1001 : End export database. 0.063204s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (123.6%)
+
+PHY-1001 : End detail routing;  57.898307s wall, 88.968750s user + 0.265625s system = 89.234375s CPU (154.1%)
+
+RUN-1003 : finish command "route" in  64.058121s wall, 96.093750s user + 0.328125s system = 96.421875s CPU (150.5%)
+
+RUN-1004 : used memory is 1105 MB, reserved memory is 1107 MB, peak memory is 1180 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10438   out of  19600   53.26%
+#reg                     9467   out of  19600   48.30%
+#le                     12956
+  #lut only              3489   out of  12956   26.93%
+  #reg only              2518   out of  12956   19.44%
+  #lut&reg               6949   out of  12956   53.64%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                                                                                          Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                                                                                            1804
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                                                                                       1428
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                                                                                      1425
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                                                                                            958
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0                                                                 139
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                                                                                       71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                                                                                      69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                                                                                            24
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                                                                                            4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_3d_reg_syn_5.f0    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_193.f1                                                                 3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                                                                                           1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                                                                                           1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                                                                                           1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                                                                                            1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P170       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P32        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12956  |9417    |1021    |9497    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |518    |413     |23      |420     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |103    |88      |4       |88      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |36     |36      |0       |20      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10     |10      |0       |9       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |796    |374     |96      |595     |0       |0       |
+|    u_ADconfig                |AD_config            |196    |132     |25      |149     |0       |0       |
+|    u_gen_sp                  |gen_sp               |284    |175     |71      |130     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |741    |409     |96      |541     |0       |0       |
+|    u_ADconfig                |AD_config            |160    |109     |25      |113     |0       |0       |
+|    u_gen_sp                  |gen_sp               |273    |181     |71      |120     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3170   |2487    |303     |2158    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |165    |99      |14      |131     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2990   |2375    |289     |2012    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |7      |4       |0       |7       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |7      |4       |0       |7       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2565   |2072    |253     |1656    |22      |1       |
+|        channelPart           |channel_part_8478    |152    |146     |3       |140     |0       |0       |
+|        fifo_adc              |fifo_adc             |57     |48      |9       |41      |0       |1       |
+|        ram_switch            |ram_switch           |2055   |1637    |197     |1251    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |283    |250     |27      |143     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |5       |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |34     |31      |3       |16      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |32     |29      |3       |18      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |32     |29      |3       |16      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
+|          insert              |insert               |955    |584     |170     |653     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |817    |803     |0       |455     |0       |0       |
+|        read_ram_i            |read_ram             |258    |209     |44      |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |210    |170     |40      |146     |0       |0       |
+|          read_ram_data       |read_ram_data        |46     |37      |4       |33      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |315    |211     |36      |273     |3       |0       |
+|        u0_soft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3585   |2919    |340     |2059    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |181    |106     |17      |142     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |3372   |2786    |323     |1885    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |6       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2941   |2430    |281     |1547    |22      |0       |
+|        channelPart           |channel_part_8478    |261    |251     |3       |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |42      |0       |0       |
+|        ram_switch            |ram_switch           |2249   |1862    |197     |1119    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |257    |224     |27      |124     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |5       |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |31     |28      |3       |16      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|          insert              |insert               |919    |565     |170     |617     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1073   |1073    |0       |378     |0       |0       |
+|        read_ram_i            |read_ram_rev         |336    |242     |72      |206     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |275    |199     |64      |164     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |61     |43      |8       |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9940  
+    #2         2       3842  
+    #3         3       1401  
+    #4         4       546   
+    #5        5-10     1250  
+    #6       11-50     626   
+    #7       51-100     29   
+    #8        >500      1    
+  Average     2.95           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.102710s wall, 3.625000s user + 0.000000s system = 3.625000s CPU (172.4%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1109 MB, peak memory is 1180 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75401, tnet num: 17554, tinst num: 7038, tnode num: 98255, tedge num: 126496.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.650518s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.3%)
+
+RUN-1004 : used memory is 1110 MB, reserved memory is 1113 MB, peak memory is 1180 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17554 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.534968s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (99.8%)
+
+RUN-1004 : used memory is 1116 MB, reserved memory is 1117 MB, peak memory is 1180 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7038
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17732, pip num: 175480
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 670
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3265 valid insts, and 487038 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.849776s wall, 66.750000s user + 0.187500s system = 66.937500s CPU (679.6%)
+
+RUN-1004 : used memory is 1278 MB, reserved memory is 1273 MB, peak memory is 1393 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_134954.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_135811.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_135811.log
new file mode 100644
index 0000000..6eb6115
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_135811.log
@@ -0,0 +1,2221 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:58:11 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.388464s wall, 2.234375s user + 0.156250s system = 2.390625s CPU (100.1%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 314 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17697 instances
+RUN-0007 : 7426 luts, 9054 seqs, 698 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20265 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13364 nets have 2 pins
+RUN-1001 : 5431 nets have [3 - 5] pins
+RUN-1001 : 1059 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 174 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17695 instances, 7426 luts, 9054 seqs, 1069 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5933 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20087, tinst num: 17695, tnode num: 114795, tedge num: 135900.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.148108s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (99.3%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 513 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.933193s wall, 1.890625s user + 0.031250s system = 1.921875s CPU (99.4%)
+
+PHY-3001 : Found 1219 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.10638e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17695.
+PHY-3001 : Level 1 #clusters 2044.
+PHY-3001 : End clustering;  0.130434s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (119.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28789e+06, overlap = 488.125
+PHY-3002 : Step(2): len = 1.22021e+06, overlap = 512.406
+PHY-3002 : Step(3): len = 849375, overlap = 606.344
+PHY-3002 : Step(4): len = 799982, overlap = 632.562
+PHY-3002 : Step(5): len = 611191, overlap = 751.156
+PHY-3002 : Step(6): len = 519431, overlap = 835.688
+PHY-3002 : Step(7): len = 462360, overlap = 885.5
+PHY-3002 : Step(8): len = 428595, overlap = 938.75
+PHY-3002 : Step(9): len = 388589, overlap = 1003.19
+PHY-3002 : Step(10): len = 349889, overlap = 1088.91
+PHY-3002 : Step(11): len = 323524, overlap = 1136.16
+PHY-3002 : Step(12): len = 290369, overlap = 1197.31
+PHY-3002 : Step(13): len = 266051, overlap = 1254.84
+PHY-3002 : Step(14): len = 243362, overlap = 1299.88
+PHY-3002 : Step(15): len = 224154, overlap = 1317.41
+PHY-3002 : Step(16): len = 209559, overlap = 1351
+PHY-3002 : Step(17): len = 192103, overlap = 1376.59
+PHY-3002 : Step(18): len = 177219, overlap = 1382.44
+PHY-3002 : Step(19): len = 161847, overlap = 1410.88
+PHY-3002 : Step(20): len = 152696, overlap = 1423.81
+PHY-3002 : Step(21): len = 139809, overlap = 1432.28
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.1389e-06
+PHY-3002 : Step(22): len = 139009, overlap = 1439.53
+PHY-3002 : Step(23): len = 168370, overlap = 1349.69
+PHY-3002 : Step(24): len = 174002, overlap = 1292.5
+PHY-3002 : Step(25): len = 182642, overlap = 1206.81
+PHY-3002 : Step(26): len = 184406, overlap = 1186.34
+PHY-3002 : Step(27): len = 184428, overlap = 1141.06
+PHY-3002 : Step(28): len = 181875, overlap = 1102.38
+PHY-3002 : Step(29): len = 182508, overlap = 1096.72
+PHY-3002 : Step(30): len = 182297, overlap = 1114.06
+PHY-3002 : Step(31): len = 181712, overlap = 1092.19
+PHY-3002 : Step(32): len = 179042, overlap = 1079.34
+PHY-3002 : Step(33): len = 176977, overlap = 1051.28
+PHY-3002 : Step(34): len = 175022, overlap = 1056.5
+PHY-3002 : Step(35): len = 175113, overlap = 1052.34
+PHY-3002 : Step(36): len = 173697, overlap = 1036.19
+PHY-3002 : Step(37): len = 172874, overlap = 1027.09
+PHY-3002 : Step(38): len = 171550, overlap = 1018.62
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.2778e-06
+PHY-3002 : Step(39): len = 174219, overlap = 1019
+PHY-3002 : Step(40): len = 183807, overlap = 1027.28
+PHY-3002 : Step(41): len = 184956, overlap = 991.625
+PHY-3002 : Step(42): len = 188705, overlap = 975.344
+PHY-3002 : Step(43): len = 191014, overlap = 964.75
+PHY-3002 : Step(44): len = 192598, overlap = 944.906
+PHY-3002 : Step(45): len = 192219, overlap = 935.438
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.55559e-06
+PHY-3002 : Step(46): len = 200566, overlap = 903.938
+PHY-3002 : Step(47): len = 218245, overlap = 848
+PHY-3002 : Step(48): len = 227815, overlap = 779.875
+PHY-3002 : Step(49): len = 234033, overlap = 735.156
+PHY-3002 : Step(50): len = 234657, overlap = 726.875
+PHY-3002 : Step(51): len = 235788, overlap = 751.688
+PHY-3002 : Step(52): len = 233178, overlap = 758.281
+PHY-3002 : Step(53): len = 232160, overlap = 752.156
+PHY-3002 : Step(54): len = 230526, overlap = 772.688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.11118e-06
+PHY-3002 : Step(55): len = 245653, overlap = 741.781
+PHY-3002 : Step(56): len = 266698, overlap = 655.062
+PHY-3002 : Step(57): len = 277902, overlap = 606.281
+PHY-3002 : Step(58): len = 286374, overlap = 588.312
+PHY-3002 : Step(59): len = 286593, overlap = 579.156
+PHY-3002 : Step(60): len = 282750, overlap = 588.531
+PHY-3002 : Step(61): len = 277859, overlap = 588.812
+PHY-3002 : Step(62): len = 275572, overlap = 577.531
+PHY-3002 : Step(63): len = 276579, overlap = 579.25
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.82224e-05
+PHY-3002 : Step(64): len = 293697, overlap = 547.281
+PHY-3002 : Step(65): len = 308424, overlap = 496.781
+PHY-3002 : Step(66): len = 317696, overlap = 454.469
+PHY-3002 : Step(67): len = 324239, overlap = 452.375
+PHY-3002 : Step(68): len = 322695, overlap = 448.156
+PHY-3002 : Step(69): len = 324572, overlap = 429.469
+PHY-3002 : Step(70): len = 321790, overlap = 418.906
+PHY-3002 : Step(71): len = 322737, overlap = 408.188
+PHY-3002 : Step(72): len = 321566, overlap = 380.938
+PHY-3002 : Step(73): len = 322866, overlap = 377.656
+PHY-3002 : Step(74): len = 321635, overlap = 374.531
+PHY-3002 : Step(75): len = 323882, overlap = 352.562
+PHY-3002 : Step(76): len = 322151, overlap = 359.844
+PHY-3002 : Step(77): len = 321864, overlap = 360
+PHY-3002 : Step(78): len = 321440, overlap = 364.781
+PHY-3002 : Step(79): len = 322211, overlap = 353.938
+PHY-3002 : Step(80): len = 321938, overlap = 353.531
+PHY-3002 : Step(81): len = 321984, overlap = 370.875
+PHY-3002 : Step(82): len = 320635, overlap = 372.031
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.64447e-05
+PHY-3002 : Step(83): len = 337274, overlap = 375.031
+PHY-3002 : Step(84): len = 350033, overlap = 340.906
+PHY-3002 : Step(85): len = 351276, overlap = 331.188
+PHY-3002 : Step(86): len = 351738, overlap = 319.156
+PHY-3002 : Step(87): len = 352003, overlap = 311.25
+PHY-3002 : Step(88): len = 354340, overlap = 302.062
+PHY-3002 : Step(89): len = 353233, overlap = 296.875
+PHY-3002 : Step(90): len = 355241, overlap = 295.812
+PHY-3002 : Step(91): len = 356552, overlap = 292.344
+PHY-3002 : Step(92): len = 357878, overlap = 300.688
+PHY-3002 : Step(93): len = 357196, overlap = 295.906
+PHY-3002 : Step(94): len = 357780, overlap = 305.406
+PHY-3002 : Step(95): len = 357854, overlap = 297.969
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.28895e-05
+PHY-3002 : Step(96): len = 375453, overlap = 283.781
+PHY-3002 : Step(97): len = 386420, overlap = 261.469
+PHY-3002 : Step(98): len = 385761, overlap = 233.688
+PHY-3002 : Step(99): len = 387091, overlap = 220.656
+PHY-3002 : Step(100): len = 391048, overlap = 221.969
+PHY-3002 : Step(101): len = 393536, overlap = 223.656
+PHY-3002 : Step(102): len = 389836, overlap = 218.688
+PHY-3002 : Step(103): len = 389834, overlap = 223.812
+PHY-3002 : Step(104): len = 392243, overlap = 228
+PHY-3002 : Step(105): len = 394899, overlap = 230.406
+PHY-3002 : Step(106): len = 392439, overlap = 234.375
+PHY-3002 : Step(107): len = 392178, overlap = 231.125
+PHY-3002 : Step(108): len = 393814, overlap = 233.938
+PHY-3002 : Step(109): len = 395616, overlap = 240.156
+PHY-3002 : Step(110): len = 392742, overlap = 248.156
+PHY-3002 : Step(111): len = 393326, overlap = 246.562
+PHY-3002 : Step(112): len = 394304, overlap = 240.562
+PHY-3002 : Step(113): len = 395156, overlap = 234.656
+PHY-3002 : Step(114): len = 393369, overlap = 248.188
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.00014328
+PHY-3002 : Step(115): len = 407207, overlap = 234
+PHY-3002 : Step(116): len = 416218, overlap = 224.75
+PHY-3002 : Step(117): len = 415344, overlap = 213.812
+PHY-3002 : Step(118): len = 416102, overlap = 206.406
+PHY-3002 : Step(119): len = 418235, overlap = 217.531
+PHY-3002 : Step(120): len = 420248, overlap = 205.125
+PHY-3002 : Step(121): len = 418489, overlap = 212.875
+PHY-3002 : Step(122): len = 419433, overlap = 215.844
+PHY-3002 : Step(123): len = 421445, overlap = 209.125
+PHY-3002 : Step(124): len = 423018, overlap = 198.75
+PHY-3002 : Step(125): len = 421924, overlap = 194.312
+PHY-3002 : Step(126): len = 422576, overlap = 194.625
+PHY-3002 : Step(127): len = 424371, overlap = 196.5
+PHY-3002 : Step(128): len = 425672, overlap = 195.031
+PHY-3002 : Step(129): len = 424331, overlap = 200.062
+PHY-3002 : Step(130): len = 424677, overlap = 199.812
+PHY-3002 : Step(131): len = 426392, overlap = 198.875
+PHY-3002 : Step(132): len = 427141, overlap = 197.656
+PHY-3002 : Step(133): len = 425632, overlap = 200.281
+PHY-3002 : Step(134): len = 425394, overlap = 199.688
+PHY-3002 : Step(135): len = 426627, overlap = 192.969
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000283603
+PHY-3002 : Step(136): len = 436889, overlap = 194.938
+PHY-3002 : Step(137): len = 444966, overlap = 199.281
+PHY-3002 : Step(138): len = 446102, overlap = 189.688
+PHY-3002 : Step(139): len = 448248, overlap = 189.844
+PHY-3002 : Step(140): len = 452450, overlap = 194.812
+PHY-3002 : Step(141): len = 456184, overlap = 192.969
+PHY-3002 : Step(142): len = 455197, overlap = 180.594
+PHY-3002 : Step(143): len = 456016, overlap = 181.156
+PHY-3002 : Step(144): len = 458890, overlap = 178.594
+PHY-3002 : Step(145): len = 460266, overlap = 177.594
+PHY-3002 : Step(146): len = 458499, overlap = 172.531
+PHY-3002 : Step(147): len = 458189, overlap = 168.906
+PHY-3002 : Step(148): len = 459670, overlap = 173.562
+PHY-3002 : Step(149): len = 460723, overlap = 168
+PHY-3002 : Step(150): len = 459300, overlap = 159.25
+PHY-3002 : Step(151): len = 459012, overlap = 157.312
+PHY-3002 : Step(152): len = 459794, overlap = 155.562
+PHY-3002 : Step(153): len = 460192, overlap = 151.719
+PHY-3002 : Step(154): len = 459170, overlap = 150.219
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000493629
+PHY-3002 : Step(155): len = 465110, overlap = 146.469
+PHY-3002 : Step(156): len = 468862, overlap = 148.438
+PHY-3002 : Step(157): len = 469358, overlap = 142.094
+PHY-3002 : Step(158): len = 470270, overlap = 140.125
+PHY-3002 : Step(159): len = 472982, overlap = 142.406
+PHY-3002 : Step(160): len = 475289, overlap = 148.812
+PHY-3002 : Step(161): len = 475892, overlap = 144.469
+PHY-3002 : Step(162): len = 476585, overlap = 143.656
+PHY-3002 : Step(163): len = 478476, overlap = 145.812
+PHY-3002 : Step(164): len = 479646, overlap = 144.031
+PHY-3002 : Step(165): len = 478836, overlap = 146.688
+PHY-3002 : Step(166): len = 478774, overlap = 146.438
+PHY-3002 : Step(167): len = 479876, overlap = 145.094
+PHY-3002 : Step(168): len = 480508, overlap = 144.125
+PHY-3002 : Step(169): len = 479819, overlap = 148
+PHY-3002 : Step(170): len = 479696, overlap = 145.344
+PHY-3002 : Step(171): len = 481180, overlap = 144
+PHY-3002 : Step(172): len = 483121, overlap = 141.781
+PHY-3002 : Step(173): len = 482324, overlap = 141.062
+PHY-3002 : Step(174): len = 482307, overlap = 141.375
+PHY-3002 : Step(175): len = 483157, overlap = 142.344
+PHY-3002 : Step(176): len = 483534, overlap = 142.969
+PHY-3002 : Step(177): len = 483281, overlap = 148.125
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.000838182
+PHY-3002 : Step(178): len = 486960, overlap = 142.125
+PHY-3002 : Step(179): len = 490806, overlap = 143.406
+PHY-3002 : Step(180): len = 492024, overlap = 143.969
+PHY-3002 : Step(181): len = 492656, overlap = 141.25
+PHY-3002 : Step(182): len = 494059, overlap = 139.25
+PHY-3002 : Step(183): len = 495037, overlap = 137.781
+PHY-3002 : Step(184): len = 495694, overlap = 137.062
+PHY-3002 : Step(185): len = 497156, overlap = 132.625
+PHY-3002 : Step(186): len = 498464, overlap = 131.312
+PHY-3002 : Step(187): len = 498966, overlap = 131.188
+PHY-3002 : Step(188): len = 499125, overlap = 129.281
+PHY-3002 : Step(189): len = 499944, overlap = 128.594
+PHY-3002 : Step(190): len = 500896, overlap = 127.688
+PHY-3002 : Step(191): len = 501098, overlap = 128.469
+PHY-3002 : Step(192): len = 501134, overlap = 128.344
+PHY-3002 : Step(193): len = 501897, overlap = 128.344
+PHY-3002 : Step(194): len = 502918, overlap = 128.406
+PHY-3002 : Step(195): len = 503394, overlap = 127.281
+PHY-3002 : Step(196): len = 503211, overlap = 130.719
+PHY-3002 : Step(197): len = 503452, overlap = 132.594
+PHY-3002 : Step(198): len = 504349, overlap = 129.375
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00155462
+PHY-3002 : Step(199): len = 507041, overlap = 129.438
+PHY-3002 : Step(200): len = 514862, overlap = 132.438
+PHY-3002 : Step(201): len = 518658, overlap = 131.156
+PHY-3002 : Step(202): len = 521297, overlap = 130.188
+PHY-3002 : Step(203): len = 521814, overlap = 129.188
+PHY-3002 : Step(204): len = 522138, overlap = 127.531
+PHY-3002 : Step(205): len = 522979, overlap = 128.5
+PHY-3002 : Step(206): len = 523862, overlap = 123.781
+PHY-3002 : Step(207): len = 524335, overlap = 128.406
+PHY-3002 : Step(208): len = 524873, overlap = 127.906
+PHY-3002 : Step(209): len = 525833, overlap = 127.531
+PHY-3002 : Step(210): len = 526105, overlap = 127.094
+PHY-3002 : Step(211): len = 525963, overlap = 127.094
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015158s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (103.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 718928, over cnt = 1600(4%), over = 7172, worst = 52
+PHY-1001 : End global iterations;  0.723714s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (114.4%)
+
+PHY-1001 : Congestion index: top1 = 79.98, top5 = 60.99, top10 = 51.88, top15 = 46.34.
+PHY-3001 : End congestion estimation;  0.966540s wall, 1.078125s user + 0.000000s system = 1.078125s CPU (111.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.861891s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000130656
+PHY-3002 : Step(212): len = 647836, overlap = 77.8438
+PHY-3002 : Step(213): len = 648122, overlap = 75.8125
+PHY-3002 : Step(214): len = 643512, overlap = 74.875
+PHY-3002 : Step(215): len = 639026, overlap = 74.0625
+PHY-3002 : Step(216): len = 637891, overlap = 72.0625
+PHY-3002 : Step(217): len = 637625, overlap = 65.125
+PHY-3002 : Step(218): len = 636107, overlap = 62.4375
+PHY-3002 : Step(219): len = 633295, overlap = 61.625
+PHY-3002 : Step(220): len = 631431, overlap = 61.5
+PHY-3002 : Step(221): len = 629025, overlap = 58.75
+PHY-3002 : Step(222): len = 627170, overlap = 59.4688
+PHY-3002 : Step(223): len = 625377, overlap = 53.9375
+PHY-3002 : Step(224): len = 623066, overlap = 50.7188
+PHY-3002 : Step(225): len = 621123, overlap = 51.4062
+PHY-3002 : Step(226): len = 620123, overlap = 47.2188
+PHY-3002 : Step(227): len = 619489, overlap = 46.4375
+PHY-3002 : Step(228): len = 617215, overlap = 45.6562
+PHY-3002 : Step(229): len = 614909, overlap = 41.7812
+PHY-3002 : Step(230): len = 613023, overlap = 40.6562
+PHY-3002 : Step(231): len = 610906, overlap = 41.4375
+PHY-3002 : Step(232): len = 608761, overlap = 40.9688
+PHY-3002 : Step(233): len = 607439, overlap = 39.0938
+PHY-3002 : Step(234): len = 605526, overlap = 39.0938
+PHY-3002 : Step(235): len = 604315, overlap = 37.2812
+PHY-3002 : Step(236): len = 602225, overlap = 38.125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000261312
+PHY-3002 : Step(237): len = 603484, overlap = 36.9688
+PHY-3002 : Step(238): len = 605504, overlap = 36.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 70/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 699144, over cnt = 2568(7%), over = 10863, worst = 67
+PHY-1001 : End global iterations;  1.755921s wall, 2.203125s user + 0.031250s system = 2.234375s CPU (127.2%)
+
+PHY-1001 : Congestion index: top1 = 79.09, top5 = 61.97, top10 = 54.59, top15 = 49.89.
+PHY-3001 : End congestion estimation;  2.017279s wall, 2.453125s user + 0.046875s system = 2.500000s CPU (123.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.877065s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.37734e-05
+PHY-3002 : Step(239): len = 603410, overlap = 291.375
+PHY-3002 : Step(240): len = 606743, overlap = 230.844
+PHY-3002 : Step(241): len = 606292, overlap = 220.906
+PHY-3002 : Step(242): len = 602804, overlap = 212.469
+PHY-3002 : Step(243): len = 600821, overlap = 192.406
+PHY-3002 : Step(244): len = 600122, overlap = 177.969
+PHY-3002 : Step(245): len = 596528, overlap = 167
+PHY-3002 : Step(246): len = 594135, overlap = 163.031
+PHY-3002 : Step(247): len = 593060, overlap = 159.625
+PHY-3002 : Step(248): len = 591427, overlap = 157.844
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000187547
+PHY-3002 : Step(249): len = 591497, overlap = 151.156
+PHY-3002 : Step(250): len = 593767, overlap = 148.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000340757
+PHY-3002 : Step(251): len = 596225, overlap = 142.469
+PHY-3002 : Step(252): len = 603784, overlap = 129.156
+PHY-3002 : Step(253): len = 608233, overlap = 121.094
+PHY-3002 : Step(254): len = 612633, overlap = 112.438
+PHY-3002 : Step(255): len = 615338, overlap = 108.375
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20087, tinst num: 17695, tnode num: 114795, tedge num: 135900.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.476445s wall, 1.406250s user + 0.062500s system = 1.468750s CPU (99.5%)
+
+RUN-1004 : used memory is 580 MB, reserved memory is 561 MB, peak memory is 716 MB
+OPT-1001 : Total overflow 420.69 peak overflow 3.53
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1424/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719824, over cnt = 2962(8%), over = 10541, worst = 23
+PHY-1001 : End global iterations;  1.140283s wall, 1.640625s user + 0.046875s system = 1.687500s CPU (148.0%)
+
+PHY-1001 : Congestion index: top1 = 67.72, top5 = 55.30, top10 = 50.00, top15 = 46.73.
+PHY-1001 : End incremental global routing;  1.465004s wall, 1.968750s user + 0.046875s system = 2.015625s CPU (137.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.909906s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (99.6%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17559 has valid locations, 333 needs to be replaced
+PHY-3001 : design contains 17977 instances, 7527 luts, 9235 seqs, 1069 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6047 pins
+PHY-3001 : Found 1230 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 640542
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16465/20547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 734232, over cnt = 3002(8%), over = 10684, worst = 24
+PHY-1001 : End global iterations;  0.242053s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (129.1%)
+
+PHY-1001 : Congestion index: top1 = 67.67, top5 = 55.53, top10 = 50.27, top15 = 46.94.
+PHY-3001 : End congestion estimation;  0.561003s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (111.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85856, tnet num: 20369, tinst num: 17977, tnode num: 116536, tedge num: 137666.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.452707s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (100.0%)
+
+RUN-1004 : used memory is 637 MB, reserved memory is 632 MB, peak memory is 718 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.410687s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(256): len = 639387, overlap = 0.03125
+PHY-3002 : Step(257): len = 638878, overlap = 0.03125
+PHY-3002 : Step(258): len = 638726, overlap = 0.09375
+PHY-3002 : Step(259): len = 638388, overlap = 0.09375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16590/20547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731448, over cnt = 3000(8%), over = 10743, worst = 24
+PHY-1001 : End global iterations;  0.186506s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (134.0%)
+
+PHY-1001 : Congestion index: top1 = 68.56, top5 = 56.05, top10 = 50.59, top15 = 47.23.
+PHY-3001 : End congestion estimation;  0.451521s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (114.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.927233s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000345038
+PHY-3002 : Step(260): len = 638259, overlap = 111.031
+PHY-3002 : Step(261): len = 638281, overlap = 111.156
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000690075
+PHY-3002 : Step(262): len = 638342, overlap = 111.406
+PHY-3002 : Step(263): len = 638848, overlap = 111.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00138015
+PHY-3002 : Step(264): len = 639002, overlap = 110.719
+PHY-3002 : Step(265): len = 639412, overlap = 110.406
+PHY-3001 : Final: Len = 639412, Over = 110.406
+PHY-3001 : End incremental placement;  5.889235s wall, 5.890625s user + 0.234375s system = 6.125000s CPU (104.0%)
+
+OPT-1001 : Total overflow 425.62 peak overflow 3.53
+OPT-1001 : End high-fanout net optimization;  8.806067s wall, 9.390625s user + 0.312500s system = 9.703125s CPU (110.2%)
+
+OPT-1001 : Current memory(MB): used = 722, reserve = 708, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16505/20547.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735344, over cnt = 2949(8%), over = 9632, worst = 23
+PHY-1002 : len = 786208, over cnt = 1950(5%), over = 4669, worst = 16
+PHY-1002 : len = 818440, over cnt = 984(2%), over = 2130, worst = 14
+PHY-1002 : len = 845872, over cnt = 211(0%), over = 308, worst = 8
+PHY-1002 : len = 851016, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.716616s wall, 2.375000s user + 0.015625s system = 2.390625s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 55.45, top5 = 49.18, top10 = 46.04, top15 = 43.92.
+OPT-1001 : End congestion update;  1.989182s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (133.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20369 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.795153s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.2%)
+
+OPT-0007 : Start: WNS -1068 TNS -1578 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1478 NUM_FEPS 2 with 118 cells processed and 19382 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1478 NUM_FEPS 2 with 43 cells processed and 4100 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1478 NUM_FEPS 2 with 19 cells processed and 1450 slack improved
+OPT-0007 : Iter 4: improved WNS -968 TNS -1478 NUM_FEPS 2 with 3 cells processed and 796 slack improved
+OPT-1001 : End bottleneck based optimization;  3.185455s wall, 3.843750s user + 0.015625s system = 3.859375s CPU (121.2%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 701, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16535/20552.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 852520, over cnt = 100(0%), over = 134, worst = 5
+PHY-1002 : len = 852520, over cnt = 61(0%), over = 74, worst = 3
+PHY-1002 : len = 853208, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 853264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.600284s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (101.5%)
+
+PHY-1001 : Congestion index: top1 = 55.28, top5 = 49.05, top10 = 45.88, top15 = 43.75.
+OPT-1001 : End congestion update;  0.873921s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (101.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20374 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.796007s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.1%)
+
+OPT-0007 : Start: WNS -968 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1428 NUM_FEPS 2 with 23 cells processed and 5800 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1428 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.793498s wall, 1.812500s user + 0.000000s system = 1.812500s CPU (101.1%)
+
+OPT-1001 : Current memory(MB): used = 715, reserve = 701, peak = 739.
+OPT-1001 : End physical optimization;  15.558102s wall, 16.859375s user + 0.390625s system = 17.250000s CPU (110.9%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7527 LUT to BLE ...
+SYN-4008 : Packed 7527 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6092 remaining SEQ's ...
+SYN-4005 : Packed 3628 SEQ with LUT/SLICE
+SYN-4006 : 1045 single LUT's are left
+SYN-4006 : 2464 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9991/13804 primitive instances ...
+PHY-3001 : End packing;  1.645546s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6893 instances
+RUN-1001 : 3372 mslices, 3373 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17537 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9962 nets have 2 pins
+RUN-1001 : 5722 nets have [3 - 5] pins
+RUN-1001 : 1171 nets have [6 - 10] pins
+RUN-1001 : 311 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6891 instances, 6745 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3583 pins
+PHY-3001 : Found 496 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 653447, Over = 275.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7470/17537.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 808328, over cnt = 1951(5%), over = 3188, worst = 9
+PHY-1002 : len = 816672, over cnt = 1246(3%), over = 1763, worst = 6
+PHY-1002 : len = 830792, over cnt = 459(1%), over = 629, worst = 5
+PHY-1002 : len = 839744, over cnt = 74(0%), over = 97, worst = 5
+PHY-1002 : len = 841280, over cnt = 5(0%), over = 5, worst = 1
+PHY-1001 : End global iterations;  1.604554s wall, 2.187500s user + 0.015625s system = 2.203125s CPU (137.3%)
+
+PHY-1001 : Congestion index: top1 = 56.70, top5 = 48.78, top10 = 45.35, top15 = 43.05.
+PHY-3001 : End congestion estimation;  2.003522s wall, 2.578125s user + 0.015625s system = 2.593750s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73811, tnet num: 17359, tinst num: 6891, tnode num: 96325, tedge num: 123942.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.668480s wall, 1.640625s user + 0.031250s system = 1.671875s CPU (100.2%)
+
+RUN-1004 : used memory is 619 MB, reserved memory is 615 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17359 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.547556s wall, 2.484375s user + 0.062500s system = 2.546875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.67679e-05
+PHY-3002 : Step(266): len = 641563, overlap = 278.25
+PHY-3002 : Step(267): len = 635918, overlap = 275.25
+PHY-3002 : Step(268): len = 632405, overlap = 271
+PHY-3002 : Step(269): len = 630490, overlap = 273.5
+PHY-3002 : Step(270): len = 630104, overlap = 279
+PHY-3002 : Step(271): len = 627977, overlap = 278.25
+PHY-3002 : Step(272): len = 625803, overlap = 282
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.35357e-05
+PHY-3002 : Step(273): len = 629532, overlap = 271.5
+PHY-3002 : Step(274): len = 634881, overlap = 258.5
+PHY-3002 : Step(275): len = 637761, overlap = 252
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000187071
+PHY-3002 : Step(276): len = 646931, overlap = 248.25
+PHY-3002 : Step(277): len = 654540, overlap = 235.25
+PHY-3002 : Step(278): len = 654239, overlap = 234
+PHY-3002 : Step(279): len = 654001, overlap = 228.75
+PHY-3002 : Step(280): len = 654608, overlap = 222.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.379074s wall, 0.328125s user + 0.578125s system = 0.906250s CPU (239.1%)
+
+PHY-3001 : Trial Legalized: Len = 732998
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 772/17537.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 855528, over cnt = 2702(7%), over = 4565, worst = 7
+PHY-1002 : len = 871800, over cnt = 1625(4%), over = 2451, worst = 7
+PHY-1002 : len = 890816, over cnt = 723(2%), over = 1027, worst = 7
+PHY-1002 : len = 904128, over cnt = 130(0%), over = 175, worst = 5
+PHY-1002 : len = 907120, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.377776s wall, 3.531250s user + 0.015625s system = 3.546875s CPU (149.2%)
+
+PHY-1001 : Congestion index: top1 = 53.62, top5 = 48.61, top10 = 45.99, top15 = 44.23.
+PHY-3001 : End congestion estimation;  2.839871s wall, 3.968750s user + 0.015625s system = 3.984375s CPU (140.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17359 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.859074s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000144528
+PHY-3002 : Step(281): len = 706960, overlap = 39
+PHY-3002 : Step(282): len = 692342, overlap = 64.25
+PHY-3002 : Step(283): len = 679237, overlap = 96.25
+PHY-3002 : Step(284): len = 670503, overlap = 123
+PHY-3002 : Step(285): len = 665152, overlap = 143.75
+PHY-3002 : Step(286): len = 661818, overlap = 156.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000289056
+PHY-3002 : Step(287): len = 667967, overlap = 157.5
+PHY-3002 : Step(288): len = 673805, overlap = 147.5
+PHY-3002 : Step(289): len = 676257, overlap = 148.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000578112
+PHY-3002 : Step(290): len = 679907, overlap = 144.75
+PHY-3002 : Step(291): len = 688915, overlap = 132.75
+PHY-3002 : Step(292): len = 697184, overlap = 129
+PHY-3002 : Step(293): len = 695247, overlap = 129.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.034100s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (91.6%)
+
+PHY-3001 : Legalized: Len = 723969, Over = 0
+PHY-3001 : Spreading special nets. 411 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.111602s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (112.0%)
+
+PHY-3001 : 589 instances has been re-located, deltaX = 183, deltaY = 355, maxDist = 3.
+PHY-3001 : Final: Len = 732929, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73811, tnet num: 17359, tinst num: 6894, tnode num: 96325, tedge num: 123942.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.873647s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.2%)
+
+RUN-1004 : used memory is 652 MB, reserved memory is 655 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3473/17537.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 869376, over cnt = 2562(7%), over = 4310, worst = 6
+PHY-1002 : len = 883048, over cnt = 1583(4%), over = 2395, worst = 6
+PHY-1002 : len = 898328, over cnt = 784(2%), over = 1149, worst = 5
+PHY-1002 : len = 912984, over cnt = 182(0%), over = 254, worst = 5
+PHY-1002 : len = 916288, over cnt = 44(0%), over = 51, worst = 3
+PHY-1001 : End global iterations;  1.929286s wall, 3.140625s user + 0.031250s system = 3.171875s CPU (164.4%)
+
+PHY-1001 : Congestion index: top1 = 53.04, top5 = 48.17, top10 = 45.59, top15 = 43.91.
+PHY-1001 : End incremental global routing;  2.307964s wall, 3.515625s user + 0.031250s system = 3.546875s CPU (153.7%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17359 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.887423s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (98.6%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6801 has valid locations, 26 needs to be replaced
+PHY-3001 : design contains 6915 instances, 6766 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3652 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 735981
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15963/17558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919224, over cnt = 115(0%), over = 127, worst = 3
+PHY-1002 : len = 919440, over cnt = 76(0%), over = 78, worst = 2
+PHY-1002 : len = 920040, over cnt = 19(0%), over = 20, worst = 2
+PHY-1002 : len = 920248, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 920264, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.791985s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (108.5%)
+
+PHY-1001 : Congestion index: top1 = 53.06, top5 = 48.19, top10 = 45.62, top15 = 43.95.
+PHY-3001 : End congestion estimation;  1.117840s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (106.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73976, tnet num: 17380, tinst num: 6915, tnode num: 96545, tedge num: 124179.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.866599s wall, 1.859375s user + 0.000000s system = 1.859375s CPU (99.6%)
+
+RUN-1004 : used memory is 690 MB, reserved memory is 688 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.757736s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(294): len = 735043, overlap = 0
+PHY-3002 : Step(295): len = 734822, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15954/17558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 918360, over cnt = 74(0%), over = 81, worst = 5
+PHY-1002 : len = 918384, over cnt = 28(0%), over = 28, worst = 1
+PHY-1002 : len = 918528, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 918632, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.594427s wall, 0.640625s user + 0.015625s system = 0.656250s CPU (110.4%)
+
+PHY-1001 : Congestion index: top1 = 53.04, top5 = 48.19, top10 = 45.59, top15 = 43.94.
+PHY-3001 : End congestion estimation;  0.911769s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (106.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.876273s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000165073
+PHY-3002 : Step(296): len = 734797, overlap = 1.75
+PHY-3002 : Step(297): len = 734980, overlap = 1.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.006280s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 735028, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060909s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.0%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 1, deltaY = 7, maxDist = 1.
+PHY-3001 : Final: Len = 735092, Over = 0
+PHY-3001 : End incremental placement;  6.137045s wall, 6.343750s user + 0.031250s system = 6.375000s CPU (103.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.827292s wall, 11.328125s user + 0.062500s system = 11.390625s CPU (115.9%)
+
+OPT-1001 : Current memory(MB): used = 747, reserve = 736, peak = 750.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15937/17558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919104, over cnt = 51(0%), over = 61, worst = 6
+PHY-1002 : len = 919168, over cnt = 34(0%), over = 37, worst = 2
+PHY-1002 : len = 919432, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 919472, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.596300s wall, 0.671875s user + 0.000000s system = 0.671875s CPU (112.7%)
+
+PHY-1001 : Congestion index: top1 = 52.97, top5 = 48.12, top10 = 45.55, top15 = 43.88.
+OPT-1001 : End congestion update;  0.912936s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (106.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.751838s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.8%)
+
+OPT-0007 : Start: WNS -986 TNS -1650 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6827 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6915 instances, 6766 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3652 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740809, Over = 0
+PHY-3001 : Spreading special nets. 25 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064352s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.1%)
+
+PHY-3001 : 38 instances has been re-located, deltaX = 19, deltaY = 39, maxDist = 3.
+PHY-3001 : Final: Len = 741805, Over = 0
+PHY-3001 : End incremental legalization;  0.415713s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.5%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1521 NUM_FEPS 2 with 57 cells processed and 19180 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6827 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6915 instances, 6766 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3652 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 743775, Over = 0
+PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062577s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.9%)
+
+PHY-3001 : 28 instances has been re-located, deltaX = 17, deltaY = 22, maxDist = 2.
+PHY-3001 : Final: Len = 744525, Over = 0
+PHY-3001 : End incremental legalization;  0.384229s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (97.6%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 34 cells processed and 6893 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6827 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6915 instances, 6766 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3652 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 745077, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061280s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.0%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 8, deltaY = 13, maxDist = 3.
+PHY-3001 : Final: Len = 745521, Over = 0
+PHY-3001 : End incremental legalization;  0.630757s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (61.9%)
+
+OPT-0007 : Iter 3: improved WNS -936 TNS -1521 NUM_FEPS 2 with 21 cells processed and 2693 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6827 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6915 instances, 6766 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3652 pins
+PHY-3001 : Found 499 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747025, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061047s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (102.4%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 3, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 747287, Over = 0
+PHY-3001 : End incremental legalization;  0.390869s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (123.9%)
+
+OPT-0007 : Iter 4: improved WNS -936 TNS -1471 NUM_FEPS 2 with 16 cells processed and 2425 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6832 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6920 instances, 6771 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3654 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747519, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059041s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.9%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 4, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 747497, Over = 0
+PHY-3001 : End incremental legalization;  0.391777s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.7%)
+
+OPT-0007 : Iter 5: improved WNS -936 TNS -1471 NUM_FEPS 2 with 5 cells processed and 975 slack improved
+OPT-1001 : End bottleneck based optimization;  4.634189s wall, 4.531250s user + 0.000000s system = 4.531250s CPU (97.8%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 737, peak = 751.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15338/17560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 931336, over cnt = 288(0%), over = 394, worst = 6
+PHY-1002 : len = 932128, over cnt = 156(0%), over = 165, worst = 3
+PHY-1002 : len = 933352, over cnt = 52(0%), over = 54, worst = 2
+PHY-1002 : len = 934112, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 934328, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.923501s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (116.7%)
+
+PHY-1001 : Congestion index: top1 = 54.89, top5 = 49.29, top10 = 46.41, top15 = 44.48.
+OPT-1001 : End congestion update;  1.249031s wall, 1.375000s user + 0.015625s system = 1.390625s CPU (111.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.733092s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.2%)
+
+OPT-0007 : Start: WNS -986 TNS -1521 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6832 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6920 instances, 6771 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3654 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747599, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058735s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.4%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 4, deltaY = 4, maxDist = 2.
+PHY-3001 : Final: Len = 747809, Over = 0
+PHY-3001 : End incremental legalization;  0.386360s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (101.1%)
+
+OPT-0007 : Iter 1: improved WNS -836 TNS -1321 NUM_FEPS 2 with 14 cells processed and 1400 slack improved
+OPT-0007 : Iter 2: improved WNS -836 TNS -1321 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.506370s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (106.0%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 738, peak = 751.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.727755s wall, 0.703125s user + 0.015625s system = 0.718750s CPU (98.8%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15923/17560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934416, over cnt = 39(0%), over = 44, worst = 2
+PHY-1002 : len = 934424, over cnt = 16(0%), over = 19, worst = 2
+PHY-1002 : len = 934584, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 934648, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 934664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.791888s wall, 0.781250s user + 0.015625s system = 0.796875s CPU (100.6%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 49.27, top10 = 46.36, top15 = 44.46.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.732733s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.1%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -936 TNS -1421 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 54.482759
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -936ps with logic level 2 
+RUN-1001 :       #2 path slack -890ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 17560 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17560 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6832 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6920 instances, 6771 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3654 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747809, Over = 0
+PHY-3001 : End spreading;  0.059061s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.8%)
+
+PHY-3001 : Final: Len = 747809, Over = 0
+PHY-3001 : End incremental legalization;  0.391996s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.7%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.728176s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.9%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15983/17560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934664, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.145380s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (96.7%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 49.27, top10 = 46.36, top15 = 44.46.
+OPT-1001 : End congestion update;  0.489987s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (98.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.751918s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (101.8%)
+
+OPT-0007 : Start: WNS -936 TNS -1421 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6832 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6920 instances, 6771 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3654 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747763, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060205s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.8%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 2, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747753, Over = 0
+PHY-3001 : End incremental legalization;  0.381224s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.4%)
+
+OPT-0007 : Iter 1: improved WNS -836 TNS -1321 NUM_FEPS 2 with 2 cells processed and 100 slack improved
+OPT-0007 : Iter 2: improved WNS -836 TNS -1321 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.737192s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.8%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 738, peak = 751.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15968/17560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934576, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 934592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.266923s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (99.5%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 49.27, top10 = 46.36, top15 = 44.46.
+OPT-1001 : End congestion update;  0.586515s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (101.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.726147s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.0%)
+
+OPT-0007 : Start: WNS -986 TNS -1521 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6832 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6920 instances, 6771 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3654 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747743, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064128s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.5%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747751, Over = 0
+PHY-3001 : End incremental legalization;  0.392120s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%)
+
+OPT-0007 : Iter 1: improved WNS -936 TNS -1521 NUM_FEPS 2 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6832 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6920 instances, 6771 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3654 pins
+PHY-3001 : Found 501 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747745, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059292s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 747753, Over = 0
+PHY-3001 : End incremental legalization;  0.391197s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (127.8%)
+
+OPT-0007 : Iter 2: improved WNS -936 TNS -1471 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -936 TNS -1471 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  2.381327s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (105.0%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 738, peak = 751.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.728741s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.6%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 748, reserve = 738, peak = 751.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.726583s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15981/17560.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934592, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.131960s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.7%)
+
+PHY-1001 : Congestion index: top1 = 54.85, top5 = 49.27, top10 = 46.36, top15 = 44.46.
+RUN-1001 : End congestion update;  0.450631s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.6%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.180515s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (100.6%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 738, peak = 751.
+OPT-1001 : End physical optimization;  29.053949s wall, 30.656250s user + 0.156250s system = 30.812500s CPU (106.1%)
+
+RUN-1003 : finish command "place" in  72.565573s wall, 99.609375s user + 5.765625s system = 105.375000s CPU (145.2%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 645 MB, peak memory is 751 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.703866s wall, 2.953125s user + 0.015625s system = 2.968750s CPU (174.2%)
+
+RUN-1004 : used memory is 660 MB, reserved memory is 645 MB, peak memory is 751 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6922 instances
+RUN-1001 : 3392 mslices, 3379 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17560 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9956 nets have 2 pins
+RUN-1001 : 5730 nets have [3 - 5] pins
+RUN-1001 : 1177 nets have [6 - 10] pins
+RUN-1001 : 313 nets have [11 - 20] pins
+RUN-1001 : 353 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74017, tnet num: 17382, tinst num: 6920, tnode num: 96601, tedge num: 124240.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.608422s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.1%)
+
+RUN-1004 : used memory is 669 MB, reserved memory is 667 MB, peak memory is 751 MB
+PHY-1001 : 3392 mslices, 3379 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_tx_last_1d is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 863328, over cnt = 2731(7%), over = 4598, worst = 7
+PHY-1002 : len = 879376, over cnt = 1800(5%), over = 2718, worst = 7
+PHY-1002 : len = 898216, over cnt = 818(2%), over = 1254, worst = 7
+PHY-1002 : len = 919088, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 919168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.981090s wall, 3.875000s user + 0.062500s system = 3.937500s CPU (132.1%)
+
+PHY-1001 : Congestion index: top1 = 54.57, top5 = 48.81, top10 = 46.02, top15 = 44.13.
+PHY-1001 : End global routing;  3.337591s wall, 4.250000s user + 0.062500s system = 4.312500s CPU (129.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 726, reserve = 721, peak = 751.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1000, reserve = 993, peak = 1000.
+PHY-1001 : End build detailed router design. 3.973139s wall, 3.921875s user + 0.062500s system = 3.984375s CPU (100.3%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 265272, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.471450s wall, 5.453125s user + 0.000000s system = 5.453125s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 265328, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.450443s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.6%)
+
+PHY-1001 : Current memory(MB): used = 1036, reserve = 1029, peak = 1036.
+PHY-1001 : End phase 1; 5.934446s wall, 5.921875s user + 0.000000s system = 5.921875s CPU (99.8%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.33899e+06, over cnt = 1919(0%), over = 1925, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1050, reserve = 1046, peak = 1051.
+PHY-1001 : End initial routed; 29.643417s wall, 66.906250s user + 0.312500s system = 67.218750s CPU (226.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 6/16485(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.939   |  -3.882   |   5   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.315342s wall, 3.312500s user + 0.000000s system = 3.312500s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1064, reserve = 1060, peak = 1064.
+PHY-1001 : End phase 2; 32.958823s wall, 70.218750s user + 0.312500s system = 70.531250s CPU (214.0%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 6 pins with SWNS -1.939ns STNS -3.692ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.148578s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.6%)
+
+PHY-1022 : len = 2.33902e+06, over cnt = 1923(0%), over = 1929, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.418520s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.30626e+06, over cnt = 651(0%), over = 651, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.841167s wall, 2.937500s user + 0.015625s system = 2.953125s CPU (160.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.30645e+06, over cnt = 169(0%), over = 169, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.698162s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (141.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.30783e+06, over cnt = 21(0%), over = 21, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.491403s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (127.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.30816e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.386645s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (105.1%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.30825e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.362685s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (103.4%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.30826e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.460075s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (98.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.30817e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.389844s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.2%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.30811e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.184917s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (101.4%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.3081e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.180718s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (112.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16485(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.939   |  -3.692   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.677846s wall, 3.640625s user + 0.031250s system = 3.671875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 557 feed throughs used by 415 nets
+PHY-1001 : End commit to database; 2.673002s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1164, reserve = 1164, peak = 1164.
+PHY-1001 : End phase 3; 12.186646s wall, 13.687500s user + 0.046875s system = 13.734375s CPU (112.7%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.813ns STNS -3.566ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.136724s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.9%)
+
+PHY-1022 : len = 2.3081e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.378683s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.0%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.813ns, -3.566ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16485(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.813   |  -3.566   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.302749s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 558 feed throughs used by 416 nets
+PHY-1001 : End commit to database; 2.338316s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (99.6%)
+
+PHY-1001 : Current memory(MB): used = 1172, reserve = 1173, peak = 1172.
+PHY-1001 : End phase 4; 6.045467s wall, 6.046875s user + 0.000000s system = 6.046875s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.3081e+06
+PHY-1001 : Current memory(MB): used = 1174, reserve = 1175, peak = 1174.
+PHY-1001 : End export database. 0.061651s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.4%)
+
+PHY-1001 : End detail routing;  61.558813s wall, 100.250000s user + 0.421875s system = 100.671875s CPU (163.5%)
+
+RUN-1003 : finish command "route" in  67.593797s wall, 107.187500s user + 0.484375s system = 107.671875s CPU (159.3%)
+
+RUN-1004 : used memory is 1098 MB, reserved memory is 1100 MB, peak memory is 1174 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10269   out of  19600   52.39%
+#reg                     9381   out of  19600   47.86%
+#le                     12667
+  #lut only              3286   out of  12667   25.94%
+  #reg only              2398   out of  12667   18.93%
+  #lut&reg               6983   out of  12667   55.13%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1813
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1419
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1360
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               948
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/reg6_syn_49.q0              133
+#6        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#7        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          68
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               25
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_184.f1    3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg48_syn_209.f1    3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P19        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12667  |9248    |1021    |9411    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |536    |444     |23      |442     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |102    |83      |4       |90      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |34     |34      |0       |21      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |774    |354     |96      |582     |0       |0       |
+|    u_ADconfig                |AD_config            |193    |124     |25      |145     |0       |0       |
+|    u_gen_sp                  |gen_sp               |265    |155     |71      |121     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |748    |375     |96      |565     |0       |0       |
+|    u_ADconfig                |AD_config            |170    |125     |25      |123     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |160     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3038   |2509    |303     |2036    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |7      |1       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |169    |119     |14      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|    u_sort                    |sort                 |2854   |2381    |289     |1887    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |5      |4       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2386   |2019    |253     |1523    |22      |1       |
+|        channelPart           |channel_part_8478    |135    |131     |3       |122     |0       |0       |
+|        fifo_adc              |fifo_adc             |59     |50      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |1876   |1573    |197     |1138    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |236    |207     |27      |123     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |15     |10      |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17     |14      |3       |8       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |12      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |12      |0       |0       |
+|          insert              |insert               |954    |682     |170     |635     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |686    |684     |0       |380     |0       |0       |
+|        read_ram_i            |read_ram             |281    |235     |44      |192     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |227    |187     |40      |154     |0       |0       |
+|          read_ram_data       |read_ram_data        |53     |47      |4       |37      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |2      |2       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |2      |2       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |321    |230     |36      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3424   |2766    |346     |2073    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |188    |127     |17      |149     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |3204   |2627    |329     |1892    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2740   |2276    |287     |1547    |22      |0       |
+|        channelPart           |channel_part_8478    |224    |221     |3       |138     |0       |0       |
+|        fifo_adc              |fifo_adc             |55     |46      |9       |41      |0       |0       |
+|        ram_switch            |ram_switch           |2075   |1737    |197     |1130    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |212    |185     |27      |99      |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |8       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |6       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |7       |0       |0       |
+|          insert              |insert               |955    |644     |170     |652     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |908    |908     |0       |379     |0       |0       |
+|        read_ram_i            |read_ram_rev         |351    |246     |78      |203     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |283    |201     |70      |154     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |68     |45      |8       |49      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9894  
+    #2         2       3800  
+    #3         3       1411  
+    #4         4       516   
+    #5        5-10     1230  
+    #6       11-50     586   
+    #7       51-100     24   
+    #8        >500      1    
+  Average     2.92           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.074899s wall, 3.562500s user + 0.031250s system = 3.593750s CPU (173.2%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1101 MB, peak memory is 1174 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74017, tnet num: 17382, tinst num: 6920, tnode num: 96601, tedge num: 124240.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.616180s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.6%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1104 MB, peak memory is 1174 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17382 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.548047s wall, 1.515625s user + 0.031250s system = 1.546875s CPU (99.9%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1105 MB, peak memory is 1174 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6920
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17560, pip num: 172892
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 558
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3255 valid insts, and 480147 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.011807s wall, 68.156250s user + 0.078125s system = 68.234375s CPU (681.5%)
+
+RUN-1004 : used memory is 1268 MB, reserved memory is 1263 MB, peak memory is 1383 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_135811.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_140730.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_140730.log
new file mode 100644
index 0000000..221f5f8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_140730.log
@@ -0,0 +1,2251 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:07:30 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.377040s wall, 2.281250s user + 0.093750s system = 2.375000s CPU (99.9%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2191 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17697 instances
+RUN-0007 : 7426 luts, 9054 seqs, 698 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20265 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13332 nets have 2 pins
+RUN-1001 : 5463 nets have [3 - 5] pins
+RUN-1001 : 1059 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 174 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17695 instances, 7426 luts, 9054 seqs, 1069 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5933 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20087, tinst num: 17695, tnode num: 114795, tedge num: 135900.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.135635s wall, 1.046875s user + 0.078125s system = 1.125000s CPU (99.1%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 513 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.925158s wall, 1.843750s user + 0.078125s system = 1.921875s CPU (99.8%)
+
+PHY-3001 : Found 1219 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11364e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17695.
+PHY-3001 : Level 1 #clusters 2023.
+PHY-3001 : End clustering;  0.130948s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (119.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28283e+06, overlap = 485.969
+PHY-3002 : Step(2): len = 1.21263e+06, overlap = 505.344
+PHY-3002 : Step(3): len = 844074, overlap = 599.156
+PHY-3002 : Step(4): len = 789561, overlap = 628.781
+PHY-3002 : Step(5): len = 603523, overlap = 768.844
+PHY-3002 : Step(6): len = 517884, overlap = 821.812
+PHY-3002 : Step(7): len = 457802, overlap = 897.812
+PHY-3002 : Step(8): len = 429720, overlap = 962.781
+PHY-3002 : Step(9): len = 389424, overlap = 1013.12
+PHY-3002 : Step(10): len = 355639, overlap = 1084.47
+PHY-3002 : Step(11): len = 323463, overlap = 1135.97
+PHY-3002 : Step(12): len = 297734, overlap = 1181.28
+PHY-3002 : Step(13): len = 269373, overlap = 1251.91
+PHY-3002 : Step(14): len = 249069, overlap = 1310.59
+PHY-3002 : Step(15): len = 231311, overlap = 1310.78
+PHY-3002 : Step(16): len = 210629, overlap = 1350.56
+PHY-3002 : Step(17): len = 194267, overlap = 1361.38
+PHY-3002 : Step(18): len = 177897, overlap = 1381.75
+PHY-3002 : Step(19): len = 168506, overlap = 1401.09
+PHY-3002 : Step(20): len = 153869, overlap = 1414.06
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.28856e-06
+PHY-3002 : Step(21): len = 151820, overlap = 1398.56
+PHY-3002 : Step(22): len = 181674, overlap = 1285.94
+PHY-3002 : Step(23): len = 191872, overlap = 1256.69
+PHY-3002 : Step(24): len = 196657, overlap = 1177.09
+PHY-3002 : Step(25): len = 193501, overlap = 1095.66
+PHY-3002 : Step(26): len = 194440, overlap = 1083.59
+PHY-3002 : Step(27): len = 193690, overlap = 1110
+PHY-3002 : Step(28): len = 193129, overlap = 1123.53
+PHY-3002 : Step(29): len = 192181, overlap = 1112.84
+PHY-3002 : Step(30): len = 190736, overlap = 1106.66
+PHY-3002 : Step(31): len = 188778, overlap = 1111.88
+PHY-3002 : Step(32): len = 186554, overlap = 1105.53
+PHY-3002 : Step(33): len = 184815, overlap = 1081.47
+PHY-3002 : Step(34): len = 183000, overlap = 1061.56
+PHY-3002 : Step(35): len = 181183, overlap = 1070.38
+PHY-3002 : Step(36): len = 180195, overlap = 1089.88
+PHY-3002 : Step(37): len = 179218, overlap = 1071.41
+PHY-3002 : Step(38): len = 178407, overlap = 1062.72
+PHY-3002 : Step(39): len = 177089, overlap = 1069
+PHY-3002 : Step(40): len = 175207, overlap = 1068.41
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.57711e-06
+PHY-3002 : Step(41): len = 179548, overlap = 1059.81
+PHY-3002 : Step(42): len = 188408, overlap = 1016.66
+PHY-3002 : Step(43): len = 192080, overlap = 1004.09
+PHY-3002 : Step(44): len = 198076, overlap = 988.125
+PHY-3002 : Step(45): len = 200125, overlap = 963.969
+PHY-3002 : Step(46): len = 201500, overlap = 951.344
+PHY-3002 : Step(47): len = 199408, overlap = 953.844
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.15422e-06
+PHY-3002 : Step(48): len = 207565, overlap = 925.5
+PHY-3002 : Step(49): len = 221550, overlap = 886.062
+PHY-3002 : Step(50): len = 230737, overlap = 820.688
+PHY-3002 : Step(51): len = 238360, overlap = 767.344
+PHY-3002 : Step(52): len = 242570, overlap = 725.062
+PHY-3002 : Step(53): len = 245306, overlap = 711.469
+PHY-3002 : Step(54): len = 244570, overlap = 695.906
+PHY-3002 : Step(55): len = 244668, overlap = 675.688
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.03084e-05
+PHY-3002 : Step(56): len = 257977, overlap = 674.219
+PHY-3002 : Step(57): len = 278169, overlap = 639.125
+PHY-3002 : Step(58): len = 287777, overlap = 608.5
+PHY-3002 : Step(59): len = 293998, overlap = 578.406
+PHY-3002 : Step(60): len = 291138, overlap = 581.344
+PHY-3002 : Step(61): len = 291611, overlap = 579.594
+PHY-3002 : Step(62): len = 288656, overlap = 555.406
+PHY-3002 : Step(63): len = 288487, overlap = 528.344
+PHY-3002 : Step(64): len = 288123, overlap = 509.219
+PHY-3002 : Step(65): len = 289082, overlap = 506.531
+PHY-3002 : Step(66): len = 287692, overlap = 507.469
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.06169e-05
+PHY-3002 : Step(67): len = 304300, overlap = 489.312
+PHY-3002 : Step(68): len = 316075, overlap = 476.031
+PHY-3002 : Step(69): len = 322654, overlap = 458.625
+PHY-3002 : Step(70): len = 326540, overlap = 452.5
+PHY-3002 : Step(71): len = 326225, overlap = 444.625
+PHY-3002 : Step(72): len = 328676, overlap = 429.688
+PHY-3002 : Step(73): len = 326400, overlap = 402.906
+PHY-3002 : Step(74): len = 328903, overlap = 405.438
+PHY-3002 : Step(75): len = 329572, overlap = 393.312
+PHY-3002 : Step(76): len = 330011, overlap = 398.812
+PHY-3002 : Step(77): len = 328454, overlap = 377.688
+PHY-3002 : Step(78): len = 329194, overlap = 379.406
+PHY-3002 : Step(79): len = 330021, overlap = 378.094
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.12338e-05
+PHY-3002 : Step(80): len = 346578, overlap = 339.062
+PHY-3002 : Step(81): len = 357659, overlap = 310.719
+PHY-3002 : Step(82): len = 357340, overlap = 309.719
+PHY-3002 : Step(83): len = 360700, overlap = 310.406
+PHY-3002 : Step(84): len = 364456, overlap = 322.969
+PHY-3002 : Step(85): len = 370591, overlap = 304.219
+PHY-3002 : Step(86): len = 366482, overlap = 314.312
+PHY-3002 : Step(87): len = 368554, overlap = 316.969
+PHY-3002 : Step(88): len = 371256, overlap = 301.781
+PHY-3002 : Step(89): len = 375141, overlap = 308
+PHY-3002 : Step(90): len = 371126, overlap = 297.188
+PHY-3002 : Step(91): len = 370188, overlap = 292.562
+PHY-3002 : Step(92): len = 370834, overlap = 299.031
+PHY-3002 : Step(93): len = 371822, overlap = 290.531
+PHY-3002 : Step(94): len = 368204, overlap = 286.219
+PHY-3002 : Step(95): len = 368270, overlap = 284
+PHY-3002 : Step(96): len = 369974, overlap = 275.906
+PHY-3002 : Step(97): len = 371736, overlap = 278.094
+PHY-3002 : Step(98): len = 368964, overlap = 296.062
+PHY-3002 : Step(99): len = 368737, overlap = 296
+PHY-3002 : Step(100): len = 369910, overlap = 293.812
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.24675e-05
+PHY-3002 : Step(101): len = 386553, overlap = 292.219
+PHY-3002 : Step(102): len = 399054, overlap = 258.469
+PHY-3002 : Step(103): len = 397552, overlap = 247.594
+PHY-3002 : Step(104): len = 397880, overlap = 248.594
+PHY-3002 : Step(105): len = 399298, overlap = 254.938
+PHY-3002 : Step(106): len = 400208, overlap = 247
+PHY-3002 : Step(107): len = 397828, overlap = 249.469
+PHY-3002 : Step(108): len = 398610, overlap = 234
+PHY-3002 : Step(109): len = 400920, overlap = 223.062
+PHY-3002 : Step(110): len = 402819, overlap = 226.156
+PHY-3002 : Step(111): len = 402035, overlap = 226.625
+PHY-3002 : Step(112): len = 403320, overlap = 224.906
+PHY-3002 : Step(113): len = 404067, overlap = 225.688
+PHY-3002 : Step(114): len = 404430, overlap = 226.719
+PHY-3002 : Step(115): len = 402865, overlap = 222.125
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000160682
+PHY-3002 : Step(116): len = 415830, overlap = 212.219
+PHY-3002 : Step(117): len = 425106, overlap = 209.344
+PHY-3002 : Step(118): len = 426051, overlap = 199.062
+PHY-3002 : Step(119): len = 426723, overlap = 191.156
+PHY-3002 : Step(120): len = 429799, overlap = 182.094
+PHY-3002 : Step(121): len = 432324, overlap = 187.469
+PHY-3002 : Step(122): len = 430812, overlap = 184.594
+PHY-3002 : Step(123): len = 432004, overlap = 188.062
+PHY-3002 : Step(124): len = 435783, overlap = 190.438
+PHY-3002 : Step(125): len = 438672, overlap = 194.281
+PHY-3002 : Step(126): len = 436933, overlap = 184.188
+PHY-3002 : Step(127): len = 438236, overlap = 174.562
+PHY-3002 : Step(128): len = 441004, overlap = 184.75
+PHY-3002 : Step(129): len = 441347, overlap = 194.219
+PHY-3002 : Step(130): len = 439419, overlap = 192.156
+PHY-3002 : Step(131): len = 438871, overlap = 183.062
+PHY-3002 : Step(132): len = 441056, overlap = 186.469
+PHY-3002 : Step(133): len = 442272, overlap = 186.156
+PHY-3002 : Step(134): len = 439923, overlap = 185.094
+PHY-3002 : Step(135): len = 439120, overlap = 183.188
+PHY-3002 : Step(136): len = 440406, overlap = 185.062
+PHY-3002 : Step(137): len = 441194, overlap = 184.906
+PHY-3002 : Step(138): len = 440287, overlap = 173.031
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000305454
+PHY-3002 : Step(139): len = 449262, overlap = 185.625
+PHY-3002 : Step(140): len = 455702, overlap = 185.562
+PHY-3002 : Step(141): len = 456325, overlap = 188.219
+PHY-3002 : Step(142): len = 457038, overlap = 184.219
+PHY-3002 : Step(143): len = 459264, overlap = 180
+PHY-3002 : Step(144): len = 460488, overlap = 180
+PHY-3002 : Step(145): len = 459041, overlap = 182.188
+PHY-3002 : Step(146): len = 459227, overlap = 176.875
+PHY-3002 : Step(147): len = 461786, overlap = 172.875
+PHY-3002 : Step(148): len = 462560, overlap = 175.875
+PHY-3002 : Step(149): len = 461637, overlap = 176.156
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.0005352
+PHY-3002 : Step(150): len = 468530, overlap = 167.594
+PHY-3002 : Step(151): len = 476039, overlap = 168.219
+PHY-3002 : Step(152): len = 475276, overlap = 162.25
+PHY-3002 : Step(153): len = 475320, overlap = 166.156
+PHY-3002 : Step(154): len = 478989, overlap = 160.875
+PHY-3002 : Step(155): len = 482642, overlap = 162.406
+PHY-3002 : Step(156): len = 482344, overlap = 161.031
+PHY-3002 : Step(157): len = 483383, overlap = 160.469
+PHY-3002 : Step(158): len = 486809, overlap = 161.438
+PHY-3002 : Step(159): len = 488518, overlap = 151.031
+PHY-3002 : Step(160): len = 487502, overlap = 155.625
+PHY-3002 : Step(161): len = 487308, overlap = 156.812
+PHY-3002 : Step(162): len = 488202, overlap = 151.5
+PHY-3002 : Step(163): len = 488439, overlap = 152.938
+PHY-3002 : Step(164): len = 487423, overlap = 145.219
+PHY-3002 : Step(165): len = 487155, overlap = 139.188
+PHY-3002 : Step(166): len = 488077, overlap = 141.312
+PHY-3002 : Step(167): len = 488436, overlap = 141.469
+PHY-3002 : Step(168): len = 487169, overlap = 137.719
+PHY-3002 : Step(169): len = 486755, overlap = 140.312
+PHY-3002 : Step(170): len = 487826, overlap = 139.281
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0010704
+PHY-3002 : Step(171): len = 491714, overlap = 140.344
+PHY-3002 : Step(172): len = 497804, overlap = 135.125
+PHY-3002 : Step(173): len = 499815, overlap = 128.5
+PHY-3002 : Step(174): len = 501367, overlap = 130.375
+PHY-3002 : Step(175): len = 503489, overlap = 133.719
+PHY-3002 : Step(176): len = 505240, overlap = 134.219
+PHY-3002 : Step(177): len = 505717, overlap = 136.219
+PHY-3002 : Step(178): len = 506215, overlap = 136.812
+PHY-3002 : Step(179): len = 507510, overlap = 127.094
+PHY-3002 : Step(180): len = 508577, overlap = 126.5
+PHY-3002 : Step(181): len = 508473, overlap = 124.938
+PHY-3002 : Step(182): len = 508741, overlap = 126.812
+PHY-3002 : Step(183): len = 509655, overlap = 125.625
+PHY-3002 : Step(184): len = 510075, overlap = 128.062
+PHY-3002 : Step(185): len = 509806, overlap = 125.625
+PHY-3002 : Step(186): len = 509896, overlap = 123.812
+PHY-3002 : Step(187): len = 510842, overlap = 127.312
+PHY-3002 : Step(188): len = 511071, overlap = 127.375
+PHY-3002 : Step(189): len = 510756, overlap = 127.125
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00185976
+PHY-3002 : Step(190): len = 513252, overlap = 128.062
+PHY-3002 : Step(191): len = 518175, overlap = 127.875
+PHY-3002 : Step(192): len = 518514, overlap = 127.469
+PHY-3002 : Step(193): len = 518717, overlap = 129.562
+PHY-3002 : Step(194): len = 519852, overlap = 120.969
+PHY-3002 : Step(195): len = 520557, overlap = 120.594
+PHY-3002 : Step(196): len = 520488, overlap = 117.594
+PHY-3002 : Step(197): len = 520842, overlap = 117.656
+PHY-3002 : Step(198): len = 522761, overlap = 125.031
+PHY-3002 : Step(199): len = 524977, overlap = 125.75
+PHY-3002 : Step(200): len = 524915, overlap = 124.25
+PHY-3002 : Step(201): len = 525066, overlap = 121.812
+PHY-3002 : Step(202): len = 525938, overlap = 127.781
+PHY-3002 : Step(203): len = 526184, overlap = 126.531
+PHY-3002 : Step(204): len = 525958, overlap = 127.562
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.0030091
+PHY-3002 : Step(205): len = 528633, overlap = 123.719
+PHY-3002 : Step(206): len = 534611, overlap = 120
+PHY-3002 : Step(207): len = 536211, overlap = 118.062
+PHY-3002 : Step(208): len = 537540, overlap = 111.375
+PHY-3002 : Step(209): len = 539534, overlap = 112
+PHY-3002 : Step(210): len = 541216, overlap = 112.469
+PHY-3002 : Step(211): len = 540947, overlap = 111.844
+PHY-3002 : Step(212): len = 541318, overlap = 112.281
+PHY-3002 : Step(213): len = 542930, overlap = 109.906
+PHY-3002 : Step(214): len = 543728, overlap = 109.031
+PHY-3002 : Step(215): len = 543152, overlap = 104.562
+PHY-3002 : Step(216): len = 543045, overlap = 106.812
+PHY-3002 : Step(217): len = 544028, overlap = 103.156
+PHY-3002 : Step(218): len = 544296, overlap = 104.312
+PHY-3002 : Step(219): len = 543720, overlap = 108.125
+PHY-3002 : Step(220): len = 543610, overlap = 107.938
+PHY-3002 : Step(221): len = 544105, overlap = 108
+PHY-3002 : Step(222): len = 544105, overlap = 108
+PHY-3002 : Step(223): len = 543896, overlap = 108.969
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.016319s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (95.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 730640, over cnt = 1569(4%), over = 7290, worst = 68
+PHY-1001 : End global iterations;  0.752135s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (143.3%)
+
+PHY-1001 : Congestion index: top1 = 78.32, top5 = 60.16, top10 = 51.63, top15 = 46.57.
+PHY-3001 : End congestion estimation;  0.973826s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (134.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.871020s wall, 0.843750s user + 0.015625s system = 0.859375s CPU (98.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000171359
+PHY-3002 : Step(224): len = 659533, overlap = 74.0625
+PHY-3002 : Step(225): len = 661138, overlap = 71.8125
+PHY-3002 : Step(226): len = 656485, overlap = 68.9688
+PHY-3002 : Step(227): len = 653025, overlap = 60.5938
+PHY-3002 : Step(228): len = 650277, overlap = 56.375
+PHY-3002 : Step(229): len = 646946, overlap = 55.2188
+PHY-3002 : Step(230): len = 644171, overlap = 57
+PHY-3002 : Step(231): len = 640672, overlap = 57.375
+PHY-3002 : Step(232): len = 636403, overlap = 44.4375
+PHY-3002 : Step(233): len = 632771, overlap = 39.5938
+PHY-3002 : Step(234): len = 629255, overlap = 38.1875
+PHY-3002 : Step(235): len = 626192, overlap = 34.9062
+PHY-3002 : Step(236): len = 624623, overlap = 33.9375
+PHY-3002 : Step(237): len = 622176, overlap = 32.75
+PHY-3002 : Step(238): len = 620484, overlap = 30.7812
+PHY-3002 : Step(239): len = 617840, overlap = 32.625
+PHY-3002 : Step(240): len = 614739, overlap = 32.7812
+PHY-3002 : Step(241): len = 612251, overlap = 36.1875
+PHY-3002 : Step(242): len = 611374, overlap = 36.5938
+PHY-3002 : Step(243): len = 608360, overlap = 36.2188
+PHY-3002 : Step(244): len = 605949, overlap = 37
+PHY-3002 : Step(245): len = 605239, overlap = 37.8125
+PHY-3002 : Step(246): len = 602759, overlap = 35.6875
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000342718
+PHY-3002 : Step(247): len = 604343, overlap = 35.8125
+PHY-3002 : Step(248): len = 607463, overlap = 35.7812
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 121/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 699464, over cnt = 2593(7%), over = 10563, worst = 45
+PHY-1001 : End global iterations;  1.715723s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (133.0%)
+
+PHY-1001 : Congestion index: top1 = 80.99, top5 = 62.25, top10 = 54.12, top15 = 49.40.
+PHY-3001 : End congestion estimation;  1.995988s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (127.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.900566s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000100351
+PHY-3002 : Step(249): len = 604774, overlap = 268.562
+PHY-3002 : Step(250): len = 607990, overlap = 210.344
+PHY-3002 : Step(251): len = 606337, overlap = 199.688
+PHY-3002 : Step(252): len = 601460, overlap = 194.781
+PHY-3002 : Step(253): len = 599875, overlap = 183.438
+PHY-3002 : Step(254): len = 597722, overlap = 182.719
+PHY-3002 : Step(255): len = 595188, overlap = 176.344
+PHY-3002 : Step(256): len = 593927, overlap = 165.25
+PHY-3002 : Step(257): len = 591065, overlap = 160.406
+PHY-3002 : Step(258): len = 588796, overlap = 160.625
+PHY-3002 : Step(259): len = 587984, overlap = 154.969
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000200703
+PHY-3002 : Step(260): len = 587745, overlap = 150.062
+PHY-3002 : Step(261): len = 590164, overlap = 144.812
+PHY-3002 : Step(262): len = 592327, overlap = 137.344
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000401406
+PHY-3002 : Step(263): len = 597951, overlap = 126.969
+PHY-3002 : Step(264): len = 607037, overlap = 105.438
+PHY-3002 : Step(265): len = 615537, overlap = 92.25
+PHY-3002 : Step(266): len = 615204, overlap = 88.2188
+PHY-3002 : Step(267): len = 613559, overlap = 84.1562
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84691, tnet num: 20087, tinst num: 17695, tnode num: 114795, tedge num: 135900.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.458555s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.6%)
+
+RUN-1004 : used memory is 581 MB, reserved memory is 562 MB, peak memory is 716 MB
+OPT-1001 : Total overflow 401.81 peak overflow 4.19
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1313/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719240, over cnt = 2975(8%), over = 10359, worst = 23
+PHY-1001 : End global iterations;  1.228087s wall, 1.781250s user + 0.031250s system = 1.812500s CPU (147.6%)
+
+PHY-1001 : Congestion index: top1 = 68.34, top5 = 54.99, top10 = 49.37, top15 = 45.85.
+PHY-1001 : End incremental global routing;  1.567405s wall, 2.109375s user + 0.031250s system = 2.140625s CPU (136.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.922113s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (98.3%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17559 has valid locations, 344 needs to be replaced
+PHY-3001 : design contains 17988 instances, 7525 luts, 9248 seqs, 1069 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6060 pins
+PHY-3001 : Found 1231 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 637321
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16526/20558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 731840, over cnt = 3016(8%), over = 10362, worst = 22
+PHY-1001 : End global iterations;  0.220226s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (120.6%)
+
+PHY-1001 : Congestion index: top1 = 67.69, top5 = 54.96, top10 = 49.60, top15 = 46.16.
+PHY-3001 : End congestion estimation;  0.462608s wall, 0.500000s user + 0.000000s system = 0.500000s CPU (108.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85887, tnet num: 20380, tinst num: 17988, tnode num: 116591, tedge num: 137706.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.448206s wall, 1.453125s user + 0.000000s system = 1.453125s CPU (100.3%)
+
+RUN-1004 : used memory is 624 MB, reserved memory is 612 MB, peak memory is 720 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.398766s wall, 2.406250s user + 0.000000s system = 2.406250s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(268): len = 636313, overlap = 0
+PHY-3002 : Step(269): len = 636107, overlap = 0
+PHY-3002 : Step(270): len = 635887, overlap = 0
+PHY-3002 : Step(271): len = 635656, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16629/20558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 729264, over cnt = 3028(8%), over = 10412, worst = 22
+PHY-1001 : End global iterations;  0.177244s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (123.4%)
+
+PHY-1001 : Congestion index: top1 = 68.10, top5 = 55.22, top10 = 49.75, top15 = 46.30.
+PHY-3001 : End congestion estimation;  0.430590s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (108.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.013406s wall, 1.000000s user + 0.015625s system = 1.015625s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000406134
+PHY-3002 : Step(272): len = 635634, overlap = 87.4688
+PHY-3002 : Step(273): len = 635581, overlap = 86.5625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000812269
+PHY-3002 : Step(274): len = 635764, overlap = 86.2188
+PHY-3002 : Step(275): len = 636260, overlap = 86.3125
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00162454
+PHY-3002 : Step(276): len = 636436, overlap = 86.6875
+PHY-3002 : Step(277): len = 637159, overlap = 86.8125
+PHY-3001 : Final: Len = 637159, Over = 86.8125
+PHY-3001 : End incremental placement;  5.049673s wall, 5.250000s user + 0.203125s system = 5.453125s CPU (108.0%)
+
+OPT-1001 : Total overflow 408.28 peak overflow 4.19
+OPT-1001 : End high-fanout net optimization;  8.089886s wall, 8.875000s user + 0.265625s system = 9.140625s CPU (113.0%)
+
+OPT-1001 : Current memory(MB): used = 723, reserve = 709, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16560/20558.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 733912, over cnt = 2943(8%), over = 9286, worst = 22
+PHY-1002 : len = 778272, over cnt = 1926(5%), over = 4778, worst = 22
+PHY-1002 : len = 813952, over cnt = 947(2%), over = 2021, worst = 19
+PHY-1002 : len = 832448, over cnt = 472(1%), over = 919, worst = 14
+PHY-1002 : len = 847800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.033771s wall, 2.562500s user + 0.000000s system = 2.562500s CPU (126.0%)
+
+PHY-1001 : Congestion index: top1 = 56.31, top5 = 49.43, top10 = 45.65, top15 = 43.37.
+OPT-1001 : End congestion update;  2.309303s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (122.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20380 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.833466s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (101.2%)
+
+OPT-0007 : Start: WNS -1068 TNS -1578 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 117 cells processed and 19100 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 13 cells processed and 1650 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1478 NUM_FEPS 2 with 2 cells processed and 750 slack improved
+OPT-1001 : End bottleneck based optimization;  3.444141s wall, 3.968750s user + 0.000000s system = 3.968750s CPU (115.2%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 689, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16656/20564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 848904, over cnt = 68(0%), over = 97, worst = 4
+PHY-1002 : len = 848712, over cnt = 39(0%), over = 42, worst = 2
+PHY-1002 : len = 848912, over cnt = 19(0%), over = 20, worst = 2
+PHY-1002 : len = 849176, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 849224, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.691198s wall, 0.703125s user + 0.000000s system = 0.703125s CPU (101.7%)
+
+PHY-1001 : Congestion index: top1 = 56.12, top5 = 49.32, top10 = 45.52, top15 = 43.26.
+OPT-1001 : End congestion update;  0.951434s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (101.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.804348s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (97.1%)
+
+OPT-0007 : Start: WNS -1018 TNS -1478 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1428 NUM_FEPS 2 with 18 cells processed and 3100 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1428 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.874424s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (100.0%)
+
+OPT-1001 : Current memory(MB): used = 710, reserve = 697, peak = 739.
+OPT-1001 : End physical optimization;  15.178205s wall, 16.546875s user + 0.296875s system = 16.843750s CPU (111.0%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7525 LUT to BLE ...
+SYN-4008 : Packed 7525 LUT and 3147 SEQ to BLE.
+SYN-4003 : Packing 6107 remaining SEQ's ...
+SYN-4005 : Packed 3755 SEQ with LUT/SLICE
+SYN-4006 : 913 single LUT's are left
+SYN-4006 : 2352 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9877/13690 primitive instances ...
+PHY-3001 : End packing;  1.603449s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.4%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6848 instances
+RUN-1001 : 3350 mslices, 3350 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17545 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9986 nets have 2 pins
+RUN-1001 : 5697 nets have [3 - 5] pins
+RUN-1001 : 1169 nets have [6 - 10] pins
+RUN-1001 : 321 nets have [11 - 20] pins
+RUN-1001 : 337 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6846 instances, 6700 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3587 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 649858, Over = 267
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7508/17545.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 801264, over cnt = 1860(5%), over = 3039, worst = 9
+PHY-1002 : len = 809160, over cnt = 1220(3%), over = 1760, worst = 7
+PHY-1002 : len = 820040, over cnt = 621(1%), over = 848, worst = 6
+PHY-1002 : len = 829872, over cnt = 243(0%), over = 314, worst = 5
+PHY-1002 : len = 835552, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.536142s wall, 2.078125s user + 0.031250s system = 2.109375s CPU (137.3%)
+
+PHY-1001 : Congestion index: top1 = 57.69, top5 = 49.49, top10 = 45.70, top15 = 43.37.
+PHY-3001 : End congestion estimation;  1.922746s wall, 2.468750s user + 0.031250s system = 2.500000s CPU (130.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73690, tnet num: 17367, tinst num: 6846, tnode num: 96141, tedge num: 123677.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.630757s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (99.6%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 615 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17367 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.493948s wall, 2.453125s user + 0.031250s system = 2.484375s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.72367e-05
+PHY-3002 : Step(278): len = 639097, overlap = 263
+PHY-3002 : Step(279): len = 633609, overlap = 271.75
+PHY-3002 : Step(280): len = 630088, overlap = 276
+PHY-3002 : Step(281): len = 627826, overlap = 274.25
+PHY-3002 : Step(282): len = 626747, overlap = 285.25
+PHY-3002 : Step(283): len = 625378, overlap = 289.5
+PHY-3002 : Step(284): len = 623568, overlap = 291.5
+PHY-3002 : Step(285): len = 622751, overlap = 272.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.44735e-05
+PHY-3002 : Step(286): len = 625407, overlap = 266.25
+PHY-3002 : Step(287): len = 628449, overlap = 262.5
+PHY-3002 : Step(288): len = 628871, overlap = 264
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000182196
+PHY-3002 : Step(289): len = 638829, overlap = 249
+PHY-3002 : Step(290): len = 649281, overlap = 235
+PHY-3002 : Step(291): len = 649532, overlap = 233.25
+PHY-3002 : Step(292): len = 649283, overlap = 237.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.381788s wall, 0.343750s user + 0.640625s system = 0.984375s CPU (257.8%)
+
+PHY-3001 : Trial Legalized: Len = 739528
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 922/17545.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 857016, over cnt = 2614(7%), over = 4352, worst = 8
+PHY-1002 : len = 871176, over cnt = 1688(4%), over = 2513, worst = 8
+PHY-1002 : len = 892096, over cnt = 578(1%), over = 899, worst = 8
+PHY-1002 : len = 903672, over cnt = 76(0%), over = 124, worst = 6
+PHY-1002 : len = 905832, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations;  2.300413s wall, 3.296875s user + 0.000000s system = 3.296875s CPU (143.3%)
+
+PHY-1001 : Congestion index: top1 = 52.82, top5 = 48.54, top10 = 45.90, top15 = 44.14.
+PHY-3001 : End congestion estimation;  2.753047s wall, 3.750000s user + 0.000000s system = 3.750000s CPU (136.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17367 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.858756s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000153516
+PHY-3002 : Step(293): len = 710594, overlap = 44.5
+PHY-3002 : Step(294): len = 692983, overlap = 75
+PHY-3002 : Step(295): len = 679260, overlap = 101.75
+PHY-3002 : Step(296): len = 670873, overlap = 123.5
+PHY-3002 : Step(297): len = 666096, overlap = 141.5
+PHY-3002 : Step(298): len = 662784, overlap = 154
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000307032
+PHY-3002 : Step(299): len = 667256, overlap = 152.75
+PHY-3002 : Step(300): len = 673091, overlap = 152.75
+PHY-3002 : Step(301): len = 677137, overlap = 156.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000614064
+PHY-3002 : Step(302): len = 680968, overlap = 154.5
+PHY-3002 : Step(303): len = 691471, overlap = 156.25
+PHY-3002 : Step(304): len = 695341, overlap = 155.5
+PHY-3002 : Step(305): len = 697655, overlap = 153.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.034399s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (90.8%)
+
+PHY-3001 : Legalized: Len = 728239, Over = 0
+PHY-3001 : Spreading special nets. 426 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.104541s wall, 0.093750s user + 0.000000s system = 0.093750s CPU (89.7%)
+
+PHY-3001 : 621 instances has been re-located, deltaX = 246, deltaY = 368, maxDist = 3.
+PHY-3001 : Final: Len = 738789, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73690, tnet num: 17367, tinst num: 6849, tnode num: 96141, tedge num: 123677.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.893651s wall, 1.859375s user + 0.031250s system = 1.890625s CPU (99.8%)
+
+RUN-1004 : used memory is 643 MB, reserved memory is 656 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3523/17545.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 868784, over cnt = 2486(7%), over = 4067, worst = 9
+PHY-1002 : len = 882816, over cnt = 1476(4%), over = 2106, worst = 6
+PHY-1002 : len = 899904, over cnt = 518(1%), over = 693, worst = 5
+PHY-1002 : len = 907640, over cnt = 143(0%), over = 186, worst = 5
+PHY-1002 : len = 910920, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.962457s wall, 2.828125s user + 0.031250s system = 2.859375s CPU (145.7%)
+
+PHY-1001 : Congestion index: top1 = 52.59, top5 = 47.80, top10 = 45.22, top15 = 43.57.
+PHY-1001 : End incremental global routing;  2.330443s wall, 3.187500s user + 0.031250s system = 3.218750s CPU (138.1%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17367 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.905162s wall, 0.875000s user + 0.031250s system = 0.906250s CPU (100.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6757 has valid locations, 20 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3666 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 741316
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15992/17565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913672, over cnt = 72(0%), over = 80, worst = 4
+PHY-1002 : len = 913848, over cnt = 34(0%), over = 35, worst = 2
+PHY-1002 : len = 914168, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 914160, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.581961s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (107.4%)
+
+PHY-1001 : Congestion index: top1 = 52.59, top5 = 47.81, top10 = 45.23, top15 = 43.58.
+PHY-3001 : End congestion estimation;  0.889668s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (103.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73838, tnet num: 17387, tinst num: 6865, tnode num: 96328, tedge num: 123879.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.844888s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (99.9%)
+
+RUN-1004 : used memory is 669 MB, reserved memory is 668 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.729103s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(306): len = 740499, overlap = 0
+PHY-3002 : Step(307): len = 740192, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15988/17565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 912256, over cnt = 42(0%), over = 57, worst = 4
+PHY-1002 : len = 912392, over cnt = 23(0%), over = 25, worst = 3
+PHY-1002 : len = 912632, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 912712, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.569012s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (101.6%)
+
+PHY-1001 : Congestion index: top1 = 52.61, top5 = 47.81, top10 = 45.24, top15 = 43.61.
+PHY-3001 : End congestion estimation;  0.875602s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (99.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.858222s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000199519
+PHY-3002 : Step(308): len = 740564, overlap = 0.75
+PHY-3002 : Step(309): len = 740564, overlap = 0.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005538s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (282.2%)
+
+PHY-3001 : Legalized: Len = 740524, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059779s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.6%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 10, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 740700, Over = 0
+PHY-3001 : End incremental placement;  5.821226s wall, 5.890625s user + 0.093750s system = 5.984375s CPU (102.8%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  9.540206s wall, 10.437500s user + 0.156250s system = 10.593750s CPU (111.0%)
+
+OPT-1001 : Current memory(MB): used = 749, reserve = 742, peak = 753.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15957/17565.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 913112, over cnt = 49(0%), over = 58, worst = 4
+PHY-1002 : len = 913152, over cnt = 28(0%), over = 30, worst = 2
+PHY-1002 : len = 913296, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 913376, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 913408, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.753232s wall, 0.734375s user + 0.015625s system = 0.750000s CPU (99.6%)
+
+PHY-1001 : Congestion index: top1 = 52.72, top5 = 47.82, top10 = 45.26, top15 = 43.63.
+OPT-1001 : End congestion update;  1.056959s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (99.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17387 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.717126s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.2%)
+
+OPT-0007 : Start: WNS -1133 TNS -1818 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6777 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3666 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 745234, Over = 0
+PHY-3001 : Spreading special nets. 27 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062454s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-3001 : 36 instances has been re-located, deltaX = 20, deltaY = 19, maxDist = 2.
+PHY-3001 : Final: Len = 746364, Over = 0
+PHY-3001 : End incremental legalization;  0.388679s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (96.5%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 49 cells processed and 14964 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6777 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3666 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 747988, Over = 0
+PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060572s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.4%)
+
+PHY-3001 : 26 instances has been re-located, deltaX = 18, deltaY = 19, maxDist = 3.
+PHY-3001 : Final: Len = 748634, Over = 0
+PHY-3001 : End incremental legalization;  0.383059s wall, 0.375000s user + 0.031250s system = 0.406250s CPU (106.1%)
+
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 35 cells processed and 9133 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6777 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6865 instances, 6716 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3666 pins
+PHY-3001 : Found 500 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 749430, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.066150s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (94.5%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 12, deltaY = 10, maxDist = 4.
+PHY-3001 : Final: Len = 749842, Over = 0
+PHY-3001 : End incremental legalization;  0.433686s wall, 0.453125s user + 0.015625s system = 0.468750s CPU (108.1%)
+
+OPT-0007 : Iter 3: improved WNS -983 TNS -1518 NUM_FEPS 2 with 22 cells processed and 2242 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3668 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750391, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060329s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.6%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 1, deltaY = 7, maxDist = 1.
+PHY-3001 : Final: Len = 750593, Over = 0
+PHY-3001 : End incremental legalization;  0.398350s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.1%)
+
+OPT-0007 : Iter 4: improved WNS -983 TNS -1518 NUM_FEPS 2 with 7 cells processed and 986 slack improved
+OPT-1001 : End bottleneck based optimization;  4.053447s wall, 4.156250s user + 0.093750s system = 4.250000s CPU (104.8%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 741, peak = 753.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15490/17569.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924192, over cnt = 206(0%), over = 275, worst = 5
+PHY-1002 : len = 924576, over cnt = 125(0%), over = 152, worst = 4
+PHY-1002 : len = 925568, over cnt = 54(0%), over = 65, worst = 4
+PHY-1002 : len = 926264, over cnt = 15(0%), over = 20, worst = 2
+PHY-1002 : len = 926624, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.863264s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (103.2%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.00, top10 = 45.44, top15 = 43.78.
+OPT-1001 : End congestion update;  1.179899s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (103.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.726426s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.9%)
+
+OPT-0007 : Start: WNS -1083 TNS -1618 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3668 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750537, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060454s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (103.4%)
+
+PHY-3001 : 10 instances has been re-located, deltaX = 7, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 750761, Over = 0
+PHY-3001 : End incremental legalization;  0.381285s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.4%)
+
+OPT-0007 : Iter 1: improved WNS -933 TNS -1468 NUM_FEPS 2 with 11 cells processed and 1250 slack improved
+OPT-0007 : Iter 2: improved WNS -933 TNS -1468 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.414269s wall, 2.484375s user + 0.031250s system = 2.515625s CPU (104.2%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 741, peak = 753.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.724157s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15982/17569.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926792, over cnt = 14(0%), over = 15, worst = 2
+PHY-1002 : len = 926808, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 926824, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 926840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.574848s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (103.3%)
+
+PHY-1001 : Congestion index: top1 = 53.17, top5 = 47.99, top10 = 45.46, top15 = 43.81.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.723213s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.4%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -983 TNS -1518 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 52.689655
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -983ps with logic level 2 
+RUN-1001 :       #2 path slack -947ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 17569 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17569 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3668 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750761, Over = 0
+PHY-3001 : End spreading;  0.059811s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+
+PHY-3001 : Final: Len = 750761, Over = 0
+PHY-3001 : End incremental legalization;  0.385277s wall, 0.390625s user + 0.015625s system = 0.406250s CPU (105.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.720742s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.7%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16018/17569.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926840, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.128318s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (97.4%)
+
+PHY-1001 : Congestion index: top1 = 53.17, top5 = 47.99, top10 = 45.46, top15 = 43.81.
+OPT-1001 : End congestion update;  0.436755s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.723331s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.4%)
+
+OPT-0007 : Start: WNS -983 TNS -1518 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3668 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750691, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.060411s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.6%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 3, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 750789, Over = 0
+PHY-3001 : End incremental legalization;  0.387005s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (125.2%)
+
+OPT-0007 : Iter 1: improved WNS -933 TNS -1418 NUM_FEPS 2 with 4 cells processed and 200 slack improved
+OPT-0007 : Iter 2: improved WNS -933 TNS -1418 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.699374s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (111.3%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 741, peak = 753.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16008/17569.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926856, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 926864, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 926872, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.412984s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (102.2%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 48.00, top10 = 45.46, top15 = 43.81.
+OPT-1001 : End congestion update;  0.727113s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.750228s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (97.9%)
+
+OPT-0007 : Start: WNS -983 TNS -1518 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3668 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750793, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058294s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (107.2%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 750825, Over = 0
+PHY-3001 : End incremental legalization;  0.411335s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.8%)
+
+OPT-0007 : Iter 1: improved WNS -983 TNS -1518 NUM_FEPS 2 with 1 cells processed and 50 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6785 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6873 instances, 6724 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3668 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 750793, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059027s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (105.9%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 750825, Over = 0
+PHY-3001 : End incremental legalization;  0.381885s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (102.3%)
+
+OPT-0007 : Iter 2: improved WNS -983 TNS -1518 NUM_FEPS 2 with 1 cells processed and 0 slack improved
+OPT-0007 : Iter 3: improved WNS -983 TNS -1518 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  2.562972s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (99.4%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 741, peak = 753.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.725084s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 748, reserve = 741, peak = 753.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17390 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.730525s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (100.5%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 16009/17569.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926872, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 926864, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.271740s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (97.7%)
+
+PHY-1001 : Congestion index: top1 = 53.21, top5 = 47.99, top10 = 45.45, top15 = 43.80.
+RUN-1001 : End congestion update;  0.587050s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (101.1%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.320863s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 748, reserve = 741, peak = 753.
+OPT-1001 : End physical optimization;  28.159402s wall, 29.375000s user + 0.328125s system = 29.703125s CPU (105.5%)
+
+RUN-1003 : finish command "place" in  71.774556s wall, 95.187500s user + 6.312500s system = 101.500000s CPU (141.4%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 658 MB, peak memory is 753 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.687790s wall, 2.937500s user + 0.000000s system = 2.937500s CPU (174.0%)
+
+RUN-1004 : used memory is 655 MB, reserved memory is 658 MB, peak memory is 753 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6875 instances
+RUN-1001 : 3363 mslices, 3361 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17569 nets
+RUN-6002 WARNING: There are 4 undriven nets.
+RUN-6004 WARNING: There are 23 nets with only 1 pin.
+RUN-1001 : 9983 nets have 2 pins
+RUN-1001 : 5707 nets have [3 - 5] pins
+RUN-1001 : 1170 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 353 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73915, tnet num: 17391, tinst num: 6873, tnode num: 96431, tedge num: 123987.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.596960s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (99.8%)
+
+RUN-1004 : used memory is 637 MB, reserved memory is 626 MB, peak memory is 753 MB
+PHY-1001 : 3363 mslices, 3361 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17391 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[13] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_frame_end_delay_cnt[12] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[23] is skipped due to 0 input or output
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_2d[22] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 861704, over cnt = 2697(7%), over = 4395, worst = 8
+PHY-1002 : len = 878344, over cnt = 1605(4%), over = 2334, worst = 6
+PHY-1002 : len = 896016, over cnt = 685(1%), over = 962, worst = 5
+PHY-1002 : len = 911448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.844603s wall, 3.875000s user + 0.046875s system = 3.921875s CPU (137.9%)
+
+PHY-1001 : Congestion index: top1 = 52.78, top5 = 47.70, top10 = 45.13, top15 = 43.37.
+PHY-1001 : End global routing;  3.186990s wall, 4.203125s user + 0.062500s system = 4.265625s CPU (133.8%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 717, reserve = 714, peak = 753.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 992, reserve = 990, peak = 992.
+PHY-1001 : End build detailed router design. 4.071634s wall, 4.000000s user + 0.062500s system = 4.062500s CPU (99.8%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 266480, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.240378s wall, 5.218750s user + 0.015625s system = 5.234375s CPU (99.9%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 266536, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.473117s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (99.1%)
+
+PHY-1001 : Current memory(MB): used = 1028, reserve = 1026, peak = 1028.
+PHY-1001 : End phase 1; 5.727205s wall, 5.703125s user + 0.015625s system = 5.718750s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.33641e+06, over cnt = 1689(0%), over = 1698, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1043, peak = 1047.
+PHY-1001 : End initial routed; 29.818531s wall, 64.437500s user + 0.343750s system = 64.781250s CPU (217.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16492(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.921   |  -3.655   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.239918s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.8%)
+
+PHY-1001 : Current memory(MB): used = 1056, reserve = 1053, peak = 1056.
+PHY-1001 : End phase 2; 33.058514s wall, 67.671875s user + 0.343750s system = 68.015625s CPU (205.7%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.795ns STNS -3.529ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.134674s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (104.4%)
+
+PHY-1022 : len = 2.33642e+06, over cnt = 1691(0%), over = 1700, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.400582s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (101.4%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.30938e+06, over cnt = 657(0%), over = 657, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.327335s wall, 2.437500s user + 0.000000s system = 2.437500s CPU (183.6%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.30786e+06, over cnt = 155(0%), over = 155, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.496803s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (173.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.30822e+06, over cnt = 27(0%), over = 27, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.336910s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (120.6%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.30818e+06, over cnt = 5(0%), over = 5, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.271834s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (115.0%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.3083e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.232514s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (100.8%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.3083e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.260046s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (102.1%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.3083e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.365840s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (102.5%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.3083e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.172141s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.8%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.30825e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.164517s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (104.5%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16492(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.795   |  -3.529   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.340949s wall, 3.328125s user + 0.000000s system = 3.328125s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 520 feed throughs used by 391 nets
+PHY-1001 : End commit to database; 2.263762s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (99.4%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1161, peak = 1160.
+PHY-1001 : End phase 3; 10.059360s wall, 11.656250s user + 0.000000s system = 11.656250s CPU (115.9%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.795ns STNS -3.529ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.137062s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (102.6%)
+
+PHY-1022 : len = 2.30825e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.376679s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.6%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.795ns, -3.529ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16492(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.795   |  -3.529   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.244413s wall, 3.234375s user + 0.015625s system = 3.250000s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 520 feed throughs used by 391 nets
+PHY-1001 : End commit to database; 2.375539s wall, 2.375000s user + 0.000000s system = 2.375000s CPU (100.0%)
+
+PHY-1001 : Current memory(MB): used = 1169, reserve = 1170, peak = 1169.
+PHY-1001 : End phase 4; 6.025272s wall, 6.015625s user + 0.015625s system = 6.031250s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.30825e+06
+PHY-1001 : Current memory(MB): used = 1171, reserve = 1172, peak = 1171.
+PHY-1001 : End export database. 0.068920s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (90.7%)
+
+PHY-1001 : End detail routing;  59.458482s wall, 95.562500s user + 0.437500s system = 96.000000s CPU (161.5%)
+
+RUN-1003 : finish command "route" in  65.340697s wall, 102.421875s user + 0.531250s system = 102.953125s CPU (157.6%)
+
+RUN-1004 : used memory is 1094 MB, reserved memory is 1090 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10259   out of  19600   52.34%
+#reg                     9391   out of  19600   47.91%
+#le                     12541
+  #lut only              3150   out of  12541   25.12%
+  #reg only              2282   out of  12541   18.20%
+  #lut&reg               7109   out of  12541   56.69%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1808
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1403
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1358
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               945
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               mslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    143
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               27
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_293.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg47_syn_219.f1    3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P19        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12541  |9238    |1021    |9421    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |519    |431     |23      |428     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |106    |90      |4       |93      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |30     |30      |0       |21      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |7      |7       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |783    |380     |96      |586     |0       |0       |
+|    u_ADconfig                |AD_config            |200    |121     |25      |147     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |151     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |749    |409     |96      |559     |0       |0       |
+|    u_ADconfig                |AD_config            |175    |136     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |262    |149     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3035   |2462    |303     |2048    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |8      |2       |0       |8       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |161    |98      |14      |129     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |2856   |2352    |289     |1901    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |6      |1       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |3      |1       |0       |3       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2395   |2013    |253     |1543    |22      |1       |
+|        channelPart           |channel_part_8478    |162    |158     |3       |137     |0       |0       |
+|        fifo_adc              |fifo_adc             |60     |51      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |1871   |1566    |197     |1148    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |256    |225     |27      |131     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |16     |9       |3       |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |15      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |8       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |12      |0       |0       |
+|          insert              |insert               |925    |651     |170     |621     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |690    |690     |0       |396     |0       |0       |
+|        read_ram_i            |read_ram             |278    |223     |44      |190     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |221    |181     |40      |149     |0       |0       |
+|          read_ram_data       |read_ram_data        |55     |40      |4       |39      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |350    |245     |36      |278     |3       |0       |
+|        u0_soft_n             |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3337   |2633    |346     |2112    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |185    |114     |17      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|    u_sort                    |sort_rev             |3121   |2499    |329     |1934    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |6       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |3      |2       |0       |3       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2728   |2234    |287     |1598    |22      |0       |
+|        channelPart           |channel_part_8478    |250    |247     |3       |143     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |45      |0       |0       |
+|        ram_switch            |ram_switch           |2007   |1649    |197     |1151    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |219    |192     |27      |107     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |10      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |10      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |13      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |5       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|          insert              |insert               |995    |664     |170     |691     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |793    |793     |0       |353     |0       |0       |
+|        read_ram_i            |read_ram_rev         |371    |258     |78      |221     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |299    |217     |70      |169     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |72     |41      |8       |52      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9921  
+    #2         2       3820  
+    #3         3       1368  
+    #4         4       516   
+    #5        5-10     1228  
+    #6       11-50     595   
+    #7       51-100     22   
+    #8        >500      1    
+  Average     2.91           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.188800s wall, 3.718750s user + 0.031250s system = 3.750000s CPU (171.3%)
+
+RUN-1004 : used memory is 1096 MB, reserved memory is 1092 MB, peak memory is 1171 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73915, tnet num: 17391, tinst num: 6873, tnode num: 96431, tedge num: 123987.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.673607s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (99.9%)
+
+RUN-1004 : used memory is 1100 MB, reserved memory is 1096 MB, peak memory is 1171 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17391 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.525198s wall, 1.515625s user + 0.015625s system = 1.531250s CPU (100.4%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1100 MB, peak memory is 1171 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6873
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17569, pip num: 172047
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 520
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3238 valid insts, and 478179 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.140968s wall, 59.109375s user + 0.203125s system = 59.312500s CPU (584.9%)
+
+RUN-1004 : used memory is 1271 MB, reserved memory is 1265 MB, peak memory is 1386 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_140730.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_141951.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_141951.log
new file mode 100644
index 0000000..4996a3d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_141951.log
@@ -0,0 +1,2010 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:19:51 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.383624s wall, 2.328125s user + 0.062500s system = 2.390625s CPU (100.3%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 314 MB, peak memory is 349 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2952 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2192 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2078 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17697 instances
+RUN-0007 : 7426 luts, 9054 seqs, 698 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20265 nets
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 13332 nets have 2 pins
+RUN-1001 : 5463 nets have [3 - 5] pins
+RUN-1001 : 1059 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 174 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     799     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3478     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17695 instances, 7426 luts, 9054 seqs, 1069 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5933 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84693, tnet num: 20087, tinst num: 17695, tnode num: 114800, tedge num: 135904.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.149777s wall, 1.140625s user + 0.015625s system = 1.156250s CPU (100.6%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 513 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.934594s wall, 1.906250s user + 0.031250s system = 1.937500s CPU (100.2%)
+
+PHY-3001 : Found 1219 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.11424e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17695.
+PHY-3001 : Level 1 #clusters 2023.
+PHY-3001 : End clustering;  0.129795s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (108.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.28332e+06, overlap = 486.344
+PHY-3002 : Step(2): len = 1.21308e+06, overlap = 506.094
+PHY-3002 : Step(3): len = 846346, overlap = 598.469
+PHY-3002 : Step(4): len = 797848, overlap = 623.562
+PHY-3002 : Step(5): len = 607741, overlap = 766.781
+PHY-3002 : Step(6): len = 517354, overlap = 828.375
+PHY-3002 : Step(7): len = 456129, overlap = 888.875
+PHY-3002 : Step(8): len = 430273, overlap = 959.625
+PHY-3002 : Step(9): len = 388556, overlap = 1016.69
+PHY-3002 : Step(10): len = 354504, overlap = 1086.78
+PHY-3002 : Step(11): len = 323172, overlap = 1136.47
+PHY-3002 : Step(12): len = 296911, overlap = 1180.41
+PHY-3002 : Step(13): len = 266701, overlap = 1236.91
+PHY-3002 : Step(14): len = 244602, overlap = 1296.28
+PHY-3002 : Step(15): len = 225791, overlap = 1297.59
+PHY-3002 : Step(16): len = 206112, overlap = 1350.78
+PHY-3002 : Step(17): len = 192562, overlap = 1372.28
+PHY-3002 : Step(18): len = 177954, overlap = 1398
+PHY-3002 : Step(19): len = 164464, overlap = 1402.94
+PHY-3002 : Step(20): len = 155144, overlap = 1411.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.39722e-06
+PHY-3002 : Step(21): len = 152948, overlap = 1413.59
+PHY-3002 : Step(22): len = 184305, overlap = 1281.47
+PHY-3002 : Step(23): len = 193594, overlap = 1206.97
+PHY-3002 : Step(24): len = 200567, overlap = 1189.34
+PHY-3002 : Step(25): len = 198182, overlap = 1116.38
+PHY-3002 : Step(26): len = 202334, overlap = 1039.53
+PHY-3002 : Step(27): len = 202488, overlap = 1030.75
+PHY-3002 : Step(28): len = 202379, overlap = 1037.5
+PHY-3002 : Step(29): len = 199893, overlap = 1024.12
+PHY-3002 : Step(30): len = 196858, overlap = 1029.66
+PHY-3002 : Step(31): len = 192443, overlap = 1047.03
+PHY-3002 : Step(32): len = 190623, overlap = 1026.97
+PHY-3002 : Step(33): len = 186891, overlap = 1043.25
+PHY-3002 : Step(34): len = 184308, overlap = 1055.22
+PHY-3002 : Step(35): len = 182595, overlap = 1052.09
+PHY-3002 : Step(36): len = 181753, overlap = 1062.97
+PHY-3002 : Step(37): len = 180794, overlap = 1063.22
+PHY-3002 : Step(38): len = 178829, overlap = 1047.31
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.79444e-06
+PHY-3002 : Step(39): len = 181373, overlap = 1045.12
+PHY-3002 : Step(40): len = 192308, overlap = 1016.78
+PHY-3002 : Step(41): len = 198043, overlap = 974.875
+PHY-3002 : Step(42): len = 201545, overlap = 949.125
+PHY-3002 : Step(43): len = 204586, overlap = 912.344
+PHY-3002 : Step(44): len = 206789, overlap = 880.594
+PHY-3002 : Step(45): len = 205293, overlap = 871.188
+PHY-3002 : Step(46): len = 205116, overlap = 873.656
+PHY-3002 : Step(47): len = 203104, overlap = 897.531
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.58888e-06
+PHY-3002 : Step(48): len = 211763, overlap = 866.281
+PHY-3002 : Step(49): len = 227984, overlap = 806.406
+PHY-3002 : Step(50): len = 240565, overlap = 739.969
+PHY-3002 : Step(51): len = 249983, overlap = 694.625
+PHY-3002 : Step(52): len = 253470, overlap = 691.719
+PHY-3002 : Step(53): len = 254222, overlap = 681.969
+PHY-3002 : Step(54): len = 254893, overlap = 669.656
+PHY-3002 : Step(55): len = 253319, overlap = 666.969
+PHY-3002 : Step(56): len = 252851, overlap = 645.031
+PHY-3002 : Step(57): len = 251877, overlap = 634.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.11778e-05
+PHY-3002 : Step(58): len = 267827, overlap = 610.844
+PHY-3002 : Step(59): len = 284221, overlap = 600.625
+PHY-3002 : Step(60): len = 290750, overlap = 583.781
+PHY-3002 : Step(61): len = 294083, overlap = 551.625
+PHY-3002 : Step(62): len = 291882, overlap = 551.969
+PHY-3002 : Step(63): len = 290345, overlap = 542.25
+PHY-3002 : Step(64): len = 290495, overlap = 531.938
+PHY-3002 : Step(65): len = 293430, overlap = 521.125
+PHY-3002 : Step(66): len = 293682, overlap = 484.719
+PHY-3002 : Step(67): len = 294134, overlap = 472.031
+PHY-3002 : Step(68): len = 294413, overlap = 468.656
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.23555e-05
+PHY-3002 : Step(69): len = 311778, overlap = 452.312
+PHY-3002 : Step(70): len = 324792, overlap = 435.938
+PHY-3002 : Step(71): len = 326230, overlap = 408.344
+PHY-3002 : Step(72): len = 328732, overlap = 403.438
+PHY-3002 : Step(73): len = 328970, overlap = 383.094
+PHY-3002 : Step(74): len = 331583, overlap = 361.906
+PHY-3002 : Step(75): len = 331158, overlap = 360.562
+PHY-3002 : Step(76): len = 332357, overlap = 365.562
+PHY-3002 : Step(77): len = 332121, overlap = 364.75
+PHY-3002 : Step(78): len = 332993, overlap = 356.562
+PHY-3002 : Step(79): len = 331473, overlap = 359.969
+PHY-3002 : Step(80): len = 331987, overlap = 360.625
+PHY-3002 : Step(81): len = 332034, overlap = 366.938
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.4711e-05
+PHY-3002 : Step(82): len = 348184, overlap = 353.469
+PHY-3002 : Step(83): len = 361956, overlap = 312.156
+PHY-3002 : Step(84): len = 365610, overlap = 332
+PHY-3002 : Step(85): len = 368706, overlap = 338.969
+PHY-3002 : Step(86): len = 370879, overlap = 317.375
+PHY-3002 : Step(87): len = 373635, overlap = 298.188
+PHY-3002 : Step(88): len = 368632, overlap = 316.25
+PHY-3002 : Step(89): len = 370787, overlap = 310
+PHY-3002 : Step(90): len = 371824, overlap = 298.781
+PHY-3002 : Step(91): len = 373377, overlap = 294.469
+PHY-3002 : Step(92): len = 370726, overlap = 295.312
+PHY-3002 : Step(93): len = 371873, overlap = 291.781
+PHY-3002 : Step(94): len = 373471, overlap = 283.594
+PHY-3002 : Step(95): len = 376551, overlap = 280.656
+PHY-3002 : Step(96): len = 372671, overlap = 268.344
+PHY-3002 : Step(97): len = 372662, overlap = 270.469
+PHY-3002 : Step(98): len = 372656, overlap = 280.094
+PHY-3002 : Step(99): len = 373712, overlap = 274.781
+PHY-3002 : Step(100): len = 371559, overlap = 279.5
+PHY-3002 : Step(101): len = 371898, overlap = 287.688
+PHY-3002 : Step(102): len = 372276, overlap = 282.531
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.9422e-05
+PHY-3002 : Step(103): len = 389192, overlap = 269.906
+PHY-3002 : Step(104): len = 401336, overlap = 256.438
+PHY-3002 : Step(105): len = 400836, overlap = 261.781
+PHY-3002 : Step(106): len = 400735, overlap = 260.375
+PHY-3002 : Step(107): len = 402240, overlap = 250.594
+PHY-3002 : Step(108): len = 403208, overlap = 249.438
+PHY-3002 : Step(109): len = 401530, overlap = 246.469
+PHY-3002 : Step(110): len = 403545, overlap = 243.156
+PHY-3002 : Step(111): len = 405560, overlap = 237.906
+PHY-3002 : Step(112): len = 406735, overlap = 234.125
+PHY-3002 : Step(113): len = 404022, overlap = 246.812
+PHY-3002 : Step(114): len = 404666, overlap = 240.531
+PHY-3002 : Step(115): len = 405542, overlap = 238.969
+PHY-3002 : Step(116): len = 406095, overlap = 228.969
+PHY-3002 : Step(117): len = 403915, overlap = 224.031
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000168238
+PHY-3002 : Step(118): len = 414983, overlap = 225.094
+PHY-3002 : Step(119): len = 422719, overlap = 211.906
+PHY-3002 : Step(120): len = 422091, overlap = 203.594
+PHY-3002 : Step(121): len = 423515, overlap = 200
+PHY-3002 : Step(122): len = 427507, overlap = 198.125
+PHY-3002 : Step(123): len = 430994, overlap = 196.938
+PHY-3002 : Step(124): len = 429850, overlap = 196.562
+PHY-3002 : Step(125): len = 432166, overlap = 194.75
+PHY-3002 : Step(126): len = 436152, overlap = 196.906
+PHY-3002 : Step(127): len = 438172, overlap = 197.125
+PHY-3002 : Step(128): len = 435432, overlap = 193.812
+PHY-3002 : Step(129): len = 434929, overlap = 188.906
+PHY-3002 : Step(130): len = 436958, overlap = 194.438
+PHY-3002 : Step(131): len = 438368, overlap = 190.938
+PHY-3002 : Step(132): len = 435812, overlap = 197.375
+PHY-3002 : Step(133): len = 435439, overlap = 202.375
+PHY-3002 : Step(134): len = 436881, overlap = 207.156
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000336476
+PHY-3002 : Step(135): len = 445557, overlap = 197.312
+PHY-3002 : Step(136): len = 453836, overlap = 184.656
+PHY-3002 : Step(137): len = 455527, overlap = 190.344
+PHY-3002 : Step(138): len = 458388, overlap = 187.688
+PHY-3002 : Step(139): len = 462125, overlap = 177.031
+PHY-3002 : Step(140): len = 464985, overlap = 177.25
+PHY-3002 : Step(141): len = 465474, overlap = 177
+PHY-3002 : Step(142): len = 466345, overlap = 178
+PHY-3002 : Step(143): len = 467613, overlap = 177.625
+PHY-3002 : Step(144): len = 467912, overlap = 177.312
+PHY-3002 : Step(145): len = 467032, overlap = 177.344
+PHY-3002 : Step(146): len = 467225, overlap = 178.656
+PHY-3002 : Step(147): len = 467909, overlap = 173.25
+PHY-3002 : Step(148): len = 468274, overlap = 171.594
+PHY-3002 : Step(149): len = 467395, overlap = 169.688
+PHY-3002 : Step(150): len = 467453, overlap = 167.531
+PHY-3002 : Step(151): len = 468456, overlap = 160.531
+PHY-3002 : Step(152): len = 469145, overlap = 161.344
+PHY-3002 : Step(153): len = 468209, overlap = 158.25
+PHY-3002 : Step(154): len = 468069, overlap = 155.25
+PHY-3002 : Step(155): len = 468784, overlap = 158.188
+PHY-3002 : Step(156): len = 469485, overlap = 159.219
+PHY-3002 : Step(157): len = 468806, overlap = 157.938
+PHY-3002 : Step(158): len = 469078, overlap = 157.812
+PHY-3002 : Step(159): len = 470040, overlap = 156.375
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000663501
+PHY-3002 : Step(160): len = 475590, overlap = 148.656
+PHY-3002 : Step(161): len = 482886, overlap = 149.812
+PHY-3002 : Step(162): len = 484888, overlap = 144.344
+PHY-3002 : Step(163): len = 486371, overlap = 140.875
+PHY-3002 : Step(164): len = 488440, overlap = 139
+PHY-3002 : Step(165): len = 489468, overlap = 136.219
+PHY-3002 : Step(166): len = 489491, overlap = 137.188
+PHY-3002 : Step(167): len = 490266, overlap = 134.938
+PHY-3002 : Step(168): len = 492101, overlap = 138.312
+PHY-3002 : Step(169): len = 493147, overlap = 139.062
+PHY-3002 : Step(170): len = 493078, overlap = 141.75
+PHY-3002 : Step(171): len = 493265, overlap = 143.094
+PHY-3002 : Step(172): len = 493972, overlap = 141.406
+PHY-3002 : Step(173): len = 494265, overlap = 141.594
+PHY-3002 : Step(174): len = 494022, overlap = 141.219
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00113796
+PHY-3002 : Step(175): len = 497008, overlap = 140.938
+PHY-3002 : Step(176): len = 499811, overlap = 136.656
+PHY-3002 : Step(177): len = 501473, overlap = 134.844
+PHY-3002 : Step(178): len = 503218, overlap = 132.844
+PHY-3002 : Step(179): len = 504884, overlap = 128.562
+PHY-3002 : Step(180): len = 505708, overlap = 128.906
+PHY-3002 : Step(181): len = 505988, overlap = 130.312
+PHY-3002 : Step(182): len = 507575, overlap = 126.844
+PHY-3002 : Step(183): len = 509444, overlap = 128.875
+PHY-3002 : Step(184): len = 510219, overlap = 122.656
+PHY-3002 : Step(185): len = 510084, overlap = 126.125
+PHY-3002 : Step(186): len = 510312, overlap = 125.688
+PHY-3002 : Step(187): len = 511582, overlap = 123.656
+PHY-3002 : Step(188): len = 513244, overlap = 119.75
+PHY-3002 : Step(189): len = 512719, overlap = 119.312
+PHY-3002 : Step(190): len = 512550, overlap = 123.656
+PHY-3002 : Step(191): len = 513190, overlap = 121.625
+PHY-3002 : Step(192): len = 513651, overlap = 120.344
+PHY-3002 : Step(193): len = 513368, overlap = 119.406
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00187744
+PHY-3002 : Step(194): len = 515803, overlap = 114.594
+PHY-3002 : Step(195): len = 519871, overlap = 114.094
+PHY-3002 : Step(196): len = 520742, overlap = 112.094
+PHY-3002 : Step(197): len = 521345, overlap = 108.062
+PHY-3002 : Step(198): len = 522408, overlap = 107.594
+PHY-3002 : Step(199): len = 523106, overlap = 107.844
+PHY-3002 : Step(200): len = 523621, overlap = 108.094
+PHY-3002 : Step(201): len = 525475, overlap = 103.344
+PHY-3002 : Step(202): len = 527834, overlap = 102.781
+PHY-3002 : Step(203): len = 529329, overlap = 102.812
+PHY-3002 : Step(204): len = 529711, overlap = 102.875
+PHY-3002 : Step(205): len = 529922, overlap = 102.875
+PHY-3002 : Step(206): len = 530414, overlap = 105.25
+PHY-3001 : :::13::: Try harder cell spreading with beta_ = 0.00314549
+PHY-3002 : Step(207): len = 531986, overlap = 103.031
+PHY-3002 : Step(208): len = 534915, overlap = 105.656
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.012775s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (122.3%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 709176, over cnt = 1572(4%), over = 7106, worst = 60
+PHY-1001 : End global iterations;  0.683925s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (141.6%)
+
+PHY-1001 : Congestion index: top1 = 76.90, top5 = 60.06, top10 = 51.35, top15 = 45.95.
+PHY-3001 : End congestion estimation;  0.907445s wall, 1.187500s user + 0.000000s system = 1.187500s CPU (130.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.922532s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000126014
+PHY-3002 : Step(209): len = 642996, overlap = 69
+PHY-3002 : Step(210): len = 643481, overlap = 61.5625
+PHY-3002 : Step(211): len = 638490, overlap = 58.8125
+PHY-3002 : Step(212): len = 634120, overlap = 57.5625
+PHY-3002 : Step(213): len = 633360, overlap = 60.0625
+PHY-3002 : Step(214): len = 631172, overlap = 64.0625
+PHY-3002 : Step(215): len = 627087, overlap = 65.2188
+PHY-3002 : Step(216): len = 622316, overlap = 63.0312
+PHY-3002 : Step(217): len = 619071, overlap = 60.2188
+PHY-3002 : Step(218): len = 615558, overlap = 52.875
+PHY-3002 : Step(219): len = 611383, overlap = 45.1875
+PHY-3002 : Step(220): len = 608241, overlap = 40.6875
+PHY-3002 : Step(221): len = 604940, overlap = 34
+PHY-3002 : Step(222): len = 601309, overlap = 29.0625
+PHY-3002 : Step(223): len = 599604, overlap = 29.2188
+PHY-3002 : Step(224): len = 598670, overlap = 30.0625
+PHY-3002 : Step(225): len = 597011, overlap = 31.0938
+PHY-3002 : Step(226): len = 596144, overlap = 33.4688
+PHY-3002 : Step(227): len = 594872, overlap = 36.625
+PHY-3002 : Step(228): len = 592840, overlap = 38.4375
+PHY-3002 : Step(229): len = 591618, overlap = 37.625
+PHY-3002 : Step(230): len = 590471, overlap = 35.5
+PHY-3002 : Step(231): len = 589234, overlap = 38.7188
+PHY-3002 : Step(232): len = 587499, overlap = 39.9062
+PHY-3002 : Step(233): len = 586339, overlap = 41.9688
+PHY-3002 : Step(234): len = 585071, overlap = 44.3125
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000252027
+PHY-3002 : Step(235): len = 587188, overlap = 43.75
+PHY-3002 : Step(236): len = 588637, overlap = 42.625
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 77/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 678080, over cnt = 2515(7%), over = 10713, worst = 67
+PHY-1001 : End global iterations;  1.694249s wall, 2.343750s user + 0.015625s system = 2.359375s CPU (139.3%)
+
+PHY-1001 : Congestion index: top1 = 78.69, top5 = 61.50, top10 = 53.80, top15 = 49.16.
+PHY-3001 : End congestion estimation;  1.968646s wall, 2.609375s user + 0.015625s system = 2.625000s CPU (133.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.878229s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (101.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 8.69288e-05
+PHY-3002 : Step(237): len = 587823, overlap = 265.969
+PHY-3002 : Step(238): len = 592528, overlap = 231.406
+PHY-3002 : Step(239): len = 589888, overlap = 220.094
+PHY-3002 : Step(240): len = 587284, overlap = 211.719
+PHY-3002 : Step(241): len = 587157, overlap = 196.5
+PHY-3002 : Step(242): len = 584207, overlap = 185.344
+PHY-3002 : Step(243): len = 582173, overlap = 170.969
+PHY-3002 : Step(244): len = 580193, overlap = 163.375
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000173858
+PHY-3002 : Step(245): len = 580980, overlap = 158
+PHY-3002 : Step(246): len = 583251, overlap = 152.219
+PHY-3002 : Step(247): len = 585808, overlap = 146.938
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000347715
+PHY-3002 : Step(248): len = 591049, overlap = 133
+PHY-3002 : Step(249): len = 597824, overlap = 122.812
+PHY-3002 : Step(250): len = 604738, overlap = 110.656
+PHY-3002 : Step(251): len = 604068, overlap = 108.562
+PHY-3002 : Step(252): len = 603117, overlap = 104.5
+PHY-3002 : Step(253): len = 602459, overlap = 98.6875
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84693, tnet num: 20087, tinst num: 17695, tnode num: 114800, tedge num: 135904.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.430243s wall, 1.359375s user + 0.062500s system = 1.421875s CPU (99.4%)
+
+RUN-1004 : used memory is 579 MB, reserved memory is 560 MB, peak memory is 716 MB
+OPT-1001 : Total overflow 434.88 peak overflow 4.06
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1530/20265.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 706448, over cnt = 2944(8%), over = 10453, worst = 29
+PHY-1001 : End global iterations;  1.135131s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (156.9%)
+
+PHY-1001 : Congestion index: top1 = 67.41, top5 = 54.41, top10 = 49.11, top15 = 45.83.
+PHY-1001 : End incremental global routing;  1.479478s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (143.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20087 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  1.297821s wall, 1.296875s user + 0.000000s system = 1.296875s CPU (99.9%)
+
+OPT-1001 : 52 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17558 has valid locations, 326 needs to be replaced
+PHY-3001 : design contains 17969 instances, 7523 luts, 9231 seqs, 1069 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6051 pins
+PHY-3001 : Found 1233 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 627318
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16458/20539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720672, over cnt = 2987(8%), over = 10510, worst = 29
+PHY-1001 : End global iterations;  0.249024s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (119.2%)
+
+PHY-1001 : Congestion index: top1 = 67.26, top5 = 54.60, top10 = 49.31, top15 = 46.07.
+PHY-3001 : End congestion estimation;  0.498021s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (109.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85819, tnet num: 20361, tinst num: 17969, tnode num: 116489, tedge num: 137608.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.447014s wall, 1.406250s user + 0.046875s system = 1.453125s CPU (100.4%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 611 MB, peak memory is 721 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.405956s wall, 2.328125s user + 0.078125s system = 2.406250s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(254): len = 626177, overlap = 0.25
+PHY-3002 : Step(255): len = 625746, overlap = 0.5625
+PHY-3002 : Step(256): len = 625478, overlap = 0.3125
+PHY-3002 : Step(257): len = 625280, overlap = 0.25
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16574/20539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 717360, over cnt = 2977(8%), over = 10563, worst = 29
+PHY-1001 : End global iterations;  0.195635s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (135.8%)
+
+PHY-1001 : Congestion index: top1 = 67.91, top5 = 54.86, top10 = 49.56, top15 = 46.30.
+PHY-3001 : End congestion estimation;  0.478222s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (114.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.923071s wall, 0.859375s user + 0.062500s system = 0.921875s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000421337
+PHY-3002 : Step(258): len = 625079, overlap = 100.344
+PHY-3002 : Step(259): len = 625057, overlap = 100.656
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000842674
+PHY-3002 : Step(260): len = 625191, overlap = 100.781
+PHY-3002 : Step(261): len = 625698, overlap = 100.594
+PHY-3001 : Final: Len = 625698, Over = 100.594
+PHY-3001 : End incremental placement;  4.950054s wall, 5.218750s user + 0.218750s system = 5.437500s CPU (109.8%)
+
+OPT-1001 : Total overflow 440.28 peak overflow 4.06
+OPT-1001 : End high-fanout net optimization;  8.260466s wall, 9.265625s user + 0.234375s system = 9.500000s CPU (115.0%)
+
+OPT-1001 : Current memory(MB): used = 724, reserve = 710, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16512/20539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 719688, over cnt = 2912(8%), over = 9559, worst = 29
+PHY-1002 : len = 766760, over cnt = 1954(5%), over = 5033, worst = 23
+PHY-1002 : len = 811760, over cnt = 701(1%), over = 1488, worst = 13
+PHY-1002 : len = 830872, over cnt = 93(0%), over = 147, worst = 11
+PHY-1002 : len = 833456, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.616632s wall, 2.296875s user + 0.000000s system = 2.296875s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 54.98, top5 = 48.69, top10 = 45.26, top15 = 43.13.
+OPT-1001 : End congestion update;  1.873574s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (135.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.793763s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.4%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 125 cells processed and 17658 slack improved
+OPT-0007 : Iter 2: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 42 cells processed and 4700 slack improved
+OPT-0007 : Iter 3: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 23 cells processed and 1250 slack improved
+OPT-0007 : Iter 4: improved WNS -1018 TNS -1528 NUM_FEPS 2 with 2 cells processed and 700 slack improved
+OPT-1001 : End bottleneck based optimization;  3.209958s wall, 3.750000s user + 0.000000s system = 3.750000s CPU (116.8%)
+
+OPT-1001 : Current memory(MB): used = 699, reserve = 689, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16541/20545.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 834880, over cnt = 106(0%), over = 135, worst = 4
+PHY-1002 : len = 834672, over cnt = 62(0%), over = 71, worst = 3
+PHY-1002 : len = 835104, over cnt = 25(0%), over = 28, worst = 2
+PHY-1002 : len = 835536, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 835768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.721607s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.8%)
+
+PHY-1001 : Congestion index: top1 = 54.83, top5 = 48.52, top10 = 45.21, top15 = 43.14.
+OPT-1001 : End congestion update;  0.993649s wall, 1.015625s user + 0.000000s system = 1.015625s CPU (102.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20367 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.794356s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (100.3%)
+
+OPT-0007 : Start: WNS -1018 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1478 NUM_FEPS 2 with 13 cells processed and 3250 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1478 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.903544s wall, 1.921875s user + 0.000000s system = 1.921875s CPU (101.0%)
+
+OPT-1001 : Current memory(MB): used = 712, reserve = 698, peak = 739.
+OPT-1001 : End physical optimization;  15.103115s wall, 16.703125s user + 0.296875s system = 17.000000s CPU (112.6%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7523 LUT to BLE ...
+SYN-4008 : Packed 7523 LUT and 3148 SEQ to BLE.
+SYN-4003 : Packing 6089 remaining SEQ's ...
+SYN-4005 : Packed 3597 SEQ with LUT/SLICE
+SYN-4006 : 1084 single LUT's are left
+SYN-4006 : 2492 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10015/13828 primitive instances ...
+PHY-3001 : End packing;  1.890516s wall, 1.578125s user + 0.000000s system = 1.578125s CPU (83.5%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6915 instances
+RUN-1001 : 3384 mslices, 3383 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17531 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9964 nets have 2 pins
+RUN-1001 : 5728 nets have [3 - 5] pins
+RUN-1001 : 1165 nets have [6 - 10] pins
+RUN-1001 : 296 nets have [11 - 20] pins
+RUN-1001 : 345 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 6913 instances, 6767 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3589 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 637965, Over = 285.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 7635/17531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 788800, over cnt = 1855(5%), over = 3037, worst = 9
+PHY-1002 : len = 796664, over cnt = 1184(3%), over = 1712, worst = 5
+PHY-1002 : len = 811056, over cnt = 354(1%), over = 486, worst = 5
+PHY-1002 : len = 815488, over cnt = 189(0%), over = 254, worst = 5
+PHY-1002 : len = 820536, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.563320s wall, 2.265625s user + 0.046875s system = 2.312500s CPU (147.9%)
+
+PHY-1001 : Congestion index: top1 = 56.64, top5 = 49.12, top10 = 45.32, top15 = 42.91.
+PHY-3001 : End congestion estimation;  1.957011s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (138.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73684, tnet num: 17353, tinst num: 6913, tnode num: 96151, tedge num: 123697.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.688085s wall, 1.671875s user + 0.015625s system = 1.687500s CPU (100.0%)
+
+RUN-1004 : used memory is 621 MB, reserved memory is 615 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.548666s wall, 2.531250s user + 0.015625s system = 2.546875s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.61717e-05
+PHY-3002 : Step(262): len = 627787, overlap = 289.5
+PHY-3002 : Step(263): len = 622422, overlap = 284.25
+PHY-3002 : Step(264): len = 619056, overlap = 286.75
+PHY-3002 : Step(265): len = 616906, overlap = 280.75
+PHY-3002 : Step(266): len = 616304, overlap = 282.25
+PHY-3002 : Step(267): len = 614005, overlap = 280.5
+PHY-3002 : Step(268): len = 609763, overlap = 271.75
+PHY-3002 : Step(269): len = 606993, overlap = 267.25
+PHY-3002 : Step(270): len = 605129, overlap = 275.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.23435e-05
+PHY-3002 : Step(271): len = 609267, overlap = 267.25
+PHY-3002 : Step(272): len = 616119, overlap = 255.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000184687
+PHY-3002 : Step(273): len = 620448, overlap = 242.75
+PHY-3002 : Step(274): len = 630557, overlap = 235.5
+PHY-3002 : Step(275): len = 636737, overlap = 230.5
+PHY-3002 : Step(276): len = 638251, overlap = 228
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.362767s wall, 0.343750s user + 0.562500s system = 0.906250s CPU (249.8%)
+
+PHY-3001 : Trial Legalized: Len = 731094
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 755/17531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 849216, over cnt = 2603(7%), over = 4411, worst = 9
+PHY-1002 : len = 866696, over cnt = 1522(4%), over = 2220, worst = 6
+PHY-1002 : len = 880048, over cnt = 787(2%), over = 1122, worst = 6
+PHY-1002 : len = 889208, over cnt = 391(1%), over = 555, worst = 5
+PHY-1002 : len = 897488, over cnt = 15(0%), over = 18, worst = 3
+PHY-1001 : End global iterations;  2.261783s wall, 3.406250s user + 0.031250s system = 3.437500s CPU (152.0%)
+
+PHY-1001 : Congestion index: top1 = 54.09, top5 = 49.01, top10 = 46.25, top15 = 44.40.
+PHY-3001 : End congestion estimation;  2.722429s wall, 3.859375s user + 0.031250s system = 3.890625s CPU (142.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.872790s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000159953
+PHY-3002 : Step(277): len = 701145, overlap = 43.5
+PHY-3002 : Step(278): len = 683955, overlap = 73
+PHY-3002 : Step(279): len = 669245, overlap = 100.5
+PHY-3002 : Step(280): len = 658868, overlap = 132.25
+PHY-3002 : Step(281): len = 653090, overlap = 149.5
+PHY-3002 : Step(282): len = 649013, overlap = 169.5
+PHY-3002 : Step(283): len = 646907, overlap = 174.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000319907
+PHY-3002 : Step(284): len = 652157, overlap = 167.75
+PHY-3002 : Step(285): len = 657830, overlap = 165.5
+PHY-3002 : Step(286): len = 659123, overlap = 166.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000637015
+PHY-3002 : Step(287): len = 663386, overlap = 165.75
+PHY-3002 : Step(288): len = 674215, overlap = 164
+PHY-3002 : Step(289): len = 678778, overlap = 165
+PHY-3002 : Step(290): len = 680215, overlap = 165
+PHY-3002 : Step(291): len = 682109, overlap = 171.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.034096s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (91.7%)
+
+PHY-3001 : Legalized: Len = 710930, Over = 0
+PHY-3001 : Spreading special nets. 449 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.103197s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (106.0%)
+
+PHY-3001 : 652 instances has been re-located, deltaX = 239, deltaY = 366, maxDist = 3.
+PHY-3001 : Final: Len = 719770, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73684, tnet num: 17353, tinst num: 6916, tnode num: 96151, tedge num: 123697.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.880634s wall, 1.875000s user + 0.000000s system = 1.875000s CPU (99.7%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 601 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 3210/17531.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 847456, over cnt = 2474(7%), over = 4058, worst = 8
+PHY-1002 : len = 865104, over cnt = 1194(3%), over = 1610, worst = 8
+PHY-1002 : len = 879368, over cnt = 350(0%), over = 442, worst = 6
+PHY-1002 : len = 885512, over cnt = 20(0%), over = 22, worst = 2
+PHY-1002 : len = 886048, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.189014s wall, 3.031250s user + 0.015625s system = 3.046875s CPU (139.2%)
+
+PHY-1001 : Congestion index: top1 = 52.52, top5 = 47.48, top10 = 44.71, top15 = 42.93.
+PHY-1001 : End incremental global routing;  2.792835s wall, 3.406250s user + 0.015625s system = 3.421875s CPU (122.5%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17353 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.898468s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (99.1%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6824 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3665 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 723088
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15957/17562.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 890208, over cnt = 76(0%), over = 81, worst = 2
+PHY-1002 : len = 890488, over cnt = 26(0%), over = 26, worst = 1
+PHY-1002 : len = 890656, over cnt = 11(0%), over = 11, worst = 1
+PHY-1002 : len = 890792, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.585416s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (104.1%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.49, top10 = 44.80, top15 = 43.00.
+PHY-3001 : End congestion estimation;  0.891615s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (103.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73890, tnet num: 17384, tinst num: 6935, tnode num: 96414, tedge num: 124019.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.856946s wall, 1.828125s user + 0.015625s system = 1.843750s CPU (99.3%)
+
+RUN-1004 : used memory is 666 MB, reserved memory is 665 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17384 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.741160s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (99.8%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(292): len = 722300, overlap = 0.25
+PHY-3002 : Step(293): len = 721916, overlap = 0.75
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15944/17562.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 888208, over cnt = 56(0%), over = 74, worst = 4
+PHY-1002 : len = 888448, over cnt = 23(0%), over = 26, worst = 3
+PHY-1002 : len = 888704, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 888784, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 888800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.774043s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.9%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.59, top10 = 44.85, top15 = 43.03.
+PHY-3001 : End congestion estimation;  1.087440s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (102.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17384 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868910s wall, 0.875000s user + 0.000000s system = 0.875000s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00010769
+PHY-3002 : Step(294): len = 721814, overlap = 2.25
+PHY-3002 : Step(295): len = 721830, overlap = 2.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000215381
+PHY-3002 : Step(296): len = 721867, overlap = 2.5
+PHY-3002 : Step(297): len = 721867, overlap = 2.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005272s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 721920, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058756s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.4%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 2, deltaY = 2, maxDist = 1.
+PHY-3001 : Final: Len = 722020, Over = 0
+PHY-3001 : End incremental placement;  6.087968s wall, 6.078125s user + 0.187500s system = 6.265625s CPU (102.9%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.295020s wall, 10.890625s user + 0.218750s system = 11.109375s CPU (107.9%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 734, peak = 747.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15922/17562.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 889416, over cnt = 58(0%), over = 85, worst = 6
+PHY-1002 : len = 889688, over cnt = 23(0%), over = 23, worst = 1
+PHY-1002 : len = 889808, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 889856, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.600182s wall, 0.625000s user + 0.015625s system = 0.640625s CPU (106.7%)
+
+PHY-1001 : Congestion index: top1 = 52.46, top5 = 47.51, top10 = 44.75, top15 = 42.97.
+OPT-1001 : End congestion update;  0.956862s wall, 0.953125s user + 0.031250s system = 0.984375s CPU (102.9%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17384 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.767409s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.8%)
+
+OPT-0007 : Start: WNS -1033 TNS -1647 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3665 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 729486, Over = 0
+PHY-3001 : Spreading special nets. 32 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.084032s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (93.0%)
+
+PHY-3001 : 46 instances has been re-located, deltaX = 23, deltaY = 38, maxDist = 3.
+PHY-3001 : Final: Len = 730874, Over = 0
+PHY-3001 : End incremental legalization;  0.613477s wall, 0.687500s user + 0.000000s system = 0.687500s CPU (112.1%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 59 cells processed and 20693 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3665 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 731316, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062896s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.4%)
+
+PHY-3001 : 12 instances has been re-located, deltaX = 4, deltaY = 12, maxDist = 2.
+PHY-3001 : Final: Len = 731608, Over = 0
+PHY-3001 : End incremental legalization;  0.397410s wall, 0.468750s user + 0.031250s system = 0.500000s CPU (125.8%)
+
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 24 cells processed and 2993 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6847 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6935 instances, 6786 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3665 pins
+PHY-3001 : Found 503 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 731332, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.065163s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (95.9%)
+
+PHY-3001 : 9 instances has been re-located, deltaX = 6, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 731608, Over = 0
+PHY-3001 : End incremental legalization;  0.415452s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (112.8%)
+
+OPT-0007 : Iter 3: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 10 cells processed and 500 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6852 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6940 instances, 6791 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3665 pins
+PHY-3001 : Found 508 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 731944, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.059632s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (104.8%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 1, deltaY = 5, maxDist = 2.
+PHY-3001 : Final: Len = 732080, Over = 0
+PHY-3001 : End incremental legalization;  0.411513s wall, 0.484375s user + 0.015625s system = 0.500000s CPU (121.5%)
+
+OPT-0007 : Iter 4: improved WNS -1033 TNS -1618 NUM_FEPS 2 with 5 cells processed and 866 slack improved
+OPT-1001 : End bottleneck based optimization;  4.177217s wall, 4.562500s user + 0.078125s system = 4.640625s CPU (111.1%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 732, peak = 747.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15508/17564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 900784, over cnt = 176(0%), over = 233, worst = 5
+PHY-1002 : len = 901192, over cnt = 88(0%), over = 108, worst = 4
+PHY-1002 : len = 902304, over cnt = 17(0%), over = 18, worst = 2
+PHY-1002 : len = 902544, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 902680, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.835044s wall, 0.953125s user + 0.015625s system = 0.968750s CPU (116.0%)
+
+PHY-1001 : Congestion index: top1 = 52.50, top5 = 47.65, top10 = 44.88, top15 = 43.11.
+OPT-1001 : End congestion update;  1.156674s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (110.8%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.775887s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.7%)
+
+OPT-0007 : Start: WNS -1033 TNS -1647 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6852 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6940 instances, 6791 slices, 221 macros(1069 instances: 698 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3665 pins
+PHY-3001 : Found 508 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 75%
+PHY-3001 : Initial: Len = 732020, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062521s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.0%)
+
+PHY-3001 : 15 instances has been re-located, deltaX = 9, deltaY = 13, maxDist = 2.
+PHY-3001 : Final: Len = 732444, Over = 0
+PHY-3001 : End incremental legalization;  0.387598s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.8%)
+
+OPT-0007 : Iter 1: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 16 cells processed and 1246 slack improved
+OPT-0007 : Iter 2: improved WNS -1033 TNS -1568 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.453380s wall, 2.578125s user + 0.015625s system = 2.593750s CPU (105.7%)
+
+OPT-1001 : Current memory(MB): used = 738, reserve = 732, peak = 747.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.740160s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.3%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Reuse net number 15908/17564.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 902968, over cnt = 56(0%), over = 66, worst = 3
+PHY-1002 : len = 902808, over cnt = 25(0%), over = 26, worst = 2
+PHY-1002 : len = 903024, over cnt = 10(0%), over = 10, worst = 1
+PHY-1002 : len = 903208, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.601919s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (106.4%)
+
+PHY-1001 : Congestion index: top1 = 52.39, top5 = 47.69, top10 = 44.95, top15 = 43.17.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.716988s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (100.2%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1033 TNS -1668 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 52.000000
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1033ps with logic level 2 
+RUN-1001 :       #2 path slack -947ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17564 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17564 nets
+OPT-1001 : End physical optimization;  21.540773s wall, 22.640625s user + 0.343750s system = 22.984375s CPU (106.7%)
+
+RUN-1003 : finish command "place" in  63.880089s wall, 88.281250s user + 6.187500s system = 94.468750s CPU (147.9%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 595 MB, peak memory is 747 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.691045s wall, 2.906250s user + 0.000000s system = 2.906250s CPU (171.9%)
+
+RUN-1004 : used memory is 611 MB, reserved memory is 596 MB, peak memory is 747 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6942 instances
+RUN-1001 : 3399 mslices, 3392 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17564 nets
+RUN-6002 WARNING: There are 1 undriven nets.
+RUN-6004 WARNING: There are 21 nets with only 1 pin.
+RUN-1001 : 9966 nets have 2 pins
+RUN-1001 : 5738 nets have [3 - 5] pins
+RUN-1001 : 1170 nets have [6 - 10] pins
+RUN-1001 : 305 nets have [11 - 20] pins
+RUN-1001 : 356 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73924, tnet num: 17386, tinst num: 6940, tnode num: 96464, tedge num: 124072.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.598933s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (100.7%)
+
+RUN-1004 : used memory is 630 MB, reserved memory is 633 MB, peak memory is 747 MB
+PHY-1001 : 3399 mslices, 3392 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-5010 WARNING: Net U_rgb_to_csi_pakage/S_rgb_data_4d[20] is skipped due to 0 input or output
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 842040, over cnt = 2634(7%), over = 4352, worst = 8
+PHY-1002 : len = 859160, over cnt = 1596(4%), over = 2322, worst = 8
+PHY-1002 : len = 877544, over cnt = 615(1%), over = 895, worst = 6
+PHY-1002 : len = 890768, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 890912, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.857361s wall, 3.906250s user + 0.015625s system = 3.921875s CPU (137.3%)
+
+PHY-1001 : Congestion index: top1 = 52.72, top5 = 47.50, top10 = 44.75, top15 = 43.00.
+PHY-1001 : End global routing;  3.201579s wall, 4.250000s user + 0.015625s system = 4.265625s CPU (133.2%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 721, reserve = 718, peak = 747.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 998, reserve = 995, peak = 998.
+PHY-1001 : End build detailed router design. 3.972923s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267784, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.134736s wall, 5.140625s user + 0.000000s system = 5.140625s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267840, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.420838s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1033, reserve = 1031, peak = 1033.
+PHY-1001 : End phase 1; 5.567949s wall, 5.578125s user + 0.000000s system = 5.578125s CPU (100.2%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 52% nets.
+PHY-1001 : Routed 61% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.33203e+06, over cnt = 1834(0%), over = 1845, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1047, reserve = 1043, peak = 1047.
+PHY-1001 : End initial routed; 26.313709s wall, 61.093750s user + 0.406250s system = 61.500000s CPU (233.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16490(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.921   |  -4.131   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.285135s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1056, reserve = 1052, peak = 1056.
+PHY-1001 : End phase 2; 29.598906s wall, 64.375000s user + 0.406250s system = 64.781250s CPU (218.9%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -1.798ns STNS -3.894ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.143304s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (98.1%)
+
+PHY-1022 : len = 2.33205e+06, over cnt = 1837(0%), over = 1848, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.415690s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (101.5%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.29915e+06, over cnt = 702(0%), over = 703, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.315958s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (193.5%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.29576e+06, over cnt = 164(0%), over = 164, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.642409s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (153.2%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.29691e+06, over cnt = 10(0%), over = 10, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.317392s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (118.2%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.29699e+06, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.185832s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (117.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.29708e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 5; 0.202349s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (100.4%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16490(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.798   |  -3.894   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.233045s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (99.6%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 545 feed throughs used by 409 nets
+PHY-1001 : End commit to database; 2.245402s wall, 2.234375s user + 0.000000s system = 2.234375s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1160, reserve = 1160, peak = 1160.
+PHY-1001 : End phase 3; 8.964134s wall, 10.609375s user + 0.000000s system = 10.609375s CPU (118.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.798ns STNS -3.894ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.140153s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (100.3%)
+
+PHY-1022 : len = 2.29708e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.379033s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.9%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.798ns, -3.894ns, 3}
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16490(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.798   |  -3.894   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.256000s wall, 3.250000s user + 0.000000s system = 3.250000s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 545 feed throughs used by 409 nets
+PHY-1001 : End commit to database; 2.318998s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (99.7%)
+
+PHY-1001 : Current memory(MB): used = 1168, reserve = 1168, peak = 1168.
+PHY-1001 : End phase 4; 5.981035s wall, 5.984375s user + 0.000000s system = 5.984375s CPU (100.1%)
+
+PHY-1003 : Routed, final wirelength = 2.29708e+06
+PHY-1001 : Current memory(MB): used = 1170, reserve = 1171, peak = 1170.
+PHY-1001 : End export database. 0.061851s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.0%)
+
+PHY-1001 : End detail routing;  54.537347s wall, 90.953125s user + 0.421875s system = 91.375000s CPU (167.5%)
+
+RUN-1003 : finish command "route" in  60.563148s wall, 97.906250s user + 0.437500s system = 98.343750s CPU (162.4%)
+
+RUN-1004 : used memory is 1093 MB, reserved memory is 1089 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10263   out of  19600   52.36%
+#reg                     9387   out of  19600   47.89%
+#le                     12684
+  #lut only              3297   out of  12684   25.99%
+  #reg only              2421   out of  12684   19.09%
+  #lut&reg               6966   out of  12684   54.92%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    18
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1812
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1418
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1346
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               941
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    140
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               31
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/reg2_syn_200.f1                          3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/reg19_syn_67.f0                          3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P107       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P133       LVCMOS33           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       OREG    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       NONE    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       NONE    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P143       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P104       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P172       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P83        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P19        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12684  |9242    |1021    |9418    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |546    |451     |23      |443     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |101    |85      |4       |89      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |30     |30      |0       |21      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |13     |13      |0       |9       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |780    |367     |96      |589     |0       |0       |
+|    u_ADconfig                |AD_config            |194    |114     |25      |146     |0       |0       |
+|    u_gen_sp                  |gen_sp               |268    |150     |71      |125     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |753    |392     |96      |569     |0       |0       |
+|    u_ADconfig                |AD_config            |177    |116     |25      |129     |0       |0       |
+|    u_gen_sp                  |gen_sp               |258    |144     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3123   |2543    |303     |2046    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |6      |2       |0       |6       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |165    |108     |14      |132     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |0       |0       |4       |0       |0       |
+|    u_sort                    |sort                 |2942   |2423    |289     |1898    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |6      |1       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |1       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2435   |2042    |253     |1535    |22      |1       |
+|        channelPart           |channel_part_8478    |139    |133     |3       |120     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |44      |0       |1       |
+|        ram_switch            |ram_switch           |1940   |1630    |197     |1160    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |222    |193     |27      |122     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |7       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |16      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |14      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|          insert              |insert               |940    |659     |170     |633     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |778    |778     |0       |405     |0       |0       |
+|        read_ram_i            |read_ram             |268    |216     |44      |182     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |218    |178     |40      |148     |0       |0       |
+|          read_ram_data       |read_ram_data        |50     |38      |4       |34      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |376    |267     |36      |275     |3       |0       |
+|        u0_soft_n             |cdc_sync             |5      |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3369   |2707    |346     |2072    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |184    |125     |17      |146     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|    u_sort                    |sort_rev             |3151   |2552    |329     |1892    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |2       |0       |2       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2683   |2232    |287     |1536    |22      |0       |
+|        channelPart           |channel_part_8478    |215    |208     |3       |136     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |42      |0       |0       |
+|        ram_switch            |ram_switch           |2021   |1691    |197     |1121    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |205    |178     |27      |95      |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |7       |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |16      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |14     |11      |3       |6       |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|          insert              |insert               |987    |684     |170     |671     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |829    |829     |0       |355     |0       |0       |
+|        read_ram_i            |read_ram_rev         |360    |260     |78      |208     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |293    |215     |70      |160     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |67     |45      |8       |48      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9904  
+    #2         2       3844  
+    #3         3       1376  
+    #4         4       515   
+    #5        5-10     1221  
+    #6       11-50     579   
+    #7       51-100     28   
+    #8        >500      1    
+  Average     2.91           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.083530s wall, 3.578125s user + 0.000000s system = 3.578125s CPU (171.7%)
+
+RUN-1004 : used memory is 1095 MB, reserved memory is 1090 MB, peak memory is 1170 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73924, tnet num: 17386, tinst num: 6940, tnode num: 96464, tedge num: 124072.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.611871s wall, 1.609375s user + 0.000000s system = 1.609375s CPU (99.8%)
+
+RUN-1004 : used memory is 1099 MB, reserved memory is 1095 MB, peak memory is 1170 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17386 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.541871s wall, 1.515625s user + 0.031250s system = 1.546875s CPU (100.3%)
+
+RUN-1004 : used memory is 1106 MB, reserved memory is 1101 MB, peak memory is 1170 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6940
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17564, pip num: 172612
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 545
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3254 valid insts, and 479353 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.950750s wall, 54.968750s user + 0.125000s system = 55.093750s CPU (553.7%)
+
+RUN-1004 : used memory is 1272 MB, reserved memory is 1268 MB, peak memory is 1388 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_141951.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_143236.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_143236.log
new file mode 100644
index 0000000..a39df0d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_143236.log
@@ -0,0 +1,2040 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:32:36 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.312028s wall, 2.171875s user + 0.140625s system = 2.312500s CPU (100.0%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 314 MB, peak memory is 348 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 17673 instances
+RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20251 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13284 nets have 2 pins
+RUN-1001 : 5550 nets have [3 - 5] pins
+RUN-1001 : 1004 nets have [6 - 10] pins
+RUN-1001 : 162 nets have [11 - 20] pins
+RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
+PHY-0007 : Cell area utilization is 48%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.139115s wall, 1.109375s user + 0.031250s system = 1.140625s CPU (100.1%)
+
+RUN-1004 : used memory is 537 MB, reserved memory is 513 MB, peak memory is 537 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.925518s wall, 1.890625s user + 0.031250s system = 1.921875s CPU (99.8%)
+
+PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.10768e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 17671.
+PHY-3001 : Level 1 #clusters 2030.
+PHY-3001 : End clustering;  0.126882s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (147.8%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 48%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.29146e+06, overlap = 461.062
+PHY-3002 : Step(2): len = 1.18768e+06, overlap = 538.719
+PHY-3002 : Step(3): len = 847496, overlap = 601.531
+PHY-3002 : Step(4): len = 796371, overlap = 611.094
+PHY-3002 : Step(5): len = 612777, overlap = 757.688
+PHY-3002 : Step(6): len = 531909, overlap = 803.406
+PHY-3002 : Step(7): len = 457589, overlap = 905.219
+PHY-3002 : Step(8): len = 422578, overlap = 999.906
+PHY-3002 : Step(9): len = 379230, overlap = 1060.59
+PHY-3002 : Step(10): len = 341979, overlap = 1101.22
+PHY-3002 : Step(11): len = 297597, overlap = 1180.19
+PHY-3002 : Step(12): len = 277502, overlap = 1217.03
+PHY-3002 : Step(13): len = 249755, overlap = 1254.81
+PHY-3002 : Step(14): len = 236212, overlap = 1296.62
+PHY-3002 : Step(15): len = 208788, overlap = 1321.03
+PHY-3002 : Step(16): len = 198940, overlap = 1344.62
+PHY-3002 : Step(17): len = 177274, overlap = 1406.19
+PHY-3002 : Step(18): len = 174778, overlap = 1440.38
+PHY-3002 : Step(19): len = 154507, overlap = 1455.12
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.13963e-06
+PHY-3002 : Step(20): len = 154444, overlap = 1443.38
+PHY-3002 : Step(21): len = 184130, overlap = 1294.09
+PHY-3002 : Step(22): len = 194065, overlap = 1212.47
+PHY-3002 : Step(23): len = 201594, overlap = 1185.81
+PHY-3002 : Step(24): len = 202231, overlap = 1140.09
+PHY-3002 : Step(25): len = 200132, overlap = 1105.69
+PHY-3002 : Step(26): len = 197351, overlap = 1086.12
+PHY-3002 : Step(27): len = 193037, overlap = 1081.72
+PHY-3002 : Step(28): len = 191796, overlap = 1070.53
+PHY-3002 : Step(29): len = 190507, overlap = 1101.28
+PHY-3002 : Step(30): len = 189419, overlap = 1101.88
+PHY-3002 : Step(31): len = 187271, overlap = 1111.34
+PHY-3002 : Step(32): len = 185878, overlap = 1098.69
+PHY-3002 : Step(33): len = 183955, overlap = 1104.06
+PHY-3002 : Step(34): len = 183280, overlap = 1107.59
+PHY-3002 : Step(35): len = 182719, overlap = 1089.31
+PHY-3002 : Step(36): len = 181562, overlap = 1070.84
+PHY-3002 : Step(37): len = 180967, overlap = 1073.81
+PHY-3002 : Step(38): len = 179924, overlap = 1084.84
+PHY-3002 : Step(39): len = 179519, overlap = 1092.03
+PHY-3002 : Step(40): len = 178314, overlap = 1125.12
+PHY-3002 : Step(41): len = 178054, overlap = 1135.06
+PHY-3002 : Step(42): len = 176858, overlap = 1139.09
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.27926e-06
+PHY-3002 : Step(43): len = 181505, overlap = 1122.25
+PHY-3002 : Step(44): len = 192539, overlap = 1075.25
+PHY-3002 : Step(45): len = 196660, overlap = 1020.47
+PHY-3002 : Step(46): len = 201430, overlap = 977.594
+PHY-3002 : Step(47): len = 203308, overlap = 976.469
+PHY-3002 : Step(48): len = 204662, overlap = 986.375
+PHY-3002 : Step(49): len = 205411, overlap = 979.188
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.55852e-06
+PHY-3002 : Step(50): len = 211563, overlap = 951.719
+PHY-3002 : Step(51): len = 231785, overlap = 876.5
+PHY-3002 : Step(52): len = 241368, overlap = 832.188
+PHY-3002 : Step(53): len = 245774, overlap = 794.25
+PHY-3002 : Step(54): len = 245298, overlap = 781
+PHY-3002 : Step(55): len = 245967, overlap = 773.125
+PHY-3002 : Step(56): len = 245314, overlap = 753.812
+PHY-3002 : Step(57): len = 245209, overlap = 757.062
+PHY-3002 : Step(58): len = 245450, overlap = 753.25
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.11704e-06
+PHY-3002 : Step(59): len = 256666, overlap = 731.688
+PHY-3002 : Step(60): len = 277900, overlap = 634.375
+PHY-3002 : Step(61): len = 288466, overlap = 582.531
+PHY-3002 : Step(62): len = 294337, overlap = 549.312
+PHY-3002 : Step(63): len = 294940, overlap = 560.031
+PHY-3002 : Step(64): len = 294414, overlap = 573.688
+PHY-3002 : Step(65): len = 292291, overlap = 571.344
+PHY-3002 : Step(66): len = 292388, overlap = 579.188
+PHY-3002 : Step(67): len = 290671, overlap = 581.938
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.82341e-05
+PHY-3002 : Step(68): len = 312716, overlap = 530.844
+PHY-3002 : Step(69): len = 331403, overlap = 457.219
+PHY-3002 : Step(70): len = 338735, overlap = 431.688
+PHY-3002 : Step(71): len = 341027, overlap = 421.312
+PHY-3002 : Step(72): len = 338617, overlap = 405.844
+PHY-3002 : Step(73): len = 337538, overlap = 405.812
+PHY-3002 : Step(74): len = 335137, overlap = 408.562
+PHY-3002 : Step(75): len = 334723, overlap = 419.5
+PHY-3002 : Step(76): len = 333654, overlap = 398
+PHY-3002 : Step(77): len = 334301, overlap = 393.062
+PHY-3002 : Step(78): len = 331866, overlap = 393.75
+PHY-3002 : Step(79): len = 332448, overlap = 394.875
+PHY-3002 : Step(80): len = 331540, overlap = 389.719
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.64681e-05
+PHY-3002 : Step(81): len = 352320, overlap = 343.812
+PHY-3002 : Step(82): len = 365395, overlap = 333
+PHY-3002 : Step(83): len = 365552, overlap = 347.062
+PHY-3002 : Step(84): len = 367736, overlap = 333.406
+PHY-3002 : Step(85): len = 368163, overlap = 318.719
+PHY-3002 : Step(86): len = 370942, overlap = 317.281
+PHY-3002 : Step(87): len = 369831, overlap = 312.062
+PHY-3002 : Step(88): len = 371545, overlap = 299.688
+PHY-3002 : Step(89): len = 371924, overlap = 292.094
+PHY-3002 : Step(90): len = 373342, overlap = 293.938
+PHY-3002 : Step(91): len = 370899, overlap = 301.281
+PHY-3002 : Step(92): len = 371112, overlap = 302.594
+PHY-3002 : Step(93): len = 371446, overlap = 313
+PHY-3002 : Step(94): len = 372973, overlap = 317.312
+PHY-3002 : Step(95): len = 371943, overlap = 306.906
+PHY-3002 : Step(96): len = 372904, overlap = 298.531
+PHY-3002 : Step(97): len = 372240, overlap = 295.188
+PHY-3002 : Step(98): len = 372936, overlap = 295.719
+PHY-3002 : Step(99): len = 371049, overlap = 308.594
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.29363e-05
+PHY-3002 : Step(100): len = 388922, overlap = 303.219
+PHY-3002 : Step(101): len = 399689, overlap = 293.625
+PHY-3002 : Step(102): len = 398271, overlap = 287.219
+PHY-3002 : Step(103): len = 398402, overlap = 280.781
+PHY-3002 : Step(104): len = 400919, overlap = 283.062
+PHY-3002 : Step(105): len = 403765, overlap = 269.656
+PHY-3002 : Step(106): len = 402111, overlap = 264
+PHY-3002 : Step(107): len = 404199, overlap = 261.875
+PHY-3002 : Step(108): len = 406243, overlap = 258.375
+PHY-3002 : Step(109): len = 408140, overlap = 256.969
+PHY-3002 : Step(110): len = 405901, overlap = 251.906
+PHY-3002 : Step(111): len = 406366, overlap = 255.062
+PHY-3002 : Step(112): len = 407590, overlap = 257.375
+PHY-3002 : Step(113): len = 409499, overlap = 260.562
+PHY-3002 : Step(114): len = 407239, overlap = 252.531
+PHY-3002 : Step(115): len = 407536, overlap = 261.656
+PHY-3002 : Step(116): len = 409511, overlap = 263.969
+PHY-3002 : Step(117): len = 410927, overlap = 260.25
+PHY-3002 : Step(118): len = 407704, overlap = 255.625
+PHY-3002 : Step(119): len = 407547, overlap = 255.625
+PHY-3002 : Step(120): len = 409283, overlap = 243.531
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000145873
+PHY-3002 : Step(121): len = 424954, overlap = 237.219
+PHY-3002 : Step(122): len = 436835, overlap = 226.969
+PHY-3002 : Step(123): len = 437396, overlap = 216.531
+PHY-3002 : Step(124): len = 439000, overlap = 211.969
+PHY-3002 : Step(125): len = 441714, overlap = 201.906
+PHY-3002 : Step(126): len = 443630, overlap = 202.281
+PHY-3002 : Step(127): len = 441593, overlap = 198.375
+PHY-3002 : Step(128): len = 440478, overlap = 201.031
+PHY-3002 : Step(129): len = 442437, overlap = 195.375
+PHY-3002 : Step(130): len = 444502, overlap = 192.375
+PHY-3002 : Step(131): len = 445400, overlap = 187.812
+PHY-3002 : Step(132): len = 443353, overlap = 191.375
+PHY-3002 : Step(133): len = 443149, overlap = 192.469
+PHY-3002 : Step(134): len = 442761, overlap = 194.062
+PHY-3002 : Step(135): len = 442875, overlap = 197.375
+PHY-3002 : Step(136): len = 442418, overlap = 201.719
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000291745
+PHY-3002 : Step(137): len = 452337, overlap = 183.562
+PHY-3002 : Step(138): len = 460554, overlap = 190.219
+PHY-3002 : Step(139): len = 462043, overlap = 192.656
+PHY-3002 : Step(140): len = 463215, overlap = 191.625
+PHY-3002 : Step(141): len = 465712, overlap = 186.75
+PHY-3002 : Step(142): len = 468004, overlap = 191.531
+PHY-3002 : Step(143): len = 467303, overlap = 185.719
+PHY-3002 : Step(144): len = 468134, overlap = 181.562
+PHY-3002 : Step(145): len = 470816, overlap = 179.875
+PHY-3002 : Step(146): len = 472698, overlap = 173.062
+PHY-3002 : Step(147): len = 471149, overlap = 177.25
+PHY-3002 : Step(148): len = 470723, overlap = 183.906
+PHY-3002 : Step(149): len = 471776, overlap = 186.375
+PHY-3002 : Step(150): len = 472804, overlap = 176.031
+PHY-3002 : Step(151): len = 472139, overlap = 177.219
+PHY-3002 : Step(152): len = 472210, overlap = 178.219
+PHY-3002 : Step(153): len = 472461, overlap = 175.219
+PHY-3002 : Step(154): len = 472984, overlap = 175.969
+PHY-3002 : Step(155): len = 474250, overlap = 180.25
+PHY-3002 : Step(156): len = 476653, overlap = 179.312
+PHY-3002 : Step(157): len = 476187, overlap = 172.812
+PHY-3002 : Step(158): len = 476088, overlap = 168.812
+PHY-3002 : Step(159): len = 475195, overlap = 161.375
+PHY-3002 : Step(160): len = 475265, overlap = 164.188
+PHY-3002 : Step(161): len = 475560, overlap = 159.781
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.0005552
+PHY-3002 : Step(162): len = 482450, overlap = 161.312
+PHY-3002 : Step(163): len = 490091, overlap = 157.688
+PHY-3002 : Step(164): len = 491828, overlap = 155.375
+PHY-3002 : Step(165): len = 492940, overlap = 153.406
+PHY-3002 : Step(166): len = 494728, overlap = 151.469
+PHY-3002 : Step(167): len = 495662, overlap = 152.188
+PHY-3002 : Step(168): len = 495681, overlap = 147.844
+PHY-3002 : Step(169): len = 496003, overlap = 144.156
+PHY-3002 : Step(170): len = 498082, overlap = 142.938
+PHY-3002 : Step(171): len = 500904, overlap = 144.5
+PHY-3002 : Step(172): len = 501009, overlap = 144.875
+PHY-3002 : Step(173): len = 501056, overlap = 143.125
+PHY-3002 : Step(174): len = 501049, overlap = 147.812
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.0010009
+PHY-3002 : Step(175): len = 506415, overlap = 145.188
+PHY-3002 : Step(176): len = 514057, overlap = 138.875
+PHY-3002 : Step(177): len = 515596, overlap = 135.781
+PHY-3002 : Step(178): len = 516603, overlap = 134.094
+PHY-3002 : Step(179): len = 518154, overlap = 132.406
+PHY-3002 : Step(180): len = 519094, overlap = 131.969
+PHY-3002 : Step(181): len = 518996, overlap = 132.969
+PHY-3002 : Step(182): len = 519532, overlap = 133.656
+PHY-3002 : Step(183): len = 521174, overlap = 135.469
+PHY-3002 : Step(184): len = 522545, overlap = 134.781
+PHY-3002 : Step(185): len = 522448, overlap = 137.875
+PHY-3002 : Step(186): len = 522877, overlap = 132.969
+PHY-3002 : Step(187): len = 524178, overlap = 135.656
+PHY-3002 : Step(188): len = 524708, overlap = 135.906
+PHY-3002 : Step(189): len = 524274, overlap = 135.562
+PHY-3002 : Step(190): len = 524311, overlap = 133.969
+PHY-3002 : Step(191): len = 525039, overlap = 134.094
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00176273
+PHY-3002 : Step(192): len = 527773, overlap = 136.625
+PHY-3002 : Step(193): len = 535374, overlap = 128.062
+PHY-3002 : Step(194): len = 537766, overlap = 129.875
+PHY-3002 : Step(195): len = 539111, overlap = 126.562
+PHY-3002 : Step(196): len = 540169, overlap = 126.438
+PHY-3002 : Step(197): len = 541215, overlap = 122.844
+PHY-3002 : Step(198): len = 542627, overlap = 120.844
+PHY-3002 : Step(199): len = 543791, overlap = 122.375
+PHY-3002 : Step(200): len = 544357, overlap = 121.594
+PHY-3002 : Step(201): len = 544722, overlap = 122.781
+PHY-3002 : Step(202): len = 545280, overlap = 125.469
+PHY-3002 : Step(203): len = 545560, overlap = 125.469
+PHY-3002 : Step(204): len = 545688, overlap = 121.875
+PHY-3002 : Step(205): len = 546210, overlap = 127.469
+PHY-3002 : Step(206): len = 546926, overlap = 121.125
+PHY-3002 : Step(207): len = 547232, overlap = 123.75
+PHY-3002 : Step(208): len = 547066, overlap = 120.312
+PHY-3002 : Step(209): len = 547083, overlap = 121.375
+PHY-3002 : Step(210): len = 547644, overlap = 118.5
+PHY-3002 : Step(211): len = 548017, overlap = 116.438
+PHY-3002 : Step(212): len = 547921, overlap = 118.5
+PHY-3002 : Step(213): len = 547981, overlap = 117.656
+PHY-3002 : Step(214): len = 548537, overlap = 118.438
+PHY-3002 : Step(215): len = 548537, overlap = 118.438
+PHY-3002 : Step(216): len = 548343, overlap = 117.656
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.013754s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (113.6%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 720232, over cnt = 1618(4%), over = 7362, worst = 42
+PHY-1001 : End global iterations;  0.702226s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (133.5%)
+
+PHY-1001 : Congestion index: top1 = 74.89, top5 = 58.93, top10 = 50.79, top15 = 45.77.
+PHY-3001 : End congestion estimation;  0.923218s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (125.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.843705s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000167362
+PHY-3002 : Step(217): len = 654659, overlap = 61.4062
+PHY-3002 : Step(218): len = 654180, overlap = 54.4062
+PHY-3002 : Step(219): len = 649811, overlap = 52.4688
+PHY-3002 : Step(220): len = 647329, overlap = 46.9688
+PHY-3002 : Step(221): len = 647982, overlap = 40.4688
+PHY-3002 : Step(222): len = 647740, overlap = 34.75
+PHY-3002 : Step(223): len = 643495, overlap = 30.125
+PHY-3002 : Step(224): len = 637808, overlap = 22.5
+PHY-3002 : Step(225): len = 633257, overlap = 21.375
+PHY-3002 : Step(226): len = 629035, overlap = 25.4375
+PHY-3002 : Step(227): len = 625548, overlap = 26.5
+PHY-3002 : Step(228): len = 623321, overlap = 25.4688
+PHY-3002 : Step(229): len = 621833, overlap = 21.4375
+PHY-3002 : Step(230): len = 620484, overlap = 22.0312
+PHY-3002 : Step(231): len = 619913, overlap = 23.5312
+PHY-3002 : Step(232): len = 619159, overlap = 19.7188
+PHY-3002 : Step(233): len = 617117, overlap = 22.1875
+PHY-3002 : Step(234): len = 615437, overlap = 20.6562
+PHY-3002 : Step(235): len = 612999, overlap = 21.4375
+PHY-3002 : Step(236): len = 611862, overlap = 21.625
+PHY-3002 : Step(237): len = 609681, overlap = 21.2812
+PHY-3002 : Step(238): len = 608001, overlap = 22.7812
+PHY-3002 : Step(239): len = 607271, overlap = 21.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000334724
+PHY-3002 : Step(240): len = 608801, overlap = 22.5
+PHY-3002 : Step(241): len = 614076, overlap = 22.4062
+PHY-3002 : Step(242): len = 617029, overlap = 21.4375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000669448
+PHY-3002 : Step(243): len = 625200, overlap = 19.0938
+PHY-3002 : Step(244): len = 639645, overlap = 15.375
+PHY-3002 : Step(245): len = 659155, overlap = 14.875
+PHY-3002 : Step(246): len = 657320, overlap = 12.9688
+PHY-3002 : Step(247): len = 653834, overlap = 13.4688
+PHY-3002 : Step(248): len = 651393, overlap = 17.3125
+PHY-3002 : Step(249): len = 650725, overlap = 19.8438
+PHY-3002 : Step(250): len = 652194, overlap = 21.0625
+PHY-3002 : Step(251): len = 652640, overlap = 19.9062
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.00122173
+PHY-3002 : Step(252): len = 657312, overlap = 18.5
+PHY-3002 : Step(253): len = 670639, overlap = 17.0625
+PHY-3002 : Step(254): len = 677443, overlap = 15.9062
+PHY-3002 : Step(255): len = 677024, overlap = 16.0625
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 0.00206257
+PHY-3002 : Step(256): len = 679741, overlap = 16.5625
+PHY-3002 : Step(257): len = 689831, overlap = 17.0625
+PHY-3002 : Step(258): len = 699448, overlap = 18.5625
+PHY-3002 : Step(259): len = 706597, overlap = 21.3125
+PHY-3002 : Step(260): len = 711733, overlap = 21.3125
+PHY-3002 : Step(261): len = 714154, overlap = 21.75
+PHY-3002 : Step(262): len = 713815, overlap = 24.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 90/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 806904, over cnt = 2861(8%), over = 12877, worst = 44
+PHY-1001 : End global iterations;  1.741461s wall, 2.296875s user + 0.015625s system = 2.312500s CPU (132.8%)
+
+PHY-1001 : Congestion index: top1 = 84.25, top5 = 68.52, top10 = 60.44, top15 = 55.41.
+PHY-3001 : End congestion estimation;  2.002920s wall, 2.562500s user + 0.031250s system = 2.593750s CPU (129.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.879815s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (99.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000169651
+PHY-3002 : Step(263): len = 695882, overlap = 214.375
+PHY-3002 : Step(264): len = 682470, overlap = 173.875
+PHY-3002 : Step(265): len = 667535, overlap = 158.344
+PHY-3002 : Step(266): len = 654770, overlap = 142.125
+PHY-3002 : Step(267): len = 644509, overlap = 118.719
+PHY-3002 : Step(268): len = 636947, overlap = 106.25
+PHY-3002 : Step(269): len = 628742, overlap = 99.2812
+PHY-3002 : Step(270): len = 625532, overlap = 93
+PHY-3002 : Step(271): len = 620217, overlap = 92
+PHY-3002 : Step(272): len = 617146, overlap = 90.7188
+PHY-3002 : Step(273): len = 613904, overlap = 93.4688
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000339302
+PHY-3002 : Step(274): len = 614791, overlap = 89.625
+PHY-3002 : Step(275): len = 617718, overlap = 86.4688
+PHY-3002 : Step(276): len = 621897, overlap = 82.9688
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000678603
+PHY-3002 : Step(277): len = 623744, overlap = 79.5625
+PHY-3002 : Step(278): len = 630103, overlap = 77.25
+PHY-3002 : Step(279): len = 635644, overlap = 77.25
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.425726s wall, 1.390625s user + 0.031250s system = 1.421875s CPU (99.7%)
+
+RUN-1004 : used memory is 582 MB, reserved memory is 563 MB, peak memory is 716 MB
+OPT-1001 : Total overflow 396.47 peak overflow 2.78
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 801/20251.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 737616, over cnt = 3025(8%), over = 10705, worst = 21
+PHY-1001 : End global iterations;  1.231701s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (140.8%)
+
+PHY-1001 : Congestion index: top1 = 66.64, top5 = 55.01, top10 = 49.60, top15 = 46.35.
+PHY-1001 : End incremental global routing;  1.581003s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (131.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20073 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.923366s wall, 0.875000s user + 0.046875s system = 0.921875s CPU (99.8%)
+
+OPT-1001 : 51 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 17535 has valid locations, 339 needs to be replaced
+PHY-3001 : design contains 17959 instances, 7505 luts, 9233 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6025 pins
+PHY-3001 : Found 1239 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 660154
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16625/20539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 753488, over cnt = 3057(8%), over = 10774, worst = 21
+PHY-1001 : End global iterations;  0.229141s wall, 0.265625s user + 0.000000s system = 0.265625s CPU (115.9%)
+
+PHY-1001 : Congestion index: top1 = 66.68, top5 = 55.34, top10 = 49.94, top15 = 46.59.
+PHY-3001 : End congestion estimation;  0.484517s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (109.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85785, tnet num: 20361, tinst num: 17959, tnode num: 116461, tedge num: 137578.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.487048s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (98.8%)
+
+RUN-1004 : used memory is 626 MB, reserved memory is 612 MB, peak memory is 721 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.451833s wall, 2.406250s user + 0.031250s system = 2.437500s CPU (99.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(280): len = 659068, overlap = 0.4375
+PHY-3002 : Step(281): len = 658675, overlap = 0.4375
+PHY-3002 : Step(282): len = 658414, overlap = 0.375
+PHY-3002 : Step(283): len = 658125, overlap = 0.3125
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16748/20539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 750624, over cnt = 3079(8%), over = 10829, worst = 21
+PHY-1001 : End global iterations;  0.191998s wall, 0.343750s user + 0.000000s system = 0.343750s CPU (179.0%)
+
+PHY-1001 : Congestion index: top1 = 67.11, top5 = 55.55, top10 = 50.20, top15 = 46.80.
+PHY-3001 : End congestion estimation;  0.451276s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (131.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.928525s wall, 0.906250s user + 0.015625s system = 0.921875s CPU (99.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000324261
+PHY-3002 : Step(284): len = 658155, overlap = 79.125
+PHY-3002 : Step(285): len = 658185, overlap = 79.0625
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000648521
+PHY-3002 : Step(286): len = 658064, overlap = 79
+PHY-3002 : Step(287): len = 658425, overlap = 79.4375
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00129704
+PHY-3002 : Step(288): len = 658689, overlap = 79.6875
+PHY-3002 : Step(289): len = 659400, overlap = 79.4688
+PHY-3001 : Final: Len = 659400, Over = 79.4688
+PHY-3001 : End incremental placement;  5.041897s wall, 5.375000s user + 0.218750s system = 5.593750s CPU (110.9%)
+
+OPT-1001 : Total overflow 402.75 peak overflow 2.78
+OPT-1001 : End high-fanout net optimization;  8.133414s wall, 8.906250s user + 0.281250s system = 9.187500s CPU (113.0%)
+
+OPT-1001 : Current memory(MB): used = 722, reserve = 709, peak = 739.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16646/20539.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 754488, over cnt = 3018(8%), over = 9701, worst = 20
+PHY-1002 : len = 808448, over cnt = 2037(5%), over = 4750, worst = 20
+PHY-1002 : len = 839856, over cnt = 1044(2%), over = 2235, worst = 15
+PHY-1002 : len = 863592, over cnt = 268(0%), over = 529, worst = 12
+PHY-1002 : len = 872000, over cnt = 3(0%), over = 7, worst = 4
+PHY-1001 : End global iterations;  1.644416s wall, 2.375000s user + 0.046875s system = 2.421875s CPU (147.3%)
+
+PHY-1001 : Congestion index: top1 = 54.55, top5 = 48.43, top10 = 45.18, top15 = 43.15.
+OPT-1001 : End congestion update;  1.917686s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (141.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20361 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.812998s wall, 0.796875s user + 0.015625s system = 0.812500s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 122 cells processed and 17850 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 20 cells processed and 1750 slack improved
+OPT-0007 : Iter 3: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 1 cells processed and 200 slack improved
+OPT-1001 : End bottleneck based optimization;  3.037012s wall, 3.765625s user + 0.062500s system = 3.828125s CPU (126.0%)
+
+OPT-1001 : Current memory(MB): used = 697, reserve = 683, peak = 739.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16748/20541.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872160, over cnt = 84(0%), over = 112, worst = 4
+PHY-1002 : len = 871968, over cnt = 43(0%), over = 48, worst = 3
+PHY-1002 : len = 872272, over cnt = 10(0%), over = 11, worst = 2
+PHY-1002 : len = 872376, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 872448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.718432s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (102.2%)
+
+PHY-1001 : Congestion index: top1 = 54.33, top5 = 48.06, top10 = 44.88, top15 = 42.91.
+OPT-1001 : End congestion update;  1.366178s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (72.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20363 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.797483s wall, 0.796875s user + 0.000000s system = 0.796875s CPU (99.9%)
+
+OPT-0007 : Start: WNS -1068 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 17 cells processed and 4750 slack improved
+OPT-0007 : Iter 2: improved WNS -1068 TNS -1528 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.279918s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (83.6%)
+
+OPT-1001 : Current memory(MB): used = 709, reserve = 695, peak = 739.
+OPT-1001 : End physical optimization;  15.180084s wall, 16.359375s user + 0.390625s system = 16.750000s CPU (110.3%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7505 LUT to BLE ...
+SYN-4008 : Packed 7505 LUT and 3133 SEQ to BLE.
+SYN-4003 : Packing 6102 remaining SEQ's ...
+SYN-4005 : Packed 3855 SEQ with LUT/SLICE
+SYN-4006 : 820 single LUT's are left
+SYN-4006 : 2247 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9752/13483 primitive instances ...
+PHY-3001 : End packing;  1.718894s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (100.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 6826 instances
+RUN-1001 : 3339 mslices, 3339 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17540 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9912 nets have 2 pins
+RUN-1001 : 5825 nets have [3 - 5] pins
+RUN-1001 : 1104 nets have [6 - 10] pins
+RUN-1001 : 325 nets have [11 - 20] pins
+RUN-1001 : 343 nets have [21 - 99] pins
+RUN-1001 : 11 nets have 100+ pins
+PHY-3001 : design contains 6824 instances, 6678 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3606 pins
+PHY-3001 : Found 504 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : After packing: Len = 671270, Over = 255
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7676/17540.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 825744, over cnt = 1888(5%), over = 3064, worst = 8
+PHY-1002 : len = 834496, over cnt = 1114(3%), over = 1624, worst = 8
+PHY-1002 : len = 846728, over cnt = 423(1%), over = 598, worst = 8
+PHY-1002 : len = 851248, over cnt = 214(0%), over = 301, worst = 5
+PHY-1002 : len = 856216, over cnt = 1(0%), over = 1, worst = 1
+PHY-1001 : End global iterations;  1.570987s wall, 2.187500s user + 0.062500s system = 2.250000s CPU (143.2%)
+
+PHY-1001 : Congestion index: top1 = 54.96, top5 = 47.90, top10 = 44.50, top15 = 42.24.
+PHY-3001 : End congestion estimation;  1.971359s wall, 2.593750s user + 0.062500s system = 2.656250s CPU (134.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73856, tnet num: 17362, tinst num: 6824, tnode num: 96431, tedge num: 123983.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.622226s wall, 1.609375s user + 0.015625s system = 1.625000s CPU (100.2%)
+
+RUN-1004 : used memory is 622 MB, reserved memory is 614 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.492288s wall, 2.453125s user + 0.046875s system = 2.500000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.05148e-05
+PHY-3002 : Step(290): len = 658053, overlap = 256
+PHY-3002 : Step(291): len = 650688, overlap = 258
+PHY-3002 : Step(292): len = 646118, overlap = 257.5
+PHY-3002 : Step(293): len = 642916, overlap = 259.25
+PHY-3002 : Step(294): len = 640259, overlap = 255.25
+PHY-3002 : Step(295): len = 637599, overlap = 257.25
+PHY-3002 : Step(296): len = 635170, overlap = 256.25
+PHY-3002 : Step(297): len = 633232, overlap = 260.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00010103
+PHY-3002 : Step(298): len = 636799, overlap = 251.5
+PHY-3002 : Step(299): len = 641489, overlap = 247.25
+PHY-3002 : Step(300): len = 642352, overlap = 242
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000202059
+PHY-3002 : Step(301): len = 651853, overlap = 223.75
+PHY-3002 : Step(302): len = 659561, overlap = 216
+PHY-3002 : Step(303): len = 658520, overlap = 217.5
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000404118
+PHY-3002 : Step(304): len = 668413, overlap = 206.75
+PHY-3002 : Step(305): len = 682752, overlap = 191.25
+PHY-3002 : Step(306): len = 680624, overlap = 196.75
+PHY-3002 : Step(307): len = 679146, overlap = 199.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.397205s wall, 0.390625s user + 0.750000s system = 1.140625s CPU (287.2%)
+
+PHY-3001 : Trial Legalized: Len = 754494
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 718/17540.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 874784, over cnt = 2703(7%), over = 4505, worst = 8
+PHY-1002 : len = 890240, over cnt = 1674(4%), over = 2503, worst = 8
+PHY-1002 : len = 905208, over cnt = 847(2%), over = 1239, worst = 8
+PHY-1002 : len = 916744, over cnt = 326(0%), over = 485, worst = 4
+PHY-1002 : len = 924296, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations;  2.308552s wall, 3.390625s user + 0.015625s system = 3.406250s CPU (147.5%)
+
+PHY-1001 : Congestion index: top1 = 52.26, top5 = 47.57, top10 = 45.00, top15 = 43.46.
+PHY-3001 : End congestion estimation;  2.768226s wall, 3.843750s user + 0.015625s system = 3.859375s CPU (139.4%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.890843s wall, 0.859375s user + 0.031250s system = 0.890625s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000161974
+PHY-3002 : Step(308): len = 725429, overlap = 37
+PHY-3002 : Step(309): len = 707876, overlap = 69.5
+PHY-3002 : Step(310): len = 693960, overlap = 97.5
+PHY-3002 : Step(311): len = 684138, overlap = 118
+PHY-3002 : Step(312): len = 676623, overlap = 144.75
+PHY-3002 : Step(313): len = 672312, overlap = 161.5
+PHY-3002 : Step(314): len = 669801, overlap = 171.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000323948
+PHY-3002 : Step(315): len = 674533, overlap = 164.25
+PHY-3002 : Step(316): len = 679032, overlap = 161
+PHY-3002 : Step(317): len = 681537, overlap = 162.25
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000647897
+PHY-3002 : Step(318): len = 684979, overlap = 157.25
+PHY-3002 : Step(319): len = 692035, overlap = 155.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.036904s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (127.0%)
+
+PHY-3001 : Legalized: Len = 723016, Over = 0
+PHY-3001 : Spreading special nets. 468 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.108030s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (101.2%)
+
+PHY-3001 : 676 instances has been re-located, deltaX = 225, deltaY = 412, maxDist = 4.
+PHY-3001 : Final: Len = 733206, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73856, tnet num: 17362, tinst num: 6827, tnode num: 96431, tedge num: 123983.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.867048s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.4%)
+
+RUN-1004 : used memory is 637 MB, reserved memory is 642 MB, peak memory is 739 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4459/17540.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 867336, over cnt = 2560(7%), over = 4087, worst = 7
+PHY-1002 : len = 880848, over cnt = 1548(4%), over = 2197, worst = 6
+PHY-1002 : len = 900456, over cnt = 445(1%), over = 601, worst = 5
+PHY-1002 : len = 906840, over cnt = 133(0%), over = 193, worst = 5
+PHY-1002 : len = 909832, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.951019s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (142.6%)
+
+PHY-1001 : Congestion index: top1 = 52.00, top5 = 47.16, top10 = 44.42, top15 = 42.77.
+PHY-1001 : End incremental global routing;  2.322455s wall, 3.140625s user + 0.015625s system = 3.156250s CPU (135.9%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17362 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.888207s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.3%)
+
+OPT-1001 : 4 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6735 has valid locations, 23 needs to be replaced
+PHY-3001 : design contains 6846 instances, 6697 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 734796
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15961/17570.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 911696, over cnt = 64(0%), over = 71, worst = 2
+PHY-1002 : len = 911800, over cnt = 26(0%), over = 28, worst = 2
+PHY-1002 : len = 911888, over cnt = 14(0%), over = 15, worst = 2
+PHY-1002 : len = 911984, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.458669s wall, 0.578125s user + 0.031250s system = 0.609375s CPU (41.8%)
+
+PHY-1001 : Congestion index: top1 = 52.00, top5 = 47.18, top10 = 44.46, top15 = 42.81.
+PHY-3001 : End congestion estimation;  1.775522s wall, 0.906250s user + 0.031250s system = 0.937500s CPU (52.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74047, tnet num: 17392, tinst num: 6846, tnode num: 96674, tedge num: 124240.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.894211s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (99.8%)
+
+RUN-1004 : used memory is 669 MB, reserved memory is 667 MB, peak memory is 739 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17392 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.829125s wall, 2.828125s user + 0.000000s system = 2.828125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(320): len = 734266, overlap = 0
+PHY-3002 : Step(321): len = 734263, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 15956/17570.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910816, over cnt = 46(0%), over = 58, worst = 5
+PHY-1002 : len = 910896, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 910968, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 911032, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.598056s wall, 0.609375s user + 0.000000s system = 0.609375s CPU (101.9%)
+
+PHY-1001 : Congestion index: top1 = 51.98, top5 = 47.14, top10 = 44.43, top15 = 42.78.
+PHY-3001 : End congestion estimation;  0.939562s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (99.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17392 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.109834s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (55.5%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 9.66297e-05
+PHY-3002 : Step(322): len = 734272, overlap = 1.5
+PHY-3002 : Step(323): len = 734272, overlap = 1.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005652s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 734254, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058468s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (80.2%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 0, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 734280, Over = 0
+PHY-3001 : End incremental placement;  8.129888s wall, 6.437500s user + 0.109375s system = 6.546875s CPU (80.5%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  11.834152s wall, 11.078125s user + 0.125000s system = 11.203125s CPU (94.7%)
+
+OPT-1001 : Current memory(MB): used = 745, reserve = 737, peak = 752.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15937/17570.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 910944, over cnt = 49(0%), over = 56, worst = 4
+PHY-1002 : len = 911024, over cnt = 8(0%), over = 8, worst = 1
+PHY-1002 : len = 911152, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 911168, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.608615s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (107.8%)
+
+PHY-1001 : Congestion index: top1 = 52.00, top5 = 47.16, top10 = 44.44, top15 = 42.78.
+OPT-1001 : End congestion update;  0.920883s wall, 0.968750s user + 0.000000s system = 0.968750s CPU (105.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17392 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.729772s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (98.5%)
+
+OPT-0007 : Start: WNS -1083 TNS -1597 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6758 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6846 instances, 6697 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 739084, Over = 0
+PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062271s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.4%)
+
+PHY-3001 : 30 instances has been re-located, deltaX = 20, deltaY = 17, maxDist = 3.
+PHY-3001 : Final: Len = 739404, Over = 0
+PHY-3001 : End incremental legalization;  0.387927s wall, 0.375000s user + 0.015625s system = 0.390625s CPU (100.7%)
+
+OPT-0007 : Iter 1: improved WNS -1047 TNS -1532 NUM_FEPS 2 with 46 cells processed and 13823 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6758 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6846 instances, 6697 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 740618, Over = 0
+PHY-3001 : Spreading special nets. 12 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061429s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : 20 instances has been re-located, deltaX = 10, deltaY = 11, maxDist = 2.
+PHY-3001 : Final: Len = 741036, Over = 0
+PHY-3001 : End incremental legalization;  0.380571s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (98.5%)
+
+OPT-0007 : Iter 2: improved WNS -1047 TNS -1532 NUM_FEPS 2 with 23 cells processed and 7629 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6758 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6846 instances, 6697 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3688 pins
+PHY-3001 : Found 507 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 741242, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.058544s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (106.8%)
+
+PHY-3001 : 5 instances has been re-located, deltaX = 1, deltaY = 4, maxDist = 1.
+PHY-3001 : Final: Len = 741206, Over = 0
+PHY-3001 : End incremental legalization;  0.415840s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (109.0%)
+
+OPT-0007 : Iter 3: improved WNS -1047 TNS -1532 NUM_FEPS 2 with 10 cells processed and 767 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6763 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6851 instances, 6702 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3689 pins
+PHY-3001 : Found 511 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 741730, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061485s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.7%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 3, maxDist = 2.
+PHY-3001 : Final: Len = 741860, Over = 0
+PHY-3001 : End incremental legalization;  0.420583s wall, 0.421875s user + 0.015625s system = 0.437500s CPU (104.0%)
+
+OPT-0007 : Iter 4: improved WNS -1047 TNS -1532 NUM_FEPS 2 with 4 cells processed and 802 slack improved
+OPT-1001 : End bottleneck based optimization;  3.805807s wall, 4.062500s user + 0.031250s system = 4.093750s CPU (107.6%)
+
+OPT-1001 : Current memory(MB): used = 745, reserve = 738, peak = 752.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15582/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 918368, over cnt = 154(0%), over = 213, worst = 9
+PHY-1002 : len = 918536, over cnt = 86(0%), over = 99, worst = 4
+PHY-1002 : len = 919376, over cnt = 22(0%), over = 26, worst = 3
+PHY-1002 : len = 919640, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 919776, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.843679s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (105.6%)
+
+PHY-1001 : Congestion index: top1 = 52.05, top5 = 47.10, top10 = 44.46, top15 = 42.78.
+OPT-1001 : End congestion update;  1.154732s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (104.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.755210s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.3%)
+
+OPT-0007 : Start: WNS -1047 TNS -1582 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 6763 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 6851 instances, 6702 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3689 pins
+PHY-3001 : Found 511 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Initial: Len = 741974, Over = 0
+PHY-3001 : Spreading special nets. 6 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063151s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.0%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 11, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 742092, Over = 0
+PHY-3001 : End incremental legalization;  0.405322s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (111.8%)
+
+OPT-0007 : Iter 1: improved WNS -997 TNS -1532 NUM_FEPS 2 with 10 cells processed and 1400 slack improved
+OPT-0007 : Iter 2: improved WNS -997 TNS -1532 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.444225s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (108.7%)
+
+OPT-1001 : Current memory(MB): used = 745, reserve = 738, peak = 752.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.742652s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.9%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 15930/17572.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 919848, over cnt = 29(0%), over = 30, worst = 2
+PHY-1002 : len = 919880, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 919960, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 920008, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.679376s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (105.8%)
+
+PHY-1001 : Congestion index: top1 = 52.03, top5 = 47.11, top10 = 44.48, top15 = 42.80.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.774993s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (98.8%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -1047 TNS -1582 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 51.689655
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -1047ps with logic level 2 
+RUN-1001 :   0 HFN exist on timing critical paths out of 17572 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 17572 nets
+OPT-1001 : End physical optimization;  22.829740s wall, 22.531250s user + 0.203125s system = 22.734375s CPU (99.6%)
+
+RUN-1003 : finish command "place" in  67.592129s wall, 97.343750s user + 7.046875s system = 104.390625s CPU (154.4%)
+
+RUN-1004 : used memory is 614 MB, reserved memory is 601 MB, peak memory is 752 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.679967s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (174.9%)
+
+RUN-1004 : used memory is 615 MB, reserved memory is 602 MB, peak memory is 752 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 6853 instances
+RUN-1001 : 3346 mslices, 3356 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 17572 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 9917 nets have 2 pins
+RUN-1001 : 5834 nets have [3 - 5] pins
+RUN-1001 : 1106 nets have [6 - 10] pins
+RUN-1001 : 330 nets have [11 - 20] pins
+RUN-1001 : 357 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74079, tnet num: 17394, tinst num: 6851, tnode num: 96720, tedge num: 124285.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.599859s wall, 1.593750s user + 0.000000s system = 1.593750s CPU (99.6%)
+
+RUN-1004 : used memory is 627 MB, reserved memory is 626 MB, peak memory is 752 MB
+PHY-1001 : 3346 mslices, 3356 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 851616, over cnt = 2758(7%), over = 4518, worst = 9
+PHY-1002 : len = 866808, over cnt = 1836(5%), over = 2719, worst = 9
+PHY-1002 : len = 887808, over cnt = 696(1%), over = 1034, worst = 6
+PHY-1002 : len = 903864, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 904104, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.931804s wall, 3.875000s user + 0.015625s system = 3.890625s CPU (132.7%)
+
+PHY-1001 : Congestion index: top1 = 51.59, top5 = 46.85, top10 = 44.25, top15 = 42.59.
+PHY-1001 : End global routing;  3.255493s wall, 4.187500s user + 0.031250s system = 4.218750s CPU (129.6%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 723, reserve = 716, peak = 752.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 993, reserve = 987, peak = 993.
+PHY-1001 : End build detailed router design. 3.988217s wall, 3.937500s user + 0.046875s system = 3.984375s CPU (99.9%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 267048, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.042864s wall, 5.046875s user + 0.000000s system = 5.046875s CPU (100.1%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 267104, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.486572s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1029, reserve = 1023, peak = 1029.
+PHY-1001 : End phase 1; 5.541986s wall, 5.546875s user + 0.000000s system = 5.546875s CPU (100.1%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 44% nets.
+PHY-1001 : Routed 51% nets.
+PHY-1001 : Routed 60% nets.
+PHY-1001 : Routed 73% nets.
+PHY-1001 : Routed 93% nets.
+PHY-1022 : len = 2.35638e+06, over cnt = 1684(0%), over = 1687, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1046, reserve = 1040, peak = 1046.
+PHY-1001 : End initial routed; 24.899663s wall, 59.171875s user + 0.406250s system = 59.578125s CPU (239.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16495(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.412   |  -4.314   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.237560s wall, 3.234375s user + 0.000000s system = 3.234375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1065, reserve = 1059, peak = 1065.
+PHY-1001 : End phase 2; 28.137283s wall, 62.406250s user + 0.406250s system = 62.812500s CPU (223.2%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 4 pins with SWNS -2.156ns STNS -4.055ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.146571s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.9%)
+
+PHY-1022 : len = 2.35642e+06, over cnt = 1687(0%), over = 1690, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.412050s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.6%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33064e+06, over cnt = 585(0%), over = 585, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.370206s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (204.1%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.33018e+06, over cnt = 137(0%), over = 137, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.480504s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (182.1%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.33122e+06, over cnt = 8(0%), over = 8, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.346224s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (130.9%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.33129e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.223894s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (104.7%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.3313e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.225839s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (96.9%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.3313e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.282206s wall, 0.281250s user + 0.015625s system = 0.296875s CPU (105.2%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.3313e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.362731s wall, 0.359375s user + 0.000000s system = 0.359375s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.3313e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.183484s wall, 0.187500s user + 0.000000s system = 0.187500s CPU (102.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.33132e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.179284s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (122.0%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16495(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.156   |  -4.055   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.368912s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (100.2%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 475 feed throughs used by 371 nets
+PHY-1001 : End commit to database; 2.276552s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (99.5%)
+
+PHY-1001 : Current memory(MB): used = 1166, reserve = 1164, peak = 1166.
+PHY-1001 : End phase 3; 10.124671s wall, 12.046875s user + 0.046875s system = 12.093750s CPU (119.4%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.156ns STNS -4.055ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.148893s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.4%)
+
+PHY-1022 : len = 2.33132e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.392411s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.5%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-2.156ns, -4.055ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.33134e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.172325s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (99.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/16495(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.156   |  -4.055   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.406038s wall, 3.406250s user + 0.000000s system = 3.406250s CPU (100.0%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 475 feed throughs used by 371 nets
+PHY-1001 : End commit to database; 2.362691s wall, 2.359375s user + 0.000000s system = 2.359375s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1175, reserve = 1174, peak = 1175.
+PHY-1001 : End phase 4; 6.378845s wall, 6.375000s user + 0.000000s system = 6.375000s CPU (99.9%)
+
+PHY-1003 : Routed, final wirelength = 2.33134e+06
+PHY-1001 : Current memory(MB): used = 1179, reserve = 1178, peak = 1179.
+PHY-1001 : End export database. 0.161940s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (106.1%)
+
+PHY-1001 : End detail routing;  54.730268s wall, 90.859375s user + 0.500000s system = 91.359375s CPU (166.9%)
+
+RUN-1003 : finish command "route" in  60.665906s wall, 97.687500s user + 0.546875s system = 98.234375s CPU (161.9%)
+
+RUN-1004 : used memory is 1103 MB, reserved memory is 1103 MB, peak memory is 1179 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10268   out of  19600   52.39%
+#reg                     9384   out of  19600   47.88%
+#le                     12444
+  #lut only              3060   out of  12444   24.59%
+  #reg only              2176   out of  12444   17.49%
+  #lut&reg               7208   out of  12444   57.92%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1826
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1442
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1360
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               944
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    142
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_255.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/u_local_bus_slve_cis/reg46_syn_246.f0    2
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
+       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |12444  |9241    |1027    |9416    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |548    |437     |23      |450     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |106    |87      |4       |93      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |24     |24      |0       |17      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10     |10      |0       |7       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |770    |433     |96      |577     |0       |0       |
+|    u_ADconfig                |AD_config            |190    |127     |25      |141     |0       |0       |
+|    u_gen_sp                  |gen_sp               |264    |162     |71      |120     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |758    |400     |96      |570     |0       |0       |
+|    u_ADconfig                |AD_config            |181    |144     |25      |132     |0       |0       |
+|    u_gen_sp                  |gen_sp               |261    |151     |71      |122     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3059   |2487    |306     |2081    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |174    |129     |17      |131     |0       |0       |
+|      u0_soft_n               |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|    u_sort                    |sort                 |2850   |2350    |289     |1915    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |4       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2407   |2006    |253     |1564    |22      |0       |
+|        channelPart           |channel_part_8478    |141    |130     |3       |124     |0       |0       |
+|        fifo_adc              |fifo_adc             |57     |48      |9       |38      |0       |0       |
+|        ram_switch            |ram_switch           |1896   |1559    |197     |1181    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |230    |203     |27      |117     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |9      |6       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |17      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |16      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |10      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |11      |0       |0       |
+|          insert              |insert               |974    |669     |170     |669     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |692    |687     |0       |395     |0       |0       |
+|        read_ram_i            |read_ram             |291    |247     |44      |199     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |235    |195     |40      |160     |0       |0       |
+|          read_ram_data       |read_ram_data        |51     |47      |4       |34      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |336    |242     |36      |279     |3       |0       |
+|        u0_soft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3262   |2554    |349     |2102    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |197    |112     |17      |155     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |3037   |2433    |332     |1919    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |3      |3       |0       |3       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2587   |2095    |290     |1571    |22      |1       |
+|        channelPart           |channel_part_8478    |230    |216     |3       |137     |0       |0       |
+|        fifo_adc              |fifo_adc             |58     |49      |9       |42      |0       |1       |
+|        ram_switch            |ram_switch           |1915   |1558    |197     |1164    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |221    |192     |27      |109     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |8       |3       |7       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |14      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |15      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |7       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |21     |18      |3       |10      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
+|          insert              |insert               |980    |657     |170     |671     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |714    |709     |0       |384     |0       |0       |
+|        read_ram_i            |read_ram_rev         |362    |252     |81      |206     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |300    |215     |73      |161     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |62     |37      |8       |45      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets  
+    #1         1       9855  
+    #2         2       3896  
+    #3         3       1348  
+    #4         4       587   
+    #5        5-10     1175  
+    #6       11-50     596   
+    #7       51-100     19   
+    #8        >500      1    
+  Average     2.92           
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.068194s wall, 3.546875s user + 0.015625s system = 3.562500s CPU (172.3%)
+
+RUN-1004 : used memory is 1104 MB, reserved memory is 1104 MB, peak memory is 1179 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 74079, tnet num: 17394, tinst num: 6851, tnode num: 96720, tedge num: 124285.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.641387s wall, 1.625000s user + 0.000000s system = 1.625000s CPU (99.0%)
+
+RUN-1004 : used memory is 1109 MB, reserved memory is 1109 MB, peak memory is 1179 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 17394 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.584647s wall, 1.578125s user + 0.015625s system = 1.593750s CPU (100.6%)
+
+RUN-1004 : used memory is 1111 MB, reserved memory is 1111 MB, peak memory is 1179 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 6851
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 17572, pip num: 172943
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 475
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3253 valid insts, and 479523 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.511072s wall, 61.921875s user + 0.234375s system = 62.156250s CPU (653.5%)
+
+RUN-1004 : used memory is 1273 MB, reserved memory is 1269 MB, peak memory is 1389 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_143236.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_144554.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_144554.log
new file mode 100644
index 0000000..b37109f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_144554.log
@@ -0,0 +1,2182 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:45:54 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.390270s wall, 2.281250s user + 0.109375s system = 2.390625s CPU (100.0%)
+
+RUN-1004 : used memory is 354 MB, reserved memory is 324 MB, peak memory is 358 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18313 instances
+RUN-0007 : 7475 luts, 9615 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20891 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13879 nets have 2 pins
+RUN-1001 : 5557 nets have [3 - 5] pins
+RUN-1001 : 1043 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 180 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    2540     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18311 instances, 7475 luts, 9615 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6469 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.221650s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (99.8%)
+
+RUN-1004 : used memory is 552 MB, reserved memory is 529 MB, peak memory is 552 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.032142s wall, 1.984375s user + 0.046875s system = 2.031250s CPU (100.0%)
+
+PHY-3001 : Found 1222 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.00806e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18311.
+PHY-3001 : Level 1 #clusters 2004.
+PHY-3001 : End clustering;  0.132266s wall, 0.140625s user + 0.015625s system = 0.156250s CPU (118.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.25808e+06, overlap = 537.594
+PHY-3002 : Step(2): len = 1.17948e+06, overlap = 555.469
+PHY-3002 : Step(3): len = 805880, overlap = 617.25
+PHY-3002 : Step(4): len = 747389, overlap = 670.188
+PHY-3002 : Step(5): len = 580252, overlap = 828.438
+PHY-3002 : Step(6): len = 506405, overlap = 888.562
+PHY-3002 : Step(7): len = 438740, overlap = 953.062
+PHY-3002 : Step(8): len = 405793, overlap = 990.031
+PHY-3002 : Step(9): len = 368140, overlap = 999.406
+PHY-3002 : Step(10): len = 335219, overlap = 1063.25
+PHY-3002 : Step(11): len = 304746, overlap = 1095.97
+PHY-3002 : Step(12): len = 274497, overlap = 1117.5
+PHY-3002 : Step(13): len = 258167, overlap = 1150.56
+PHY-3002 : Step(14): len = 234928, overlap = 1220.59
+PHY-3002 : Step(15): len = 218432, overlap = 1280.91
+PHY-3002 : Step(16): len = 199574, overlap = 1330.09
+PHY-3002 : Step(17): len = 179244, overlap = 1360.41
+PHY-3002 : Step(18): len = 168619, overlap = 1364.97
+PHY-3002 : Step(19): len = 153530, overlap = 1394.62
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.37726e-06
+PHY-3002 : Step(20): len = 156286, overlap = 1372.84
+PHY-3002 : Step(21): len = 190148, overlap = 1281.91
+PHY-3002 : Step(22): len = 194863, overlap = 1229.56
+PHY-3002 : Step(23): len = 199569, overlap = 1171.84
+PHY-3002 : Step(24): len = 197760, overlap = 1203.22
+PHY-3002 : Step(25): len = 197337, overlap = 1227.56
+PHY-3002 : Step(26): len = 194838, overlap = 1227.19
+PHY-3002 : Step(27): len = 192802, overlap = 1221.19
+PHY-3002 : Step(28): len = 190823, overlap = 1218.09
+PHY-3002 : Step(29): len = 189585, overlap = 1208.81
+PHY-3002 : Step(30): len = 187401, overlap = 1200.69
+PHY-3002 : Step(31): len = 186285, overlap = 1197.38
+PHY-3002 : Step(32): len = 186493, overlap = 1166.91
+PHY-3002 : Step(33): len = 185759, overlap = 1155.12
+PHY-3002 : Step(34): len = 185102, overlap = 1127.38
+PHY-3002 : Step(35): len = 183975, overlap = 1115.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.75453e-06
+PHY-3002 : Step(36): len = 187471, overlap = 1107.03
+PHY-3002 : Step(37): len = 198764, overlap = 1090.66
+PHY-3002 : Step(38): len = 202928, overlap = 1067.75
+PHY-3002 : Step(39): len = 207381, overlap = 1034.38
+PHY-3002 : Step(40): len = 210559, overlap = 1015.44
+PHY-3002 : Step(41): len = 213446, overlap = 990
+PHY-3002 : Step(42): len = 212214, overlap = 968.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.50906e-06
+PHY-3002 : Step(43): len = 221098, overlap = 913.219
+PHY-3002 : Step(44): len = 242358, overlap = 819.594
+PHY-3002 : Step(45): len = 255165, overlap = 778.438
+PHY-3002 : Step(46): len = 267478, overlap = 731
+PHY-3002 : Step(47): len = 271662, overlap = 720.438
+PHY-3002 : Step(48): len = 271709, overlap = 706.906
+PHY-3002 : Step(49): len = 270113, overlap = 680
+PHY-3002 : Step(50): len = 269630, overlap = 679.875
+PHY-3002 : Step(51): len = 267425, overlap = 688.156
+PHY-3002 : Step(52): len = 265303, overlap = 695.812
+PHY-3002 : Step(53): len = 262713, overlap = 706.719
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.10181e-05
+PHY-3002 : Step(54): len = 281886, overlap = 673.031
+PHY-3002 : Step(55): len = 297627, overlap = 598.438
+PHY-3002 : Step(56): len = 304406, overlap = 543.031
+PHY-3002 : Step(57): len = 308710, overlap = 545.219
+PHY-3002 : Step(58): len = 307694, overlap = 551.438
+PHY-3002 : Step(59): len = 307802, overlap = 554.938
+PHY-3002 : Step(60): len = 304819, overlap = 550.656
+PHY-3002 : Step(61): len = 305086, overlap = 548.125
+PHY-3002 : Step(62): len = 303942, overlap = 549.188
+PHY-3002 : Step(63): len = 304623, overlap = 548.75
+PHY-3002 : Step(64): len = 301771, overlap = 538.562
+PHY-3002 : Step(65): len = 301740, overlap = 527.969
+PHY-3002 : Step(66): len = 301591, overlap = 528.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.20362e-05
+PHY-3002 : Step(67): len = 316913, overlap = 533.75
+PHY-3002 : Step(68): len = 328114, overlap = 511.719
+PHY-3002 : Step(69): len = 332758, overlap = 471.406
+PHY-3002 : Step(70): len = 335310, overlap = 472.625
+PHY-3002 : Step(71): len = 334783, overlap = 483.938
+PHY-3002 : Step(72): len = 337780, overlap = 470.219
+PHY-3002 : Step(73): len = 338712, overlap = 458.938
+PHY-3002 : Step(74): len = 340455, overlap = 459.062
+PHY-3002 : Step(75): len = 339404, overlap = 467.625
+PHY-3002 : Step(76): len = 340251, overlap = 463.375
+PHY-3002 : Step(77): len = 339541, overlap = 456.281
+PHY-3002 : Step(78): len = 340666, overlap = 462.219
+PHY-3002 : Step(79): len = 339598, overlap = 465.75
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.40725e-05
+PHY-3002 : Step(80): len = 358475, overlap = 417.094
+PHY-3002 : Step(81): len = 371673, overlap = 392.438
+PHY-3002 : Step(82): len = 371429, overlap = 384
+PHY-3002 : Step(83): len = 373076, overlap = 377.188
+PHY-3002 : Step(84): len = 375376, overlap = 382.594
+PHY-3002 : Step(85): len = 379126, overlap = 374.875
+PHY-3002 : Step(86): len = 376946, overlap = 358.219
+PHY-3002 : Step(87): len = 380036, overlap = 349.438
+PHY-3002 : Step(88): len = 381497, overlap = 324.781
+PHY-3002 : Step(89): len = 383751, overlap = 328.844
+PHY-3002 : Step(90): len = 378101, overlap = 320.062
+PHY-3002 : Step(91): len = 377588, overlap = 307.562
+PHY-3002 : Step(92): len = 380210, overlap = 315.656
+PHY-3002 : Step(93): len = 382216, overlap = 309.469
+PHY-3002 : Step(94): len = 377413, overlap = 316.156
+PHY-3002 : Step(95): len = 376819, overlap = 314.219
+PHY-3002 : Step(96): len = 378971, overlap = 320.594
+PHY-3002 : Step(97): len = 381832, overlap = 309.156
+PHY-3002 : Step(98): len = 378679, overlap = 322.562
+PHY-3002 : Step(99): len = 378909, overlap = 328.312
+PHY-3002 : Step(100): len = 381466, overlap = 320.75
+PHY-3002 : Step(101): len = 383108, overlap = 322.375
+PHY-3002 : Step(102): len = 379254, overlap = 323.375
+PHY-3002 : Step(103): len = 378855, overlap = 336.344
+PHY-3002 : Step(104): len = 382473, overlap = 334.438
+PHY-3002 : Step(105): len = 385118, overlap = 324.469
+PHY-3002 : Step(106): len = 379894, overlap = 330
+PHY-3002 : Step(107): len = 379380, overlap = 334
+PHY-3002 : Step(108): len = 381186, overlap = 337.844
+PHY-3002 : Step(109): len = 383820, overlap = 343.094
+PHY-3002 : Step(110): len = 380397, overlap = 343.188
+PHY-3002 : Step(111): len = 380110, overlap = 335.906
+PHY-3002 : Step(112): len = 381876, overlap = 333.656
+PHY-3002 : Step(113): len = 382988, overlap = 331.688
+PHY-3002 : Step(114): len = 379633, overlap = 340.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.69695e-05
+PHY-3002 : Step(115): len = 396380, overlap = 324.281
+PHY-3002 : Step(116): len = 404504, overlap = 316.625
+PHY-3002 : Step(117): len = 402189, overlap = 319.906
+PHY-3002 : Step(118): len = 402844, overlap = 307.562
+PHY-3002 : Step(119): len = 407559, overlap = 300.656
+PHY-3002 : Step(120): len = 410960, overlap = 293.938
+PHY-3002 : Step(121): len = 409023, overlap = 313.469
+PHY-3002 : Step(122): len = 410609, overlap = 307.719
+PHY-3002 : Step(123): len = 413005, overlap = 302.188
+PHY-3002 : Step(124): len = 415370, overlap = 304.281
+PHY-3002 : Step(125): len = 411929, overlap = 304.812
+PHY-3002 : Step(126): len = 411455, overlap = 301.156
+PHY-3002 : Step(127): len = 413253, overlap = 297.406
+PHY-3002 : Step(128): len = 415569, overlap = 296.688
+PHY-3002 : Step(129): len = 413280, overlap = 298.125
+PHY-3002 : Step(130): len = 414014, overlap = 299.562
+PHY-3002 : Step(131): len = 415804, overlap = 291.688
+PHY-3002 : Step(132): len = 416706, overlap = 287.562
+PHY-3002 : Step(133): len = 414488, overlap = 293.062
+PHY-3002 : Step(134): len = 414222, overlap = 296.188
+PHY-3002 : Step(135): len = 416186, overlap = 297.844
+PHY-3002 : Step(136): len = 418247, overlap = 297.594
+PHY-3002 : Step(137): len = 415157, overlap = 307.406
+PHY-3002 : Step(138): len = 414792, overlap = 302.969
+PHY-3002 : Step(139): len = 416141, overlap = 297.094
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000173939
+PHY-3002 : Step(140): len = 429093, overlap = 281.469
+PHY-3002 : Step(141): len = 436379, overlap = 267.344
+PHY-3002 : Step(142): len = 436546, overlap = 270.844
+PHY-3002 : Step(143): len = 437380, overlap = 260
+PHY-3002 : Step(144): len = 439507, overlap = 261.031
+PHY-3002 : Step(145): len = 442472, overlap = 260.094
+PHY-3002 : Step(146): len = 443304, overlap = 254.219
+PHY-3002 : Step(147): len = 444774, overlap = 251.031
+PHY-3002 : Step(148): len = 447138, overlap = 255.531
+PHY-3002 : Step(149): len = 448747, overlap = 255.688
+PHY-3002 : Step(150): len = 447451, overlap = 243.031
+PHY-3002 : Step(151): len = 447432, overlap = 241.656
+PHY-3002 : Step(152): len = 447994, overlap = 237.375
+PHY-3002 : Step(153): len = 448451, overlap = 237.281
+PHY-3002 : Step(154): len = 446798, overlap = 237.188
+PHY-3002 : Step(155): len = 446275, overlap = 236.5
+PHY-3002 : Step(156): len = 447543, overlap = 230.219
+PHY-3002 : Step(157): len = 449128, overlap = 220.375
+PHY-3002 : Step(158): len = 447139, overlap = 219.219
+PHY-3002 : Step(159): len = 446549, overlap = 211.5
+PHY-3002 : Step(160): len = 447169, overlap = 214.344
+PHY-3002 : Step(161): len = 447800, overlap = 215.125
+PHY-3002 : Step(162): len = 446898, overlap = 207.406
+PHY-3002 : Step(163): len = 446875, overlap = 201.406
+PHY-3002 : Step(164): len = 447304, overlap = 210.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000347504
+PHY-3002 : Step(165): len = 457687, overlap = 210.438
+PHY-3002 : Step(166): len = 465640, overlap = 207.938
+PHY-3002 : Step(167): len = 466285, overlap = 204.312
+PHY-3002 : Step(168): len = 467249, overlap = 195.25
+PHY-3002 : Step(169): len = 469554, overlap = 192.719
+PHY-3002 : Step(170): len = 471718, overlap = 200
+PHY-3002 : Step(171): len = 471191, overlap = 203.031
+PHY-3002 : Step(172): len = 471762, overlap = 203.625
+PHY-3002 : Step(173): len = 474201, overlap = 204.312
+PHY-3002 : Step(174): len = 475784, overlap = 201.562
+PHY-3002 : Step(175): len = 474873, overlap = 204.906
+PHY-3002 : Step(176): len = 474276, overlap = 202.906
+PHY-3002 : Step(177): len = 475208, overlap = 198.844
+PHY-3002 : Step(178): len = 478795, overlap = 189.438
+PHY-3002 : Step(179): len = 478779, overlap = 190.219
+PHY-3002 : Step(180): len = 479429, overlap = 196.031
+PHY-3002 : Step(181): len = 480439, overlap = 190.375
+PHY-3002 : Step(182): len = 481046, overlap = 190.844
+PHY-3002 : Step(183): len = 480074, overlap = 193.062
+PHY-3002 : Step(184): len = 479914, overlap = 196.062
+PHY-3002 : Step(185): len = 480011, overlap = 187.688
+PHY-3002 : Step(186): len = 480060, overlap = 186.594
+PHY-3002 : Step(187): len = 479977, overlap = 191.312
+PHY-3002 : Step(188): len = 480291, overlap = 189.219
+PHY-3002 : Step(189): len = 480033, overlap = 187.594
+PHY-3002 : Step(190): len = 480026, overlap = 184.906
+PHY-3002 : Step(191): len = 480182, overlap = 185.344
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000629862
+PHY-3002 : Step(192): len = 484636, overlap = 185
+PHY-3002 : Step(193): len = 491568, overlap = 188.906
+PHY-3002 : Step(194): len = 492459, overlap = 174.625
+PHY-3002 : Step(195): len = 493328, overlap = 178.156
+PHY-3002 : Step(196): len = 494684, overlap = 175.781
+PHY-3002 : Step(197): len = 495973, overlap = 182.688
+PHY-3002 : Step(198): len = 496068, overlap = 180.688
+PHY-3002 : Step(199): len = 496492, overlap = 179.375
+PHY-3002 : Step(200): len = 497525, overlap = 179.062
+PHY-3002 : Step(201): len = 497860, overlap = 178.938
+PHY-3002 : Step(202): len = 497995, overlap = 176.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00106194
+PHY-3002 : Step(203): len = 501189, overlap = 172.438
+PHY-3002 : Step(204): len = 505162, overlap = 170.562
+PHY-3002 : Step(205): len = 505875, overlap = 159.469
+PHY-3002 : Step(206): len = 506812, overlap = 163.594
+PHY-3002 : Step(207): len = 509113, overlap = 160.812
+PHY-3002 : Step(208): len = 511531, overlap = 160.969
+PHY-3002 : Step(209): len = 512285, overlap = 163.625
+PHY-3002 : Step(210): len = 512751, overlap = 164.281
+PHY-3002 : Step(211): len = 513549, overlap = 160.531
+PHY-3002 : Step(212): len = 514423, overlap = 165.031
+PHY-3002 : Step(213): len = 514641, overlap = 168.281
+PHY-3002 : Step(214): len = 515054, overlap = 166.562
+PHY-3002 : Step(215): len = 515798, overlap = 163.719
+PHY-3002 : Step(216): len = 516032, overlap = 161.594
+PHY-3002 : Step(217): len = 516078, overlap = 162.438
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0017657
+PHY-3002 : Step(218): len = 519424, overlap = 162.188
+PHY-3002 : Step(219): len = 528170, overlap = 161.281
+PHY-3002 : Step(220): len = 528993, overlap = 160.875
+PHY-3002 : Step(221): len = 529757, overlap = 166
+PHY-3002 : Step(222): len = 531547, overlap = 169.75
+PHY-3002 : Step(223): len = 532471, overlap = 171.062
+PHY-3002 : Step(224): len = 532202, overlap = 169.25
+PHY-3002 : Step(225): len = 532186, overlap = 160.906
+PHY-3002 : Step(226): len = 533182, overlap = 164.469
+PHY-3002 : Step(227): len = 534273, overlap = 161.219
+PHY-3002 : Step(228): len = 534293, overlap = 156.25
+PHY-3002 : Step(229): len = 534480, overlap = 155.875
+PHY-3002 : Step(230): len = 535266, overlap = 157.812
+PHY-3002 : Step(231): len = 535593, overlap = 158.156
+PHY-3002 : Step(232): len = 535598, overlap = 156.781
+PHY-3002 : Step(233): len = 535732, overlap = 156.344
+PHY-3002 : Step(234): len = 536545, overlap = 158.906
+PHY-3002 : Step(235): len = 537668, overlap = 158.875
+PHY-3002 : Step(236): len = 537696, overlap = 160.156
+PHY-3002 : Step(237): len = 537796, overlap = 157.844
+PHY-3002 : Step(238): len = 538367, overlap = 157.031
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.015632s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (100.0%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 706104, over cnt = 1605(4%), over = 7585, worst = 45
+PHY-1001 : End global iterations;  0.686724s wall, 1.062500s user + 0.062500s system = 1.125000s CPU (163.8%)
+
+PHY-1001 : Congestion index: top1 = 81.38, top5 = 61.13, top10 = 52.56, top15 = 47.12.
+PHY-3001 : End congestion estimation;  0.905170s wall, 1.265625s user + 0.062500s system = 1.328125s CPU (146.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.868801s wall, 0.859375s user + 0.015625s system = 0.875000s CPU (100.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000147396
+PHY-3002 : Step(239): len = 641511, overlap = 105.406
+PHY-3002 : Step(240): len = 640037, overlap = 96.4375
+PHY-3002 : Step(241): len = 635785, overlap = 90.5938
+PHY-3002 : Step(242): len = 635141, overlap = 80.8438
+PHY-3002 : Step(243): len = 635198, overlap = 74.8125
+PHY-3002 : Step(244): len = 631981, overlap = 69.3125
+PHY-3002 : Step(245): len = 628790, overlap = 63.875
+PHY-3002 : Step(246): len = 627388, overlap = 61.75
+PHY-3002 : Step(247): len = 624297, overlap = 57.1875
+PHY-3002 : Step(248): len = 620643, overlap = 57.3125
+PHY-3002 : Step(249): len = 618809, overlap = 59.7188
+PHY-3002 : Step(250): len = 616473, overlap = 58.375
+PHY-3002 : Step(251): len = 614842, overlap = 52.0312
+PHY-3002 : Step(252): len = 614370, overlap = 51.6562
+PHY-3002 : Step(253): len = 613433, overlap = 50.5938
+PHY-3002 : Step(254): len = 612101, overlap = 51.4375
+PHY-3002 : Step(255): len = 611656, overlap = 55.5312
+PHY-3002 : Step(256): len = 609221, overlap = 55.7812
+PHY-3002 : Step(257): len = 607441, overlap = 55.875
+PHY-3002 : Step(258): len = 605551, overlap = 56.7812
+PHY-3002 : Step(259): len = 603713, overlap = 56.9375
+PHY-3002 : Step(260): len = 601945, overlap = 58.375
+PHY-3002 : Step(261): len = 600761, overlap = 58.9688
+PHY-3002 : Step(262): len = 599246, overlap = 57.5312
+PHY-3002 : Step(263): len = 598384, overlap = 54.0625
+PHY-3002 : Step(264): len = 597774, overlap = 54.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000294791
+PHY-3002 : Step(265): len = 602124, overlap = 52.9062
+PHY-3002 : Step(266): len = 602124, overlap = 52.9062
+PHY-3002 : Step(267): len = 602455, overlap = 51.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 102/20891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 684712, over cnt = 2538(7%), over = 10926, worst = 61
+PHY-1001 : End global iterations;  1.656622s wall, 2.109375s user + 0.015625s system = 2.125000s CPU (128.3%)
+
+PHY-1001 : Congestion index: top1 = 79.40, top5 = 62.52, top10 = 54.61, top15 = 49.89.
+PHY-3001 : End congestion estimation;  1.931292s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (124.6%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.286212s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.83893e-05
+PHY-3002 : Step(268): len = 602232, overlap = 264.625
+PHY-3002 : Step(269): len = 606216, overlap = 234.656
+PHY-3002 : Step(270): len = 600744, overlap = 225.219
+PHY-3002 : Step(271): len = 599256, overlap = 214.812
+PHY-3002 : Step(272): len = 596499, overlap = 207.125
+PHY-3002 : Step(273): len = 593592, overlap = 190.25
+PHY-3002 : Step(274): len = 593046, overlap = 180.375
+PHY-3002 : Step(275): len = 589416, overlap = 180.781
+PHY-3002 : Step(276): len = 587384, overlap = 179.938
+PHY-3002 : Step(277): len = 586438, overlap = 174.219
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000156779
+PHY-3002 : Step(278): len = 585723, overlap = 170.719
+PHY-3002 : Step(279): len = 588639, overlap = 164.906
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000298785
+PHY-3002 : Step(280): len = 597053, overlap = 150.094
+PHY-3002 : Step(281): len = 605801, overlap = 136.844
+PHY-3002 : Step(282): len = 609405, overlap = 129
+PHY-3002 : Step(283): len = 609633, overlap = 127.938
+PHY-3002 : Step(284): len = 609883, overlap = 125.094
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000597571
+PHY-3002 : Step(285): len = 612494, overlap = 118.562
+PHY-3002 : Step(286): len = 618492, overlap = 112.938
+PHY-3002 : Step(287): len = 622904, overlap = 102.719
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.500231s wall, 1.468750s user + 0.031250s system = 1.500000s CPU (100.0%)
+
+RUN-1004 : used memory is 595 MB, reserved memory is 577 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 433.69 peak overflow 3.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1484/20891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 721464, over cnt = 3027(8%), over = 11212, worst = 32
+PHY-1001 : End global iterations;  1.177773s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (148.6%)
+
+PHY-1001 : Congestion index: top1 = 70.32, top5 = 57.04, top10 = 50.86, top15 = 47.22.
+PHY-1001 : End incremental global routing;  1.510129s wall, 2.062500s user + 0.000000s system = 2.062500s CPU (136.6%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.936481s wall, 0.890625s user + 0.046875s system = 0.937500s CPU (100.1%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18176 has valid locations, 336 needs to be replaced
+PHY-3001 : design contains 18597 instances, 7580 luts, 9796 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6584 pins
+PHY-3001 : Found 1231 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 646398
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16965/21177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736936, over cnt = 3085(8%), over = 11319, worst = 32
+PHY-1001 : End global iterations;  0.238583s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (131.0%)
+
+PHY-1001 : Congestion index: top1 = 70.15, top5 = 57.25, top10 = 51.37, top15 = 47.64.
+PHY-3001 : End congestion estimation;  0.497731s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (116.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88307, tnet num: 20999, tinst num: 18597, tnode num: 120641, tedge num: 141346.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.481432s wall, 1.453125s user + 0.031250s system = 1.484375s CPU (100.2%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 629 MB, peak memory is 737 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.546675s wall, 2.500000s user + 0.046875s system = 2.546875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(288): len = 645449, overlap = 0.28125
+PHY-3002 : Step(289): len = 645089, overlap = 0.1875
+PHY-3002 : Step(290): len = 644945, overlap = 0.125
+PHY-3002 : Step(291): len = 644686, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17109/21177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735064, over cnt = 3094(8%), over = 11333, worst = 32
+PHY-1001 : End global iterations;  0.186322s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (117.4%)
+
+PHY-1001 : Congestion index: top1 = 70.75, top5 = 57.57, top10 = 51.49, top15 = 47.80.
+PHY-3001 : End congestion estimation;  0.440962s wall, 0.468750s user + 0.000000s system = 0.468750s CPU (106.3%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.370874s wall, 1.343750s user + 0.031250s system = 1.375000s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000425296
+PHY-3002 : Step(292): len = 644677, overlap = 104.375
+PHY-3002 : Step(293): len = 644738, overlap = 104.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000850593
+PHY-3002 : Step(294): len = 644784, overlap = 105.688
+PHY-3002 : Step(295): len = 645163, overlap = 106.156
+PHY-3001 : Final: Len = 645163, Over = 106.156
+PHY-3001 : End incremental placement;  5.522302s wall, 5.625000s user + 0.156250s system = 5.781250s CPU (104.7%)
+
+OPT-1001 : Total overflow 440.84 peak overflow 3.00
+OPT-1001 : End high-fanout net optimization;  8.535166s wall, 9.234375s user + 0.203125s system = 9.437500s CPU (110.6%)
+
+OPT-1001 : Current memory(MB): used = 740, reserve = 729, peak = 758.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17031/21177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738344, over cnt = 3046(8%), over = 10371, worst = 32
+PHY-1002 : len = 787592, over cnt = 2141(6%), over = 5560, worst = 22
+PHY-1002 : len = 839104, over cnt = 840(2%), over = 1899, worst = 15
+PHY-1002 : len = 860952, over cnt = 225(0%), over = 430, worst = 11
+PHY-1002 : len = 868704, over cnt = 15(0%), over = 15, worst = 1
+PHY-1001 : End global iterations;  2.141061s wall, 2.843750s user + 0.000000s system = 2.843750s CPU (132.8%)
+
+PHY-1001 : Congestion index: top1 = 57.20, top5 = 50.49, top10 = 46.81, top15 = 44.58.
+OPT-1001 : End congestion update;  2.402909s wall, 3.109375s user + 0.000000s system = 3.109375s CPU (129.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.836510s wall, 0.812500s user + 0.015625s system = 0.828125s CPU (99.0%)
+
+OPT-0007 : Start: WNS -1118 TNS -1628 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1528 NUM_FEPS 2 with 124 cells processed and 17742 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1528 NUM_FEPS 2 with 40 cells processed and 5550 slack improved
+OPT-0007 : Iter 3: improved WNS -968 TNS -1528 NUM_FEPS 2 with 3 cells processed and 350 slack improved
+OPT-0007 : Iter 4: improved WNS -968 TNS -1528 NUM_FEPS 2 with 2 cells processed and 650 slack improved
+OPT-1001 : End bottleneck based optimization;  3.645404s wall, 4.328125s user + 0.015625s system = 4.343750s CPU (119.2%)
+
+OPT-1001 : Current memory(MB): used = 717, reserve = 709, peak = 758.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17071/21182.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 869152, over cnt = 118(0%), over = 156, worst = 5
+PHY-1002 : len = 868936, over cnt = 78(0%), over = 93, worst = 4
+PHY-1002 : len = 869464, over cnt = 28(0%), over = 29, worst = 2
+PHY-1002 : len = 869576, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 870128, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.771684s wall, 0.750000s user + 0.015625s system = 0.765625s CPU (99.2%)
+
+PHY-1001 : Congestion index: top1 = 56.85, top5 = 50.10, top10 = 46.58, top15 = 44.41.
+OPT-1001 : End congestion update;  1.046436s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (100.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21004 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.822596s wall, 0.828125s user + 0.000000s system = 0.828125s CPU (100.7%)
+
+OPT-0007 : Start: WNS -968 TNS -1528 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -968 TNS -1428 NUM_FEPS 2 with 23 cells processed and 7600 slack improved
+OPT-0007 : Iter 2: improved WNS -968 TNS -1428 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.991878s wall, 1.984375s user + 0.015625s system = 2.000000s CPU (100.4%)
+
+OPT-1001 : Current memory(MB): used = 727, reserve = 716, peak = 758.
+OPT-1001 : End physical optimization;  15.983200s wall, 17.421875s user + 0.281250s system = 17.703125s CPU (110.8%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7580 LUT to BLE ...
+SYN-4008 : Packed 7580 LUT and 3158 SEQ to BLE.
+SYN-4003 : Packing 6643 remaining SEQ's ...
+SYN-4005 : Packed 3910 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2733 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10313/15192 primitive instances ...
+PHY-3001 : End packing;  1.815882s wall, 1.796875s user + 0.000000s system = 1.796875s CPU (99.0%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7109 instances
+RUN-1001 : 3481 mslices, 3480 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18155 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10479 nets have 2 pins
+RUN-1001 : 5818 nets have [3 - 5] pins
+RUN-1001 : 1171 nets have [6 - 10] pins
+RUN-1001 : 319 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 7107 instances, 6961 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3890 pins
+PHY-3001 : Found 480 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : After packing: Len = 658243, Over = 313.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7629/18155.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 811992, over cnt = 2030(5%), over = 3420, worst = 9
+PHY-1002 : len = 820680, over cnt = 1392(3%), over = 2051, worst = 7
+PHY-1002 : len = 830632, over cnt = 841(2%), over = 1234, worst = 6
+PHY-1002 : len = 843848, over cnt = 330(0%), over = 464, worst = 6
+PHY-1002 : len = 852248, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.675717s wall, 2.312500s user + 0.000000s system = 2.312500s CPU (138.0%)
+
+PHY-1001 : Congestion index: top1 = 59.07, top5 = 50.46, top10 = 46.66, top15 = 44.14.
+PHY-3001 : End congestion estimation;  2.072763s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (129.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75978, tnet num: 17977, tinst num: 7107, tnode num: 99607, tedge num: 127304.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.739628s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (100.6%)
+
+RUN-1004 : used memory is 640 MB, reserved memory is 639 MB, peak memory is 758 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17977 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.673745s wall, 2.625000s user + 0.000000s system = 2.625000s CPU (98.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.13615e-05
+PHY-3002 : Step(296): len = 644764, overlap = 308.25
+PHY-3002 : Step(297): len = 638515, overlap = 309.75
+PHY-3002 : Step(298): len = 634801, overlap = 313.25
+PHY-3002 : Step(299): len = 632692, overlap = 316
+PHY-3002 : Step(300): len = 631202, overlap = 311.75
+PHY-3002 : Step(301): len = 630081, overlap = 306.5
+PHY-3002 : Step(302): len = 628119, overlap = 305.75
+PHY-3002 : Step(303): len = 626080, overlap = 313.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.27231e-05
+PHY-3002 : Step(304): len = 629043, overlap = 300.5
+PHY-3002 : Step(305): len = 633064, overlap = 297.75
+PHY-3002 : Step(306): len = 633904, overlap = 295.75
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000165446
+PHY-3002 : Step(307): len = 643403, overlap = 280.75
+PHY-3002 : Step(308): len = 654841, overlap = 261.5
+PHY-3002 : Step(309): len = 656792, overlap = 260.75
+PHY-3002 : Step(310): len = 656479, overlap = 260
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.349713s wall, 0.265625s user + 0.609375s system = 0.875000s CPU (250.2%)
+
+PHY-3001 : Trial Legalized: Len = 742560
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 674/18155.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 859560, over cnt = 2740(7%), over = 4669, worst = 7
+PHY-1002 : len = 877072, over cnt = 1788(5%), over = 2663, worst = 6
+PHY-1002 : len = 894848, over cnt = 916(2%), over = 1321, worst = 6
+PHY-1002 : len = 910928, over cnt = 224(0%), over = 353, worst = 6
+PHY-1002 : len = 916936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.213433s wall, 3.453125s user + 0.015625s system = 3.468750s CPU (156.7%)
+
+PHY-1001 : Congestion index: top1 = 56.70, top5 = 50.72, top10 = 47.56, top15 = 45.49.
+PHY-3001 : End congestion estimation;  2.662073s wall, 3.875000s user + 0.031250s system = 3.906250s CPU (146.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17977 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.905150s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.1%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000158443
+PHY-3002 : Step(311): len = 716643, overlap = 51
+PHY-3002 : Step(312): len = 700521, overlap = 80.5
+PHY-3002 : Step(313): len = 689107, overlap = 107.5
+PHY-3002 : Step(314): len = 680636, overlap = 123.5
+PHY-3002 : Step(315): len = 674054, overlap = 146.5
+PHY-3002 : Step(316): len = 670131, overlap = 166.5
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000316886
+PHY-3002 : Step(317): len = 675548, overlap = 159.25
+PHY-3002 : Step(318): len = 681747, overlap = 151.5
+PHY-3002 : Step(319): len = 684574, overlap = 157.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000633773
+PHY-3002 : Step(320): len = 688897, overlap = 152.5
+PHY-3002 : Step(321): len = 701112, overlap = 152.25
+PHY-3002 : Step(322): len = 705037, overlap = 157.25
+PHY-3002 : Step(323): len = 704194, overlap = 161.5
+PHY-3002 : Step(324): len = 702940, overlap = 166
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.036602s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (85.4%)
+
+PHY-3001 : Legalized: Len = 735363, Over = 0
+PHY-3001 : Spreading special nets. 553 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.121663s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (102.7%)
+
+PHY-3001 : 819 instances has been re-located, deltaX = 294, deltaY = 521, maxDist = 3.
+PHY-3001 : Final: Len = 748319, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75978, tnet num: 17977, tinst num: 7110, tnode num: 99607, tedge num: 127304.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.898112s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (100.4%)
+
+RUN-1004 : used memory is 654 MB, reserved memory is 669 MB, peak memory is 758 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 3722/18155.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 880376, over cnt = 2683(7%), over = 4418, worst = 6
+PHY-1002 : len = 893792, over cnt = 1719(4%), over = 2529, worst = 6
+PHY-1002 : len = 917160, over cnt = 509(1%), over = 685, worst = 5
+PHY-1002 : len = 921304, over cnt = 310(0%), over = 432, worst = 5
+PHY-1002 : len = 927896, over cnt = 3(0%), over = 3, worst = 1
+PHY-1001 : End global iterations;  2.110658s wall, 2.984375s user + 0.015625s system = 3.000000s CPU (142.1%)
+
+PHY-1001 : Congestion index: top1 = 55.67, top5 = 49.48, top10 = 46.71, top15 = 44.89.
+PHY-1001 : End incremental global routing;  2.474185s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (136.4%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17977 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.892528s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.8%)
+
+OPT-1001 : 5 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7017 has valid locations, 25 needs to be replaced
+PHY-3001 : design contains 7130 instances, 6981 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3946 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 751538
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16437/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 931960, over cnt = 103(0%), over = 125, worst = 4
+PHY-1002 : len = 932064, over cnt = 39(0%), over = 40, worst = 2
+PHY-1002 : len = 932392, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932392, over cnt = 5(0%), over = 5, worst = 1
+PHY-1002 : len = 932576, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.799231s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (101.7%)
+
+PHY-1001 : Congestion index: top1 = 55.86, top5 = 49.55, top10 = 46.79, top15 = 44.99.
+PHY-3001 : End congestion estimation;  1.113140s wall, 1.140625s user + 0.000000s system = 1.140625s CPU (102.5%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76226, tnet num: 18000, tinst num: 7130, tnode num: 99911, tedge num: 127611.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.929443s wall, 1.906250s user + 0.015625s system = 1.921875s CPU (99.6%)
+
+RUN-1004 : used memory is 683 MB, reserved memory is 674 MB, peak memory is 758 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.854099s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (99.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(325): len = 750634, overlap = 0.25
+PHY-3002 : Step(326): len = 750345, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16433/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 930872, over cnt = 53(0%), over = 67, worst = 5
+PHY-1002 : len = 930936, over cnt = 18(0%), over = 20, worst = 2
+PHY-1002 : len = 931144, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 931208, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.611076s wall, 0.656250s user + 0.078125s system = 0.734375s CPU (120.2%)
+
+PHY-1001 : Congestion index: top1 = 55.86, top5 = 49.51, top10 = 46.75, top15 = 44.92.
+PHY-3001 : End congestion estimation;  0.938344s wall, 0.984375s user + 0.078125s system = 1.062500s CPU (113.2%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.891217s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (99.9%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000338469
+PHY-3002 : Step(327): len = 750227, overlap = 3.5
+PHY-3002 : Step(328): len = 750091, overlap = 3.25
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000676938
+PHY-3002 : Step(329): len = 750081, overlap = 3
+PHY-3002 : Step(330): len = 750198, overlap = 2.5
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005715s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 750701, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062488s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.0%)
+
+PHY-3001 : 3 instances has been re-located, deltaX = 1, deltaY = 1, maxDist = 2.
+PHY-3001 : Final: Len = 750813, Over = 0
+PHY-3001 : End incremental placement;  6.333823s wall, 6.437500s user + 0.218750s system = 6.656250s CPU (105.1%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.197139s wall, 11.234375s user + 0.250000s system = 11.484375s CPU (112.6%)
+
+OPT-1001 : Current memory(MB): used = 764, reserve = 758, peak = 767.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16402/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 931416, over cnt = 69(0%), over = 86, worst = 5
+PHY-1002 : len = 931792, over cnt = 18(0%), over = 19, worst = 2
+PHY-1002 : len = 931928, over cnt = 1(0%), over = 1, worst = 1
+PHY-1002 : len = 931936, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.389483s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (47.2%)
+
+PHY-1001 : Congestion index: top1 = 55.73, top5 = 49.43, top10 = 46.67, top15 = 44.89.
+OPT-1001 : End congestion update;  1.715064s wall, 0.984375s user + 0.000000s system = 0.984375s CPU (57.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.740465s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.2%)
+
+OPT-0007 : Start: WNS -836 TNS -1350 NUM_FEPS 3
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7042 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7130 instances, 6981 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3946 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 754094, Over = 0
+PHY-3001 : Spreading special nets. 20 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.065579s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (119.1%)
+
+PHY-3001 : 26 instances has been re-located, deltaX = 10, deltaY = 19, maxDist = 3.
+PHY-3001 : Final: Len = 754614, Over = 0
+PHY-3001 : End incremental legalization;  0.408612s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (99.4%)
+
+OPT-0007 : Iter 1: improved WNS -836 TNS -1321 NUM_FEPS 2 with 44 cells processed and 14762 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7042 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7130 instances, 6981 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3946 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 756744, Over = 0
+PHY-3001 : Spreading special nets. 21 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061907s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.0%)
+
+PHY-3001 : 26 instances has been re-located, deltaX = 14, deltaY = 16, maxDist = 2.
+PHY-3001 : Final: Len = 756900, Over = 0
+PHY-3001 : End incremental legalization;  0.397944s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.2%)
+
+OPT-0007 : Iter 2: improved WNS -836 TNS -1321 NUM_FEPS 2 with 28 cells processed and 5633 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7042 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7130 instances, 6981 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3946 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 756904, Over = 0
+PHY-3001 : Spreading special nets. 13 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063221s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.9%)
+
+PHY-3001 : 14 instances has been re-located, deltaX = 11, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 757022, Over = 0
+PHY-3001 : End incremental legalization;  0.394547s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (130.7%)
+
+OPT-0007 : Iter 3: improved WNS -836 TNS -1321 NUM_FEPS 2 with 18 cells processed and 1000 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7047 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7135 instances, 6986 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3947 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 758092, Over = 0
+PHY-3001 : Spreading special nets. 5 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062557s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.9%)
+
+PHY-3001 : 7 instances has been re-located, deltaX = 3, deltaY = 7, maxDist = 2.
+PHY-3001 : Final: Len = 758478, Over = 0
+PHY-3001 : End incremental legalization;  0.396088s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.6%)
+
+OPT-0007 : Iter 4: improved WNS -836 TNS -1321 NUM_FEPS 2 with 5 cells processed and 812 slack improved
+OPT-1001 : End bottleneck based optimization;  4.602939s wall, 4.171875s user + 0.000000s system = 4.171875s CPU (90.6%)
+
+OPT-1001 : Current memory(MB): used = 765, reserve = 758, peak = 768.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16054/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 939568, over cnt = 189(0%), over = 239, worst = 4
+PHY-1002 : len = 939632, over cnt = 87(0%), over = 97, worst = 3
+PHY-1002 : len = 940288, over cnt = 34(0%), over = 35, worst = 2
+PHY-1002 : len = 940568, over cnt = 12(0%), over = 12, worst = 1
+PHY-1002 : len = 940808, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.908908s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (104.9%)
+
+PHY-1001 : Congestion index: top1 = 55.56, top5 = 49.38, top10 = 46.57, top15 = 44.78.
+OPT-1001 : End congestion update;  1.231939s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (104.0%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.777873s wall, 0.781250s user + 0.000000s system = 0.781250s CPU (100.4%)
+
+OPT-0007 : Start: WNS -836 TNS -1321 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7047 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7135 instances, 6986 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3947 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 758526, Over = 0
+PHY-3001 : Spreading special nets. 8 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.067303s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (92.9%)
+
+PHY-3001 : 8 instances has been re-located, deltaX = 9, deltaY = 2, maxDist = 3.
+PHY-3001 : Final: Len = 758636, Over = 0
+PHY-3001 : End incremental legalization;  0.434007s wall, 0.515625s user + 0.000000s system = 0.515625s CPU (118.8%)
+
+OPT-0007 : Iter 1: improved WNS -836 TNS -1321 NUM_FEPS 2 with 16 cells processed and 1400 slack improved
+OPT-0007 : Iter 2: improved WNS -836 TNS -1321 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.584559s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (105.2%)
+
+OPT-1001 : Current memory(MB): used = 765, reserve = 758, peak = 768.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.740806s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16428/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940752, over cnt = 19(0%), over = 20, worst = 2
+PHY-1002 : len = 940712, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 940736, over cnt = 2(0%), over = 2, worst = 1
+PHY-1002 : len = 940768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.597801s wall, 0.593750s user + 0.000000s system = 0.593750s CPU (99.3%)
+
+PHY-1001 : Congestion index: top1 = 55.62, top5 = 49.42, top10 = 46.58, top15 = 44.78.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.739481s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.3%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS -836 TNS -1321 NUM_FEPS 2
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 55.206897
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack -836ps with logic level 2 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+RUN-1001 :   0 HFN exist on timing critical paths out of 18178 nets
+RUN-1001 :   0 long nets exist on timing critical paths out of 18178 nets
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7047 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7135 instances, 6986 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3947 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 758636, Over = 0
+PHY-3001 : End spreading;  0.061835s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.1%)
+
+PHY-3001 : Final: Len = 758636, Over = 0
+PHY-3001 : End incremental legalization;  0.392062s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (99.6%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.742885s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.0%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16456/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.133099s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (105.7%)
+
+PHY-1001 : Congestion index: top1 = 55.62, top5 = 49.42, top10 = 46.58, top15 = 44.78.
+OPT-1001 : End congestion update;  0.446976s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.740445s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.2%)
+
+OPT-0007 : Start: WNS -836 TNS -1321 NUM_FEPS 2
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7047 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7135 instances, 6986 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3947 pins
+PHY-3001 : Found 490 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 758620, Over = 0
+PHY-3001 : Spreading special nets. 1 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062225s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.4%)
+
+PHY-3001 : 1 instances has been re-located, deltaX = 1, deltaY = 0, maxDist = 1.
+PHY-3001 : Final: Len = 758636, Over = 0
+PHY-3001 : End incremental legalization;  0.392524s wall, 0.406250s user + 0.031250s system = 0.437500s CPU (111.5%)
+
+OPT-0007 : Iter 1: improved WNS -836 TNS -1321 NUM_FEPS 2 with 1 cells processed and 50 slack improved
+OPT-0007 : Iter 2: improved WNS -836 TNS -1321 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.692654s wall, 1.703125s user + 0.031250s system = 1.734375s CPU (102.5%)
+
+OPT-1001 : Current memory(MB): used = 765, reserve = 758, peak = 768.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16456/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.131759s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.9%)
+
+PHY-1001 : Congestion index: top1 = 55.62, top5 = 49.42, top10 = 46.58, top15 = 44.78.
+OPT-1001 : End congestion update;  0.447707s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (101.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.743220s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.8%)
+
+OPT-0007 : Start: WNS -836 TNS -1321 NUM_FEPS 2
+OPT-0007 : Iter 1: improved WNS -836 TNS -1321 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS -836 TNS -1321 NUM_FEPS 2 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.352959s wall, 1.359375s user + 0.000000s system = 1.359375s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 765, reserve = 758, peak = 768.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.740924s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (99.1%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 765, reserve = 758, peak = 768.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.741070s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.2%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16456/18178.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 940768, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.131964s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.7%)
+
+PHY-1001 : Congestion index: top1 = 55.62, top5 = 49.42, top10 = 46.58, top15 = 44.78.
+RUN-1001 : End congestion update;  0.452952s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.0%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.197218s wall, 1.203125s user + 0.000000s system = 1.203125s CPU (100.5%)
+
+OPT-1001 : Current memory(MB): used = 765, reserve = 758, peak = 768.
+OPT-1001 : End physical optimization;  28.297527s wall, 29.062500s user + 0.281250s system = 29.343750s CPU (103.7%)
+
+RUN-1003 : finish command "place" in  74.782839s wall, 102.031250s user + 6.484375s system = 108.515625s CPU (145.1%)
+
+RUN-1004 : used memory is 668 MB, reserved memory is 656 MB, peak memory is 768 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.746177s wall, 3.031250s user + 0.015625s system = 3.046875s CPU (174.5%)
+
+RUN-1004 : used memory is 669 MB, reserved memory is 657 MB, peak memory is 768 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7137 instances
+RUN-1001 : 3488 mslices, 3498 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18178 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10465 nets have 2 pins
+RUN-1001 : 5821 nets have [3 - 5] pins
+RUN-1001 : 1183 nets have [6 - 10] pins
+RUN-1001 : 329 nets have [11 - 20] pins
+RUN-1001 : 351 nets have [21 - 99] pins
+RUN-1001 : 9 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76277, tnet num: 18000, tinst num: 7135, tnode num: 99979, tedge num: 127674.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.643117s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.8%)
+
+RUN-1004 : used memory is 679 MB, reserved memory is 683 MB, peak memory is 768 MB
+PHY-1001 : 3488 mslices, 3498 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 867656, over cnt = 2883(8%), over = 4739, worst = 7
+PHY-1002 : len = 887848, over cnt = 1625(4%), over = 2319, worst = 6
+PHY-1002 : len = 908536, over cnt = 573(1%), over = 766, worst = 6
+PHY-1002 : len = 920848, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 921008, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  2.994163s wall, 4.156250s user + 0.078125s system = 4.234375s CPU (141.4%)
+
+PHY-1001 : Congestion index: top1 = 54.59, top5 = 48.77, top10 = 45.99, top15 = 44.29.
+PHY-1001 : End global routing;  3.332303s wall, 4.468750s user + 0.093750s system = 4.562500s CPU (136.9%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 742, reserve = 739, peak = 768.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1017, reserve = 1013, peak = 1017.
+PHY-1001 : End build detailed router design. 4.029511s wall, 3.968750s user + 0.062500s system = 4.031250s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271248, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.039162s wall, 5.031250s user + 0.000000s system = 5.031250s CPU (99.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271304, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.436929s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1052, reserve = 1048, peak = 1052.
+PHY-1001 : End phase 1; 5.487954s wall, 5.484375s user + 0.000000s system = 5.484375s CPU (99.9%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.37462e+06, over cnt = 1943(0%), over = 1947, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1069, reserve = 1064, peak = 1069.
+PHY-1001 : End initial routed; 30.739234s wall, 64.718750s user + 0.234375s system = 64.953125s CPU (211.3%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17101(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.220   |  -4.251   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.442627s wall, 3.437500s user + 0.000000s system = 3.437500s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1083, reserve = 1079, peak = 1083.
+PHY-1001 : End phase 2; 34.181923s wall, 68.156250s user + 0.234375s system = 68.390625s CPU (200.1%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -2.105ns STNS -4.146ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.147039s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (95.6%)
+
+PHY-1022 : len = 2.37465e+06, over cnt = 1945(0%), over = 1949, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.423035s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (99.7%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.3461e+06, over cnt = 946(0%), over = 946, worst = 1, crit = 0
+PHY-1001 : End DR Iter 1; 1.873709s wall, 2.781250s user + 0.000000s system = 2.781250s CPU (148.4%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.34215e+06, over cnt = 234(0%), over = 234, worst = 1, crit = 0
+PHY-1001 : End DR Iter 2; 0.831597s wall, 1.296875s user + 0.046875s system = 1.343750s CPU (161.6%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.34258e+06, over cnt = 36(0%), over = 36, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.605528s wall, 0.687500s user + 0.015625s system = 0.703125s CPU (116.1%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.34324e+06, over cnt = 7(0%), over = 7, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.249932s wall, 0.250000s user + 0.015625s system = 0.265625s CPU (106.3%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.34334e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.231559s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (101.2%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.34334e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.245547s wall, 0.234375s user + 0.000000s system = 0.234375s CPU (95.5%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.34334e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.378342s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (99.1%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.34334e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.173719s wall, 0.203125s user + 0.015625s system = 0.218750s CPU (125.9%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.34335e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.183666s wall, 0.203125s user + 0.000000s system = 0.203125s CPU (110.6%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17101(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -2.105   |  -4.146   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.457181s wall, 3.468750s user + 0.000000s system = 3.468750s CPU (100.3%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 587 feed throughs used by 439 nets
+PHY-1001 : End commit to database; 2.301576s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (99.1%)
+
+PHY-1001 : Current memory(MB): used = 1186, reserve = 1185, peak = 1186.
+PHY-1001 : End phase 3; 11.405757s wall, 12.890625s user + 0.109375s system = 13.000000s CPU (114.0%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -1.962ns STNS -4.003ns FEP 3.
+PHY-1001 : End OPT Iter 1; 0.148441s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (94.7%)
+
+PHY-1022 : len = 2.34334e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End optimize timing; 0.401120s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (97.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.962ns, -4.003ns, 3}
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.34335e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.170263s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (91.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 4/17101(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -1.962   |  -4.003   |   3   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.396665s wall, 3.375000s user + 0.015625s system = 3.390625s CPU (99.8%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 588 feed throughs used by 440 nets
+PHY-1001 : End commit to database; 2.393680s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (99.9%)
+
+PHY-1001 : Current memory(MB): used = 1196, reserve = 1196, peak = 1196.
+PHY-1001 : End phase 4; 6.407775s wall, 6.390625s user + 0.015625s system = 6.406250s CPU (100.0%)
+
+PHY-1003 : Routed, final wirelength = 2.34335e+06
+PHY-1001 : Current memory(MB): used = 1198, reserve = 1198, peak = 1198.
+PHY-1001 : End export database. 0.063676s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.2%)
+
+PHY-1001 : End detail routing;  61.985278s wall, 97.375000s user + 0.421875s system = 97.796875s CPU (157.8%)
+
+RUN-1003 : finish command "route" in  68.065268s wall, 104.593750s user + 0.515625s system = 105.109375s CPU (154.4%)
+
+RUN-1004 : used memory is 1121 MB, reserved memory is 1118 MB, peak memory is 1198 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10417   out of  19600   53.15%
+#reg                     9944   out of  19600   50.73%
+#le                     13071
+  #lut only              3127   out of  13071   23.92%
+  #reg only              2654   out of  13071   20.30%
+  #lut&reg               7290   out of  13071   55.77%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1826
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1427
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1343
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               1235
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    141
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             u_mipi_eot_min/reg1_syn_299.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               lslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_163.f0    3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P141       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P111       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P106       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P71        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |13071  |9390    |1027    |9976    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |545    |439     |23      |444     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |80      |4       |87      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |35     |35      |0       |24      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |777    |384     |96      |578     |0       |0       |
+|    u_ADconfig                |AD_config            |202    |136     |25      |149     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |160     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |741    |380     |96      |564     |0       |0       |
+|    u_ADconfig                |AD_config            |169    |124     |25      |127     |0       |0       |
+|    u_gen_sp                  |gen_sp               |255    |147     |71      |120     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3205   |2616    |306     |2067    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |183    |144     |17      |135     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2989   |2459    |289     |1900    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |4       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |0       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2587   |2139    |253     |1573    |22      |0       |
+|        channelPart           |channel_part_8478    |160    |155     |3       |127     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |39      |0       |0       |
+|        ram_switch            |ram_switch           |2025   |1638    |197     |1169    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |254    |226     |27      |113     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |23     |20      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |11      |0       |0       |
+|          insert              |insert               |988    |629     |170     |682     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |783    |783     |0       |374     |0       |0       |
+|        read_ram_i            |read_ram             |313    |266     |44      |209     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |251    |211     |40      |166     |0       |0       |
+|          read_ram_data       |read_ram_data        |57     |51      |4       |38      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |326    |252     |36      |271     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1      |0       |0       |1       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3166   |2463    |349     |2108    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |187    |105     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2947   |2343    |332     |1928    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |5       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |5       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2486   |1994    |290     |1575    |22      |1       |
+|        channelPart           |channel_part_8478    |275    |272     |3       |151     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |1757   |1392    |197     |1139    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |198    |169     |27      |122     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |8       |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |18      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |18      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|          insert              |insert               |1013   |681     |170     |673     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |546    |542     |0       |344     |0       |0       |
+|        read_ram_i            |read_ram_rev         |363    |258     |81      |213     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |298    |218     |73      |166     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |40      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10403  
+    #2         2       3900   
+    #3         3       1372   
+    #4         4        546   
+    #5        5-10     1245   
+    #6       11-50      589   
+    #7       51-100     27    
+    #8        >500       1    
+  Average     2.89            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.146930s wall, 3.687500s user + 0.000000s system = 3.687500s CPU (171.8%)
+
+RUN-1004 : used memory is 1122 MB, reserved memory is 1118 MB, peak memory is 1198 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76277, tnet num: 18000, tinst num: 7135, tnode num: 99979, tedge num: 127674.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.663071s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (100.5%)
+
+RUN-1004 : used memory is 1128 MB, reserved memory is 1125 MB, peak memory is 1198 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18000 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.518959s wall, 1.515625s user + 0.000000s system = 1.515625s CPU (99.8%)
+
+RUN-1004 : used memory is 1131 MB, reserved memory is 1128 MB, peak memory is 1198 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7135
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18178, pip num: 176377
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 588
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 490155 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.528032s wall, 63.640625s user + 0.171875s system = 63.812500s CPU (669.7%)
+
+RUN-1004 : used memory is 1299 MB, reserved memory is 1295 MB, peak memory is 1414 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_144554.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_145210.log b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_145210.log
new file mode 100644
index 0000000..76cbb20
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/phy_1/td_20240312_145210.log
@@ -0,0 +1,2179 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:52:10 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "import_db ../syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.470817s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (99.9%)
+
+RUN-1004 : used memory is 354 MB, reserved memory is 324 MB, peak memory is 358 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "place"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
+RUN-1001 : Print Place Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :      detailed_place     |     on     |        on        |        
+RUN-1001 :          effort         |   medium   |      medium      |        
+RUN-1001 :         fix_hold        |    off     |       off        |        
+RUN-1001 :       legalization      |    ori     |       ori        |        
+RUN-1001 :      new_spreading      |     on     |        on        |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
+RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
+RUN-1001 :       pr_strategy       |     1      |        1         |        
+RUN-1001 :        relaxation       |    1.00    |       1.00       |        
+RUN-1001 :         retiming        |    off     |       off        |        
+RUN-1001 : --------------------------------------------------------------
+PHY-3001 : Placer runs in 8 thread(s).
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+SYN-5055 WARNING: The kept net scan_start_diff/busy will be merged to another kept net BUSY_MIPI_sync_d1
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[31] will be merged to another kept net S_hs_data[31]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[30] will be merged to another kept net S_hs_data[30]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[29] will be merged to another kept net S_hs_data[29]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net u_mipi_dphy_tx_wrapper/I_hs_tx_data[28] will be merged to another kept net S_hs_data[28]
+SYN-5055 WARNING: The kept net U_rgb_to_csi_pakage/O_hs_data[27] will be merged to another kept net S_hs_data[27]
+SYN-5055 Similar messages will be suppressed.
+RUN-1002 : start command "phys_opt -simplify_lut"
+SYN-4016 : Net u_mipi_dphy_tx_wrapper/I_lpdt_clk driven by BUFG (2949 clock/control pins, 1 other pins).
+SYN-4016 : Net u_pll_lvds/clk0_out driven by BUFG (2212 clock/control pins, 2 other pins).
+SYN-4016 : Net uu_pll_lvds/clk0_out driven by BUFG (2052 clock/control pins, 2 other pins).
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 is clkc1 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 is clkc2 of pll u_pll/pll_inst.
+SYN-4027 : Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d is clkc3 of pll u_pll/pll_inst.
+SYN-4027 : Net exdev_ctl_a/clk_adc is clkc4 of pll u_pll/pll_inst.
+SYN-4019 : Net clock_source_dup_1 is refclk of pll u_pll/pll_inst.
+SYN-4020 : Net clock_source_dup_1 is fbclk of pll u_pll/pll_inst.
+SYN-4027 : Net ua_lvds_rx/sclk is clkc1 of pll u_pll_lvds/pll_inst.
+SYN-4019 : Net a_lvds_clk_p_dup_1 is refclk of pll u_pll_lvds/pll_inst.
+SYN-4020 : Net a_lvds_clk_p_dup_1 is fbclk of pll u_pll_lvds/pll_inst.
+SYN-4027 : Net ub_lvds_rx/sclk is clkc1 of pll uu_pll_lvds/pll_inst.
+SYN-4019 : Net b_lvds_clk_p_dup_1 is refclk of pll uu_pll_lvds/pll_inst.
+SYN-4020 : Net b_lvds_clk_p_dup_1 is fbclk of pll uu_pll_lvds/pll_inst.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/clk_config" drives clk pins.
+SYN-4024 : Net "exdev_ctl_a/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4024 : Net "exdev_ctl_b/u_ADconfig/gret9lit16_n" drives clk pins.
+SYN-4025 : Tag rtl::Net a_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net b_lvds_clk_p_dup_1 as clock net
+SYN-4025 : Tag rtl::Net clock_source_dup_1 as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/clk_adc as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/clk_config as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_a/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net exdev_ctl_b/u_ADconfig/gret9lit16_n as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/I_lpdt_clk as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 as clock net
+SYN-4025 : Tag rtl::Net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 as clock net
+SYN-4025 : Tag rtl::Net u_pll_lvds/clk0_out as clock net
+SYN-4025 : Tag rtl::Net ua_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net ub_lvds_rx/sclk as clock net
+SYN-4025 : Tag rtl::Net uu_pll_lvds/clk0_out as clock net
+SYN-4026 : Tagged 15 rtl::Net as clock net
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to drive 246 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 18313 instances
+RUN-0007 : 7475 luts, 9615 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20891 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 13879 nets have 2 pins
+RUN-1001 : 5557 nets have [3 - 5] pins
+RUN-1001 : 1043 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 180 nets have [21 - 99] pins
+RUN-1001 : 54 nets have 100+ pins
+PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
+RUN-1001 : Report Control nets information:
+RUN-1001 : DFF Distribution
+RUN-1001 : ----------------------------------
+RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
+RUN-1001 : ----------------------------------
+RUN-1001 :   No   |  No   |  No   |     793     
+RUN-1001 :   No   |  No   |  Yes  |    2540     
+RUN-1001 :   No   |  Yes  |  No   |    3473     
+RUN-1001 :   Yes  |  No   |  No   |     64      
+RUN-1001 :   Yes  |  No   |  Yes  |     72      
+RUN-1001 :   Yes  |  Yes  |  No   |    2673     
+RUN-1001 : ----------------------------------
+RUN-0007 : Control Group Statistic
+RUN-0007 : ---------------------------
+RUN-0007 :   #CLK  |  #CE  |  #SSR/ASR  
+RUN-0007 : ---------------------------
+RUN-0007 :    12   |  76   |     57     
+RUN-0007 : ---------------------------
+RUN-0007 : Control Set = 142
+PHY-3001 : Initial placement ...
+PHY-3001 : design contains 18311 instances, 7475 luts, 9615 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6469 pins
+PHY-0007 : Cell area utilization is 49%
+PHY-3001 : Start timing update ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.206386s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.7%)
+
+RUN-1004 : used memory is 552 MB, reserved memory is 529 MB, peak memory is 552 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.026228s wall, 2.000000s user + 0.031250s system = 2.031250s CPU (100.2%)
+
+PHY-3001 : Found 1222 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 4.00806e+06
+PHY-3001 : Clustering ...
+PHY-3001 : Level 0 #clusters 18311.
+PHY-3001 : Level 1 #clusters 2004.
+PHY-3001 : End clustering;  0.130135s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (144.1%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 49%
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(1): len = 1.25808e+06, overlap = 537.594
+PHY-3002 : Step(2): len = 1.17948e+06, overlap = 555.469
+PHY-3002 : Step(3): len = 805880, overlap = 617.25
+PHY-3002 : Step(4): len = 747389, overlap = 670.188
+PHY-3002 : Step(5): len = 580252, overlap = 828.438
+PHY-3002 : Step(6): len = 506405, overlap = 888.562
+PHY-3002 : Step(7): len = 438740, overlap = 953.062
+PHY-3002 : Step(8): len = 405793, overlap = 990.031
+PHY-3002 : Step(9): len = 368140, overlap = 999.406
+PHY-3002 : Step(10): len = 335219, overlap = 1063.25
+PHY-3002 : Step(11): len = 304746, overlap = 1095.97
+PHY-3002 : Step(12): len = 274497, overlap = 1117.5
+PHY-3002 : Step(13): len = 258167, overlap = 1150.56
+PHY-3002 : Step(14): len = 234928, overlap = 1220.59
+PHY-3002 : Step(15): len = 218432, overlap = 1280.91
+PHY-3002 : Step(16): len = 199574, overlap = 1330.09
+PHY-3002 : Step(17): len = 179244, overlap = 1360.41
+PHY-3002 : Step(18): len = 168619, overlap = 1364.97
+PHY-3002 : Step(19): len = 153530, overlap = 1394.62
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.37726e-06
+PHY-3002 : Step(20): len = 156286, overlap = 1372.84
+PHY-3002 : Step(21): len = 190148, overlap = 1281.91
+PHY-3002 : Step(22): len = 194863, overlap = 1229.56
+PHY-3002 : Step(23): len = 199569, overlap = 1171.84
+PHY-3002 : Step(24): len = 197760, overlap = 1203.22
+PHY-3002 : Step(25): len = 197337, overlap = 1227.56
+PHY-3002 : Step(26): len = 194838, overlap = 1227.19
+PHY-3002 : Step(27): len = 192802, overlap = 1221.19
+PHY-3002 : Step(28): len = 190823, overlap = 1218.09
+PHY-3002 : Step(29): len = 189585, overlap = 1208.81
+PHY-3002 : Step(30): len = 187401, overlap = 1200.69
+PHY-3002 : Step(31): len = 186285, overlap = 1197.38
+PHY-3002 : Step(32): len = 186493, overlap = 1166.91
+PHY-3002 : Step(33): len = 185759, overlap = 1155.12
+PHY-3002 : Step(34): len = 185102, overlap = 1127.38
+PHY-3002 : Step(35): len = 183975, overlap = 1115.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.75453e-06
+PHY-3002 : Step(36): len = 187471, overlap = 1107.03
+PHY-3002 : Step(37): len = 198764, overlap = 1090.66
+PHY-3002 : Step(38): len = 202928, overlap = 1067.75
+PHY-3002 : Step(39): len = 207381, overlap = 1034.38
+PHY-3002 : Step(40): len = 210559, overlap = 1015.44
+PHY-3002 : Step(41): len = 213446, overlap = 990
+PHY-3002 : Step(42): len = 212214, overlap = 968.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.50906e-06
+PHY-3002 : Step(43): len = 221098, overlap = 913.219
+PHY-3002 : Step(44): len = 242358, overlap = 819.594
+PHY-3002 : Step(45): len = 255165, overlap = 778.438
+PHY-3002 : Step(46): len = 267478, overlap = 731
+PHY-3002 : Step(47): len = 271662, overlap = 720.438
+PHY-3002 : Step(48): len = 271709, overlap = 706.906
+PHY-3002 : Step(49): len = 270113, overlap = 680
+PHY-3002 : Step(50): len = 269630, overlap = 679.875
+PHY-3002 : Step(51): len = 267425, overlap = 688.156
+PHY-3002 : Step(52): len = 265303, overlap = 695.812
+PHY-3002 : Step(53): len = 262713, overlap = 706.719
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.10181e-05
+PHY-3002 : Step(54): len = 281886, overlap = 673.031
+PHY-3002 : Step(55): len = 297627, overlap = 598.438
+PHY-3002 : Step(56): len = 304406, overlap = 543.031
+PHY-3002 : Step(57): len = 308710, overlap = 545.219
+PHY-3002 : Step(58): len = 307694, overlap = 551.438
+PHY-3002 : Step(59): len = 307802, overlap = 554.938
+PHY-3002 : Step(60): len = 304819, overlap = 550.656
+PHY-3002 : Step(61): len = 305086, overlap = 548.125
+PHY-3002 : Step(62): len = 303942, overlap = 549.188
+PHY-3002 : Step(63): len = 304623, overlap = 548.75
+PHY-3002 : Step(64): len = 301771, overlap = 538.562
+PHY-3002 : Step(65): len = 301740, overlap = 527.969
+PHY-3002 : Step(66): len = 301591, overlap = 528.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.20362e-05
+PHY-3002 : Step(67): len = 316913, overlap = 533.75
+PHY-3002 : Step(68): len = 328114, overlap = 511.719
+PHY-3002 : Step(69): len = 332758, overlap = 471.406
+PHY-3002 : Step(70): len = 335310, overlap = 472.625
+PHY-3002 : Step(71): len = 334783, overlap = 483.938
+PHY-3002 : Step(72): len = 337780, overlap = 470.219
+PHY-3002 : Step(73): len = 338712, overlap = 458.938
+PHY-3002 : Step(74): len = 340455, overlap = 459.062
+PHY-3002 : Step(75): len = 339404, overlap = 467.625
+PHY-3002 : Step(76): len = 340251, overlap = 463.375
+PHY-3002 : Step(77): len = 339541, overlap = 456.281
+PHY-3002 : Step(78): len = 340666, overlap = 462.219
+PHY-3002 : Step(79): len = 339598, overlap = 465.75
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.40725e-05
+PHY-3002 : Step(80): len = 358475, overlap = 417.094
+PHY-3002 : Step(81): len = 371673, overlap = 392.438
+PHY-3002 : Step(82): len = 371429, overlap = 384
+PHY-3002 : Step(83): len = 373076, overlap = 377.188
+PHY-3002 : Step(84): len = 375376, overlap = 382.594
+PHY-3002 : Step(85): len = 379126, overlap = 374.875
+PHY-3002 : Step(86): len = 376946, overlap = 358.219
+PHY-3002 : Step(87): len = 380036, overlap = 349.438
+PHY-3002 : Step(88): len = 381497, overlap = 324.781
+PHY-3002 : Step(89): len = 383751, overlap = 328.844
+PHY-3002 : Step(90): len = 378101, overlap = 320.062
+PHY-3002 : Step(91): len = 377588, overlap = 307.562
+PHY-3002 : Step(92): len = 380210, overlap = 315.656
+PHY-3002 : Step(93): len = 382216, overlap = 309.469
+PHY-3002 : Step(94): len = 377413, overlap = 316.156
+PHY-3002 : Step(95): len = 376819, overlap = 314.219
+PHY-3002 : Step(96): len = 378971, overlap = 320.594
+PHY-3002 : Step(97): len = 381832, overlap = 309.156
+PHY-3002 : Step(98): len = 378679, overlap = 322.562
+PHY-3002 : Step(99): len = 378909, overlap = 328.312
+PHY-3002 : Step(100): len = 381466, overlap = 320.75
+PHY-3002 : Step(101): len = 383108, overlap = 322.375
+PHY-3002 : Step(102): len = 379254, overlap = 323.375
+PHY-3002 : Step(103): len = 378855, overlap = 336.344
+PHY-3002 : Step(104): len = 382473, overlap = 334.438
+PHY-3002 : Step(105): len = 385118, overlap = 324.469
+PHY-3002 : Step(106): len = 379894, overlap = 330
+PHY-3002 : Step(107): len = 379380, overlap = 334
+PHY-3002 : Step(108): len = 381186, overlap = 337.844
+PHY-3002 : Step(109): len = 383820, overlap = 343.094
+PHY-3002 : Step(110): len = 380397, overlap = 343.188
+PHY-3002 : Step(111): len = 380110, overlap = 335.906
+PHY-3002 : Step(112): len = 381876, overlap = 333.656
+PHY-3002 : Step(113): len = 382988, overlap = 331.688
+PHY-3002 : Step(114): len = 379633, overlap = 340.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.69695e-05
+PHY-3002 : Step(115): len = 396380, overlap = 324.281
+PHY-3002 : Step(116): len = 404504, overlap = 316.625
+PHY-3002 : Step(117): len = 402189, overlap = 319.906
+PHY-3002 : Step(118): len = 402844, overlap = 307.562
+PHY-3002 : Step(119): len = 407559, overlap = 300.656
+PHY-3002 : Step(120): len = 410960, overlap = 293.938
+PHY-3002 : Step(121): len = 409023, overlap = 313.469
+PHY-3002 : Step(122): len = 410609, overlap = 307.719
+PHY-3002 : Step(123): len = 413005, overlap = 302.188
+PHY-3002 : Step(124): len = 415370, overlap = 304.281
+PHY-3002 : Step(125): len = 411929, overlap = 304.812
+PHY-3002 : Step(126): len = 411455, overlap = 301.156
+PHY-3002 : Step(127): len = 413253, overlap = 297.406
+PHY-3002 : Step(128): len = 415569, overlap = 296.688
+PHY-3002 : Step(129): len = 413280, overlap = 298.125
+PHY-3002 : Step(130): len = 414014, overlap = 299.562
+PHY-3002 : Step(131): len = 415804, overlap = 291.688
+PHY-3002 : Step(132): len = 416706, overlap = 287.562
+PHY-3002 : Step(133): len = 414488, overlap = 293.062
+PHY-3002 : Step(134): len = 414222, overlap = 296.188
+PHY-3002 : Step(135): len = 416186, overlap = 297.844
+PHY-3002 : Step(136): len = 418247, overlap = 297.594
+PHY-3002 : Step(137): len = 415157, overlap = 307.406
+PHY-3002 : Step(138): len = 414792, overlap = 302.969
+PHY-3002 : Step(139): len = 416141, overlap = 297.094
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000173939
+PHY-3002 : Step(140): len = 429093, overlap = 281.469
+PHY-3002 : Step(141): len = 436379, overlap = 267.344
+PHY-3002 : Step(142): len = 436546, overlap = 270.844
+PHY-3002 : Step(143): len = 437380, overlap = 260
+PHY-3002 : Step(144): len = 439507, overlap = 261.031
+PHY-3002 : Step(145): len = 442472, overlap = 260.094
+PHY-3002 : Step(146): len = 443304, overlap = 254.219
+PHY-3002 : Step(147): len = 444774, overlap = 251.031
+PHY-3002 : Step(148): len = 447138, overlap = 255.531
+PHY-3002 : Step(149): len = 448747, overlap = 255.688
+PHY-3002 : Step(150): len = 447451, overlap = 243.031
+PHY-3002 : Step(151): len = 447432, overlap = 241.656
+PHY-3002 : Step(152): len = 447994, overlap = 237.375
+PHY-3002 : Step(153): len = 448451, overlap = 237.281
+PHY-3002 : Step(154): len = 446798, overlap = 237.188
+PHY-3002 : Step(155): len = 446275, overlap = 236.5
+PHY-3002 : Step(156): len = 447543, overlap = 230.219
+PHY-3002 : Step(157): len = 449128, overlap = 220.375
+PHY-3002 : Step(158): len = 447139, overlap = 219.219
+PHY-3002 : Step(159): len = 446549, overlap = 211.5
+PHY-3002 : Step(160): len = 447169, overlap = 214.344
+PHY-3002 : Step(161): len = 447800, overlap = 215.125
+PHY-3002 : Step(162): len = 446898, overlap = 207.406
+PHY-3002 : Step(163): len = 446875, overlap = 201.406
+PHY-3002 : Step(164): len = 447304, overlap = 210.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000347504
+PHY-3002 : Step(165): len = 457687, overlap = 210.438
+PHY-3002 : Step(166): len = 465640, overlap = 207.938
+PHY-3002 : Step(167): len = 466285, overlap = 204.312
+PHY-3002 : Step(168): len = 467249, overlap = 195.25
+PHY-3002 : Step(169): len = 469554, overlap = 192.719
+PHY-3002 : Step(170): len = 471718, overlap = 200
+PHY-3002 : Step(171): len = 471191, overlap = 203.031
+PHY-3002 : Step(172): len = 471762, overlap = 203.625
+PHY-3002 : Step(173): len = 474201, overlap = 204.312
+PHY-3002 : Step(174): len = 475784, overlap = 201.562
+PHY-3002 : Step(175): len = 474873, overlap = 204.906
+PHY-3002 : Step(176): len = 474276, overlap = 202.906
+PHY-3002 : Step(177): len = 475208, overlap = 198.844
+PHY-3002 : Step(178): len = 478795, overlap = 189.438
+PHY-3002 : Step(179): len = 478779, overlap = 190.219
+PHY-3002 : Step(180): len = 479429, overlap = 196.031
+PHY-3002 : Step(181): len = 480439, overlap = 190.375
+PHY-3002 : Step(182): len = 481046, overlap = 190.844
+PHY-3002 : Step(183): len = 480074, overlap = 193.062
+PHY-3002 : Step(184): len = 479914, overlap = 196.062
+PHY-3002 : Step(185): len = 480011, overlap = 187.688
+PHY-3002 : Step(186): len = 480060, overlap = 186.594
+PHY-3002 : Step(187): len = 479977, overlap = 191.312
+PHY-3002 : Step(188): len = 480291, overlap = 189.219
+PHY-3002 : Step(189): len = 480033, overlap = 187.594
+PHY-3002 : Step(190): len = 480026, overlap = 184.906
+PHY-3002 : Step(191): len = 480182, overlap = 185.344
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000629862
+PHY-3002 : Step(192): len = 484636, overlap = 185
+PHY-3002 : Step(193): len = 491568, overlap = 188.906
+PHY-3002 : Step(194): len = 492459, overlap = 174.625
+PHY-3002 : Step(195): len = 493328, overlap = 178.156
+PHY-3002 : Step(196): len = 494684, overlap = 175.781
+PHY-3002 : Step(197): len = 495973, overlap = 182.688
+PHY-3002 : Step(198): len = 496068, overlap = 180.688
+PHY-3002 : Step(199): len = 496492, overlap = 179.375
+PHY-3002 : Step(200): len = 497525, overlap = 179.062
+PHY-3002 : Step(201): len = 497860, overlap = 178.938
+PHY-3002 : Step(202): len = 497995, overlap = 176.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00106194
+PHY-3002 : Step(203): len = 501189, overlap = 172.438
+PHY-3002 : Step(204): len = 505162, overlap = 170.562
+PHY-3002 : Step(205): len = 505875, overlap = 159.469
+PHY-3002 : Step(206): len = 506812, overlap = 163.594
+PHY-3002 : Step(207): len = 509113, overlap = 160.812
+PHY-3002 : Step(208): len = 511531, overlap = 160.969
+PHY-3002 : Step(209): len = 512285, overlap = 163.625
+PHY-3002 : Step(210): len = 512751, overlap = 164.281
+PHY-3002 : Step(211): len = 513549, overlap = 160.531
+PHY-3002 : Step(212): len = 514423, overlap = 165.031
+PHY-3002 : Step(213): len = 514641, overlap = 168.281
+PHY-3002 : Step(214): len = 515054, overlap = 166.562
+PHY-3002 : Step(215): len = 515798, overlap = 163.719
+PHY-3002 : Step(216): len = 516032, overlap = 161.594
+PHY-3002 : Step(217): len = 516078, overlap = 162.438
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0017657
+PHY-3002 : Step(218): len = 519424, overlap = 162.188
+PHY-3002 : Step(219): len = 528170, overlap = 161.281
+PHY-3002 : Step(220): len = 528993, overlap = 160.875
+PHY-3002 : Step(221): len = 529757, overlap = 166
+PHY-3002 : Step(222): len = 531547, overlap = 169.75
+PHY-3002 : Step(223): len = 532471, overlap = 171.062
+PHY-3002 : Step(224): len = 532202, overlap = 169.25
+PHY-3002 : Step(225): len = 532186, overlap = 160.906
+PHY-3002 : Step(226): len = 533182, overlap = 164.469
+PHY-3002 : Step(227): len = 534273, overlap = 161.219
+PHY-3002 : Step(228): len = 534293, overlap = 156.25
+PHY-3002 : Step(229): len = 534480, overlap = 155.875
+PHY-3002 : Step(230): len = 535266, overlap = 157.812
+PHY-3002 : Step(231): len = 535593, overlap = 158.156
+PHY-3002 : Step(232): len = 535598, overlap = 156.781
+PHY-3002 : Step(233): len = 535732, overlap = 156.344
+PHY-3002 : Step(234): len = 536545, overlap = 158.906
+PHY-3002 : Step(235): len = 537668, overlap = 158.875
+PHY-3002 : Step(236): len = 537696, overlap = 160.156
+PHY-3002 : Step(237): len = 537796, overlap = 157.844
+PHY-3002 : Step(238): len = 538367, overlap = 157.031
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.014376s wall, 0.015625s user + 0.046875s system = 0.062500s CPU (434.7%)
+
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+RUN-1001 : Building simple global routing graph ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 0/20891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 706104, over cnt = 1605(4%), over = 7585, worst = 45
+PHY-1001 : End global iterations;  0.688595s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (136.1%)
+
+PHY-1001 : Congestion index: top1 = 81.38, top5 = 61.13, top10 = 52.56, top15 = 47.12.
+PHY-3001 : End congestion estimation;  0.911135s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (126.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.876627s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (101.6%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000147396
+PHY-3002 : Step(239): len = 641511, overlap = 105.406
+PHY-3002 : Step(240): len = 640037, overlap = 96.4375
+PHY-3002 : Step(241): len = 635785, overlap = 90.5938
+PHY-3002 : Step(242): len = 635141, overlap = 80.8438
+PHY-3002 : Step(243): len = 635198, overlap = 74.8125
+PHY-3002 : Step(244): len = 631981, overlap = 69.3125
+PHY-3002 : Step(245): len = 628790, overlap = 63.875
+PHY-3002 : Step(246): len = 627388, overlap = 61.75
+PHY-3002 : Step(247): len = 624297, overlap = 57.1875
+PHY-3002 : Step(248): len = 620643, overlap = 57.3125
+PHY-3002 : Step(249): len = 618809, overlap = 59.7188
+PHY-3002 : Step(250): len = 616473, overlap = 58.375
+PHY-3002 : Step(251): len = 614842, overlap = 52.0312
+PHY-3002 : Step(252): len = 614370, overlap = 51.6562
+PHY-3002 : Step(253): len = 613433, overlap = 50.5938
+PHY-3002 : Step(254): len = 612101, overlap = 51.4375
+PHY-3002 : Step(255): len = 611656, overlap = 55.5312
+PHY-3002 : Step(256): len = 609221, overlap = 55.7812
+PHY-3002 : Step(257): len = 607441, overlap = 55.875
+PHY-3002 : Step(258): len = 605551, overlap = 56.7812
+PHY-3002 : Step(259): len = 603713, overlap = 56.9375
+PHY-3002 : Step(260): len = 601945, overlap = 58.375
+PHY-3002 : Step(261): len = 600761, overlap = 58.9688
+PHY-3002 : Step(262): len = 599246, overlap = 57.5312
+PHY-3002 : Step(263): len = 598384, overlap = 54.0625
+PHY-3002 : Step(264): len = 597774, overlap = 54.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000294791
+PHY-3002 : Step(265): len = 602124, overlap = 52.9062
+PHY-3002 : Step(266): len = 602124, overlap = 52.9062
+PHY-3002 : Step(267): len = 602455, overlap = 51.9375
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 102/20891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 684712, over cnt = 2538(7%), over = 10926, worst = 61
+PHY-1001 : End global iterations;  1.668208s wall, 2.125000s user + 0.015625s system = 2.140625s CPU (128.3%)
+
+PHY-1001 : Congestion index: top1 = 79.40, top5 = 62.52, top10 = 54.61, top15 = 49.89.
+PHY-3001 : End congestion estimation;  1.942959s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (123.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.903062s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.83893e-05
+PHY-3002 : Step(268): len = 602232, overlap = 264.625
+PHY-3002 : Step(269): len = 606216, overlap = 234.656
+PHY-3002 : Step(270): len = 600744, overlap = 225.219
+PHY-3002 : Step(271): len = 599256, overlap = 214.812
+PHY-3002 : Step(272): len = 596499, overlap = 207.125
+PHY-3002 : Step(273): len = 593592, overlap = 190.25
+PHY-3002 : Step(274): len = 593046, overlap = 180.375
+PHY-3002 : Step(275): len = 589416, overlap = 180.781
+PHY-3002 : Step(276): len = 587384, overlap = 179.938
+PHY-3002 : Step(277): len = 586438, overlap = 174.219
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000156779
+PHY-3002 : Step(278): len = 585723, overlap = 170.719
+PHY-3002 : Step(279): len = 588639, overlap = 164.906
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000298785
+PHY-3002 : Step(280): len = 597053, overlap = 150.094
+PHY-3002 : Step(281): len = 605801, overlap = 136.844
+PHY-3002 : Step(282): len = 609405, overlap = 129
+PHY-3002 : Step(283): len = 609633, overlap = 127.938
+PHY-3002 : Step(284): len = 609883, overlap = 125.094
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000597571
+PHY-3002 : Step(285): len = 612494, overlap = 118.562
+PHY-3002 : Step(286): len = 618492, overlap = 112.938
+PHY-3002 : Step(287): len = 622904, overlap = 102.719
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.460893s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.5%)
+
+RUN-1004 : used memory is 596 MB, reserved memory is 578 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 433.69 peak overflow 3.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 1484/20891.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 721464, over cnt = 3027(8%), over = 11212, worst = 32
+PHY-1001 : End global iterations;  1.187443s wall, 1.734375s user + 0.046875s system = 1.781250s CPU (150.0%)
+
+PHY-1001 : Congestion index: top1 = 70.32, top5 = 57.04, top10 = 50.86, top15 = 47.22.
+PHY-1001 : End incremental global routing;  1.526473s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (138.2%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20713 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.952616s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.1%)
+
+OPT-1001 : 50 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 18176 has valid locations, 336 needs to be replaced
+PHY-3001 : design contains 18597 instances, 7580 luts, 9796 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6584 pins
+PHY-3001 : Found 1231 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 646398
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16965/21177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 736936, over cnt = 3085(8%), over = 11319, worst = 32
+PHY-1001 : End global iterations;  0.236596s wall, 0.375000s user + 0.046875s system = 0.421875s CPU (178.3%)
+
+PHY-1001 : Congestion index: top1 = 70.15, top5 = 57.25, top10 = 51.37, top15 = 47.64.
+PHY-3001 : End congestion estimation;  0.492914s wall, 0.609375s user + 0.046875s system = 0.656250s CPU (133.1%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88307, tnet num: 20999, tinst num: 18597, tnode num: 120641, tedge num: 141346.
+TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.476353s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.5%)
+
+RUN-1004 : used memory is 642 MB, reserved memory is 641 MB, peak memory is 740 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.836114s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (100.3%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(288): len = 645449, overlap = 0.28125
+PHY-3002 : Step(289): len = 645089, overlap = 0.1875
+PHY-3002 : Step(290): len = 644945, overlap = 0.125
+PHY-3002 : Step(291): len = 644686, overlap = 0.1875
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 57%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 17109/21177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 735064, over cnt = 3094(8%), over = 11333, worst = 32
+PHY-1001 : End global iterations;  0.184287s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (152.6%)
+
+PHY-1001 : Congestion index: top1 = 70.75, top5 = 57.57, top10 = 51.49, top15 = 47.80.
+PHY-3001 : End congestion estimation;  0.439402s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (120.9%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 20999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.327813s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000425296
+PHY-3002 : Step(292): len = 644677, overlap = 104.375
+PHY-3002 : Step(293): len = 644738, overlap = 104.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000850593
+PHY-3002 : Step(294): len = 644784, overlap = 105.688
+PHY-3002 : Step(295): len = 645163, overlap = 106.156
+PHY-3001 : Final: Len = 645163, Over = 106.156
+PHY-3001 : End incremental placement;  5.757935s wall, 6.187500s user + 0.156250s system = 6.343750s CPU (110.2%)
+
+OPT-1001 : Total overflow 440.84 peak overflow 3.00
+OPT-1001 : End high-fanout net optimization;  8.788392s wall, 9.781250s user + 0.218750s system = 10.000000s CPU (113.8%)
+
+OPT-1001 : Current memory(MB): used = 741, reserve = 729, peak = 759.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17031/21177.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 738344, over cnt = 3046(8%), over = 10371, worst = 32
+PHY-1002 : len = 787592, over cnt = 2141(6%), over = 5560, worst = 22
+PHY-1002 : len = 839104, over cnt = 840(2%), over = 1899, worst = 15
+PHY-1002 : len = 860952, over cnt = 225(0%), over = 430, worst = 11
+PHY-1002 : len = 868704, over cnt = 15(0%), over = 15, worst = 1
+PHY-1001 : End global iterations;  2.151436s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (132.9%)
+
+PHY-1001 : Congestion index: top1 = 57.20, top5 = 50.49, top10 = 46.81, top15 = 44.58.
+OPT-1001 : End congestion update;  2.414332s wall, 3.125000s user + 0.015625s system = 3.140625s CPU (130.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 20999 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.861345s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%)
+
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 122 cells processed and 17592 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 40 cells processed and 5550 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 350 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved
+OPT-1001 : End bottleneck based optimization;  3.685889s wall, 4.390625s user + 0.015625s system = 4.406250s CPU (119.5%)
+
+OPT-1001 : Current memory(MB): used = 718, reserve = 708, peak = 759.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17073/21182.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 869152, over cnt = 117(0%), over = 155, worst = 5
+PHY-1002 : len = 868936, over cnt = 77(0%), over = 92, worst = 4
+PHY-1002 : len = 869448, over cnt = 28(0%), over = 29, worst = 2
+PHY-1002 : len = 869560, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 870112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.740435s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (103.4%)
+
+PHY-1001 : Congestion index: top1 = 56.85, top5 = 50.10, top10 = 46.58, top15 = 44.41.
+OPT-1001 : End congestion update;  1.011846s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (103.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21004 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.823754s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (98.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 7500 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.954227s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (101.5%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 759.
+OPT-1001 : End physical optimization;  16.200395s wall, 17.875000s user + 0.296875s system = 18.171875s CPU (112.2%)
+
+PHY-3001 : Start packing ...
+SYN-4007 : Packing 0 MUX to BLE ...
+SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
+SYN-4007 : Packing 7580 LUT to BLE ...
+SYN-4008 : Packed 7580 LUT and 3158 SEQ to BLE.
+SYN-4003 : Packing 6643 remaining SEQ's ...
+SYN-4005 : Packed 3910 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2733 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10313/15192 primitive instances ...
+PHY-3001 : End packing;  1.740255s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.7%)
+
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+RUN-1001 : There are total 7112 instances
+RUN-1001 : 3482 mslices, 3482 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18155 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10478 nets have 2 pins
+RUN-1001 : 5820 nets have [3 - 5] pins
+RUN-1001 : 1171 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
+RUN-1001 : 12 nets have 100+ pins
+PHY-3001 : design contains 7110 instances, 6964 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3890 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : After packing: Len = 658208, Over = 310.5
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 7633/18155.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 812144, over cnt = 2024(5%), over = 3420, worst = 9
+PHY-1002 : len = 820920, over cnt = 1386(3%), over = 2044, worst = 7
+PHY-1002 : len = 830728, over cnt = 842(2%), over = 1233, worst = 6
+PHY-1002 : len = 843928, over cnt = 332(0%), over = 466, worst = 6
+PHY-1002 : len = 852432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.661414s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (135.4%)
+
+PHY-1001 : Congestion index: top1 = 59.09, top5 = 50.37, top10 = 46.64, top15 = 44.09.
+PHY-3001 : End congestion estimation;  2.063662s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (128.7%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75983, tnet num: 17977, tinst num: 7110, tnode num: 99613, tedge num: 127314.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.666912s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (100.3%)
+
+RUN-1004 : used memory is 639 MB, reserved memory is 634 MB, peak memory is 759 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17977 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.574225s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (100.2%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.15623e-05
+PHY-3002 : Step(296): len = 644818, overlap = 308.5
+PHY-3002 : Step(297): len = 638418, overlap = 308.25
+PHY-3002 : Step(298): len = 634474, overlap = 314.25
+PHY-3002 : Step(299): len = 632259, overlap = 317
+PHY-3002 : Step(300): len = 630446, overlap = 318.25
+PHY-3002 : Step(301): len = 628888, overlap = 310.25
+PHY-3002 : Step(302): len = 627240, overlap = 304.5
+PHY-3002 : Step(303): len = 625948, overlap = 300
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.31246e-05
+PHY-3002 : Step(304): len = 630038, overlap = 294.25
+PHY-3002 : Step(305): len = 633929, overlap = 286.75
+PHY-3002 : Step(306): len = 633553, overlap = 288.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000166249
+PHY-3002 : Step(307): len = 644507, overlap = 273.25
+PHY-3002 : Step(308): len = 652926, overlap = 259
+PHY-3002 : Step(309): len = 651075, overlap = 265.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000332498
+PHY-3002 : Step(310): len = 659753, overlap = 252.75
+PHY-3002 : Step(311): len = 674197, overlap = 230
+PHY-3002 : Step(312): len = 672323, overlap = 229.5
+PHY-3002 : Step(313): len = 670444, overlap = 225.25
+PHY-3002 : Step(314): len = 670963, overlap = 218.75
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.377444s wall, 0.421875s user + 0.546875s system = 0.968750s CPU (256.7%)
+
+PHY-3001 : Trial Legalized: Len = 754658
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 690/18155.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 872960, over cnt = 2762(7%), over = 4649, worst = 6
+PHY-1002 : len = 890384, over cnt = 1683(4%), over = 2460, worst = 6
+PHY-1002 : len = 911080, over cnt = 619(1%), over = 883, worst = 6
+PHY-1002 : len = 920896, over cnt = 198(0%), over = 280, worst = 4
+PHY-1002 : len = 925576, over cnt = 6(0%), over = 6, worst = 1
+PHY-1001 : End global iterations;  2.382388s wall, 3.484375s user + 0.015625s system = 3.500000s CPU (146.9%)
+
+PHY-1001 : Congestion index: top1 = 56.08, top5 = 50.39, top10 = 47.39, top15 = 45.29.
+PHY-3001 : End congestion estimation;  2.843501s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (139.0%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17977 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  1.050007s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (99.7%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155905
+PHY-3002 : Step(315): len = 726001, overlap = 47
+PHY-3002 : Step(316): len = 708939, overlap = 79
+PHY-3002 : Step(317): len = 693934, overlap = 107
+PHY-3002 : Step(318): len = 682022, overlap = 134.25
+PHY-3002 : Step(319): len = 675303, overlap = 153.75
+PHY-3002 : Step(320): len = 670910, overlap = 166.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000311809
+PHY-3002 : Step(321): len = 675899, overlap = 161
+PHY-3002 : Step(322): len = 680411, overlap = 157.25
+PHY-3002 : Step(323): len = 680703, overlap = 159
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000623619
+PHY-3002 : Step(324): len = 685248, overlap = 162
+PHY-3002 : Step(325): len = 694537, overlap = 157.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.036878s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (127.1%)
+
+PHY-3001 : Legalized: Len = 726660, Over = 0
+PHY-3001 : Spreading special nets. 535 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.122626s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.9%)
+
+PHY-3001 : 792 instances has been re-located, deltaX = 311, deltaY = 496, maxDist = 3.
+PHY-3001 : Final: Len = 740432, Over = 0
+PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
+PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
+OPT-1001 : Start physical optimization ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75983, tnet num: 17977, tinst num: 7113, tnode num: 99613, tedge num: 127314.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.912544s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (99.7%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 669 MB, peak memory is 759 MB
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : Start high-fanout net optimization ...
+OPT-1001 : Update timing in global mode
+PHY-1001 : Start incremental global routing, caller is place ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 4601/18155.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 875920, over cnt = 2595(7%), over = 4177, worst = 7
+PHY-1002 : len = 892216, over cnt = 1474(4%), over = 2070, worst = 7
+PHY-1002 : len = 907184, over cnt = 609(1%), over = 815, worst = 7
+PHY-1002 : len = 916400, over cnt = 215(0%), over = 283, worst = 6
+PHY-1002 : len = 920760, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations;  2.048733s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (139.6%)
+
+PHY-1001 : Congestion index: top1 = 54.18, top5 = 48.76, top10 = 46.25, top15 = 44.51.
+PHY-1001 : End incremental global routing;  2.414312s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (133.3%)
+
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 17977 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.934980s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.3%)
+
+OPT-1001 : 6 high-fanout net processed.
+PHY-3001 : Start incremental placement ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7019 has valid locations, 30 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Global placement ...
+PHY-3001 : Initial: Len = 744753
+PHY-3001 : Run with size of 4
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16430/18187.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 926080, over cnt = 136(0%), over = 159, worst = 4
+PHY-1002 : len = 926352, over cnt = 49(0%), over = 50, worst = 2
+PHY-1002 : len = 926744, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 926864, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 926928, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.030650s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (83.4%)
+
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.91, top10 = 46.39, top15 = 44.65.
+PHY-3001 : End congestion estimation;  1.349627s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (86.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76272, tnet num: 18009, tinst num: 7137, tnode num: 99971, tedge num: 127701.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.886720s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.2%)
+
+RUN-1004 : used memory is 685 MB, reserved memory is 685 MB, peak memory is 759 MB
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18009 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 Similar messages will be suppressed.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  2.797503s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (100.0%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
+PHY-3002 : Step(326): len = 743867, overlap = 0
+PHY-3002 : Step(327): len = 743305, overlap = 0
+PHY-3001 : Run with size of 2
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Analyzing congestion ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Incremental mode ON
+PHY-1001 : Reuse net number 16418/18187.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 924720, over cnt = 82(0%), over = 103, worst = 5
+PHY-1002 : len = 924960, over cnt = 35(0%), over = 37, worst = 2
+PHY-1002 : len = 925400, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 925448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.595471s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (105.0%)
+
+PHY-1001 : Congestion index: top1 = 54.44, top5 = 48.92, top10 = 46.35, top15 = 44.58.
+PHY-3001 : End congestion estimation;  0.911954s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (102.8%)
+
+PHY-3001 : Update density targets...
+PHY-3001 : Update congestion history...
+PHY-3001 : Update timing in global mode ...
+TMR-2503 : Start to update net delay, extr mode = 5.
+TMR-2504 : Update delay of 18009 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 5.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-3001 : End timing update;  0.887492s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.4%)
+
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000923339
+PHY-3002 : Step(328): len = 743215, overlap = 2.75
+PHY-3002 : Step(329): len = 743191, overlap = 2.25
+PHY-3001 : Legalization ...
+PHY-3001 : End legalization;  0.005560s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+
+PHY-3001 : Legalized: Len = 743458, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062842s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%)
+
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 743452, Over = 0
+PHY-3001 : End incremental placement;  6.439997s wall, 6.546875s user + 0.109375s system = 6.656250s CPU (103.4%)
+
+OPT-1001 : Total overflow 0.00 peak overflow 0.00
+OPT-1001 : End high-fanout net optimization;  10.287435s wall, 11.187500s user + 0.125000s system = 11.312500s CPU (110.0%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16399/18187.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 925280, over cnt = 75(0%), over = 98, worst = 6
+PHY-1002 : len = 925352, over cnt = 34(0%), over = 38, worst = 3
+PHY-1002 : len = 925488, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 925616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.595918s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (107.5%)
+
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.82, top10 = 46.31, top15 = 44.55.
+OPT-1001 : End congestion update;  0.906222s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (105.2%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18009 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.751194s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.8%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 747310, Over = 0
+PHY-3001 : Spreading special nets. 23 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.070216s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.3%)
+
+PHY-3001 : 32 instances has been re-located, deltaX = 22, deltaY = 14, maxDist = 2.
+PHY-3001 : Final: Len = 747890, Over = 0
+PHY-3001 : End incremental legalization;  0.441613s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.1%)
+
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 48 cells processed and 14898 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 749174, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062913s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.3%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 8, deltaY = 19, maxDist = 3.
+PHY-3001 : Final: Len = 749554, Over = 0
+PHY-3001 : End incremental legalization;  0.438820s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (124.6%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 30 cells processed and 4936 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 749714, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064612s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.7%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 4, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 750026, Over = 0
+PHY-3001 : End incremental legalization;  0.396699s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.5%)
+
+OPT-0007 : Iter 3: improved WNS 21 TNS 0 NUM_FEPS 0 with 13 cells processed and 800 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750160, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062460s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 4, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 750268, Over = 0
+PHY-3001 : End incremental legalization;  0.395010s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.6%)
+
+OPT-0007 : Iter 4: improved WNS 21 TNS 0 NUM_FEPS 0 with 3 cells processed and 571 slack improved
+OPT-1001 : End bottleneck based optimization;  3.925253s wall, 4.437500s user + 0.000000s system = 4.437500s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16033/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932256, over cnt = 182(0%), over = 245, worst = 5
+PHY-1002 : len = 932488, over cnt = 90(0%), over = 102, worst = 4
+PHY-1002 : len = 933096, over cnt = 43(0%), over = 46, worst = 2
+PHY-1002 : len = 933736, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 933800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.865332s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (106.5%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.78, top10 = 46.37, top15 = 44.62.
+OPT-1001 : End congestion update;  1.186710s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (105.3%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.765806s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.0%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750488, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063977s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.7%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 4, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 750544, Over = 0
+PHY-3001 : End incremental legalization;  0.397794s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.2%)
+
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 15 cells processed and 1500 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.477193s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (102.8%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.744515s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.7%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16404/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 933968, over cnt = 17(0%), over = 20, worst = 2
+PHY-1002 : len = 933984, over cnt = 5(0%), over = 6, worst = 2
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.430153s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.1%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.746601s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.5%)
+
+RUN-1001 : QoR Analysis:
+OPT-0007 :   WNS 71 TNS 0 NUM_FEPS 0
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.310345
+RUN-1001 :   Top critical paths
+RUN-1001 :       #1 path slack 71ps with logic level 1 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750544, Over = 0
+PHY-3001 : End spreading;  0.060422s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.6%)
+
+PHY-3001 : Final: Len = 750544, Over = 0
+PHY-3001 : End incremental legalization;  0.393231s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (95.4%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.745243s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.5%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16457/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.130621s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
+OPT-1001 : End congestion update;  0.445948s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.739271s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.5%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750502, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061781s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 750544, Over = 0
+PHY-3001 : End incremental legalization;  0.390925s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (123.9%)
+
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 2 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.698525s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (104.9%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16457/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.135864s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
+OPT-1001 : End congestion update;  0.479069s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.770251s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.412098s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (100.7%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.756289s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.770803s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.3%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16457/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.132917s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.0%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
+RUN-1001 : End congestion update;  0.453021s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.0%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.227344s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.6%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : End physical optimization;  27.483302s wall, 29.062500s user + 0.140625s system = 29.203125s CPU (106.3%)
+
+RUN-1003 : finish command "place" in  73.177550s wall, 102.531250s user + 6.625000s system = 109.156250s CPU (149.2%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 660 MB, peak memory is 771 MB
+RUN-1002 : start command "export_db hg_anlogic_place.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.736455s wall, 3.000000s user + 0.000000s system = 3.000000s CPU (172.8%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 661 MB, peak memory is 771 MB
+RUN-1002 : start command "route"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Route Property
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :    Parameters    |  Settings  |  Default Values  |  Note  
+RUN-1001 : -------------------------------------------------------
+RUN-1001 :      effort      |   medium   |      medium      |        
+RUN-1001 :     fix_hold     |    off     |       off        |        
+RUN-1001 :    opt_timing    |   medium   |      medium      |        
+RUN-1001 :   phy_sim_model  |    off     |       off        |        
+RUN-1001 :     priority     |   timing   |      timing      |        
+RUN-1001 :     swap_pin     |     on     |        on        |        
+RUN-1001 : -------------------------------------------------------
+PHY-1001 : Route runs in 8 thread(s)
+RUN-1001 : There are total 7142 instances
+RUN-1001 : 3487 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18189 nets
+RUN-6004 WARNING: There are 20 nets with only 1 pin.
+RUN-1001 : 10477 nets have 2 pins
+RUN-1001 : 5822 nets have [3 - 5] pins
+RUN-1001 : 1180 nets have [6 - 10] pins
+RUN-1001 : 327 nets have [11 - 20] pins
+RUN-1001 : 355 nets have [21 - 99] pins
+RUN-1001 : 8 nets have 100+ pins
+RUN-1002 : start command "start_timer -report"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76296, tnet num: 18011, tinst num: 7140, tnode num: 100004, tedge num: 127731.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -report" in  1.669688s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.2%)
+
+RUN-1004 : used memory is 644 MB, reserved memory is 632 MB, peak memory is 771 MB
+PHY-1001 : 3487 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18011 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+PHY-1001 : Start global routing, caller is route ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 860440, over cnt = 2807(7%), over = 4694, worst = 8
+PHY-1002 : len = 878304, over cnt = 1769(5%), over = 2646, worst = 7
+PHY-1002 : len = 899936, over cnt = 722(2%), over = 1043, worst = 6
+PHY-1002 : len = 914928, over cnt = 24(0%), over = 33, worst = 5
+PHY-1002 : len = 915672, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.062873s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (133.1%)
+
+PHY-1001 : Congestion index: top1 = 53.77, top5 = 48.72, top10 = 45.99, top15 = 44.26.
+PHY-1001 : End global routing;  3.394154s wall, 4.406250s user + 0.015625s system = 4.421875s CPU (130.3%)
+
+PHY-1001 : Start detail routing ...
+PHY-1001 : Current memory(MB): used = 734, reserve = 732, peak = 771.
+PHY-1001 : Detailed router is running in normal mode.
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : Current memory(MB): used = 1009, reserve = 1011, peak = 1009.
+PHY-1001 : End build detailed router design. 4.123919s wall, 4.093750s user + 0.031250s system = 4.125000s CPU (100.0%)
+
+PHY-1001 : Detail Route ...
+PHY-1001 : ===== Detail Route Phase 1 =====
+PHY-1001 : Clock net routing.....
+PHY-1001 : Routed 0% nets.
+PHY-1022 : len = 271128, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.303886s wall, 5.312500s user + 0.000000s system = 5.312500s CPU (100.2%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 271184, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.432936s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.4%)
+
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1047, peak = 1044.
+PHY-1001 : End phase 1; 5.749378s wall, 5.750000s user + 0.000000s system = 5.750000s CPU (100.0%)
+
+PHY-1001 : ===== Detail Route Phase 2 =====
+PHY-1001 : Initial routing.....
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.35174e+06, over cnt = 1913(0%), over = 1916, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1063, reserve = 1062, peak = 1063.
+PHY-1001 : End initial routed; 30.566888s wall, 61.609375s user + 0.359375s system = 61.968750s CPU (202.7%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 3/17112(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -0.821   |  -1.201   |   5   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.373019s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1071, reserve = 1069, peak = 1071.
+PHY-1001 : End phase 2; 33.939995s wall, 64.984375s user + 0.359375s system = 65.343750s CPU (192.5%)
+
+PHY-1001 : ===== Detail Route Phase 3 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 3 pins with SWNS -0.811ns STNS -0.811ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.152328s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.6%)
+
+PHY-1022 : len = 2.35176e+06, over cnt = 1914(0%), over = 1917, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.447400s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.8%)
+
+PHY-1001 : Ripup-reroute.....
+PHY-1001 : ===== DR Iter 1 =====
+PHY-1022 : len = 2.32276e+06, over cnt = 783(0%), over = 786, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.138908s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (189.3%)
+
+PHY-1001 : ===== DR Iter 2 =====
+PHY-1022 : len = 2.31824e+06, over cnt = 149(0%), over = 150, worst = 2, crit = 0
+PHY-1001 : End DR Iter 2; 0.829325s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (147.0%)
+
+PHY-1001 : ===== DR Iter 3 =====
+PHY-1022 : len = 2.31907e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.450179s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (118.0%)
+
+PHY-1001 : ===== DR Iter 4 =====
+PHY-1022 : len = 2.31944e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.278370s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (117.9%)
+
+PHY-1001 : ===== DR Iter 5 =====
+PHY-1022 : len = 2.31957e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.272769s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (114.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.299020s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.291461s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (101.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.177934s wall, 0.171875s user + 0.031250s system = 0.203125s CPU (114.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.3196e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.177859s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (131.8%)
+
+PHY-1001 : Update timing.....
+PHY-1001 : 1/17112(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -0.811   |  -0.811   |   1   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.385904s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (100.1%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 604 feed throughs used by 440 nets
+PHY-1001 : End commit to database; 2.263587s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.1%)
+
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1182, peak = 1178.
+PHY-1001 : End phase 3; 10.447954s wall, 12.000000s user + 0.078125s system = 12.078125s CPU (115.6%)
+
+PHY-1001 : ===== Detail Route Phase 4 =====
+PHY-1001 : Optimize timing.....
+PHY-1001 : ===== OPT Iter 1 =====
+PHY-1001 : Processed 1 pins with SWNS -0.811ns STNS -0.811ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.140792s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%)
+
+PHY-1022 : len = 2.3196e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.389031s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.4%)
+
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.811ns, -0.811ns, 1}
+PHY-1001 : Update timing.....
+PHY-1001 : 1/17112(0%) critical/total net(s).
+RUN-1001 : --------------------------------------
+RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
+RUN-1001 : --------------------------------------
+RUN-1001 :   Setup  |  -0.811   |  -0.811   |   1   
+RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
+RUN-1001 : --------------------------------------
+PHY-1001 : End update timing; 3.348725s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.9%)
+
+PHY-1001 : Commit to database.....
+PHY-1001 : 604 feed throughs used by 440 nets
+PHY-1001 : End commit to database; 2.386680s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (100.2%)
+
+PHY-1001 : Current memory(MB): used = 1188, reserve = 1191, peak = 1188.
+PHY-1001 : End phase 4; 6.151776s wall, 6.140625s user + 0.000000s system = 6.140625s CPU (99.8%)
+
+PHY-1003 : Routed, final wirelength = 2.3196e+06
+PHY-1001 : Current memory(MB): used = 1189, reserve = 1193, peak = 1189.
+PHY-1001 : End export database. 0.062610s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
+
+PHY-1001 : End detail routing;  60.875243s wall, 93.437500s user + 0.468750s system = 93.906250s CPU (154.3%)
+
+RUN-1003 : finish command "route" in  67.053396s wall, 100.609375s user + 0.484375s system = 101.093750s CPU (150.8%)
+
+RUN-1004 : used memory is 1116 MB, reserved memory is 1113 MB, peak memory is 1189 MB
+RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Utilization Statistics
+#lut                    10421   out of  19600   53.17%
+#reg                     9955   out of  19600   50.79%
+#le                     13076
+  #lut only              3121   out of  13076   23.87%
+  #reg only              2655   out of  13076   20.30%
+  #lut&reg               7300   out of  13076   55.83%
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+#gclk                       6   out of     16   37.50%
+
+Clock Resource Statistics
+Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1825
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1432
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1342
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               1235
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    140
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
+#8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
+#9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             u_mipi_eot_min/reg1_syn_299.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_163.f0    3
+#12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
+#13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
+#14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
+#15       u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d             GCLK               pll                u_pll/pll_inst.clkc3                               1
+
+
+Detailed IO Report
+
+         Name            Direction    Location    IOStandard    DriveStrength    PullType    PackReg  
+       a_ad_sdi            INPUT        P51        LVCMOS33          N/A          PULLUP      NONE    
+     a_lvds_clk_p          INPUT        P31         LVDS25           N/A           NONE      IDDRX1   
+    a_lvds_clk_p(n)        INPUT        P30         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[4]        INPUT        P42         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[4](n)      INPUT        P41         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[3]        INPUT        P37         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[3](n)      INPUT        P36         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[2]        INPUT        P28         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[2](n)      INPUT        P29         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[1]        INPUT        P26         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[1](n)      INPUT        P27         LVDS25           N/A           NONE      IDDRX1   
+   a_lvds_data_p[0]        INPUT        P22         LVDS25           N/A           NONE      IDDRX1   
+  a_lvds_data_p[0](n)      INPUT        P23         LVDS25           N/A           NONE      IDDRX1   
+       b_ad_sdi            INPUT        P56        LVCMOS33          N/A          PULLUP      NONE    
+     b_lvds_clk_p          INPUT        P130        LVDS25           N/A           NONE      IDDRX1   
+    b_lvds_clk_p(n)        INPUT        P129        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[4]        INPUT        P103        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[4](n)      INPUT        P102        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[3]        INPUT        P131        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[3](n)      INPUT        P132        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[2]        INPUT        P126        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[2](n)      INPUT        P127        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[1]        INPUT        P124        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[1](n)      INPUT        P123        LVDS25           N/A           NONE      IDDRX1   
+   b_lvds_data_p[0]        INPUT        P121        LVDS25           N/A           NONE      IDDRX1   
+  b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
+     clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
+    global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
+       onoff_in            INPUT        P141       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
+        rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
+      O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
+     O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
+      O_clk_lp_n          OUTPUT        P73        LVCMOS25           8            NONE       NONE    
+      O_clk_lp_p          OUTPUT        P74        LVCMOS25           8            NONE       OREG    
+    O_data_hs_p[3]        OUTPUT        P100        LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[3](n)      OUTPUT        P101        LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[2]        OUTPUT        P97         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[2](n)      OUTPUT        P95         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[1]        OUTPUT        P93         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[1](n)      OUTPUT        P94         LVDS25           NA            NONE      ODDRX2   
+    O_data_hs_p[0]        OUTPUT        P90         LVDS25           NA            NONE      ODDRX2   
+   O_data_hs_p[0](n)      OUTPUT        P89         LVDS25           NA            NONE      ODDRX2   
+    O_data_lp_n[3]        OUTPUT        P81        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[2]        OUTPUT        P77        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[1]        OUTPUT        P75        LVCMOS25           8            NONE       NONE    
+    O_data_lp_n[0]        OUTPUT        P62        LVCMOS25           8            NONE       NONE    
+    O_data_lp_p[3]        OUTPUT        P79        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[2]        OUTPUT        P78        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[1]        OUTPUT        P76        LVCMOS25           8            NONE       OREG    
+    O_data_lp_p[0]        OUTPUT        P63        LVCMOS25           8            NONE       OREG    
+       a_ad_sck           OUTPUT        P52        LVCMOS33           8            NONE       NONE    
+       a_ad_sdo           OUTPUT        P50        LVCMOS33           8            NONE       NONE    
+       a_ad_sen           OUTPUT        P53        LVCMOS33           8            NONE       NONE    
+       a_sp_pad           OUTPUT        P49        LVCMOS33           8            N/A        OREG    
+     a_sp_sampling        OUTPUT        P25        LVCMOS25           8            N/A        OREG    
+       b_ad_sck           OUTPUT        P57        LVCMOS33           8            NONE       NONE    
+       b_ad_sdo           OUTPUT        P55        LVCMOS33           8            NONE       NONE    
+       b_ad_sen           OUTPUT        P58        LVCMOS33           8            NONE       NONE    
+       b_sp_pad           OUTPUT        P54        LVCMOS33           8            NONE       OREG    
+       debug[7]           OUTPUT        P161       LVCMOS33           8            NONE       OREG    
+       debug[6]           OUTPUT        P159       LVCMOS33           8            NONE       NONE    
+       debug[5]           OUTPUT        P158       LVCMOS33           8            NONE       OREG    
+       debug[4]           OUTPUT        P157       LVCMOS33           8            NONE       OREG    
+       debug[3]           OUTPUT        P155       LVCMOS33           8            NONE       OREG    
+       debug[2]           OUTPUT        P153       LVCMOS33           8            NONE       NONE    
+       debug[1]           OUTPUT        P61        LVCMOS33           8            NONE       NONE    
+       debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
+        fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
+    frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
+       onoff_out          OUTPUT        P111       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P106       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P71        LVCMOS25           8            N/A        NONE    
+        txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
+
+Report Hierarchy Area:
++---------------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
++---------------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |13076  |9394    |1027    |9987    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |544    |438     |23      |443     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |80      |4       |87      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |35     |35      |0       |24      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |779    |386     |96      |580     |0       |0       |
+|    u_ADconfig                |AD_config            |204    |138     |25      |151     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |160     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |739    |378     |96      |562     |0       |0       |
+|    u_ADconfig                |AD_config            |167    |122     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |255    |147     |71      |120     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3214   |2625    |306     |2077    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |184    |145     |17      |136     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2998   |2468    |289     |1909    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |4       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |0       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2596   |2148    |253     |1582    |22      |0       |
+|        channelPart           |channel_part_8478    |160    |155     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |39      |0       |0       |
+|        ram_switch            |ram_switch           |2024   |1637    |197     |1169    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |255    |227     |27      |113     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |10      |0       |0       |
+|          insert              |insert               |987    |628     |170     |682     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |782    |782     |0       |374     |0       |0       |
+|        read_ram_i            |read_ram             |313    |266     |44      |209     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |251    |211     |40      |166     |0       |0       |
+|          read_ram_data       |read_ram_data        |57     |51      |4       |38      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |326    |252     |36      |271     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1      |0       |0       |1       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3165   |2462    |349     |2109    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |187    |105     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2946   |2342    |332     |1929    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |5       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |5       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2485   |1993    |290     |1576    |22      |1       |
+|        channelPart           |channel_part_8478    |275    |272     |3       |151     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |1756   |1391    |197     |1140    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |198    |169     |27      |122     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |8       |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |18      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |18      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|          insert              |insert               |1012   |680     |170     |674     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |546    |542     |0       |344     |0       |0       |
+|        read_ram_i            |read_ram_rev         |363    |258     |81      |213     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |298    |218     |73      |166     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |40      |8       |47      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|......                        |......               |-      |-       |-       |-       |-       |-       |
++---------------------------------------------------------------------------------------------------------+
+
+
+DataNet Average Fanout:
+
+   Index     Fanout    Nets   
+    #1         1       10415  
+    #2         2       3902   
+    #3         3       1365   
+    #4         4        552   
+    #5        5-10     1241   
+    #6       11-50      592   
+    #7       51-100     26    
+    #8        >500       1    
+  Average     2.89            
+
+RUN-1002 : start command "export_db hg_anlogic_pr.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.122784s wall, 3.656250s user + 0.000000s system = 3.656250s CPU (172.2%)
+
+RUN-1004 : used memory is 1117 MB, reserved memory is 1115 MB, peak memory is 1189 MB
+RUN-1002 : start command "start_timer"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76296, tnet num: 18011, tinst num: 7140, tnode num: 100004, tedge num: 127731.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer" in  1.647971s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.6%)
+
+RUN-1004 : used memory is 1123 MB, reserved memory is 1121 MB, peak memory is 1189 MB
+RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
+TMR-2503 : Start to update net delay, extr mode = 6.
+TMR-2504 : Update delay of 18011 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 6.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+TMR-3506 : Start to generate timing report.
+TMR-1502 : Number of clock constraints = 12. Number of clock nets = 15 (3 unconstrainted).
+TMR-5009 WARNING: No clock constraint on 3 clock net(s): 
+		exdev_ctl_a/u_ADconfig/clk_config_syn_4
+		exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2
+		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
+TMR-3508 : Export timing summary.
+TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.560815s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.1%)
+
+RUN-1004 : used memory is 1126 MB, reserved memory is 1123 MB, peak memory is 1189 MB
+RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
+PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
+RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
+BIT-1003 : Start to generate bitstream. 
+BIT-1002 : Init instances with 8 threads.
+BIT-1002 : Init instances completely, inst num: 7140
+BIT-1002 : Init pips with 8 threads.
+BIT-1002 : Init pips completely, net num: 18189, pip num: 175850
+BIT-1002 : Init feedthrough with 8 threads.
+BIT-1002 : Init feedthrough completely, num: 604
+BIT-1003 : Multithreading accelaration with 8 threads.
+BIT-1003 : Generate bitstream completely, there are 3263 valid insts, and 489276 bits set as '1'.
+BIT-1004 : the usercode register value: 00000000101110110000000000000000
+BIT-1004 : PLL setting string = 1011
+BIT-1004 : Generate bits file hg_anlogic.bit.
+BIT-1004 : Generate bin file hg_anlogic.bin.
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.457605s wall, 62.250000s user + 0.156250s system = 62.406250s CPU (659.9%)
+
+RUN-1004 : used memory is 1297 MB, reserved memory is 1293 MB, peak memory is 1412 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_145210.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_094510.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_094510.log
new file mode 100644
index 0000000..4017540
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_094510.log
@@ -0,0 +1,1874 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 09:45:10 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.048157s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (99.9%)
+
+RUN-1004 : used memory is 192 MB, reserved memory is 171 MB, peak memory is 232 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.288994s wall, 15.953125s user + 2.343750s system = 18.296875s CPU (100.0%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 303 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.051678s wall, 1.687500s user + 0.015625s system = 1.703125s CPU (161.9%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 314 MB, peak memory is 398 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.250305s wall, 1.203125s user + 0.046875s system = 1.250000s CPU (100.0%)
+
+RUN-1004 : used memory is 516 MB, reserved memory is 496 MB, peak memory is 516 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.821286s wall, 53.390625s user + 0.390625s system = 53.781250s CPU (99.9%)
+
+RUN-1004 : used memory is 393 MB, reserved memory is 386 MB, peak memory is 698 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.555094s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (172.8%)
+
+RUN-1004 : used memory is 401 MB, reserved memory is 383 MB, peak memory is 698 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_094510.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_101229.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_101229.log
new file mode 100644
index 0000000..a3716ff
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_101229.log
@@ -0,0 +1,1874 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:12:29 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.027499s wall, 0.984375s user + 0.046875s system = 1.031250s CPU (100.4%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 172 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.265399s wall, 15.843750s user + 2.421875s system = 18.265625s CPU (100.0%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 348 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.048593s wall, 1.671875s user + 0.031250s system = 1.703125s CPU (162.4%)
+
+RUN-1004 : used memory is 326 MB, reserved memory is 299 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.251879s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (101.1%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.105318s wall, 52.828125s user + 0.281250s system = 53.109375s CPU (100.0%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 385 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.550248s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (174.4%)
+
+RUN-1004 : used memory is 402 MB, reserved memory is 387 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_101229.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_102146.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_102146.log
new file mode 100644
index 0000000..ebcc6df
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_102146.log
@@ -0,0 +1,1872 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:21:46 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.049398s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (99.8%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 173 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.506805s wall, 16.406250s user + 2.078125s system = 18.484375s CPU (99.9%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 304 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.041830s wall, 1.656250s user + 0.046875s system = 1.703125s CPU (163.5%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 314 MB, peak memory is 400 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.290364s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (100.5%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 497 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  55.008036s wall, 54.734375s user + 0.234375s system = 54.968750s CPU (99.9%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 390 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.565431s wall, 2.734375s user + 0.000000s system = 2.734375s CPU (174.7%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 388 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_102146.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_102609.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_102609.log
new file mode 100644
index 0000000..2e5e92e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_102609.log
@@ -0,0 +1,1870 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:26:09 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.037470s wall, 0.968750s user + 0.062500s system = 1.031250s CPU (99.4%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 175 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.723631s wall, 16.093750s user + 1.625000s system = 17.718750s CPU (100.0%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 302 MB, peak memory is 348 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.048575s wall, 1.671875s user + 0.031250s system = 1.703125s CPU (162.4%)
+
+RUN-1004 : used memory is 326 MB, reserved memory is 301 MB, peak memory is 398 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.296667s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (100.0%)
+
+RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.17 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.356668s wall, 53.031250s user + 0.312500s system = 53.343750s CPU (100.0%)
+
+RUN-1004 : used memory is 393 MB, reserved memory is 377 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.530592s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (173.5%)
+
+RUN-1004 : used memory is 428 MB, reserved memory is 416 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_102609.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_103136.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_103136.log
new file mode 100644
index 0000000..641cf89
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_103136.log
@@ -0,0 +1,1875 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:31:36 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.047305s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (100.0%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.257289s wall, 15.968750s user + 2.296875s system = 18.265625s CPU (100.0%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 348 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.060217s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (162.1%)
+
+RUN-1004 : used memory is 325 MB, reserved memory is 298 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.275760s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (100.4%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 496 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.740811s wall, 53.421875s user + 0.312500s system = 53.734375s CPU (100.0%)
+
+RUN-1004 : used memory is 393 MB, reserved memory is 376 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.553136s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (173.0%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 383 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_103136.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_103748.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_103748.log
new file mode 100644
index 0000000..35112a8
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_103748.log
@@ -0,0 +1,1876 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:37:48 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.028857s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (100.2%)
+
+RUN-1004 : used memory is 194 MB, reserved memory is 171 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.149595s wall, 16.109375s user + 2.031250s system = 18.140625s CPU (100.0%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 302 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.040361s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (162.2%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 313 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.270679s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (99.6%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 496 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.19 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.532839s wall, 53.343750s user + 0.187500s system = 53.531250s CPU (100.0%)
+
+RUN-1004 : used memory is 394 MB, reserved memory is 380 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.553449s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (173.0%)
+
+RUN-1004 : used memory is 431 MB, reserved memory is 419 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_103748.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_104529.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_104529.log
new file mode 100644
index 0000000..7b03a28
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_104529.log
@@ -0,0 +1,1875 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:45:29 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.032941s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (99.8%)
+
+RUN-1004 : used memory is 194 MB, reserved memory is 172 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.255782s wall, 15.765625s user + 2.437500s system = 18.203125s CPU (99.7%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.061195s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (162.0%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 312 MB, peak memory is 400 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.275384s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (100.5%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 496 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.17 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.536052s wall, 53.250000s user + 0.281250s system = 53.531250s CPU (100.0%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 392 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.541671s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (172.3%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 386 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_104529.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_105536.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_105536.log
new file mode 100644
index 0000000..67a1313
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_105536.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:55:36 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.052908s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (100.9%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 172 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort_rev/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.739348s wall, 16.281250s user + 1.437500s system = 17.718750s CPU (99.9%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 302 MB, peak memory is 351 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.033773s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (164.7%)
+
+RUN-1004 : used memory is 339 MB, reserved memory is 311 MB, peak memory is 400 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.276280s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (100.4%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  55.884700s wall, 55.531250s user + 0.312500s system = 55.843750s CPU (99.9%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 383 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.534556s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (174.1%)
+
+RUN-1004 : used memory is 431 MB, reserved memory is 422 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_105536.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_105746.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_105746.log
new file mode 100644
index 0000000..80b8308
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_105746.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 10:57:46 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.064522s wall, 0.984375s user + 0.078125s system = 1.062500s CPU (99.8%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 173 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.210796s wall, 16.187500s user + 2.031250s system = 18.218750s CPU (100.0%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.097425s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (153.8%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 313 MB, peak memory is 400 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.249828s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (100.0%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 496 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.17 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  52.308563s wall, 51.781250s user + 0.515625s system = 52.296875s CPU (100.0%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 392 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.540655s wall, 2.640625s user + 0.031250s system = 2.671875s CPU (173.4%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 386 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_105746.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_110004.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_110004.log
new file mode 100644
index 0000000..5169f17
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_110004.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 11:00:04 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.038479s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (99.3%)
+
+RUN-1004 : used memory is 194 MB, reserved memory is 173 MB, peak memory is 234 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 25 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.334428s wall, 16.328125s user + 2.000000s system = 18.328125s CPU (100.0%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 302 MB, peak memory is 349 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.032121s wall, 1.671875s user + 0.000000s system = 1.671875s CPU (162.0%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 313 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.255275s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (99.6%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 496 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.17 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  54.202447s wall, 53.953125s user + 0.250000s system = 54.203125s CPU (100.0%)
+
+RUN-1004 : used memory is 393 MB, reserved memory is 378 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.534192s wall, 2.671875s user + 0.015625s system = 2.687500s CPU (175.2%)
+
+RUN-1004 : used memory is 429 MB, reserved memory is 419 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_110004.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_110222.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_110222.log
new file mode 100644
index 0000000..02996b1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_110222.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 11:02:22 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.035461s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (101.1%)
+
+RUN-1004 : used memory is 193 MB, reserved memory is 170 MB, peak memory is 233 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.026788s wall, 16.281250s user + 1.750000s system = 18.031250s CPU (100.0%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 301 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.032340s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (163.5%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 313 MB, peak memory is 398 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.244841s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (100.4%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.19 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  51.835419s wall, 51.453125s user + 0.375000s system = 51.828125s CPU (100.0%)
+
+RUN-1004 : used memory is 394 MB, reserved memory is 378 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.535780s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (174.0%)
+
+RUN-1004 : used memory is 431 MB, reserved memory is 417 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_110222.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_134651.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_134651.log
new file mode 100644
index 0000000..fccc5d4
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_134651.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 13:46:51 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.051133s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (99.6%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 173 MB, peak memory is 237 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53909/20307 useful/useless nets, 20692/1850 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.827919s wall, 16.015625s user + 1.781250s system = 17.796875s CPU (99.8%)
+
+RUN-1004 : used memory is 332 MB, reserved memory is 304 MB, peak memory is 351 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.117525s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (156.6%)
+
+RUN-1004 : used memory is 342 MB, reserved memory is 314 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.256357s wall, 1.265625s user + 0.000000s system = 1.265625s CPU (100.7%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 496 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7488 (3.87), #lev = 9 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7368 (3.96), #lev = 7 (3.03)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7396 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9971
+  #lut4                  5255
+  #lut5                  2161
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9971   out of  19600   50.87%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7416    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |272     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |89      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2321    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1910    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1482    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1088    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |167     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |26      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |207     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |180     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |27      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.790190s wall, 53.343750s user + 0.421875s system = 53.765625s CPU (100.0%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 387 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.560471s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (175.2%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 387 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_134651.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_135035.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_135035.log
new file mode 100644
index 0000000..083a6c1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_135035.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 13:50:35 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.084763s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (100.8%)
+
+RUN-1004 : used memory is 196 MB, reserved memory is 174 MB, peak memory is 237 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55227/19208 useful/useless nets, 20716/1826 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 43758/8976 useful/useless nets, 10998/4743 useful/useless insts
+SYN-1016 : Merged 1877 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41427/367 useful/useless nets, 38624/563 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 31194 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26432/1547 useful/useless nets, 23721/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 26183/80 useful/useless nets, 23504/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 26090/93 useful/useless nets, 23422/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25812/20 useful/useless nets, 23160/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.924546s wall, 16.718750s user + 2.203125s system = 18.921875s CPU (100.0%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 309 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14607
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9750
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9756   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2576   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |2394   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |2048   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.066359s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (162.6%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 306 MB, peak memory is 407 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25846/24 useful/useless nets, 23209/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26164/670 useful/useless nets, 23543/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29600/338 useful/useless nets, 26980/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 37144/296 useful/useless nets, 34418/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 124313, tnet num: 37146, tinst num: 34418, tnode num: 160248, tedge num: 183092.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.278431s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (100.2%)
+
+RUN-1004 : used memory is 527 MB, reserved memory is 505 MB, peak memory is 527 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 37146 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7488 (3.87), #lev = 9 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7368 (3.96), #lev = 7 (3.03)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7396 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9971
+  #lut4                  5255
+  #lut5                  2161
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9971   out of  19600   50.87%
+#reg                     9830   out of  19600   50.15%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7416    |2555    |9862    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |272     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |89      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2321    |738     |2576    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |2394    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1910    |615     |2048    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1482    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1088    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |167     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |26      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |207     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |180     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |27      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9830 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  56.156174s wall, 55.812500s user + 0.343750s system = 56.156250s CPU (100.0%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 398 MB, peak memory is 712 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.586515s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (173.3%)
+
+RUN-1004 : used memory is 411 MB, reserved memory is 390 MB, peak memory is 712 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_135035.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_135933.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_135933.log
new file mode 100644
index 0000000..cce3bf4
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_135933.log
@@ -0,0 +1,1901 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 13:59:33 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(340)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(360)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.075741s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (100.2%)
+
+RUN-1004 : used memory is 196 MB, reserved memory is 177 MB, peak memory is 237 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55431/19160 useful/useless nets, 20746/1817 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38312 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 43962/8977 useful/useless nets, 11028/4744 useful/useless insts
+SYN-1016 : Merged 1883 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41626/367 useful/useless nets, 38823/563 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4017 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6454 instances.
+SYN-1015 : Optimize round 1, 31590 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26499/1547 useful/useless nets, 23788/7649 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9493 better
+SYN-1032 : 26250/80 useful/useless nets, 23571/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 26157/93 useful/useless nets, 23489/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25879/20 useful/useless nets, 23227/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.817463s wall, 17.046875s user + 1.781250s system = 18.828125s CPU (100.1%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 309 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14673
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9816
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 226
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9822   |800    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2642   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |2460   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |2048   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.119468s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (156.3%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 319 MB, peak memory is 406 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25913/24 useful/useless nets, 23276/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26231/670 useful/useless nets, 23610/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29676/338 useful/useless nets, 27056/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 37220/296 useful/useless nets, 34494/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 124605, tnet num: 37222, tinst num: 34494, tnode num: 160737, tedge num: 183524.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.293125s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (100.3%)
+
+RUN-1004 : used memory is 529 MB, reserved memory is 506 MB, peak memory is 529 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 37222 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 9 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7367 (3.97), #lev = 7 (3.04)
+SYN-3001 : Logic optimization runtime opt =   1.23 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18926 instances into 7395 LUTs, name keeping = 57%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9970
+  #lut4                  5245
+  #lut5                  2170
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9970   out of  19600   50.87%
+#reg                     9896   out of  19600   50.49%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7415    |2555    |9928    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |338     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |285     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |278     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2330    |738     |2642    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2258    |691     |2460    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1917    |615     |2048    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |201     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |170     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2347    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2277    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1936    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |147     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |216     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |34      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9896 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 7 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  55.997620s wall, 55.546875s user + 0.437500s system = 55.984375s CPU (100.0%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 395 MB, peak memory is 715 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.576917s wall, 2.750000s user + 0.000000s system = 2.750000s CPU (174.4%)
+
+RUN-1004 : used memory is 412 MB, reserved memory is 394 MB, peak memory is 715 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_135933.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_140650.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_140650.log
new file mode 100644
index 0000000..94f14d5
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_140650.log
@@ -0,0 +1,1925 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:06:50 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(340)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(360)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(371)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(391)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.095446s wall, 1.031250s user + 0.062500s system = 1.093750s CPU (99.8%)
+
+RUN-1004 : used memory is 198 MB, reserved memory is 178 MB, peak memory is 239 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 56957/19111 useful/useless nets, 20800/1808 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 45488/8978 useful/useless nets, 11082/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 43151/363 useful/useless nets, 40348/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 33312 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 27229/1547 useful/useless nets, 24518/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 26980/80 useful/useless nets, 24301/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 26887/93 useful/useless nets, 24219/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 26609/20 useful/useless nets, 23957/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.115719s wall, 17.421875s user + 1.703125s system = 19.125000s CPU (100.0%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 315 MB, peak memory is 361 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            15402
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                  10545
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |10551  |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2645   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |2463   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |2051   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2662   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |2480   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |2068   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.090984s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (161.8%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 310 MB, peak memory is 413 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 26643/24 useful/useless nets, 24006/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26961/670 useful/useless nets, 24340/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 30415/338 useful/useless nets, 27795/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 37959/296 useful/useless nets, 35233/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 127549, tnet num: 37961, tinst num: 35233, tnode num: 165867, tedge num: 187934.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.340546s wall, 1.328125s user + 0.015625s system = 1.343750s CPU (100.2%)
+
+RUN-1004 : used memory is 538 MB, reserved memory is 516 MB, peak memory is 538 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 37961 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7494 (3.86), #lev = 10 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7339 (3.98), #lev = 7 (3.04)
+SYN-3001 : Logic optimization runtime opt =   1.16 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7367 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9942
+  #lut4                  5169
+  #lut5                  2218
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9942   out of  19600   50.72%
+#reg                    10625   out of  19600   54.21%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7387    |2555    |10657   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |338     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |90      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2340    |738     |2645    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2268    |691     |2463    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1929    |615     |2051    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |212     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |176     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |35      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2341    |751     |2662    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2269    |704     |2480    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1926    |628     |2068    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |212     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |184     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 10625 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  59.957798s wall, 59.562500s user + 0.343750s system = 59.906250s CPU (99.9%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 387 MB, peak memory is 727 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.620996s wall, 2.796875s user + 0.031250s system = 2.828125s CPU (174.5%)
+
+RUN-1004 : used memory is 418 MB, reserved memory is 399 MB, peak memory is 727 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_140650.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_141624.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_141624.log
new file mode 100644
index 0000000..57e68d4
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_141624.log
@@ -0,0 +1,2560 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:16:24 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(340)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: net 'RD_addr_i_sync_d3[109]' does not have a driver in ../../../../hg_mp/fe/prebuffer.v(283)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(360)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(371)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: net 'RD_addr_i_sync_d3[109]' does not have a driver in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(391)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.109239s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (100.0%)
+
+RUN-1004 : used memory is 198 MB, reserved memory is 177 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55044/21708 useful/useless nets, 20145/2475 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 37296 instances.
+SYN-1025 : Merged 21 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 44007/8366 useful/useless nets, 10876/4566 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(288) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[109]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[108]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[107]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[106]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[105]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[104]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[103]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[102]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[101]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[100]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[99]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[98]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[97]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[96]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[95]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[94]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[93]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[92]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[91]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[90]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[89]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[88]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[87]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[86]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[85]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[84]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[83]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[82]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[81]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[80]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[79]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[78]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[77]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[76]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[75]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[74]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[73]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[72]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[71]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[70]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[69]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[68]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[67]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[66]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[65]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[64]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[63]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[62]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[61]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[60]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[59]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[58]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[57]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[56]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[55]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[54]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[53]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[52]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[51]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[50]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[49]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[48]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[47]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[46]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[45]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[44]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[43]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[42]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[41]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[40]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[39]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[38]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[37]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[36]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[35]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[34]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[33]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[32]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[31]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[30]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[29]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[28]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[27]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[26]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[25]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[24]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[23]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[22]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[21]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[20]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[19]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[18]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[17]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[16]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[15]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[14]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[13]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[12]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[11]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[10]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[9]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[8]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[7]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[6]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[5]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[4]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[3]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[2]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[1]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/RD_addr_i_sync_d3[0]" in ../../../../hg_mp/fe/prebuffer.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[109]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[108]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[107]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[106]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[105]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[104]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[103]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[102]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[101]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[100]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[99]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[98]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[97]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[96]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[95]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[94]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[93]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[92]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[91]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[90]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[89]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[88]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[87]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[86]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[85]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[84]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[83]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[82]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[81]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[80]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[79]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[78]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[77]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[76]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[75]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[74]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[73]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[72]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[71]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[70]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[69]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[68]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[67]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[66]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[65]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[64]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[63]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[62]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[61]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[60]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[59]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[58]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[57]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[56]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[55]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[54]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[53]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[52]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[51]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[50]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[49]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[48]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[47]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[46]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[45]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[44]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[43]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[42]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[41]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[40]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[39]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[38]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[37]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[36]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[35]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[34]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[33]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[32]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[31]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[30]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[29]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[28]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[27]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[26]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[25]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[24]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[23]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[22]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[21]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[20]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[19]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[18]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[17]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[16]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[15]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[14]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[13]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[12]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[11]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[10]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[9]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[9]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[8]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[8]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[7]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[7]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[6]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[6]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[5]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[5]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[4]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[4]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[3]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[3]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[2]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[2]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[1]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[1]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/RD_addr_i_sync_d3[0]" in ../../../../hg_mp/fe/prebuffer_rev.v(283)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5014 WARNING: the net's pin: pin "addrb[0]" in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(61)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41460/359 useful/useless nets, 38900/549 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4009 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6564 instances.
+SYN-1015 : Optimize round 1, 32218 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26072/1536 useful/useless nets, 23604/7418 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9251 better
+SYN-1032 : 25823/80 useful/useless nets, 23387/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25730/93 useful/useless nets, 23305/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 49 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25680/20 useful/useless nets, 23271/0 useful/useless insts
+SYN-1015 : Optimize round 2, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.283542s wall, 15.281250s user + 1.984375s system = 17.265625s CPU (99.9%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 310 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            15031
+  #and                   2416
+  #nand                     0
+  #or                    1052
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    450
+  #bufif1                   5
+  #MX21                   607
+  #FADD                     0
+  #DFF                  10291
+  #LATCH                    6
+#MACRO_ADD                466
+#MACRO_EQ                 217
+#MACRO_MULT                 4
+#MACRO_MUX               4539
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4734   |10297  |760    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1783   |2524   |250    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1739   |2342   |239    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1484   |1930   |99     |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |57     |37     |12     |
+|          read_ram_data       |read_ram_data        |55     |32     |12     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1754   |2529   |248    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1712   |2347   |238    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1458   |1935   |99     |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |37     |42     |12     |
+|          read_ram_data       |read_ram_data_rev    |37     |42     |12     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.081922s wall, 1.750000s user + 0.031250s system = 1.781250s CPU (164.6%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 306 MB, peak memory is 408 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25714/24 useful/useless nets, 23320/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26032/670 useful/useless nets, 23654/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 304 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29396/338 useful/useless nets, 27019/38 useful/useless insts
+SYN-1016 : Merged 389 instances.
+SYN-2501 : Optimize round 1, 1722 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 467 macro adder
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12074 instances.
+SYN-1032 : 36679/290 useful/useless nets, 34196/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 123305, tnet num: 36681, tinst num: 34196, tnode num: 160630, tedge num: 181504.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.304823s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (100.6%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 506 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36681 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7204 (3.91), #lev = 9 (3.18)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7114 (4.01), #lev = 7 (3.09)
+SYN-3001 : Logic optimization runtime opt =   1.21 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18452 instances into 7142 LUTs, name keeping = 56%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9418
+  #lut4                  5036
+  #lut5                  2104
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2278
+
+Utilization Statistics
+#lut                     9418   out of  19600   48.05%
+#reg                    10371   out of  19600   52.91%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7140    |2278    |10403   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |9       |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |101     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2169    |606     |2524    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2097    |559     |2342    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1756    |483     |1930    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |40      |26      |37      |0       |0       |
+|          read_ram_data       |read_ram_data        |39      |26      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2175    |606     |2529    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2103    |559     |2347    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1764    |483     |1935    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |49      |26      |42      |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |49      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 10371 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 71 carry chain into lslice
+SYN-4007 : Packing 1135 adder to BLE ...
+SYN-4008 : Packed 1135 adder and 106 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  57.695739s wall, 57.171875s user + 0.500000s system = 57.671875s CPU (100.0%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 390 MB, peak memory is 713 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.585901s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (172.4%)
+
+RUN-1004 : used memory is 441 MB, reserved memory is 428 MB, peak memory is 713 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_141624.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_142816.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_142816.log
new file mode 100644
index 0000000..ea83a43
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_142816.log
@@ -0,0 +1,1925 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:28:16 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(340)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(360)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(371)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(391)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.084319s wall, 1.000000s user + 0.078125s system = 1.078125s CPU (99.4%)
+
+RUN-1004 : used memory is 194 MB, reserved memory is 172 MB, peak memory is 235 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54317/19111 useful/useless nets, 20752/1808 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42848/8978 useful/useless nets, 11034/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40511/363 useful/useless nets, 37708/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 30672 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25909/1547 useful/useless nets, 23198/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 25660/80 useful/useless nets, 22981/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25567/93 useful/useless nets, 22899/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25289/20 useful/useless nets, 22637/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.382524s wall, 16.500000s user + 1.875000s system = 18.375000s CPU (100.0%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 306 MB, peak memory is 351 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14082
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9225
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9231   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1985   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1803   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.047619s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (162.6%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 314 MB, peak memory is 401 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25323/24 useful/useless nets, 22686/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25641/670 useful/useless nets, 23020/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29095/338 useful/useless nets, 26475/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36639/296 useful/useless nets, 33913/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122269, tnet num: 36641, tinst num: 33913, tnode num: 156627, tedge num: 180014.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.328874s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (99.9%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 498 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7501 (3.86), #lev = 10 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7384 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.16 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7412 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9987
+  #lut4                  5287
+  #lut5                  2145
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9987   out of  19600   50.95%
+#reg                     9305   out of  19600   47.47%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7432    |2555    |9337    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |344     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |285     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |276     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |93      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2331    |738     |1985    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2259    |691     |1803    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1916    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1478    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1084    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |204     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |172     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |31      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2337    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9305 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  55.879656s wall, 55.421875s user + 0.437500s system = 55.859375s CPU (100.0%)
+
+RUN-1004 : used memory is 398 MB, reserved memory is 384 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.554334s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (173.9%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 389 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_142816.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_143540.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_143540.log
new file mode 100644
index 0000000..1fdb024
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_143540.log
@@ -0,0 +1,1925 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:35:40 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(340)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(360)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(371)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(391)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.038775s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (99.3%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 174 MB, peak memory is 235 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54312/19116 useful/useless nets, 20747/1813 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42848/8978 useful/useless nets, 11034/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40511/363 useful/useless nets, 37708/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 30672 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25909/1547 useful/useless nets, 23198/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 25660/80 useful/useless nets, 22981/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25567/93 useful/useless nets, 22899/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25289/20 useful/useless nets, 22637/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.251610s wall, 16.125000s user + 2.125000s system = 18.250000s CPU (100.0%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 305 MB, peak memory is 350 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14082
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9225
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9231   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1985   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1803   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.077606s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (160.9%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 316 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25323/24 useful/useless nets, 22686/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25641/670 useful/useless nets, 23020/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29095/338 useful/useless nets, 26475/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36639/296 useful/useless nets, 33913/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122265, tnet num: 36641, tinst num: 33913, tnode num: 156617, tedge num: 180006.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.255468s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (99.6%)
+
+RUN-1004 : used memory is 522 MB, reserved memory is 499 MB, peak memory is 522 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7479 (3.86), #lev = 9 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7369 (3.96), #lev = 8 (3.08)
+SYN-3001 : Logic optimization runtime opt =   1.16 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7397 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9972
+  #lut4                  5277
+  #lut5                  2140
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9972   out of  19600   50.88%
+#reg                     9305   out of  19600   47.47%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7417    |2555    |9335    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |286     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |276     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |90      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1985    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2245    |691     |1803    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1904    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1478    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1084    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |193     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |31      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2342    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2270    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1931    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |216     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |186     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |30      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9305 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  56.628132s wall, 56.203125s user + 0.375000s system = 56.578125s CPU (99.9%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 384 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.559870s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (173.3%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 389 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_143540.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_144324.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_144324.log
new file mode 100644
index 0000000..17b79a4
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_144324.log
@@ -0,0 +1,1925 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:43:24 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(295)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(423)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(340)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(369)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(360)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(371)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(401)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(391)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.224353s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (86.8%)
+
+RUN-1004 : used memory is 196 MB, reserved memory is 174 MB, peak memory is 238 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55632/19116 useful/useless nets, 20771/1813 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 44168/8978 useful/useless nets, 11058/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41831/363 useful/useless nets, 39028/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 31992 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26569/1547 useful/useless nets, 23858/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 26320/80 useful/useless nets, 23641/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 26227/93 useful/useless nets, 23559/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25949/20 useful/useless nets, 23297/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.771483s wall, 16.359375s user + 2.421875s system = 18.781250s CPU (100.1%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 309 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14742
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9885
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9891   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2645   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |2463   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |2051   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.123901s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (155.7%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 308 MB, peak memory is 408 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25983/24 useful/useless nets, 23346/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26301/670 useful/useless nets, 23680/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29755/338 useful/useless nets, 27135/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 37299/296 useful/useless nets, 34573/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 124905, tnet num: 37301, tinst num: 34573, tnode num: 161237, tedge num: 183966.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.265505s wall, 1.250000s user + 0.015625s system = 1.265625s CPU (100.0%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 508 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 37301 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7477 (3.86), #lev = 8 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7372 (3.96), #lev = 7 (3.04)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7400 LUTs, name keeping = 57%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9975
+  #lut4                  5274
+  #lut5                  2146
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9975   out of  19600   50.89%
+#reg                     9965   out of  19600   50.84%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7420    |2555    |9995    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |335     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |97      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |276     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2325    |738     |2645    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2253    |691     |2463    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1912    |615     |2051    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |196     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |165     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2341    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2269    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1930    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9965 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  54.805665s wall, 54.453125s user + 0.343750s system = 54.796875s CPU (100.0%)
+
+RUN-1004 : used memory is 400 MB, reserved memory is 388 MB, peak memory is 717 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.581745s wall, 2.734375s user + 0.031250s system = 2.765625s CPU (174.8%)
+
+RUN-1004 : used memory is 412 MB, reserved memory is 397 MB, peak memory is 717 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_144324.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_145451.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_145451.log
new file mode 100644
index 0000000..76081ab
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_145451.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 14:54:51 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(356)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(333)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.062768s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (100.0%)
+
+RUN-1004 : used memory is 196 MB, reserved memory is 175 MB, peak memory is 237 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55632/19116 useful/useless nets, 20771/1813 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 44168/8978 useful/useless nets, 11058/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41831/363 useful/useless nets, 39028/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 31992 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26569/1547 useful/useless nets, 23858/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 26320/80 useful/useless nets, 23641/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 26227/93 useful/useless nets, 23559/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25949/20 useful/useless nets, 23297/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.462159s wall, 17.390625s user + 2.046875s system = 19.437500s CPU (99.9%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 309 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14742
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9885
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9891   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2645   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |2463   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |2051   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.111418s wall, 1.734375s user + 0.031250s system = 1.765625s CPU (158.9%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 309 MB, peak memory is 407 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25983/24 useful/useless nets, 23346/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26301/670 useful/useless nets, 23680/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29755/338 useful/useless nets, 27135/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 37299/296 useful/useless nets, 34573/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 124905, tnet num: 37301, tinst num: 34573, tnode num: 161237, tedge num: 183966.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.320400s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (99.4%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 507 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 37301 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7477 (3.86), #lev = 8 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7372 (3.96), #lev = 7 (3.04)
+SYN-3001 : Logic optimization runtime opt =   1.27 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7400 LUTs, name keeping = 57%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9975
+  #lut4                  5274
+  #lut5                  2146
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9975   out of  19600   50.89%
+#reg                     9965   out of  19600   50.84%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7420    |2555    |9995    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |335     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |97      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |276     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2325    |738     |2645    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2253    |691     |2463    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1912    |615     |2051    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |196     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |165     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2341    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2269    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1930    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9965 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  58.287405s wall, 57.812500s user + 0.437500s system = 58.250000s CPU (99.9%)
+
+RUN-1004 : used memory is 398 MB, reserved memory is 378 MB, peak memory is 716 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.594102s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (171.5%)
+
+RUN-1004 : used memory is 413 MB, reserved memory is 397 MB, peak memory is 716 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_145451.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_150910.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_150910.log
new file mode 100644
index 0000000..94a3cd5
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_150910.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:09:11 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(365)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(356)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(333)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.088682s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (100.5%)
+
+RUN-1004 : used memory is 196 MB, reserved memory is 173 MB, peak memory is 237 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55632/19116 useful/useless nets, 20771/1813 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 44168/8978 useful/useless nets, 11058/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg16_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41831/363 useful/useless nets, 39028/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 31992 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26569/1547 useful/useless nets, 23858/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 26320/80 useful/useless nets, 23641/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 26227/93 useful/useless nets, 23559/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25949/20 useful/useless nets, 23297/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.022719s wall, 16.703125s user + 2.296875s system = 19.000000s CPU (99.9%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 309 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14742
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9885
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9891   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2645   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |2463   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |2051   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.109773s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (156.3%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 306 MB, peak memory is 407 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25983/24 useful/useless nets, 23346/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26301/670 useful/useless nets, 23680/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29757/338 useful/useless nets, 27137/38 useful/useless insts
+SYN-1016 : Merged 390 instances.
+SYN-2501 : Optimize round 1, 1768 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 37307/296 useful/useless nets, 34581/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 124925, tnet num: 37309, tinst num: 34581, tnode num: 161257, tedge num: 183990.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.322623s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (100.4%)
+
+RUN-1004 : used memory is 530 MB, reserved memory is 507 MB, peak memory is 530 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 37309 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7489 (3.86), #lev = 10 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7379 (3.96), #lev = 8 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.21 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18944 instances into 7407 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9982
+  #lut4                  5281
+  #lut5                  2146
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9982   out of  19600   50.93%
+#reg                     9965   out of  19600   50.84%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7427    |2555    |9995    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |335     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |285     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |124     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2322    |738     |2645    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2250    |691     |2463    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1909    |615     |2051    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1482    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1088    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2346    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2274    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1933    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |215     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |34      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9965 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  60.845710s wall, 60.375000s user + 0.421875s system = 60.796875s CPU (99.9%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 388 MB, peak memory is 715 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.570760s wall, 2.734375s user + 0.015625s system = 2.750000s CPU (175.1%)
+
+RUN-1004 : used memory is 412 MB, reserved memory is 393 MB, peak memory is 715 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_150910.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_151537.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_151537.log
new file mode 100644
index 0000000..2881ca6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_151537.log
@@ -0,0 +1,426 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:15:37 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'set_flag_1d' is already declared in ../../../../hg_mp/fe/sort.v(297)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../../../hg_mp/fe/sort.v(297)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../../../hg_mp/fe/sort.v(297)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(333)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(334)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(333)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(334)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(333)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(334)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../../../hg_mp/fe/sort.v(335)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-8007 ERROR: external reference 'set_flag_2d' remains unresolved in ../../../../hg_mp/fe/sort.v(333)
+HDL-1007 : module 'sort' remains a black box due to errors in its contents in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_151537.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_151606.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_151606.log
new file mode 100644
index 0000000..d12aca1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_151606.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:16:06 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.029748s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (100.1%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 174 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54516/19116 useful/useless nets, 20777/1813 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 43052/8978 useful/useless nets, 11064/4745 useful/useless insts
+SYN-1016 : Merged 1894 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40709/363 useful/useless nets, 37906/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4149 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6850 instances.
+SYN-1015 : Optimize round 1, 31068 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25975/1547 useful/useless nets, 23264/7781 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9625 better
+SYN-1032 : 25726/80 useful/useless nets, 23047/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25633/93 useful/useless nets, 22965/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25355/20 useful/useless nets, 22703/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.097730s wall, 16.640625s user + 1.468750s system = 18.109375s CPU (100.1%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 305 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14148
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9291
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9297   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2051   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1869   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.090684s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (157.6%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 301 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25389/24 useful/useless nets, 22752/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25707/670 useful/useless nets, 23086/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29161/338 useful/useless nets, 26541/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36705/296 useful/useless nets, 33979/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122529, tnet num: 36707, tinst num: 33979, tnode num: 157079, tedge num: 180402.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.253357s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (99.7%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 498 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36707 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7473 (3.86), #lev = 10 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7288 (3.96), #lev = 8 (3.01)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7316 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9891
+  #lut4                  5019
+  #lut5                  2317
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9891   out of  19600   50.46%
+#reg                     9371   out of  19600   47.81%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7336    |2555    |9401    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |343     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |130     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2281    |738     |2051    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2209    |691     |1869    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1868    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1445    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |190     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |162     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |27      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2300    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2228    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1888    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1442    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1048    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9371 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  52.778852s wall, 52.296875s user + 0.437500s system = 52.734375s CPU (99.9%)
+
+RUN-1004 : used memory is 401 MB, reserved memory is 389 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.539102s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (175.6%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 387 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_151606.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_152356.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_152356.log
new file mode 100644
index 0000000..b697d50
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_152356.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:23:56 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.033267s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (99.8%)
+
+RUN-1004 : used memory is 195 MB, reserved memory is 174 MB, peak memory is 236 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54414/19184 useful/useless nets, 20762/1828 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42950/8978 useful/useless nets, 11049/4745 useful/useless insts
+SYN-1016 : Merged 1891 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40610/363 useful/useless nets, 37807/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4116 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6751 instances.
+SYN-1015 : Optimize round 1, 30870 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25942/1547 useful/useless nets, 23231/7748 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9592 better
+SYN-1032 : 25693/80 useful/useless nets, 23014/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25600/93 useful/useless nets, 22932/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25322/20 useful/useless nets, 22670/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.243825s wall, 16.656250s user + 1.531250s system = 18.187500s CPU (99.7%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 305 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14115
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9258
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9264   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2018   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1836   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.118515s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (156.5%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 316 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25356/24 useful/useless nets, 22719/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25674/670 useful/useless nets, 23053/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29128/338 useful/useless nets, 26508/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36672/296 useful/useless nets, 33946/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122397, tnet num: 36674, tinst num: 33946, tnode num: 156848, tedge num: 180204.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.333201s wall, 1.265625s user + 0.062500s system = 1.328125s CPU (99.6%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 498 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36674 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7473 (3.86), #lev = 10 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7288 (3.96), #lev = 8 (3.01)
+SYN-3001 : Logic optimization runtime opt =   1.20 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7316 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9891
+  #lut4                  5019
+  #lut5                  2317
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9891   out of  19600   50.46%
+#reg                     9338   out of  19600   47.64%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7336    |2555    |9368    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |343     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |130     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2281    |738     |2018    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2209    |691     |1836    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1868    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1445    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |190     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |162     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |27      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2300    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2228    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1888    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1442    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1048    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9338 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  59.333856s wall, 58.796875s user + 0.421875s system = 59.218750s CPU (99.8%)
+
+RUN-1004 : used memory is 400 MB, reserved memory is 390 MB, peak memory is 704 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.562530s wall, 2.687500s user + 0.000000s system = 2.687500s CPU (172.0%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 388 MB, peak memory is 704 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_152356.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_152817.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_152817.log
new file mode 100644
index 0000000..2acf7be
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_152817.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:28:17 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.034679s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (99.7%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 172 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54426/19196 useful/useless nets, 20759/1831 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42962/8978 useful/useless nets, 11046/4745 useful/useless insts
+SYN-1016 : Merged 1885 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40628/363 useful/useless nets, 37825/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4122 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6769 instances.
+SYN-1015 : Optimize round 1, 30906 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25948/1547 useful/useless nets, 23237/7754 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9598 better
+SYN-1032 : 25699/80 useful/useless nets, 23020/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25606/93 useful/useless nets, 22938/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25328/20 useful/useless nets, 22676/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.988631s wall, 16.484375s user + 1.484375s system = 17.968750s CPU (99.9%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 304 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14121
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9264
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9270   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |2024   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1842   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.099033s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (156.4%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 314 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25362/24 useful/useless nets, 22725/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25680/670 useful/useless nets, 23059/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29134/338 useful/useless nets, 26514/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36678/296 useful/useless nets, 33952/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122421, tnet num: 36680, tinst num: 33952, tnode num: 156890, tedge num: 180240.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.239194s wall, 1.218750s user + 0.015625s system = 1.234375s CPU (99.6%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 498 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36680 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7473 (3.86), #lev = 10 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7288 (3.96), #lev = 8 (3.01)
+SYN-3001 : Logic optimization runtime opt =   1.23 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7316 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9891
+  #lut4                  5019
+  #lut5                  2317
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9891   out of  19600   50.46%
+#reg                     9344   out of  19600   47.67%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7336    |2555    |9374    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |343     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |130     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2281    |738     |2024    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2209    |691     |1842    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1868    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1445    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |190     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |162     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |27      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2300    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2228    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1888    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1442    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1048    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9344 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  55.377243s wall, 55.125000s user + 0.265625s system = 55.390625s CPU (100.0%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 394 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.557644s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (173.5%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 383 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_152817.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_153547.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_153547.log
new file mode 100644
index 0000000..83731be
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_153547.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:35:47 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.028369s wall, 1.015625s user + 0.015625s system = 1.031250s CPU (100.3%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 173 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54108/19490 useful/useless nets, 20717/1873 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38312 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42644/8977 useful/useless nets, 11004/4744 useful/useless insts
+SYN-1016 : Merged 1882 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40312/363 useful/useless nets, 37509/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4017 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6454 instances.
+SYN-1015 : Optimize round 1, 30276 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25842/1547 useful/useless nets, 23131/7649 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9493 better
+SYN-1032 : 25593/80 useful/useless nets, 22914/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25500/93 useful/useless nets, 22832/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25222/20 useful/useless nets, 22570/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.057097s wall, 16.062500s user + 2.000000s system = 18.062500s CPU (100.0%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 353 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14016
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9159
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 226
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9165   |800    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.111464s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (154.6%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 303 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25256/24 useful/useless nets, 22619/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25574/670 useful/useless nets, 22953/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29019/338 useful/useless nets, 26399/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36563/296 useful/useless nets, 33837/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121973, tnet num: 36565, tinst num: 33837, tnode num: 156128, tedge num: 179574.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.268216s wall, 1.218750s user + 0.046875s system = 1.265625s CPU (99.8%)
+
+RUN-1004 : used memory is 520 MB, reserved memory is 497 MB, peak memory is 520 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36565 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7477 (3.87), #lev = 9 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7361 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.16 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18926 instances into 7389 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9964
+  #lut4                  5248
+  #lut5                  2161
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9964   out of  19600   50.84%
+#reg                     9239   out of  19600   47.14%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7409    |2555    |9269    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |9       |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |286     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2319    |738     |1919    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2249    |691     |1737    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |193     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |31      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |2002    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2263    |704     |1820    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1925    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |147     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9239 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 7 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.268289s wall, 52.859375s user + 0.375000s system = 53.234375s CPU (99.9%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 382 MB, peak memory is 704 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.530429s wall, 2.640625s user + 0.015625s system = 2.656250s CPU (173.6%)
+
+RUN-1004 : used memory is 432 MB, reserved memory is 419 MB, peak memory is 704 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_153547.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_154213.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_154213.log
new file mode 100644
index 0000000..638fb22
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_154213.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 15:42:13 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.051368s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (99.6%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 176 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54312/19286 useful/useless nets, 20747/1843 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42848/8978 useful/useless nets, 11034/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40511/363 useful/useless nets, 37708/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 30672 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25909/1547 useful/useless nets, 23198/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 25660/80 useful/useless nets, 22981/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25567/93 useful/useless nets, 22899/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25289/20 useful/useless nets, 22637/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.427539s wall, 16.578125s user + 1.843750s system = 18.421875s CPU (100.0%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 305 MB, peak memory is 353 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14082
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9225
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9231   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1985   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1803   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.102515s wall, 1.703125s user + 0.015625s system = 1.718750s CPU (155.9%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 301 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25323/24 useful/useless nets, 22686/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25641/670 useful/useless nets, 23020/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29095/338 useful/useless nets, 26475/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36639/296 useful/useless nets, 33913/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122265, tnet num: 36641, tinst num: 33913, tnode num: 156617, tedge num: 180006.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.253283s wall, 1.203125s user + 0.062500s system = 1.265625s CPU (101.0%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 498 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7473 (3.86), #lev = 10 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7288 (3.96), #lev = 8 (3.01)
+SYN-3001 : Logic optimization runtime opt =   1.19 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7316 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9891
+  #lut4                  5019
+  #lut5                  2317
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9891   out of  19600   50.46%
+#reg                     9305   out of  19600   47.47%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7336    |2555    |9335    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |343     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |130     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2281    |738     |1985    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2209    |691     |1803    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1868    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1445    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |190     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |162     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |27      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2300    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2228    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1888    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1442    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1048    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9305 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  55.488667s wall, 55.187500s user + 0.265625s system = 55.453125s CPU (99.9%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 390 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.576323s wall, 2.718750s user + 0.031250s system = 2.750000s CPU (174.5%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 388 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_154213.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_161125.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_161125.log
new file mode 100644
index 0000000..0d2400e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_161125.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:11:25 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.033303s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (99.8%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 173 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54312/19286 useful/useless nets, 20747/1843 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42848/8978 useful/useless nets, 11034/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40511/363 useful/useless nets, 37708/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 30672 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25909/1547 useful/useless nets, 23198/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 25660/80 useful/useless nets, 22981/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25567/93 useful/useless nets, 22899/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25289/20 useful/useless nets, 22637/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.386880s wall, 16.562500s user + 1.828125s system = 18.390625s CPU (100.0%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 303 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14082
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9225
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9231   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1985   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1803   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.090024s wall, 1.687500s user + 0.031250s system = 1.718750s CPU (157.7%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 298 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25323/24 useful/useless nets, 22686/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25641/670 useful/useless nets, 23020/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29095/338 useful/useless nets, 26475/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36639/296 useful/useless nets, 33913/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122265, tnet num: 36641, tinst num: 33913, tnode num: 156617, tedge num: 180006.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.251406s wall, 1.218750s user + 0.031250s system = 1.250000s CPU (99.9%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 498 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7473 (3.86), #lev = 10 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7288 (3.96), #lev = 8 (3.01)
+SYN-3001 : Logic optimization runtime opt =   1.20 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7316 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9891
+  #lut4                  5019
+  #lut5                  2317
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9891   out of  19600   50.46%
+#reg                     9305   out of  19600   47.47%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7336    |2555    |9335    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |343     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |130     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2281    |738     |1985    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2209    |691     |1803    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1868    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1445    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1051    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |190     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |162     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |27      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2300    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2228    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1888    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1442    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1048    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9305 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  54.341707s wall, 53.828125s user + 0.390625s system = 54.218750s CPU (99.8%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 384 MB, peak memory is 704 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.547212s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (175.7%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 385 MB, peak memory is 704 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_161125.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_162824.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_162824.log
new file mode 100644
index 0000000..0921a04
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_162824.log
@@ -0,0 +1,1890 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:28:24 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-5007 WARNING: port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer.v(342)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(109)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: input port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer.v(354)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-5007 WARNING: port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer_rev.v(341)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: input port 'trig_FIFO' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(254)
+HDL-5007 WARNING: input port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer_rev.v(353)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.068106s wall, 1.046875s user + 0.031250s system = 1.078125s CPU (100.9%)
+
+RUN-1004 : used memory is 191 MB, reserved memory is 157 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54313/19288 useful/useless nets, 20747/1843 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42864/8963 useful/useless nets, 11053/4726 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(288) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/channelPart/trig_FIFO" in ../../../../hg_mp/fe/channel_part_8478.v(27)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/channel_part_8478.v(49)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/channel_part_8478.v(49)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/channel_part_8478.v(49)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/channel_part_8478.v(49)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/channel_part_8478.v(49)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/channel_part_8478.v(49)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40517/363 useful/useless nets, 37714/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 133 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4088 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6658 instances.
+SYN-1015 : Optimize round 1, 30682 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25914/1547 useful/useless nets, 23203/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9561 better
+SYN-1032 : 25659/90 useful/useless nets, 22988/111 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25565/94 useful/useless nets, 22905/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 4 instances.
+SYN-1015 : Optimize round 1, 277 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25294/10 useful/useless nets, 22642/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.176271s wall, 16.703125s user + 1.484375s system = 18.187500s CPU (100.1%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 304 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14087
+  #and                   2483
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    470
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9226
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4855   |9232   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1849   |1986   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1805   |1804   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1550   |1392   |119    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1809   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1767   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1513   |1408   |120    |
+|        channelPart           |channel_part_8478    |867    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.101750s wall, 1.718750s user + 0.015625s system = 1.734375s CPU (157.4%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 300 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25328/24 useful/useless nets, 22691/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25646/670 useful/useless nets, 23025/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 313 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29096/338 useful/useless nets, 26476/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36640/296 useful/useless nets, 33914/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122262, tnet num: 36642, tinst num: 33914, tnode num: 156616, tedge num: 179998.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.248548s wall, 1.234375s user + 0.015625s system = 1.250000s CPU (100.1%)
+
+RUN-1004 : used memory is 520 MB, reserved memory is 497 MB, peak memory is 520 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36642 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7481 (3.86), #lev = 10 (3.07)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7316 (3.95), #lev = 8 (3.06)
+SYN-3001 : Logic optimization runtime opt =   1.16 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7344 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9919
+  #lut4                  5093
+  #lut5                  2271
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9919   out of  19600   50.61%
+#reg                     9306   out of  19600   47.48%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7364    |2555    |9336    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |340     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |101     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |275     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2283    |738     |1986    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2211    |691     |1804    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1872    |615     |1392    |22      |0       |
+|        channelPart           |channel_part_8478    |151     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |50      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1446    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1052    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |193     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |31      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2296    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2224    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1885    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1442    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1048    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |209     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |27      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9306 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  52.477601s wall, 52.109375s user + 0.328125s system = 52.437500s CPU (99.9%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 376 MB, peak memory is 704 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.547539s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (176.7%)
+
+RUN-1004 : used memory is 432 MB, reserved memory is 419 MB, peak memory is 704 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_162824.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_163301.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_163301.log
new file mode 100644
index 0000000..f422a2a
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_163301.log
@@ -0,0 +1,1881 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:33:01 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-5007 WARNING: port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer.v(342)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(109)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: input port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer.v(354)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-5007 WARNING: port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer_rev.v(342)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: input port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer_rev.v(354)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.036410s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (101.0%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 176 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54312/19288 useful/useless nets, 20747/1843 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42844/8982 useful/useless nets, 11034/4745 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(288) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40515/363 useful/useless nets, 37712/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4094 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6670 instances.
+SYN-1015 : Optimize round 1, 30694 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25912/1547 useful/useless nets, 23201/7721 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9567 better
+SYN-1032 : 25658/90 useful/useless nets, 22987/110 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25565/93 useful/useless nets, 22905/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 276 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25295/10 useful/useless nets, 22643/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.992160s wall, 16.218750s user + 1.765625s system = 17.984375s CPU (100.0%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 305 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14088
+  #and                   2482
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    471
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9227
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4855   |9233   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1849   |1986   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1805   |1804   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1550   |1392   |119    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1809   |2003   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1767   |1821   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1513   |1409   |120    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.107420s wall, 1.671875s user + 0.031250s system = 1.703125s CPU (153.8%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25329/24 useful/useless nets, 22692/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25647/670 useful/useless nets, 23026/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 319 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29103/338 useful/useless nets, 26483/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36647/296 useful/useless nets, 33921/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122277, tnet num: 36649, tinst num: 33921, tnode num: 156628, tedge num: 180014.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.249105s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (100.1%)
+
+RUN-1004 : used memory is 522 MB, reserved memory is 499 MB, peak memory is 522 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36649 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7483 (3.86), #lev = 9 (3.09)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7369 (3.96), #lev = 7 (3.06)
+SYN-3001 : Logic optimization runtime opt =   1.17 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18942 instances into 7397 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9972
+  #lut4                  5298
+  #lut5                  2119
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9972   out of  19600   50.88%
+#reg                     9307   out of  19600   47.48%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7417    |2555    |9337    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |338     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |276     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |93      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2323    |738     |1986    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |1804    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1912    |615     |1392    |22      |0       |
+|        channelPart           |channel_part_8478    |151     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |50      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |196     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |31      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2339    |751     |2003    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2267    |704     |1821    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1928    |628     |1409    |22      |1       |
+|        channelPart           |channel_part_8478    |152     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |50      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |209     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |27      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9307 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  53.133299s wall, 52.781250s user + 0.328125s system = 53.109375s CPU (100.0%)
+
+RUN-1004 : used memory is 398 MB, reserved memory is 390 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.548604s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (174.6%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 390 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_163301.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_163550.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_163550.log
new file mode 100644
index 0000000..3c118d6
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_163550.log
@@ -0,0 +1,1875 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:35:50 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(342)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(371)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-5007 WARNING: port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer.v(342)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(109)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: input port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer.v(354)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(362)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(339)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-5007 WARNING: port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer_rev.v(342)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: input port 'trig_FIFO' is not connected on this instance in ../../../../hg_mp/fe/prebuffer_rev.v(354)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.035915s wall, 1.000000s user + 0.031250s system = 1.031250s CPU (99.5%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 173 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54312/19292 useful/useless nets, 20747/1847 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42844/8982 useful/useless nets, 11034/4745 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(288) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40515/363 useful/useless nets, 37712/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4094 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6670 instances.
+SYN-1015 : Optimize round 1, 30694 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25912/1547 useful/useless nets, 23201/7721 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9567 better
+SYN-1032 : 25658/90 useful/useless nets, 22987/110 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25565/93 useful/useless nets, 22905/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 276 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25295/10 useful/useless nets, 22643/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.307458s wall, 15.937500s user + 2.359375s system = 18.296875s CPU (99.9%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 353 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14088
+  #and                   2482
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    471
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9227
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4855   |9233   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1849   |1986   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1805   |1804   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1550   |1392   |119    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1809   |2003   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1767   |1821   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1513   |1409   |120    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.092961s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (155.8%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 316 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25329/24 useful/useless nets, 22692/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25647/670 useful/useless nets, 23026/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 319 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29103/338 useful/useless nets, 26483/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36647/296 useful/useless nets, 33921/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122277, tnet num: 36649, tinst num: 33921, tnode num: 156628, tedge num: 180014.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.252826s wall, 1.218750s user + 0.046875s system = 1.265625s CPU (101.0%)
+
+RUN-1004 : used memory is 522 MB, reserved memory is 499 MB, peak memory is 522 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36649 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7483 (3.86), #lev = 9 (3.09)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7369 (3.96), #lev = 7 (3.06)
+SYN-3001 : Logic optimization runtime opt =   1.18 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18942 instances into 7397 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9972
+  #lut4                  5298
+  #lut5                  2119
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9972   out of  19600   50.88%
+#reg                     9307   out of  19600   47.48%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7417    |2555    |9337    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |338     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |276     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |93      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2323    |738     |1986    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |1804    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1912    |615     |1392    |22      |0       |
+|        channelPart           |channel_part_8478    |151     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |50      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |196     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |31      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2339    |751     |2003    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2267    |704     |1821    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1928    |628     |1409    |22      |1       |
+|        channelPart           |channel_part_8478    |152     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |50      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |209     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |27      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9307 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  54.613227s wall, 54.156250s user + 0.406250s system = 54.562500s CPU (99.9%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 379 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.550668s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (174.3%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 386 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_163550.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_164733.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_164733.log
new file mode 100644
index 0000000..7ee8e06
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_164733.log
@@ -0,0 +1,1886 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:47:33 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(357)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(334)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'trig_FIFO' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: input port 'trig_FIFO' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(201)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.111429s wall, 1.062500s user + 0.046875s system = 1.109375s CPU (99.8%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54395/19120 useful/useless nets, 20759/1817 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42985/8924 useful/useless nets, 11104/4687 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(289) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/trig_FIFO" in ../../../../hg_mp/fe/fifo_adc.v(21)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 WARNING: the net's pin: pin "sel" in ../../../../hg_mp/fe/fifo_adc.v(54)
+SYN-5014 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40599/363 useful/useless nets, 37796/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 168 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4135 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6792 instances.
+SYN-1015 : Optimize round 1, 30898 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25915/1585 useful/useless nets, 23204/7762 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 119 instances.
+SYN-1015 : Optimize round 2, 9647 better
+SYN-1032 : 25660/90 useful/useless nets, 22989/110 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 1185 const0 DFF(s)
+SYN-3008 : Optimized 12 const1 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 21657/4003 useful/useless nets, 19412/2306 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 298 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 21365/10 useful/useless nets, 19128/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.652449s wall, 15.656250s user + 1.968750s system = 17.625000s CPU (99.8%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 305 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            11637
+  #and                   1820
+  #nand                     0
+  #or                     719
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    433
+  #bufif1                   5
+  #MX21                   612
+  #FADD                     0
+  #DFF                   7838
+  #LATCH                    6
+#MACRO_ADD                447
+#MACRO_EQ                 212
+#MACRO_MULT                 3
+#MACRO_MUX               3815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |3793   |7844   |735    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |788    |610    |205    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |75     |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |744    |500    |194    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |489    |178    |54     |
+|        ram_switch            |ram_switch           |0      |0      |0      |
+|          adc_addr_gen        |adc_addr_gen         |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1811   |2003   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1769   |1821   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1515   |1409   |120    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |114    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|          read_ram_data       |read_ram_data_rev    |34     |42     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.000175s wall, 1.578125s user + 0.046875s system = 1.625000s CPU (162.5%)
+
+RUN-1004 : used memory is 341 MB, reserved memory is 311 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 21399/24 useful/useless nets, 19177/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 3 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 21645/742 useful/useless nets, 19439/652 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1325 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 258 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 24900/338 useful/useless nets, 22695/38 useful/useless insts
+SYN-1016 : Merged 367 instances.
+SYN-2501 : Optimize round 1, 1659 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 448 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9244 mux instances.
+SYN-1016 : Merged 10598 instances.
+SYN-1032 : 30193/293 useful/useless nets, 27882/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 99112, tnet num: 30195, tinst num: 27882, tnode num: 128714, tedge num: 145709.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.096943s wall, 1.093750s user + 0.000000s system = 1.093750s CPU (99.7%)
+
+RUN-1004 : used memory is 471 MB, reserved memory is 446 MB, peak memory is 471 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 30195 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 5720 (3.87), #lev = 9 (2.97)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 5644 (3.94), #lev = 7 (2.99)
+SYN-3001 : Logic optimization runtime opt =   1.01 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 14802 instances into 5672 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              7778
+  #lut4                  3898
+  #lut5                  1794
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2086
+
+Utilization Statistics
+#lut                     7778   out of  19600   39.68%
+#reg                     7882   out of  19600   40.21%
+#le                         0
+#dsp                        2   out of     29    6.90%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      12
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |5692    |2086    |7912    |58      |2       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |338     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |97      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |275     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |603     |281     |610     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |75      |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |555     |234     |500     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |210     |158     |178     |22      |0       |
+|        read_ram_i            |read_ram             |200     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |166     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |33      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |130     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2353    |751     |2003    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2281    |704     |1821    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1942    |628     |1409    |22      |0       |
+|        channelPart           |channel_part_8478    |152     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |50      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |219     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |184     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |35      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 7882 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 63 carry chain into lslice
+SYN-4007 : Packing 1033 adder to BLE ...
+SYN-4008 : Packed 1033 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 12 DRAM and 7 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  44.612125s wall, 44.296875s user + 0.250000s system = 44.546875s CPU (99.9%)
+
+RUN-1004 : used memory is 366 MB, reserved memory is 347 MB, peak memory is 617 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.405564s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (172.3%)
+
+RUN-1004 : used memory is 375 MB, reserved memory is 355 MB, peak memory is 617 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_164733.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_165809.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_165809.log
new file mode 100644
index 0000000..a1a5676
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_165809.log
@@ -0,0 +1,1878 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 16:58:09 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(357)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(334)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'trig_FIFO' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: input port 'trig_FIFO' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(201)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.178696s wall, 1.125000s user + 0.015625s system = 1.140625s CPU (96.8%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54395/19120 useful/useless nets, 20759/1817 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38237 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42925/8962 useful/useless nets, 11038/4728 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(289) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/trig_FIFO" in ../../../../hg_mp/fe/fifo_adc.v(21)
+SYN-5014 WARNING: the net's pin: pin "I" in ../../../../hg_mp/fe/fifo_adc.v(66)
+SYN-5014 WARNING: the net's pin: pin "i1" in ../../../../hg_mp/fe/fifo_adc.v(62)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40594/363 useful/useless nets, 37791/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4179 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6912 instances.
+SYN-1015 : Optimize round 1, 31021 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 16 inv instances.
+SYN-1032 : 25912/1624 useful/useless nets, 23201/7809 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 120 instances.
+SYN-1015 : Optimize round 2, 9734 better
+SYN-1032 : 25656/90 useful/useless nets, 22985/110 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 1185 const0 DFF(s)
+SYN-3008 : Optimized 12 const1 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 1183 const0 DFF(s)
+SYN-3008 : Optimized 12 const1 DFF(s)
+SYN-1032 : 17736/7920 useful/useless nets, 15914/4607 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 317 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 17430/0 useful/useless nets, 15608/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.426615s wall, 16.375000s user + 1.984375s system = 18.359375s CPU (99.6%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 305 MB, peak memory is 356 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates             9182
+  #and                   1154
+  #nand                     0
+  #or                     360
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    395
+  #bufif1                   5
+  #MX21                   609
+  #FADD                     0
+  #DFF                   6449
+  #LATCH                    6
+#MACRO_ADD                397
+#MACRO_EQ                 197
+#MACRO_MULT                 2
+#MACRO_MUX               2816
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |2727   |6455   |669    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |788    |610    |205    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |75     |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |744    |500    |194    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |489    |178    |54     |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |748    |627    |204    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |75     |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |706    |517    |194    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |452    |195    |55     |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|          read_ram_data       |read_ram_data_rev    |34     |42     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  scan_start_diff             |scan_start_diff      |8      |12     |0      |
+|  u0_test_en                  |cdc_sync             |2      |5      |0      |
+|  u1_test_en                  |cdc_sync             |2      |5      |0      |
+|  u2_test_en                  |cdc_sync             |2      |5      |0      |
+|  u_a_pclk                    |cdc_sync             |2      |5      |0      |
+|  u_a_sp_sampling             |cdc_sync             |2      |5      |0      |
+|  u_a_sp_sampling_cam         |cdc_sync             |2      |5      |0      |
+|  u_a_sp_sampling_last        |cdc_sync             |2      |5      |0      |
+|  u_b_pclk                    |cdc_sync             |2      |5      |0      |
+|  u_b_sp_sampling             |cdc_sync             |2      |5      |0      |
+|  u_b_sp_sampling_cam         |cdc_sync             |2      |5      |0      |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.053520s wall, 1.578125s user + 0.031250s system = 1.609375s CPU (152.8%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 309 MB, peak memory is 393 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 17464/24 useful/useless nets, 15657/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 2 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 17638/814 useful/useless nets, 15847/724 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1469 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 187 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 20671/349 useful/useless nets, 18882/49 useful/useless insts
+SYN-1016 : Merged 338 instances.
+SYN-2501 : Optimize round 1, 1555 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 398 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 8798 mux instances.
+SYN-1016 : Merged 9091 instances.
+SYN-1032 : 23713/290 useful/useless nets, 21818/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75869, tnet num: 23715, tinst num: 21818, tnode num: 100713, tedge num: 111234.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.074404s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (98.9%)
+
+RUN-1004 : used memory is 422 MB, reserved memory is 395 MB, peak memory is 422 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 23715 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 3911 (3.92), #lev = 9 (2.74)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 3873 (3.90), #lev = 7 (2.75)
+SYN-3001 : Logic optimization runtime opt =   0.80 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 10647 instances into 3901 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              5538
+  #lut4                  2509
+  #lut5                  1412
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            1617
+
+Utilization Statistics
+#lut                     5538   out of  19600   28.26%
+#reg                     6446   out of  19600   32.89%
+#le                         0
+#dsp                        2   out of     29    6.90%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                       8
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |3921    |1617    |6476    |58      |2       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |430     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |283     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |279     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |586     |281     |610     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |75      |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |538     |234     |500     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |197     |158     |178     |22      |0       |
+|        read_ram_i            |read_ram             |185     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |158     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |26      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |606     |294     |627     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |75      |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |558     |247     |517     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |217     |171     |195     |22      |0       |
+|        read_ram_i            |read_ram_rev         |207     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |179     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  scan_start_diff             |scan_start_diff      |30      |0       |12      |0       |0       |
+|  u0_test_en                  |cdc_sync             |1       |0       |5       |0       |0       |
+|  u1_test_en                  |cdc_sync             |1       |0       |5       |0       |0       |
+|  u2_test_en                  |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_a_pclk                    |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_a_sp_sampling             |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_a_sp_sampling_cam         |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_a_sp_sampling_last        |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_b_pclk                    |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_b_sp_sampling             |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_b_sp_sampling_cam         |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_b_sp_sampling_last        |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_bus_top                   |ubus_top             |813     |50      |1248    |0       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 6446 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 42 carry chain into lslice
+SYN-4007 : Packing 800 adder to BLE ...
+SYN-4008 : Packed 800 adder and 167 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 8 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  40.718235s wall, 40.437500s user + 0.234375s system = 40.671875s CPU (99.9%)
+
+RUN-1004 : used memory is 349 MB, reserved memory is 331 MB, peak memory is 527 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.300738s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (175.4%)
+
+RUN-1004 : used memory is 368 MB, reserved memory is 354 MB, peak memory is 527 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_165809.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_170201.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_170201.log
new file mode 100644
index 0000000..473767f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_170201.log
@@ -0,0 +1,1877 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 17:02:01 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(357)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(334)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'trig_FIFO' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: input port 'trig_FIFO' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(201)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.179552s wall, 1.171875s user + 0.015625s system = 1.187500s CPU (100.7%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 169 MB, peak memory is 239 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54385/19130 useful/useless nets, 20749/1827 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38227 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42925/8962 useful/useless nets, 11038/4728 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(289) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/trig_FIFO" in ../../../../hg_mp/fe/fifo_adc.v(21)
+SYN-5014 WARNING: the net's pin: pin "I" in ../../../../hg_mp/fe/fifo_adc.v(66)
+SYN-5014 WARNING: the net's pin: pin "i1" in ../../../../hg_mp/fe/fifo_adc.v(62)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40594/363 useful/useless nets, 37791/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4179 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6910 instances.
+SYN-1015 : Optimize round 1, 31019 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 16 inv instances.
+SYN-1032 : 25914/1624 useful/useless nets, 23203/7809 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9732 better
+SYN-1032 : 25660/90 useful/useless nets, 22989/110 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 1182 const0 DFF(s)
+SYN-3008 : Optimized 12 const1 DFF(s)
+SYN-1032 : 21649/4011 useful/useless nets, 19412/2309 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 295 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 21365/0 useful/useless nets, 19128/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.370786s wall, 17.156250s user + 2.187500s system = 19.343750s CPU (99.9%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            11637
+  #and                   1819
+  #nand                     0
+  #or                     719
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    434
+  #bufif1                   5
+  #MX21                   612
+  #FADD                     0
+  #DFF                   7838
+  #LATCH                    6
+#MACRO_ADD                447
+#MACRO_EQ                 212
+#MACRO_MULT                 3
+#MACRO_MUX               3815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |3793   |7844   |735    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1851   |1986   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1807   |1804   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1552   |1392   |119    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |114    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |748    |627    |204    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |75     |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |706    |517    |194    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |452    |195    |55     |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|          read_ram_data       |read_ram_data_rev    |34     |42     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.091546s wall, 1.703125s user + 0.000000s system = 1.703125s CPU (156.0%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 313 MB, peak memory is 399 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 21399/24 useful/useless nets, 19177/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 3 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 21645/742 useful/useless nets, 19439/652 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1325 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 251 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 24893/338 useful/useless nets, 22688/38 useful/useless insts
+SYN-1016 : Merged 367 instances.
+SYN-2501 : Optimize round 1, 1659 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 448 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9244 mux instances.
+SYN-1016 : Merged 10598 instances.
+SYN-1032 : 30186/293 useful/useless nets, 27875/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 99089, tnet num: 30188, tinst num: 27875, tnode num: 128693, tedge num: 145679.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.203544s wall, 1.156250s user + 0.046875s system = 1.203125s CPU (100.0%)
+
+RUN-1004 : used memory is 471 MB, reserved memory is 445 MB, peak memory is 471 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 30188 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 5713 (3.89), #lev = 10 (2.98)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 5564 (3.95), #lev = 7 (2.95)
+SYN-3001 : Logic optimization runtime opt =   1.12 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 14795 instances into 5592 LUTs, name keeping = 60%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              7698
+  #lut4                  3687
+  #lut5                  1925
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2086
+
+Utilization Statistics
+#lut                     7698   out of  19600   39.28%
+#reg                     7882   out of  19600   40.21%
+#le                         0
+#dsp                        2   out of     29    6.90%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      12
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |5612    |2086    |7912    |58      |2       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |275     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2296    |738     |1986    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2224    |691     |1804    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1879    |615     |1392    |22      |0       |
+|        channelPart           |channel_part_8478    |152     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |55      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1440    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1046    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |200     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |173     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |26      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |130     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |613     |294     |627     |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |75      |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |565     |247     |517     |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |222     |171     |195     |22      |0       |
+|        fifo_adc              |fifo_adc             |1       |0       |0       |0       |0       |
+|        read_ram_i            |read_ram_rev         |212     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |30      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 7882 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 63 carry chain into lslice
+SYN-4007 : Packing 1033 adder to BLE ...
+SYN-4008 : Packed 1033 adder and 146 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 12 DRAM and 7 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  52.353075s wall, 52.000000s user + 0.328125s system = 52.328125s CPU (100.0%)
+
+RUN-1004 : used memory is 366 MB, reserved memory is 342 MB, peak memory is 616 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.481267s wall, 2.546875s user + 0.031250s system = 2.578125s CPU (174.0%)
+
+RUN-1004 : used memory is 376 MB, reserved memory is 358 MB, peak memory is 616 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_170201.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_170914.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_170914.log
new file mode 100644
index 0000000..908b4b7
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240311_170914.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 17:09:14 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(216)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(357)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(334)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.677089s wall, 1.484375s user + 0.062500s system = 1.546875s CPU (92.2%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 173 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54372/19130 useful/useless nets, 20747/1827 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38303 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42902/8982 useful/useless nets, 11042/4745 useful/useless insts
+SYN-1016 : Merged 1873 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(290) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40584/363 useful/useless nets, 37781/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4175 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6910 instances.
+SYN-1015 : Optimize round 1, 31008 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25915/1623 useful/useless nets, 23204/7797 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9721 better
+SYN-1032 : 25654/100 useful/useless nets, 22991/110 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25561/93 useful/useless nets, 22909/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 273 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25299/0 useful/useless nets, 22647/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.382824s wall, 17.484375s user + 1.906250s system = 19.390625s CPU (100.0%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 305 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14092
+  #and                   2484
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    473
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9227
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4859   |9233   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1851   |1986   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1807   |1804   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1552   |1392   |119    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |114    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1811   |2003   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1769   |1821   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1515   |1409   |120    |
+|        channelPart           |channel_part_8478    |866    |145    |8      |
+|        fifo_adc              |fifo_adc             |114    |41     |5      |
+|        ram_switch            |ram_switch           |61     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |26     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.158836s wall, 1.828125s user + 0.000000s system = 1.828125s CPU (157.8%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 301 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25333/24 useful/useless nets, 22696/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25651/670 useful/useless nets, 23030/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 315 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29103/338 useful/useless nets, 26483/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36647/296 useful/useless nets, 33921/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122268, tnet num: 36649, tinst num: 33921, tnode num: 156617, tedge num: 179996.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.384306s wall, 1.359375s user + 0.031250s system = 1.390625s CPU (100.5%)
+
+RUN-1004 : used memory is 520 MB, reserved memory is 497 MB, peak memory is 520 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36649 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7491 (3.85), #lev = 9 (3.08)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7403 (3.95), #lev = 7 (3.06)
+SYN-3001 : Logic optimization runtime opt =   1.37 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18942 instances into 7431 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10006
+  #lut4                  5323
+  #lut5                  2128
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                    10006   out of  19600   51.05%
+#reg                     9307   out of  19600   47.48%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7451    |2555    |9337    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |335     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |9       |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |288     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |130     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |280     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |131     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2325    |738     |1986    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2253    |691     |1804    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1914    |615     |1392    |22      |0       |
+|        channelPart           |channel_part_8478    |151     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |54      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |165     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |28      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2347    |751     |2003    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2275    |704     |1821    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1936    |628     |1409    |22      |1       |
+|        channelPart           |channel_part_8478    |152     |11      |145     |0       |0       |
+|        fifo_adc              |fifo_adc             |54      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |220     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |184     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |36      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9307 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  64.459522s wall, 64.000000s user + 0.390625s system = 64.390625s CPU (99.9%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 386 MB, peak memory is 706 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.658769s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (177.1%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 388 MB, peak memory is 706 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240311_170914.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_092722.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_092722.log
new file mode 100644
index 0000000..1281b6d
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_092722.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 09:27:23 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(337)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(366)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(357)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(334)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(367)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(397)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(387)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.074766s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (100.3%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 173 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54312/19120 useful/useless nets, 20747/1817 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38311 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42848/8978 useful/useless nets, 11034/4745 useful/useless insts
+SYN-1016 : Merged 1888 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40511/363 useful/useless nets, 37708/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 4083 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6652 instances.
+SYN-1015 : Optimize round 1, 30672 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25909/1547 useful/useless nets, 23198/7715 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9559 better
+SYN-1032 : 25660/80 useful/useless nets, 22981/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25567/93 useful/useless nets, 22899/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25289/20 useful/useless nets, 22637/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.959851s wall, 16.625000s user + 1.296875s system = 17.921875s CPU (99.8%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 305 MB, peak memory is 353 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14082
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9225
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9231   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1985   |270    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1803   |259    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2002   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1820   |259    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |120    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |5      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.103524s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (155.8%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 302 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25323/24 useful/useless nets, 22686/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25641/670 useful/useless nets, 23020/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29095/338 useful/useless nets, 26475/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36639/296 useful/useless nets, 33913/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 122265, tnet num: 36641, tinst num: 33913, tnode num: 156617, tedge num: 180006.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.272651s wall, 1.218750s user + 0.062500s system = 1.281250s CPU (100.7%)
+
+RUN-1004 : used memory is 520 MB, reserved memory is 497 MB, peak memory is 520 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36641 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7479 (3.86), #lev = 9 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7369 (3.96), #lev = 8 (3.08)
+SYN-3001 : Logic optimization runtime opt =   1.20 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18936 instances into 7397 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9972
+  #lut4                  5277
+  #lut5                  2140
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9972   out of  19600   50.88%
+#reg                     9305   out of  19600   47.47%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7417    |2555    |9335    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |286     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |276     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |90      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1985    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2245    |691     |1803    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1904    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1478    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1084    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |193     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |31      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2342    |751     |2002    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |41      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2270    |704     |1820    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1931    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1480    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1086    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |216     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |186     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |30      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9305 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 10 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  56.563164s wall, 56.093750s user + 0.437500s system = 56.531250s CPU (99.9%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 380 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.551971s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (174.2%)
+
+RUN-1004 : used memory is 407 MB, reserved memory is 387 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_092722.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_093131.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_093131.log
new file mode 100644
index 0000000..7418ce2
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_093131.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 09:31:31 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.032558s wall, 0.968750s user + 0.062500s system = 1.031250s CPU (99.9%)
+
+RUN-1004 : used memory is 198 MB, reserved memory is 172 MB, peak memory is 239 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53904/19216 useful/useless nets, 20687/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  17.946365s wall, 16.406250s user + 1.500000s system = 17.906250s CPU (99.8%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 304 MB, peak memory is 352 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.080538s wall, 1.671875s user + 0.046875s system = 1.718750s CPU (159.1%)
+
+RUN-1004 : used memory is 329 MB, reserved memory is 298 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121681, tnet num: 36489, tinst num: 33761, tnode num: 155639, tedge num: 179142.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.266295s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (99.9%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 495 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7464 (3.87), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7335 (3.96), #lev = 7 (3.04)
+SYN-3001 : Logic optimization runtime opt =   1.21 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7363 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9938
+  #lut4                  5189
+  #lut5                  2194
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9938   out of  19600   50.70%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7383    |2555    |9203    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |338     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |278     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |128     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2299    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2229    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1889    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |190     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |28      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2338    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2268    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1929    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |215     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |185     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |30      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  54.321417s wall, 53.984375s user + 0.281250s system = 54.265625s CPU (99.9%)
+
+RUN-1004 : used memory is 394 MB, reserved memory is 383 MB, peak memory is 699 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.536098s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (172.9%)
+
+RUN-1004 : used memory is 402 MB, reserved memory is 385 MB, peak memory is 699 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_093131.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_100945.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_100945.log
new file mode 100644
index 0000000..2cebc81
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_100945.log
@@ -0,0 +1,434 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:09:46 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-5007 WARNING: data object 'DVAL' is already declared in ../../../../hg_mp/fe/read_ram_data.v(120)
+HDL-1007 : previous declaration of 'DVAL' is from here in ../../../../hg_mp/fe/read_ram_data.v(31)
+HDL-5007 WARNING: second declaration of 'DVAL' is ignored in ../../../../hg_mp/fe/read_ram_data.v(120)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(130)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(133)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(134)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(135)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(136)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(130)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(133)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(134)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(135)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(136)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(130)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(133)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(134)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(135)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../../../hg_mp/fe/read_ram_data.v(136)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-8007 ERROR: external reference 'DVAL_tmp' remains unresolved in ../../../../hg_mp/fe/read_ram_data.v(130)
+HDL-1007 : module 'read_ram_data' remains a black box due to errors in its contents in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_100945.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_101001.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_101001.log
new file mode 100644
index 0000000..43ee9e1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_101001.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:10:02 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.144939s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (101.0%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 174 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53955/19216 useful/useless nets, 20669/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42520/8971 useful/useless nets, 10985/4738 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40193/363 useful/useless nets, 37390/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3976 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6280 instances.
+SYN-1015 : Optimize round 1, 29979 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25806/1547 useful/useless nets, 23095/7608 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9452 better
+SYN-1032 : 25557/80 useful/useless nets, 22878/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25464/93 useful/useless nets, 22796/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25186/20 useful/useless nets, 22534/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.660758s wall, 17.031250s user + 1.500000s system = 18.531250s CPU (99.3%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 302 MB, peak memory is 353 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13981
+  #and                   2486
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9118
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4857   |9124   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1848   |1944   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1804   |1762   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1549   |1416   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |122    |189    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |51     |57     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1812   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1770   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1516   |1408   |119    |
+|        channelPart           |channel_part_8478    |870    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.046895s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (165.7%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 313 MB, peak memory is 401 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25220/24 useful/useless nets, 22583/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25538/670 useful/useless nets, 22917/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28974/338 useful/useless nets, 26354/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36518/296 useful/useless nets, 33792/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121799, tnet num: 36520, tinst num: 33792, tnode num: 155832, tedge num: 179316.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.273762s wall, 1.234375s user + 0.031250s system = 1.265625s CPU (99.4%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 495 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36520 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7480 (3.86), #lev = 10 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7380 (3.96), #lev = 7 (3.02)
+SYN-3001 : Logic optimization runtime opt =   1.24 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18922 instances into 7408 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9983
+  #lut4                  5301
+  #lut5                  2127
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9983   out of  19600   50.93%
+#reg                     9198   out of  19600   46.93%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7428    |2555    |9228    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |341     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2321    |738     |1944    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |1762    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2096    |615     |1416    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1482    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1088    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |380     |158     |189     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |165     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |214     |13      |57      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2338    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2268    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1928    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9198 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  57.983253s wall, 57.515625s user + 0.375000s system = 57.890625s CPU (99.8%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 392 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.554080s wall, 2.703125s user + 0.015625s system = 2.718750s CPU (174.9%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 384 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_101001.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_103007.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_103007.log
new file mode 100644
index 0000000..808cbd3
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_103007.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:30:07 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.114127s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (99.6%)
+
+RUN-1004 : used memory is 191 MB, reserved memory is 159 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53978/19216 useful/useless nets, 20688/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42538/8976 useful/useless nets, 10999/4743 useful/useless insts
+SYN-1016 : Merged 1875 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40215/359 useful/useless nets, 37413/553 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3980 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6292 instances.
+SYN-1015 : Optimize round 1, 30001 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25822/1545 useful/useless nets, 23112/7610 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9452 better
+SYN-1032 : 25573/80 useful/useless nets, 22895/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25480/93 useful/useless nets, 22813/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25202/20 useful/useless nets, 22551/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.652980s wall, 16.421875s user + 2.203125s system = 18.625000s CPU (99.8%)
+
+RUN-1004 : used memory is 333 MB, reserved memory is 303 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13980
+  #and                   2481
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9122
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4852   |9128   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1848   |1948   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1804   |1766   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1549   |1420   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |122    |189    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |51     |57     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.058292s wall, 1.703125s user + 0.031250s system = 1.734375s CPU (163.9%)
+
+RUN-1004 : used memory is 328 MB, reserved memory is 298 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25236/24 useful/useless nets, 22600/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25554/670 useful/useless nets, 22934/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 311 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28984/338 useful/useless nets, 26365/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36528/296 useful/useless nets, 33803/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121824, tnet num: 36530, tinst num: 33803, tnode num: 155905, tedge num: 179375.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.286263s wall, 1.281250s user + 0.015625s system = 1.296875s CPU (100.8%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 495 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36530 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7483 (3.86), #lev = 9 (3.12)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7369 (3.96), #lev = 7 (3.01)
+SYN-3001 : Logic optimization runtime opt =   1.23 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18913 instances into 7397 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9972
+  #lut4                  5270
+  #lut5                  2147
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9972   out of  19600   50.88%
+#reg                     9202   out of  19600   46.95%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7417    |2555    |9232    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |339     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |285     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |90      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2322    |738     |1948    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2252    |691     |1766    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2095    |615     |1420    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1482    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1088    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |382     |158     |189     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |166     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |215     |13      |57      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2336    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2266    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1925    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9202 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  57.911331s wall, 57.640625s user + 0.265625s system = 57.906250s CPU (100.0%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 390 MB, peak memory is 702 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.546314s wall, 2.656250s user + 0.046875s system = 2.703125s CPU (174.8%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 387 MB, peak memory is 702 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_103007.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_103910.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_103910.log
new file mode 100644
index 0000000..36621af
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_103910.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:39:10 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.098599s wall, 1.046875s user + 0.046875s system = 1.093750s CPU (99.6%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 173 MB, peak memory is 239 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53984/19216 useful/useless nets, 20694/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42542/8976 useful/useless nets, 11003/4743 useful/useless insts
+SYN-1016 : Merged 1875 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40219/359 useful/useless nets, 37417/553 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3980 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6292 instances.
+SYN-1015 : Optimize round 1, 30005 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25824/1545 useful/useless nets, 23114/7610 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9452 better
+SYN-1032 : 25575/80 useful/useless nets, 22897/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25482/93 useful/useless nets, 22815/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25204/20 useful/useless nets, 22553/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.215237s wall, 16.687500s user + 1.531250s system = 18.218750s CPU (100.0%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 353 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13982
+  #and                   2481
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9124
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4852   |9130   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1848   |1950   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1804   |1768   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1549   |1422   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |122    |189    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |51     |57     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.060207s wall, 1.750000s user + 0.015625s system = 1.765625s CPU (166.5%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 313 MB, peak memory is 401 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25238/24 useful/useless nets, 22602/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25556/670 useful/useless nets, 22936/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 311 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28986/338 useful/useless nets, 26367/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36530/296 useful/useless nets, 33805/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121832, tnet num: 36532, tinst num: 33805, tnode num: 155919, tedge num: 179387.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.347363s wall, 1.312500s user + 0.031250s system = 1.343750s CPU (99.7%)
+
+RUN-1004 : used memory is 520 MB, reserved memory is 497 MB, peak memory is 520 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36532 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7486 (3.86), #lev = 9 (3.13)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7327 (3.94), #lev = 8 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.22 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18913 instances into 7355 LUTs, name keeping = 61%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9930
+  #lut4                  5113
+  #lut5                  2262
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9930   out of  19600   50.66%
+#reg                     9204   out of  19600   46.96%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7375    |2555    |9234    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |343     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |289     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |131     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |275     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2291    |738     |1950    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2221    |691     |1768    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2064    |615     |1422    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |52      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1447    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |264     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1054    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |385     |158     |189     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |162     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |222     |13      |57      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2303    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2233    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1891    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1443    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1049    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |214     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |184     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |30      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9204 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  55.897892s wall, 55.515625s user + 0.390625s system = 55.906250s CPU (100.0%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 380 MB, peak memory is 702 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.559079s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (174.4%)
+
+RUN-1004 : used memory is 434 MB, reserved memory is 424 MB, peak memory is 702 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_103910.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_104933.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_104933.log
new file mode 100644
index 0000000..b4dd2b9
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_104933.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 10:49:33 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.119415s wall, 1.031250s user + 0.078125s system = 1.109375s CPU (99.1%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 175 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54824/19216 useful/useless nets, 20710/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38313 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 43384/8976 useful/useless nets, 11021/4743 useful/useless insts
+SYN-1016 : Merged 1875 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41061/359 useful/useless nets, 38259/553 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3980 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6292 instances.
+SYN-1015 : Optimize round 1, 30845 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26246/1545 useful/useless nets, 23536/7610 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9452 better
+SYN-1032 : 25997/80 useful/useless nets, 23319/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25904/93 useful/useless nets, 23237/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25626/20 useful/useless nets, 22975/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.706738s wall, 16.421875s user + 2.281250s system = 18.703125s CPU (100.0%)
+
+RUN-1004 : used memory is 337 MB, reserved memory is 306 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14404
+  #and                   2481
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    471
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9544
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4854   |9550   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1849   |2160   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1805   |1978   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1550   |1632   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |61     |1233   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |28     |426    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |122    |189    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |51     |57     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1808   |2146   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1766   |1964   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1512   |1618   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |61     |1233   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |28     |426    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.110190s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (156.2%)
+
+RUN-1004 : used memory is 346 MB, reserved memory is 316 MB, peak memory is 405 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25660/24 useful/useless nets, 23024/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25978/670 useful/useless nets, 23358/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 311 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29408/338 useful/useless nets, 26789/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36952/296 useful/useless nets, 34227/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 123516, tnet num: 36954, tinst num: 34227, tnode num: 158863, tedge num: 181911.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.289336s wall, 1.250000s user + 0.031250s system = 1.281250s CPU (99.4%)
+
+RUN-1004 : used memory is 525 MB, reserved memory is 501 MB, peak memory is 525 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36954 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7466 (3.86), #lev = 9 (3.12)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7293 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.23 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18915 instances into 7321 LUTs, name keeping = 61%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9896
+  #lut4                  5032
+  #lut5                  2309
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9896   out of  19600   50.49%
+#reg                     9624   out of  19600   49.10%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7341    |2555    |9654    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |286     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |90      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2282    |738     |2160    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2212    |691     |1978    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2056    |615     |1632    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |52      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1440    |422     |1233    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |266     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1045    |0       |426     |0       |0       |
+|        read_ram_i            |read_ram             |384     |158     |189     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |219     |13      |57      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |127     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2303    |751     |2146    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2233    |704     |1964    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1889    |628     |1618    |22      |1       |
+|        channelPart           |channel_part_8478    |147     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1443    |422     |1233    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1049    |0       |426     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9624 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  58.907898s wall, 58.640625s user + 0.281250s system = 58.921875s CPU (100.0%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 383 MB, peak memory is 709 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.565135s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (174.7%)
+
+RUN-1004 : used memory is 435 MB, reserved memory is 420 MB, peak memory is 709 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_104933.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_110141.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_110141.log
new file mode 100644
index 0000000..55cd321
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_110141.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:01:41 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(123)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.081049s wall, 1.000000s user + 0.078125s system = 1.078125s CPU (99.7%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 170 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54820/19216 useful/useless nets, 20706/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 43368/8986 useful/useless nets, 11015/4743 useful/useless insts
+SYN-1016 : Merged 1904 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41025/359 useful/useless nets, 38223/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3980 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6292 instances.
+SYN-1015 : Optimize round 1, 30809 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26228/1545 useful/useless nets, 23518/7610 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9452 better
+SYN-1032 : 25979/80 useful/useless nets, 23301/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25886/93 useful/useless nets, 23219/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25608/20 useful/useless nets, 22957/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.978293s wall, 16.578125s user + 2.406250s system = 18.984375s CPU (100.0%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 305 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14386
+  #and                   2481
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9528
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4852   |9534   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1848   |2152   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1804   |1970   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1549   |1624   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1225   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |122    |189    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |51     |57     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |2138   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1956   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1610   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1225   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.068364s wall, 1.765625s user + 0.000000s system = 1.765625s CPU (165.3%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 304 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25642/24 useful/useless nets, 23006/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25960/670 useful/useless nets, 23340/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 311 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29390/338 useful/useless nets, 26771/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36934/296 useful/useless nets, 34209/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 123466, tnet num: 36936, tinst num: 34209, tnode num: 158763, tedge num: 181847.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.288517s wall, 1.203125s user + 0.093750s system = 1.296875s CPU (100.6%)
+
+RUN-1004 : used memory is 524 MB, reserved memory is 501 MB, peak memory is 524 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36936 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7360 (3.96), #lev = 9 (2.90)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7232 (3.98), #lev = 7 (2.74)
+SYN-3001 : Logic optimization runtime opt =   1.23 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18913 instances into 7260 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9835
+  #lut4                  5144
+  #lut5                  2136
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9835   out of  19600   50.18%
+#reg                     9608   out of  19600   49.02%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7280    |2555    |9638    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |124     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2246    |738     |2152    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2176    |691     |1970    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2019    |615     |1624    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |52      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1410    |422     |1225    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |124     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |841     |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |377     |158     |189     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |212     |13      |57      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2274    |751     |2138    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2204    |704     |1956    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1863    |628     |1610    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1410    |422     |1225    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |124     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |841     |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |219     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |38      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9608 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  56.849114s wall, 56.421875s user + 0.406250s system = 56.828125s CPU (100.0%)
+
+RUN-1004 : used memory is 400 MB, reserved memory is 390 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.576405s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (172.5%)
+
+RUN-1004 : used memory is 407 MB, reserved memory is 389 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_110141.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_111006.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_111006.log
new file mode 100644
index 0000000..0ca3160
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_111006.log
@@ -0,0 +1,426 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:10:06 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-5007 WARNING: data object 'ram_data_tmp' is already declared in ../../../../hg_mp/fe/ram_switch.v(99)
+HDL-1007 : previous declaration of 'ram_data_tmp' is from here in ../../../../hg_mp/fe/ram_switch.v(52)
+HDL-5007 WARNING: second declaration of 'ram_data_tmp' is ignored in ../../../../hg_mp/fe/ram_switch.v(99)
+HDL-5007 WARNING: data object 'ram_addr_tmp' is already declared in ../../../../hg_mp/fe/ram_switch.v(100)
+HDL-1007 : previous declaration of 'ram_addr_tmp' is from here in ../../../../hg_mp/fe/ram_switch.v(53)
+HDL-5007 WARNING: second declaration of 'ram_addr_tmp' is ignored in ../../../../hg_mp/fe/ram_switch.v(100)
+HDL-5007 WARNING: data object 'ram_en_tmp' is already declared in ../../../../hg_mp/fe/ram_switch.v(101)
+HDL-1007 : previous declaration of 'ram_en_tmp' is from here in ../../../../hg_mp/fe/ram_switch.v(54)
+HDL-5007 WARNING: second declaration of 'ram_en_tmp' is ignored in ../../../../hg_mp/fe/ram_switch.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(139)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-8007 ERROR: net 'ram_data_tmp[87]' is constantly driven from multiple places in ../../../../hg_mp/fe/ram_switch.v(143)
+HDL-8007 ERROR: found another driver here in ../../../../hg_mp/fe/ram_switch.v(168)
+HDL-1007 : module 'ram_switch' remains a black box due to errors in its contents in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_111006.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_111103.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_111103.log
new file mode 100644
index 0000000..bbbc469
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_111103.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:11:03 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(139)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.066958s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (99.6%)
+
+RUN-1004 : used memory is 201 MB, reserved memory is 176 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55656/19216 useful/useless nets, 20718/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 44209/8981 useful/useless nets, 11032/4738 useful/useless insts
+SYN-1016 : Merged 1904 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41866/359 useful/useless nets, 39064/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3980 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6292 instances.
+SYN-1015 : Optimize round 1, 31645 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 26651/1545 useful/useless nets, 23941/7610 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9452 better
+SYN-1032 : 26402/80 useful/useless nets, 23724/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 26309/93 useful/useless nets, 23642/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 26031/20 useful/useless nets, 23380/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  20.231701s wall, 17.031250s user + 2.515625s system = 19.546875s CPU (96.6%)
+
+RUN-1004 : used memory is 338 MB, reserved memory is 308 MB, peak memory is 358 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14809
+  #and                   2486
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9946
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4857   |9952   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1848   |2361   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1804   |2179   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1549   |1833   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1434   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |122    |189    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |51     |57     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1812   |2347   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1770   |2165   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1516   |1819   |119    |
+|        channelPart           |channel_part_8478    |870    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1434   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.125447s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (155.5%)
+
+RUN-1004 : used memory is 332 MB, reserved memory is 302 MB, peak memory is 406 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 26065/24 useful/useless nets, 23429/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 26383/670 useful/useless nets, 23763/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 311 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29813/338 useful/useless nets, 27194/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 37357/296 useful/useless nets, 34632/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 125153, tnet num: 37359, tinst num: 34632, tnode num: 161704, tedge num: 184375.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.309760s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (99.0%)
+
+RUN-1004 : used memory is 528 MB, reserved memory is 506 MB, peak memory is 528 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 37359 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7364 (3.96), #lev = 9 (2.90)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7246 (3.97), #lev = 7 (2.75)
+SYN-3001 : Logic optimization runtime opt =   1.30 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18918 instances into 7274 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9849
+  #lut4                  5171
+  #lut5                  2123
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9849   out of  19600   50.25%
+#reg                    10026   out of  19600   51.15%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7294    |2555    |10056   |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |9       |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |287     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |100     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |129     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2249    |738     |2361    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2179    |691     |2179    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2020    |615     |1833    |22      |0       |
+|        channelPart           |channel_part_8478    |147     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |52      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1410    |422     |1434    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |124     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |841     |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |377     |158     |189     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |160     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |216     |13      |57      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |130     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2276    |751     |2347    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2206    |704     |2165    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1861    |628     |1819    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1410    |422     |1434    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |124     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |12      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |841     |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |217     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |184     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |33      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 10026 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  60.178704s wall, 59.500000s user + 0.390625s system = 59.890625s CPU (99.5%)
+
+RUN-1004 : used memory is 403 MB, reserved memory is 391 MB, peak memory is 708 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.584822s wall, 2.671875s user + 0.078125s system = 2.750000s CPU (173.5%)
+
+RUN-1004 : used memory is 411 MB, reserved memory is 392 MB, peak memory is 708 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_111103.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_112717.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_112717.log
new file mode 100644
index 0000000..6e64dec
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_112717.log
@@ -0,0 +1,1871 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:27:18 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.089324s wall, 1.078125s user + 0.015625s system = 1.093750s CPU (100.4%)
+
+RUN-1004 : used memory is 201 MB, reserved memory is 169 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54001/19216 useful/useless nets, 20717/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42531/8980 useful/useless nets, 11002/4743 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40200/362 useful/useless nets, 37401/553 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3969 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6378 instances.
+SYN-1015 : Optimize round 1, 30063 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25885/1556 useful/useless nets, 23178/7559 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9439 better
+SYN-1032 : 25644/80 useful/useless nets, 22969/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25551/93 useful/useless nets, 22887/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25273/20 useful/useless nets, 22625/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.555981s wall, 16.546875s user + 1.781250s system = 18.328125s CPU (98.8%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 305 MB, peak memory is 356 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14063
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9129
+  #LATCH                    6
+#MACRO_ADD                498
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9135   |800    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1925   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.062811s wall, 1.687500s user + 0.062500s system = 1.750000s CPU (164.7%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 405 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25307/24 useful/useless nets, 22674/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25625/670 useful/useless nets, 23008/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 311 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29156/338 useful/useless nets, 26540/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1800 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 499 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11786 instances.
+SYN-1032 : 36462/296 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121358, tnet num: 36464, tinst num: 33740, tnode num: 155430, tedge num: 178539.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.274109s wall, 1.218750s user + 0.062500s system = 1.281250s CPU (100.6%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 495 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36464 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7558 (3.97), #lev = 10 (3.00)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7451 (3.99), #lev = 8 (2.88)
+SYN-3001 : Logic optimization runtime opt =   1.27 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18838 instances into 7479 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10059
+  #lut4                  5170
+  #lut5                  2329
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2560
+
+Utilization Statistics
+#lut                    10059   out of  19600   51.32%
+#reg                     9209   out of  19600   46.98%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7499    |2560    |9239    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |295     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |139     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |291     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |89      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |144     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2346    |738     |1925    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2276    |691     |1743    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1934    |615     |1397    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1509    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |154     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |192     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2362    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2291    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1950    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1507    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |150     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |15      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1092    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9209 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1276 adder to BLE ...
+SYN-4008 : Packed 1276 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  58.991899s wall, 58.687500s user + 0.296875s system = 58.984375s CPU (100.0%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 389 MB, peak memory is 703 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.562122s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (174.0%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 385 MB, peak memory is 703 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_112717.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_112950.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_112950.log
new file mode 100644
index 0000000..c239de7
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_112950.log
@@ -0,0 +1,1869 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:29:50 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.060302s wall, 1.046875s user + 0.015625s system = 1.062500s CPU (100.2%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 171 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54001/19216 useful/useless nets, 20717/1835 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42531/8980 useful/useless nets, 11002/4743 useful/useless insts
+SYN-1016 : Merged 1884 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40200/362 useful/useless nets, 37401/553 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3969 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6378 instances.
+SYN-1015 : Optimize round 1, 30063 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25885/1556 useful/useless nets, 23178/7559 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9439 better
+SYN-1032 : 25644/80 useful/useless nets, 22969/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25551/93 useful/useless nets, 22887/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25273/20 useful/useless nets, 22625/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.315966s wall, 16.390625s user + 1.921875s system = 18.312500s CPU (100.0%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14063
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9129
+  #LATCH                    6
+#MACRO_ADD                498
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9135   |800    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1925   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.037579s wall, 1.687500s user + 0.000000s system = 1.687500s CPU (162.6%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 314 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25307/24 useful/useless nets, 22674/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25625/670 useful/useless nets, 23008/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 311 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29156/338 useful/useless nets, 26540/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1800 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 499 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11786 instances.
+SYN-1032 : 36462/296 useful/useless nets, 33740/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121358, tnet num: 36464, tinst num: 33740, tnode num: 155430, tedge num: 178539.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.288548s wall, 1.234375s user + 0.046875s system = 1.281250s CPU (99.4%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 495 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36464 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7558 (3.97), #lev = 10 (3.00)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7451 (3.99), #lev = 8 (2.88)
+SYN-3001 : Logic optimization runtime opt =   1.24 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18838 instances into 7479 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10059
+  #lut4                  5170
+  #lut5                  2329
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2560
+
+Utilization Statistics
+#lut                    10059   out of  19600   51.32%
+#reg                     9209   out of  19600   46.98%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7499    |2560    |9239    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |295     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |139     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |291     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |89      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |144     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2346    |738     |1925    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2276    |691     |1743    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1934    |615     |1397    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1509    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |154     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |192     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2362    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2291    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1950    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1507    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |150     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |15      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1092    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9209 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1276 adder to BLE ...
+SYN-4008 : Packed 1276 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  59.183292s wall, 58.765625s user + 0.281250s system = 59.046875s CPU (99.8%)
+
+RUN-1004 : used memory is 398 MB, reserved memory is 388 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.575236s wall, 2.671875s user + 0.046875s system = 2.718750s CPU (172.6%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 384 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_112950.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_114359.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_114359.log
new file mode 100644
index 0000000..4b5b0d9
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_114359.log
@@ -0,0 +1,1875 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:43:59 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(211)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.075788s wall, 1.000000s user + 0.062500s system = 1.062500s CPU (98.8%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 173 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54152/19184 useful/useless nets, 20748/1819 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42660/8988 useful/useless nets, 11019/4743 useful/useless insts
+SYN-1016 : Merged 2071 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(368) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40195/362 useful/useless nets, 37396/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3941 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6294 instances.
+SYN-1015 : Optimize round 1, 29982 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25899/1550 useful/useless nets, 23192/7537 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9419 better
+SYN-1032 : 25652/83 useful/useless nets, 22979/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25557/95 useful/useless nets, 22896/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25279/20 useful/useless nets, 22634/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  22.728062s wall, 17.796875s user + 1.515625s system = 19.312500s CPU (85.0%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14068
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9134
+  #LATCH                    6
+#MACRO_ADD                500
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9140   |804    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.194439s wall, 1.843750s user + 0.000000s system = 1.843750s CPU (154.4%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 301 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25313/24 useful/useless nets, 22683/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25631/670 useful/useless nets, 23017/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29183/338 useful/useless nets, 26572/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1809 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 500 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11787 instances.
+SYN-1032 : 36482/297 useful/useless nets, 33765/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121412, tnet num: 36484, tinst num: 33765, tnode num: 155488, tedge num: 178591.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.296816s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (100.0%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 493 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36484 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7584 (3.97), #lev = 9 (2.97)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7464 (3.99), #lev = 9 (2.93)
+SYN-3001 : Logic optimization runtime opt =   1.29 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18870 instances into 7492 LUTs, name keeping = 59%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10060
+  #lut4                  5124
+  #lut5                  2388
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2548
+
+Utilization Statistics
+#lut                    10060   out of  19600   51.33%
+#reg                     9214   out of  19600   47.01%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7512    |2548    |9244    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |343     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |296     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |101     |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |137     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |287     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |92      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |137     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2342    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |46      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2260    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1918    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1496    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |140     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1091    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |189     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |161     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |27      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2351    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2280    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1940    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1496    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |140     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1091    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |211     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |183     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9214 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1265 adder to BLE ...
+SYN-4008 : Packed 1265 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  62.525136s wall, 62.156250s user + 0.234375s system = 62.390625s CPU (99.8%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 381 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.551636s wall, 2.718750s user + 0.046875s system = 2.765625s CPU (178.2%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 385 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_114359.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_115139.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_115139.log
new file mode 100644
index 0000000..d1788f1
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_115139.log
@@ -0,0 +1,1881 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:51:39 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(211)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.058297s wall, 1.000000s user + 0.062500s system = 1.062500s CPU (100.4%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 174 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54233/19175 useful/useless nets, 20838/1801 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42723/8988 useful/useless nets, 11091/4743 useful/useless insts
+SYN-1016 : Merged 2071 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(368) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40258/362 useful/useless nets, 37468/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3941 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6294 instances.
+SYN-1015 : Optimize round 1, 29982 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25962/1550 useful/useless nets, 23264/7537 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9419 better
+SYN-1032 : 25715/83 useful/useless nets, 23051/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25620/95 useful/useless nets, 22968/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25342/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.179137s wall, 16.718750s user + 1.468750s system = 18.187500s CPU (100.0%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 305 MB, peak memory is 356 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14068
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9134
+  #LATCH                    6
+#MACRO_ADD                500
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9140   |804    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.097657s wall, 1.687500s user + 0.015625s system = 1.703125s CPU (155.2%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 300 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25376/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25694/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29246/338 useful/useless nets, 26644/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1809 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 500 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11787 instances.
+SYN-1032 : 36545/297 useful/useless nets, 33837/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121556, tnet num: 36547, tinst num: 33837, tnode num: 155776, tedge num: 178870.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.300600s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (100.9%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 495 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7567 (3.97), #lev = 9 (2.98)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7484 (3.99), #lev = 8 (2.89)
+SYN-3001 : Logic optimization runtime opt =   1.34 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18870 instances into 7512 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10080
+  #lut4                  5192
+  #lut5                  2340
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2548
+
+Utilization Statistics
+#lut                    10080   out of  19600   51.43%
+#reg                     9214   out of  19600   47.01%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7532    |2548    |9244    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |295     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |139     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |290     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |141     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2362    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |46      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2280    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1937    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1510    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1093    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |163     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2362    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2291    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1950    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1507    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9214 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1265 adder to BLE ...
+SYN-4008 : Packed 1265 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  58.854285s wall, 58.593750s user + 0.250000s system = 58.843750s CPU (100.0%)
+
+RUN-1004 : used memory is 398 MB, reserved memory is 385 MB, peak memory is 703 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.569114s wall, 2.703125s user + 0.031250s system = 2.734375s CPU (174.3%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 388 MB, peak memory is 703 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_115139.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_120058.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_120058.log
new file mode 100644
index 0000000..eb62d34
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_120058.log
@@ -0,0 +1,1881 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 12:00:58 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(211)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.058450s wall, 1.000000s user + 0.062500s system = 1.062500s CPU (100.4%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 172 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54233/19175 useful/useless nets, 20838/1801 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42723/8988 useful/useless nets, 11091/4743 useful/useless insts
+SYN-1016 : Merged 2071 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(368) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40258/362 useful/useless nets, 37468/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3941 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6294 instances.
+SYN-1015 : Optimize round 1, 29982 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25962/1550 useful/useless nets, 23264/7537 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9419 better
+SYN-1032 : 25715/83 useful/useless nets, 23051/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25620/95 useful/useless nets, 22968/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25342/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.587842s wall, 16.078125s user + 2.500000s system = 18.578125s CPU (99.9%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 357 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14068
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9134
+  #LATCH                    6
+#MACRO_ADD                500
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9140   |804    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.095573s wall, 1.671875s user + 0.015625s system = 1.687500s CPU (154.0%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 301 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25376/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25694/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29246/338 useful/useless nets, 26644/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1809 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 500 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11787 instances.
+SYN-1032 : 36545/297 useful/useless nets, 33837/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121556, tnet num: 36547, tinst num: 33837, tnode num: 155776, tedge num: 178870.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.275137s wall, 1.281250s user + 0.000000s system = 1.281250s CPU (100.5%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 494 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7567 (3.97), #lev = 9 (2.98)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7484 (3.99), #lev = 8 (2.89)
+SYN-3001 : Logic optimization runtime opt =   1.24 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18870 instances into 7512 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10080
+  #lut4                  5192
+  #lut5                  2340
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2548
+
+Utilization Statistics
+#lut                    10080   out of  19600   51.43%
+#reg                     9214   out of  19600   47.01%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7532    |2548    |9244    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |295     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |139     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |290     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |141     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2362    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |46      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2280    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1937    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1510    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1093    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |163     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2362    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2291    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1950    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1507    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9214 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1265 adder to BLE ...
+SYN-4008 : Packed 1265 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  56.978450s wall, 56.609375s user + 0.265625s system = 56.875000s CPU (99.8%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 386 MB, peak memory is 700 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.568891s wall, 2.687500s user + 0.015625s system = 2.703125s CPU (172.3%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 385 MB, peak memory is 700 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_120058.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_133804.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_133804.log
new file mode 100644
index 0000000..f237562
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_133804.log
@@ -0,0 +1,1881 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:38:04 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(211)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.067369s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (99.5%)
+
+RUN-1004 : used memory is 201 MB, reserved memory is 171 MB, peak memory is 242 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54233/19175 useful/useless nets, 20838/1801 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42723/8988 useful/useless nets, 11091/4743 useful/useless insts
+SYN-1016 : Merged 2071 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(368) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40258/362 useful/useless nets, 37468/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3941 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6294 instances.
+SYN-1015 : Optimize round 1, 29982 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25962/1550 useful/useless nets, 23264/7537 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9419 better
+SYN-1032 : 25715/83 useful/useless nets, 23051/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25620/95 useful/useless nets, 22968/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25342/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.249368s wall, 16.640625s user + 1.593750s system = 18.234375s CPU (99.9%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 356 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14068
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9134
+  #LATCH                    6
+#MACRO_ADD                500
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9140   |804    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.100499s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (156.2%)
+
+RUN-1004 : used memory is 330 MB, reserved memory is 300 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25376/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25694/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29246/338 useful/useless nets, 26644/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1809 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 500 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11787 instances.
+SYN-1032 : 36545/297 useful/useless nets, 33837/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121556, tnet num: 36547, tinst num: 33837, tnode num: 155776, tedge num: 178870.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.273688s wall, 1.265625s user + 0.015625s system = 1.281250s CPU (100.6%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 494 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 8 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7567 (3.97), #lev = 9 (2.98)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7484 (3.99), #lev = 8 (2.89)
+SYN-3001 : Logic optimization runtime opt =   1.26 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18870 instances into 7512 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10080
+  #lut4                  5192
+  #lut5                  2340
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2548
+
+Utilization Statistics
+#lut                    10080   out of  19600   51.43%
+#reg                     9214   out of  19600   47.01%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7532    |2548    |9244    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |295     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |139     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |290     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |141     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2362    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |46      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2280    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1937    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1510    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1093    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |163     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2362    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2291    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1950    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1507    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9214 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1265 adder to BLE ...
+SYN-4008 : Packed 1265 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  57.550688s wall, 57.140625s user + 0.359375s system = 57.500000s CPU (99.9%)
+
+RUN-1004 : used memory is 398 MB, reserved memory is 388 MB, peak memory is 702 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.562888s wall, 2.718750s user + 0.000000s system = 2.718750s CPU (174.0%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 387 MB, peak memory is 702 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_133804.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_134530.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_134530.log
new file mode 100644
index 0000000..daf79de
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_134530.log
@@ -0,0 +1,1899 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:45:30 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(211)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.094354s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (98.5%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 172 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54233/19175 useful/useless nets, 20838/1801 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42723/8988 useful/useless nets, 11091/4743 useful/useless insts
+SYN-1016 : Merged 2071 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(368) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40258/362 useful/useless nets, 37468/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3941 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6294 instances.
+SYN-1015 : Optimize round 1, 29982 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25962/1550 useful/useless nets, 23264/7537 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9419 better
+SYN-1032 : 25715/83 useful/useless nets, 23051/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25620/95 useful/useless nets, 22968/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25342/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.397319s wall, 16.937500s user + 1.453125s system = 18.390625s CPU (100.0%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14068
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9134
+  #LATCH                    6
+#MACRO_ADD                500
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9140   |804    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.104263s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (157.1%)
+
+RUN-1004 : used memory is 331 MB, reserved memory is 301 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25376/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25694/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29246/338 useful/useless nets, 26644/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1809 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 500 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11787 instances.
+SYN-1032 : 36545/297 useful/useless nets, 33837/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121556, tnet num: 36547, tinst num: 33837, tnode num: 155776, tedge num: 178870.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.304103s wall, 1.296875s user + 0.015625s system = 1.312500s CPU (100.6%)
+
+RUN-1004 : used memory is 518 MB, reserved memory is 494 MB, peak memory is 518 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36547 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7567 (3.97), #lev = 9 (2.98)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7484 (3.99), #lev = 8 (2.89)
+SYN-3001 : Logic optimization runtime opt =   1.25 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18870 instances into 7512 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10080
+  #lut4                  5192
+  #lut5                  2340
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2548
+
+Utilization Statistics
+#lut                    10080   out of  19600   51.43%
+#reg                     9214   out of  19600   47.01%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7532    |2548    |9244    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |295     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |139     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |290     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |141     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2362    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |46      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2280    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1937    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1510    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1093    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |163     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2362    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2291    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1950    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1507    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9214 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1265 adder to BLE ...
+SYN-4008 : Packed 1265 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  60.587158s wall, 60.062500s user + 0.312500s system = 60.375000s CPU (99.6%)
+
+RUN-1004 : used memory is 395 MB, reserved memory is 374 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.565318s wall, 2.671875s user + 0.000000s system = 2.671875s CPU (170.7%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 386 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_134530.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_134830.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_134830.log
new file mode 100644
index 0000000..646dc61
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_134830.log
@@ -0,0 +1,1899 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:48:30 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=8,CLKC1_DIV=4,CLKC2_DIV=2,CLKC3_DIV=2,CLKC4_DIV=24,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=4,CLKC0_CPHASE=7,CLKC1_CPHASE=3,CLKC4_CPHASE=23,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(211)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_36M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.062128s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (100.0%)
+
+RUN-1004 : used memory is 201 MB, reserved memory is 173 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54251/19166 useful/useless nets, 20839/1801 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42741/8988 useful/useless nets, 11092/4743 useful/useless insts
+SYN-1016 : Merged 2071 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(368) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40276/362 useful/useless nets, 37477/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg1_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 288 onehot mux instances.
+SYN-1020 : Optimized 3941 distributor mux.
+SYN-1001 : Optimize 13 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6294 instances.
+SYN-1015 : Optimize round 1, 29982 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25971/1550 useful/useless nets, 23264/7537 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 16 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9419 better
+SYN-1032 : 25724/83 useful/useless nets, 23051/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25629/95 useful/useless nets, 22968/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25351/20 useful/useless nets, 22706/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.221100s wall, 16.937500s user + 1.281250s system = 18.218750s CPU (100.0%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 305 MB, peak memory is 356 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14068
+  #and                   2499
+  #nand                     0
+  #or                    1128
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    472
+  #bufif1                   5
+  #MX21                   620
+  #FADD                     0
+  #DFF                   9134
+  #LATCH                    6
+#MACRO_ADD                500
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4805
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4928   |9140   |804    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.155459s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (148.8%)
+
+RUN-1004 : used memory is 332 MB, reserved memory is 302 MB, peak memory is 405 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -6.944 -13.889 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25385/24 useful/useless nets, 22755/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25703/670 useful/useless nets, 23089/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29255/338 useful/useless nets, 26644/38 useful/useless insts
+SYN-1016 : Merged 381 instances.
+SYN-2501 : Optimize round 1, 1809 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 500 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9258 mux instances.
+SYN-1016 : Merged 11787 instances.
+SYN-1032 : 36554/297 useful/useless nets, 33837/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121556, tnet num: 36556, tinst num: 33837, tnode num: 155776, tedge num: 178879.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.283571s wall, 1.218750s user + 0.078125s system = 1.296875s CPU (101.0%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 495 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36556 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7567 (3.97), #lev = 9 (2.98)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7484 (3.99), #lev = 8 (2.89)
+SYN-3001 : Logic optimization runtime opt =   1.24 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18870 instances into 7512 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10080
+  #lut4                  5192
+  #lut5                  2340
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2548
+
+Utilization Statistics
+#lut                    10080   out of  19600   51.43%
+#reg                     9214   out of  19600   47.01%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7532    |2548    |9244    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |337     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |49      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |295     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |139     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |290     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |141     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2362    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |46      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2280    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1937    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1510    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1093    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |163     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |30      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2362    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |40      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2291    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1950    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1507    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |152     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |17      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |16      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |14      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |28      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9214 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 84 carry chain into lslice
+SYN-4007 : Packing 1265 adder to BLE ...
+SYN-4008 : Packed 1265 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  59.362188s wall, 58.953125s user + 0.359375s system = 59.312500s CPU (99.9%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 389 MB, peak memory is 703 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.584583s wall, 2.718750s user + 0.015625s system = 2.734375s CPU (172.6%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 384 MB, peak memory is 703 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_134830.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_135649.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_135649.log
new file mode 100644
index 0000000..f2b7d2f
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_135649.log
@@ -0,0 +1,1899 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:56:49 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(211)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.078159s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (100.0%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 170 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54183/19166 useful/useless nets, 20834/1801 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38315 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42677/8984 useful/useless nets, 11087/4743 useful/useless insts
+SYN-1016 : Merged 2062 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(368) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40220/359 useful/useless nets, 37418/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3927 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6184 instances.
+SYN-1015 : Optimize round 1, 29825 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25884/1539 useful/useless nets, 23174/7563 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9407 better
+SYN-1032 : 25629/83 useful/useless nets, 22953/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25534/95 useful/useless nets, 22870/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25256/20 useful/useless nets, 22608/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.830118s wall, 16.625000s user + 2.187500s system = 18.812500s CPU (99.9%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13961
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9104
+  #LATCH                    6
+#MACRO_ADD                499
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9110   |803    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.073521s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (163.0%)
+
+RUN-1004 : used memory is 345 MB, reserved memory is 315 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25290/24 useful/useless nets, 22657/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25608/670 useful/useless nets, 22991/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29059/338 useful/useless nets, 26445/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1783 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 499 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12106 instances.
+SYN-1032 : 36596/297 useful/useless nets, 33876/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121927, tnet num: 36598, tinst num: 33876, tnode num: 156087, tedge num: 179573.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.298850s wall, 1.265625s user + 0.031250s system = 1.296875s CPU (99.8%)
+
+RUN-1004 : used memory is 522 MB, reserved memory is 497 MB, peak memory is 522 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36598 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7507 (3.85), #lev = 9 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7378 (3.96), #lev = 7 (3.02)
+SYN-3001 : Logic optimization runtime opt =   1.22 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18944 instances into 7406 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9969
+  #lut4                  5291
+  #lut5                  2135
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2543
+
+Utilization Statistics
+#lut                     9969   out of  19600   50.86%
+#reg                     9184   out of  19600   46.86%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7426    |2543    |9214    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2332    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |45      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1909    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |52      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2342    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2272    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1931    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |213     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |31      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9184 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1267 adder to BLE ...
+SYN-4008 : Packed 1267 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  56.847608s wall, 56.546875s user + 0.250000s system = 56.796875s CPU (99.9%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 389 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.595534s wall, 2.750000s user + 0.046875s system = 2.796875s CPU (175.3%)
+
+RUN-1004 : used memory is 406 MB, reserved memory is 387 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_135649.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_140606.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_140606.log
new file mode 100644
index 0000000..fb4456e
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_140606.log
@@ -0,0 +1,1898 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:06:06 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.053867s wall, 1.031250s user + 0.015625s system = 1.046875s CPU (99.3%)
+
+RUN-1004 : used memory is 200 MB, reserved memory is 173 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54215/19134 useful/useless nets, 20866/1769 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38314 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42709/8984 useful/useless nets, 11088/4743 useful/useless insts
+SYN-1016 : Merged 2062 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(369) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40252/359 useful/useless nets, 37450/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3927 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6184 instances.
+SYN-1015 : Optimize round 1, 29825 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25884/1539 useful/useless nets, 23174/7563 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9407 better
+SYN-1032 : 25629/83 useful/useless nets, 22953/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25534/95 useful/useless nets, 22870/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25256/20 useful/useless nets, 22608/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.859251s wall, 16.687500s user + 2.031250s system = 18.718750s CPU (99.3%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 353 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13961
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9104
+  #LATCH                    6
+#MACRO_ADD                499
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9110   |803    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.094626s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (157.0%)
+
+RUN-1004 : used memory is 343 MB, reserved memory is 312 MB, peak memory is 402 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25290/24 useful/useless nets, 22657/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25608/670 useful/useless nets, 22991/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29059/338 useful/useless nets, 26445/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1783 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 499 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12106 instances.
+SYN-1032 : 36596/297 useful/useless nets, 33876/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121927, tnet num: 36598, tinst num: 33876, tnode num: 156087, tedge num: 179573.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.330884s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (99.8%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 497 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36598 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7507 (3.85), #lev = 9 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7378 (3.96), #lev = 7 (3.02)
+SYN-3001 : Logic optimization runtime opt =   1.22 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18944 instances into 7406 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9969
+  #lut4                  5291
+  #lut5                  2135
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2543
+
+Utilization Statistics
+#lut                     9969   out of  19600   50.86%
+#reg                     9184   out of  19600   46.86%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    17
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7426    |2543    |9214    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2332    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |45      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1909    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |52      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2342    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2272    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1931    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |213     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |31      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9184 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1267 adder to BLE ...
+SYN-4008 : Packed 1267 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  59.374751s wall, 59.125000s user + 0.234375s system = 59.359375s CPU (100.0%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 390 MB, peak memory is 705 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.554101s wall, 2.703125s user + 0.000000s system = 2.703125s CPU (173.9%)
+
+RUN-1004 : used memory is 404 MB, reserved memory is 383 MB, peak memory is 705 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_140606.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141738.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141738.log
new file mode 100644
index 0000000..5ddf893
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141738.log
@@ -0,0 +1,413 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:17:38 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: 'line_sync_a' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'line_sync_a' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5007 WARNING: 'line_sync_a' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-8007 ERROR: external reference 'line_sync_a' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_141738.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141755.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141755.log
new file mode 100644
index 0000000..5034bed
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141755.log
@@ -0,0 +1,413 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:17:55 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: 'line_snyc_a' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'line_snyc_a' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5007 WARNING: 'line_snyc_a' is not declared in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-8007 ERROR: external reference 'line_snyc_a' remains unresolved in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-1007 : module 'huagao_mipi_top' remains a black box due to errors in its contents in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_141755.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141829.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141829.log
new file mode 100644
index 0000000..896510b
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_141829.log
@@ -0,0 +1,1898 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:18:29 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(203)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1395)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1478)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.072126s wall, 1.062500s user + 0.015625s system = 1.078125s CPU (100.6%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 170 MB, peak memory is 241 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54215/19134 useful/useless nets, 20866/1769 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38314 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42709/8984 useful/useless nets, 11088/4743 useful/useless insts
+SYN-1016 : Merged 2062 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_sort/u_data_prebuffer_rev/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer_rev.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/reg20_syn_11" in ../../../../hg_mp/local_bus/ubus_top.v(369) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40252/359 useful/useless nets, 37450/554 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg20_syn_10
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3927 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6184 instances.
+SYN-1015 : Optimize round 1, 29825 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25884/1539 useful/useless nets, 23174/7563 useful/useless insts
+SYN-1017 : Remove 35 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg23_syn_10
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     sampling_fe_a/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1002 :     sampling_fe_a/reg1_syn_3
+SYN-1002 :     sampling_fe_a/reg2_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg2_syn_4
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg1_syn_4
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9407 better
+SYN-1032 : 25629/83 useful/useless nets, 22953/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 3 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25534/95 useful/useless nets, 22870/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 280 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25256/20 useful/useless nets, 22608/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.234705s wall, 16.906250s user + 1.328125s system = 18.234375s CPU (100.0%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 303 MB, peak memory is 355 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13961
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9104
+  #LATCH                    6
+#MACRO_ADD                499
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4815
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9110   |803    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1891   |271    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |134    |12     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1743   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1397   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |265    |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |89     |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.042085s wall, 1.656250s user + 0.046875s system = 1.703125s CPU (163.4%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 313 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_a_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_b_tmp[*]"
+RUN-1002 : start command "get_regs u_bus_top/start_sp_b_sync1d_48m[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25290/24 useful/useless nets, 22657/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25608/670 useful/useless nets, 22991/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 324 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 29059/338 useful/useless nets, 26445/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1783 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 499 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12106 instances.
+SYN-1032 : 36596/297 useful/useless nets, 33876/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121929, tnet num: 36598, tinst num: 33876, tnode num: 156092, tedge num: 179577.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.326785s wall, 1.312500s user + 0.015625s system = 1.328125s CPU (100.1%)
+
+RUN-1004 : used memory is 521 MB, reserved memory is 496 MB, peak memory is 521 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36598 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7507 (3.85), #lev = 9 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7378 (3.96), #lev = 7 (3.02)
+SYN-3001 : Logic optimization runtime opt =   1.22 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18944 instances into 7406 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9969
+  #lut4                  5291
+  #lut5                  2135
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2543
+
+Utilization Statistics
+#lut                     9969   out of  19600   50.86%
+#reg                     9184   out of  19600   46.86%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    18
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7426    |2543    |9215    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |284     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2332    |726     |1891    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |45      |35      |134     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2251    |691     |1743    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1909    |615     |1397    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |52      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |194     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |164     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2342    |751     |1936    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2272    |704     |1754    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1931    |628     |1408    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |213     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |182     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |31      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9184 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1267 adder to BLE ...
+SYN-4008 : Packed 1267 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  57.605930s wall, 57.171875s user + 0.421875s system = 57.593750s CPU (100.0%)
+
+RUN-1004 : used memory is 396 MB, reserved memory is 378 MB, peak memory is 703 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.553025s wall, 2.625000s user + 0.031250s system = 2.656250s CPU (171.0%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 383 MB, peak memory is 703 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_141829.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_142859.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_142859.log
new file mode 100644
index 0000000..431bc10
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_142859.log
@@ -0,0 +1,1549 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:29:00 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.051567s wall, 0.984375s user + 0.062500s system = 1.046875s CPU (99.6%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 168 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 54069/19051 useful/useless nets, 20728/1794 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38465 instances.
+SYN-1025 : Merged 25 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42633/9040 useful/useless nets, 10981/4744 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40306/363 useful/useless nets, 37503/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3983 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6318 instances.
+SYN-1015 : Optimize round 1, 30070 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25810/1547 useful/useless nets, 23099/7679 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9523 better
+SYN-1032 : 25561/80 useful/useless nets, 22882/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25468/93 useful/useless nets, 22800/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25190/20 useful/useless nets, 22538/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.446085s wall, 17.156250s user + 2.281250s system = 19.437500s CPU (100.0%)
+
+RUN-1004 : used memory is 334 MB, reserved memory is 303 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13985
+  #and                   2483
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9125
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4854   |9131   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.075710s wall, 1.750000s user + 0.000000s system = 1.750000s CPU (162.7%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 313 MB, peak memory is 403 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_bus_top/start_sp_a_tmp[*]"
+USR-8132 ERROR: No net match the pattern:  u_bus_top/start_sp_a_tmp[*].
+USR-8159 ERROR: ../../hg_anlogic.sdc Line: 31, set_false_path -from [get_nets {u_bus_top/start_sp_a_tmp[*]}] -to [get_regs {u_bus_top/start_sp_a_sync1d_48m[*]}] fails.
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_142859.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_143112.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_143112.log
new file mode 100644
index 0000000..4fb5419
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_143112.log
@@ -0,0 +1,1886 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:31:12 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.153176s wall, 1.125000s user + 0.031250s system = 1.156250s CPU (100.3%)
+
+RUN-1004 : used memory is 199 MB, reserved memory is 171 MB, peak memory is 240 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 53941/19179 useful/useless nets, 20724/1798 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38312 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 42472/8976 useful/useless nets, 10975/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 40145/363 useful/useless nets, 37342/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 29880 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  18.708725s wall, 16.468750s user + 2.250000s system = 18.718750s CPU (100.1%)
+
+RUN-1004 : used memory is 335 MB, reserved memory is 304 MB, peak memory is 354 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            13950
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9093
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 225
+#MACRO_MULT                 4
+#MACRO_MUX               4813
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.043867s wall, 1.687500s user + 0.015625s system = 1.703125s CPU (163.2%)
+
+RUN-1004 : used memory is 344 MB, reserved memory is 314 MB, peak memory is 404 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.280339s wall, 1.218750s user + 0.062500s system = 1.281250s CPU (100.1%)
+
+RUN-1004 : used memory is 519 MB, reserved memory is 495 MB, peak memory is 519 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 36489 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
+SYN-3001 : Logic optimization runtime opt =   1.20 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts              9962
+  #lut4                  5231
+  #lut5                  2176
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                     9962   out of  19600   50.83%
+#reg                     9173   out of  19600   46.80%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  59.158836s wall, 58.781250s user + 0.375000s system = 59.156250s CPU (100.0%)
+
+RUN-1004 : used memory is 397 MB, reserved memory is 383 MB, peak memory is 701 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.544869s wall, 2.671875s user + 0.031250s system = 2.703125s CPU (175.0%)
+
+RUN-1004 : used memory is 405 MB, reserved memory is 387 MB, peak memory is 701 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_143112.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_144419.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_144419.log
new file mode 100644
index 0000000..716f5eb
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_144419.log
@@ -0,0 +1,1894 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:44:19 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(596)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(959)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(356)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(357)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(366)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(367)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1415)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1498)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.100238s wall, 1.078125s user + 0.031250s system = 1.109375s CPU (100.8%)
+
+RUN-1004 : used memory is 202 MB, reserved memory is 174 MB, peak memory is 243 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :    u_O_clk_lp_p   |       true       |  cdc_sync(DEPTH=20,WIDTH...  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :    u_O_clk_lp_n   |       true       |  cdc_sync(DEPTH=20,WIDTH...  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55777/19243 useful/useless nets, 21967/1798 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38316 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 44304/8976 useful/useless nets, 12214/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41977/363 useful/useless nets, 39174/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 30452 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 27603/1547 useful/useless nets, 24892/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 27354/80 useful/useless nets, 24675/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 27261/93 useful/useless nets, 24593/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 26983/20 useful/useless nets, 24331/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.253570s wall, 16.765625s user + 2.484375s system = 19.250000s CPU (100.0%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 309 MB, peak memory is 359 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14522
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9665
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4839
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9671   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.073710s wall, 1.765625s user + 0.015625s system = 1.781250s CPU (165.9%)
+
+RUN-1004 : used memory is 349 MB, reserved memory is 319 MB, peak memory is 410 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 27017/24 useful/useless nets, 24380/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 27335/670 useful/useless nets, 24714/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 30821/338 useful/useless nets, 28201/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 38365/296 useful/useless nets, 35639/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 126687, tnet num: 38367, tinst num: 35639, tnode num: 164251, tedge num: 187234.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.315133s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (99.8%)
+
+RUN-1004 : used memory is 536 MB, reserved memory is 513 MB, peak memory is 536 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 38367 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 12 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7521 (3.86), #lev = 9 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7427 (3.95), #lev = 7 (3.06)
+SYN-3001 : Logic optimization runtime opt =   1.19 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18994 instances into 7455 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10030
+  #lut4                  5343
+  #lut5                  2132
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                    10030   out of  19600   51.17%
+#reg                     9745   out of  19600   49.72%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7475    |2555    |9777    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |283     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |93      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2334    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2264    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1922    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |206     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |173     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |32      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2334    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2264    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1925    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |206     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |180     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |26      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9745 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  69.049634s wall, 68.421875s user + 0.359375s system = 68.781250s CPU (99.6%)
+
+RUN-1004 : used memory is 410 MB, reserved memory is 399 MB, peak memory is 725 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.602960s wall, 2.765625s user + 0.000000s system = 2.765625s CPU (172.5%)
+
+RUN-1004 : used memory is 416 MB, reserved memory is 401 MB, peak memory is 725 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_144419.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_145044.log b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_145044.log
new file mode 100644
index 0000000..6648f34
--- /dev/null
+++ b/src/prj/td_project/hg_anlogic_Runs/.logs/syn_1/td_20240312_145044.log
@@ -0,0 +1,1900 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:50:44 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1002 : start command "open_project hg_anlogic.prj"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Project manager successfully analyzed 61 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
+RUN-1002 : start command "elaborate -top huagao_mipi_top"
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
+HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(596)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(959)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
+HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
+HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="24.000",REFCLK_DIV=2,FBCLK_DIV=9,CLKC0_DIV=4,CLKC1_DIV=2,CLKC4_DIV=72,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",CLKC3_ENABLE="ENABLE",CLKC4_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC3_FPHASE=2,CLKC0_CPHASE=3,CLKC4_CPHASE=71,GMC_GAIN=0,ICP_CURRENT=9,KVCO=2,LPF_CAPACITOR=2,LPF_RESISTOR=8,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-1007 : elaborate module pll_lvds in ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(24)
+HDL-1007 : elaborate module EG_PHY_PLL(FIN="48.000",CLKC0_DIV=21,CLKC1_DIV=6,CLKC2_DIV=7,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",CLKC2_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",STDBY_ENABLE="DISABLE",CLKC0_CPHASE=20,CLKC1_CPHASE=5,CLKC2_CPHASE=6,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,DPHASE_SOURCE="ENABLE",SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(930)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(131)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 1 for port 'psdown' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(147)
+HDL-1007 : elaborate module lvds_rx in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(3)
+HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
+HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
+HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(356)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(357)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(366)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(367)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
+HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
+HDL-1007 : elaborate module AD_config in ../../../../hg_mp/fe/AD_config.v(1)
+HDL-5007 WARNING: latch inferred for net 'addr[2]' in ../../../../hg_mp/fe/AD_config.v(203)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(506)
+HDL-7007 CRITICAL-WARNING: 'adc_cfg_data_d1' should be on the sensitivity list in ../../../../hg_mp/fe/AD_config.v(507)
+HDL-1007 : elaborate module gen_sp(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/gen_sp.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=24) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(95)
+HDL-1007 : port 'end_trig' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe.v(116)
+HDL-1007 : elaborate module sampling_fe(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe.v(1)
+HDL-1007 : elaborate module ad_sampling in ../../../../hg_mp/fe/ad_sampling.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(316)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'rd_done' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sort.v(345)
+HDL-1007 : elaborate module sort(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer.v(196)
+HDL-1007 : elaborate module data_prebuffer in ../../../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : elaborate module fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10) in ../../../../hg_mp/fe/fifo_adc.v(6)
+HDL-1007 : elaborate module channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1) in ../../../../hg_mp/fe/channel_part_8478.v(1)
+HDL-1007 : port 'wr_done' remains unconnected for this instance in ../../../../hg_mp/fe/ram_switch.v(107)
+HDL-1007 : elaborate module ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : elaborate module adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/adc_addr_gen.v(1)
+HDL-1007 : elaborate module ch_addr_gen(PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ch_addr_gen.v(3)
+HDL-1007 : elaborate module mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866) in ../../../../hg_mp/fe/mapping.v(1)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866) in ../../../../hg_mp/fe/link_line.v(5)
+HDL-1007 : elaborate module ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/ram_switch_state.v(1)
+HDL-1007 : elaborate module mux_e(D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=10,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module mux_e(D_WIDTH=1,D_NUM=11) in ../../../../hg_mp/fe/mux_e.v(1)
+HDL-1007 : elaborate module insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/insert.v(1)
+HDL-1007 : elaborate module read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram.v(1)
+HDL-1007 : elaborate module read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : elaborate module mux_i(I_NUM=11,O_NUM=3) in ../../../../hg_mp/fe/mux_i.v(1)
+HDL-5007 WARNING: net 'mux_sel[15][23]' does not have a driver in ../../../../hg_mp/fe/mux_i.v(14)
+HDL-1007 : elaborate module read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr.v(38)
+HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
+HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
+HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
+HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
+HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=24,DATA_WIDTH_B=24,ADDR_WIDTH_B=10,DATA_DEPTH_A=816,DATA_DEPTH_B=816,MODE="PDPW",INIT_FILE="test_200dpi.mif") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
+HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(69)
+HDL-5007 WARNING: net 'camdata[23]' does not have a driver in ../../../../hg_mp/fe/sort.v(313)
+HDL-1007 : port 'wren' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/sampling_fe_rev.v(124)
+HDL-1007 : elaborate module sampling_fe_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sampling_fe_rev.v(1)
+HDL-1007 : port 'RD_addr' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(348)
+HDL-1007 : port 'rden1' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'rden2' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'dval_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : port 'data_o' remains unconnected for this instance in ../../../../hg_mp/fe/sort_rev.v(378)
+HDL-1007 : elaborate module sort_rev(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/sort_rev.v(1)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/fe/prebuffer_rev.v(196)
+HDL-1007 : elaborate module data_prebuffer_rev in ../../../../hg_mp/fe/prebuffer_rev.v(3)
+HDL-1007 : elaborate module read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10) in ../../../../hg_mp/fe/read_ram_rev.v(1)
+HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_data_rev.v(1)
+HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
+HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
+HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
+HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
+HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
+HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
+HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
+HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
+HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
+HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
+HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
+HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
+HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1415)
+HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
+HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
+HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
+HDL-1007 : elaborate module clk_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v(3)
+HDL-1007 : elaborate module clk_hs_generate in ../../../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(3)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2l in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(130)
+HDL-1007 : elaborate module clk_lp_generate in ../../../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(3)
+HDL-1007 : elaborate module data_lane_wrapper in ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v(2)
+HDL-1007 : elaborate module data_lp_generate in ../../../../hg_mp/mipi_dphy_tx/data_lp_generate.v(3)
+HDL-1007 : elaborate module data_hs_generate in ../../../../hg_mp/mipi_dphy_tx/data_hs_generate.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=50) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-1007 : elaborate module d1024_w8_fifo in ../../../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v(14)
+HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEPTH_R=1024,F=1024,RESETMODE="SYNC",ENDIAN="BIG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(142)
+HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
+HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
+HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1498)
+HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
+HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
+HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
+HDL-1200 : Current top model is huagao_mipi_top
+HDL-1100 : Inferred 1 RAMs.
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.071047s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (100.7%)
+
+RUN-1004 : used memory is 202 MB, reserved memory is 177 MB, peak memory is 243 MB
+RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1002 : start command "read_adc ../../hg_anlogic.adc"
+RUN-1002 : start command "set_pin_assignment  O_clk_hs_p   LOCATION = P98; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_n   LOCATION = P73; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_clk_lp_p   LOCATION = P74; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[0]   LOCATION = P90; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[1]   LOCATION = P93; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[2]   LOCATION = P97; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_hs_p[3]   LOCATION = P100; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[0]   LOCATION = P62; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[1]   LOCATION = P75; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[2]   LOCATION = P77; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_n[3]   LOCATION = P81; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[0]   LOCATION = P63; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[1]   LOCATION = P76; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[2]   LOCATION = P78; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  O_data_lp_p[3]   LOCATION = P79; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = NONE; SLEWRATE = FAST; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sck   LOCATION = P52; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdi   LOCATION = P51; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sdo   LOCATION = P50; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_ad_sen   LOCATION = P53; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_clk_p   LOCATION = P31; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[0]   LOCATION = P22; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[1]   LOCATION = P26; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[2]   LOCATION = P28; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[3]   LOCATION = P37; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  a_lvds_data_p[4]   LOCATION = P42; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P49; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sck   LOCATION = P57; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdi   LOCATION = P56; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sdo   LOCATION = P55; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_ad_sen   LOCATION = P58; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_clk_p   LOCATION = P130; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[0]   LOCATION = P121; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[1]   LOCATION = P124; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[2]   LOCATION = P126; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[3]   LOCATION = P131; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_lvds_data_p[4]   LOCATION = P103; IOSTANDARD = LVDS25; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  b_sp_pad   LOCATION = P54; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  clock_source   LOCATION = P176; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  debug[0]   LOCATION = P60; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[1]   LOCATION = P61; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[2]   LOCATION = P153; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[3]   LOCATION = P155; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[4]   LOCATION = P157; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[5]   LOCATION = P158; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[6]   LOCATION = P159; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  debug[7]   LOCATION = P161; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_pin_assignment  global_reset_n   LOCATION = P174; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; "
+RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
+RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
+RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO setups legality check.
+RUN-1001 : Starting of IO vref setups legality check.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_pad has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin a_sp_sampling has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin fan_pwm has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin frame_indicator has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin gpio_trigger has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin onoff_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_in has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin paper_out has no constraint.
+USR-6010 WARNING: ADC constraints: top model pin scan_in has no constraint.
+USR-6010 Similar messages will be suppressed.
+RUN-1002 : start command "optimize_rtl"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+SYN-1012 : SanityCheck: Model "huagao_mipi_top"
+SYN-1012 : SanityCheck: Model "rgb_to_csi_pakage"
+SYN-1012 : SanityCheck: Model "crc16_24b"
+SYN-1012 : SanityCheck: Model "ecc_gen"
+SYN-1012 : SanityCheck: Model "fifo_w32_d8192"
+SYN-1012 : SanityCheck: Model "exdev_ctl(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "AD_config"
+SYN-1012 : SanityCheck: Model "gen_sp(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sampling_fe(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3)"
+SYN-1012 : SanityCheck: Model "ad_sampling"
+SYN-1012 : SanityCheck: Model "sort(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer"
+SYN-1012 : SanityCheck: Model "channel_part_8478(PBUFF_CHANNEL_NUM=9,PBUFF_LENGTH_WIDTH=10,PBUFF_AFE_NUM=1)"
+SYN-1012 : SanityCheck: Model "fifo_adc(AFE_TYPE=3,PBUFF_AFE_NUM=1,PBUFF_LENGTH_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "ram_switch(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "adc_addr_gen(PBUFF_ADDR_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "ch_addr_gen(PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "insert(PBUFF_LENGTH_WIDTH=10,PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mapping(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10,PBUFF_LENGTH_200DPI=288,PBUFF_LENGTH_300DPI=432,PBUFF_LENGTH_600DPI=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=288)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=432)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=10,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "link_line(PBUFF_CHANNEL_USED=9,PBUFF_RAM_NUM=11,WIDTH=1,LENGTH=866)"
+SYN-1012 : SanityCheck: Model "ram_switch_state(PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=10,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_e(D_WIDTH=1,D_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "mux_i(I_NUM=11,O_NUM=3)"
+SYN-1012 : SanityCheck: Model "SORT_RAM_9k"
+SYN-1012 : SanityCheck: Model "transfer_300_to_200"
+SYN-1012 : SanityCheck: Model "SORT_RAM_200DPI"
+SYN-1012 : SanityCheck: Model "sampling_fe_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "sort_rev(YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22)"
+SYN-1012 : SanityCheck: Model "data_prebuffer_rev"
+SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11,PBUFF_ADDR_WIDTH=10)"
+SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
+SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "ubus_top"
+SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
+SYN-1012 : SanityCheck: Model "CRC4_D16"
+SYN-1012 : SanityCheck: Model "uart_2dsp"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=2)"
+SYN-1012 : SanityCheck: Model "fan_ctrl"
+SYN-1012 : SanityCheck: Model "mipi_dphy_tx_wrapper"
+SYN-1012 : SanityCheck: Model "hs_tx_wrapper"
+SYN-1012 : SanityCheck: Model "data_lane_wrapper"
+SYN-1012 : SanityCheck: Model "data_hs_generate"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=50)"
+SYN-1012 : SanityCheck: Model "d1024_w8_fifo"
+SYN-1012 : SanityCheck: Model "data_lp_generate"
+SYN-1012 : SanityCheck: Model "clk_lane_wrapper"
+SYN-1012 : SanityCheck: Model "clk_hs_generate"
+SYN-1012 : SanityCheck: Model "clk_lp_generate"
+SYN-1012 : SanityCheck: Model "hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10)"
+SYN-1012 : SanityCheck: Model "lp_tx_wrapper"
+SYN-1012 : SanityCheck: Model "dphy_tx_fifo(DRAM_DEPTH=100)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=13)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=24)"
+SYN-1012 : SanityCheck: Model "pixel_cdc"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=16)"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=3,WIDTH=22)"
+SYN-1012 : SanityCheck: Model "pll"
+SYN-1012 : SanityCheck: Model "pll_lvds"
+SYN-1012 : SanityCheck: Model "lscc_sensor"
+SYN-1012 : SanityCheck: Model "lvds_rx"
+SYN-1012 : SanityCheck: Model "iddr(DEVICE="EG4")"
+SYN-1043 : Mark iddr(DEVICE="EG4") as IO macro for instance u_iddr
+SYN-1043 : Mark lvds_rx as IO macro for instance u0_iddr
+SYN-1043 : Mark pll_lvds as IO macro for instance bufg_feedback
+SYN-1043 : Mark pll as IO macro for instance bufg_feedback
+SYN-1043 : Mark clk_hs_generate as IO macro for instance O_clk_hs_p_i
+SYN-1043 : Mark clk_lane_wrapper as IO macro for instance u_clk_hs_generate
+SYN-1043 : Mark data_hs_generate as IO macro for instance O_data_hs_p_i
+SYN-1043 : Mark data_lane_wrapper as IO macro for instance u_data_hs_generate
+SYN-1043 : Mark hs_tx_wrapper as IO macro for instance [0]$u_data_lane_wrapper
+SYN-1043 : Mark mipi_dphy_tx_wrapper as IO macro for instance u_hs_tx_wrapper
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1050 : Instances selected by 'keep_hierarchy':
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :      instance     |  keep_hierarchy  |         down_module          |          file(line)          
+RUN-1001 : ------------------------------------------------------------------------------------------------
+RUN-1001 :    u_pixel_cdc    |       true       |          pixel_cdc           |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :    u_O_clk_lp_p   |       true       |  cdc_sync(DEPTH=20,WIDTH...  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :    u_O_clk_lp_n   |       true       |  cdc_sync(DEPTH=20,WIDTH...  |  ../../../../hg_mp/drx_t...  
+RUN-1001 : ------------------------------------------------------------------------------------------------
+SYN-1032 : 55777/19243 useful/useless nets, 21967/1798 useful/useless insts
+SYN-1001 : Optimize 156 less-than instances
+SYN-1016 : Merged 38316 instances.
+SYN-1025 : Merged 24 RAM ports.
+SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
+SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
+SYN-1032 : 44304/8976 useful/useless nets, 12214/4743 useful/useless insts
+SYN-1016 : Merged 1876 instances.
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_4", d: "exdev_ctl_a/u_ADconfig/addr_b[2]", q: "exdev_ctl_a/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_2", d: "exdev_ctl_b/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_b/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_3", d: "exdev_ctl_b/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_b/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_b/u_ADconfig/reg5_syn_4", d: "exdev_ctl_b/u_ADconfig/addr_b[2]", q: "exdev_ctl_b/u_ADconfig/addr[2]" // ../../../../hg_mp/fe/AD_config.v(203)
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg10_syn_2" in ../../../../hg_mp/fe/AD_config.v(29) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "exdev_ctl_a/u_ADconfig/reg4_syn_5" in ../../../../hg_mp/fe/AD_config.v(91) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_a/u_sort/u_data_prebuffer/reg4_syn_2" in ../../../../hg_mp/fe/prebuffer.v(287) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "sampling_fe_b/u_ad_sampling/reg7_syn_10" in ../../../../hg_mp/fe/ad_sampling.v(329) / pin "d"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_1" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_2" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_4" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_5" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 WARNING: Undriven pin: model "huagao_mipi_top" / inst "u_bus_top/u_local_bus_slve_cis/mux6_syn_6" in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(495) / pin "i0"
+SYN-5011 Similar messages will be suppressed.
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[11][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i11" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[12][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i12" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[13][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i13" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[14][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i14" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][23]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][22]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][21]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][20]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][19]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][18]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][17]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][16]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][15]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][14]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][13]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][12]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][11]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][10]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][9]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][8]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][7]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][6]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][5]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][4]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][3]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][2]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][1]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_data/mux_i/mux_sel[15][0]" in ../../../../hg_mp/fe/mux_i.v(14)
+SYN-5014 WARNING: the net's pin: pin "i15" in ../../../../hg_mp/fe/mux_i.v(39)
+SYN-5013 WARNING: Undriven net: model "huagao_mipi_top" / net "u_senor/clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(2)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(97)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(115)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(121)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/sensor_lane/lscc_sensor.v(28)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(33)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16)
+SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
+SYN-5014 Similar messages will be suppressed.
+SYN-5025 WARNING: Using 0 for all undriven pins and nets
+SYN-1032 : 41977/363 useful/useless nets, 39174/558 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1017 : Remove 16 const input seq instances
+SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
+SYN-1002 :     U_rgb_to_csi_pakage/reg6_syn_10
+SYN-1002 :     U_rgb_to_csi_pakage/U_ecc_gen/reg0_syn_8
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg3_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg0_syn_14
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg0_syn_14
+SYN-1002 :     u_bus_top/reg6_syn_19
+SYN-1002 :     u_bus_top/u_local_bus_slve_cis/u_uart_2dsp/reg5_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_3
+SYN-1002 :     u_senor/reg0_syn_10
+SYN-1002 :     reg16_syn_2
+SYN-1002 :     exdev_ctl_a/u_ADconfig/reg4_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_last_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_fifo_wr_en_reg
+SYN-1002 :     u_senor/reg1_syn_10
+SYN-1002 :     reg17_syn_2
+SYN-1018 : Transformed 91 mux instances.
+SYN-1019 : Optimized 127 mux instances.
+SYN-1021 : Optimized 297 onehot mux instances.
+SYN-1020 : Optimized 3951 distributor mux.
+SYN-1001 : Optimize 12 less-than instances
+SYN-1019 : Optimized 39 mux instances.
+SYN-1016 : Merged 6256 instances.
+SYN-1015 : Optimize round 1, 30452 better
+SYN-1014 : Optimize round 2
+SYN-1044 : Optimized 15 inv instances.
+SYN-1032 : 27603/1547 useful/useless nets, 24892/7583 useful/useless insts
+SYN-1017 : Remove 29 const input seq instances
+SYN-1002 :     reg18_syn_2
+SYN-1002 :     reg22_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_2
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_3
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_4
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_16
+SYN-1002 :     U_rgb_to_csi_pakage/reg18_syn_17
+SYN-1002 :     U_rgb_to_csi_pakage/reg5_syn_3
+SYN-1002 :     sampling_fe_a/u_ad_sampling/reg3_syn_15
+SYN-1002 :     sampling_fe_b/u_ad_sampling/reg3_syn_15
+SYN-1002 :     u_bus_top/reg8_syn_19
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_esc_entry_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/S_lp_tx_en_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg1_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_12
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg4_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_11
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_p_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/O_lp_tx_n_reg
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_10
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_2
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_3
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_4
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_5
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_6
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_7
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_8
+SYN-1002 :     u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper/reg0_syn_9
+SYN-1019 : Optimized 24 mux instances.
+SYN-1020 : Optimized 43 distributor mux.
+SYN-1016 : Merged 118 instances.
+SYN-1015 : Optimize round 2, 9427 better
+SYN-1032 : 27354/80 useful/useless nets, 24675/112 useful/useless insts
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3004 : Optimized 8 const0 DFF(s)
+SYN-3008 : Optimized 1 const1 DFF(s)
+SYN-3004 : Optimized 1 const0 DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3003 : Optimized 1 equivalent DFF(s)
+SYN-3004 : Optimized 2 const0 DFF(s)
+SYN-1032 : 27261/93 useful/useless nets, 24593/6 useful/useless insts
+SYN-1014 : Optimize round 1
+SYN-1019 : Optimized 228 mux instances.
+SYN-1020 : Optimized 2 distributor mux.
+SYN-1016 : Merged 3 instances.
+SYN-1015 : Optimize round 1, 279 better
+SYN-1014 : Optimize round 2
+SYN-1032 : 26983/20 useful/useless nets, 24331/2 useful/useless insts
+SYN-1015 : Optimize round 2, 2 better
+SYN-1014 : Optimize round 3
+SYN-1015 : Optimize round 3, 0 better
+RUN-1003 : finish command "optimize_rtl" in  19.481519s wall, 16.921875s user + 2.562500s system = 19.484375s CPU (100.0%)
+
+RUN-1004 : used memory is 340 MB, reserved memory is 308 MB, peak memory is 359 MB
+RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+Gate Statistics
+#Basic gates            14522
+  #and                   2480
+  #nand                     0
+  #or                    1078
+  #nor                      0
+  #xor                    204
+  #xnor                     0
+  #buf                      0
+  #not                    469
+  #bufif1                   5
+  #MX21                   615
+  #FADD                     0
+  #DFF                   9665
+  #LATCH                    6
+#MACRO_ADD                497
+#MACRO_EQ                 227
+#MACRO_MULT                 4
+#MACRO_MUX               4839
+#MACRO_OTHERS              73
+
+Report Hierarchy Area:
++----------------------------------------------------------------------------+
+|Instance                      |Module               |gates  |seq    |macros |
++----------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |4851   |9671   |801    |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
+|    U_crc16_24b               |crc16_24b            |67     |16     |0      |
+|    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |0      |0      |1      |
+|  exdev_ctl_a                 |exdev_ctl            |161    |559    |45     |
+|    u_ADconfig                |AD_config            |84     |138    |22     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  exdev_ctl_b                 |exdev_ctl            |158    |546    |41     |
+|    u_ADconfig                |AD_config            |81     |125    |18     |
+|    u_gen_sp                  |gen_sp               |76     |104    |19     |
+|  sampling_fe_a               |sampling_fe          |1847   |1919   |269    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |40     |147    |10     |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort                 |1803   |1737   |258    |
+|      rddpram_ctl             |rddpram_ctl          |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer        |data_prebuffer       |1548   |1391   |118    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram             |121    |164    |32     |
+|          read_ram_addr       |read_ram_addr        |69     |127    |22     |
+|          read_ram_data       |read_ram_data        |50     |32     |10     |
+|            mux_i             |mux_i                |0      |0      |0      |
+|          u0_rdsoft_n         |cdc_sync             |2      |5      |0      |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0      |1      |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0      |1      |
+|      u_transfer_300_to_200   |transfer_300_to_200  |215    |276    |139    |
+|        u0_soft_n             |cdc_sync             |2      |5      |0      |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0      |1      |
+|  sampling_fe_b               |sampling_fe_rev      |1807   |1936   |268    |
+|    u0_soft_n                 |cdc_sync             |2      |5      |0      |
+|    u_ad_sampling             |ad_sampling          |39     |147    |9      |
+|      u0_soft_n               |cdc_sync             |2      |5      |0      |
+|    u_sort                    |sort_rev             |1765   |1754   |258    |
+|      rddpram_ctl             |rddpram_ctl_rev      |2      |5      |0      |
+|        u0_rdsoft_n           |cdc_sync             |2      |5      |0      |
+|      u0_rdsoft_n             |cdc_sync             |2      |5      |0      |
+|      u0_wrsoft_n             |cdc_sync             |2      |5      |0      |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1511   |1408   |119    |
+|        channelPart           |channel_part_8478    |865    |144    |8      |
+|        fifo_adc              |fifo_adc             |112    |41     |4      |
+|        ram_switch            |ram_switch           |60     |1023   |52     |
+|          adc_addr_gen        |adc_addr_gen         |25     |115    |9      |
+|            [0]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [1]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [2]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [3]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [4]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [5]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [6]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [7]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|            [8]$ch_addr_gen   |ch_addr_gen          |2      |11     |1      |
+|          insert              |insert               |5      |692    |37     |
+|          mapping             |mapping              |0      |0      |0      |
+|          ram_switch_state    |ram_switch_state     |27     |216    |4      |
+|            mux_addr          |mux_e                |0      |0      |0      |
+|            mux_data          |mux_e                |0      |0      |0      |
+|            mux_valid         |mux_e                |0      |0      |0      |
+|        read_ram_i            |read_ram_rev         |90     |181    |33     |
+|          read_ram_addr       |read_ram_addr_rev    |56     |139    |23     |
+|......                        |......               |-      |-      |-      |
++----------------------------------------------------------------------------+
+
+RUN-1002 : start command "export_db hg_anlogic_rtl.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.122930s wall, 1.734375s user + 0.031250s system = 1.765625s CPU (157.2%)
+
+RUN-1004 : used memory is 336 MB, reserved memory is 306 MB, peak memory is 410 MB
+RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
+RUN-1102 : create_clock: clock name: clock_source, type: 0, period: 41666, rise: 0, fall: 20833.
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "create_clock -name a_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: a_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "create_clock -name b_lvds_clk_p -period 20.833 -waveform 0 10.417 "
+RUN-1102 : create_clock: clock name: b_lvds_clk_p, type: 0, period: 20833, rise: 0, fall: 10417.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name S_clk -source  -master_clock clock_source -edges 1 2 3 -edge_shift 0 -16.203 -32.408 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name a_pclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "create_generated_clock -name b_pclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 0 0 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x2 -source  -master_clock S_clk -phase 0 -multiply_by 2 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4 -source  -master_clock S_clk -phase 0 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "create_generated_clock -name S_clk_x4_90d -source  -master_clock S_clk -phase 90 -multiply_by 4 -duty_cycle 0.5 "
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name a_sclk -source  -master_clock a_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_clock b_lvds_clk_p -edges 1 2 3 -edge_shift 0 -7.441 -14.881 "
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2"
+RUN-1002 : start command "set_false_path -setup -from  -to "
+RUN-1002 : start command "get_regs BUSY_MIPI"
+RUN-1002 : start command "get_regs BUSY_MIPI_sync_d0"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets a_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_regs clkubus_rstn"
+RUN-1002 : start command "get_nets b_pclk_rstn"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
+RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param gate opt_area low"
+RUN-1002 : start command "set_param gate opt_timing high"
+RUN-1001 : Print Gate Property
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :          Parameters         |  Settings  |  Default Values  |  Note  
+RUN-1001 : ------------------------------------------------------------------
+RUN-1001 :         cascade_dsp         |    off     |       off        |        
+RUN-1001 :         cascade_eram        |    off     |       off        |        
+RUN-1001 :        gate_sim_model       |    off     |       off        |        
+RUN-1001 :        map_sim_model        |    off     |       off        |        
+RUN-1001 :         map_strategy        |     1      |        1         |        
+RUN-1001 :           opt_area          |    low     |      medium      |   *    
+RUN-1001 :          opt_timing         |    high    |       auto       |   *    
+RUN-1001 :         pack_effort         |   medium   |      medium      |        
+RUN-1001 :      pack_lslice_ripple     |     on     |        on        |        
+RUN-1001 :   pack_lslice_ripple_ratio  |    0.5     |       0.5        |        
+RUN-1001 :        pack_seq_in_io       |    auto    |       auto       |        
+RUN-1001 :        ph1_mux_ratio        |    1.0     |       1.0        |        
+RUN-1001 :            report           |  standard  |     standard     |        
+RUN-1001 :           retiming          |    off     |       off        |        
+RUN-1001 : ------------------------------------------------------------------
+SYN-2001 : Map 61 IOs to PADs
+SYN-1032 : 27017/24 useful/useless nets, 24380/26 useful/useless insts
+RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
+SYN-2501 : Processed 0 LOGIC_BUF instances.
+SYN-2501 : 3 BUFG to GCLK
+SYN-2541 : Logic Ram FIFO "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo"
+SYN-2512 : LOGIC BRAM "U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_415"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_a/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst"
+SYN-2512 : LOGIC BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst"
+SYN-2541 : Reading BRAM "sampling_fe_b/u_sort/u_transfer_300_to_200/u_SORT_RAM_200DPI/inst" init file "D:\huagao\huagao_anlogic_mono_lvds\huagao_mono_lvds_mode2-add_value-hualing-16m\src\hg_mp\anlogic_ip\sort_ram_200dpi\test_200dpi.mif"
+SYN-2542 : Parsing MIF init file
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2541 : Write 1024x8, read 1024x8.
+SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
+SYN-2571 : Map 4 macro multiplier
+SYN-2571 : Optimize after map_dsp, round 1
+SYN-1032 : 27335/670 useful/useless nets, 24714/580 useful/useless insts
+SYN-1016 : Merged 11 instances.
+SYN-2571 : Optimize after map_dsp, round 1, 1181 better
+SYN-2571 : Optimize after map_dsp, round 2
+SYN-2571 : Optimize after map_dsp, round 2, 0 better
+SYN-1001 : Throwback 317 control mux instances
+SYN-1001 : Convert 12 adder
+SYN-2501 : Optimize round 1
+SYN-1032 : 30821/338 useful/useless nets, 28201/38 useful/useless insts
+SYN-1016 : Merged 396 instances.
+SYN-2501 : Optimize round 1, 1774 better
+SYN-2501 : Optimize round 2
+SYN-2501 : Optimize round 2, 0 better
+SYN-2501 : Map 498 macro adder
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
+SYN-2501 : Inferred 22 ROM instances
+SYN-1019 : Optimized 9690 mux instances.
+SYN-1016 : Merged 12105 instances.
+SYN-1032 : 38365/296 useful/useless nets, 35639/0 useful/useless insts
+RUN-1002 : start command "start_timer -prepack"
+TMR-2505 : Start building timing graph for model huagao_mipi_top.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 126687, tnet num: 38367, tinst num: 35639, tnode num: 164251, tedge num: 187234.
+TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
+TMR-2501 : Timing graph initialized successfully.
+RUN-1003 : finish command "start_timer -prepack" in  1.326087s wall, 1.281250s user + 0.046875s system = 1.328125s CPU (100.2%)
+
+RUN-1004 : used memory is 536 MB, reserved memory is 512 MB, peak memory is 536 MB
+TMR-2503 : Start to update net delay, extr mode = 2.
+TMR-2504 : Update delay of 38367 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 2.
+TMR-3001 : Initiate 12 clocks from SDC.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-3003 : Constraints initiated successfully.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+SYN-3001 : Running gate level optimization.
+SYN-2581 : Mapping with K=5, #lut = 7521 (3.86), #lev = 9 (3.15)
+SYN-2551 : Post LUT mapping optimization.
+SYN-2581 : Mapping with K=5, #lut = 7427 (3.95), #lev = 7 (3.06)
+SYN-3001 : Logic optimization runtime opt =   1.25 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18994 instances into 7455 LUTs, name keeping = 58%.
+SYN-3001 : Mapper removed 2 lut buffers
+RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
+RUN-1001 : standard
+***Report Model: huagao_mipi_top Device: EG4D20EG176***
+
+IO Statistics
+#IO                        61
+  #input                   21
+  #output                  40
+  #inout                    0
+
+LUT Statistics
+#Total_luts             10030
+  #lut4                  5343
+  #lut5                  2132
+  #lut6                     0
+  #lut5_mx41                0
+  #lut4_alu1b            2555
+
+Utilization Statistics
+#lut                    10030   out of  19600   51.17%
+#reg                     9745   out of  19600   49.72%
+#le                         0
+#dsp                        3   out of     29   10.34%
+#bram                      54   out of     64   84.38%
+  #bram9k                  50
+  #fifo9k                   4
+#bram32k                    4   out of     16   25.00%
+#dram                      16
+#pad                       75   out of    130   57.69%
+  #ireg                    13
+  #oreg                    19
+  #treg                     0
+#pll                        3   out of      4   75.00%
+
+Report Hierarchy Area:
++-------------------------------------------------------------------------------------------------+
+|Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
++-------------------------------------------------------------------------------------------------+
+|top                           |huagao_mipi_top      |7475    |2555    |9777    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
+|    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |283     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |93      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2334    |738     |1919    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2264    |691     |1737    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |1922    |615     |1391    |22      |0       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |206     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |173     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |32      |13      |32      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |2334    |751     |1936    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
+|      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
+|    u_sort                    |sort_rev             |2264    |704     |1754    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1925    |628     |1408    |22      |1       |
+|        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
+|        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
+|          insert              |insert               |265     |323     |692     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |206     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |180     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |26      |26      |42      |0       |0       |
+|        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_2       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_3       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_5       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
+|......                        |......               |-       |-       |-       |-       |-       |
++-------------------------------------------------------------------------------------------------+
+
+SYN-1001 : Packing model "huagao_mipi_top" ...
+SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
+SYN-1014 : Optimize round 1
+SYN-1015 : Optimize round 1, 0 better
+SYN-4002 : Packing 9745 DFF/LATCH to SEQ ...
+SYN-4009 : Pack 83 carry chain into lslice
+SYN-4007 : Packing 1278 adder to BLE ...
+SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
+SYN-4007 : Packing 0 gate4 to BLE ...
+SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
+SYN-4012 : Packed 0 FxMUX
+SYN-4013 : Packed 16 DRAM and 4 SEQ.
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  60.377693s wall, 59.921875s user + 0.453125s system = 60.375000s CPU (100.0%)
+
+RUN-1004 : used memory is 399 MB, reserved memory is 376 MB, peak memory is 726 MB
+RUN-1002 : start command "legalize_phy_inst"
+SYN-1011 : Flatten model huagao_mipi_top
+SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
+RUN-1002 : start command "export_db hg_anlogic_gate.db"
+RUN-1001 : Exported /
+RUN-1001 : Exported flow parameters
+RUN-1001 : Exported libs
+RUN-1001 : Exported entities
+RUN-1001 : Exported ports
+RUN-1001 : Exported pins
+RUN-1001 : Exported instances
+RUN-1001 : Exported nets
+RUN-1001 : Exported buses
+RUN-1001 : Exported models
+RUN-1001 : Exported congestions
+RUN-1001 : Exported violations
+RUN-1001 : Exported timing constraints
+RUN-1001 : Exported IO constraints
+RUN-1001 : Exported Inst constraints
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.605917s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (174.2%)
+
+RUN-1004 : used memory is 415 MB, reserved memory is 399 MB, peak memory is 726 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_145044.log"
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
index 5b91233..1f12086 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.bitgen.begin.f
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="13544">
+    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="9868">
     </Process>
 </ProcessHandle>
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
index 5b91233..1f12086 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_place.begin.f
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="13544">
+    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="9868">
     </Process>
 </ProcessHandle>
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
index 5b91233..1f12086 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/.opt_route.begin.f
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="13544">
+    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="9868">
     </Process>
 </ProcessHandle>
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit
index 85c7fca..34ba510 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
index 3ebb862..8657074 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.prj
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Project Version="3" Minor="2" RunTime="2024-02-19T10:56:25.015868">
+<Project Version="3" Minor="2" RunTime="2024-03-12T14:50:44.847119">
     <Project_Created_Time></Project_Created_Time>
     <TD_Encoding>UTF-8</TD_Encoding>
     <TD_Version>5.6.71036</TD_Version>
@@ -556,6 +556,9 @@
         <BitgenProperty::GeneralOption>
             <bin>on</bin>
         </BitgenProperty::GeneralOption>
+        <PlaceProperty>
+            <opt_timing>high</opt_timing>
+        </PlaceProperty>
     </Property>
     <Device_Settings>
     </Device_Settings>
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf
index 4105502..7cc7e00 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.rbf differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_2024021_1108_soft_reset.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_2024021_1108_soft_reset.bin
deleted file mode 100644
index 2482c96..0000000
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_2024021_1108_soft_reset.bin and /dev/null differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240312.bin b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240312.bin
new file mode 100644
index 0000000..32571c4
Binary files /dev/null and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_20240312.bin differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
index 4e86c9c..5fa516d 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.area
@@ -8,12 +8,12 @@ IO Statistics
   #inout                    0
 
 Utilization Statistics
-#lut                    10273   out of  19600   52.41%
-#reg                     9368   out of  19600   47.80%
-#le                     12618
-  #lut only              3250   out of  12618   25.76%
-  #reg only              2345   out of  12618   18.58%
-  #lut&reg               7023   out of  12618   55.66%
+#lut                    10421   out of  19600   53.17%
+#reg                     9955   out of  19600   50.79%
+#le                     13076
+  #lut only              3121   out of  13076   23.87%
+  #reg only              2655   out of  13076   20.30%
+  #lut&reg               7300   out of  13076   55.83%
 #dsp                        3   out of     29   10.34%
 #bram                      54   out of     64   84.38%
   #bram9k                  50
@@ -28,17 +28,17 @@ Utilization Statistics
 
 Clock Resource Statistics
 Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
-#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1810
-#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1425
-#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1358
-#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               942
-#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    143
-#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
-#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1825
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1432
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1342
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               1235
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    140
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
 #8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
 #9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
-#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_277.f1                     3
-#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/reg10_syn_122.f1                         3
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             u_mipi_eot_min/reg1_syn_299.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_163.f0    3
 #12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
 #13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
 #14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
@@ -76,8 +76,8 @@ Detailed IO Report
   b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
      clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
     global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
-       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
-       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+       onoff_in            INPUT        P141       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
         rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
       O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
      O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
@@ -118,108 +118,109 @@ Detailed IO Report
        debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
         fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
     frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
-       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
-       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
-       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
-   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+       onoff_out          OUTPUT        P111       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P106       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P71        LVCMOS25           8            N/A        NONE    
         txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
 
 Report Hierarchy Area:
 +---------------------------------------------------------------------------------------------------------+
 |Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
 +---------------------------------------------------------------------------------------------------------+
-|top                           |huagao_mipi_top      |12618  |9246    |1027    |9400    |58      |3       |
-|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |561    |454     |23      |449     |4       |1       |
-|    U_fifo_w32_d8192          |fifo_w32_d8192       |110    |93      |4       |93      |4       |0       |
-|    U_crc16_24b               |crc16_24b            |32     |32      |0       |22      |0       |0       |
-|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |9       |0       |0       |
-|  exdev_ctl_a                 |exdev_ctl            |781    |337     |96      |583     |0       |0       |
-|    u_ADconfig                |AD_config            |191    |118     |25      |142     |0       |0       |
-|    u_gen_sp                  |gen_sp               |269    |158     |71      |120     |0       |0       |
-|  exdev_ctl_b                 |exdev_ctl            |743    |379     |96      |554     |0       |0       |
-|    u_ADconfig                |AD_config            |177    |129     |25      |125     |0       |0       |
-|    u_gen_sp                  |gen_sp               |259    |144     |71      |122     |0       |0       |
-|  sampling_fe_a               |sampling_fe          |3071   |2501    |306     |2076    |25      |0       |
-|    u0_soft_n                 |cdc_sync             |6      |6       |0       |6       |0       |0       |
-|    u_ad_sampling             |ad_sampling          |180    |137     |17      |133     |0       |0       |
-|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
-|    u_sort                    |sort                 |2855   |2346    |289     |1907    |25      |0       |
-|      rddpram_ctl             |rddpram_ctl          |2      |1       |0       |2       |0       |0       |
-|        u0_rdsoft_n           |cdc_sync             |2      |1       |0       |2       |0       |0       |
-|      u0_rdsoft_n             |cdc_sync             |9      |4       |0       |9       |0       |0       |
-|      u0_wrsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
-|      u_data_prebuffer        |data_prebuffer       |2407   |1999    |253     |1544    |22      |0       |
-|        channelPart           |channel_part_8478    |143    |136     |3       |126     |0       |0       |
-|        fifo_adc              |fifo_adc             |58     |49      |9       |41      |0       |0       |
-|        ram_switch            |ram_switch           |1870   |1532    |197     |1149    |0       |0       |
-|          adc_addr_gen        |adc_addr_gen         |247    |220     |27      |123     |0       |0       |
-|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |5       |0       |0       |
-|            [1]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |15      |0       |0       |
-|            [2]$ch_addr_gen   |ch_addr_gen          |31     |28      |3       |17      |0       |0       |
-|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
-|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
-|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
-|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
-|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |10      |0       |0       |
-|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
-|          insert              |insert               |965    |654     |170     |661     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |658    |658     |0       |365     |0       |0       |
-|        read_ram_i            |read_ram             |300    |255     |44      |195     |0       |0       |
-|          read_ram_addr       |read_ram_addr        |240    |200     |40      |155     |0       |0       |
-|          read_ram_data       |read_ram_data        |56     |51      |4       |36      |0       |0       |
-|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|top                           |huagao_mipi_top      |13076  |9394    |1027    |9987    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |544    |438     |23      |443     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |80      |4       |87      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |35     |35      |0       |24      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |779    |386     |96      |580     |0       |0       |
+|    u_ADconfig                |AD_config            |204    |138     |25      |151     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |160     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |739    |378     |96      |562     |0       |0       |
+|    u_ADconfig                |AD_config            |167    |122     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |255    |147     |71      |120     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3214   |2625    |306     |2077    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |184    |145     |17      |136     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2998   |2468    |289     |1909    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |4       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |0       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2596   |2148    |253     |1582    |22      |0       |
+|        channelPart           |channel_part_8478    |160    |155     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |39      |0       |0       |
+|        ram_switch            |ram_switch           |2024   |1637    |197     |1169    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |255    |227     |27      |113     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |10      |0       |0       |
+|          insert              |insert               |987    |628     |170     |682     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |782    |782     |0       |374     |0       |0       |
+|        read_ram_i            |read_ram             |313    |266     |44      |209     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |251    |211     |40      |166     |0       |0       |
+|          read_ram_data       |read_ram_data        |57     |51      |4       |38      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |5      |4       |0       |5       |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
 |        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_8       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
 |        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|      u_transfer_300_to_200   |transfer_300_to_200  |337    |245     |36      |283     |3       |0       |
-|        u0_soft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |326    |252     |36      |271     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1      |0       |0       |1       |0       |0       |
 |        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
-|  sampling_fe_b               |sampling_fe_rev      |3397   |2743    |349     |2088    |25      |1       |
-|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
-|    u_ad_sampling             |ad_sampling          |189    |127     |17      |147     |0       |0       |
-|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
-|    u_sort                    |sort_rev             |3178   |2597    |332     |1911    |25      |1       |
-|      rddpram_ctl             |rddpram_ctl_rev      |4      |4       |0       |4       |0       |0       |
-|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
-|      u0_rdsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
-|      u_data_prebuffer_rev    |data_prebuffer_rev   |2741   |2251    |290     |1561    |22      |1       |
-|        channelPart           |channel_part_8478    |243    |238     |3       |137     |0       |0       |
-|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
-|        ram_switch            |ram_switch           |2023   |1671    |197     |1132    |0       |0       |
-|          adc_addr_gen        |adc_addr_gen         |219    |192     |27      |98      |0       |0       |
-|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |6       |0       |0       |
-|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
-|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
-|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
-|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
-|            [5]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |6       |0       |0       |
-|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
-|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
-|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
-|          insert              |insert               |982    |658     |170     |674     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |822    |821     |0       |360     |0       |0       |
-|        read_ram_i            |read_ram_rev         |378    |263     |81      |214     |0       |0       |
-|          read_ram_addr       |read_ram_addr_rev    |311    |226     |73      |165     |0       |0       |
-|          read_ram_data       |read_ram_data_rev    |67     |37      |8       |49      |0       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3165   |2462    |349     |2109    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |187    |105     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2946   |2342    |332     |1929    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |5       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |5       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2485   |1993    |290     |1576    |22      |1       |
+|        channelPart           |channel_part_8478    |275    |272     |3       |151     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |1756   |1391    |197     |1140    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |198    |169     |27      |122     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |8       |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |18      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |18      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|          insert              |insert               |1012   |680     |170     |674     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |546    |542     |0       |344     |0       |0       |
+|        read_ram_i            |read_ram_rev         |363    |258     |81      |213     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |298    |218     |73      |166     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |40      |8       |47      |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
@@ -242,79 +243,81 @@ Report Hierarchy Area:
 |        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|      u_transfer_300_to_200   |transfer_300_to_200  |342    |260     |42      |277     |3       |0       |
-|        u0_soft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |348    |260     |42      |273     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1      |1       |0       |1       |0       |0       |
 |        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
-|  scan_start_diff             |scan_start_diff      |29     |29      |0       |18      |0       |0       |
-|  u0_test_en                  |cdc_sync             |3      |3       |0       |3       |0       |0       |
-|  u1_test_en                  |cdc_sync             |5      |2       |0       |5       |0       |0       |
-|  u2_test_en                  |cdc_sync             |2      |1       |0       |2       |0       |0       |
-|  u_a_pclk                    |cdc_sync             |1      |0       |0       |1       |0       |0       |
-|  u_a_sp_sampling             |cdc_sync             |3      |2       |0       |3       |0       |0       |
-|  u_a_sp_sampling_cam         |cdc_sync             |6      |4       |0       |6       |0       |0       |
+|  scan_start_diff             |scan_start_diff      |26     |26      |0       |14      |0       |0       |
+|  u0_test_en                  |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|  u1_test_en                  |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|  u2_test_en                  |cdc_sync             |4      |3       |0       |4       |0       |0       |
+|  u_O_clk_lp_n                |cdc_sync             |270    |209     |0       |269     |0       |0       |
+|  u_O_clk_lp_p                |cdc_sync             |285    |48      |0       |285     |0       |0       |
+|  u_a_pclk                    |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|  u_a_sp_sampling             |cdc_sync             |6      |6       |0       |6       |0       |0       |
+|  u_a_sp_sampling_cam         |cdc_sync             |3      |3       |0       |3       |0       |0       |
 |  u_a_sp_sampling_last        |cdc_sync             |4      |4       |0       |4       |0       |0       |
-|  u_b_pclk                    |cdc_sync             |3      |3       |0       |3       |0       |0       |
-|  u_b_sp_sampling             |cdc_sync             |2      |2       |0       |2       |0       |0       |
-|  u_b_sp_sampling_cam         |cdc_sync             |5      |5       |0       |5       |0       |0       |
-|  u_b_sp_sampling_last        |cdc_sync             |4      |4       |0       |4       |0       |0       |
-|  u_bus_top                   |ubus_top             |1333   |944     |22      |1243    |0       |0       |
-|    u_local_bus_slve_cis      |local_bus_slve_cis   |821    |667     |22      |731     |0       |0       |
-|      u_uart_2dsp             |uart_2dsp            |103    |87      |12      |64      |0       |0       |
-|  u_dpi_mode                  |cdc_sync             |5      |4       |0       |5       |0       |0       |
-|  u_eot                       |cdc_sync             |5      |4       |0       |5       |0       |0       |
-|  u_lv_en_flag                |cdc_sync             |5      |5       |0       |5       |0       |0       |
-|  u_mipi_dphy_tx_wrapper      |mipi_dphy_tx_wrapper |262    |213     |20      |209     |4       |0       |
-|    u_hs_tx_wrapper           |hs_tx_wrapper        |220    |171     |20      |184     |4       |0       |
-|      [0]$u_data_lane_wrapper |data_lane_wrapper    |110    |76      |15      |85      |1       |0       |
-|        u_data_hs_generate    |data_hs_generate     |105    |72      |15      |80      |1       |0       |
+|  u_b_pclk                    |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|  u_b_sp_sampling             |cdc_sync             |5      |2       |0       |5       |0       |0       |
+|  u_b_sp_sampling_cam         |cdc_sync             |8      |1       |0       |8       |0       |0       |
+|  u_b_sp_sampling_last        |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|  u_bus_top                   |ubus_top             |1297   |953     |22      |1222    |0       |0       |
+|    u_local_bus_slve_cis      |local_bus_slve_cis   |784    |645     |22      |709     |0       |0       |
+|      u_uart_2dsp             |uart_2dsp            |87     |72      |12      |56      |0       |0       |
+|  u_dpi_mode                  |cdc_sync             |8      |8       |0       |8       |0       |0       |
+|  u_eot                       |cdc_sync             |3      |3       |0       |3       |0       |0       |
+|  u_lv_en_flag                |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|  u_mipi_dphy_tx_wrapper      |mipi_dphy_tx_wrapper |269    |213     |20      |220     |4       |0       |
+|    u_hs_tx_wrapper           |hs_tx_wrapper        |226    |170     |20      |188     |4       |0       |
+|      [0]$u_data_lane_wrapper |data_lane_wrapper    |110    |77      |15      |85      |1       |0       |
+|        u_data_hs_generate    |data_hs_generate     |106    |73      |15      |81      |1       |0       |
 |          u_dphy_tx_fifo      |dphy_tx_fifo         |0      |0       |0       |0       |1       |0       |
 |            u_d1024_w8_fifo   |d1024_w8_fifo        |0      |0       |0       |0       |1       |0       |
-|        u_data_lp_generate    |data_lp_generate     |5      |4       |0       |5       |0       |0       |
-|      [1]$u_data_lane_wrapper |data_lane_wrapper    |28     |27      |0       |28      |1       |0       |
-|        u_data_hs_generate    |data_hs_generate     |28     |27      |0       |28      |1       |0       |
+|        u_data_lp_generate    |data_lp_generate     |4      |4       |0       |4       |0       |0       |
+|      [1]$u_data_lane_wrapper |data_lane_wrapper    |26     |15      |0       |26      |1       |0       |
+|        u_data_hs_generate    |data_hs_generate     |26     |15      |0       |26      |1       |0       |
 |          u_dphy_tx_fifo      |dphy_tx_fifo         |0      |0       |0       |0       |1       |0       |
 |            u_d1024_w8_fifo   |d1024_w8_fifo        |0      |0       |0       |0       |1       |0       |
-|      [2]$u_data_lane_wrapper |data_lane_wrapper    |31     |27      |0       |31      |1       |0       |
-|        u_data_hs_generate    |data_hs_generate     |31     |27      |0       |31      |1       |0       |
-|          u_dphy_tx_fifo      |dphy_tx_fifo         |0      |0       |0       |0       |1       |0       |
-|            u_d1024_w8_fifo   |d1024_w8_fifo        |0      |0       |0       |0       |1       |0       |
-|      [3]$u_data_lane_wrapper |data_lane_wrapper    |19     |14      |0       |19      |1       |0       |
-|        u_data_hs_generate    |data_hs_generate     |19     |14      |0       |19      |1       |0       |
-|          u_dphy_tx_fifo      |dphy_tx_fifo         |0      |0       |0       |0       |1       |0       |
-|            u_d1024_w8_fifo   |d1024_w8_fifo        |0      |0       |0       |0       |1       |0       |
-|      u_hs_tx_controler       |hs_tx_controler      |26     |21      |5       |15      |0       |0       |
-|      u_clk_lane_wrapper      |clk_lane_wrapper     |6      |6       |0       |6       |0       |0       |
-|        u_clk_lp_generate     |clk_lp_generate      |2      |2       |0       |2       |0       |0       |
+|      [2]$u_data_lane_wrapper |data_lane_wrapper    |37     |32      |0       |36      |1       |0       |
+|        u_data_hs_generate    |data_hs_generate     |37     |32      |0       |36      |1       |0       |
+|          u_dphy_tx_fifo      |dphy_tx_fifo         |2      |2       |0       |1       |1       |0       |
+|            u_d1024_w8_fifo   |d1024_w8_fifo        |2      |2       |0       |1       |1       |0       |
+|      [3]$u_data_lane_wrapper |data_lane_wrapper    |21     |19      |0       |19      |1       |0       |
+|        u_data_hs_generate    |data_hs_generate     |21     |19      |0       |19      |1       |0       |
+|          u_dphy_tx_fifo      |dphy_tx_fifo         |2      |2       |0       |1       |1       |0       |
+|            u_d1024_w8_fifo   |d1024_w8_fifo        |2      |2       |0       |1       |1       |0       |
+|      u_hs_tx_controler       |hs_tx_controler      |24     |19      |5       |14      |0       |0       |
+|      u_clk_lane_wrapper      |clk_lane_wrapper     |8      |8       |0       |8       |0       |0       |
+|        u_clk_lp_generate     |clk_lp_generate      |4      |4       |0       |4       |0       |0       |
 |        u_clk_hs_generate     |clk_hs_generate      |4      |4       |0       |4       |0       |0       |
-|  u_mipi_eot_min              |cdc_sync             |64     |39      |0       |64      |0       |0       |
-|  u_mipi_sot_min              |cdc_sync             |58     |46      |0       |58      |0       |0       |
-|  u_pic_cnt                   |cdc_sync             |108    |58      |0       |108     |0       |0       |
-|  u_pixel_cdc                 |pixel_cdc            |676    |577     |0       |676     |0       |1       |
-|    u_clk_cis_frame_num       |cdc_sync             |77     |77      |0       |77      |0       |0       |
-|    u_clk_cis_pixel_y         |cdc_sync             |71     |65      |0       |71      |0       |0       |
-|    u_clk_mipi_pixel_y        |cdc_sync             |73     |71      |0       |73      |0       |0       |
-|    u_clka_cis_total_num      |cdc_sync             |90     |76      |0       |90      |0       |0       |
-|    u_clka_mipi_total_num     |cdc_sync             |102    |87      |0       |102     |0       |0       |
-|    u_clkb_cis_total_num      |cdc_sync             |105    |92      |0       |105     |0       |0       |
-|    u_clkb_mipi_total_num     |cdc_sync             |95     |77      |0       |95      |0       |0       |
+|  u_mipi_eot_min              |cdc_sync             |60     |57      |0       |60      |0       |0       |
+|  u_mipi_sot_min              |cdc_sync             |58     |55      |0       |58      |0       |0       |
+|  u_pic_cnt                   |cdc_sync             |117    |58      |0       |117     |0       |0       |
+|  u_pixel_cdc                 |pixel_cdc            |697    |517     |0       |695     |0       |1       |
+|    u_clk_cis_frame_num       |cdc_sync             |73     |62      |0       |73      |0       |0       |
+|    u_clk_cis_pixel_y         |cdc_sync             |77     |73      |0       |75      |0       |0       |
+|    u_clk_mipi_pixel_y        |cdc_sync             |73     |67      |0       |73      |0       |0       |
+|    u_clka_cis_total_num      |cdc_sync             |100    |94      |0       |100     |0       |0       |
+|    u_clka_mipi_total_num     |cdc_sync             |101    |60      |0       |101     |0       |0       |
+|    u_clkb_cis_total_num      |cdc_sync             |108    |46      |0       |108     |0       |0       |
+|    u_clkb_mipi_total_num     |cdc_sync             |98     |66      |0       |98      |0       |0       |
 |  u_pll                       |pll                  |0      |0       |0       |0       |0       |0       |
 |  u_pll_lvds                  |pll_lvds             |0      |0       |0       |0       |0       |0       |
-|  u_softrst_done              |cdc_sync             |4      |4       |0       |4       |0       |0       |
-|  ua_lvds_rx                  |lvds_rx              |284    |208     |19      |203     |0       |0       |
-|  ub_lvds_rx                  |lvds_rx              |290    |191     |19      |211     |0       |0       |
+|  u_softrst_done              |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|  ua_lvds_rx                  |lvds_rx              |278    |194     |19      |198     |0       |0       |
+|  ub_lvds_rx                  |lvds_rx              |288    |192     |19      |209     |0       |0       |
 |  uu_pll_lvds                 |pll_lvds             |0      |0       |0       |0       |0       |0       |
 +---------------------------------------------------------------------------------------------------------+
 
 
 DataNet Average Fanout:
 
-   Index     Fanout    Nets  
-    #1         1       9907  
-    #2         2       3801  
-    #3         3       1374  
-    #4         4       579   
-    #5        5-10     1189  
-    #6       11-50     584   
-    #7       51-100     22   
-    #8        >500      1    
-  Average     2.92           
+   Index     Fanout    Nets   
+    #1         1       10415  
+    #2         2       3902   
+    #3         3       1365   
+    #4         4        552   
+    #5        5-10     1241   
+    #6       11-50      592   
+    #7       51-100     26    
+    #8        >500       1    
+  Average     2.89            
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
index d187ea2..78bbea1 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.timing
@@ -1,7 +1,7 @@
 =========================================================================================================
 Auto created by Tang Dynasty v5.6.71036
    Copyright (c) 2012-2023 Anlogic Inc.
-Mon Feb 19 10:59:58 2024
+Tue Mar 12 14:54:41 2024
 =========================================================================================================
 
 
@@ -25,20 +25,20 @@ Minimum period is 0ns
 Timing constraint:        clock: a_pclk                                                   
 Clock = a_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns
 
-6218 endpoints analyzed totally, and 103438 paths analyzed
+6154 endpoints analyzed totally, and 105576 paths analyzed
 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 12.299ns
+Minimum period is 12.828ns
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (691 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 (691 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     8.534 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk)
+ Slack (setup check):     8.005 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[1] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         12.047ns  (logic 6.702ns, net 5.345ns, 55% logic)               
- Logic Levels:            7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )                            
+ Data Path Delay:         12.648ns  (logic 6.774ns, net 5.874ns, 53% logic)               
+ Logic Levels:            7 ( LUT5=3 ADDER=2 MULT18=1 )                                   
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -46,183 +46,31 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21 (
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1]      clk2q                   0.146 r     2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.622 r     4.044      ../../../../hg_mp/fe/prebuffer.v(109)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18]                       cell (MULT18)           3.563 r     7.607
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       1.705 r     9.312                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     9.939
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     9.939                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER)            0.355 r    10.294
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net  (fanout = 1)       0.468 r    10.762                    
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4)             0.431 r    11.193
- u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.309 r    11.502      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_396.f[0]                                 cell (LUT5)             0.424 r    11.926
- u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net  (fanout = 1)       0.738 r    12.664      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_384.f[0]                                 cell (LUT5)             0.424 r    13.088
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.503 r    13.591      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21  path2reg0 (LUT5)        0.732      14.323
- Arrival time                                                                       14.323                  (7 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0]  clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.601 r     4.023      ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[23]                       cell (MULT18)           3.563 r     7.586
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net  (fanout = 1)       1.643 r     9.229                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.706 r     9.935
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     9.935                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r    10.290
+ ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.664 r    10.954                    
+ ua_lvds_rx/reg8_syn_170.f[0]                                cell (LUT5)             0.424 r    11.378
+ u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.757 r    12.135      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[1]                                 cell (LUT5)             0.424 r    12.559
+ u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net  (fanout = 1)       0.738 r    13.297      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[0]                                 cell (LUT5)             0.424 r    13.721
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.471 r    14.192      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 path2reg0               0.732      14.924
+ Arrival time                                                                       14.924                  (7 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                 20.833      22.878
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116      22.762
- clock uncertainty                                                                  -0.000      22.762
- clock recovergence pessimism                                                        0.095      22.857
- Required time                                                                      22.857            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               8.534ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     8.534 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         12.047ns  (logic 6.702ns, net 5.345ns, 55% logic)               
- Logic Levels:            7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )                            
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0]      clk2q                   0.146 r     2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net  (fanout = 4)       1.622 r     4.044      ../../../../hg_mp/fe/prebuffer.v(109)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18]                       cell (MULT18)           3.563 r     7.607
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       1.705 r     9.312                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     9.939
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     9.939                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER)            0.355 r    10.294
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net  (fanout = 1)       0.468 r    10.762                    
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4)             0.431 r    11.193
- u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.309 r    11.502      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_396.f[0]                                 cell (LUT5)             0.424 r    11.926
- u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net  (fanout = 1)       0.738 r    12.664      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_384.f[0]                                 cell (LUT5)             0.424 r    13.088
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.503 r    13.591      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21  path2reg0 (LUT5)        0.732      14.323
- Arrival time                                                                       14.323                  (7 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                 20.833      22.878
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116      22.762
- clock uncertainty                                                                  -0.000      22.762
- clock recovergence pessimism                                                        0.095      22.857
- Required time                                                                      22.857            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               8.534ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     8.534 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         12.047ns  (logic 6.702ns, net 5.345ns, 55% logic)               
- Logic Levels:            7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )                            
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1]      clk2q                   0.146 r     2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.622 r     4.044      ../../../../hg_mp/fe/prebuffer.v(109)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18]                       cell (MULT18)           3.563 r     7.607
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       1.705 r     9.312                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     9.939
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     9.939                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER)            0.355 r    10.294
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net  (fanout = 1)       0.468 r    10.762                    
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4)             0.431 r    11.193
- u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.309 r    11.502      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_396.f[0]                                 cell (LUT5)             0.424 r    11.926
- u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net  (fanout = 1)       0.738 r    12.664      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_384.f[0]                                 cell (LUT5)             0.424 r    13.088
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.503 r    13.591      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21  path2reg0 (LUT5)        0.732      14.323
- Arrival time                                                                       14.323                  (7 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                 20.833      22.878
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116      22.762
- clock uncertainty                                                                  -0.000      22.762
- clock recovergence pessimism                                                        0.095      22.857
- Required time                                                                      22.857            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               8.534ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (659 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     8.641 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         12.012ns  (logic 6.702ns, net 5.310ns, 55% logic)               
- Logic Levels:            7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )                            
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1]      clk2q                   0.146 r     2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.622 r     4.044      ../../../../hg_mp/fe/prebuffer.v(109)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18]                       cell (MULT18)           3.563 r     7.607
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       1.705 r     9.312                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     9.939
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     9.939                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER)            0.355 r    10.294
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net  (fanout = 1)       0.468 r    10.762                    
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4)             0.431 r    11.193
- u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.309 r    11.502      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_396.f[0]                                 cell (LUT5)             0.424 r    11.926
- u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net  (fanout = 1)       0.738 r    12.664      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_384.f[0]                                 cell (LUT5)             0.424 r    13.088
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.468 r    13.556      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25  path2reg0 (LUT5)        0.732      14.288
- Arrival time                                                                       14.288                  (7 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116      22.762
@@ -230,17 +78,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
  clock recovergence pessimism                                                        0.167      22.929
  Required time                                                                      22.929            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               8.641ns          
+ Slack                                                                               8.005ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     8.641 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock a_pclk)
+ Slack (setup check):     8.005 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         12.012ns  (logic 6.702ns, net 5.310ns, 55% logic)               
- Logic Levels:            7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )                            
+ Data Path Delay:         12.648ns  (logic 6.774ns, net 5.874ns, 53% logic)               
+ Logic Levels:            7 ( LUT5=3 ADDER=2 MULT18=1 )                                   
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -248,31 +96,31 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[0]      clk2q                   0.146 r     2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[12] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4]) net  (fanout = 4)       1.622 r     4.044      ../../../../hg_mp/fe/prebuffer.v(109)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18]                       cell (MULT18)           3.563 r     7.607
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       1.705 r     9.312                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     9.939
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     9.939                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER)            0.355 r    10.294
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net  (fanout = 1)       0.468 r    10.762                    
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4)             0.431 r    11.193
- u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.309 r    11.502      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_396.f[0]                                 cell (LUT5)             0.424 r    11.926
- u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net  (fanout = 1)       0.738 r    12.664      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_384.f[0]                                 cell (LUT5)             0.424 r    13.088
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.468 r    13.556      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25  path2reg0 (LUT5)        0.732      14.288
- Arrival time                                                                       14.288                  (7 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0]  clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.601 r     4.023      ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[23]                       cell (MULT18)           3.563 r     7.586
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net  (fanout = 1)       1.643 r     9.229                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.706 r     9.935
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     9.935                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r    10.290
+ ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.664 r    10.954                    
+ ua_lvds_rx/reg8_syn_170.f[0]                                cell (LUT5)             0.424 r    11.378
+ u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.757 r    12.135      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[1]                                 cell (LUT5)             0.424 r    12.559
+ u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net  (fanout = 1)       0.738 r    13.297      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[0]                                 cell (LUT5)             0.424 r    13.721
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.471 r    14.192      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 path2reg0               0.732      14.924
+ Arrival time                                                                       14.924                  (7 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116      22.762
@@ -280,17 +128,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
  clock recovergence pessimism                                                        0.167      22.929
  Required time                                                                      22.929            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               8.641ns          
+ Slack                                                                               8.005ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     8.641 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock a_pclk)
+ Slack (setup check):     8.005 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         12.012ns  (logic 6.702ns, net 5.310ns, 55% logic)               
- Logic Levels:            7 ( LUT5=3 ADDER=2 LUT4=1 MULT18=1 )                            
+ Data Path Delay:         12.648ns  (logic 6.920ns, net 5.728ns, 54% logic)               
+ Logic Levels:            7 ( LUT5=3 ADDER=2 MULT18=1 )                                   
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -298,31 +146,35 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.q[1]      clk2q                   0.146 r     2.422
- U_rgb_to_csi_pakage/mult0_syn_4.a[14] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.622 r     4.044      ../../../../hg_mp/fe/prebuffer.v(109)
- U_rgb_to_csi_pakage/mult0_syn_4.p[18]                       cell (MULT18)           3.563 r     7.607
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       1.705 r     9.312                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     9.939
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     9.939                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.f[1] cell (ADDER)            0.355 r    10.294
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6]) net  (fanout = 1)       0.468 r    10.762                    
- sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.f[0] cell (LUT4)             0.431 r    11.193
- u_pic_cnt/reg1_syn_396.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.309 r    11.502      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_396.f[0]                                 cell (LUT5)             0.424 r    11.926
- u_pic_cnt/reg1_syn_384.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239) net  (fanout = 1)       0.738 r    12.664      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pic_cnt/reg1_syn_384.f[0]                                 cell (LUT5)             0.424 r    13.088
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.468 r    13.556      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25  path2reg0 (LUT5)        0.732      14.288
- Arrival time                                                                       14.288                  (7 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0]  clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.601 r     4.023      ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[19]                       cell (MULT18)           3.563 r     7.586
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net  (fanout = 1)       1.497 r     9.083                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.706 r     9.789
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     9.789                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     9.862
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     9.862                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     9.935
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     9.935                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r    10.290
+ ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.664 r    10.954                    
+ ua_lvds_rx/reg8_syn_170.f[0]                                cell (LUT5)             0.424 r    11.378
+ u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.757 r    12.135      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[1]                                 cell (LUT5)             0.424 r    12.559
+ u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net  (fanout = 1)       0.738 r    13.297      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[0]                                 cell (LUT5)             0.424 r    13.721
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.471 r    14.192      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6 path2reg0               0.732      14.924
+ Arrival time                                                                       14.924                  (7 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116      22.762
@@ -330,19 +182,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25 (
  clock recovergence pessimism                                                        0.167      22.929
  Required time                                                                      22.929            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               8.641ns          
+ Slack                                                                               8.005ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 (85 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24 (659 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     12.509 ns                                                       
- Start Point:             scan_start_diff/trigger_syn_7099.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (rising edge triggered by clock a_pclk)
+ Slack (setup check):     8.153 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         8.144ns  (logic 2.383ns, net 5.761ns, 29% logic)                
- Logic Levels:            6 ( LUT4=6 )                                                    
+ Data Path Delay:         12.500ns  (logic 6.774ns, net 5.726ns, 54% logic)               
+ Logic Levels:            7 ( LUT5=4 ADDER=2 MULT18=1 )                                   
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -350,29 +202,31 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- scan_start_diff/trigger_syn_7099.clk (u_pll_lvds/clk0_out)  net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- scan_start_diff/trigger_syn_7099.q[0]                       clk2q                   0.146 r     2.422
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1]) net  (fanout = 94)      1.817 r     4.239      ../../../../hg_mp/fe/ram_switch.v(33)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.f[1] cell (LUT4)             0.348 r     4.587
- sampling_fe_a/u_sort/reg2_syn_54.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39) net  (fanout = 61)      1.327 r     5.914      ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/reg2_syn_54.f[1]                       cell (LUT4)             0.431 r     6.345
- sampling_fe_a/u_sort/reg0_syn_58.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656) net  (fanout = 5)       0.685 r     7.030      ../../../../hg_mp/fe/mux_e.v(24)
- sampling_fe_a/u_sort/reg0_syn_58.f[0]                       cell (LUT4)             0.333 r     7.363
- sampling_fe_a/u_sort/reg0_syn_58.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2) net  (fanout = 1)       0.593 r     7.956      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/reg0_syn_58.f[1]                       cell (LUT4)             0.251 r     8.207
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4) net  (fanout = 3)       0.601 r     8.808      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.f[0] cell (LUT4)             0.408 r     9.216
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2) net  (fanout = 1)       0.738 r     9.954      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 path2reg0 (LUT4)        0.466      10.420
- Arrival time                                                                       10.420                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0]  clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.601 r     4.023      ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[23]                       cell (MULT18)           3.563 r     7.586
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net  (fanout = 1)       1.643 r     9.229                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.706 r     9.935
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     9.935                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r    10.290
+ ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.664 r    10.954                    
+ ua_lvds_rx/reg8_syn_170.f[0]                                cell (LUT5)             0.424 r    11.378
+ u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.757 r    12.135      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[1]                                 cell (LUT5)             0.424 r    12.559
+ u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net  (fanout = 1)       0.738 r    13.297      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[0]                                 cell (LUT5)             0.424 r    13.721
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.323 r    14.044      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24  path2reg0 (LUT5)        0.732      14.776
+ Arrival time                                                                       14.776                  (7 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116      22.762
@@ -380,17 +234,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
  clock recovergence pessimism                                                        0.167      22.929
  Required time                                                                      22.929            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              12.509ns          
+ Slack                                                                               8.153ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     12.523 ns                                                       
- Start Point:             scan_start_diff/trigger_syn_7101.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (rising edge triggered by clock a_pclk)
+ Slack (setup check):     8.153 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         8.130ns  (logic 2.297ns, net 5.833ns, 28% logic)                
- Logic Levels:            6 ( LUT4=6 )                                                    
+ Data Path Delay:         12.500ns  (logic 6.774ns, net 5.726ns, 54% logic)               
+ Logic Levels:            7 ( LUT5=4 ADDER=2 MULT18=1 )                                   
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -398,29 +252,31 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- scan_start_diff/trigger_syn_7101.clk (u_pll_lvds/clk0_out)  net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- scan_start_diff/trigger_syn_7101.q[0]                       clk2q                   0.146 r     2.422
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.d[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0]) net  (fanout = 90)      1.889 r     4.311      ../../../../hg_mp/fe/ram_switch.v(33)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.f[1] cell (LUT4)             0.262 r     4.573
- sampling_fe_a/u_sort/reg2_syn_54.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39) net  (fanout = 61)      1.327 r     5.900      ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/reg2_syn_54.f[1]                       cell (LUT4)             0.431 r     6.331
- sampling_fe_a/u_sort/reg0_syn_58.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656) net  (fanout = 5)       0.685 r     7.016      ../../../../hg_mp/fe/mux_e.v(24)
- sampling_fe_a/u_sort/reg0_syn_58.f[0]                       cell (LUT4)             0.333 r     7.349
- sampling_fe_a/u_sort/reg0_syn_58.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2) net  (fanout = 1)       0.593 r     7.942      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/reg0_syn_58.f[1]                       cell (LUT4)             0.251 r     8.193
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4) net  (fanout = 3)       0.601 r     8.794      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.f[0] cell (LUT4)             0.408 r     9.202
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2) net  (fanout = 1)       0.738 r     9.940      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 path2reg0 (LUT4)        0.466      10.406
- Arrival time                                                                       10.406                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0]  clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.601 r     4.023      ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[23]                       cell (MULT18)           3.563 r     7.586
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9]) net  (fanout = 1)       1.643 r     9.229                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.706 r     9.935
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     9.935                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r    10.290
+ ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.664 r    10.954                    
+ ua_lvds_rx/reg8_syn_170.f[0]                                cell (LUT5)             0.424 r    11.378
+ u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.757 r    12.135      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[1]                                 cell (LUT5)             0.424 r    12.559
+ u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net  (fanout = 1)       0.738 r    13.297      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[0]                                 cell (LUT5)             0.424 r    13.721
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.323 r    14.044      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24  path2reg0 (LUT5)        0.732      14.776
+ Arrival time                                                                       14.776                  (7 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116      22.762
@@ -428,17 +284,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
  clock recovergence pessimism                                                        0.167      22.929
  Required time                                                                      22.929            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              12.523ns          
+ Slack                                                                               8.153ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     12.660 ns                                                       
- Start Point:             scan_start_diff/trigger_syn_7099.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (rising edge triggered by clock a_pclk)
+ Slack (setup check):     8.153 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         7.993ns  (logic 2.360ns, net 5.633ns, 29% logic)                
- Logic Levels:            6 ( LUT4=6 )                                                    
+ Data Path Delay:         12.500ns  (logic 6.920ns, net 5.580ns, 55% logic)               
+ Logic Levels:            7 ( LUT5=4 ADDER=2 MULT18=1 )                                   
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -446,29 +302,35 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- scan_start_diff/trigger_syn_7099.clk (u_pll_lvds/clk0_out)  net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- scan_start_diff/trigger_syn_7099.q[0]                       clk2q                   0.146 r     2.422
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1]) net  (fanout = 94)      1.817 r     4.239      ../../../../hg_mp/fe/ram_switch.v(33)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.f[1] cell (LUT4)             0.348 r     4.587
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[84]_syn_62.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39) net  (fanout = 61)      1.218 r     5.805      ../../../../hg_mp/fe/ram_switch_state.v(64)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[84]_syn_62.f[0] cell (LUT4)             0.333 r     6.138
- sampling_fe_a/u_sort/reg0_syn_58.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4756) net  (fanout = 5)       0.666 r     6.804      ../../../../hg_mp/fe/mux_e.v(24)
- sampling_fe_a/u_sort/reg0_syn_58.f[0]                       cell (LUT4)             0.408 r     7.212
- sampling_fe_a/u_sort/reg0_syn_58.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2) net  (fanout = 1)       0.593 r     7.805      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/reg0_syn_58.f[1]                       cell (LUT4)             0.251 r     8.056
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4) net  (fanout = 3)       0.601 r     8.657      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.f[0] cell (LUT4)             0.408 r     9.065
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2) net  (fanout = 1)       0.738 r     9.803      ../../../../hg_mp/fe/ram_switch_state.v(47)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14 path2reg0 (LUT4)        0.466      10.269
- Arrival time                                                                       10.269                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.q[0]  clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/mult0_syn_4.a[11] (sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9]) net  (fanout = 4)       1.601 r     4.023      ../../../../hg_mp/fe/prebuffer.v(109)
+ U_rgb_to_csi_pakage/mult0_syn_4.p[19]                       cell (MULT18)           3.563 r     7.586
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5]) net  (fanout = 1)       1.497 r     9.083                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.706 r     9.789
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     9.789                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     9.862
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     9.862                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     9.935
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     9.935                    
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r    10.290
+ ua_lvds_rx/reg8_syn_170.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.664 r    10.954                    
+ ua_lvds_rx/reg8_syn_170.f[0]                                cell (LUT5)             0.424 r    11.378
+ u_pic_cnt/reg1_syn_370.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235) net  (fanout = 1)       0.757 r    12.135      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[1]                                 cell (LUT5)             0.424 r    12.559
+ u_pic_cnt/reg1_syn_370.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237) net  (fanout = 1)       0.738 r    13.297      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_pic_cnt/reg1_syn_370.f[0]                                 cell (LUT5)             0.424 r    13.721
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243) net  (fanout = 4)       0.323 r    14.044      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24  path2reg0 (LUT5)        0.732      14.776
+ Arrival time                                                                       14.776                  (7 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116      22.762
@@ -476,17 +338,269 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_
  clock recovergence pessimism                                                        0.167      22.929
  Required time                                                                      22.929            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              12.660ns          
+ Slack                                                                               8.153ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 (12 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     12.557 ns                                                       
+ Start Point:             u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (rising edge triggered by clock clk_adc)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.c[1] (rising edge triggered by clock a_pclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         7.929ns  (logic 2.338ns, net 5.591ns, 29% logic)                
+ Logic Levels:            6 ( LUT4=5 LUT3=1 )                                             
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (exdev_ctl_a/clk_adc) net                     2.276       2.276      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.q[0]     clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] (u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109) net  (fanout = 36)      1.618 r     4.040      ../../../../hg_mp/local_bus/local_bus_slve_cis.v(56)
+ U_rgb_to_csi_pakage/reg4_syn_137_syn_2.f[0]                 cell (LUT3)             0.251 r     4.291
+ reg14_syn_50.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2) net  (fanout = 52)      1.283 r     5.574      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ reg14_syn_50.f[0]                                           cell (LUT4)             0.408 r     5.982
+ ua_lvds_rx/reg8_syn_184.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5086) net  (fanout = 5)       0.901 r     6.883      ../../../../hg_mp/fe/mux_e.v(24)
+ ua_lvds_rx/reg8_syn_184.f[0]                                cell (LUT4)             0.408 r     7.291
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_31.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_10) net  (fanout = 1)       0.594 r     7.885      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_31.f[1] cell (LUT4)             0.251 r     8.136
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_33.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_12) net  (fanout = 3)       0.601 r     8.737      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_33.f[0] cell (LUT4)             0.408 r     9.145
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[50]_syn_2) net  (fanout = 1)       0.594 r     9.739      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 path2reg1 (LUT4)        0.466      10.205
+ Arrival time                                                                       10.205                  (6 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                 20.833      22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116      22.762
+ clock uncertainty                                                                  -0.000      22.762
+ clock recovergence pessimism                                                        0.000      22.762
+ Required time                                                                      22.762            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                              12.557ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     13.869 ns                                                       
+ Start Point:             u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (rising edge triggered by clock clk_adc)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (rising edge triggered by clock a_pclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         6.617ns  (logic 2.126ns, net 4.491ns, 32% logic)                
+ Logic Levels:            5 ( LUT4=4 LUT3=1 )                                             
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (exdev_ctl_a/clk_adc) net                     2.276       2.276      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.q[0]     clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] (u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109) net  (fanout = 36)      1.618 r     4.040      ../../../../hg_mp/local_bus/local_bus_slve_cis.v(56)
+ U_rgb_to_csi_pakage/reg4_syn_137_syn_2.f[0]                 cell (LUT3)             0.251 r     4.291
+ reg14_syn_50.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2) net  (fanout = 52)      1.283 r     5.574      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ reg14_syn_50.f[1]                                           cell (LUT4)             0.408 r     5.982
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.a[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3436) net  (fanout = 5)       0.664 r     6.646      ../../../../hg_mp/fe/mux_e.v(24)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[0] cell (LUT4)             0.424 r     7.070
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20) net  (fanout = 1)       0.456 r     7.526      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[1] cell (LUT4)             0.348 r     7.874
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22) net  (fanout = 3)       0.470 r     8.344      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 path2reg1 (LUT4)        0.549       8.893
+ Arrival time                                                                        8.893                  (5 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                 20.833      22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116      22.762
+ clock uncertainty                                                                  -0.000      22.762
+ clock recovergence pessimism                                                        0.000      22.762
+ Required time                                                                      22.762            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                              13.869ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     14.080 ns                                                       
+ Start Point:             u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (rising edge triggered by clock clk_adc)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (rising edge triggered by clock a_pclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         6.406ns  (logic 2.133ns, net 4.273ns, 33% logic)                
+ Logic Levels:            5 ( LUT4=4 LUT3=1 )                                             
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk (exdev_ctl_a/clk_adc) net                     2.276       2.276      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.q[0]     clk2q                   0.146 r     2.422
+ U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0] (u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109) net  (fanout = 36)      1.618 r     4.040      ../../../../hg_mp/local_bus/local_bus_slve_cis.v(56)
+ U_rgb_to_csi_pakage/reg4_syn_137_syn_2.f[0]                 cell (LUT3)             0.251 r     4.291
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_75.a[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2) net  (fanout = 52)      1.091 r     5.382      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_75.f[1] cell (LUT4)             0.408 r     5.790
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4536) net  (fanout = 5)       0.638 r     6.428      ../../../../hg_mp/fe/mux_e.v(24)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[0] cell (LUT4)             0.431 r     6.859
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20) net  (fanout = 1)       0.456 r     7.315      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.f[1] cell (LUT4)             0.348 r     7.663
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22) net  (fanout = 3)       0.470 r     8.133      ../../../../hg_mp/fe/ram_switch_state.v(47)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716 path2reg1 (LUT4)        0.549       8.682
+ Arrival time                                                                        8.682                  (5 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.clk (u_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                 20.833      22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116      22.762
+ clock uncertainty                                                                  -0.000      22.762
+ clock recovergence pessimism                                                        0.000      22.762
+ Required time                                                                      22.762            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                              14.080ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Hold checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 (10 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 (8 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      0.080 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[7] (rising edge triggered by clock a_pclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.325ns  (logic 0.109ns, net 0.216ns, 33% logic)                
+ Logic Levels:            1 ( EMB=1 )                                                     
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge                                                                   0.000       1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.q[0] clk2q                   0.109 r     2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[7] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[71]) net  (fanout = 2)       0.216 r     2.263      ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 path2reg (EMB)          0.000       2.263
+ Arrival time                                                                        2.263                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                  0.000       2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.200       2.330
+ clock uncertainty                                                                   0.000       2.330
+ clock recovergence pessimism                                                       -0.147       2.183
+ Required time                                                                       2.183            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.080ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.251 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[3] (rising edge triggered by clock a_pclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.496ns  (logic 0.109ns, net 0.387ns, 21% logic)                
+ Logic Levels:            1 ( EMB=1 )                                                     
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge                                                                   0.000       1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.q[1] clk2q                   0.109 r     2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[67]) net  (fanout = 2)       0.387 r     2.434      ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 path2reg (EMB)          0.000       2.434
+ Arrival time                                                                        2.434                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                  0.000       2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.200       2.330
+ clock uncertainty                                                                   0.000       2.330
+ clock recovergence pessimism                                                       -0.147       2.183
+ Required time                                                                       2.183            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.251ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.336 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[4] (rising edge triggered by clock a_pclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.581ns  (logic 0.109ns, net 0.472ns, 18% logic)                
+ Logic Levels:            1 ( EMB=1 )                                                     
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge                                                                   0.000       1.938
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.q[0] clk2q                   0.109 r     2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[4] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[68]) net  (fanout = 2)       0.472 r     2.519      ../../../../hg_mp/fe/prebuffer.v(329)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1 path2reg (EMB)          0.000       2.519
+ Arrival time                                                                        2.519                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                  0.000       2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.200       2.330
+ clock uncertainty                                                                   0.000       2.330
+ clock recovergence pessimism                                                       -0.147       2.183
+ Required time                                                                       2.183            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.336ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 (10 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.089 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[8] (rising edge triggered by clock a_pclk)
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[11] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.334ns  (logic 0.109ns, net 0.225ns, 32% logic)                
@@ -498,19 +612,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_s
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[8] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[65]) net  (fanout = 2)       0.225 r     2.272      ../../../../hg_mp/fe/prebuffer.v(331)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 path2reg (EMB)          0.000       2.272
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.q[0] clk2q                   0.109 r     2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[11] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[18]) net  (fanout = 2)       0.225 r     2.272      ../../../../hg_mp/fe/prebuffer.v(331)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 path2reg (EMB)          0.000       2.272
  Arrival time                                                                        2.272                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -522,12 +636,12 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_s
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.195 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[3] (rising edge triggered by clock a_pclk)
+ Slack (hold check):      0.130 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[7] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.440ns  (logic 0.109ns, net 0.331ns, 24% logic)                
+ Data Path Delay:         0.375ns  (logic 0.109ns, net 0.266ns, 29% logic)                
  Logic Levels:            1 ( EMB=1 )                                                     
 
  Point                                                       Type                     Incr        Path      Info          
@@ -536,19 +650,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_s
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[60]) net  (fanout = 2)       0.331 r     2.378      ../../../../hg_mp/fe/prebuffer.v(331)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 path2reg (EMB)          0.000       2.378
- Arrival time                                                                        2.378                  (1 lvl)       
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.q[1] clk2q                   0.109 r     2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[7] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[14]) net  (fanout = 2)       0.266 r     2.313      ../../../../hg_mp/fe/prebuffer.v(331)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 path2reg (EMB)          0.000       2.313
+ Arrival time                                                                        2.313                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -556,245 +670,13 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_s
  clock recovergence pessimism                                                       -0.147       2.183
  Required time                                                                       2.183            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.195ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.196 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[9] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.441ns  (logic 0.109ns, net 0.332ns, 24% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[9] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66]) net  (fanout = 2)       0.332 r     2.379      ../../../../hg_mp/fe/prebuffer.v(331)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1 path2reg (EMB)          0.000       2.379
- Arrival time                                                                        2.379                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.196ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.114 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[5] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.359ns  (logic 0.109ns, net 0.250ns, 30% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[5] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[21]) net  (fanout = 2)       0.250 r     2.297      ../../../../hg_mp/fe/prebuffer.v(329)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB)          0.000       2.297
- Arrival time                                                                        2.297                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.114ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.218 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[3] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.463ns  (logic 0.109ns, net 0.354ns, 23% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19]) net  (fanout = 2)       0.354 r     2.401      ../../../../hg_mp/fe/prebuffer.v(329)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB)          0.000       2.401
- Arrival time                                                                        2.401                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.218ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.311 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[6] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.556ns  (logic 0.109ns, net 0.447ns, 19% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[6] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[22]) net  (fanout = 2)       0.447 r     2.494      ../../../../hg_mp/fe/prebuffer.v(329)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB)          0.000       2.494
- Arrival time                                                                        2.494                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.311ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.114 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[1] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.359ns  (logic 0.109ns, net 0.250ns, 30% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[1] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[17]) net  (fanout = 2)       0.250 r     2.297      ../../../../hg_mp/fe/prebuffer.v(329)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB)          0.000       2.297
- Arrival time                                                                        2.297                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.114ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.196 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[3] (rising edge triggered by clock a_pclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.441ns  (logic 0.109ns, net 0.332ns, 24% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[3] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19]) net  (fanout = 2)       0.332 r     2.379      ../../../../hg_mp/fe/prebuffer.v(329)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB)          0.000       2.379
- Arrival time                                                                        2.379                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
- u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.196ns          
+ Slack                                                                               0.130ns          
 
 ---------------------------------------------------------------------------------------------------------
 
  Slack (hold check):      0.234 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[0] (rising edge triggered by clock a_pclk)
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[12] (rising edge triggered by clock a_pclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.479ns  (logic 0.109ns, net 0.370ns, 22% logic)                
@@ -806,19 +688,19 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_s
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk (u_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.q[0] clk2q                   0.109 r     2.047
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[0] (sampling_fe_a/u_sort/u_data_prebuffer/ram_data[16]) net  (fanout = 2)       0.370 r     2.417      ../../../../hg_mp/fe/prebuffer.v(329)
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB)          0.000       2.417
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.q[0] clk2q                   0.109 r     2.047
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[12] (sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[19]) net  (fanout = 2)       0.370 r     2.417      ../../../../hg_mp/fe/prebuffer.v(331)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1 path2reg (EMB)          0.000       2.417
  Arrival time                                                                        2.417                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
  u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clka (u_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -830,111 +712,77 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_s
 
 ---------------------------------------------------------------------------------------------------------
 
+Paths for end point u0_test_en/reg0_syn_26 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      0.167 ns                                                        
+ Start Point:             u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk (rising edge triggered by clock clk_adc)
+ End Point:               u0_test_en/reg0_syn_26.mi[0] (rising edge triggered by clock a_pclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk (exdev_ctl_a/clk_adc) net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge                                                                   0.000       1.938
+---------------------------------------------------------------------------------------------------------
+ u_bus_top/u_local_bus_slve_cis/reg46_syn_241.q[0]           clk2q                   0.109 r     2.047
+ u0_test_en/reg0_syn_26.mi[0] (u0_test_en/signal_from[0])    net  (fanout = 2)       0.216 r     2.263      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u0_test_en/reg0_syn_26                                      path2reg0               0.095       2.358
+ Arrival time                                                                        2.358                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ u0_test_en/reg0_syn_26.clk (u_pll_lvds/clk0_out)            net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                  0.000       2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.061       2.191
+ clock uncertainty                                                                   0.000       2.191
+ clock recovergence pessimism                                                        0.000       2.191
+ Required time                                                                       2.191            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.167ns          
+
+---------------------------------------------------------------------------------------------------------
+
 
 =========================================================================================================
 Timing constraint:        clock: a_sclk                                                   
 Clock = a_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns
 
-282 endpoints analyzed totally, and 706 paths analyzed
+282 endpoints analyzed totally, and 698 paths analyzed
 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.172ns
+Minimum period is 1.906ns
 ---------------------------------------------------------------------------------------------------------
 
 Paths for end point ua_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     3.780 ns                                                        
- Start Point:             ua_lvds_rx/reg7_syn_44.clk (rising edge triggered by clock a_sclk)
+ Slack (setup check):     4.046 ns                                                        
+ Start Point:             ua_lvds_rx/reg7_syn_33.clk (rising edge triggered by clock a_sclk)
  End Point:               ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         2.020ns  (logic 0.941ns, net 1.079ns, 46% logic)                
+ Data Path Delay:         1.726ns  (logic 0.948ns, net 0.778ns, 54% logic)                
  Logic Levels:            2 ( LUT5=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg7_syn_44.clk (ua_lvds_rx/sclk)                net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/reg7_syn_33.clk (ua_lvds_rx/sclk)                net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_44.q[1]                                 clk2q                   0.146 r     2.556
- ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ua_lvds_rx/rx_clk_sft[0]) net  (fanout = 2)       0.623 r     3.179      encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.424 r     3.603
- ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.456 r     4.059      encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.430
- Arrival time                                                                        4.430                  (2 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk)      net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       8.118
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       8.002
- clock uncertainty                                                                  -0.000       8.002
- clock recovergence pessimism                                                        0.208       8.210
- Required time                                                                       8.210            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               3.780ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     3.815 ns                                                        
- Start Point:             ua_lvds_rx/reg7_syn_47.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         2.000ns  (logic 0.779ns, net 1.221ns, 38% logic)                
- Logic Levels:            2 ( LUT5=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg7_syn_47.clk (ua_lvds_rx/sclk)                net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_47.q[0]                                 clk2q                   0.146 r     2.556
- ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0] (ua_lvds_rx/rx_clk_sft[3]) net  (fanout = 2)       0.765 r     3.321      encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.262 r     3.583
- ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.456 r     4.039      encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.410
- Arrival time                                                                        4.410                  (2 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk)      net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       8.118
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       8.002
- clock uncertainty                                                                  -0.000       8.002
- clock recovergence pessimism                                                        0.223       8.225
- Required time                                                                       8.225            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               3.815ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     3.849 ns                                                        
- Start Point:             ua_lvds_rx/reg7_syn_38.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.923ns  (logic 0.865ns, net 1.058ns, 44% logic)                
- Logic Levels:            2 ( LUT5=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg7_syn_38.clk (ua_lvds_rx/sclk)                net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg7_syn_38.q[1]                                 clk2q                   0.146 r     2.556
- ua_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ua_lvds_rx/rx_clk_sft[2]) net  (fanout = 2)       0.602 r     3.158      encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.348 r     3.506
- ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.456 r     3.962      encrypted_text(0)
- ua_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.333
- Arrival time                                                                        4.333                  (2 lvl)       
+ ua_lvds_rx/reg7_syn_33.q[1]                                 clk2q                   0.146 r     2.556
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ua_lvds_rx/rx_clk_sft[1]) net  (fanout = 2)       0.620 r     3.176      encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.431 r     3.607
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.158 r     3.765      encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.136
+ Arrival time                                                                        4.136                  (2 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
@@ -946,35 +794,35 @@ Paths for end point ua_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
  clock recovergence pessimism                                                        0.180       8.182
  Required time                                                                       8.182            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               3.849ns          
+ Slack                                                                               4.046ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point ua_lvds_rx/reg8_syn_145 (9 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     4.058 ns                                                        
- Start Point:             ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/reg8_syn_145.d[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check):     4.086 ns                                                        
+ Start Point:             ua_lvds_rx/reg7_syn_24.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.714ns  (logic 0.655ns, net 1.059ns, 38% logic)                
- Logic Levels:            1                                                               
+ Data Path Delay:         1.686ns  (logic 0.779ns, net 0.907ns, 46% logic)                
+ Logic Levels:            2 ( LUT5=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk)            net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/reg7_syn_24.clk (ua_lvds_rx/sclk)                net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/sync0_reg_syn_4.q[1]                             clk2q                   0.146 r     2.556
- ua_lvds_rx/reg8_syn_145.d[1] (ua_lvds_rx/sync0)             net  (fanout = 43)      1.059 r     3.615      encrypted_text(0)
- ua_lvds_rx/reg8_syn_145                                     path2reg0               0.509       4.124
- Arrival time                                                                        4.124                  (1 lvl)       
+ ua_lvds_rx/reg7_syn_24.q[1]                                 clk2q                   0.146 r     2.556
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0] (ua_lvds_rx/rx_clk_sft[3]) net  (fanout = 2)       0.749 r     3.305      encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.262 r     3.567
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.158 r     3.725      encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.096
+ Arrival time                                                                        4.096                  (2 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk)               net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk)      net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  5.952       8.118
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116       8.002
@@ -982,33 +830,35 @@ Paths for end point ua_lvds_rx/reg8_syn_145 (9 paths)
  clock recovergence pessimism                                                        0.180       8.182
  Required time                                                                       8.182            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.058ns          
+ Slack                                                                               4.086ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     4.058 ns                                                        
- Start Point:             ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/reg8_syn_145.d[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check):     4.194 ns                                                        
+ Start Point:             ua_lvds_rx/reg7_syn_30.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.714ns  (logic 0.655ns, net 1.059ns, 38% logic)                
- Logic Levels:            1                                                               
+ Data Path Delay:         1.578ns  (logic 0.941ns, net 0.637ns, 59% logic)                
+ Logic Levels:            2 ( LUT5=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk)            net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/reg7_syn_30.clk (ua_lvds_rx/sclk)                net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/sync0_reg_syn_4.q[1]                             clk2q                   0.146 r     2.556
- ua_lvds_rx/reg8_syn_145.d[0] (ua_lvds_rx/sync0)             net  (fanout = 43)      1.059 r     3.615      encrypted_text(0)
- ua_lvds_rx/reg8_syn_145                                     path2reg0               0.509       4.124
- Arrival time                                                                        4.124                  (1 lvl)       
+ ua_lvds_rx/reg7_syn_30.q[1]                                 clk2q                   0.146 r     2.556
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ua_lvds_rx/rx_clk_sft[0]) net  (fanout = 2)       0.479 r     3.035      encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.424 r     3.459
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ua_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.158 r     3.617      encrypted_text(0)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       3.988
+ Arrival time                                                                        3.988                  (2 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk)               net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/rx_clk_sync_reg_syn_5.clk (ua_lvds_rx/sclk)      net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  5.952       8.118
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116       8.002
@@ -1016,150 +866,222 @@ Paths for end point ua_lvds_rx/reg8_syn_145 (9 paths)
  clock recovergence pessimism                                                        0.180       8.182
  Required time                                                                       8.182            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.058ns          
+ Slack                                                                               4.194ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     4.198 ns                                                        
- Start Point:             ua_lvds_rx/reg8_syn_145.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/reg8_syn_145.a[1] (rising edge triggered by clock a_sclk)
+Paths for end point ua_lvds_rx/ramread0_syn_88 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     4.116 ns                                                        
+ Start Point:             ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_88.c[0] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.638ns  (logic 0.878ns, net 0.760ns, 53% logic)                
+ Data Path Delay:         1.663ns  (logic 0.146ns, net 1.517ns, 8% logic)                 
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk)               net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk)               net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg8_syn_145.q[0]                                clk2q                   0.146 r     2.556
- ua_lvds_rx/reg8_syn_145.a[1] (ua_lvds_rx/para_data[2])      net  (fanout = 3)       0.760 r     3.316      encrypted_text(0)
- ua_lvds_rx/reg8_syn_145                                     path2reg0               0.732       4.048
- Arrival time                                                                        4.048                  (1 lvl)       
+ ua_lvds_rx/reg16_syn_31.q[0]                                clk2q                   0.146 r     2.556
+ ua_lvds_rx/ramread0_syn_88.c[0] (ua_lvds_rx/wcnt[2])        net  (fanout = 9)       1.517 r     4.073      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_88                                  path2reg                0.000       4.073
+ Arrival time                                                                        4.073                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg8_syn_145.clk (ua_lvds_rx/sclk)               net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/ramread0_syn_88.clk (ua_lvds_rx/sclk)            net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  5.952       8.118
 ---------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       8.002
- clock uncertainty                                                                  -0.000       8.002
- clock recovergence pessimism                                                        0.244       8.246
- Required time                                                                       8.246            
+ cell setup                                                                         -0.109       8.009
+ clock uncertainty                                                                  -0.000       8.009
+ clock recovergence pessimism                                                        0.180       8.189
+ Required time                                                                       8.189            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.198ns          
+ Slack                                                                               4.116ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point ua_lvds_rx/reg8_syn_157 (9 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     4.092 ns                                                        
- Start Point:             ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/reg8_syn_157.d[1] (rising edge triggered by clock a_sclk)
+ Slack (setup check):     5.160 ns                                                        
+ Start Point:             ua_lvds_rx/reg8_syn_157.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_88.c[1] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.680ns  (logic 0.655ns, net 1.025ns, 38% logic)                
+ Data Path Delay:         0.619ns  (logic 0.146ns, net 0.473ns, 23% logic)                
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk)            net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk)               net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/sync0_reg_syn_4.q[1]                             clk2q                   0.146 r     2.556
- ua_lvds_rx/reg8_syn_157.d[1] (ua_lvds_rx/sync0)             net  (fanout = 43)      1.025 r     3.581      encrypted_text(0)
- ua_lvds_rx/reg8_syn_157                                     path2reg0               0.509       4.090
- Arrival time                                                                        4.090                  (1 lvl)       
+ ua_lvds_rx/reg8_syn_157.q[0]                                clk2q                   0.146 r     2.556
+ ua_lvds_rx/ramread0_syn_88.c[1] (ua_lvds_rx/para_data[22])  net  (fanout = 3)       0.473 r     3.029      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_88                                  path2reg                0.000       3.029
+ Arrival time                                                                        3.029                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk)               net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/ramread0_syn_88.clk (ua_lvds_rx/sclk)            net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  5.952       8.118
 ---------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       8.002
- clock uncertainty                                                                  -0.000       8.002
- clock recovergence pessimism                                                        0.180       8.182
- Required time                                                                       8.182            
+ cell setup                                                                         -0.109       8.009
+ clock uncertainty                                                                  -0.000       8.009
+ clock recovergence pessimism                                                        0.180       8.189
+ Required time                                                                       8.189            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.092ns          
+ Slack                                                                               5.160ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     4.092 ns                                                        
- Start Point:             ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/reg8_syn_157.d[0] (rising edge triggered by clock a_sclk)
+Paths for end point ua_lvds_rx/ramread0_syn_46 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     4.116 ns                                                        
+ Start Point:             ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_46.c[0] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.680ns  (logic 0.655ns, net 1.025ns, 38% logic)                
+ Data Path Delay:         1.663ns  (logic 0.146ns, net 1.517ns, 8% logic)                 
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk)            net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk)               net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/sync0_reg_syn_4.q[1]                             clk2q                   0.146 r     2.556
- ua_lvds_rx/reg8_syn_157.d[0] (ua_lvds_rx/sync0)             net  (fanout = 43)      1.025 r     3.581      encrypted_text(0)
- ua_lvds_rx/reg8_syn_157                                     path2reg0               0.509       4.090
- Arrival time                                                                        4.090                  (1 lvl)       
+ ua_lvds_rx/reg16_syn_31.q[0]                                clk2q                   0.146 r     2.556
+ ua_lvds_rx/ramread0_syn_46.c[0] (ua_lvds_rx/wcnt[2])        net  (fanout = 9)       1.517 r     4.073      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_46                                  path2reg                0.000       4.073
+ Arrival time                                                                        4.073                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk)               net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk)            net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  5.952       8.118
 ---------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       8.002
- clock uncertainty                                                                  -0.000       8.002
- clock recovergence pessimism                                                        0.180       8.182
- Required time                                                                       8.182            
+ cell setup                                                                         -0.109       8.009
+ clock uncertainty                                                                  -0.000       8.009
+ clock recovergence pessimism                                                        0.180       8.189
+ Required time                                                                       8.189            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.092ns          
+ Slack                                                                               4.116ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     4.387 ns                                                        
- Start Point:             ua_lvds_rx/sync0_reg_syn_4.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/reg8_syn_157.mi[0] (rising edge triggered by clock a_sclk)
+ Slack (setup check):     4.574 ns                                                        
+ Start Point:             ua_lvds_rx/reg8_syn_153.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_46.c[1] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.385ns  (logic 0.553ns, net 0.832ns, 39% logic)                
+ Data Path Delay:         1.205ns  (logic 0.146ns, net 1.059ns, 12% logic)                
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/sync0_reg_syn_4.clk (ua_lvds_rx/sclk)            net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/reg8_syn_153.clk (ua_lvds_rx/sclk)               net                     2.410       2.410      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- ua_lvds_rx/sync0_reg_syn_4.q[0]                             clk2q                   0.146 r     2.556
- ua_lvds_rx/reg8_syn_157.mi[0] (ua_lvds_rx/sync1)            net  (fanout = 32)      0.832 r     3.388      encrypted_text(0)
- ua_lvds_rx/reg8_syn_157                                     path2reg0               0.407       3.795
- Arrival time                                                                        3.795                  (1 lvl)       
+ ua_lvds_rx/reg8_syn_153.q[0]                                clk2q                   0.146 r     2.556
+ ua_lvds_rx/ramread0_syn_46.c[1] (ua_lvds_rx/para_data[10])  net  (fanout = 3)       1.059 r     3.615      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_46                                  path2reg                0.000       3.615
+ Arrival time                                                                        3.615                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg8_syn_157.clk (ua_lvds_rx/sclk)               net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/ramread0_syn_46.clk (ua_lvds_rx/sclk)            net                     2.166       2.166      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  5.952       8.118
 ---------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       8.002
- clock uncertainty                                                                  -0.000       8.002
- clock recovergence pessimism                                                        0.180       8.182
- Required time                                                                       8.182            
+ cell setup                                                                         -0.109       8.009
+ clock uncertainty                                                                  -0.000       8.009
+ clock recovergence pessimism                                                        0.180       8.189
+ Required time                                                                       8.189            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.387ns          
+ Slack                                                                               4.574ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Hold checks:
 ---------------------------------------------------------------------------------------------------------
+Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      0.092 ns                                                        
+ Start Point:             ua_lvds_rx/reg3_syn_184.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_102.c[1] (rising edge triggered by clock a_sclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.220ns  (logic 0.109ns, net 0.111ns, 49% logic)                
+ Logic Levels:            1                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/reg3_syn_184.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg3_syn_184.q[1]                                clk2q                   0.109 r     2.138
+ ua_lvds_rx/ramread0_syn_102.c[1] (ua_lvds_rx/para_data[26]) net  (fanout = 2)       0.111 r     2.249      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.249
+ Arrival time                                                                        2.249                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  0.000       2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.113       2.343
+ clock uncertainty                                                                   0.000       2.343
+ clock recovergence pessimism                                                       -0.186       2.157
+ Required time                                                                       2.157            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.092ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.700 ns                                                        
+ Start Point:             ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_102.c[0] (rising edge triggered by clock a_sclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.858ns  (logic 0.109ns, net 0.749ns, 12% logic)                
+ Logic Levels:            1                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg16_syn_31.q[0]                                clk2q                   0.109 r     2.138
+ ua_lvds_rx/ramread0_syn_102.c[0] (ua_lvds_rx/wcnt[2])       net  (fanout = 9)       0.749 r     2.887      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.887
+ Arrival time                                                                        2.887                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  0.000       2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.113       2.343
+ clock uncertainty                                                                   0.000       2.343
+ clock recovergence pessimism                                                       -0.156       2.187
+ Required time                                                                       2.187            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.700ns          
+
+---------------------------------------------------------------------------------------------------------
+
 Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.092 ns                                                        
@@ -1196,152 +1118,12 @@ Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.409 ns                                                        
- Start Point:             ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
+ Slack (hold check):      0.403 ns                                                        
+ Start Point:             ua_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock a_sclk)
  End Point:               ua_lvds_rx/ramread0_syn_102.b[0] (rising edge triggered by clock a_sclk)
  Clock group:             a_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.551ns  (logic 0.109ns, net 0.442ns, 19% logic)                
- Logic Levels:            1                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_31.q[1]                                clk2q                   0.109 r     2.138
- ua_lvds_rx/ramread0_syn_102.b[0] (ua_lvds_rx/wcnt[1])       net  (fanout = 10)      0.442 r     2.580      encrypted_text(0)
- ua_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.580
- Arrival time                                                                        2.580                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  0.000       2.230
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.113       2.343
- clock uncertainty                                                                   0.000       2.343
- clock recovergence pessimism                                                       -0.172       2.171
- Required time                                                                       2.171            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.409ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.167 ns                                                        
- Start Point:             ua_lvds_rx/reg14_syn_62.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/ramread0_syn_116.c[1] (rising edge triggered by clock a_sclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.325ns  (logic 0.109ns, net 0.216ns, 33% logic)                
- Logic Levels:            1                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg14_syn_62.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg14_syn_62.q[0]                                clk2q                   0.109 r     2.138
- ua_lvds_rx/ramread0_syn_116.c[1] (ua_lvds_rx/para_data[34]) net  (fanout = 2)       0.216 r     2.354      encrypted_text(0)
- ua_lvds_rx/ramread0_syn_116                                 path2reg                0.000       2.354
- Arrival time                                                                        2.354                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  0.000       2.230
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.113       2.343
- clock uncertainty                                                                   0.000       2.343
- clock recovergence pessimism                                                       -0.156       2.187
- Required time                                                                       2.187            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.167ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.345 ns                                                        
- Start Point:             ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/ramread0_syn_116.c[0] (rising edge triggered by clock a_sclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.503ns  (logic 0.109ns, net 0.394ns, 21% logic)                
- Logic Levels:            1                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg16_syn_31.q[0]                                clk2q                   0.109 r     2.138
- ua_lvds_rx/ramread0_syn_116.c[0] (ua_lvds_rx/wcnt[2])       net  (fanout = 9)       0.394 r     2.532      encrypted_text(0)
- ua_lvds_rx/ramread0_syn_116                                 path2reg                0.000       2.532
- Arrival time                                                                        2.532                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  0.000       2.230
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.113       2.343
- clock uncertainty                                                                   0.000       2.343
- clock recovergence pessimism                                                       -0.156       2.187
- Required time                                                                       2.187            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.345ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.167 ns                                                        
- Start Point:             ua_lvds_rx/reg3_syn_195.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/ramread0_syn_116.a[1] (rising edge triggered by clock a_sclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.325ns  (logic 0.109ns, net 0.216ns, 33% logic)                
- Logic Levels:            1                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/reg3_syn_195.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- ua_lvds_rx/reg3_syn_195.q[1]                                clk2q                   0.109 r     2.138
- ua_lvds_rx/ramread0_syn_116.a[1] (ua_lvds_rx/para_data[32]) net  (fanout = 2)       0.216 r     2.354      encrypted_text(0)
- ua_lvds_rx/ramread0_syn_116                                 path2reg                0.000       2.354
- Arrival time                                                                        2.354                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  0.000       2.230
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.113       2.343
- clock uncertainty                                                                   0.000       2.343
- clock recovergence pessimism                                                       -0.156       2.187
- Required time                                                                       2.187            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.167ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.586 ns                                                        
- Start Point:             ua_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock a_sclk)
- End Point:               ua_lvds_rx/ramread0_syn_116.a[0] (rising edge triggered by clock a_sclk)
- Clock group:             a_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.744ns  (logic 0.109ns, net 0.635ns, 14% logic)                
+ Data Path Delay:         0.561ns  (logic 0.109ns, net 0.452ns, 19% logic)                
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -1352,13 +1134,13 @@ Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
  ua_lvds_rx/reg16_syn_33.q[0]                                clk2q                   0.109 r     2.138
- ua_lvds_rx/ramread0_syn_116.a[0] (ua_lvds_rx/wcnt[0])       net  (fanout = 11)      0.635 r     2.773      encrypted_text(0)
- ua_lvds_rx/ramread0_syn_116                                 path2reg                0.000       2.773
- Arrival time                                                                        2.773                  (1 lvl)       
+ ua_lvds_rx/ramread0_syn_102.b[0] (ua_lvds_rx/wcnt[1])       net  (fanout = 10)      0.452 r     2.590      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.590
+ Arrival time                                                                        2.590                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
- ua_lvds_rx/ramread0_syn_116.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.113       2.343
@@ -1366,7 +1148,77 @@ Paths for end point ua_lvds_rx/ramread0_syn_116 (2 paths)
  clock recovergence pessimism                                                       -0.156       2.187
  Required time                                                                       2.187            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.586ns          
+ Slack                                                                               0.403ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point ua_lvds_rx/ramread0_syn_102 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      0.167 ns                                                        
+ Start Point:             ua_lvds_rx/reg3_syn_181.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_102.a[1] (rising edge triggered by clock a_sclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.325ns  (logic 0.109ns, net 0.216ns, 33% logic)                
+ Logic Levels:            1                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/reg3_syn_181.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg3_syn_181.q[0]                                clk2q                   0.109 r     2.138
+ ua_lvds_rx/ramread0_syn_102.a[1] (ua_lvds_rx/para_data[24]) net  (fanout = 2)       0.216 r     2.354      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.354
+ Arrival time                                                                        2.354                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  0.000       2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.113       2.343
+ clock uncertainty                                                                   0.000       2.343
+ clock recovergence pessimism                                                       -0.156       2.187
+ Required time                                                                       2.187            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.167ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.412 ns                                                        
+ Start Point:             ua_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock a_sclk)
+ End Point:               ua_lvds_rx/ramread0_syn_102.a[0] (rising edge triggered by clock a_sclk)
+ Clock group:             a_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.570ns  (logic 0.109ns, net 0.461ns, 19% logic)                
+ Logic Levels:            1                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/reg16_syn_31.clk (ua_lvds_rx/sclk)               net                     2.029       2.029      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ ua_lvds_rx/reg16_syn_31.q[1]                                clk2q                   0.109 r     2.138
+ ua_lvds_rx/ramread0_syn_102.a[0] (ua_lvds_rx/wcnt[0])       net  (fanout = 11)      0.461 r     2.599      encrypted_text(0)
+ ua_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.599
+ Arrival time                                                                        2.599                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[1]                                                         0.000       0.000                    
+ ua_lvds_rx/ramread0_syn_102.clk (ua_lvds_rx/sclk)           net                     2.230       2.230      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  0.000       2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.113       2.343
+ clock uncertainty                                                                   0.000       2.343
+ clock recovergence pessimism                                                       -0.156       2.187
+ Required time                                                                       2.187            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.412ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -1385,19 +1237,19 @@ Minimum period is 0ns
 Timing constraint:        clock: b_pclk                                                   
 Clock = b_pclk, period 20.833ns, rising at 0ns, falling at 10.417ns
 
-5874 endpoints analyzed totally, and 101266 paths analyzed
+5792 endpoints analyzed totally, and 101792 paths analyzed
 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 10.093ns
+Minimum period is 10.513ns
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 (70 paths)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 (139 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     10.740 ns                                                       
+ Slack (setup check):     10.320 ns                                                       
  Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         10.050ns  (logic 6.455ns, net 3.595ns, 64% logic)               
+ Data Path Delay:         10.470ns  (logic 6.651ns, net 3.819ns, 63% logic)               
  Logic Levels:            6 ( LUT5=4 ADDER=2 )                                            
 
  Point                                                       Type                     Incr        Path      Info          
@@ -1409,26 +1261,24 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net                     2.067       2.067      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.067
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q                   3.433 r     5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       0.886 r     6.386                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     7.013
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     7.013                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.073 r     7.086
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     7.086                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     7.159
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.159                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.232
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.232                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.587
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.827 r     8.414                    
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0]           cell (LUT5)             0.424 r     8.838
- u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.615 r     9.453      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg3_syn_167.f[0]                                 cell (LUT5)             0.424 r     9.877
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.603 r    10.480      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0]         cell (LUT5)             0.431 r    10.911
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 3)       0.664 r    11.575      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5)        0.542      12.117
- Arrival time                                                                       12.117                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q                   3.433 r     5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net  (fanout = 1)       1.253 r     6.753                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.706 r     7.459
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     7.459                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     7.532
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.532                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.605
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.605                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.960
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.911 r     8.871                    
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0]           cell (LUT5)             0.424 r     9.295
+ u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.672 r     9.967      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_213.f[1]                                cell (LUT5)             0.424 r    10.391
+ u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.515 r    10.906      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_210.f[0]                                cell (LUT5)             0.431 r    11.337
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 4)       0.468 r    11.805      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5)        0.732      12.537
+ Arrival time                                                                       12.537                  (6 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
@@ -1442,16 +1292,68 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  clock recovergence pessimism                                                        0.095      22.857
  Required time                                                                      22.857            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              10.740ns          
+ Slack                                                                              10.320ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     10.763 ns                                                       
+ Slack (setup check):     10.320 ns                                                       
  Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
  End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         10.027ns  (logic 6.388ns, net 3.639ns, 63% logic)               
+ Data Path Delay:         10.470ns  (logic 6.651ns, net 3.819ns, 63% logic)               
+ Logic Levels:            6 ( LUT5=4 ADDER=2 )                                            
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net                     2.067       2.067      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge                                                                   0.000       2.067
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q                   3.433 r     5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net  (fanout = 1)       1.253 r     6.753                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.706 r     7.459
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     7.459                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     7.532
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.532                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.605
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.605                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.960
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.911 r     8.871                    
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0]           cell (LUT5)             0.424 r     9.295
+ u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.672 r     9.967      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_213.f[1]                                cell (LUT5)             0.424 r    10.391
+ u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.515 r    10.906      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_210.f[0]                                cell (LUT5)             0.431 r    11.337
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 4)       0.468 r    11.805      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5)        0.732      12.537
+ Arrival time                                                                       12.537                  (6 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
+ uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ capture clock edge                                                                 20.833      22.878
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116      22.762
+ clock uncertainty                                                                  -0.000      22.762
+ clock recovergence pessimism                                                        0.095      22.857
+ Required time                                                                      22.857            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                              10.320ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     10.553 ns                                                       
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (rising edge triggered by clock b_pclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         10.237ns  (logic 6.578ns, net 3.659ns, 64% logic)               
  Logic Levels:            6 ( LUT5=4 ADDER=2 )                                            
 
  Point                                                       Type                     Incr        Path      Info          
@@ -1464,21 +1366,21 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  launch clock edge                                                                   0.000       2.067
 ---------------------------------------------------------------------------------------------------------
  sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[3] clk2q                   3.433 r     5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net  (fanout = 1)       0.930 r     6.430                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.706 r     7.136
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.136                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.209
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.209                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.564
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.827 r     8.391                    
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0]           cell (LUT5)             0.424 r     8.815
- u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.615 r     9.430      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg3_syn_167.f[0]                                 cell (LUT5)             0.424 r     9.854
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.603 r    10.457      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0]         cell (LUT5)             0.431 r    10.888
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 3)       0.664 r    11.552      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5)        0.542      12.094
- Arrival time                                                                       12.094                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net  (fanout = 1)       1.093 r     6.593                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.706 r     7.299
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.299                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.372
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.372                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.727
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.911 r     8.638                    
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0]           cell (LUT5)             0.424 r     9.062
+ u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.672 r     9.734      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_213.f[1]                                cell (LUT5)             0.424 r    10.158
+ u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.515 r    10.673      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_210.f[0]                                cell (LUT5)             0.431 r    11.104
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 4)       0.468 r    11.572      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5)        0.732      12.304
+ Arrival time                                                                       12.304                  (6 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
@@ -1492,66 +1394,18 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  clock recovergence pessimism                                                        0.095      22.857
  Required time                                                                      22.857            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              10.763ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     10.810 ns                                                       
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (rising edge triggered by clock b_pclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         9.980ns  (logic 6.236ns, net 3.744ns, 62% logic)                
- Logic Levels:            6 ( LUT5=4 ADDER=2 )                                            
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net                     2.067       2.067      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       2.067
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[6] clk2q                   3.433 r     5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10]) net  (fanout = 1)       1.035 r     6.535                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.627 r     7.162
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.162                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.517
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.827 r     8.344                    
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0]           cell (LUT5)             0.424 r     8.768
- u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.615 r     9.383      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg3_syn_167.f[0]                                 cell (LUT5)             0.424 r     9.807
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.603 r    10.410      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0]         cell (LUT5)             0.431 r    10.841
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 3)       0.664 r    11.505      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25 path2reg0 (LUT5)        0.542      12.047
- Arrival time                                                                       12.047                  (6 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                 20.833      22.878
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116      22.762
- clock uncertainty                                                                  -0.000      22.762
- clock recovergence pessimism                                                        0.095      22.857
- Required time                                                                      22.857            
----------------------------------------------------------------------------------------------------------
- Slack                                                                              10.810ns          
+ Slack                                                                              10.553ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 (171 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     10.755 ns                                                       
+ Slack (setup check):     10.320 ns                                                       
  Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
  End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         10.035ns  (logic 6.645ns, net 3.390ns, 66% logic)               
+ Data Path Delay:         10.470ns  (logic 6.651ns, net 3.819ns, 63% logic)               
  Logic Levels:            6 ( LUT5=4 ADDER=2 )                                            
 
  Point                                                       Type                     Incr        Path      Info          
@@ -1563,26 +1417,24 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net                     2.067       2.067      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.067
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q                   3.433 r     5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       0.886 r     6.386                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     7.013
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     7.013                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.073 r     7.086
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     7.086                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     7.159
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.159                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.232
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.232                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.587
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.827 r     8.414                    
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0]           cell (LUT5)             0.424 r     8.838
- u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.615 r     9.453      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg3_syn_167.f[0]                                 cell (LUT5)             0.424 r     9.877
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.603 r    10.480      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0]         cell (LUT5)             0.431 r    10.911
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 3)       0.459 r    11.370      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5)        0.732      12.102
- Arrival time                                                                       12.102                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q                   3.433 r     5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net  (fanout = 1)       1.253 r     6.753                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.706 r     7.459
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     7.459                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     7.532
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.532                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.605
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.605                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.960
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.911 r     8.871                    
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0]           cell (LUT5)             0.424 r     9.295
+ u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.672 r     9.967      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_213.f[1]                                cell (LUT5)             0.424 r    10.391
+ u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.515 r    10.906      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_210.f[0]                                cell (LUT5)             0.431 r    11.337
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 4)       0.468 r    11.805      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5)        0.732      12.537
+ Arrival time                                                                       12.537                  (6 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
@@ -1596,16 +1448,16 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  clock recovergence pessimism                                                        0.095      22.857
  Required time                                                                      22.857            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              10.755ns          
+ Slack                                                                              10.320ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     10.755 ns                                                       
+ Slack (setup check):     10.320 ns                                                       
  Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
  End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         10.035ns  (logic 6.645ns, net 3.390ns, 66% logic)               
+ Data Path Delay:         10.470ns  (logic 6.651ns, net 3.819ns, 63% logic)               
  Logic Levels:            6 ( LUT5=4 ADDER=2 )                                            
 
  Point                                                       Type                     Incr        Path      Info          
@@ -1617,26 +1469,24 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (uu_pll_lvds/clk0_out) net                     2.067       2.067      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.067
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[0] clk2q                   3.433 r     5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]) net  (fanout = 1)       0.886 r     6.386                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.fco cell (ADDER)            0.627 r     7.013
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45) net  (fanout = 1)       0.000 f     7.013                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.073 r     7.086
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     7.086                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     7.159
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.159                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.232
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.232                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.587
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.827 r     8.414                    
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0]           cell (LUT5)             0.424 r     8.838
- u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.615 r     9.453      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg3_syn_167.f[0]                                 cell (LUT5)             0.424 r     9.877
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.603 r    10.480      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0]         cell (LUT5)             0.431 r    10.911
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 3)       0.459 r    11.370      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5)        0.732      12.102
- Arrival time                                                                       12.102                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[1] clk2q                   3.433 r     5.500
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5]) net  (fanout = 1)       1.253 r     6.753                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fco cell (ADDER)            0.706 r     7.459
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47) net  (fanout = 1)       0.000 f     7.459                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.073 r     7.532
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.532                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.605
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.605                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.960
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.911 r     8.871                    
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0]           cell (LUT5)             0.424 r     9.295
+ u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.672 r     9.967      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_213.f[1]                                cell (LUT5)             0.424 r    10.391
+ u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.515 r    10.906      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_210.f[0]                                cell (LUT5)             0.431 r    11.337
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 4)       0.468 r    11.805      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5)        0.732      12.537
+ Arrival time                                                                       12.537                  (6 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
@@ -1650,16 +1500,16 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  clock recovergence pessimism                                                        0.095      22.857
  Required time                                                                      22.857            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              10.755ns          
+ Slack                                                                              10.320ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     10.778 ns                                                       
+ Slack (setup check):     10.553 ns                                                       
  Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk (rising edge triggered by clock b_pclk)
  End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         10.012ns  (logic 6.578ns, net 3.434ns, 65% logic)               
+ Data Path Delay:         10.237ns  (logic 6.578ns, net 3.659ns, 64% logic)               
  Logic Levels:            6 ( LUT5=4 ADDER=2 )                                            
 
  Point                                                       Type                     Incr        Path      Info          
@@ -1672,21 +1522,21 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  launch clock edge                                                                   0.000       2.067
 ---------------------------------------------------------------------------------------------------------
  sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.p[3] clk2q                   3.433 r     5.500
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net  (fanout = 1)       0.930 r     6.430                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.706 r     7.136
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.136                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.209
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.209                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.564
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.827 r     8.391                    
- u_bus_top/u_local_bus_slve_cis/reg50_syn_201.f[0]           cell (LUT5)             0.424 r     8.815
- u_bus_top/reg3_syn_167.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.615 r     9.430      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_bus_top/reg3_syn_167.f[0]                                 cell (LUT5)             0.424 r     9.854
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.603 r    10.457      ../../../../hg_mp/fe/fifo_adc.v(36)
- u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.f[0]         cell (LUT5)             0.431 r    10.888
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 3)       0.459 r    11.347      ../../../../hg_mp/fe/fifo_adc.v(36)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5)        0.732      12.079
- Arrival time                                                                       12.079                  (6 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7]) net  (fanout = 1)       1.093 r     6.593                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fco cell (ADDER)            0.706 r     7.299
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49) net  (fanout = 1)       0.000 f     7.299                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fco cell (ADDER)            0.073 r     7.372
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51) net  (fanout = 1)       0.000 f     7.372                    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.f[1] cell (ADDER)            0.355 r     7.727
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12]) net  (fanout = 2)       0.911 r     8.638                    
+ u_bus_top/u_local_bus_slve_cis/reg49_syn_201.f[0]           cell (LUT5)             0.424 r     9.062
+ u_bus_top/reg14_syn_213.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232) net  (fanout = 1)       0.672 r     9.734      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_213.f[1]                                cell (LUT5)             0.424 r    10.158
+ u_bus_top/reg14_syn_210.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236) net  (fanout = 1)       0.515 r    10.673      ../../../../hg_mp/fe/fifo_adc.v(36)
+ u_bus_top/reg14_syn_210.f[0]                                cell (LUT5)             0.431 r    11.104
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242) net  (fanout = 4)       0.468 r    11.572      ../../../../hg_mp/fe/fifo_adc.v(36)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21 path2reg0 (LUT5)        0.732      12.304
+ Arrival time                                                                       12.304                  (6 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
@@ -1700,19 +1550,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_
  clock recovergence pessimism                                                        0.095      22.857
  Required time                                                                      22.857            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              10.778ns          
+ Slack                                                                              10.553ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_77 (214 paths)
+Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_89 (214 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     12.253 ns                                                       
- Start Point:             exdev_ctl_b/u_gen_sp/reg9_syn_78.clk (rising edge triggered by clock b_pclk)
- End Point:               exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (rising edge triggered by clock b_pclk)
+ Slack (setup check):     12.376 ns                                                       
+ Start Point:             exdev_ctl_b/u_gen_sp/reg9_syn_73.clk (rising edge triggered by clock b_pclk)
+ End Point:               exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         8.329ns  (logic 3.667ns, net 4.662ns, 44% logic)                
- Logic Levels:            7 ( LUT5=4 ADDER=2 LUT2=1 )                                     
+ Data Path Delay:         8.206ns  (logic 4.304ns, net 3.902ns, 52% logic)                
+ Logic Levels:            8 ( LUT5=5 ADDER=2 LUT4=1 )                                     
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -1720,33 +1570,39 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_77 (214 paths)
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- exdev_ctl_b/u_gen_sp/reg9_syn_78.clk (uu_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg9_syn_73.clk (uu_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_78.q[1]                       clk2q                   0.146 r     2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_104.a[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[7]) net  (fanout = 1)       0.803 r     3.225      ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco                       cell (ADDER)            0.947 r     4.172
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net  (fanout = 1)       0.000 f     4.172      ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0]                     cell (ADDER)            0.387 r     4.559
- u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net  (fanout = 1)       0.648 r     5.207                    
- u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.f[1]         cell (LUT5)             0.424 r     5.631
- exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_138) net  (fanout = 1)       0.738 r     6.369      ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg9_syn_69.f[0]                       cell (LUT5)             0.424 r     6.793
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_140) net  (fanout = 1)       0.456 r     7.249      ../../../../hg_mp/fe/gen_sp.v(137)
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.f[1]          cell (LUT5)             0.424 r     7.673
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_148) net  (fanout = 1)       0.468 r     8.141      ../../../../hg_mp/fe/gen_sp.v(137)
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.f[1]          cell (LUT5)             0.424 r     8.565
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net  (fanout = 1)       0.676 r     9.241                    
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.f[0]          cell (LUT2)             0.348 r     9.589
- exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net  (fanout = 8)       0.873 r    10.462      ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_77                            path2reg                0.143      10.605
- Arrival time                                                                       10.605                  (7 lvl)       
+ exdev_ctl_b/u_gen_sp/reg9_syn_73.q[1]                       clk2q                   0.146 r     2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net  (fanout = 1)       0.625 r     3.047      ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.fco                       cell (ADDER)            0.836 r     3.883
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net  (fanout = 1)       0.000 f     3.883      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fco                       cell (ADDER)            0.132 r     4.015
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net  (fanout = 1)       0.000 f     4.015      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco                       cell (ADDER)            0.132 r     4.147
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net  (fanout = 1)       0.000 f     4.147      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0]                     cell (ADDER)            0.387 r     4.534
+ exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net  (fanout = 1)       0.941 r     5.475                    
+ exdev_ctl_b/u_gen_sp/reg9_syn_80.f[0]                       cell (LUT4)             0.408 r     5.883
+ sampling_fe_b/reg1_syn_48.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_135) net  (fanout = 1)       0.309 r     6.192      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg1_syn_48.f[1]                              cell (LUT5)             0.424 r     6.616
+ sampling_fe_b/reg1_syn_51.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net  (fanout = 1)       0.456 r     7.072      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg1_syn_51.f[1]                              cell (LUT5)             0.424 r     7.496
+ sampling_fe_b/reg2_syn_46.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net  (fanout = 1)       0.307 r     7.803      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg2_syn_46.f[1]                              cell (LUT5)             0.424 r     8.227
+ sampling_fe_b/reg2_syn_46.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net  (fanout = 1)       0.158 r     8.385                    
+ sampling_fe_b/reg2_syn_46.f[0]                              cell (LUT5)             0.424 r     8.809
+ sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net  (fanout = 1)       0.456 r     9.265                    
+ sampling_fe_b/u_ad_sampling/reg2_syn_56.f[1]                cell (LUT5)             0.424 r     9.689
+ exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net  (fanout = 8)       0.650 r    10.339      ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_89                            path2reg                0.143      10.482
+ Arrival time                                                                       10.482                  (8 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- exdev_ctl_b/u_gen_sp/reg0_syn_77.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_89.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.187      22.691
@@ -1754,17 +1610,17 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_77 (214 paths)
  clock recovergence pessimism                                                        0.167      22.858
  Required time                                                                      22.858            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              12.253ns          
+ Slack                                                                              12.376ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     12.379 ns                                                       
- Start Point:             exdev_ctl_b/u_gen_sp/reg9_syn_92.clk (rising edge triggered by clock b_pclk)
- End Point:               exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (rising edge triggered by clock b_pclk)
+ Slack (setup check):     12.465 ns                                                       
+ Start Point:             exdev_ctl_b/u_gen_sp/reg9_syn_77.clk (rising edge triggered by clock b_pclk)
+ End Point:               exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         8.203ns  (logic 3.865ns, net 4.338ns, 47% logic)                
- Logic Levels:            7 ( LUT5=4 ADDER=2 LUT2=1 )                                     
+ Data Path Delay:         8.145ns  (logic 4.349ns, net 3.796ns, 53% logic)                
+ Logic Levels:            8 ( LUT5=5 ADDER=2 LUT4=1 )                                     
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -1772,55 +1628,57 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_77 (214 paths)
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- exdev_ctl_b/u_gen_sp/reg9_syn_92.clk (uu_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg9_syn_77.clk (uu_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_92.q[0]                       clk2q                   0.146 r     2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[1]) net  (fanout = 1)       0.479 r     2.901      ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_102.fco                       cell (ADDER)            0.881 r     3.782
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net  (fanout = 1)       0.000 f     3.782      ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fco                       cell (ADDER)            0.132 r     3.914
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net  (fanout = 1)       0.000 f     3.914      ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco                       cell (ADDER)            0.132 r     4.046
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net  (fanout = 1)       0.000 f     4.046      ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0]                     cell (ADDER)            0.387 r     4.433
- u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net  (fanout = 1)       0.648 r     5.081                    
- u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.f[1]         cell (LUT5)             0.424 r     5.505
- exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_138) net  (fanout = 1)       0.738 r     6.243      ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg9_syn_69.f[0]                       cell (LUT5)             0.424 r     6.667
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_140) net  (fanout = 1)       0.456 r     7.123      ../../../../hg_mp/fe/gen_sp.v(137)
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.f[1]          cell (LUT5)             0.424 r     7.547
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_148) net  (fanout = 1)       0.468 r     8.015      ../../../../hg_mp/fe/gen_sp.v(137)
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.f[1]          cell (LUT5)             0.424 r     8.439
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net  (fanout = 1)       0.676 r     9.115                    
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.f[0]          cell (LUT2)             0.348 r     9.463
- exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net  (fanout = 8)       0.873 r    10.336      ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_77                            path2reg                0.143      10.479
- Arrival time                                                                       10.479                  (7 lvl)       
+ exdev_ctl_b/u_gen_sp/reg9_syn_77.q[1]                       clk2q                   0.146 r     2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1] (exdev_ctl_b/u_gen_sp/sp_t_d1[1]) net  (fanout = 1)       0.519 r     2.941      ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_102.fco                       cell (ADDER)            0.881 r     3.822
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net  (fanout = 1)       0.000 f     3.822      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fco                       cell (ADDER)            0.132 r     3.954
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net  (fanout = 1)       0.000 f     3.954      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco                       cell (ADDER)            0.132 r     4.086
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net  (fanout = 1)       0.000 f     4.086      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0]                     cell (ADDER)            0.387 r     4.473
+ exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net  (fanout = 1)       0.941 r     5.414                    
+ exdev_ctl_b/u_gen_sp/reg9_syn_80.f[0]                       cell (LUT4)             0.408 r     5.822
+ sampling_fe_b/reg1_syn_48.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_135) net  (fanout = 1)       0.309 r     6.131      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg1_syn_48.f[1]                              cell (LUT5)             0.424 r     6.555
+ sampling_fe_b/reg1_syn_51.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net  (fanout = 1)       0.456 r     7.011      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg1_syn_51.f[1]                              cell (LUT5)             0.424 r     7.435
+ sampling_fe_b/reg2_syn_46.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net  (fanout = 1)       0.307 r     7.742      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg2_syn_46.f[1]                              cell (LUT5)             0.424 r     8.166
+ sampling_fe_b/reg2_syn_46.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net  (fanout = 1)       0.158 r     8.324                    
+ sampling_fe_b/reg2_syn_46.f[0]                              cell (LUT5)             0.424 r     8.748
+ sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net  (fanout = 1)       0.456 r     9.204                    
+ sampling_fe_b/u_ad_sampling/reg2_syn_56.f[1]                cell (LUT5)             0.424 r     9.628
+ exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net  (fanout = 8)       0.650 r    10.278      ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_89                            path2reg                0.143      10.421
+ Arrival time                                                                       10.421                  (8 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- exdev_ctl_b/u_gen_sp/reg0_syn_77.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_89.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.187      22.691
  clock uncertainty                                                                  -0.000      22.691
- clock recovergence pessimism                                                        0.167      22.858
- Required time                                                                      22.858            
+ clock recovergence pessimism                                                        0.195      22.886
+ Required time                                                                      22.886            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              12.379ns          
+ Slack                                                                              12.465ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     12.427 ns                                                       
- Start Point:             exdev_ctl_b/u_gen_sp/reg9_syn_90.clk (rising edge triggered by clock b_pclk)
- End Point:               exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (rising edge triggered by clock b_pclk)
+ Slack (setup check):     12.546 ns                                                       
+ Start Point:             exdev_ctl_b/u_gen_sp/reg9_syn_97.clk (rising edge triggered by clock b_pclk)
+ End Point:               exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         8.155ns  (logic 3.820ns, net 4.335ns, 46% logic)                
- Logic Levels:            7 ( LUT5=4 ADDER=2 LUT2=1 )                                     
+ Data Path Delay:         8.036ns  (logic 4.283ns, net 3.753ns, 53% logic)                
+ Logic Levels:            8 ( LUT5=5 ADDER=2 LUT4=1 )                                     
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -1828,37 +1686,37 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_77 (214 paths)
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- exdev_ctl_b/u_gen_sp/reg9_syn_90.clk (uu_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg9_syn_97.clk (uu_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- exdev_ctl_b/u_gen_sp/reg9_syn_90.q[1]                       clk2q                   0.146 r     2.422
- exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[0]) net  (fanout = 1)       0.476 r     2.898      ../../../../hg_mp/fe/gen_sp.v(87)
- exdev_ctl_b/u_gen_sp/sub1_syn_102.fco                       cell (ADDER)            0.836 r     3.734
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fci (exdev_ctl_b/u_gen_sp/sub1_syn_87) net  (fanout = 1)       0.000 f     3.734      ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_103.fco                       cell (ADDER)            0.132 r     3.866
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net  (fanout = 1)       0.000 f     3.866      ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_104.fco                       cell (ADDER)            0.132 r     3.998
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net  (fanout = 1)       0.000 f     3.998      ../../../../hg_mp/fe/gen_sp.v(142)
- exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0]                     cell (ADDER)            0.387 r     4.385
- u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net  (fanout = 1)       0.648 r     5.033                    
- u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.f[1]         cell (LUT5)             0.424 r     5.457
- exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0] (exdev_ctl_b/u_gen_sp/mux31_syn_138) net  (fanout = 1)       0.738 r     6.195      ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg9_syn_69.f[0]                       cell (LUT5)             0.424 r     6.619
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_140) net  (fanout = 1)       0.456 r     7.075      ../../../../hg_mp/fe/gen_sp.v(137)
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.f[1]          cell (LUT5)             0.424 r     7.499
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_148) net  (fanout = 1)       0.468 r     7.967      ../../../../hg_mp/fe/gen_sp.v(137)
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.f[1]          cell (LUT5)             0.424 r     8.391
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net  (fanout = 1)       0.676 r     9.067                    
- u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.f[0]          cell (LUT2)             0.348 r     9.415
- exdev_ctl_b/u_gen_sp/reg0_syn_77.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net  (fanout = 8)       0.873 r    10.288      ../../../../hg_mp/fe/gen_sp.v(137)
- exdev_ctl_b/u_gen_sp/reg0_syn_77                            path2reg                0.143      10.431
- Arrival time                                                                       10.431                  (7 lvl)       
+ exdev_ctl_b/u_gen_sp/reg9_syn_97.q[1]                       clk2q                   0.146 r     2.422
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.a[0] (exdev_ctl_b/u_gen_sp/sp_t_d1[3]) net  (fanout = 1)       0.476 r     2.898      ../../../../hg_mp/fe/gen_sp.v(87)
+ exdev_ctl_b/u_gen_sp/sub1_syn_103.fco                       cell (ADDER)            0.947 r     3.845
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fci (exdev_ctl_b/u_gen_sp/sub1_syn_91) net  (fanout = 1)       0.000 f     3.845      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_104.fco                       cell (ADDER)            0.132 r     3.977
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fci (exdev_ctl_b/u_gen_sp/sub1_syn_95) net  (fanout = 1)       0.000 f     3.977      ../../../../hg_mp/fe/gen_sp.v(142)
+ exdev_ctl_b/u_gen_sp/sub1_syn_105.fx[0]                     cell (ADDER)            0.387 r     4.364
+ exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12]) net  (fanout = 1)       0.941 r     5.305                    
+ exdev_ctl_b/u_gen_sp/reg9_syn_80.f[0]                       cell (LUT4)             0.408 r     5.713
+ sampling_fe_b/reg1_syn_48.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_135) net  (fanout = 1)       0.309 r     6.022      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg1_syn_48.f[1]                              cell (LUT5)             0.424 r     6.446
+ sampling_fe_b/reg1_syn_51.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_141) net  (fanout = 1)       0.456 r     6.902      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg1_syn_51.f[1]                              cell (LUT5)             0.424 r     7.326
+ sampling_fe_b/reg2_syn_46.a[1] (exdev_ctl_b/u_gen_sp/mux31_syn_143) net  (fanout = 1)       0.307 r     7.633      ../../../../hg_mp/fe/gen_sp.v(137)
+ sampling_fe_b/reg2_syn_46.f[1]                              cell (LUT5)             0.424 r     8.057
+ sampling_fe_b/reg2_syn_46.a[0] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1) net  (fanout = 1)       0.158 r     8.215                    
+ sampling_fe_b/reg2_syn_46.f[0]                              cell (LUT5)             0.424 r     8.639
+ sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1] (exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2) net  (fanout = 1)       0.456 r     9.095                    
+ sampling_fe_b/u_ad_sampling/reg2_syn_56.f[1]                cell (LUT5)             0.424 r     9.519
+ exdev_ctl_b/u_gen_sp/reg0_syn_89.sr (exdev_ctl_b/u_gen_sp/mux31_syn_19) net  (fanout = 8)       0.650 r    10.169      ../../../../hg_mp/fe/gen_sp.v(137)
+ exdev_ctl_b/u_gen_sp/reg0_syn_89                            path2reg                0.143      10.312
+ Arrival time                                                                       10.312                  (8 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- exdev_ctl_b/u_gen_sp/reg0_syn_77.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/u_gen_sp/reg0_syn_89.clk (uu_pll_lvds/clk0_out) net                     2.045       2.045      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                 20.833      22.878
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.187      22.691
@@ -1866,20 +1724,20 @@ Paths for end point exdev_ctl_b/u_gen_sp/reg0_syn_77 (214 paths)
  clock recovergence pessimism                                                        0.167      22.858
  Required time                                                                      22.858            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              12.427ns          
+ Slack                                                                              12.546ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Hold checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 (10 paths)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 (10 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.114 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[12] (rising edge triggered by clock b_pclk)
+ Slack (hold check):      0.130 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[11] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.359ns  (logic 0.109ns, net 0.250ns, 30% logic)                
+ Data Path Delay:         0.375ns  (logic 0.109ns, net 0.266ns, 29% logic)                
  Logic Levels:            1 ( EMB=1 )                                                     
 
  Point                                                       Type                     Incr        Path      Info          
@@ -1888,19 +1746,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/in
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.q[0] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[12] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[39]) net  (fanout = 2)       0.250 r     2.297      ../../../../hg_mp/fe/prebuffer_rev.v(331)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB)          0.000       2.297
- Arrival time                                                                        2.297                  (1 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.q[1] clk2q                   0.109 r     2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[11] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[28]) net  (fanout = 2)       0.266 r     2.313      ../../../../hg_mp/fe/prebuffer_rev.v(331)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB)          0.000       2.313
+ Arrival time                                                                        2.313                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -1908,51 +1766,13 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/in
  clock recovergence pessimism                                                       -0.147       2.183
  Required time                                                                       2.183            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.114ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.114 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11] (rising edge triggered by clock b_pclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.359ns  (logic 0.109ns, net 0.250ns, 30% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.q[0] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[38]) net  (fanout = 2)       0.250 r     2.297      ../../../../hg_mp/fe/prebuffer_rev.v(331)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB)          0.000       2.297
- Arrival time                                                                        2.297                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.114ns          
+ Slack                                                                               0.130ns          
 
 ---------------------------------------------------------------------------------------------------------
 
  Slack (hold check):      0.195 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[3] (rising edge triggered by clock b_pclk)
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[3] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.440ns  (logic 0.109ns, net 0.331ns, 24% logic)                
@@ -1964,19 +1784,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/in
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.q[1] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[30]) net  (fanout = 2)       0.331 r     2.378      ../../../../hg_mp/fe/prebuffer_rev.v(331)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1 path2reg (EMB)          0.000       2.378
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.q[1] clk2q                   0.109 r     2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[20]) net  (fanout = 2)       0.331 r     2.378      ../../../../hg_mp/fe/prebuffer_rev.v(331)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB)          0.000       2.378
  Arrival time                                                                        2.378                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -1988,14 +1808,12 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/in
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.147 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[4] (rising edge triggered by clock b_pclk)
+ Slack (hold check):      0.248 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.392ns  (logic 0.109ns, net 0.283ns, 27% logic)                
+ Data Path Delay:         0.493ns  (logic 0.109ns, net 0.384ns, 22% logic)                
  Logic Levels:            1 ( EMB=1 )                                                     
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2004,19 +1822,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/in
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.q[0] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[12]) net  (fanout = 2)       0.283 r     2.330      ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB)          0.000       2.330
- Arrival time                                                                        2.330                  (1 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.q[1] clk2q                   0.109 r     2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[23]) net  (fanout = 2)       0.384 r     2.431      ../../../../hg_mp/fe/prebuffer_rev.v(331)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1 path2reg (EMB)          0.000       2.431
+ Arrival time                                                                        2.431                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -2024,16 +1842,18 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/in
  clock recovergence pessimism                                                       -0.147       2.183
  Required time                                                                       2.183            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.147ns          
+ Slack                                                                               0.248ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.186 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[7] (rising edge triggered by clock b_pclk)
+Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 (8 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      0.130 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[3] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.431ns  (logic 0.109ns, net 0.322ns, 25% logic)                
+ Data Path Delay:         0.375ns  (logic 0.109ns, net 0.266ns, 29% logic)                
  Logic Levels:            1 ( EMB=1 )                                                     
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2042,19 +1862,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/in
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.q[0] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[7] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[15]) net  (fanout = 2)       0.322 r     2.369      ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB)          0.000       2.369
- Arrival time                                                                        2.369                  (1 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.q[1] clk2q                   0.109 r     2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[3] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[19]) net  (fanout = 2)       0.266 r     2.313      ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB)          0.000       2.313
+ Arrival time                                                                        2.313                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -2062,16 +1882,16 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/in
  clock recovergence pessimism                                                       -0.147       2.183
  Required time                                                                       2.183            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.186ns          
+ Slack                                                                               0.130ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.186 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[5] (rising edge triggered by clock b_pclk)
+ Slack (hold check):      0.232 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[4] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.431ns  (logic 0.109ns, net 0.322ns, 25% logic)                
+ Data Path Delay:         0.477ns  (logic 0.109ns, net 0.368ns, 22% logic)                
  Logic Levels:            1 ( EMB=1 )                                                     
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2080,19 +1900,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/in
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.q[1] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[5] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[13]) net  (fanout = 2)       0.322 r     2.369      ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1 path2reg (EMB)          0.000       2.369
- Arrival time                                                                        2.369                  (1 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.q[0] clk2q                   0.109 r     2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[4] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[20]) net  (fanout = 2)       0.368 r     2.415      ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB)          0.000       2.415
+ Arrival time                                                                        2.415                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -2100,18 +1920,16 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/in
  clock recovergence pessimism                                                       -0.147       2.183
  Required time                                                                       2.183            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.186ns          
+ Slack                                                                               0.232ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 (8 paths)
----------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.186 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[7] (rising edge triggered by clock b_pclk)
+ Slack (hold check):      0.236 ns                                                        
+ Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk (rising edge triggered by clock b_pclk)
+ End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[5] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.431ns  (logic 0.109ns, net 0.322ns, 25% logic)                
+ Data Path Delay:         0.481ns  (logic 0.109ns, net 0.372ns, 22% logic)                
  Logic Levels:            1 ( EMB=1 )                                                     
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2120,19 +1938,19 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.q[0] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[7] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[47]) net  (fanout = 2)       0.322 r     2.369      ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB)          0.000       2.369
- Arrival time                                                                        2.369                  (1 lvl)       
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.q[0] clk2q                   0.109 r     2.047
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[5] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[21]) net  (fanout = 2)       0.372 r     2.419      ../../../../hg_mp/fe/prebuffer_rev.v(329)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1 path2reg (EMB)          0.000       2.419
+ Arrival time                                                                        2.419                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.200       2.330
@@ -2140,83 +1958,45 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
  clock recovergence pessimism                                                       -0.147       2.183
  Required time                                                                       2.183            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.186ns          
+ Slack                                                                               0.236ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.311 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1] (rising edge triggered by clock b_pclk)
+Paths for end point exdev_ctl_b/reg3_syn_190 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      0.167 ns                                                        
+ Start Point:             u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk (rising edge triggered by clock clk_adc)
+ End Point:               exdev_ctl_b/reg3_syn_190.mi[1] (rising edge triggered by clock b_pclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.556ns  (logic 0.109ns, net 0.447ns, 19% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
+ Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
+ Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk (exdev_ctl_a/clk_adc) net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.q[0] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[41]) net  (fanout = 2)       0.447 r     2.494      ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB)          0.000       2.494
- Arrival time                                                                        2.494                  (1 lvl)       
+ u_bus_top/u_local_bus_slve_cis/reg42_syn_205.q[0]           clk2q                   0.109 r     2.047
+ exdev_ctl_b/reg3_syn_190.mi[1] (u_bus_top/u_local_bus_slve_cis/reg21[2]) net  (fanout = 2)       0.216 r     2.263      ../../../../hg_mp/local_bus/local_bus_slve_cis.v(75)
+ exdev_ctl_b/reg3_syn_190                                    path2reg1               0.095       2.358
+ Arrival time                                                                        2.358                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
  uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
  uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ exdev_ctl_b/reg3_syn_190.clk (uu_pll_lvds/clk0_out)         net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
+ cell hold                                                                           0.061       2.191
+ clock uncertainty                                                                   0.000       2.191
+ clock recovergence pessimism                                                        0.000       2.191
+ Required time                                                                       2.191            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.311ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.411 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[5] (rising edge triggered by clock b_pclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.656ns  (logic 0.109ns, net 0.547ns, 16% logic)                
- Logic Levels:            1 ( EMB=1 )                                                     
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk (uu_pll_lvds/clk0_out) net                     1.938       1.938      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       1.938
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.q[1] clk2q                   0.109 r     2.047
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[5] (sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[45]) net  (fanout = 2)       0.547 r     2.594      ../../../../hg_mp/fe/prebuffer_rev.v(329)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1 path2reg (EMB)          0.000       2.594
- Arrival time                                                                        2.594                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clka (uu_pll_lvds/clk0_out) net                     2.130       2.130      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- capture clock edge                                                                  0.000       2.130
----------------------------------------------------------------------------------------------------------
- cell hold                                                                           0.200       2.330
- clock uncertainty                                                                   0.000       2.330
- clock recovergence pessimism                                                       -0.147       2.183
- Required time                                                                       2.183            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.411ns          
+ Slack                                                                               0.167ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -2225,34 +2005,242 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/in
 Timing constraint:        clock: b_sclk                                                   
 Clock = b_sclk, period 5.952ns, rising at 0ns, falling at 2.976ns
 
-282 endpoints analyzed totally, and 706 paths analyzed
+282 endpoints analyzed totally, and 714 paths analyzed
 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.158ns
+Minimum period is 2.08ns
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point ub_lvds_rx/reg3_syn_179 (5 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     3.872 ns                                                        
+ Start Point:             ub_lvds_rx/reg8_syn_219.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/reg3_syn_179.b[0] (rising edge triggered by clock b_sclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.900ns  (logic 0.695ns, net 1.205ns, 36% logic)                
+ Logic Levels:            1 ( LUT5=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg8_syn_219.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg8_syn_219.q[0]                                clk2q                   0.146 r     2.422
+ ub_lvds_rx/reg3_syn_179.b[0] (ub_lvds_rx/rx_data[26])       net  (fanout = 4)       1.205 r     3.627      encrypted_text(0)
+ ub_lvds_rx/reg3_syn_179                                     path2reg0 (LUT5)        0.549       4.176
+ Arrival time                                                                        4.176                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg3_syn_179.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  5.952       7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       7.881
+ clock uncertainty                                                                  -0.000       7.881
+ clock recovergence pessimism                                                        0.167       8.048
+ Required time                                                                       8.048            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               3.872ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     4.385 ns                                                        
+ Start Point:             ub_lvds_rx/reg8_syn_163.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/reg3_syn_179.c[0] (rising edge triggered by clock b_sclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.387ns  (logic 0.612ns, net 0.775ns, 44% logic)                
+ Logic Levels:            1 ( LUT5=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg8_syn_163.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg8_syn_163.q[1]                                clk2q                   0.146 r     2.422
+ ub_lvds_rx/reg3_syn_179.c[0] (ub_lvds_rx/rx_data[27])       net  (fanout = 3)       0.775 r     3.197      encrypted_text(0)
+ ub_lvds_rx/reg3_syn_179                                     path2reg0 (LUT5)        0.466       3.663
+ Arrival time                                                                        3.663                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg3_syn_179.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  5.952       7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       7.881
+ clock uncertainty                                                                  -0.000       7.881
+ clock recovergence pessimism                                                        0.167       8.048
+ Required time                                                                       8.048            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               4.385ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     4.636 ns                                                        
+ Start Point:             ub_lvds_rx/reg8_syn_197.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/reg3_syn_179.d[0] (rising edge triggered by clock b_sclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.136ns  (logic 0.517ns, net 0.619ns, 45% logic)                
+ Logic Levels:            1 ( LUT5=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg8_syn_197.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg8_syn_197.q[0]                                clk2q                   0.146 r     2.422
+ ub_lvds_rx/reg3_syn_179.d[0] (ub_lvds_rx/sync0)             net  (fanout = 44)      0.619 r     3.041      encrypted_text(0)
+ ub_lvds_rx/reg3_syn_179                                     path2reg0 (LUT5)        0.371       3.412
+ Arrival time                                                                        3.412                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg3_syn_179.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  5.952       7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       7.881
+ clock uncertainty                                                                  -0.000       7.881
+ clock recovergence pessimism                                                        0.167       8.048
+ Required time                                                                       8.048            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               4.636ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point ub_lvds_rx/reg3_syn_195 (5 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     4.034 ns                                                        
+ Start Point:             ub_lvds_rx/reg8_syn_197.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/reg3_syn_195.b[0] (rising edge triggered by clock b_sclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.738ns  (logic 0.695ns, net 1.043ns, 39% logic)                
+ Logic Levels:            1 ( LUT5=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg8_syn_197.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg8_syn_197.q[1]                                clk2q                   0.146 r     2.422
+ ub_lvds_rx/reg3_syn_195.b[0] (ub_lvds_rx/rx_data[24])       net  (fanout = 2)       1.043 r     3.465      encrypted_text(0)
+ ub_lvds_rx/reg3_syn_195                                     path2reg0 (LUT5)        0.549       4.014
+ Arrival time                                                                        4.014                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg3_syn_195.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  5.952       7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       7.881
+ clock uncertainty                                                                  -0.000       7.881
+ clock recovergence pessimism                                                        0.167       8.048
+ Required time                                                                       8.048            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               4.034ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     4.636 ns                                                        
+ Start Point:             ub_lvds_rx/reg8_syn_197.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/reg3_syn_195.d[0] (rising edge triggered by clock b_sclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.136ns  (logic 0.517ns, net 0.619ns, 45% logic)                
+ Logic Levels:            1 ( LUT5=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg8_syn_197.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg8_syn_197.q[0]                                clk2q                   0.146 r     2.422
+ ub_lvds_rx/reg3_syn_195.d[0] (ub_lvds_rx/sync0)             net  (fanout = 44)      0.619 r     3.041      encrypted_text(0)
+ ub_lvds_rx/reg3_syn_195                                     path2reg0 (LUT5)        0.371       3.412
+ Arrival time                                                                        3.412                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg3_syn_195.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  5.952       7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       7.881
+ clock uncertainty                                                                  -0.000       7.881
+ clock recovergence pessimism                                                        0.167       8.048
+ Required time                                                                       8.048            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               4.636ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     4.678 ns                                                        
+ Start Point:             ub_lvds_rx/reg8_syn_219.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/reg3_syn_195.c[0] (rising edge triggered by clock b_sclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.094ns  (logic 0.612ns, net 0.482ns, 55% logic)                
+ Logic Levels:            1 ( LUT5=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg8_syn_219.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg8_syn_219.q[1]                                clk2q                   0.146 r     2.422
+ ub_lvds_rx/reg3_syn_195.c[0] (ub_lvds_rx/rx_data[25])       net  (fanout = 4)       0.482 r     2.904      encrypted_text(0)
+ ub_lvds_rx/reg3_syn_195                                     path2reg0 (LUT5)        0.466       3.370
+ Arrival time                                                                        3.370                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg3_syn_195.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  5.952       7.997
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       7.881
+ clock uncertainty                                                                  -0.000       7.881
+ clock recovergence pessimism                                                        0.167       8.048
+ Required time                                                                       8.048            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               4.678ns          
+
 ---------------------------------------------------------------------------------------------------------
 
 Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     3.794 ns                                                        
- Start Point:             ub_lvds_rx/reg7_syn_33.clk (rising edge triggered by clock b_sclk)
+ Slack (setup check):     4.071 ns                                                        
+ Start Point:             ub_lvds_rx/reg7_syn_34.clk (rising edge triggered by clock b_sclk)
  End Point:               ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         2.006ns  (logic 0.948ns, net 1.058ns, 47% logic)                
+ Data Path Delay:         1.701ns  (logic 0.941ns, net 0.760ns, 55% logic)                
  Logic Levels:            2 ( LUT5=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg7_syn_33.clk (ub_lvds_rx/sclk)                net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/reg7_syn_34.clk (ub_lvds_rx/sclk)                net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_33.q[0]                                 clk2q                   0.146 r     2.422
- ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0] (ub_lvds_rx/rx_clk_sft[1]) net  (fanout = 2)       0.602 r     3.024      encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.431 r     3.455
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.456 r     3.911      encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.282
- Arrival time                                                                        4.282                  (2 lvl)       
+ ub_lvds_rx/reg7_syn_34.q[1]                                 clk2q                   0.146 r     2.422
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0] (ub_lvds_rx/rx_clk_sft[0]) net  (fanout = 2)       0.602 r     3.024      encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.424 r     3.448
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.158 r     3.606      encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       3.977
+ Arrival time                                                                        3.977                  (2 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
@@ -2261,34 +2249,32 @@ Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116       7.881
  clock uncertainty                                                                  -0.000       7.881
- clock recovergence pessimism                                                        0.195       8.076
- Required time                                                                       8.076            
+ clock recovergence pessimism                                                        0.167       8.048
+ Required time                                                                       8.048            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               3.794ns          
+ Slack                                                                               4.071ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     4.018 ns                                                        
- Start Point:             ub_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
+ Slack (setup check):     4.371 ns                                                        
+ Start Point:             ub_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/rx_clk_sync_reg_syn_5.b[1] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.797ns  (logic 0.865ns, net 0.932ns, 48% logic)                
- Logic Levels:            2 ( LUT5=1 )                                                    
+ Data Path Delay:         1.444ns  (logic 0.695ns, net 0.749ns, 48% logic)                
+ Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg7_syn_25.clk (ub_lvds_rx/sclk)                net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/reg7_syn_28.clk (ub_lvds_rx/sclk)                net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_25.q[1]                                 clk2q                   0.146 r     2.422
- ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0] (ub_lvds_rx/rx_clk_sft[2]) net  (fanout = 2)       0.476 r     2.898      encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.348 r     3.246
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.456 r     3.702      encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.073
- Arrival time                                                                        4.073                  (2 lvl)       
+ ub_lvds_rx/reg7_syn_28.q[1]                                 clk2q                   0.146 r     2.422
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.b[1] (ub_lvds_rx/rx_clk_sft[5]) net  (fanout = 1)       0.749 r     3.171      encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.549       3.720
+ Arrival time                                                                        3.720                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
@@ -2300,31 +2286,31 @@ Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
  clock recovergence pessimism                                                        0.210       8.091
  Required time                                                                       8.091            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.018ns          
+ Slack                                                                               4.371ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     4.087 ns                                                        
- Start Point:             ub_lvds_rx/reg7_syn_25.clk (rising edge triggered by clock b_sclk)
+ Slack (setup check):     4.382 ns                                                        
+ Start Point:             ub_lvds_rx/reg7_syn_28.clk (rising edge triggered by clock b_sclk)
  End Point:               ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.728ns  (logic 0.799ns, net 0.929ns, 46% logic)                
+ Data Path Delay:         1.433ns  (logic 0.799ns, net 0.634ns, 55% logic)                
  Logic Levels:            2 ( LUT5=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg7_syn_25.clk (ub_lvds_rx/sclk)                net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/reg7_syn_28.clk (ub_lvds_rx/sclk)                net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg7_syn_25.q[0]                                 clk2q                   0.146 r     2.422
- ub_lvds_rx/rx_clk_sync_reg_syn_5.e[0] (ub_lvds_rx/rx_clk_sft[4]) net  (fanout = 2)       0.473 r     2.895      encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.282 r     3.177
- ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.456 r     3.633      encrypted_text(0)
- ub_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       4.004
- Arrival time                                                                        4.004                  (2 lvl)       
+ ub_lvds_rx/reg7_syn_28.q[0]                                 clk2q                   0.146 r     2.422
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.e[0] (ub_lvds_rx/rx_clk_sft[4]) net  (fanout = 2)       0.476 r     2.898      encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.f[0]                       cell (LUT5)             0.282 r     3.180
+ ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1] (ub_lvds_rx/rx_clk_sync_n_syn_2) net  (fanout = 1)       0.158 r     3.338      encrypted_text(0)
+ ub_lvds_rx/rx_clk_sync_reg_syn_5                            path2reg1               0.371       3.709
+ Arrival time                                                                        3.709                  (2 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
@@ -2336,215 +2322,7 @@ Paths for end point ub_lvds_rx/rx_clk_sync_reg_syn_5 (7 paths)
  clock recovergence pessimism                                                        0.210       8.091
  Required time                                                                       8.091            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               4.087ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ub_lvds_rx/reg16_syn_31 (4 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     4.143 ns                                                        
- Start Point:             ub_lvds_rx/para_en_reg_syn_5.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/reg16_syn_31.a[0] (rising edge triggered by clock b_sclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.672ns  (logic 0.688ns, net 0.984ns, 41% logic)                
- Logic Levels:            1 ( LUT4=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/para_en_reg_syn_5.clk (ub_lvds_rx/sclk)          net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/para_en_reg_syn_5.q[1]                           clk2q                   0.146 r     2.422
- ub_lvds_rx/reg16_syn_31.a[0] (ub_lvds_rx/para_en)           net  (fanout = 11)      0.984 r     3.406      encrypted_text(0)
- ub_lvds_rx/reg16_syn_31                                     path2reg0 (LUT4)        0.542       3.948
- Arrival time                                                                        3.948                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       7.997
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       7.881
- clock uncertainty                                                                  -0.000       7.881
- clock recovergence pessimism                                                        0.210       8.091
- Required time                                                                       8.091            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               4.143ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     4.403 ns                                                        
- Start Point:             ub_lvds_rx/reg16_syn_33.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/reg16_syn_31.b[0] (rising edge triggered by clock b_sclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.369ns  (logic 0.695ns, net 0.674ns, 50% logic)                
- Logic Levels:            1 ( LUT4=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg16_syn_33.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_33.q[0]                                clk2q                   0.146 r     2.422
- ub_lvds_rx/reg16_syn_31.b[0] (ub_lvds_rx/wcnt[0])           net  (fanout = 11)      0.674 r     3.096      encrypted_text(0)
- ub_lvds_rx/reg16_syn_31                                     path2reg0 (LUT4)        0.549       3.645
- Arrival time                                                                        3.645                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       7.997
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       7.881
- clock uncertainty                                                                  -0.000       7.881
- clock recovergence pessimism                                                        0.167       8.048
- Required time                                                                       8.048            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               4.403ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     4.442 ns                                                        
- Start Point:             ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/reg16_syn_31.c[0] (rising edge triggered by clock b_sclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.394ns  (logic 0.612ns, net 0.782ns, 43% logic)                
- Logic Levels:            1 ( LUT4=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_31.q[1]                                clk2q                   0.146 r     2.422
- ub_lvds_rx/reg16_syn_31.c[0] (ub_lvds_rx/wcnt[1])           net  (fanout = 10)      0.782 r     3.204      encrypted_text(0)
- ub_lvds_rx/reg16_syn_31                                     path2reg0 (LUT4)        0.466       3.670
- Arrival time                                                                        3.670                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       7.997
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       7.881
- clock uncertainty                                                                  -0.000       7.881
- clock recovergence pessimism                                                        0.231       8.112
- Required time                                                                       8.112            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               4.442ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point ub_lvds_rx/reg8_syn_147 (9 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     4.145 ns                                                        
- Start Point:             ub_lvds_rx/reg8_syn_147.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/reg8_syn_147.a[1] (rising edge triggered by clock b_sclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.691ns  (logic 0.878ns, net 0.813ns, 51% logic)                
- Logic Levels:            1                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_147.q[0]                                clk2q                   0.146 r     2.422
- ub_lvds_rx/reg8_syn_147.a[1] (ub_lvds_rx/para_data[11])     net  (fanout = 3)       0.813 r     3.235      encrypted_text(0)
- ub_lvds_rx/reg8_syn_147                                     path2reg0               0.732       3.967
- Arrival time                                                                        3.967                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       7.997
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       7.881
- clock uncertainty                                                                  -0.000       7.881
- clock recovergence pessimism                                                        0.231       8.112
- Required time                                                                       8.112            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               4.145ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     4.294 ns                                                        
- Start Point:             ub_lvds_rx/reg12_syn_17.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/reg8_syn_147.d[1] (rising edge triggered by clock b_sclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.478ns  (logic 0.655ns, net 0.823ns, 44% logic)                
- Logic Levels:            1                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg12_syn_17.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg12_syn_17.q[0]                                clk2q                   0.146 r     2.422
- ub_lvds_rx/reg8_syn_147.d[1] (ub_lvds_rx/sync0)             net  (fanout = 43)      0.823 r     3.245      encrypted_text(0)
- ub_lvds_rx/reg8_syn_147                                     path2reg0               0.509       3.754
- Arrival time                                                                        3.754                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       7.997
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       7.881
- clock uncertainty                                                                  -0.000       7.881
- clock recovergence pessimism                                                        0.167       8.048
- Required time                                                                       8.048            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               4.294ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     4.294 ns                                                        
- Start Point:             ub_lvds_rx/reg12_syn_17.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/reg8_syn_147.d[0] (rising edge triggered by clock b_sclk)
- Clock group:             b_lvds_clk_p                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.478ns  (logic 0.655ns, net 0.823ns, 44% logic)                
- Logic Levels:            1                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg12_syn_17.clk (ub_lvds_rx/sclk)               net                     2.276       2.276      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg12_syn_17.q[0]                                clk2q                   0.146 r     2.422
- ub_lvds_rx/reg8_syn_147.d[0] (ub_lvds_rx/sync0)             net  (fanout = 43)      0.823 r     3.245      encrypted_text(0)
- ub_lvds_rx/reg8_syn_147                                     path2reg0               0.509       3.754
- Arrival time                                                                        3.754                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg8_syn_147.clk (ub_lvds_rx/sclk)               net                     2.045       2.045      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
- capture clock edge                                                                  5.952       7.997
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       7.881
- clock uncertainty                                                                  -0.000       7.881
- clock recovergence pessimism                                                        0.167       8.048
- Required time                                                                       8.048            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               4.294ns          
+ Slack                                                                               4.382ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -2553,7 +2331,7 @@ Hold checks:
 Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.167 ns                                                        
- Start Point:             ub_lvds_rx/reg8_syn_161.clk (rising edge triggered by clock b_sclk)
+ Start Point:             ub_lvds_rx/reg3_syn_182.clk (rising edge triggered by clock b_sclk)
  End Point:               ub_lvds_rx/ramread0_syn_102.c[1] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
@@ -2564,10 +2342,10 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg8_syn_161.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/reg3_syn_182.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg8_syn_161.q[0]                                clk2q                   0.109 r     2.047
+ ub_lvds_rx/reg3_syn_182.q[1]                                clk2q                   0.109 r     2.047
  ub_lvds_rx/ramread0_syn_102.c[1] (ub_lvds_rx/para_data[26]) net  (fanout = 2)       0.216 r     2.263      encrypted_text(0)
  ub_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.263
  Arrival time                                                                        2.263                  (1 lvl)       
@@ -2586,12 +2364,12 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.345 ns                                                        
+ Slack (hold check):      0.548 ns                                                        
  Start Point:             ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
  End Point:               ub_lvds_rx/ramread0_syn_102.c[0] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.503ns  (logic 0.109ns, net 0.394ns, 21% logic)                
+ Data Path Delay:         0.690ns  (logic 0.109ns, net 0.581ns, 15% logic)                
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2602,9 +2380,9 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
  ub_lvds_rx/reg16_syn_31.q[0]                                clk2q                   0.109 r     2.047
- ub_lvds_rx/ramread0_syn_102.c[0] (ub_lvds_rx/wcnt[2])       net  (fanout = 9)       0.394 r     2.441      encrypted_text(0)
- ub_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.441
- Arrival time                                                                        2.441                  (1 lvl)       
+ ub_lvds_rx/ramread0_syn_102.c[0] (ub_lvds_rx/wcnt[2])       net  (fanout = 9)       0.581 r     2.628      encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.628
+ Arrival time                                                                        2.628                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
@@ -2613,18 +2391,18 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (2 paths)
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.113       2.243
  clock uncertainty                                                                   0.000       2.243
- clock recovergence pessimism                                                       -0.147       2.096
- Required time                                                                       2.096            
+ clock recovergence pessimism                                                       -0.163       2.080
+ Required time                                                                       2.080            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.345ns          
+ Slack                                                                               0.548ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point ub_lvds_rx/ramread0_syn_18 (2 paths)
+Paths for end point ub_lvds_rx/ramread0_syn_74 (2 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.167 ns                                                        
- Start Point:             ub_lvds_rx/reg3_syn_163.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/ramread0_syn_18.c[1] (rising edge triggered by clock b_sclk)
+ Start Point:             ub_lvds_rx/reg3_syn_174.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/ramread0_syn_74.a[1] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.325ns  (logic 0.109ns, net 0.216ns, 33% logic)                
@@ -2634,17 +2412,17 @@ Paths for end point ub_lvds_rx/ramread0_syn_18 (2 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg3_syn_163.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/reg3_syn_174.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg3_syn_163.q[1]                                clk2q                   0.109 r     2.047
- ub_lvds_rx/ramread0_syn_18.c[1] (ub_lvds_rx/para_data[2])   net  (fanout = 2)       0.216 r     2.263      encrypted_text(0)
- ub_lvds_rx/ramread0_syn_18                                  path2reg                0.000       2.263
+ ub_lvds_rx/reg3_syn_174.q[0]                                clk2q                   0.109 r     2.047
+ ub_lvds_rx/ramread0_syn_74.a[1] (ub_lvds_rx/para_data[16])  net  (fanout = 2)       0.216 r     2.263      encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_74                                  path2reg                0.000       2.263
  Arrival time                                                                        2.263                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/ramread0_syn_18.clk (ub_lvds_rx/sclk)            net                     2.130       2.130      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk)            net                     2.130       2.130      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.113       2.243
@@ -2656,12 +2434,12 @@ Paths for end point ub_lvds_rx/ramread0_syn_18 (2 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.199 ns                                                        
+ Slack (hold check):      0.207 ns                                                        
  Start Point:             ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/ramread0_syn_18.c[0] (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/ramread0_syn_74.a[0] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.357ns  (logic 0.109ns, net 0.248ns, 30% logic)                
+ Data Path Delay:         0.349ns  (logic 0.109ns, net 0.240ns, 31% logic)                
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2671,50 +2449,50 @@ Paths for end point ub_lvds_rx/ramread0_syn_18 (2 paths)
  ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg16_syn_31.q[0]                                clk2q                   0.109 r     2.047
- ub_lvds_rx/ramread0_syn_18.c[0] (ub_lvds_rx/wcnt[2])        net  (fanout = 9)       0.248 r     2.295      encrypted_text(0)
- ub_lvds_rx/ramread0_syn_18                                  path2reg                0.000       2.295
- Arrival time                                                                        2.295                  (1 lvl)       
+ ub_lvds_rx/reg16_syn_31.q[1]                                clk2q                   0.109 r     2.047
+ ub_lvds_rx/ramread0_syn_74.a[0] (ub_lvds_rx/wcnt[0])        net  (fanout = 11)      0.240 r     2.287      encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_74                                  path2reg                0.000       2.287
+ Arrival time                                                                        2.287                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/ramread0_syn_18.clk (ub_lvds_rx/sclk)            net                     2.130       2.130      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/ramread0_syn_74.clk (ub_lvds_rx/sclk)            net                     2.130       2.130      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.113       2.243
  clock uncertainty                                                                   0.000       2.243
- clock recovergence pessimism                                                       -0.147       2.096
- Required time                                                                       2.096            
+ clock recovergence pessimism                                                       -0.163       2.080
+ Required time                                                                       2.080            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.199ns          
+ Slack                                                                               0.207ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point ub_lvds_rx/ramread0_syn_102 (1 paths)
+Paths for end point ub_lvds_rx/ramread0_syn_60 (2 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.176 ns                                                        
- Start Point:             ub_lvds_rx/reg3_syn_185.clk (rising edge triggered by clock b_sclk)
- End Point:               ub_lvds_rx/ramread0_syn_102.d[1] (rising edge triggered by clock b_sclk)
+ Slack (hold check):      0.167 ns                                                        
+ Start Point:             ub_lvds_rx/reg3_syn_190.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/ramread0_syn_60.a[1] (rising edge triggered by clock b_sclk)
  Clock group:             b_lvds_clk_p                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.334ns  (logic 0.109ns, net 0.225ns, 32% logic)                
+ Data Path Delay:         0.325ns  (logic 0.109ns, net 0.216ns, 33% logic)                
  Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/reg3_syn_185.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/reg3_syn_190.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- ub_lvds_rx/reg3_syn_185.q[1]                                clk2q                   0.109 r     2.047
- ub_lvds_rx/ramread0_syn_102.d[1] (ub_lvds_rx/para_data[27]) net  (fanout = 2)       0.225 r     2.272      encrypted_text(0)
- ub_lvds_rx/ramread0_syn_102                                 path2reg                0.000       2.272
- Arrival time                                                                        2.272                  (1 lvl)       
+ ub_lvds_rx/reg3_syn_190.q[0]                                clk2q                   0.109 r     2.047
+ ub_lvds_rx/ramread0_syn_60.a[1] (ub_lvds_rx/para_data[12])  net  (fanout = 2)       0.216 r     2.263      encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_60                                  path2reg                0.000       2.263
+ Arrival time                                                                        2.263                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
- ub_lvds_rx/ramread0_syn_102.clk (ub_lvds_rx/sclk)           net                     2.130       2.130      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ ub_lvds_rx/ramread0_syn_60.clk (ub_lvds_rx/sclk)            net                     2.130       2.130      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.113       2.243
@@ -2722,7 +2500,41 @@ Paths for end point ub_lvds_rx/ramread0_syn_102 (1 paths)
  clock recovergence pessimism                                                       -0.147       2.096
  Required time                                                                       2.096            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.176ns          
+ Slack                                                                               0.167ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.324 ns                                                        
+ Start Point:             ub_lvds_rx/reg16_syn_31.clk (rising edge triggered by clock b_sclk)
+ End Point:               ub_lvds_rx/ramread0_syn_60.a[0] (rising edge triggered by clock b_sclk)
+ Clock group:             b_lvds_clk_p                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.482ns  (logic 0.109ns, net 0.373ns, 22% logic)                
+ Logic Levels:            1                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/reg16_syn_31.clk (ub_lvds_rx/sclk)               net                     1.938       1.938      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ launch clock edge                                                                   0.000       1.938
+---------------------------------------------------------------------------------------------------------
+ ub_lvds_rx/reg16_syn_31.q[1]                                clk2q                   0.109 r     2.047
+ ub_lvds_rx/ramread0_syn_60.a[0] (ub_lvds_rx/wcnt[0])        net  (fanout = 11)      0.373 r     2.420      encrypted_text(0)
+ ub_lvds_rx/ramread0_syn_60                                  path2reg                0.000       2.420
+ Arrival time                                                                        2.420                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ uu_pll_lvds/pll_inst.clkc[1]                                                        0.000       0.000                    
+ ub_lvds_rx/ramread0_syn_60.clk (ub_lvds_rx/sclk)            net                     2.130       2.130      ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(21)
+ capture clock edge                                                                  0.000       2.130
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.113       2.243
+ clock uncertainty                                                                   0.000       2.243
+ clock recovergence pessimism                                                       -0.147       2.096
+ Required time                                                                       2.096            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.324ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -2741,61 +2553,19 @@ Minimum period is 0ns
 Timing constraint:        clock: S_clk                                                    
 Clock = S_clk, period 9.258ns, rising at 0ns, falling at 4.63ns
 
-8640 endpoints analyzed totally, and 107786 paths analyzed
+8560 endpoints analyzed totally, and 109052 paths analyzed
 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 9.05ns
+Minimum period is 9.231ns
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86 (1 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     0.208 ns                                                        
- Start Point:             sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (rising edge triggered by clock b_pclk)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.mi[0] (rising edge triggered by clock S_clk)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.833ns  (logic 0.720ns, net 1.113ns, 39% logic)                
- Logic Levels:            1 ( LUT5=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- uu_pll_lvds/pll_inst.clkc[0]                                                        0.000       0.000                    
- uu_pll_lvds/bufg_feedback.clki (uu_pll_lvds/clk0_buf)       net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
- uu_pll_lvds/bufg_feedback.clko                              cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk (uu_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
- launch clock edge                                                                   0.000       2.276
----------------------------------------------------------------------------------------------------------
- sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.q[1]  clk2q                   0.146 r     2.422
- sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_49.b[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0]) net  (fanout = 14)      0.418 r     2.840      ../../../../hg_mp/fe/prebuffer_rev.v(272)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_49.f[0]  cell (LUT5)             0.431 r     3.271
- sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.mi[0] (sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13) net  (fanout = 4)       0.695 r     3.966      ../../../../hg_mp/fe/prebuffer_rev.v(301)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86 path2reg0               0.143       4.109
- Arrival time                                                                        4.109                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge                                                                  2.267       4.433
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       4.317
- clock uncertainty                                                                  -0.000       4.317
- clock recovergence pessimism                                                        0.000       4.317
- Required time                                                                       4.317            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.208ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     0.279 ns                                                        
+ Slack (setup check):     0.027 ns                                                        
  Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[0] (rising edge triggered by clock S_clk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.mi[0] (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.762ns  (logic 0.720ns, net 1.042ns, 40% logic)                
+ Data Path Delay:         2.014ns  (logic 0.720ns, net 1.294ns, 35% logic)                
  Logic Levels:            1 ( LUT5=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2808,17 +2578,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 p
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
  sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1]      clk2q                   0.146 r     2.422
- sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net  (fanout = 14)      0.528 r     2.950      ../../../../hg_mp/fe/prebuffer.v(272)
- sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.f[0] cell (LUT5)             0.431 r     3.381
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net  (fanout = 12)      0.514 r     3.895      ../../../../hg_mp/fe/prebuffer.v(301)
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2     path2reg0               0.143       4.038
- Arrival time                                                                        4.038                  (1 lvl)       
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net  (fanout = 14)      0.675 r     3.097      ../../../../hg_mp/fe/prebuffer.v(272)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.f[0]      cell (LUT5)             0.431 r     3.528
+ sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net  (fanout = 10)      0.619 r     4.147      ../../../../hg_mp/fe/prebuffer.v(301)
+ sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56 path2reg0               0.143       4.290
+ Arrival time                                                                        4.290                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  2.267       4.433
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116       4.317
@@ -2826,18 +2596,18 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 p
  clock recovergence pessimism                                                        0.000       4.317
  Required time                                                                       4.317            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.279ns          
+ Slack                                                                               0.027ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/reg14_syn_101_syn_2 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     0.279 ns                                                        
+ Slack (setup check):     0.027 ns                                                        
  Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[1] (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/reg14_syn_101_syn_2.mi[0] (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.762ns  (logic 0.720ns, net 1.042ns, 40% logic)                
+ Data Path Delay:         2.014ns  (logic 0.720ns, net 1.294ns, 35% logic)                
  Logic Levels:            1 ( LUT5=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -2850,17 +2620,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 p
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
  sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1]      clk2q                   0.146 r     2.422
- sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net  (fanout = 14)      0.528 r     2.950      ../../../../hg_mp/fe/prebuffer.v(272)
- sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.f[0] cell (LUT5)             0.431 r     3.381
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[1] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net  (fanout = 12)      0.514 r     3.895      ../../../../hg_mp/fe/prebuffer.v(301)
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2     path2reg1               0.143       4.038
- Arrival time                                                                        4.038                  (1 lvl)       
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net  (fanout = 14)      0.675 r     3.097      ../../../../hg_mp/fe/prebuffer.v(272)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.f[0]      cell (LUT5)             0.431 r     3.528
+ U_rgb_to_csi_pakage/reg14_syn_101_syn_2.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net  (fanout = 10)      0.619 r     4.147      ../../../../hg_mp/fe/prebuffer.v(301)
+ U_rgb_to_csi_pakage/reg14_syn_101_syn_2                     path2reg0               0.143       4.290
+ Arrival time                                                                        4.290                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/reg14_syn_101_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  2.267       4.433
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116       4.317
@@ -2868,17 +2638,59 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2 (1 p
  clock recovergence pessimism                                                        0.000       4.317
  Required time                                                                       4.317            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.279ns          
+ Slack                                                                               0.027ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     0.027 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (rising edge triggered by clock a_pclk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.mi[0] (rising edge triggered by clock S_clk)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         2.014ns  (logic 0.720ns, net 1.294ns, 35% logic)                
+ Logic Levels:            1 ( LUT5=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll_lvds/pll_inst.clkc[0]                                                         0.000       0.000                    
+ u_pll_lvds/bufg_feedback.clki (u_pll_lvds/clk0_buf)         net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(50)
+ u_pll_lvds/bufg_feedback.clko                               cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk (u_pll_lvds/clk0_out) net                     2.276       2.276      ../../../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(46)
+ launch clock edge                                                                   0.000       2.276
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.q[1]      clk2q                   0.146 r     2.422
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0] (sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0]) net  (fanout = 14)      0.675 r     3.097      ../../../../hg_mp/fe/prebuffer.v(272)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.f[0]      cell (LUT5)             0.431 r     3.528
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.mi[0] (sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13) net  (fanout = 10)      0.619 r     4.147      ../../../../hg_mp/fe/prebuffer.v(301)
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81           path2reg0               0.143       4.290
+ Arrival time                                                                        4.290                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge                                                                  2.267       4.433
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       4.317
+ clock uncertainty                                                                  -0.000       4.317
+ clock recovergence pessimism                                                        0.000       4.317
+ Required time                                                                       4.317            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.027ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Hold checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point u_mipi_eot_min/reg1_syn_275 (1 paths)
+Paths for end point u_pic_cnt/reg1_syn_385 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.067 ns                                                        
- Start Point:             u_bus_top/reg18_syn_74.clk (rising edge triggered by clock clk_adc)
- End Point:               u_mipi_eot_min/reg1_syn_275.mi[1] (rising edge triggered by clock S_clk)
+ Start Point:             reg36_syn_108.clk (rising edge triggered by clock clk_adc)      
+ End Point:               u_pic_cnt/reg1_syn_385.mi[0] (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
@@ -2888,19 +2700,19 @@ Paths for end point u_mipi_eot_min/reg1_syn_275 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- u_bus_top/reg18_syn_74.clk (exdev_ctl_a/clk_adc)            net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ reg36_syn_108.clk (exdev_ctl_a/clk_adc)                     net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- u_bus_top/reg18_syn_74.q[1]                                 clk2q                   0.109 r     2.047
- u_mipi_eot_min/reg1_syn_275.mi[1] (u_mipi_eot_min/signal_from[1]) net  (fanout = 1)       0.216 r     2.263      ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_mipi_eot_min/reg1_syn_275                                 path2reg1               0.095       2.358
+ reg36_syn_108.q[0]                                          clk2q                   0.109 r     2.047
+ u_pic_cnt/reg1_syn_385.mi[0] (u_pic_cnt/signal_from[5])     net  (fanout = 2)       0.216 r     2.263      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_pic_cnt/reg1_syn_385                                      path2reg0               0.095       2.358
  Arrival time                                                                        2.358                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_mipi_eot_min/reg1_syn_275.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_pic_cnt/reg1_syn_385.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.291
@@ -2912,11 +2724,11 @@ Paths for end point u_mipi_eot_min/reg1_syn_275 (1 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point add0_syn_146 (1 paths)
+Paths for end point u_mipi_eot_min/reg1_syn_289 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.067 ns                                                        
- Start Point:             reg36_syn_118.clk (rising edge triggered by clock clk_adc)      
- End Point:               add0_syn_146.mi[0] (rising edge triggered by clock S_clk)       
+ Start Point:             u_bus_top/reg18_syn_66.clk (rising edge triggered by clock clk_adc)
+ End Point:               u_mipi_eot_min/reg1_syn_289.mi[1] (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
@@ -2926,19 +2738,19 @@ Paths for end point add0_syn_146 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- reg36_syn_118.clk (exdev_ctl_a/clk_adc)                     net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg18_syn_66.clk (exdev_ctl_a/clk_adc)            net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- reg36_syn_118.q[1]                                          clk2q                   0.109 r     2.047
- add0_syn_146.mi[0] (u_pic_cnt/signal_from[9])               net  (fanout = 2)       0.216 r     2.263      ../../../../hg_mp/cdc/cdc_sync.v(9)
- add0_syn_146                                                path2reg0               0.095       2.358
+ u_bus_top/reg18_syn_66.q[1]                                 clk2q                   0.109 r     2.047
+ u_mipi_eot_min/reg1_syn_289.mi[1] (u_mipi_eot_min/signal_from[0]) net  (fanout = 1)       0.216 r     2.263      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_mipi_eot_min/reg1_syn_289                                 path2reg1               0.095       2.358
  Arrival time                                                                        2.358                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- add0_syn_146.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)        net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_eot_min/reg1_syn_289.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.291
@@ -2950,11 +2762,11 @@ Paths for end point add0_syn_146 (1 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point u_pic_cnt/reg1_syn_465 (1 paths)
+Paths for end point u_pic_cnt/reg1_syn_436 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.067 ns                                                        
- Start Point:             reg36_syn_130.clk (rising edge triggered by clock clk_adc)      
- End Point:               u_pic_cnt/reg1_syn_465.mi[0] (rising edge triggered by clock S_clk)
+ Start Point:             reg36_syn_111.clk (rising edge triggered by clock clk_adc)      
+ End Point:               u_pic_cnt/reg1_syn_436.mi[1] (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
@@ -2964,19 +2776,19 @@ Paths for end point u_pic_cnt/reg1_syn_465 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- reg36_syn_130.clk (exdev_ctl_a/clk_adc)                     net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ reg36_syn_111.clk (exdev_ctl_a/clk_adc)                     net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- reg36_syn_130.q[0]                                          clk2q                   0.109 r     2.047
- u_pic_cnt/reg1_syn_465.mi[0] (u_pic_cnt/signal_from[4])     net  (fanout = 2)       0.216 r     2.263      ../../../../hg_mp/cdc/cdc_sync.v(9)
- u_pic_cnt/reg1_syn_465                                      path2reg0               0.095       2.358
+ reg36_syn_111.q[1]                                          clk2q                   0.109 r     2.047
+ u_pic_cnt/reg1_syn_436.mi[1] (u_pic_cnt/signal_from[19])    net  (fanout = 2)       0.216 r     2.263      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ u_pic_cnt/reg1_syn_436                                      path2reg1               0.095       2.358
  Arrival time                                                                        2.358                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_pic_cnt/reg1_syn_465.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_pic_cnt/reg1_syn_436.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.291
@@ -2990,15 +2802,15 @@ Paths for end point u_pic_cnt/reg1_syn_465 (1 paths)
 
 Recovery checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/reg10_syn_53_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 (2 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (recovery check):  5.512 ns                                                        
+ Slack (recovery check):  5.372 ns                                                        
  Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point:               U_rgb_to_csi_pakage/reg10_syn_53_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         3.382ns  (logic 0.494ns, net 2.888ns, 14% logic)                
- Logic Levels:            1 ( LUT2=1 )                                                    
+ Data Path Delay:         3.522ns  (logic 0.756ns, net 2.766ns, 21% logic)                
+ Logic Levels:            2 ( LUT3=1 LUT2=1 )                                             
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -3010,17 +2822,19 @@ Paths for end point U_rgb_to_csi_pakage/reg10_syn_53_syn_2 (1 paths)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
  U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.146 r     2.556
- U_rgb_to_csi_pakage/S_frame_start_delay_n_edge_1d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net  (fanout = 7)       0.892 r     3.448      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- U_rgb_to_csi_pakage/S_frame_start_delay_n_edge_1d_reg_syn_6_syn_2.f[0] cell (LUT2)             0.205 r     3.653
- U_rgb_to_csi_pakage/reg10_syn_53_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_1) net  (fanout = 10)      1.996 r     5.649      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg10_syn_53_syn_2                      path2reg                0.143       5.792
- Arrival time                                                                        5.792                  (1 lvl)       
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net  (fanout = 6)       0.492 r     3.048      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0]     cell (LUT2)             0.262 r     3.310
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_1) net  (fanout = 28)      1.256 r     4.566      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1]  cell (LUT3)             0.262 r     4.828
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 20)      1.018 r     5.846      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 path2reg                0.086       5.932
+ Arrival time                                                                        5.932                  (2 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/reg10_syn_53_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  9.258      11.424
 ---------------------------------------------------------------------------------------------------------
  cell recovery                                                                      -0.300      11.124
@@ -3028,61 +2842,17 @@ Paths for end point U_rgb_to_csi_pakage/reg10_syn_53_syn_2 (1 paths)
  clock recovergence pessimism                                                        0.180      11.304
  Required time                                                                      11.304            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               5.512ns          
+ Slack                                                                               5.372ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (recovery check):  5.735 ns                                                        
- Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (rising edge triggered by clock S_clk)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         3.159ns  (logic 0.756ns, net 2.403ns, 23% logic)                
- Logic Levels:            2 ( LUT2=2 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.146 r     2.556
- reg20_syn_64_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en)   net  (fanout = 7)       0.530 r     3.086      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg20_syn_64_syn_2.f[0]                                     cell (LUT2)             0.262 r     3.348
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.d[0] (U_rgb_to_csi_pakage/S_rst_n_dup_5) net  (fanout = 26)      0.727 r     4.075      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.f[0] cell (LUT2)             0.262 r     4.337
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 16)      1.146 r     5.483      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2 path2reg                0.086       5.569
- Arrival time                                                                        5.569                  (2 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge                                                                  9.258      11.424
----------------------------------------------------------------------------------------------------------
- cell recovery                                                                      -0.300      11.124
- clock uncertainty                                                                  -0.000      11.124
- clock recovergence pessimism                                                        0.180      11.304
- Required time                                                                      11.304            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               5.735ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (recovery check):  6.339 ns                                                        
+ Slack (recovery check):  6.051 ns                                                        
  Start Point:             adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk) 
- End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         2.555ns  (logic 0.580ns, net 1.975ns, 22% logic)                
- Logic Levels:            1 ( LUT2=1 )                                                    
+ Data Path Delay:         2.843ns  (logic 0.580ns, net 2.263ns, 20% logic)                
+ Logic Levels:            1 ( LUT3=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -3093,18 +2863,18 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_
  adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- adj_vsynco_reg_syn_5.q[0]                                   clk2q                   0.146 r     2.556
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.c[0] (U_rgb_to_csi_pakage/I_rgb_vsync) net  (fanout = 7)       0.829 r     3.385      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.f[0] cell (LUT2)             0.348 r     3.733
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 16)      1.146 r     4.879      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2 path2reg                0.086       4.965
- Arrival time                                                                        4.965                  (1 lvl)       
+ adj_vsynco_reg_syn_5.q[1]                                   clk2q                   0.146 r     2.556
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net  (fanout = 8)       1.245 r     3.801      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1]  cell (LUT3)             0.348 r     4.149
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 20)      1.018 r     5.167      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275 path2reg                0.086       5.253
+ Arrival time                                                                        5.253                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  9.258      11.424
 ---------------------------------------------------------------------------------------------------------
  cell recovery                                                                      -0.300      11.124
@@ -3112,19 +2882,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_
  clock recovergence pessimism                                                        0.180      11.304
  Required time                                                                      11.304            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               6.339ns          
+ Slack                                                                               6.051ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 (2 paths)
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 (2 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (recovery check):  5.754 ns                                                        
+ Slack (recovery check):  5.379 ns                                                        
  Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         3.140ns  (logic 0.699ns, net 2.441ns, 22% logic)                
- Logic Levels:            2 ( LUT4=1 LUT2=1 )                                             
+ Data Path Delay:         3.515ns  (logic 0.756ns, net 2.759ns, 21% logic)                
+ Logic Levels:            2 ( LUT3=1 LUT2=1 )                                             
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -3136,19 +2906,19 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
  U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.146 r     2.556
- reg20_syn_64_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en)   net  (fanout = 7)       0.530 r     3.086      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg20_syn_64_syn_2.f[0]                                     cell (LUT2)             0.262 r     3.348
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_5) net  (fanout = 26)      0.874 r     4.222      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.f[1]  cell (LUT4)             0.205 r     4.427
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net  (fanout = 17)      1.037 r     5.464      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 path2reg                0.086       5.550
- Arrival time                                                                        5.550                  (2 lvl)       
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net  (fanout = 6)       0.492 r     3.048      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0]     cell (LUT2)             0.262 r     3.310
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_1) net  (fanout = 28)      1.256 r     4.566      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1]  cell (LUT3)             0.262 r     4.828
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 20)      1.011 r     5.839      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 path2reg                0.086       5.925
+ Arrival time                                                                        5.925                  (2 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  9.258      11.424
 ---------------------------------------------------------------------------------------------------------
  cell recovery                                                                      -0.300      11.124
@@ -3156,17 +2926,17 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
  clock recovergence pessimism                                                        0.180      11.304
  Required time                                                                      11.304            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               5.754ns          
+ Slack                                                                               5.379ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (recovery check):  6.319 ns                                                        
+ Slack (recovery check):  6.058 ns                                                        
  Start Point:             adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk) 
- End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         2.575ns  (logic 0.483ns, net 2.092ns, 18% logic)                
- Logic Levels:            1 ( LUT4=1 )                                                    
+ Data Path Delay:         2.836ns  (logic 0.580ns, net 2.256ns, 20% logic)                
+ Logic Levels:            1 ( LUT3=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -3177,18 +2947,18 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
  adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- adj_vsynco_reg_syn_5.q[0]                                   clk2q                   0.146 r     2.556
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net  (fanout = 7)       1.055 r     3.611      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.f[1]  cell (LUT4)             0.251 r     3.862
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19) net  (fanout = 17)      1.037 r     4.899      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284 path2reg                0.086       4.985
- Arrival time                                                                        4.985                  (1 lvl)       
+ adj_vsynco_reg_syn_5.q[1]                                   clk2q                   0.146 r     2.556
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net  (fanout = 8)       1.245 r     3.801      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1]  cell (LUT3)             0.348 r     4.149
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 20)      1.011 r     5.160      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2 path2reg                0.086       5.246
+ Arrival time                                                                        5.246                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  9.258      11.424
 ---------------------------------------------------------------------------------------------------------
  cell recovery                                                                      -0.300      11.124
@@ -3196,20 +2966,104 @@ Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
  clock recovergence pessimism                                                        0.180      11.304
  Required time                                                                      11.304            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               6.319ns          
+ Slack                                                                               6.058ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (recovery check):  5.379 ns                                                        
+ Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (rising edge triggered by clock S_clk)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         3.515ns  (logic 0.756ns, net 2.759ns, 21% logic)                
+ Logic Levels:            2 ( LUT3=1 LUT2=1 )                                             
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.146 r     2.556
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net  (fanout = 6)       0.492 r     3.048      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0]     cell (LUT2)             0.262 r     3.310
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1] (U_rgb_to_csi_pakage/S_rst_n_dup_1) net  (fanout = 28)      1.256 r     4.566      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1]  cell (LUT3)             0.262 r     4.828
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 20)      1.011 r     5.839      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 path2reg                0.086       5.925
+ Arrival time                                                                        5.925                  (2 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge                                                                  9.258      11.424
+---------------------------------------------------------------------------------------------------------
+ cell recovery                                                                      -0.300      11.124
+ clock uncertainty                                                                  -0.000      11.124
+ clock recovergence pessimism                                                        0.180      11.304
+ Required time                                                                      11.304            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               5.379ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (recovery check):  6.058 ns                                                        
+ Start Point:             adj_vsynco_reg_syn_5.clk (rising edge triggered by clock S_clk) 
+ End Point:               U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (rising edge triggered by clock S_clk)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         2.836ns  (logic 0.580ns, net 2.256ns, 20% logic)                
+ Logic Levels:            1 ( LUT3=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ adj_vsynco_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ adj_vsynco_reg_syn_5.q[1]                                   clk2q                   0.146 r     2.556
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1] (U_rgb_to_csi_pakage/I_rgb_vsync) net  (fanout = 8)       1.245 r     3.801      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.f[1]  cell (LUT3)             0.348 r     4.149
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr (U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst) net  (fanout = 20)      1.011 r     5.160      ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(22)
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2 path2reg                0.086       5.246
+ Arrival time                                                                        5.246                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge                                                                  9.258      11.424
+---------------------------------------------------------------------------------------------------------
+ cell recovery                                                                      -0.300      11.124
+ clock uncertainty                                                                  -0.000      11.124
+ clock recovergence pessimism                                                        0.180      11.304
+ Required time                                                                      11.304            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               6.058ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Removal checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths)
+Paths for end point U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (removal check):   0.685 ns                                                        
+ Slack (removal check):   0.697 ns                                                        
  Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point:               U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.sr (rising edge triggered by clock S_clk)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.967ns  (logic 0.375ns, net 0.592ns, 38% logic)                
+ Data Path Delay:         0.995ns  (logic 0.375ns, net 0.620ns, 37% logic)                
  Logic Levels:            1 ( LUT2=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3222,11 +3076,95 @@ Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
  U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.109 r     2.138
- reg20_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en)   net  (fanout = 7)       0.240 r     2.378      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg20_syn_54_syn_2.f[0]                                     cell (LUT2)             0.179 r     2.557
- U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net  (fanout = 20)      0.352 r     2.909      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg12_syn_73_syn_2                      path2reg                0.087       2.996
- Arrival time                                                                        2.996                  (1 lvl)       
+ U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net  (fanout = 6)       0.232 r     2.370      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ U_rgb_to_csi_pakage/reg16_syn_103_syn_2.f[0]                cell (LUT2)             0.179 r     2.549
+ U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n) net  (fanout = 27)      0.388 r     2.937      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2           path2reg                0.087       3.024
+ Arrival time                                                                        3.024                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge                                                                  0.000       2.230
+---------------------------------------------------------------------------------------------------------
+ cell removal                                                                        0.253       2.483
+ clock uncertainty                                                                   0.000       2.483
+ clock recovergence pessimism                                                       -0.156       2.327
+ Required time                                                                       2.327            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.697ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point U_rgb_to_csi_pakage/reg2_syn_151_syn_2 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (removal check):   0.727 ns                                                        
+ Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/reg2_syn_151_syn_2.sr (rising edge triggered by clock S_clk)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         1.025ns  (logic 0.375ns, net 0.650ns, 36% logic)                
+ Logic Levels:            1 ( LUT2=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.109 r     2.138
+ U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[1] (U_rgb_to_csi_pakage/S_global_en) net  (fanout = 6)       0.232 r     2.370      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ U_rgb_to_csi_pakage/reg16_syn_103_syn_2.f[1]                cell (LUT2)             0.179 r     2.549
+ U_rgb_to_csi_pakage/reg2_syn_151_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_3) net  (fanout = 14)      0.418 r     2.967      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg2_syn_151_syn_2                      path2reg                0.087       3.054
+ Arrival time                                                                        3.054                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ U_rgb_to_csi_pakage/reg2_syn_151_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ capture clock edge                                                                  0.000       2.230
+---------------------------------------------------------------------------------------------------------
+ cell removal                                                                        0.253       2.483
+ clock uncertainty                                                                   0.000       2.483
+ clock recovergence pessimism                                                       -0.156       2.327
+ Required time                                                                       2.327            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.727ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (removal check):   0.767 ns                                                        
+ Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
+ End Point:               U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (rising edge triggered by clock S_clk)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         1.065ns  (logic 0.375ns, net 0.690ns, 35% logic)                
+ Logic Levels:            1 ( LUT2=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.109 r     2.138
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en) net  (fanout = 6)       0.339 r     2.477      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
+ U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.f[0]     cell (LUT2)             0.179 r     2.656
+ U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_1) net  (fanout = 28)      0.351 r     3.007      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
+ U_rgb_to_csi_pakage/reg12_syn_73_syn_2                      path2reg                0.087       3.094
+ Arrival time                                                                        3.094                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
@@ -3234,97 +3172,13 @@ Paths for end point U_rgb_to_csi_pakage/reg12_syn_73_syn_2 (1 paths)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
  U_rgb_to_csi_pakage/reg12_syn_73_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  capture clock edge                                                                  0.000       2.230
----------------------------------------------------------------------------------------------------------
- cell removal                                                                        0.253       2.483
- clock uncertainty                                                                   0.000       2.483
- clock recovergence pessimism                                                       -0.172       2.311
- Required time                                                                       2.311            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.685ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point U_rgb_to_csi_pakage/reg12_syn_69_syn_2 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (removal check):   0.685 ns                                                        
- Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point:               U_rgb_to_csi_pakage/reg12_syn_69_syn_2.sr (rising edge triggered by clock S_clk)
- Clock group:             clock_source                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.967ns  (logic 0.375ns, net 0.592ns, 38% logic)                
- Logic Levels:            1 ( LUT2=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.109 r     2.138
- reg20_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en)   net  (fanout = 7)       0.240 r     2.378      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg20_syn_54_syn_2.f[0]                                     cell (LUT2)             0.179 r     2.557
- U_rgb_to_csi_pakage/reg12_syn_69_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net  (fanout = 20)      0.352 r     2.909      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg12_syn_69_syn_2                      path2reg                0.087       2.996
- Arrival time                                                                        2.996                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/reg12_syn_69_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge                                                                  0.000       2.230
----------------------------------------------------------------------------------------------------------
- cell removal                                                                        0.253       2.483
- clock uncertainty                                                                   0.000       2.483
- clock recovergence pessimism                                                       -0.172       2.311
- Required time                                                                       2.311            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.685ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point U_rgb_to_csi_pakage/reg7_syn_151_syn_2 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (removal check):   0.781 ns                                                        
- Start Point:             U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (rising edge triggered by clock S_clk)
- End Point:               U_rgb_to_csi_pakage/reg7_syn_151_syn_2.sr (rising edge triggered by clock S_clk)
- Clock group:             clock_source                                                    
- Process:                 Fast                                                            
- Data Path Delay:         1.079ns  (logic 0.375ns, net 0.704ns, 34% logic)                
- Logic Levels:            1 ( LUT2=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- U_rgb_to_csi_pakage/S_global_en_reg_syn_9.q[0]              clk2q                   0.109 r     2.138
- reg20_syn_54_syn_2.d[0] (U_rgb_to_csi_pakage/S_global_en)   net  (fanout = 7)       0.240 r     2.378      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(101)
- reg20_syn_54_syn_2.f[0]                                     cell (LUT2)             0.179 r     2.557
- U_rgb_to_csi_pakage/reg7_syn_151_syn_2.sr (U_rgb_to_csi_pakage/S_rst_n_dup_2) net  (fanout = 20)      0.464 r     3.021      ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(102)
- U_rgb_to_csi_pakage/reg7_syn_151_syn_2                      path2reg                0.087       3.108
- Arrival time                                                                        3.108                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- U_rgb_to_csi_pakage/reg7_syn_151_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell removal                                                                        0.253       2.483
  clock uncertainty                                                                   0.000       2.483
  clock recovergence pessimism                                                       -0.156       2.327
  Required time                                                                       2.327            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.781ns          
+ Slack                                                                               0.767ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -3332,182 +3186,72 @@ Period checks:
 ---------------------------------------------------------------------------------------------------------
  Point                                             Type          Setting(ns)    Requied(ns)     Slack(ns)  
 ---------------------------------------------------------------------------------------------------------
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb min period       9.258          3.400          5.858    
+ sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb min period       9.258          3.400          5.858    
- sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clkb min period       9.258          3.400          5.858    
  sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clkb min period       9.258          3.400          5.858    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period       9.258          3.300          5.958    
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period       9.258          3.300          5.958    
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period       9.258          3.300          5.958    
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period       9.258          3.300          5.958    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw min period       9.258          3.300          5.958    
 
 =========================================================================================================
 Timing constraint:        clock: clk_adc                                                  
 Clock = clk_adc, period 166.664ns, rising at 0ns, falling at 83.332ns
 
-4240 endpoints analyzed totally, and 43224 paths analyzed
-3 errors detected : 3 setup errors (TNS = -3.279), 0 hold errors (TNS = 0.000)
-Minimum period is 168.609ns
+5330 endpoints analyzed totally, and 46330 paths analyzed
+0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
+Minimum period is 159.25ns
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point reg40_syn_12 (2 paths)
+Paths for end point u_bus_top/reg12_syn_135 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):    -1.945 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk (rising edge triggered by clock S_clk_x2)
- End Point:               reg40_syn_12.mi[1] (rising edge triggered by clock clk_adc)     
+ Slack (setup check):     7.414 ns                                                        
+ Start Point:             reg26_syn_196.clk (rising edge triggered by clock S_clk)        
+ End Point:               u_bus_top/reg12_syn_135.mi[1] (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.484ns  (logic 0.494ns, net 0.990ns, 33% logic)                
- Logic Levels:            1 ( LUT2=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.q[0] clk2q                   0.146 r     2.556
- reg29_syn_13.d[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d) net  (fanout = 1)       0.683 r     3.239      encrypted_text(0)
- reg29_syn_13.f[0]                                           cell (LUT2)             0.205 r     3.444
- reg40_syn_12.mi[1] (O_clk_lp_n_dup_1)                       net  (fanout = 2)       0.307 r     3.751      ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
- reg40_syn_12                                                path2reg1               0.143       3.894
- Arrival time                                                                        3.894                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- reg40_syn_12.clk (exdev_ctl_a/clk_adc)                      net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
- capture clock edge                                                                  0.020       2.065
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       1.949
- clock uncertainty                                                                  -0.000       1.949
- clock recovergence pessimism                                                        0.000       1.949
- Required time                                                                       1.949            
----------------------------------------------------------------------------------------------------------
- Slack                                                                              -1.945ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):    -1.844 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (rising edge triggered by clock S_clk_x2)
- End Point:               reg40_syn_12.mi[1] (rising edge triggered by clock clk_adc)     
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.383ns  (logic 0.540ns, net 0.843ns, 39% logic)                
- Logic Levels:            1 ( LUT2=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.q[0] clk2q                   0.146 r     2.556
- reg29_syn_13.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net  (fanout = 3)       0.536 r     3.092      encrypted_text(0)
- reg29_syn_13.f[0]                                           cell (LUT2)             0.251 r     3.343
- reg40_syn_12.mi[1] (O_clk_lp_n_dup_1)                       net  (fanout = 2)       0.307 r     3.650      ../../../../hg_mp/drx_top/huagao_mipi_top.v(42)
- reg40_syn_12                                                path2reg1               0.143       3.793
- Arrival time                                                                        3.793                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- reg40_syn_12.clk (exdev_ctl_a/clk_adc)                      net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
- capture clock edge                                                                  0.020       2.065
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       1.949
- clock uncertainty                                                                  -0.000       1.949
- clock recovergence pessimism                                                        0.000       1.949
- Required time                                                                       1.949            
----------------------------------------------------------------------------------------------------------
- Slack                                                                              -1.844ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point reg40_syn_12 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):    -1.334 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (rising edge triggered by clock S_clk_x2)
- End Point:               reg40_syn_12.mi[0] (rising edge triggered by clock clk_adc)     
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         0.873ns  (logic 0.289ns, net 0.584ns, 33% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.q[0] clk2q                   0.146 r     2.556
- reg40_syn_12.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d) net  (fanout = 3)       0.584 r     3.140      encrypted_text(0)
- reg40_syn_12                                                path2reg0               0.143       3.283
- Arrival time                                                                        3.283                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- reg40_syn_12.clk (exdev_ctl_a/clk_adc)                      net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
- capture clock edge                                                                  0.020       2.065
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       1.949
- clock uncertainty                                                                  -0.000       1.949
- clock recovergence pessimism                                                        0.000       1.949
- Required time                                                                       1.949            
----------------------------------------------------------------------------------------------------------
- Slack                                                                              -1.334ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point u_bus_top/reg15_syn_166 (1 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     7.526 ns                                                        
- Start Point:             reg27_syn_214.clk (rising edge triggered by clock S_clk)        
- End Point:               u_bus_top/reg15_syn_166.mi[1] (rising edge triggered by clock clk_adc)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.251ns  (logic 0.289ns, net 0.962ns, 23% logic)                
+ Data Path Delay:         1.363ns  (logic 0.289ns, net 1.074ns, 21% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3516,17 +3260,17 @@ Paths for end point u_bus_top/reg15_syn_166 (1 paths)
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- reg27_syn_214.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)       net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg26_syn_196.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)       net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- reg27_syn_214.q[1]                                          clk2q                   0.146 r     2.556
- u_bus_top/reg15_syn_166.mi[1] (lv_cnt_b[12])                net  (fanout = 4)       0.962 r     3.518      ../../../../hg_mp/drx_top/huagao_mipi_top.v(1072)
- u_bus_top/reg15_syn_166                                     path2reg1               0.143       3.661
- Arrival time                                                                        3.661                  (0 lvl)       
+ reg26_syn_196.q[0]                                          clk2q                   0.146 r     2.556
+ u_bus_top/reg12_syn_135.mi[1] (lv_cnt_a[0])                 net  (fanout = 4)       1.074 r     3.630      ../../../../hg_mp/drx_top/huagao_mipi_top.v(1093)
+ u_bus_top/reg12_syn_135                                     path2reg1               0.143       3.773
+ Arrival time                                                                        3.773                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- u_bus_top/reg15_syn_166.clk (exdev_ctl_a/clk_adc)           net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg12_syn_135.clk (exdev_ctl_a/clk_adc)           net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                  9.258      11.303
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116      11.187
@@ -3534,17 +3278,93 @@ Paths for end point u_bus_top/reg15_syn_166 (1 paths)
  clock recovergence pessimism                                                        0.000      11.187
  Required time                                                                      11.187            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               7.526ns          
+ Slack                                                                               7.414ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_bus_top/reg6_syn_118 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     7.493 ns                                                        
+ Start Point:             reg24_syn_80.clk (rising edge triggered by clock S_clk)         
+ End Point:               u_bus_top/reg6_syn_118.mi[0] (rising edge triggered by clock clk_adc)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.284ns  (logic 0.289ns, net 0.995ns, 22% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ reg24_syn_80.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)        net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ reg24_syn_80.q[0]                                           clk2q                   0.146 r     2.556
+ u_bus_top/reg6_syn_118.mi[0] (frame_cnt[10])                net  (fanout = 3)       0.995 r     3.551      ../../../../hg_mp/drx_top/huagao_mipi_top.v(249)
+ u_bus_top/reg6_syn_118                                      path2reg0               0.143       3.694
+ Arrival time                                                                        3.694                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ u_bus_top/reg6_syn_118.clk (exdev_ctl_a/clk_adc)            net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ capture clock edge                                                                  9.258      11.303
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116      11.187
+ clock uncertainty                                                                  -0.000      11.187
+ clock recovergence pessimism                                                        0.000      11.187
+ Required time                                                                      11.187            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               7.493ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_bus_top/reg0_syn_143_syn_2 (1 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     7.607 ns                                                        
+ Start Point:             reg1_syn_154.clk (rising edge triggered by clock S_clk)         
+ End Point:               u_bus_top/reg0_syn_143_syn_2.mi[1] (rising edge triggered by clock clk_adc)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.170ns  (logic 0.289ns, net 0.881ns, 24% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ reg1_syn_154.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)        net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ reg1_syn_154.q[0]                                           clk2q                   0.146 r     2.556
+ u_bus_top/reg0_syn_143_syn_2.mi[1] (S_hs_data_reg[11])      net  (fanout = 1)       0.881 r     3.437      ../../../../hg_mp/drx_top/huagao_mipi_top.v(1296)
+ u_bus_top/reg0_syn_143_syn_2                                path2reg1               0.143       3.580
+ Arrival time                                                                        3.580                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ u_bus_top/reg0_syn_143_syn_2.clk (exdev_ctl_a/clk_adc)      net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ capture clock edge                                                                  9.258      11.303
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116      11.187
+ clock uncertainty                                                                  -0.000      11.187
+ clock recovergence pessimism                                                        0.000      11.187
+ Required time                                                                      11.187            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               7.607ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Hold checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point u_bus_top/reg9_syn_165 (1 paths)
+Paths for end point add9_syn_98 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.258 ns                                                        
- Start Point:             reg25_syn_115.clk (rising edge triggered by clock S_clk)        
- End Point:               u_bus_top/reg9_syn_165.mi[1] (rising edge triggered by clock clk_adc)
+ Start Point:             reg24_syn_89.clk (rising edge triggered by clock S_clk)         
+ End Point:               add9_syn_98.mi[0] (rising edge triggered by clock clk_adc)      
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
@@ -3556,17 +3376,17 @@ Paths for end point u_bus_top/reg9_syn_165 (1 paths)
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- reg25_syn_115.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)       net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg24_syn_89.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)        net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
- reg25_syn_115.q[1]                                          clk2q                   0.109 r     2.138
- u_bus_top/reg9_syn_165.mi[1] (lv_cnt2bus[6])                net  (fanout = 1)       0.216 r     2.354      ../../../../hg_mp/drx_top/huagao_mipi_top.v(1273)
- u_bus_top/reg9_syn_165                                      path2reg1               0.095       2.449
+ reg24_syn_89.q[0]                                           clk2q                   0.109 r     2.138
+ add9_syn_98.mi[0] (frame_cnt[2])                            net  (fanout = 3)       0.216 r     2.354      ../../../../hg_mp/drx_top/huagao_mipi_top.v(249)
+ add9_syn_98                                                 path2reg0               0.095       2.449
  Arrival time                                                                        2.449                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- u_bus_top/reg9_syn_165.clk (exdev_ctl_a/clk_adc)            net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ add9_syn_98.clk (exdev_ctl_a/clk_adc)                       net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.191
@@ -3578,11 +3398,11 @@ Paths for end point u_bus_top/reg9_syn_165 (1 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point u_bus_top/reg9_syn_165 (1 paths)
+Paths for end point u_bus_top/reg0_syn_151_syn_2 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.258 ns                                                        
- Start Point:             reg25_syn_127.clk (rising edge triggered by clock S_clk)        
- End Point:               u_bus_top/reg9_syn_165.mi[0] (rising edge triggered by clock clk_adc)
+ Start Point:             reg1_syn_142.clk (rising edge triggered by clock S_clk)         
+ End Point:               u_bus_top/reg0_syn_151_syn_2.mi[0] (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
@@ -3594,17 +3414,17 @@ Paths for end point u_bus_top/reg9_syn_165 (1 paths)
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- reg25_syn_127.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)       net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ reg1_syn_142.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)        net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
- reg25_syn_127.q[1]                                          clk2q                   0.109 r     2.138
- u_bus_top/reg9_syn_165.mi[0] (lv_cnt2bus[8])                net  (fanout = 1)       0.216 r     2.354      ../../../../hg_mp/drx_top/huagao_mipi_top.v(1273)
- u_bus_top/reg9_syn_165                                      path2reg0               0.095       2.449
+ reg1_syn_142.q[0]                                           clk2q                   0.109 r     2.138
+ u_bus_top/reg0_syn_151_syn_2.mi[0] (S_hs_data_reg[14])      net  (fanout = 1)       0.216 r     2.354      ../../../../hg_mp/drx_top/huagao_mipi_top.v(1296)
+ u_bus_top/reg0_syn_151_syn_2                                path2reg0               0.095       2.449
  Arrival time                                                                        2.449                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- u_bus_top/reg9_syn_165.clk (exdev_ctl_a/clk_adc)            net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ u_bus_top/reg0_syn_151_syn_2.clk (exdev_ctl_a/clk_adc)      net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.191
@@ -3616,54 +3436,52 @@ Paths for end point u_bus_top/reg9_syn_165 (1 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point u_bus_top/reg9_syn_152 (1 paths)
+Paths for end point exdev_ctl_b/reg2_syn_213 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.258 ns                                                        
- Start Point:             reg25_syn_133.clk (rising edge triggered by clock S_clk)        
- End Point:               u_bus_top/reg9_syn_152.mi[1] (rising edge triggered by clock clk_adc)
+ Slack (hold check):      0.260 ns                                                        
+ Start Point:             exdev_ctl_b/reg1_syn_176.clk (rising edge triggered by clock clk_adc)
+ End Point:               exdev_ctl_b/reg2_syn_213.mi[0] (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.420ns  (logic 0.204ns, net 0.216ns, 48% logic)                
+ Data Path Delay:         0.429ns  (logic 0.204ns, net 0.225ns, 47% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- reg25_syn_133.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk)       net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.029
+ u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
+ exdev_ctl_b/reg1_syn_176.clk (exdev_ctl_a/clk_adc)          net                     1.938       1.938      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
- reg25_syn_133.q[0]                                          clk2q                   0.109 r     2.138
- u_bus_top/reg9_syn_152.mi[1] (lv_cnt2bus[3])                net  (fanout = 1)       0.216 r     2.354      ../../../../hg_mp/drx_top/huagao_mipi_top.v(1273)
- u_bus_top/reg9_syn_152                                      path2reg1               0.095       2.449
- Arrival time                                                                        2.449                  (0 lvl)       
+ exdev_ctl_b/reg1_syn_176.q[1]                               clk2q                   0.109 r     2.047
+ exdev_ctl_b/reg2_syn_213.mi[0] (exdev_ctl_b/adc_cfg_dat_d1[27]) net  (fanout = 2)       0.225 r     2.272      ../../../../hg_mp/fe/exdev_ctl.v(72)
+ exdev_ctl_b/reg2_syn_213                                    path2reg0               0.095       2.367
+ Arrival time                                                                        2.367                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- u_bus_top/reg9_syn_152.clk (exdev_ctl_a/clk_adc)            net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ exdev_ctl_b/reg2_syn_213.clk (exdev_ctl_a/clk_adc)          net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.191
  clock uncertainty                                                                   0.000       2.191
- clock recovergence pessimism                                                        0.000       2.191
- Required time                                                                       2.191            
+ clock recovergence pessimism                                                       -0.084       2.107
+ Required time                                                                       2.107            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.258ns          
+ Slack                                                                               0.260ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Recovery checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/reg2_syn_21 (1 paths)
+Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (recovery check):  161.807 ns                                                      
+ Slack (recovery check):  163.478 ns                                                      
  Start Point:             clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point:               scan_start_diff/reg2_syn_21.sr (rising edge triggered by clock clk_adc)
+ End Point:               scan_start_diff/a_ex_frame_en_reg_syn_5.sr (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         4.421ns  (logic 0.551ns, net 3.870ns, 12% logic)                
+ Data Path Delay:         2.822ns  (logic 0.494ns, net 2.328ns, 17% logic)                
  Logic Levels:            1 ( LUT2=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3674,34 +3492,34 @@ Paths for end point scan_start_diff/reg2_syn_21 (1 paths)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
  clkubus_rstn_reg_syn_8.q[0]                                 clk2q                   0.146 r     2.422
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 14)      3.051 r     5.473      ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.262 r     5.735
- scan_start_diff/reg2_syn_21.sr (BUSY_MIPI_sync_d0_i_syn_9)  net  (fanout = 16)      0.819 r     6.554      ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg2_syn_21                                 path2reg                0.143       6.697
- Arrival time                                                                        6.697                  (1 lvl)       
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 16)      1.416 r     3.838      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.205 r     4.043
+ scan_start_diff/a_ex_frame_en_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net  (fanout = 11)      0.912 r     4.955      ../../../../hg_mp/drx_top/huagao_mipi_top.v(570)
+ scan_start_diff/a_ex_frame_en_reg_syn_5                     path2reg                0.143       5.098
+ Arrival time                                                                        5.098                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- scan_start_diff/reg2_syn_21.clk (exdev_ctl_a/clk_adc)       net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/a_ex_frame_en_reg_syn_5.clk (exdev_ctl_a/clk_adc) net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                166.664     168.709
 ---------------------------------------------------------------------------------------------------------
  cell recovery                                                                      -0.300     168.409
  clock uncertainty                                                                  -0.000     168.409
- clock recovergence pessimism                                                        0.095     168.504
- Required time                                                                     168.504            
+ clock recovergence pessimism                                                        0.167     168.576
+ Required time                                                                     168.576            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                             161.807ns          
+ Slack                                                                             163.478ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20 (1 paths)
+Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (recovery check):  161.807 ns                                                      
+ Slack (recovery check):  163.665 ns                                                      
  Start Point:             clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point:               sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.sr (rising edge triggered by clock clk_adc)
+ End Point:               scan_start_diff/a_ex_frame_reg_syn_5.sr (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         4.421ns  (logic 0.551ns, net 3.870ns, 12% logic)                
+ Data Path Delay:         2.635ns  (logic 0.494ns, net 2.141ns, 18% logic)                
  Logic Levels:            1 ( LUT2=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3712,34 +3530,34 @@ Paths for end point sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_swi
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
  clkubus_rstn_reg_syn_8.q[0]                                 clk2q                   0.146 r     2.422
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 14)      3.051 r     5.473      ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.262 r     5.735
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.sr (BUSY_MIPI_sync_d0_i_syn_9) net  (fanout = 16)      0.819 r     6.554      ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20 path2reg                0.143       6.697
- Arrival time                                                                        6.697                  (1 lvl)       
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 16)      1.416 r     3.838      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.205 r     4.043
+ scan_start_diff/a_ex_frame_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net  (fanout = 11)      0.725 r     4.768      ../../../../hg_mp/drx_top/huagao_mipi_top.v(570)
+ scan_start_diff/a_ex_frame_reg_syn_5                        path2reg                0.143       4.911
+ Arrival time                                                                        4.911                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.clk (exdev_ctl_a/clk_adc) net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/a_ex_frame_reg_syn_5.clk (exdev_ctl_a/clk_adc) net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                166.664     168.709
 ---------------------------------------------------------------------------------------------------------
  cell recovery                                                                      -0.300     168.409
  clock uncertainty                                                                  -0.000     168.409
- clock recovergence pessimism                                                        0.095     168.504
- Required time                                                                     168.504            
+ clock recovergence pessimism                                                        0.167     168.576
+ Required time                                                                     168.576            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                             161.807ns          
+ Slack                                                                             163.665ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
+Paths for end point scan_start_diff/enable_from_arm_rog_reg_syn_5 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (recovery check):  161.970 ns                                                      
+ Slack (recovery check):  163.676 ns                                                      
  Start Point:             clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point:               scan_start_diff/reg2_syn_19.sr (rising edge triggered by clock clk_adc)
+ End Point:               scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         4.258ns  (logic 0.551ns, net 3.707ns, 12% logic)                
+ Data Path Delay:         2.624ns  (logic 0.494ns, net 2.130ns, 18% logic)                
  Logic Levels:            1 ( LUT2=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3750,36 +3568,36 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
  launch clock edge                                                                   0.000       2.276
 ---------------------------------------------------------------------------------------------------------
  clkubus_rstn_reg_syn_8.q[0]                                 clk2q                   0.146 r     2.422
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 14)      3.051 r     5.473      ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.262 r     5.735
- scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_9)  net  (fanout = 16)      0.656 r     6.391      ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg2_syn_19                                 path2reg                0.143       6.534
- Arrival time                                                                        6.534                  (1 lvl)       
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 16)      1.416 r     3.838      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.205 r     4.043
+ scan_start_diff/enable_from_arm_rog_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net  (fanout = 11)      0.714 r     4.757      ../../../../hg_mp/drx_top/huagao_mipi_top.v(570)
+ scan_start_diff/enable_from_arm_rog_reg_syn_5               path2reg                0.143       4.900
+ Arrival time                                                                        4.900                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- scan_start_diff/reg2_syn_19.clk (exdev_ctl_a/clk_adc)       net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/enable_from_arm_rog_reg_syn_5.clk (exdev_ctl_a/clk_adc) net                     2.045       2.045      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                166.664     168.709
 ---------------------------------------------------------------------------------------------------------
  cell recovery                                                                      -0.300     168.409
  clock uncertainty                                                                  -0.000     168.409
- clock recovergence pessimism                                                        0.095     168.504
- Required time                                                                     168.504            
+ clock recovergence pessimism                                                        0.167     168.576
+ Required time                                                                     168.576            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                             161.970ns          
+ Slack                                                                             163.676ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Removal checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths)
+Paths for end point scan_start_diff/reg2_syn_20 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (removal check):   2.526 ns                                                        
+ Slack (removal check):   1.366 ns                                                        
  Start Point:             clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point:               scan_start_diff/a_ex_frame_reg_syn_5.sr (rising edge triggered by clock clk_adc)
+ End Point:               scan_start_diff/reg2_syn_20.sr (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         2.887ns  (logic 0.375ns, net 2.512ns, 12% logic)                
+ Data Path Delay:         1.664ns  (logic 0.322ns, net 1.342ns, 19% logic)                
  Logic Levels:            1 ( LUT2=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3790,34 +3608,34 @@ Paths for end point scan_start_diff/a_ex_frame_reg_syn_5 (1 paths)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
  clkubus_rstn_reg_syn_8.q[0]                                 clk2q                   0.109 r     2.047
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 14)      2.171 r     4.218      ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.179 r     4.397
- scan_start_diff/a_ex_frame_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net  (fanout = 16)      0.341 r     4.738      ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/a_ex_frame_reg_syn_5                        path2reg                0.087       4.825
- Arrival time                                                                        4.825                  (1 lvl)       
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 16)      0.991 r     3.038      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.126 r     3.164
+ scan_start_diff/reg2_syn_20.sr (BUSY_MIPI_sync_d0_i_syn_9)  net  (fanout = 11)      0.351 r     3.515      ../../../../hg_mp/drx_top/huagao_mipi_top.v(570)
+ scan_start_diff/reg2_syn_20                                 path2reg                0.087       3.602
+ Arrival time                                                                        3.602                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- scan_start_diff/a_ex_frame_reg_syn_5.clk (exdev_ctl_a/clk_adc) net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/reg2_syn_20.clk (exdev_ctl_a/clk_adc)       net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell removal                                                                        0.253       2.383
  clock uncertainty                                                                   0.000       2.383
- clock recovergence pessimism                                                       -0.084       2.299
- Required time                                                                       2.299            
+ clock recovergence pessimism                                                       -0.147       2.236
+ Required time                                                                       2.236            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               2.526ns          
+ Slack                                                                               1.366ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths)
+Paths for end point scan_start_diff/a_frame_pad_rog_reg_syn_5 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (removal check):   2.537 ns                                                        
+ Slack (removal check):   1.410 ns                                                        
  Start Point:             clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point:               scan_start_diff/a_ex_frame_en_reg_syn_5.sr (rising edge triggered by clock clk_adc)
+ End Point:               scan_start_diff/a_frame_pad_rog_reg_syn_5.sr (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         2.898ns  (logic 0.375ns, net 2.523ns, 12% logic)                
+ Data Path Delay:         1.708ns  (logic 0.322ns, net 1.386ns, 18% logic)                
  Logic Levels:            1 ( LUT2=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3828,34 +3646,34 @@ Paths for end point scan_start_diff/a_ex_frame_en_reg_syn_5 (1 paths)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
  clkubus_rstn_reg_syn_8.q[0]                                 clk2q                   0.109 r     2.047
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 14)      2.171 r     4.218      ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.179 r     4.397
- scan_start_diff/a_ex_frame_en_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net  (fanout = 16)      0.352 r     4.749      ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/a_ex_frame_en_reg_syn_5                     path2reg                0.087       4.836
- Arrival time                                                                        4.836                  (1 lvl)       
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 16)      0.991 r     3.038      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.126 r     3.164
+ scan_start_diff/a_frame_pad_rog_reg_syn_5.sr (BUSY_MIPI_sync_d0_i_syn_9) net  (fanout = 11)      0.395 r     3.559      ../../../../hg_mp/drx_top/huagao_mipi_top.v(570)
+ scan_start_diff/a_frame_pad_rog_reg_syn_5                   path2reg                0.087       3.646
+ Arrival time                                                                        3.646                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- scan_start_diff/a_ex_frame_en_reg_syn_5.clk (exdev_ctl_a/clk_adc) net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/a_frame_pad_rog_reg_syn_5.clk (exdev_ctl_a/clk_adc) net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell removal                                                                        0.253       2.383
  clock uncertainty                                                                   0.000       2.383
- clock recovergence pessimism                                                       -0.084       2.299
- Required time                                                                       2.299            
+ clock recovergence pessimism                                                       -0.147       2.236
+ Required time                                                                       2.236            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               2.537ns          
+ Slack                                                                               1.410ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
+Paths for end point scan_start_diff/reg2_syn_22 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (removal check):   2.627 ns                                                        
+ Slack (removal check):   1.433 ns                                                        
  Start Point:             clkubus_rstn_reg_syn_8.clk (rising edge triggered by clock clk_adc)
- End Point:               scan_start_diff/reg2_syn_19.sr (rising edge triggered by clock clk_adc)
+ End Point:               scan_start_diff/reg2_syn_22.sr (rising edge triggered by clock clk_adc)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         2.988ns  (logic 0.375ns, net 2.613ns, 12% logic)                
+ Data Path Delay:         1.731ns  (logic 0.322ns, net 1.409ns, 18% logic)                
  Logic Levels:            1 ( LUT2=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3866,23 +3684,23 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
  launch clock edge                                                                   0.000       1.938
 ---------------------------------------------------------------------------------------------------------
  clkubus_rstn_reg_syn_8.q[0]                                 clk2q                   0.109 r     2.047
- scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 14)      2.171 r     4.218      ../../../../hg_mp/cdc/cdc_sync.v(9)
- scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.179 r     4.397
- scan_start_diff/reg2_syn_19.sr (BUSY_MIPI_sync_d0_i_syn_9)  net  (fanout = 16)      0.442 r     4.839      ../../../../hg_mp/drx_top/huagao_mipi_top.v(548)
- scan_start_diff/reg2_syn_19                                 path2reg                0.087       4.926
- Arrival time                                                                        4.926                  (1 lvl)       
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0] (u_softrst_fan_ctrl/signal_from[0]) net  (fanout = 16)      0.991 r     3.038      ../../../../hg_mp/cdc/cdc_sync.v(9)
+ scan_start_diff/sys_initial_done_d0_reg_syn_8.f[0]          cell (LUT2)             0.126 r     3.164
+ scan_start_diff/reg2_syn_22.sr (BUSY_MIPI_sync_d0_i_syn_9)  net  (fanout = 11)      0.418 r     3.582      ../../../../hg_mp/drx_top/huagao_mipi_top.v(570)
+ scan_start_diff/reg2_syn_22                                 path2reg                0.087       3.669
+ Arrival time                                                                        3.669                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[4]                                                              0.000       0.000                    
- scan_start_diff/reg2_syn_19.clk (exdev_ctl_a/clk_adc)       net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
+ scan_start_diff/reg2_syn_22.clk (exdev_ctl_a/clk_adc)       net                     2.130       2.130      ../../../../hg_mp/fe/exdev_ctl.v(4)
  capture clock edge                                                                  0.000       2.130
 ---------------------------------------------------------------------------------------------------------
  cell removal                                                                        0.253       2.383
  clock uncertainty                                                                   0.000       2.383
- clock recovergence pessimism                                                       -0.084       2.299
- Required time                                                                       2.299            
+ clock recovergence pessimism                                                       -0.147       2.236
+ Required time                                                                       2.236            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               2.627ns          
+ Slack                                                                               1.433ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -3891,19 +3709,19 @@ Paths for end point scan_start_diff/reg2_syn_19 (1 paths)
 Timing constraint:        clock: S_clk_x2                                                 
 Clock = S_clk_x2, period 4.629ns, rising at 0ns, falling at 2.314ns
 
-80 endpoints analyzed totally, and 146 paths analyzed
+86 endpoints analyzed totally, and 152 paths analyzed
 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 2.561ns
+Minimum period is 2.21ns
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     2.068 ns                                                        
- Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
+ Slack (setup check):     2.419 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (rising edge triggered by clock S_clk)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (rising edge triggered by clock S_clk_x2)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         2.201ns  (logic 0.695ns, net 1.506ns, 31% logic)                
+ Data Path Delay:         1.850ns  (logic 0.597ns, net 1.253ns, 32% logic)                
  Logic Levels:            1 ( LUT3=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -3912,17 +3730,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.q[0] clk2q                   0.146 r     2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0]) net  (fanout = 1)       1.506 r     4.062      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3)        0.549       4.611
- Arrival time                                                                        4.611                  (1 lvl)       
+ sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.q[1] clk2q                   0.146 r     2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net  (fanout = 1)       1.253 r     3.809      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3)        0.451       4.260
+ Arrival time                                                                        4.260                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  capture clock edge                                                                  4.629       6.795
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116       6.679
@@ -3930,164 +3748,164 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapp
  clock recovergence pessimism                                                        0.000       6.679
  Required time                                                                       6.679            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               2.068ns          
+ Slack                                                                               2.419ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     2.526 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.743ns  (logic 0.612ns, net 1.131ns, 35% logic)                
- Logic Levels:            1 ( LUT3=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.q[1] clk2q                   0.146 r     2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4]) net  (fanout = 1)       1.131 r     3.687      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3)        0.466       4.153
- Arrival time                                                                        4.153                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge                                                                  4.629       6.795
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       6.679
- clock uncertainty                                                                  -0.000       6.679
- clock recovergence pessimism                                                        0.000       6.679
- Required time                                                                       6.679            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               2.526ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     2.297 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (rising edge triggered by clock S_clk_x2)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.972ns  (logic 0.695ns, net 1.277ns, 35% logic)                
- Logic Levels:            1 ( LUT3=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.q[0] clk2q                   0.146 r     2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net  (fanout = 1)       1.277 r     3.833      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3)        0.549       4.382
- Arrival time                                                                        4.382                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge                                                                  4.629       6.795
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       6.679
- clock uncertainty                                                                  -0.000       6.679
- clock recovergence pessimism                                                        0.000       6.679
- Required time                                                                       6.679            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               2.297ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     2.367 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (rising edge triggered by clock S_clk_x2)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.902ns  (logic 0.612ns, net 1.290ns, 32% logic)                
- Logic Levels:            1 ( LUT3=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.q[1] clk2q                   0.146 r     2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net  (fanout = 1)       1.290 r     3.846      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3)        0.466       4.312
- Arrival time                                                                        4.312                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge                                                                  4.629       6.795
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       6.679
- clock uncertainty                                                                  -0.000       6.679
- clock recovergence pessimism                                                        0.000       6.679
- Required time                                                                       6.679            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               2.367ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 (2 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     2.443 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         1.826ns  (logic 0.695ns, net 1.131ns, 38% logic)                
- Logic Levels:            1 ( LUT3=1 )                                                    
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
- u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
- u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.q[0] clk2q                   0.146 r     2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[2]) net  (fanout = 1)       1.131 r     3.687      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3)        0.549       4.236
- Arrival time                                                                        4.236                  (1 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- capture clock edge                                                                  4.629       6.795
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.116       6.679
- clock uncertainty                                                                  -0.000       6.679
- clock recovergence pessimism                                                        0.000       6.679
- Required time                                                                       6.679            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               2.443ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     2.532 ns                                                        
+ Slack (setup check):     2.942 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (rising edge triggered by clock S_clk_x2)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         1.737ns  (logic 0.612ns, net 1.125ns, 35% logic)                
+ Data Path Delay:         1.327ns  (logic 0.506ns, net 0.821ns, 38% logic)                
+ Logic Levels:            1 ( LUT3=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[0] clk2q                   0.146 r     2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net  (fanout = 1)       0.821 r     3.377      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg1 (LUT3)        0.360       3.737
+ Arrival time                                                                        3.737                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge                                                                  4.629       6.795
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       6.679
+ clock uncertainty                                                                  -0.000       6.679
+ clock recovergence pessimism                                                        0.000       6.679
+ Required time                                                                       6.679            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               2.942ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     2.457 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk (rising edge triggered by clock S_clk)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.812ns  (logic 0.612ns, net 1.200ns, 33% logic)                
+ Logic Levels:            1 ( LUT3=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.q[1] clk2q                   0.146 r     2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5]) net  (fanout = 1)       1.200 r     3.756      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3)        0.466       4.222
+ Arrival time                                                                        4.222                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge                                                                  4.629       6.795
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       6.679
+ clock uncertainty                                                                  -0.000       6.679
+ clock recovergence pessimism                                                        0.000       6.679
+ Required time                                                                       6.679            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               2.457ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     3.101 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk (rising edge triggered by clock S_clk)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.168ns  (logic 0.695ns, net 0.473ns, 59% logic)                
+ Logic Levels:            1 ( LUT3=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.q[0] clk2q                   0.146 r     2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1]) net  (fanout = 1)       0.473 r     3.029      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3)        0.549       3.578
+ Arrival time                                                                        3.578                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge                                                                  4.629       6.795
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       6.679
+ clock uncertainty                                                                  -0.000       6.679
+ clock recovergence pessimism                                                        0.000       6.679
+ Required time                                                                       6.679            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               3.101ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 (2 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     2.507 ns                                                        
+ Start Point:             sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (rising edge triggered by clock S_clk)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (rising edge triggered by clock S_clk_x2)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.762ns  (logic 0.597ns, net 1.165ns, 33% logic)                
+ Logic Levels:            1 ( LUT3=1 )                                                    
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.q[0] clk2q                   0.146 r     2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0]) net  (fanout = 1)       1.165 r     3.721      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3)        0.451       4.172
+ Arrival time                                                                        4.172                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge                                                                  4.629       6.795
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.116       6.679
+ clock uncertainty                                                                  -0.000       6.679
+ clock recovergence pessimism                                                        0.000       6.679
+ Required time                                                                       6.679            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               2.507ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     2.831 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (rising edge triggered by clock S_clk_x2)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         1.438ns  (logic 0.506ns, net 0.932ns, 35% logic)                
  Logic Levels:            1 ( LUT3=1 )                                                    
 
  Point                                                       Type                     Incr        Path      Info          
@@ -4100,13 +3918,13 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.q[1] clk2q                   0.146 r     2.556
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[6]) net  (fanout = 1)       1.125 r     3.681      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2 path2reg0 (LUT3)        0.466       4.147
- Arrival time                                                                        4.147                  (1 lvl)       
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4]) net  (fanout = 1)       0.932 r     3.488      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2 path2reg0 (LUT3)        0.360       3.848
+ Arrival time                                                                        3.848                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.166       2.166      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  capture clock edge                                                                  4.629       6.795
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.116       6.679
@@ -4114,17 +3932,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapp
  clock recovergence pessimism                                                        0.000       6.679
  Required time                                                                       6.679            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               2.532ns          
+ Slack                                                                               2.831ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Hold checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69 (1 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69 (1 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.167 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk (rising edge triggered by clock S_clk)
- End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.mi[0] (rising edge triggered by clock S_clk_x2)
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.mi[0] (rising edge triggered by clock S_clk_x2)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.429ns  (logic 0.204ns, net 0.225ns, 47% logic)                
@@ -4136,17 +3954,17 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.q[0] clk2q                   0.109 r     2.138
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net  (fanout = 1)       0.225 r     2.363      encrypted_text(0)
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69 path2reg0               0.095       2.458
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.q[0] clk2q                   0.109 r     2.138
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d) net  (fanout = 1)       0.225 r     2.363      encrypted_text(0)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69 path2reg0               0.095       2.458
  Arrival time                                                                        2.458                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.291
@@ -4158,14 +3976,14 @@ Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5 (1 paths)
+Paths for end point sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69 (1 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.281 ns                                                        
+ Slack (hold check):      0.190 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
+ End Point:               sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.mi[0] (rising edge triggered by clock S_clk_x2)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.543ns  (logic 0.204ns, net 0.339ns, 37% logic)                
+ Data Path Delay:         0.452ns  (logic 0.204ns, net 0.248ns, 45% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -4178,13 +3996,13 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.q[0] clk2q                   0.109 r     2.138
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d) net  (fanout = 5)       0.339 r     2.477      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5 path2reg0               0.095       2.572
- Arrival time                                                                        2.572                  (0 lvl)       
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d) net  (fanout = 5)       0.248 r     2.386      encrypted_text(0)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69 path2reg0               0.095       2.481
+ Arrival time                                                                        2.481                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.291
@@ -4192,19 +4010,19 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
  clock recovergence pessimism                                                        0.000       2.291
  Required time                                                                       2.291            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.281ns          
+ Slack                                                                               0.190ns          
 
 ---------------------------------------------------------------------------------------------------------
 
-Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 (1 paths)
+Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 (2 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.306 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk (rising edge triggered by clock S_clk)
- End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0] (rising edge triggered by clock S_clk_x2)
+ Slack (hold check):      0.341 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.d[1] (rising edge triggered by clock S_clk_x2)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.568ns  (logic 0.204ns, net 0.364ns, 35% logic)                
- Logic Levels:            0                                                               
+ Data Path Delay:         0.603ns  (logic 0.378ns, net 0.225ns, 62% logic)                
+ Logic Levels:            1                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
@@ -4212,17 +4030,17 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
  u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
  u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
  u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.q[0] clk2q                   0.109 r     2.138
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en) net  (fanout = 12)      0.364 r     2.502      encrypted_text(0)
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5 path2reg0               0.095       2.597
- Arrival time                                                                        2.597                  (0 lvl)       
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.q[0] clk2q                   0.109 r     2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.d[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_en) net  (fanout = 2)       0.225 r     2.363      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 path2reg1               0.269       2.632
+ Arrival time                                                                        2.632                  (1 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  capture clock edge                                                                  0.000       2.230
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                           0.061       2.291
@@ -4230,7 +4048,43 @@ Paths for end point u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapp
  clock recovergence pessimism                                                        0.000       2.291
  Required time                                                                       2.291            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.306ns          
+ Slack                                                                               0.341ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.490 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (rising edge triggered by clock S_clk)
+ End Point:               u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.c[1] (rising edge triggered by clock S_clk_x2)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.752ns  (logic 0.430ns, net 0.322ns, 57% logic)                
+ Logic Levels:            1                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[0]                                                              0.000       0.000                    
+ u_pll/bufg_feedback.clki (u_pll/clk0_buf)                   net                     0.000       0.000      ../../../../hg_mp/anlogic_ip/pll/pll.v(46)
+ u_pll/bufg_feedback.clko                                    cell (GCLK)             0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk (u_mipi_dphy_tx_wrapper/I_lpdt_clk) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(21)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.q[1] clk2q                   0.109 r     2.138
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.c[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data[0]) net  (fanout = 1)       0.322 r     2.460      encrypted_text(0)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2 path2reg1               0.321       2.781
+ Arrival time                                                                        2.781                  (1 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.230       2.230      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ capture clock edge                                                                  0.000       2.230
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                           0.061       2.291
+ clock uncertainty                                                                   0.000       2.291
+ clock recovergence pessimism                                                        0.000       2.291
+ Required time                                                                       2.291            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.490ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -4241,120 +4095,154 @@ Clock = S_clk_x4, period 2.314ns, rising at 0ns, falling at 1.157ns
 
 8 endpoints analyzed totally, and 32 paths analyzed
 0 errors detected : 0 setup errors (TNS = 0.000), 0 hold errors (TNS = 0.000)
-Minimum period is 1.438ns
----------------------------------------------------------------------------------------------------------
-
-Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
----------------------------------------------------------------------------------------------------------
- Slack (setup check):     0.876 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[0]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         0.824ns  (logic 0.146ns, net 0.678ns, 17% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q                   0.146 r     2.556
- O_data_hs_p[0]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.678 r     3.234      encrypted_text(0)
- O_data_hs_p[0]_syn_2                                        path2reg                0.000       3.234
- Arrival time                                                                        3.234                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  2.314       4.171
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.061       4.110
- clock uncertainty                                                                  -0.000       4.110
- clock recovergence pessimism                                                        0.000       4.110
- Required time                                                                       4.110            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.876ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     0.952 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         0.748ns  (logic 0.146ns, net 0.602ns, 19% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q                   0.146 r     2.556
- O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.602 r     3.158      encrypted_text(0)
- O_data_hs_p[0]_syn_2                                        path2reg                0.000       3.158
- Arrival time                                                                        3.158                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  2.314       4.171
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.061       4.110
- clock uncertainty                                                                  -0.000       4.110
- clock recovergence pessimism                                                        0.000       4.110
- Required time                                                                       4.110            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.952ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     1.028 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         0.672ns  (logic 0.146ns, net 0.526ns, 21% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q                   0.146 r     2.556
- O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.526 r     3.082      encrypted_text(0)
- O_data_hs_p[0]_syn_2                                        path2reg                0.000       3.082
- Arrival time                                                                        3.082                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  2.314       4.171
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.061       4.110
- clock uncertainty                                                                  -0.000       4.110
- clock recovergence pessimism                                                        0.000       4.110
- Required time                                                                       4.110            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               1.028ns          
-
+Minimum period is 1.435ns
 ---------------------------------------------------------------------------------------------------------
 
 Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (setup check):     0.925 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ Slack (setup check):     0.879 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         0.821ns  (logic 0.146ns, net 0.675ns, 17% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q                   0.146 r     2.556
+ O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.675 r     3.231      encrypted_text(0)
+ O_data_hs_p[1]_syn_2                                        path2reg                0.000       3.231
+ Arrival time                                                                        3.231                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  2.314       4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.061       4.110
+ clock uncertainty                                                                  -0.000       4.110
+ clock recovergence pessimism                                                        0.000       4.110
+ Required time                                                                       4.110            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.879ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     0.879 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         0.821ns  (logic 0.146ns, net 0.675ns, 17% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q                   0.146 r     2.556
+ O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.675 r     3.231      encrypted_text(0)
+ O_data_hs_p[1]_syn_2                                        path2reg                0.000       3.231
+ Arrival time                                                                        3.231                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  2.314       4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.061       4.110
+ clock uncertainty                                                                  -0.000       4.110
+ clock recovergence pessimism                                                        0.000       4.110
+ Required time                                                                       4.110            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.879ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     0.923 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
+ Data Path Delay:         0.777ns  (logic 0.146ns, net 0.631ns, 18% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.146 r     2.556
+ O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net  (fanout = 1)       0.631 r     3.187      encrypted_text(0)
+ O_data_hs_p[1]_syn_2                                        path2reg                0.000       3.187
+ Arrival time                                                                        3.187                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  2.314       4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.061       4.110
+ clock uncertainty                                                                  -0.000       4.110
+ clock recovergence pessimism                                                        0.000       4.110
+ Required time                                                                       4.110            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.923ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (setup check):     0.923 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[2]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
+ Data Path Delay:         0.777ns  (logic 0.146ns, net 0.631ns, 18% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.410
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q                   0.146 r     2.556
+ O_data_hs_p[2]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.631 r     3.187      encrypted_text(0)
+ O_data_hs_p[2]_syn_2                                        path2reg                0.000       3.187
+ Arrival time                                                                        3.187                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  2.314       4.171
+---------------------------------------------------------------------------------------------------------
+ cell setup                                                                         -0.061       4.110
+ clock uncertainty                                                                  -0.000       4.110
+ clock recovergence pessimism                                                        0.000       4.110
+ Required time                                                                       4.110            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.923ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (setup check):     0.925 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[2]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Slow                                                            
  Data Path Delay:         0.775ns  (logic 0.146ns, net 0.629ns, 18% logic)                
  Logic Levels:            0                                                               
 
@@ -4362,17 +4250,17 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.146 r     2.556
- O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net  (fanout = 1)       0.629 r     3.185      encrypted_text(0)
- O_data_hs_p[1]_syn_2                                        path2reg                0.000       3.185
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.146 r     2.556
+ O_data_hs_p[2]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.629 r     3.185      encrypted_text(0)
+ O_data_hs_p[2]_syn_2                                        path2reg                0.000       3.185
  Arrival time                                                                        3.185                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
  capture clock edge                                                                  2.314       4.171
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.061       4.110
@@ -4384,29 +4272,29 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     0.952 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Slack (setup check):     1.224 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[2]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         0.748ns  (logic 0.146ns, net 0.602ns, 19% logic)                
+ Data Path Delay:         0.476ns  (logic 0.146ns, net 0.330ns, 30% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.146 r     2.556
- O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.602 r     3.158      encrypted_text(0)
- O_data_hs_p[1]_syn_2                                        path2reg                0.000       3.158
- Arrival time                                                                        3.158                  (0 lvl)       
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q                   0.146 r     2.556
+ O_data_hs_p[2]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net  (fanout = 1)       0.330 r     2.886      encrypted_text(0)
+ O_data_hs_p[2]_syn_2                                        path2reg                0.000       2.886
+ Arrival time                                                                        2.886                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
  capture clock edge                                                                  2.314       4.171
 ---------------------------------------------------------------------------------------------------------
  cell setup                                                                         -0.061       4.110
@@ -4414,48 +4302,14 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
  clock recovergence pessimism                                                        0.000       4.110
  Required time                                                                       4.110            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.952ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (setup check):     0.952 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Slow                                                            
- Data Path Delay:         0.748ns  (logic 0.146ns, net 0.602ns, 19% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.410
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q                   0.146 r     2.556
- O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.602 r     3.158      encrypted_text(0)
- O_data_hs_p[1]_syn_2                                        path2reg                0.000       3.158
- Arrival time                                                                        3.158                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.857       1.857      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  2.314       4.171
----------------------------------------------------------------------------------------------------------
- cell setup                                                                         -0.061       4.110
- clock uncertainty                                                                  -0.000       4.110
- clock recovergence pessimism                                                        0.000       4.110
- Required time                                                                       4.110            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.952ns          
+ Slack                                                                               1.224ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (setup check):     0.928 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_data_hs_p[3]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
@@ -4466,10 +4320,10 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q                   0.146 r     2.556
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.146 r     2.556
  O_data_hs_p[3]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net  (fanout = 1)       0.626 r     3.182      encrypted_text(0)
  O_data_hs_p[3]_syn_2                                        path2reg                0.000       3.182
  Arrival time                                                                        3.182                  (0 lvl)       
@@ -4488,12 +4342,12 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     0.952 ns                                                        
+ Slack (setup check):     0.929 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         0.748ns  (logic 0.146ns, net 0.602ns, 19% logic)                
+ Data Path Delay:         0.771ns  (logic 0.146ns, net 0.625ns, 18% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -4503,10 +4357,10 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.410       2.410      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.146 r     2.556
- O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.602 r     3.158      encrypted_text(0)
- O_data_hs_p[3]_syn_2                                        path2reg                0.000       3.158
- Arrival time                                                                        3.158                  (0 lvl)       
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q                   0.146 r     2.556
+ O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.625 r     3.181      encrypted_text(0)
+ O_data_hs_p[3]_syn_2                                        path2reg                0.000       3.181
+ Arrival time                                                                        3.181                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
@@ -4518,16 +4372,16 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  clock recovergence pessimism                                                        0.000       4.110
  Required time                                                                       4.110            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.952ns          
+ Slack                                                                               0.929ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):     0.952 ns                                                        
+ Slack (setup check):     1.075 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         0.748ns  (logic 0.146ns, net 0.602ns, 19% logic)                
+ Data Path Delay:         0.625ns  (logic 0.146ns, net 0.479ns, 23% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -4538,9 +4392,9 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q                   0.146 r     2.556
- O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.602 r     3.158      encrypted_text(0)
- O_data_hs_p[3]_syn_2                                        path2reg                0.000       3.158
- Arrival time                                                                        3.158                  (0 lvl)       
+ O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.479 r     3.035      encrypted_text(0)
+ O_data_hs_p[3]_syn_2                                        path2reg                0.000       3.035
+ Arrival time                                                                        3.035                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
@@ -4552,17 +4406,17 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  clock recovergence pessimism                                                        0.000       4.110
  Required time                                                                       4.110            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.952ns          
+ Slack                                                                               1.075ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Hold checks:
 ---------------------------------------------------------------------------------------------------------
-Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
+Paths for end point O_data_hs_p[2]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.401 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[0]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[2]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.334ns  (logic 0.109ns, net 0.225ns, 32% logic)                
@@ -4572,17 +4426,17 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[1] clk2q                   0.109 r     2.138
- O_data_hs_p[0]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net  (fanout = 1)       0.225 r     2.363      encrypted_text(0)
- O_data_hs_p[0]_syn_2                                        path2reg                0.000       2.363
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q                   0.109 r     2.138
+ O_data_hs_p[2]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net  (fanout = 1)       0.225 r     2.363      encrypted_text(0)
+ O_data_hs_p[2]_syn_2                                        path2reg                0.000       2.363
  Arrival time                                                                        2.363                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
  capture clock edge                                                                  0.000       1.965
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                          -0.003       1.962
@@ -4594,79 +4448,9 @@ Paths for end point O_data_hs_p[0]_syn_2 (4 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.546 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[0]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.479ns  (logic 0.109ns, net 0.370ns, 22% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q                   0.109 r     2.138
- O_data_hs_p[0]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.370 r     2.508      encrypted_text(0)
- O_data_hs_p[0]_syn_2                                        path2reg                0.000       2.508
- Arrival time                                                                        2.508                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  0.000       1.965
----------------------------------------------------------------------------------------------------------
- cell hold                                                                          -0.003       1.962
- clock uncertainty                                                                   0.000       1.962
- clock recovergence pessimism                                                        0.000       1.962
- Required time                                                                       1.962            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.546ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.583 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[0]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.516ns  (logic 0.109ns, net 0.407ns, 21% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.q[0] clk2q                   0.109 r     2.138
- O_data_hs_p[0]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.407 r     2.545      encrypted_text(0)
- O_data_hs_p[0]_syn_2                                        path2reg                0.000       2.545
- Arrival time                                                                        2.545                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[0]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  0.000       1.965
----------------------------------------------------------------------------------------------------------
- cell hold                                                                          -0.003       1.962
- clock uncertainty                                                                   0.000       1.962
- clock recovergence pessimism                                                        0.000       1.962
- Required time                                                                       1.962            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.583ns          
-
----------------------------------------------------------------------------------------------------------
-
-Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
----------------------------------------------------------------------------------------------------------
  Slack (hold check):      0.401 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[1]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[2]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
  Data Path Delay:         0.334ns  (logic 0.109ns, net 0.225ns, 32% logic)                
@@ -4676,17 +4460,17 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q                   0.109 r     2.138
- O_data_hs_p[1]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.225 r     2.363      encrypted_text(0)
- O_data_hs_p[1]_syn_2                                        path2reg                0.000       2.363
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.q[0] clk2q                   0.109 r     2.138
+ O_data_hs_p[2]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.225 r     2.363      encrypted_text(0)
+ O_data_hs_p[2]_syn_2                                        path2reg                0.000       2.363
  Arrival time                                                                        2.363                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
  capture clock edge                                                                  0.000       1.965
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                          -0.003       1.962
@@ -4698,29 +4482,29 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.583 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Slack (hold check):      0.623 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[2]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.516ns  (logic 0.109ns, net 0.407ns, 21% logic)                
+ Data Path Delay:         0.556ns  (logic 0.109ns, net 0.447ns, 19% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
 ---------------------------------------------------------------------------------------------------------
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.109 r     2.138
- O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.407 r     2.545      encrypted_text(0)
- O_data_hs_p[1]_syn_2                                        path2reg                0.000       2.545
- Arrival time                                                                        2.545                  (0 lvl)       
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.109 r     2.138
+ O_data_hs_p[2]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.447 r     2.585      encrypted_text(0)
+ O_data_hs_p[2]_syn_2                                        path2reg                0.000       2.585
+ Arrival time                                                                        2.585                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ O_data_hs_p[2]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
  capture clock edge                                                                  0.000       1.965
 ---------------------------------------------------------------------------------------------------------
  cell hold                                                                          -0.003       1.962
@@ -4728,52 +4512,18 @@ Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
  clock recovergence pessimism                                                        0.000       1.962
  Required time                                                                       1.962            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.583ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.583 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.516ns  (logic 0.109ns, net 0.407ns, 21% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q                   0.109 r     2.138
- O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.407 r     2.545      encrypted_text(0)
- O_data_hs_p[1]_syn_2                                        path2reg                0.000       2.545
- Arrival time                                                                        2.545                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  0.000       1.965
----------------------------------------------------------------------------------------------------------
- cell hold                                                                          -0.003       1.962
- clock uncertainty                                                                   0.000       1.962
- clock recovergence pessimism                                                        0.000       1.962
- Required time                                                                       1.962            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.583ns          
+ Slack                                                                               0.623ns          
 
 ---------------------------------------------------------------------------------------------------------
 
 Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
 ---------------------------------------------------------------------------------------------------------
- Slack (hold check):      0.401 ns                                                        
+ Slack (hold check):      0.498 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_data_hs_p[3]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.334ns  (logic 0.109ns, net 0.225ns, 32% logic)                
+ Data Path Delay:         0.431ns  (logic 0.109ns, net 0.322ns, 25% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -4784,9 +4534,9 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[0] clk2q                   0.109 r     2.138
- O_data_hs_p[3]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.225 r     2.363      encrypted_text(0)
- O_data_hs_p[3]_syn_2                                        path2reg                0.000       2.363
- Arrival time                                                                        2.363                  (0 lvl)       
+ O_data_hs_p[3]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.322 r     2.460      encrypted_text(0)
+ O_data_hs_p[3]_syn_2                                        path2reg                0.000       2.460
+ Arrival time                                                                        2.460                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
@@ -4798,50 +4548,16 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  clock recovergence pessimism                                                        0.000       1.962
  Required time                                                                       1.962            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.401ns          
+ Slack                                                                               0.498ns          
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (hold check):      0.583 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
- Clock group:             clock_source                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.516ns  (logic 0.109ns, net 0.407ns, 21% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.109 r     2.138
- O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.407 r     2.545      encrypted_text(0)
- O_data_hs_p[3]_syn_2                                        path2reg                0.000       2.545
- Arrival time                                                                        2.545                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
- O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
- capture clock edge                                                                  0.000       1.965
----------------------------------------------------------------------------------------------------------
- cell hold                                                                          -0.003       1.962
- clock uncertainty                                                                   0.000       1.962
- clock recovergence pessimism                                                        0.000       1.962
- Required time                                                                       1.962            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               0.583ns          
-
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      0.583 ns                                                        
+ Slack (hold check):      0.508 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_data_hs_p[3]_syn_2.do[1] (rising edge triggered by clock S_clk_x4)
  Clock group:             clock_source                                                    
  Process:                 Fast                                                            
- Data Path Delay:         0.516ns  (logic 0.109ns, net 0.407ns, 21% logic)                
+ Data Path Delay:         0.441ns  (logic 0.109ns, net 0.332ns, 24% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -4852,9 +4568,9 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  launch clock edge                                                                   0.000       2.029
 ---------------------------------------------------------------------------------------------------------
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.q[1] clk2q                   0.109 r     2.138
- O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.407 r     2.545      encrypted_text(0)
- O_data_hs_p[3]_syn_2                                        path2reg                0.000       2.545
- Arrival time                                                                        2.545                  (0 lvl)       
+ O_data_hs_p[3]_syn_2.do[1] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1]) net  (fanout = 1)       0.332 r     2.470      encrypted_text(0)
+ O_data_hs_p[3]_syn_2                                        path2reg                0.000       2.470
+ Arrival time                                                                        2.470                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
@@ -4866,7 +4582,145 @@ Paths for end point O_data_hs_p[3]_syn_2 (4 paths)
  clock recovergence pessimism                                                        0.000       1.962
  Required time                                                                       1.962            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                               0.583ns          
+ Slack                                                                               0.508ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.614 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[3]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.547ns  (logic 0.109ns, net 0.438ns, 19% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q                   0.109 r     2.138
+ O_data_hs_p[3]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.438 r     2.576      encrypted_text(0)
+ O_data_hs_p[3]_syn_2                                        path2reg                0.000       2.576
+ Arrival time                                                                        2.576                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[3]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  0.000       1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                          -0.003       1.962
+ clock uncertainty                                                                   0.000       1.962
+ clock recovergence pessimism                                                        0.000       1.962
+ Required time                                                                       1.962            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.614ns          
+
+---------------------------------------------------------------------------------------------------------
+
+Paths for end point O_data_hs_p[1]_syn_2 (4 paths)
+---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      0.507 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[1]_syn_2.do[0] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.440ns  (logic 0.109ns, net 0.331ns, 24% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.q[1] clk2q                   0.109 r     2.138
+ O_data_hs_p[1]_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0]) net  (fanout = 1)       0.331 r     2.469      encrypted_text(0)
+ O_data_hs_p[1]_syn_2                                        path2reg                0.000       2.469
+ Arrival time                                                                        2.469                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  0.000       1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                          -0.003       1.962
+ clock uncertainty                                                                   0.000       1.962
+ clock recovergence pessimism                                                        0.000       1.962
+ Required time                                                                       1.962            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.507ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.624 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[1]_syn_2.do[2] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.557ns  (logic 0.109ns, net 0.448ns, 19% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[0] clk2q                   0.109 r     2.138
+ O_data_hs_p[1]_syn_2.do[2] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2]) net  (fanout = 1)       0.448 r     2.586      encrypted_text(0)
+ O_data_hs_p[1]_syn_2                                        path2reg                0.000       2.586
+ Arrival time                                                                        2.586                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  0.000       1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                          -0.003       1.962
+ clock uncertainty                                                                   0.000       1.962
+ clock recovergence pessimism                                                        0.000       1.962
+ Required time                                                                       1.962            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.624ns          
+
+---------------------------------------------------------------------------------------------------------
+
+ Slack (hold check):      0.653 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_data_hs_p[1]_syn_2.do[3] (rising edge triggered by clock S_clk_x4)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.586ns  (logic 0.109ns, net 0.477ns, 18% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.q[1] clk2q                   0.109 r     2.138
+ O_data_hs_p[1]_syn_2.do[3] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3]) net  (fanout = 1)       0.477 r     2.615      encrypted_text(0)
+ O_data_hs_p[1]_syn_2                                        path2reg                0.000       2.615
+ Arrival time                                                                        2.615                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[2]                                                              0.000       0.000                    
+ O_data_hs_p[1]_syn_2.osclk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(17)
+ capture clock edge                                                                  0.000       1.965
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                          -0.003       1.962
+ clock uncertainty                                                                   0.000       1.962
+ clock recovergence pessimism                                                        0.000       1.962
+ Required time                                                                       1.962            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               0.653ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -4916,12 +4770,12 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
 
 ---------------------------------------------------------------------------------------------------------
 
- Slack (setup check):    -0.810 ns                                                        
+ Slack (setup check):    -0.708 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d)
  Clock group:             clock_source                                                    
  Process:                 Slow                                                            
- Data Path Delay:         0.774ns  (logic 0.146ns, net 0.628ns, 18% logic)                
+ Data Path Delay:         0.672ns  (logic 0.146ns, net 0.526ns, 21% logic)                
  Logic Levels:            0                                                               
 
  Point                                                       Type                     Incr        Path      Info          
@@ -4932,9 +4786,9 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
  launch clock edge                                                                   0.000       2.410
 ---------------------------------------------------------------------------------------------------------
  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q                   0.146 r     2.556
- O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net  (fanout = 2)       0.628 r     3.184      encrypted_text(0)
- O_clk_hs_p_syn_2                                            path2reg                0.000       3.184
- Arrival time                                                                        3.184                  (0 lvl)       
+ O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net  (fanout = 2)       0.526 r     3.082      encrypted_text(0)
+ O_clk_hs_p_syn_2                                            path2reg                0.000       3.082
+ Arrival time                                                                        3.082                  (0 lvl)       
 
  source latency                                                                      0.000       0.000                    
  u_pll/pll_inst.clkc[3]                                                              0.000       0.000                    
@@ -4946,7 +4800,7 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
  clock recovergence pessimism                                                        0.000       2.374
  Required time                                                                       2.374            
 ---------------------------------------------------------------------------------------------------------
- Slack                                                                              -0.810ns          
+ Slack                                                                              -0.708ns          
 
 ---------------------------------------------------------------------------------------------------------
 
@@ -4954,6 +4808,40 @@ Hold checks:
 ---------------------------------------------------------------------------------------------------------
 Paths for end point O_clk_hs_p_syn_2 (2 paths)
 ---------------------------------------------------------------------------------------------------------
+ Slack (hold check):      2.282 ns                                                        
+ Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
+ End Point:               O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d)
+ Clock group:             clock_source                                                    
+ Process:                 Fast                                                            
+ Data Path Delay:         0.479ns  (logic 0.109ns, net 0.370ns, 22% logic)                
+ Logic Levels:            0                                                               
+
+ Point                                                       Type                     Incr        Path      Info          
+---------------------------------------------------------------------------------------------------------
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
+ launch clock edge                                                                   0.000       2.029
+---------------------------------------------------------------------------------------------------------
+ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q                   0.109 r     2.138
+ O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net  (fanout = 2)       0.370 r     2.508      encrypted_text(0)
+ O_clk_hs_p_syn_2                                            path2reg                0.000       2.508
+ Arrival time                                                                        2.508                  (0 lvl)       
+
+ source latency                                                                      0.000       0.000                    
+ u_pll/pll_inst.clkc[3]                                                              0.000       0.000                    
+ O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20)
+ capture clock edge                                                                 -1.736       0.229
+---------------------------------------------------------------------------------------------------------
+ cell hold                                                                          -0.003       0.226
+ clock uncertainty                                                                   0.000       0.226
+ clock recovergence pessimism                                                        0.000       0.226
+ Required time                                                                       0.226            
+---------------------------------------------------------------------------------------------------------
+ Slack                                                                               2.282ns          
+
+---------------------------------------------------------------------------------------------------------
+
  Slack (hold check):      2.359 ns                                                        
  Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
  End Point:               O_clk_hs_p_syn_2.do[2] (rising edge triggered by clock S_clk_x4_90d)
@@ -4986,61 +4874,27 @@ Paths for end point O_clk_hs_p_syn_2 (2 paths)
 ---------------------------------------------------------------------------------------------------------
  Slack                                                                               2.359ns          
 
----------------------------------------------------------------------------------------------------------
-
- Slack (hold check):      2.359 ns                                                        
- Start Point:             u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (rising edge triggered by clock S_clk_x2)
- End Point:               O_clk_hs_p_syn_2.do[0] (rising edge triggered by clock S_clk_x4_90d)
- Clock group:             clock_source                                                    
- Process:                 Fast                                                            
- Data Path Delay:         0.556ns  (logic 0.109ns, net 0.447ns, 19% logic)                
- Logic Levels:            0                                                               
-
- Point                                                       Type                     Incr        Path      Info          
----------------------------------------------------------------------------------------------------------
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[1]                                                              0.000       0.000                    
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2) net                     2.029       2.029      ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(16)
- launch clock edge                                                                   0.000       2.029
----------------------------------------------------------------------------------------------------------
- u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.q[1] clk2q                   0.109 r     2.138
- O_clk_hs_p_syn_2.do[0] (u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0]) net  (fanout = 2)       0.447 r     2.585      encrypted_text(0)
- O_clk_hs_p_syn_2                                            path2reg                0.000       2.585
- Arrival time                                                                        2.585                  (0 lvl)       
-
- source latency                                                                      0.000       0.000                    
- u_pll/pll_inst.clkc[3]                                                              0.000       0.000                    
- O_clk_hs_p_syn_2.osclk (u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d) net                     1.965       1.965      ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(20)
- capture clock edge                                                                 -1.736       0.229
----------------------------------------------------------------------------------------------------------
- cell hold                                                                          -0.003       0.226
- clock uncertainty                                                                   0.000       0.226
- clock recovergence pessimism                                                        0.000       0.226
- Required time                                                                       0.226            
----------------------------------------------------------------------------------------------------------
- Slack                                                                               2.359ns          
-
 ---------------------------------------------------------------------------------------------------------
 
 
 =========================================================================================================
 Timing summary:                                                                           
 ---------------------------------------------------------------------------------------------------------
-Constraint path number: 357308 (STA coverage = 91.87%)
-Timing violations: 5 setup errors, and 0 hold errors.
-Minimal setup slack: -1.945, minimal hold slack: 0.067
+Constraint path number: 364350 (STA coverage = 91.56%)
+Timing violations: 2 setup errors, and 0 hold errors.
+Minimal setup slack: -0.811, minimal hold slack: 0.067
 
 Timing group statistics: 
 	Clock constraints: 
 	  Clock Name                                  Min Period     Max Freq           Skew      Fanout            TNS
-	  S_clk (108.0MHz)                               9.050ns     110.497MHz        0.326ns      1810        0.000ns
-	  a_pclk (48.0MHz)                              12.299ns      81.307MHz        0.326ns      1425        0.000ns
-	  b_pclk (48.0MHz)                              10.093ns      99.079MHz        0.326ns      1358        0.000ns
-	  clk_adc (6.0MHz)                             168.609ns       5.931MHz        0.326ns       942       -3.279ns
-	  a_sclk (168.0MHz)                              2.172ns     460.405MHz        0.254ns        69        0.000ns
-	  b_sclk (168.0MHz)                              2.158ns     463.392MHz        0.326ns        69        0.000ns
-	  S_clk_x2 (216.0MHz)                            2.561ns     390.472MHz        0.480ns        22        0.000ns
-	  S_clk_x4 (432.0MHz)                            1.438ns     695.410MHz        0.018ns         4        0.000ns
+	  S_clk (108.0MHz)                               9.231ns     108.331MHz        0.326ns      1825        0.000ns
+	  a_pclk (48.0MHz)                              12.828ns      77.954MHz        0.326ns      1432        0.000ns
+	  b_pclk (48.0MHz)                              10.513ns      95.120MHz        0.326ns      1342        0.000ns
+	  clk_adc (6.0MHz)                             159.250ns       6.279MHz        0.326ns      1235        0.000ns
+	  a_sclk (168.0MHz)                              1.906ns     524.659MHz        0.254ns        71        0.000ns
+	  b_sclk (168.0MHz)                              2.080ns     480.769MHz        0.326ns        70        0.000ns
+	  S_clk_x2 (216.0MHz)                            2.210ns     452.489MHz        0.480ns        22        0.000ns
+	  S_clk_x4 (432.0MHz)                            1.435ns     696.864MHz        0.018ns         4        0.000ns
 	  S_clk_x4_90d (432.0MHz)                        3.125ns     320.000MHz        0.000ns         1       -0.811ns
 	Minimum input arrival time before clock: no constraint path
 	Maximum output required time after clock: no constraint path
@@ -5056,19 +4910,35 @@ Warning: No clock constraint on 3 clock net(s):
 		Check Type:	MAX
 		----------------------------------------------------------------------------------------------------
 		       Path Num     Constraint                                                                      
-		              0     set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ]
 		              0     set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[3]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d} ]
 		              0     set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[1]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2} ]
 		              1     set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ]
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] 
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 
+		              1     set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ]
+		              2     set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ]
 
 		Check Type:	MIN
 		----------------------------------------------------------------------------------------------------
 		       Path Num     Constraint                                                                      
-		              0     set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ]
 		              1     set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ]
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] 
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 
+		              1     set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ]
+		              2     set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ]
 
 ---------------------------------------------------------------------------------------------------------
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
index 1295a84..d454a1f 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_phy.tsm
@@ -1,1319 +1,1299 @@
 eagle_s20
-13 5027 3393 2877 25626 357308 5 0
--1.945 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 38 12
+13 4881 4737 2689 26496 364350 2 0
+-0.811 0.067 huagao_mipi_top eagle_s20 EG4D20EG176 Detail NA 54 12
 clock: a_lvds_clk_p
 15 0 0 0
 
 clock: a_pclk
-23 103438 6218 2
+23 105576 6154 2
 Setup check
 33 3
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-33 8.534000 691 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-35 8.534000 22.857000 14.323000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1]
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6
+33 8.005000 691 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk
+sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6
+35 8.005000 22.929000 14.924000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[1]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-85 8.534000 22.857000 14.323000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[1]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk
+sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6
+85 8.005000 22.929000 14.924000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21
-135 8.534000 22.857000 14.323000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_21.a[0]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk
+sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6
+135 8.005000 22.929000 14.924000 7 9
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/trig_ADC_r1_reg[0]_reg_syn_6.a[0]
 
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-185 8.641000 659 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-187 8.641000 22.929000 14.288000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24
+189 8.153000 659 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24
+191 8.153000 22.929000 14.776000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[1]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-237 8.641000 22.929000 14.288000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[4] U_rgb_to_csi_pakage/mult0_syn_4.a[12]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[1]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24
+241 8.153000 22.929000 14.776000 7 7
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[9] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-sampling_fe_a/u_sort/u_data_prebuffer/reg7_syn_47.clk
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25
-287 8.641000 22.929000 14.288000 7 7
-sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[14]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[6] sampling_fe_a/u_sort/u_transfer_300_to_200/u0_soft_n/signal_to_reg[0]_reg_syn_5.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_396.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1239 u_pic_cnt/reg1_syn_384.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_25.a[0]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk->sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24
+sampling_fe_b/u_sort/u_data_prebuffer_rev/reg7_syn_52.clk
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24
+291 8.153000 22.929000 14.776000 7 9
+sampling_fe_a/u_sort/u_data_prebuffer/sensor_length_trig[9] U_rgb_to_csi_pakage/mult0_syn_4.a[11]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[5] sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE_b5[12] ua_lvds_rx/reg8_syn_170.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1235 u_pic_cnt/reg1_syn_370.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1237 u_pic_cnt/reg1_syn_370.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/ADC_STATE[0]_syn_1243 sampling_fe_a/u_sort/u_data_prebuffer/fifo_adc/reg0_syn_24.a[0]
 
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
-337 12.509000 85 3
-Timing path: scan_start_diff/trigger_syn_7099.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
-scan_start_diff/trigger_syn_7099.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
-339 12.509000 22.929000 10.420000 6 6
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39 sampling_fe_a/u_sort/reg2_syn_54.b[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656 sampling_fe_a/u_sort/reg0_syn_58.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2 sampling_fe_a/u_sort/reg0_syn_58.c[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0]
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716
+345 12.557000 12 3
+Timing path: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716
+u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716
+347 12.557000 22.762000 10.205000 6 6
+u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109 U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2 reg14_syn_50.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_5086 ua_lvds_rx/reg8_syn_184.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_10 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_31.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_12 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[90]_syn_33.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[50]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.c[1]
 
-Timing path: scan_start_diff/trigger_syn_7101.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
-scan_start_diff/trigger_syn_7101.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
-387 12.523000 22.929000 10.406000 6 6
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[0] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.d[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39 sampling_fe_a/u_sort/reg2_syn_54.b[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3656 sampling_fe_a/u_sort/reg0_syn_58.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2 sampling_fe_a/u_sort/reg0_syn_58.c[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0]
+Timing path: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716
+u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716
+393 13.869000 22.762000 8.893000 5 5
+u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109 U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2 reg14_syn_50.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_3436 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.a[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1]
 
-Timing path: scan_start_diff/trigger_syn_7099.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
-scan_start_diff/trigger_syn_7099.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14
-435 12.660000 22.929000 10.269000 6 6
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/DPIset[1] sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_244.c[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg4_syn_39 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[84]_syn_62.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4756 sampling_fe_a/u_sort/reg0_syn_58.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_2 sampling_fe_a/u_sort/reg0_syn_58.c[1]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[94]_syn_4 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_712.a[0]
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[24]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[64]_syn_14.c[0]
+Timing path: u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716
+u_bus_top/u_local_bus_slve_cis/reg43_syn_202_syn_2.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716
+437 14.080000 22.762000 8.682000 5 5
+u_bus_top/u_local_bus_slve_cis/reg2[5]_dup_109 U_rgb_to_csi_pakage/reg4_syn_137_syn_2.c[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[107]_syn_2 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_75.a[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/mux_addr/mux0_syn_4536 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_20 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_80.c[1]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[80]_syn_22 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/reg1_syn_716.b[1]
 
 
 
 Hold check
-483 3
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
-485 0.089000 10 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[75]_syn_8.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
-487 0.089000 2.183000 2.272000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[65] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[8]
+481 3
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1
+483 0.080000 8 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add30_syn_70.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1
+485 0.080000 2.183000 2.263000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[71] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[7]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/ram_switch_state/ram_addr_tmp[95]_syn_22.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
-525 0.195000 2.183000 2.378000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[60] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[3]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_463.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1
+523 0.251000 2.183000 2.434000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[67] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[3]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_735.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1
-563 0.196000 2.183000 2.379000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[66] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.addra[9]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add14_syn_69.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1
+561 0.336000 2.183000 2.519000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_data[68] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.dia[4]
 
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
-601 0.114000 8 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_547.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
-603 0.114000 2.183000 2.297000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[21] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[5]
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1
+599 0.089000 10 3
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_662.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1
+601 0.089000 2.183000 2.272000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[18] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[11]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
-641 0.218000 2.183000 2.401000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[3]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg5_syn_742.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1
+639 0.130000 2.183000 2.313000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[14] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[7]
 
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_512.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1
-679 0.311000 2.183000 2.494000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[22] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.dia[6]
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg6_syn_667.clk
+sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1
+677 0.234000 2.183000 2.417000 1 1
+sampling_fe_a/u_sort/u_data_prebuffer/ram_addr[19] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.addra[12]
 
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
-717 0.114000 8 3
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add8_syn_69.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
-719 0.114000 2.183000 2.297000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[17] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[1]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_549.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
-757 0.196000 2.183000 2.379000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[19] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[3]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk->sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg7_syn_548.clk
-sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1
-795 0.234000 2.183000 2.417000 1 1
-sampling_fe_a/u_sort/u_data_prebuffer/ram_data[16] sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.dia[0]
+Endpoint: u0_test_en/reg0_syn_26
+715 0.167000 1 1
+Timing path: u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk->u0_test_en/reg0_syn_26
+u_bus_top/u_local_bus_slve_cis/reg46_syn_241.clk
+u0_test_en/reg0_syn_26
+717 0.167000 2.191000 2.358000 0 1
+u0_test_en/signal_from[0] u0_test_en/reg0_syn_26.mi[0]
 
 
 
 
 clock: a_sclk
-833 706 282 2
+753 698 282 2
 Setup check
-843 3
+763 3
 Endpoint: ua_lvds_rx/rx_clk_sync_reg_syn_5
-843 3.780000 7 3
-Timing path: ua_lvds_rx/reg7_syn_44.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
-ua_lvds_rx/reg7_syn_44.clk
+763 4.046000 7 3
+Timing path: ua_lvds_rx/reg7_syn_33.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
+ua_lvds_rx/reg7_syn_33.clk
 ua_lvds_rx/rx_clk_sync_reg_syn_5
-845 3.780000 8.210000 4.430000 2 2
-ua_lvds_rx/rx_clk_sft[0] ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0]
+765 4.046000 8.182000 4.136000 2 2
+ua_lvds_rx/rx_clk_sft[1] ua_lvds_rx/rx_clk_sync_reg_syn_5.b[0]
 ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
 
-Timing path: ua_lvds_rx/reg7_syn_47.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
-ua_lvds_rx/reg7_syn_47.clk
+Timing path: ua_lvds_rx/reg7_syn_24.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
+ua_lvds_rx/reg7_syn_24.clk
 ua_lvds_rx/rx_clk_sync_reg_syn_5
-881 3.815000 8.210000 4.395000 2 2
+801 4.086000 8.182000 4.096000 2 2
 ua_lvds_rx/rx_clk_sft[3] ua_lvds_rx/rx_clk_sync_reg_syn_5.d[0]
 ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
 
-Timing path: ua_lvds_rx/reg7_syn_38.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
-ua_lvds_rx/reg7_syn_38.clk
+Timing path: ua_lvds_rx/reg7_syn_30.clk->ua_lvds_rx/rx_clk_sync_reg_syn_5
+ua_lvds_rx/reg7_syn_30.clk
 ua_lvds_rx/rx_clk_sync_reg_syn_5
-917 3.849000 8.210000 4.361000 2 2
-ua_lvds_rx/rx_clk_sft[2] ua_lvds_rx/rx_clk_sync_reg_syn_5.c[0]
+837 4.194000 8.182000 3.988000 2 2
+ua_lvds_rx/rx_clk_sft[0] ua_lvds_rx/rx_clk_sync_reg_syn_5.a[0]
 ua_lvds_rx/rx_clk_sync_n_syn_2 ua_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
 
 
-Endpoint: ua_lvds_rx/reg8_syn_145
-953 4.058000 9 3
-Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_145
-ua_lvds_rx/sync0_reg_syn_4.clk
-ua_lvds_rx/reg8_syn_145
-955 4.058000 8.182000 4.124000 1 1
-ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_145.d[1]
+Endpoint: ua_lvds_rx/ramread0_syn_88
+873 4.116000 2 2
+Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_88
+ua_lvds_rx/reg16_syn_31.clk
+ua_lvds_rx/ramread0_syn_88
+875 4.116000 8.189000 4.073000 1 1
+ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_88.c[0]
 
-Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_145
-ua_lvds_rx/sync0_reg_syn_4.clk
-ua_lvds_rx/reg8_syn_145
-989 4.058000 8.182000 4.124000 1 1
-ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_145.d[0]
-
-Timing path: ua_lvds_rx/reg8_syn_145.clk->ua_lvds_rx/reg8_syn_145
-ua_lvds_rx/reg8_syn_145.clk
-ua_lvds_rx/reg8_syn_145
-1023 4.198000 8.182000 3.984000 1 1
-ua_lvds_rx/para_data[2] ua_lvds_rx/reg8_syn_145.a[1]
+Timing path: ua_lvds_rx/reg8_syn_157.clk->ua_lvds_rx/ramread0_syn_88
+ua_lvds_rx/reg8_syn_157.clk
+ua_lvds_rx/ramread0_syn_88
+909 5.160000 8.189000 3.029000 1 1
+ua_lvds_rx/para_data[22] ua_lvds_rx/ramread0_syn_88.c[1]
 
 
-Endpoint: ua_lvds_rx/reg8_syn_157
-1057 4.092000 9 3
-Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_157
-ua_lvds_rx/sync0_reg_syn_4.clk
-ua_lvds_rx/reg8_syn_157
-1059 4.092000 8.182000 4.090000 1 1
-ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_157.d[1]
+Endpoint: ua_lvds_rx/ramread0_syn_46
+943 4.116000 2 2
+Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_46
+ua_lvds_rx/reg16_syn_31.clk
+ua_lvds_rx/ramread0_syn_46
+945 4.116000 8.189000 4.073000 1 1
+ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_46.c[0]
 
-Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_157
-ua_lvds_rx/sync0_reg_syn_4.clk
-ua_lvds_rx/reg8_syn_157
-1093 4.092000 8.182000 4.090000 1 1
-ua_lvds_rx/sync0 ua_lvds_rx/reg8_syn_157.d[0]
-
-Timing path: ua_lvds_rx/sync0_reg_syn_4.clk->ua_lvds_rx/reg8_syn_157
-ua_lvds_rx/sync0_reg_syn_4.clk
-ua_lvds_rx/reg8_syn_157
-1127 4.387000 8.182000 3.795000 1 1
-ua_lvds_rx/sync1 ua_lvds_rx/reg8_syn_157.mi[0]
+Timing path: ua_lvds_rx/reg8_syn_153.clk->ua_lvds_rx/ramread0_syn_46
+ua_lvds_rx/reg8_syn_153.clk
+ua_lvds_rx/ramread0_syn_46
+979 4.574000 8.189000 3.615000 1 1
+ua_lvds_rx/para_data[10] ua_lvds_rx/ramread0_syn_46.c[1]
 
 
 
 Hold check
-1161 3
+1013 3
 Endpoint: ua_lvds_rx/ramread0_syn_102
-1163 0.092000 2 2
+1015 0.092000 2 2
 Timing path: ua_lvds_rx/reg3_syn_184.clk->ua_lvds_rx/ramread0_syn_102
 ua_lvds_rx/reg3_syn_184.clk
 ua_lvds_rx/ramread0_syn_102
-1165 0.092000 2.157000 2.249000 1 1
-ua_lvds_rx/para_data[25] ua_lvds_rx/ramread0_syn_102.b[1]
+1017 0.092000 2.157000 2.249000 1 1
+ua_lvds_rx/para_data[26] ua_lvds_rx/ramread0_syn_102.c[1]
 
 Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_102
 ua_lvds_rx/reg16_syn_31.clk
 ua_lvds_rx/ramread0_syn_102
-1199 0.409000 2.157000 2.566000 1 1
+1051 0.700000 2.157000 2.857000 1 1
+ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_102.c[0]
+
+
+Endpoint: ua_lvds_rx/ramread0_syn_102
+1085 0.092000 2 2
+Timing path: ua_lvds_rx/reg3_syn_184.clk->ua_lvds_rx/ramread0_syn_102
+ua_lvds_rx/reg3_syn_184.clk
+ua_lvds_rx/ramread0_syn_102
+1087 0.092000 2.157000 2.249000 1 1
+ua_lvds_rx/para_data[25] ua_lvds_rx/ramread0_syn_102.b[1]
+
+Timing path: ua_lvds_rx/reg16_syn_33.clk->ua_lvds_rx/ramread0_syn_102
+ua_lvds_rx/reg16_syn_33.clk
+ua_lvds_rx/ramread0_syn_102
+1121 0.403000 2.157000 2.560000 1 1
 ua_lvds_rx/wcnt[1] ua_lvds_rx/ramread0_syn_102.b[0]
 
 
-Endpoint: ua_lvds_rx/ramread0_syn_116
-1233 0.167000 2 2
-Timing path: ua_lvds_rx/reg14_syn_62.clk->ua_lvds_rx/ramread0_syn_116
-ua_lvds_rx/reg14_syn_62.clk
-ua_lvds_rx/ramread0_syn_116
-1235 0.167000 2.187000 2.354000 1 1
-ua_lvds_rx/para_data[34] ua_lvds_rx/ramread0_syn_116.c[1]
+Endpoint: ua_lvds_rx/ramread0_syn_102
+1155 0.167000 2 2
+Timing path: ua_lvds_rx/reg3_syn_181.clk->ua_lvds_rx/ramread0_syn_102
+ua_lvds_rx/reg3_syn_181.clk
+ua_lvds_rx/ramread0_syn_102
+1157 0.167000 2.187000 2.354000 1 1
+ua_lvds_rx/para_data[24] ua_lvds_rx/ramread0_syn_102.a[1]
 
-Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_116
+Timing path: ua_lvds_rx/reg16_syn_31.clk->ua_lvds_rx/ramread0_syn_102
 ua_lvds_rx/reg16_syn_31.clk
-ua_lvds_rx/ramread0_syn_116
-1269 0.345000 2.187000 2.532000 1 1
-ua_lvds_rx/wcnt[2] ua_lvds_rx/ramread0_syn_116.c[0]
-
-
-Endpoint: ua_lvds_rx/ramread0_syn_116
-1303 0.167000 2 2
-Timing path: ua_lvds_rx/reg3_syn_195.clk->ua_lvds_rx/ramread0_syn_116
-ua_lvds_rx/reg3_syn_195.clk
-ua_lvds_rx/ramread0_syn_116
-1305 0.167000 2.187000 2.354000 1 1
-ua_lvds_rx/para_data[32] ua_lvds_rx/ramread0_syn_116.a[1]
-
-Timing path: ua_lvds_rx/reg16_syn_33.clk->ua_lvds_rx/ramread0_syn_116
-ua_lvds_rx/reg16_syn_33.clk
-ua_lvds_rx/ramread0_syn_116
-1339 0.586000 2.187000 2.773000 1 1
-ua_lvds_rx/wcnt[0] ua_lvds_rx/ramread0_syn_116.a[0]
+ua_lvds_rx/ramread0_syn_102
+1191 0.412000 2.187000 2.599000 1 1
+ua_lvds_rx/wcnt[0] ua_lvds_rx/ramread0_syn_102.a[0]
 
 
 
 
 clock: b_lvds_clk_p
-1375 0 0 0
+1227 0 0 0
 
 clock: b_pclk
-1383 101266 5874 2
+1235 101792 5792 2
 Setup check
-1393 3
+1245 3
 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
-1393 10.740000 70 3
+1245 10.320000 139 3
 Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
-1395 10.740000 22.857000 12.117000 6 9
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+1247 10.320000 22.857000 12.537000 6 8
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1]
+
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
+1299 10.320000 22.857000 12.537000 6 8
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0]
 
 Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
-1449 10.763000 22.857000 12.094000 6 7
+1351 10.553000 22.857000 12.304000 6 7
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0]
-
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25
-1499 10.810000 22.857000 12.047000 6 6
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[10] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_25.a[1]
 
 
 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1547 10.755000 171 3
+1401 10.320000 171 3
 Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1549 10.755000 22.857000 12.102000 6 9
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+1403 10.320000 22.857000 12.537000 6 8
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1]
 
 Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1603 10.755000 22.857000 12.102000 6 9
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_76.a[1]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_45 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.fci
+1455 10.320000 22.857000 12.537000 6 8
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[5] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_79.a[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_47 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[0]
 
 Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/mult0_syn_4.clk
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21
-1657 10.778000 22.857000 12.079000 6 7
+1507 10.553000 22.857000 12.304000 6 7
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[7] sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_82.a[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_49 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_85.fci
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_51 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b6[4]_syn_88.fci
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg50_syn_201.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg3_syn_167.a[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_pixel_cdc/u_clka_mipi_total_num/reg1_syn_449.b[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE_b5[12] u_bus_top/u_local_bus_slve_cis/reg49_syn_201.a[0]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1232 u_bus_top/reg14_syn_213.a[1]
+sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1236 u_bus_top/reg14_syn_210.b[0]
 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/ADC_STATE[0]_syn_1242 sampling_fe_b/u_sort/u_data_prebuffer_rev/fifo_adc/reg0_syn_21.a[1]
 
 
-Endpoint: exdev_ctl_b/u_gen_sp/reg0_syn_77
-1707 12.253000 214 3
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_78.clk->exdev_ctl_b/u_gen_sp/reg0_syn_77
-exdev_ctl_b/u_gen_sp/reg9_syn_78.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_77
-1709 12.253000 22.858000 10.605000 7 8
-exdev_ctl_b/u_gen_sp/sp_t_d1[7] exdev_ctl_b/u_gen_sp/sub1_syn_104.a[0]
-exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_138 exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_140 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_148 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_77.sr
-
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_92.clk->exdev_ctl_b/u_gen_sp/reg0_syn_77
-exdev_ctl_b/u_gen_sp/reg9_syn_92.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_77
-1761 12.379000 22.858000 10.479000 7 10
-exdev_ctl_b/u_gen_sp/sp_t_d1[1] exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1]
-exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci
-exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
-exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_138 exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_140 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_148 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_77.sr
-
-Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_90.clk->exdev_ctl_b/u_gen_sp/reg0_syn_77
-exdev_ctl_b/u_gen_sp/reg9_syn_90.clk
-exdev_ctl_b/u_gen_sp/reg0_syn_77
-1817 12.427000 22.858000 10.431000 7 10
+Endpoint: exdev_ctl_b/u_gen_sp/reg0_syn_89
+1557 12.376000 214 3
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_73.clk->exdev_ctl_b/u_gen_sp/reg0_syn_89
+exdev_ctl_b/u_gen_sp/reg9_syn_73.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_89
+1559 12.376000 22.858000 10.482000 8 11
 exdev_ctl_b/u_gen_sp/sp_t_d1[0] exdev_ctl_b/u_gen_sp/sub1_syn_102.b[0]
 exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci
 exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
 exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
-exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] u_pixel_cdc/u_clkb_mipi_total_num/reg1_syn_415.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_138 exdev_ctl_b/u_gen_sp/reg9_syn_69.a[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_140 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_464.a[1]
-exdev_ctl_b/u_gen_sp/mux31_syn_148 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_456.a[1]
-exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 u_pixel_cdc/u_clkb_cis_total_num/reg1_syn_517.c[0]
-exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_77.sr
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_135 sampling_fe_b/reg1_syn_48.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_b/reg1_syn_51.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_143 sampling_fe_b/reg2_syn_46.a[1]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 sampling_fe_b/reg2_syn_46.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_89.sr
+
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_77.clk->exdev_ctl_b/u_gen_sp/reg0_syn_89
+exdev_ctl_b/u_gen_sp/reg9_syn_77.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_89
+1617 12.465000 22.858000 10.393000 8 11
+exdev_ctl_b/u_gen_sp/sp_t_d1[1] exdev_ctl_b/u_gen_sp/sub1_syn_102.a[1]
+exdev_ctl_b/u_gen_sp/sub1_syn_87 exdev_ctl_b/u_gen_sp/sub1_syn_103.fci
+exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
+exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_135 sampling_fe_b/reg1_syn_48.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_b/reg1_syn_51.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_143 sampling_fe_b/reg2_syn_46.a[1]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 sampling_fe_b/reg2_syn_46.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_89.sr
+
+Timing path: exdev_ctl_b/u_gen_sp/reg9_syn_97.clk->exdev_ctl_b/u_gen_sp/reg0_syn_89
+exdev_ctl_b/u_gen_sp/reg9_syn_97.clk
+exdev_ctl_b/u_gen_sp/reg0_syn_89
+1675 12.546000 22.858000 10.312000 8 10
+exdev_ctl_b/u_gen_sp/sp_t_d1[3] exdev_ctl_b/u_gen_sp/sub1_syn_103.a[0]
+exdev_ctl_b/u_gen_sp/sub1_syn_91 exdev_ctl_b/u_gen_sp/sub1_syn_104.fci
+exdev_ctl_b/u_gen_sp/sub1_syn_95 exdev_ctl_b/u_gen_sp/sub1_syn_105.fci
+exdev_ctl_b/u_gen_sp/cnt_one_line_b5[12] exdev_ctl_b/u_gen_sp/reg9_syn_80.a[0]
+exdev_ctl_b/u_gen_sp/mux31_syn_135 sampling_fe_b/reg1_syn_48.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_141 sampling_fe_b/reg1_syn_51.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_143 sampling_fe_b/reg2_syn_46.a[1]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n1 sampling_fe_b/reg2_syn_46.a[0]
+exdev_ctl_b/u_gen_sp/cnt_one_line_b3_n_syn_2 sampling_fe_b/u_ad_sampling/reg2_syn_56.a[1]
+exdev_ctl_b/u_gen_sp/mux31_syn_19 exdev_ctl_b/u_gen_sp/reg0_syn_89.sr
 
 
 
 Hold check
-1873 3
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
-1875 0.114000 10 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
-1877 0.114000 2.183000 2.297000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[39] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[12]
+1731 3
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
+1733 0.130000 10 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
+1735 0.130000 2.183000 2.313000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[28] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[11]
 
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_721.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
-1915 0.114000 2.183000 2.297000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[38] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[11]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_633.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
+1773 0.195000 2.183000 2.378000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[20] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[3]
 
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_719.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1
-1953 0.195000 2.183000 2.378000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[30] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.addra[3]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_636.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1
+1811 0.248000 2.183000 2.431000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_addr[23] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.addra[6]
 
 
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
-1991 0.147000 8 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_624.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
-1993 0.147000 2.183000 2.330000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[12] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[4]
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1
+1849 0.130000 8 3
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_518.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1
+1851 0.130000 2.183000 2.313000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[19] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[3]
 
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
-2031 0.186000 2.183000 2.369000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[15] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[7]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_693.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1
+1889 0.232000 2.183000 2.415000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[20] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[4]
 
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_606.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1
-2069 0.186000 2.183000 2.369000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[13] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.dia[5]
+Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg5_syn_673.clk
+sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1
+1927 0.236000 2.183000 2.419000 1 1
+sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[21] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.dia[5]
 
 
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-2107 0.186000 8 3
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_582.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-2109 0.186000 2.183000 2.369000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[47] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[7]
-
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_574.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-2147 0.311000 2.183000 2.494000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[41] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[1]
-
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/insert/reg7_syn_525.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1
-2185 0.411000 2.183000 2.594000 1 1
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_data[45] sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.dia[5]
+Endpoint: exdev_ctl_b/reg3_syn_190
+1965 0.167000 1 1
+Timing path: u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk->exdev_ctl_b/reg3_syn_190
+u_bus_top/u_local_bus_slve_cis/reg42_syn_205.clk
+exdev_ctl_b/reg3_syn_190
+1967 0.167000 2.191000 2.358000 0 1
+u_bus_top/u_local_bus_slve_cis/reg21[2] exdev_ctl_b/reg3_syn_190.mi[1]
 
 
 
 
 clock: b_sclk
-2223 706 282 2
+2003 714 282 2
 Setup check
-2233 3
+2013 3
+Endpoint: ub_lvds_rx/reg3_syn_179
+2013 3.872000 5 3
+Timing path: ub_lvds_rx/reg8_syn_219.clk->ub_lvds_rx/reg3_syn_179
+ub_lvds_rx/reg8_syn_219.clk
+ub_lvds_rx/reg3_syn_179
+2015 3.872000 8.048000 4.176000 1 1
+ub_lvds_rx/rx_data[26] ub_lvds_rx/reg3_syn_179.b[0]
+
+Timing path: ub_lvds_rx/reg8_syn_163.clk->ub_lvds_rx/reg3_syn_179
+ub_lvds_rx/reg8_syn_163.clk
+ub_lvds_rx/reg3_syn_179
+2049 4.385000 8.048000 3.663000 1 1
+ub_lvds_rx/rx_data[27] ub_lvds_rx/reg3_syn_179.c[0]
+
+Timing path: ub_lvds_rx/reg8_syn_197.clk->ub_lvds_rx/reg3_syn_179
+ub_lvds_rx/reg8_syn_197.clk
+ub_lvds_rx/reg3_syn_179
+2083 4.636000 8.048000 3.412000 1 1
+ub_lvds_rx/sync0 ub_lvds_rx/reg3_syn_179.d[0]
+
+
+Endpoint: ub_lvds_rx/reg3_syn_195
+2117 4.034000 5 3
+Timing path: ub_lvds_rx/reg8_syn_197.clk->ub_lvds_rx/reg3_syn_195
+ub_lvds_rx/reg8_syn_197.clk
+ub_lvds_rx/reg3_syn_195
+2119 4.034000 8.048000 4.014000 1 1
+ub_lvds_rx/rx_data[24] ub_lvds_rx/reg3_syn_195.b[0]
+
+Timing path: ub_lvds_rx/reg8_syn_197.clk->ub_lvds_rx/reg3_syn_195
+ub_lvds_rx/reg8_syn_197.clk
+ub_lvds_rx/reg3_syn_195
+2153 4.636000 8.048000 3.412000 1 1
+ub_lvds_rx/sync0 ub_lvds_rx/reg3_syn_195.d[0]
+
+Timing path: ub_lvds_rx/reg8_syn_219.clk->ub_lvds_rx/reg3_syn_195
+ub_lvds_rx/reg8_syn_219.clk
+ub_lvds_rx/reg3_syn_195
+2187 4.678000 8.048000 3.370000 1 1
+ub_lvds_rx/rx_data[25] ub_lvds_rx/reg3_syn_195.c[0]
+
+
 Endpoint: ub_lvds_rx/rx_clk_sync_reg_syn_5
-2233 3.794000 7 3
-Timing path: ub_lvds_rx/reg7_syn_33.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_33.clk
+2221 4.071000 7 3
+Timing path: ub_lvds_rx/reg7_syn_34.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_34.clk
 ub_lvds_rx/rx_clk_sync_reg_syn_5
-2235 3.794000 8.076000 4.282000 2 2
-ub_lvds_rx/rx_clk_sft[1] ub_lvds_rx/rx_clk_sync_reg_syn_5.b[0]
+2223 4.071000 8.048000 3.977000 2 2
+ub_lvds_rx/rx_clk_sft[0] ub_lvds_rx/rx_clk_sync_reg_syn_5.a[0]
 ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
 
-Timing path: ub_lvds_rx/reg7_syn_25.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_25.clk
+Timing path: ub_lvds_rx/reg7_syn_28.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_28.clk
 ub_lvds_rx/rx_clk_sync_reg_syn_5
-2271 4.018000 8.076000 4.058000 2 2
-ub_lvds_rx/rx_clk_sft[2] ub_lvds_rx/rx_clk_sync_reg_syn_5.c[0]
-ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
+2259 4.371000 8.048000 3.677000 1 1
+ub_lvds_rx/rx_clk_sft[5] ub_lvds_rx/rx_clk_sync_reg_syn_5.b[1]
 
-Timing path: ub_lvds_rx/reg7_syn_25.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
-ub_lvds_rx/reg7_syn_25.clk
+Timing path: ub_lvds_rx/reg7_syn_28.clk->ub_lvds_rx/rx_clk_sync_reg_syn_5
+ub_lvds_rx/reg7_syn_28.clk
 ub_lvds_rx/rx_clk_sync_reg_syn_5
-2307 4.087000 8.076000 3.989000 2 2
+2293 4.382000 8.048000 3.666000 2 2
 ub_lvds_rx/rx_clk_sft[4] ub_lvds_rx/rx_clk_sync_reg_syn_5.e[0]
 ub_lvds_rx/rx_clk_sync_n_syn_2 ub_lvds_rx/rx_clk_sync_reg_syn_5.d[1]
 
 
-Endpoint: ub_lvds_rx/reg16_syn_31
-2343 4.143000 4 3
-Timing path: ub_lvds_rx/para_en_reg_syn_5.clk->ub_lvds_rx/reg16_syn_31
-ub_lvds_rx/para_en_reg_syn_5.clk
-ub_lvds_rx/reg16_syn_31
-2345 4.143000 8.091000 3.948000 1 1
-ub_lvds_rx/para_en ub_lvds_rx/reg16_syn_31.a[0]
-
-Timing path: ub_lvds_rx/reg16_syn_33.clk->ub_lvds_rx/reg16_syn_31
-ub_lvds_rx/reg16_syn_33.clk
-ub_lvds_rx/reg16_syn_31
-2379 4.403000 8.091000 3.688000 1 1
-ub_lvds_rx/wcnt[0] ub_lvds_rx/reg16_syn_31.b[0]
-
-Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/reg16_syn_31
-ub_lvds_rx/reg16_syn_31.clk
-ub_lvds_rx/reg16_syn_31
-2413 4.442000 8.091000 3.649000 1 1
-ub_lvds_rx/wcnt[1] ub_lvds_rx/reg16_syn_31.c[0]
-
-
-Endpoint: ub_lvds_rx/reg8_syn_147
-2447 4.145000 9 3
-Timing path: ub_lvds_rx/reg8_syn_147.clk->ub_lvds_rx/reg8_syn_147
-ub_lvds_rx/reg8_syn_147.clk
-ub_lvds_rx/reg8_syn_147
-2449 4.145000 8.112000 3.967000 1 1
-ub_lvds_rx/para_data[11] ub_lvds_rx/reg8_syn_147.a[1]
-
-Timing path: ub_lvds_rx/reg12_syn_17.clk->ub_lvds_rx/reg8_syn_147
-ub_lvds_rx/reg12_syn_17.clk
-ub_lvds_rx/reg8_syn_147
-2483 4.294000 8.112000 3.818000 1 1
-ub_lvds_rx/sync0 ub_lvds_rx/reg8_syn_147.d[1]
-
-Timing path: ub_lvds_rx/reg12_syn_17.clk->ub_lvds_rx/reg8_syn_147
-ub_lvds_rx/reg12_syn_17.clk
-ub_lvds_rx/reg8_syn_147
-2517 4.294000 8.112000 3.818000 1 1
-ub_lvds_rx/sync0 ub_lvds_rx/reg8_syn_147.d[0]
-
-
 
 Hold check
-2551 3
+2329 3
 Endpoint: ub_lvds_rx/ramread0_syn_102
-2553 0.167000 2 2
-Timing path: ub_lvds_rx/reg8_syn_161.clk->ub_lvds_rx/ramread0_syn_102
-ub_lvds_rx/reg8_syn_161.clk
+2331 0.167000 2 2
+Timing path: ub_lvds_rx/reg3_syn_182.clk->ub_lvds_rx/ramread0_syn_102
+ub_lvds_rx/reg3_syn_182.clk
 ub_lvds_rx/ramread0_syn_102
-2555 0.167000 2.096000 2.263000 1 1
+2333 0.167000 2.096000 2.263000 1 1
 ub_lvds_rx/para_data[26] ub_lvds_rx/ramread0_syn_102.c[1]
 
 Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_102
 ub_lvds_rx/reg16_syn_31.clk
 ub_lvds_rx/ramread0_syn_102
-2589 0.345000 2.096000 2.441000 1 1
+2367 0.548000 2.096000 2.644000 1 1
 ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_102.c[0]
 
 
-Endpoint: ub_lvds_rx/ramread0_syn_18
-2623 0.167000 2 2
-Timing path: ub_lvds_rx/reg3_syn_163.clk->ub_lvds_rx/ramread0_syn_18
-ub_lvds_rx/reg3_syn_163.clk
-ub_lvds_rx/ramread0_syn_18
-2625 0.167000 2.096000 2.263000 1 1
-ub_lvds_rx/para_data[2] ub_lvds_rx/ramread0_syn_18.c[1]
+Endpoint: ub_lvds_rx/ramread0_syn_74
+2401 0.167000 2 2
+Timing path: ub_lvds_rx/reg3_syn_174.clk->ub_lvds_rx/ramread0_syn_74
+ub_lvds_rx/reg3_syn_174.clk
+ub_lvds_rx/ramread0_syn_74
+2403 0.167000 2.096000 2.263000 1 1
+ub_lvds_rx/para_data[16] ub_lvds_rx/ramread0_syn_74.a[1]
 
-Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_18
+Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_74
 ub_lvds_rx/reg16_syn_31.clk
-ub_lvds_rx/ramread0_syn_18
-2659 0.199000 2.096000 2.295000 1 1
-ub_lvds_rx/wcnt[2] ub_lvds_rx/ramread0_syn_18.c[0]
+ub_lvds_rx/ramread0_syn_74
+2437 0.207000 2.096000 2.303000 1 1
+ub_lvds_rx/wcnt[0] ub_lvds_rx/ramread0_syn_74.a[0]
 
 
-Endpoint: ub_lvds_rx/ramread0_syn_102
-2693 0.176000 1 1
-Timing path: ub_lvds_rx/reg3_syn_185.clk->ub_lvds_rx/ramread0_syn_102
-ub_lvds_rx/reg3_syn_185.clk
-ub_lvds_rx/ramread0_syn_102
-2695 0.176000 2.096000 2.272000 1 1
-ub_lvds_rx/para_data[27] ub_lvds_rx/ramread0_syn_102.d[1]
+Endpoint: ub_lvds_rx/ramread0_syn_60
+2471 0.167000 2 2
+Timing path: ub_lvds_rx/reg3_syn_190.clk->ub_lvds_rx/ramread0_syn_60
+ub_lvds_rx/reg3_syn_190.clk
+ub_lvds_rx/ramread0_syn_60
+2473 0.167000 2.096000 2.263000 1 1
+ub_lvds_rx/para_data[12] ub_lvds_rx/ramread0_syn_60.a[1]
+
+Timing path: ub_lvds_rx/reg16_syn_31.clk->ub_lvds_rx/ramread0_syn_60
+ub_lvds_rx/reg16_syn_31.clk
+ub_lvds_rx/ramread0_syn_60
+2507 0.324000 2.096000 2.420000 1 1
+ub_lvds_rx/wcnt[0] ub_lvds_rx/ramread0_syn_60.a[0]
 
 
 
 
 clock: clock_source
-2731 0 0 0
+2543 0 0 0
 
 clock: S_clk
-2739 107786 8640 5
+2551 109052 8560 5
 Setup check
-2749 3
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86
-2749 0.208000 1 1
-Timing path: sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86
-sampling_fe_b/u_sort/u_data_prebuffer_rev/reg3_syn_28.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86
-2751 0.208000 4.317000 4.109000 1 2
-sampling_fe_b/u_sort/u_data_prebuffer_rev/raw_switch[0] sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_49.b[0]
-sampling_fe_b/u_sort/u_data_prebuffer_rev/reg5_syn_13 sampling_fe_b/u_sort/u_data_prebuffer_rev/read_ram_i/read_ram_addr/add9_syn_86.mi[0]
-
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
-2791 0.279000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
+2561 3
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56
+2561 0.027000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56
 sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
-2793 0.279000 4.317000 4.038000 1 2
-sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[0]
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56
+2563 0.027000 4.317000 4.290000 1 2
+sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/reg4_syn_56.mi[0]
 
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
-2833 0.279000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
+Endpoint: U_rgb_to_csi_pakage/reg14_syn_101_syn_2
+2603 0.027000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->U_rgb_to_csi_pakage/reg14_syn_101_syn_2
 sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2
-2835 0.279000 4.317000 4.038000 1 2
-sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_transfer_300_to_200/data_f_b4_n87_syn_28.b[0]
-sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_58_syn_2.mi[1]
+U_rgb_to_csi_pakage/reg14_syn_101_syn_2
+2605 0.027000 4.317000 4.290000 1 2
+sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 U_rgb_to_csi_pakage/reg14_syn_101_syn_2.mi[0]
+
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81
+2645 0.027000 1 1
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk->sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81
+sampling_fe_a/u_sort/u_data_prebuffer/reg3_syn_28.clk
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81
+2647 0.027000 4.317000 4.290000 1 2
+sampling_fe_a/u_sort/u_data_prebuffer/raw_switch[0] sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_71.b[0]
+sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_13 sampling_fe_a/u_sort/u_data_prebuffer/reg5_syn_81.mi[0]
 
 
 
 Hold check
-2875 3
-Endpoint: u_mipi_eot_min/reg1_syn_275
-2877 0.067000 1 1
-Timing path: u_bus_top/reg18_syn_74.clk->u_mipi_eot_min/reg1_syn_275
-u_bus_top/reg18_syn_74.clk
-u_mipi_eot_min/reg1_syn_275
-2879 0.067000 2.291000 2.358000 0 1
-u_mipi_eot_min/signal_from[1] u_mipi_eot_min/reg1_syn_275.mi[1]
+2687 3
+Endpoint: u_pic_cnt/reg1_syn_385
+2689 0.067000 1 1
+Timing path: reg36_syn_108.clk->u_pic_cnt/reg1_syn_385
+reg36_syn_108.clk
+u_pic_cnt/reg1_syn_385
+2691 0.067000 2.291000 2.358000 0 1
+u_pic_cnt/signal_from[5] u_pic_cnt/reg1_syn_385.mi[0]
 
 
-Endpoint: add0_syn_146
-2915 0.067000 1 1
-Timing path: reg36_syn_118.clk->add0_syn_146
-reg36_syn_118.clk
-add0_syn_146
-2917 0.067000 2.291000 2.358000 0 1
-u_pic_cnt/signal_from[9] add0_syn_146.mi[0]
+Endpoint: u_mipi_eot_min/reg1_syn_289
+2727 0.067000 1 1
+Timing path: u_bus_top/reg18_syn_66.clk->u_mipi_eot_min/reg1_syn_289
+u_bus_top/reg18_syn_66.clk
+u_mipi_eot_min/reg1_syn_289
+2729 0.067000 2.291000 2.358000 0 1
+u_mipi_eot_min/signal_from[0] u_mipi_eot_min/reg1_syn_289.mi[1]
 
 
-Endpoint: u_pic_cnt/reg1_syn_465
-2953 0.067000 1 1
-Timing path: reg36_syn_130.clk->u_pic_cnt/reg1_syn_465
-reg36_syn_130.clk
-u_pic_cnt/reg1_syn_465
-2955 0.067000 2.291000 2.358000 0 1
-u_pic_cnt/signal_from[4] u_pic_cnt/reg1_syn_465.mi[0]
+Endpoint: u_pic_cnt/reg1_syn_436
+2765 0.067000 1 1
+Timing path: reg36_syn_111.clk->u_pic_cnt/reg1_syn_436
+reg36_syn_111.clk
+u_pic_cnt/reg1_syn_436
+2767 0.067000 2.291000 2.358000 0 1
+u_pic_cnt/signal_from[19] u_pic_cnt/reg1_syn_436.mi[1]
 
 
 
 Recovery check
-2991 3
-Endpoint: U_rgb_to_csi_pakage/reg10_syn_53_syn_2
-2993 5.512000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg10_syn_53_syn_2
+2803 3
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275
+2805 5.372000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275
 U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg10_syn_53_syn_2
-2995 5.512000 11.304000 5.792000 1 2
-U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_frame_start_delay_n_edge_1d_reg_syn_6_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/reg10_syn_53_syn_2.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275
+2807 5.372000 11.304000 5.932000 2 3
+U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr
 
-
-Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
-3035 5.735000 2 2
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
-U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
-3037 5.735000 11.304000 5.569000 2 3
-U_rgb_to_csi_pakage/S_global_en reg20_syn_64_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_5 sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.d[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr
-
-Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275
 adj_vsynco_reg_syn_5.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2
-3079 6.339000 11.304000 4.965000 1 2
-U_rgb_to_csi_pakage/I_rgb_vsync sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/reg8_syn_620.c[0]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1109_syn_2.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275
+2849 6.051000 11.304000 5.253000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1275.sr
 
 
-Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
-3119 5.754000 2 2
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2
+2889 5.379000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2
 U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
-3121 5.754000 11.304000 5.550000 2 3
-U_rgb_to_csi_pakage/S_global_en reg20_syn_64_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_5 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.d[1]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2
+2891 5.379000 11.304000 5.925000 2 3
+U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr
 
-Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2
 adj_vsynco_reg_syn_5.clk
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284
-3163 6.319000 11.304000 4.985000 1 2
-U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_34_syn_2.c[1]
-U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_dup_19 U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1284.sr
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2
+2933 6.058000 11.304000 5.246000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1243_syn_2.sr
+
+
+Endpoint: U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2
+2973 5.379000 2 2
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2
+U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2
+2975 5.379000 11.304000 5.925000 2 3
+U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.d[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr
+
+Timing path: adj_vsynco_reg_syn_5.clk->U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2
+adj_vsynco_reg_syn_5.clk
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2
+3017 6.058000 11.304000 5.246000 1 2
+U_rgb_to_csi_pakage/I_rgb_vsync U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst_syn_33_syn_2.c[1]
+U_rgb_to_csi_pakage/U_fifo_w32_d8192/rst U_rgb_to_csi_pakage/U_fifo_w32_d8192/logic_ramfifo_syn_1233_syn_2.sr
 
 
 
 Removal check
-3203 3
+3057 3
+Endpoint: U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2
+3059 0.697000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2
+U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
+U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2
+3061 0.697000 2.327000 3.024000 1 2
+U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n U_rgb_to_csi_pakage/U_crc16_24b/reg0_syn_71_syn_2.sr
+
+
+Endpoint: U_rgb_to_csi_pakage/reg2_syn_151_syn_2
+3101 0.727000 1 1
+Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg2_syn_151_syn_2
+U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
+U_rgb_to_csi_pakage/reg2_syn_151_syn_2
+3103 0.727000 2.327000 3.054000 1 2
+U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/reg16_syn_103_syn_2.d[1]
+U_rgb_to_csi_pakage/S_rst_n_dup_3 U_rgb_to_csi_pakage/reg2_syn_151_syn_2.sr
+
+
 Endpoint: U_rgb_to_csi_pakage/reg12_syn_73_syn_2
-3205 0.685000 1 1
+3143 0.767000 1 1
 Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg12_syn_73_syn_2
 U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
 U_rgb_to_csi_pakage/reg12_syn_73_syn_2
-3207 0.685000 2.311000 2.996000 1 2
-U_rgb_to_csi_pakage/S_global_en reg20_syn_54_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr
-
-
-Endpoint: U_rgb_to_csi_pakage/reg12_syn_69_syn_2
-3247 0.685000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg12_syn_69_syn_2
-U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg12_syn_69_syn_2
-3249 0.685000 2.311000 2.996000 1 2
-U_rgb_to_csi_pakage/S_global_en reg20_syn_54_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg12_syn_69_syn_2.sr
-
-
-Endpoint: U_rgb_to_csi_pakage/reg7_syn_151_syn_2
-3289 0.781000 1 1
-Timing path: U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk->U_rgb_to_csi_pakage/reg7_syn_151_syn_2
-U_rgb_to_csi_pakage/S_global_en_reg_syn_9.clk
-U_rgb_to_csi_pakage/reg7_syn_151_syn_2
-3291 0.781000 2.327000 3.108000 1 2
-U_rgb_to_csi_pakage/S_global_en reg20_syn_54_syn_2.d[0]
-U_rgb_to_csi_pakage/S_rst_n_dup_2 U_rgb_to_csi_pakage/reg7_syn_151_syn_2.sr
+3145 0.767000 2.327000 3.094000 1 2
+U_rgb_to_csi_pakage/S_global_en U_rgb_to_csi_pakage/S_rgb_vsync_2d_reg_syn_6_syn_2.d[0]
+U_rgb_to_csi_pakage/S_rst_n_dup_1 U_rgb_to_csi_pakage/reg12_syn_73_syn_2.sr
 
 
 
 Period check
-3331 48
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst_syn_1.clkb
-3335 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clkb
-3336 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb
-3337 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb
-3338 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb
-3339 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb
-3340 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb
-3341 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb
-3342 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb
-3343 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb
-3344 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb
-3345 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb
-3346 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb
-3347 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb
-3348 5.858000 1 0
-
+3185 48
 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_8/inst_syn_1.clkb
-3349 5.858000 1 0
+3189 5.858000 1 0
 
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb
-3350 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb
-3351 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb
-3352 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb
-3353 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb
-3354 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb
-3355 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb
-3356 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_7/inst_syn_1.clkb
+3190 5.858000 1 0
 
 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_6/inst_syn_1.clkb
-3357 5.858000 1 0
+3191 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_5/inst_syn_1.clkb
+3192 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_3/inst_syn_1.clkb
+3193 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_10/inst_syn_1.clkb
+3194 5.858000 1 0
 
 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_1/inst_syn_1.clkb
-3358 5.858000 1 0
+3195 5.858000 1 0
 
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb
-3359 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_9/inst_syn_1.clkb
+3196 5.858000 1 0
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb
-3360 5.858000 1 0
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb
-3361 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb
-3362 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb
-3363 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
-3364 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_9/inst_syn_1.clkb
+3197 5.858000 1 0
 
 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_7/inst_syn_1.clkb
-3365 5.858000 1 0
+3198 5.858000 1 0
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb
-3366 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb
-3367 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_6/inst_syn_1.clkb
+3199 5.858000 1 0
 
 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_7/inst_syn_1.clkb
-3368 5.858000 1 0
+3200 5.858000 1 0
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb
-3369 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_3/inst_syn_1.clkb
+3201 5.858000 1 0
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb
-3370 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_10/inst_syn_1.clkb
+3202 5.858000 1 0
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb
-3371 5.858000 1 0
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_9/inst_syn_1.clkb
+3203 5.858000 1 0
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb
-3372 5.858000 1 0
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_8/inst_syn_1.clkb
+3204 5.858000 1 0
 
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb
-3373 5.858000 1 0
-
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
-3374 5.858000 1 0
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_8/inst_syn_1.clkb
+3205 5.858000 1 0
 
 Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_1/inst_syn_1.clkb
-3375 5.858000 1 0
+3206 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_7/inst_syn_1.clkb
+3207 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_5/inst_syn_1.clkb
+3208 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_6/inst_syn_1.clkb
+3209 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_5/inst_syn_1.clkb
+3210 5.858000 1 0
 
 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_10/inst_syn_1.clkb
-3376 5.858000 1 0
+3211 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_0/inst_syn_1.clkb
+3212 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_2/inst_syn_1.clkb
+3213 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_4/inst_syn_1.clkb
+3214 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_4/inst_syn_1.clkb
+3215 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_3/inst_syn_1.clkb
+3216 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_b_0/inst_syn_1.clkb
+3217 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_2/inst_syn_1.clkb
+3218 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_1/inst_syn_1.clkb
+3219 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_4/inst_syn_1.clkb
+3220 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_0/inst_syn_1.clkb
+3221 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_9/inst_syn_1.clkb
+3222 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_8/inst_syn_1.clkb
+3223 5.858000 1 0
+
+Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/u0_sort_ram_a_2/inst_syn_1.clkb
+3224 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_6/inst_syn_1.clkb
+3225 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_5/inst_syn_1.clkb
+3226 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_b_10/inst_syn_1.clkb
+3227 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_4/inst_syn_1.clkb
+3228 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_3/inst_syn_1.clkb
+3229 5.858000 1 0
+
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_2/inst_syn_1.clkb
+3230 5.858000 1 0
 
 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_1/inst_syn_1.clkb
-3377 5.858000 1 0
+3231 5.858000 1 0
 
 Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/u0_sort_ram_a_0/inst_syn_1.clkb
-3378 5.858000 1 0
-
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3379 5.958000 1 0
+3232 5.858000 1 0
 
 Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3380 5.958000 1 0
+3233 5.958000 1 0
 
 Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3381 5.958000 1 0
+3234 5.958000 1 0
 
 Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
-3382 5.958000 1 0
+3235 5.958000 1 0
+
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/u_dphy_tx_fifo/u_d1024_w8_fifo/fifo_inst_syn_8.clkw
+3236 5.958000 1 0
 
 
 
 clock: clk_adc
-3383 43224 4240 4
+3237 46330 5330 4
 Setup check
-3393 3
-Endpoint: reg40_syn_12
-3393 -1.945000 2 2
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk->reg40_syn_12
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add18_syn_70.clk
-reg40_syn_12
-3395 -1.945000 1.949000 3.894000 1 2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_01_en_2d reg29_syn_13.d[0]
-O_clk_lp_n_dup_1 reg40_syn_12.mi[1]
-
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk->reg40_syn_12
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk
-reg40_syn_12
-3431 -1.844000 1.949000 3.793000 1 2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg29_syn_13.c[0]
-O_clk_lp_n_dup_1 reg40_syn_12.mi[1]
+3247 3
+Endpoint: u_bus_top/reg12_syn_135
+3247 7.414000 1 1
+Timing path: reg26_syn_196.clk->u_bus_top/reg12_syn_135
+reg26_syn_196.clk
+u_bus_top/reg12_syn_135
+3249 7.414000 11.187000 3.773000 0 1
+lv_cnt_a[0] u_bus_top/reg12_syn_135.mi[1]
 
 
-Endpoint: reg40_syn_12
-3467 -1.334000 1 1
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk->reg40_syn_12
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add1_syn_69.clk
-reg40_syn_12
-3469 -1.334000 1.949000 3.283000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_lp_generate/S_lp_11_en_2d reg40_syn_12.mi[0]
+Endpoint: u_bus_top/reg6_syn_118
+3285 7.493000 1 1
+Timing path: reg24_syn_80.clk->u_bus_top/reg6_syn_118
+reg24_syn_80.clk
+u_bus_top/reg6_syn_118
+3287 7.493000 11.187000 3.694000 0 1
+frame_cnt[10] u_bus_top/reg6_syn_118.mi[0]
 
 
-Endpoint: u_bus_top/reg15_syn_166
-3503 7.526000 1 1
-Timing path: reg27_syn_214.clk->u_bus_top/reg15_syn_166
-reg27_syn_214.clk
-u_bus_top/reg15_syn_166
-3505 7.526000 11.187000 3.661000 0 1
-lv_cnt_b[12] u_bus_top/reg15_syn_166.mi[1]
+Endpoint: u_bus_top/reg0_syn_143_syn_2
+3323 7.607000 1 1
+Timing path: reg1_syn_154.clk->u_bus_top/reg0_syn_143_syn_2
+reg1_syn_154.clk
+u_bus_top/reg0_syn_143_syn_2
+3325 7.607000 11.187000 3.580000 0 1
+S_hs_data_reg[11] u_bus_top/reg0_syn_143_syn_2.mi[1]
 
 
 
 Hold check
-3541 3
-Endpoint: u_bus_top/reg9_syn_165
-3543 0.258000 1 1
-Timing path: reg25_syn_115.clk->u_bus_top/reg9_syn_165
-reg25_syn_115.clk
-u_bus_top/reg9_syn_165
-3545 0.258000 2.191000 2.449000 0 1
-lv_cnt2bus[6] u_bus_top/reg9_syn_165.mi[1]
+3361 3
+Endpoint: add9_syn_98
+3363 0.258000 1 1
+Timing path: reg24_syn_89.clk->add9_syn_98
+reg24_syn_89.clk
+add9_syn_98
+3365 0.258000 2.191000 2.449000 0 1
+frame_cnt[2] add9_syn_98.mi[0]
 
 
-Endpoint: u_bus_top/reg9_syn_165
-3581 0.258000 1 1
-Timing path: reg25_syn_127.clk->u_bus_top/reg9_syn_165
-reg25_syn_127.clk
-u_bus_top/reg9_syn_165
-3583 0.258000 2.191000 2.449000 0 1
-lv_cnt2bus[8] u_bus_top/reg9_syn_165.mi[0]
+Endpoint: u_bus_top/reg0_syn_151_syn_2
+3401 0.258000 1 1
+Timing path: reg1_syn_142.clk->u_bus_top/reg0_syn_151_syn_2
+reg1_syn_142.clk
+u_bus_top/reg0_syn_151_syn_2
+3403 0.258000 2.191000 2.449000 0 1
+S_hs_data_reg[14] u_bus_top/reg0_syn_151_syn_2.mi[0]
 
 
-Endpoint: u_bus_top/reg9_syn_152
-3619 0.258000 1 1
-Timing path: reg25_syn_133.clk->u_bus_top/reg9_syn_152
-reg25_syn_133.clk
-u_bus_top/reg9_syn_152
-3621 0.258000 2.191000 2.449000 0 1
-lv_cnt2bus[3] u_bus_top/reg9_syn_152.mi[1]
+Endpoint: exdev_ctl_b/reg2_syn_213
+3439 0.260000 1 1
+Timing path: exdev_ctl_b/reg1_syn_176.clk->exdev_ctl_b/reg2_syn_213
+exdev_ctl_b/reg1_syn_176.clk
+exdev_ctl_b/reg2_syn_213
+3441 0.260000 2.107000 2.367000 0 1
+exdev_ctl_b/adc_cfg_dat_d1[27] exdev_ctl_b/reg2_syn_213.mi[0]
 
 
 
 Recovery check
-3657 3
-Endpoint: scan_start_diff/reg2_syn_21
-3659 161.807000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_21
-clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg2_syn_21
-3661 161.807000 168.504000 6.697000 1 2
-u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_21.sr
-
-
-Endpoint: sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20
-3697 161.807000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20
-clkubus_rstn_reg_syn_8.clk
-sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20
-3699 161.807000 168.504000 6.697000 1 2
-u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_9 sampling_fe_b/u_sort/u_data_prebuffer_rev/ram_switch/ram_switch_state/ram_data_tmp[53]_syn_20.sr
-
-
-Endpoint: scan_start_diff/reg2_syn_19
-3735 161.970000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_19
-clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg2_syn_19
-3737 161.970000 168.504000 6.534000 1 2
-u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_19.sr
-
-
-
-Removal check
-3773 3
-Endpoint: scan_start_diff/a_ex_frame_reg_syn_5
-3775 2.526000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_reg_syn_5
-clkubus_rstn_reg_syn_8.clk
-scan_start_diff/a_ex_frame_reg_syn_5
-3777 2.526000 2.299000 4.825000 1 2
-u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_ex_frame_reg_syn_5.sr
-
-
+3475 3
 Endpoint: scan_start_diff/a_ex_frame_en_reg_syn_5
-3813 2.537000 1 1
+3477 163.478000 1 1
 Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_en_reg_syn_5
 clkubus_rstn_reg_syn_8.clk
 scan_start_diff/a_ex_frame_en_reg_syn_5
-3815 2.537000 2.299000 4.836000 1 2
+3479 163.478000 168.576000 5.098000 1 2
 u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
 BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_ex_frame_en_reg_syn_5.sr
 
 
-Endpoint: scan_start_diff/reg2_syn_19
-3851 2.627000 1 1
-Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_19
+Endpoint: scan_start_diff/a_ex_frame_reg_syn_5
+3515 163.665000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_ex_frame_reg_syn_5
 clkubus_rstn_reg_syn_8.clk
-scan_start_diff/reg2_syn_19
-3853 2.627000 2.299000 4.926000 1 2
+scan_start_diff/a_ex_frame_reg_syn_5
+3517 163.665000 168.576000 4.911000 1 2
 u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
-BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_19.sr
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_ex_frame_reg_syn_5.sr
+
+
+Endpoint: scan_start_diff/enable_from_arm_rog_reg_syn_5
+3553 163.676000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/enable_from_arm_rog_reg_syn_5
+clkubus_rstn_reg_syn_8.clk
+scan_start_diff/enable_from_arm_rog_reg_syn_5
+3555 163.676000 168.576000 4.900000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/enable_from_arm_rog_reg_syn_5.sr
+
+
+
+Removal check
+3591 3
+Endpoint: scan_start_diff/reg2_syn_20
+3593 1.366000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_20
+clkubus_rstn_reg_syn_8.clk
+scan_start_diff/reg2_syn_20
+3595 1.366000 2.236000 3.602000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_20.sr
+
+
+Endpoint: scan_start_diff/a_frame_pad_rog_reg_syn_5
+3631 1.410000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/a_frame_pad_rog_reg_syn_5
+clkubus_rstn_reg_syn_8.clk
+scan_start_diff/a_frame_pad_rog_reg_syn_5
+3633 1.410000 2.236000 3.646000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/a_frame_pad_rog_reg_syn_5.sr
+
+
+Endpoint: scan_start_diff/reg2_syn_22
+3669 1.433000 1 1
+Timing path: clkubus_rstn_reg_syn_8.clk->scan_start_diff/reg2_syn_22
+clkubus_rstn_reg_syn_8.clk
+scan_start_diff/reg2_syn_22
+3671 1.433000 2.236000 3.669000 1 2
+u_softrst_fan_ctrl/signal_from[0] scan_start_diff/sys_initial_done_d0_reg_syn_8.d[0]
+BUSY_MIPI_sync_d0_i_syn_9 scan_start_diff/reg2_syn_22.sr
 
 
 
 
 clock: S_clk_x2
-3889 146 80 2
+3707 152 86 2
 Setup check
-3899 3
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-3899 2.068000 2 2
-Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add32_syn_70.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-3901 2.068000 6.679000 4.611000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0]
+3717 3
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3717 2.419000 2 2
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3719 2.419000 6.679000 4.260000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1]
 
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_41_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-3937 2.526000 6.679000 4.153000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0]
-
-
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-3973 2.297000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_39_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-3975 2.297000 6.679000 4.382000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[1]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_43_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
-4011 2.367000 6.679000 4.312000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1]
-
-
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-4047 2.443000 2 2
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_47.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-4049 2.443000 6.679000 4.236000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[2] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
-4085 2.532000 6.679000 4.147000 1 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[6] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0]
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3755 2.942000 6.679000 3.737000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[1]
+
+
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+3791 2.457000 2 2
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add28_syn_70.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+3793 2.457000 6.679000 4.222000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[5] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.c[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2
+3829 3.101000 6.679000 3.578000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[1] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.b[0]
+
+
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3865 2.507000 2 2
+Timing path: sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+sampling_fe_a/u_sort/u_data_prebuffer/read_ram_i/read_ram_addr/add7_syn_62.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3867 2.507000 6.679000 4.172000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.b[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg2_syn_37_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2
+3903 2.831000 6.679000 3.848000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs[4] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.c[0]
 
 
 
 Hold check
-4121 3
-Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69
-4123 0.167000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6.clk
-sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69
-4125 0.167000 2.291000 2.458000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add7_syn_69.mi[0]
+3939 3
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69
+3941 0.167000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d_reg_syn_6_syn_2.clk
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69
+3943 0.167000 2.291000 2.458000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_01_en_2d sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add10_syn_69.mi[0]
 
 
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5
-4161 0.281000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5
+Endpoint: sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69
+3979 0.190000 1 1
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk->sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d_reg_syn_6_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5
-4163 0.281000 2.291000 2.572000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_3d_reg_syn_5.mi[0]
+sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69
+3981 0.190000 2.291000 2.481000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_lp_generate/S_lp_11_en_2d sampling_fe_a/u_sort/u_data_prebuffer/ram_switch/insert/add11_syn_69.mi[0]
 
 
-Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5
-4199 0.306000 1 1
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_reg_syn_10_syn_2.clk
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5
-4201 0.306000 2.291000 2.597000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_en_1d_reg_syn_5.mi[0]
+Endpoint: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2
+4017 0.341000 2 2
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2
+4019 0.341000 2.291000 2.632000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_en u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.d[1]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk->u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg1_syn_14_syn_2.clk
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2
+4055 0.490000 2.291000 2.781000 1 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data[0] u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.c[1]
 
 
 
 
 clock: S_clk_x4
-4237 32 8 2
+4091 32 8 2
 Setup check
-4247 3
-Endpoint: O_data_hs_p[0]_syn_2
-4247 0.876000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[0]_syn_2
-4249 0.876000 4.110000 3.234000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[0]_syn_2.do[3]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[0]_syn_2
-4283 0.952000 4.110000 3.158000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[0]_syn_2
-4317 1.028000 4.110000 3.082000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
-
-
+4101 3
 Endpoint: O_data_hs_p[1]_syn_2
-4351 0.925000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[1]_syn_2
-4353 0.925000 4.110000 3.185000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
-
+4101 0.879000 4 3
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
 O_data_hs_p[1]_syn_2
-4387 0.952000 4.110000 3.158000 0 1
+4103 0.879000 4.110000 3.231000 0 1
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3]
 
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
 O_data_hs_p[1]_syn_2
-4421 0.952000 4.110000 3.158000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
-
-
-Endpoint: O_data_hs_p[3]_syn_2
-4455 0.928000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[3]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[3]_syn_2
-4457 0.928000 4.110000 3.182000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[3]_syn_2.do[2]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
-O_data_hs_p[3]_syn_2
-4491 0.952000 4.110000 3.158000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[3]_syn_2
-4525 0.952000 4.110000 3.158000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1]
-
-
-
-Hold check
-4559 3
-Endpoint: O_data_hs_p[0]_syn_2
-4561 0.401000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[0]_syn_2
-4563 0.401000 1.962000 2.363000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[0]_syn_2.do[2]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[0]_syn_2
-4597 0.546000 1.962000 2.508000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[0]_syn_2.do[1]
-
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[0]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
-O_data_hs_p[0]_syn_2
-4631 0.583000 1.962000 2.545000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[0]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[0]_syn_2.do[0]
-
-
-Endpoint: O_data_hs_p[1]_syn_2
-4665 0.401000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[1]_syn_2
-4667 0.401000 1.962000 2.363000 0 1
+4137 0.879000 4.110000 3.231000 0 1
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[1]_syn_2.do[1]
 
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
 O_data_hs_p[1]_syn_2
-4701 0.583000 1.962000 2.545000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3]
+4171 0.923000 4.110000 3.187000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
 
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[1]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
-O_data_hs_p[1]_syn_2
-4735 0.583000 1.962000 2.545000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
+
+Endpoint: O_data_hs_p[2]_syn_2
+4205 0.923000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[2]_syn_2
+4207 0.923000 4.110000 3.187000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[2]_syn_2.do[3]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[2]_syn_2
+4241 0.925000 4.110000 3.185000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[2]_syn_2.do[1]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[2]_syn_2
+4275 1.224000 4.110000 2.886000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[2]_syn_2.do[2]
 
 
 Endpoint: O_data_hs_p[3]_syn_2
-4769 0.401000 4 3
-Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+4309 0.928000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
 O_data_hs_p[3]_syn_2
-4771 0.401000 1.962000 2.363000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[3]_syn_2.do[0]
+4311 0.928000 4.110000 3.182000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[3]_syn_2.do[2]
 
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
 O_data_hs_p[3]_syn_2
-4805 0.583000 1.962000 2.545000 0 1
+4345 0.929000 4.110000 3.181000 0 1
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3]
 
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
 O_data_hs_p[3]_syn_2
-4839 0.583000 1.962000 2.545000 0 1
+4379 1.075000 4.110000 3.035000 0 1
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1]
 
 
 
+Hold check
+4413 3
+Endpoint: O_data_hs_p[2]_syn_2
+4415 0.401000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_17_syn_2.clk
+O_data_hs_p[2]_syn_2
+4417 0.401000 1.962000 2.363000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[2]_syn_2.do[2]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk
+O_data_hs_p[2]_syn_2
+4451 0.401000 1.962000 2.363000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[2]_syn_2.do[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[2]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[2]_syn_2
+4485 0.623000 1.962000 2.585000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[2]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[2]_syn_2.do[1]
+
+
+Endpoint: O_data_hs_p[3]_syn_2
+4519 0.498000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[3]_syn_2
+4521 0.498000 1.962000 2.460000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[3]_syn_2.do[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_19_syn_2.clk
+O_data_hs_p[3]_syn_2
+4555 0.508000 1.962000 2.470000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[1] O_data_hs_p[3]_syn_2.do[1]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[3]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[3]_syn_2
+4589 0.614000 1.962000 2.576000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[3]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[3]_syn_2.do[3]
+
+
+Endpoint: O_data_hs_p[1]_syn_2
+4623 0.507000 4 3
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_21_syn_2.clk
+O_data_hs_p[1]_syn_2
+4625 0.507000 1.962000 2.469000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[0] O_data_hs_p[1]_syn_2.do[0]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[1]_syn_2
+4659 0.624000 1.962000 2.586000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[2] O_data_hs_p[1]_syn_2.do[2]
+
+Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk->O_data_hs_p[1]_syn_2
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/reg1_syn_15_syn_2.clk
+O_data_hs_p[1]_syn_2
+4693 0.653000 1.962000 2.615000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/[1]$u_data_lane_wrapper/u_data_hs_generate/S_data_hs_oddr[3] O_data_hs_p[1]_syn_2.do[3]
+
+
+
 
 clock: S_clk_x4_90d
-4873 4 2 2
+4727 4 2 2
 Setup check
-4883 1
+4737 1
 Endpoint: O_clk_hs_p_syn_2
-4883 -0.811000 2 2
+4737 -0.811000 2 2
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
 O_clk_hs_p_syn_2
-4885 -0.811000 2.374000 3.185000 0 1
+4739 -0.811000 2.374000 3.185000 0 1
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
 
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
 O_clk_hs_p_syn_2
-4919 -0.810000 2.374000 3.184000 0 1
+4773 -0.708000 2.374000 3.082000 0 1
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
 
 
 
 Hold check
-4953 1
+4807 1
 Endpoint: O_clk_hs_p_syn_2
-4955 2.359000 2 2
+4809 2.282000 2 2
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
 O_clk_hs_p_syn_2
-4957 2.359000 0.226000 2.585000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
+4811 2.282000 0.226000 2.508000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
 
 Timing path: u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk->O_clk_hs_p_syn_2
 u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/reg0_syn_13_syn_2.clk
 O_clk_hs_p_syn_2
-4991 2.359000 0.226000 2.585000 0 1
-u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[0]
+4845 2.359000 0.226000 2.585000 0 1
+u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_clk_hs_data_oddr[0] O_clk_hs_p_syn_2.do[2]
 
 
 
@@ -1322,14 +1302,14 @@ u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/u_clk_lane_wrapper/u_clk_hs_generate/S_cl
 Timing group statistics: 
 	Clock constraints: 
 	  Clock Name                                  Min Period     Max Freq           Skew      Fanout            TNS
-	  S_clk (108.0MHz)                               9.050ns     110.497MHz        0.326ns      1810        0.000ns
-	  a_pclk (48.0MHz)                              12.299ns      81.307MHz        0.326ns      1425        0.000ns
-	  b_pclk (48.0MHz)                              10.093ns      99.079MHz        0.326ns      1358        0.000ns
-	  clk_adc (6.0MHz)                             168.609ns       5.931MHz        0.326ns       942       -3.279ns
-	  a_sclk (168.0MHz)                              2.172ns     460.405MHz        0.254ns        69        0.000ns
-	  b_sclk (168.0MHz)                              2.158ns     463.392MHz        0.326ns        69        0.000ns
-	  S_clk_x2 (216.0MHz)                            2.561ns     390.472MHz        0.480ns        22        0.000ns
-	  S_clk_x4 (432.0MHz)                            1.438ns     695.410MHz        0.018ns         4        0.000ns
+	  S_clk (108.0MHz)                               9.231ns     108.331MHz        0.326ns      1825        0.000ns
+	  a_pclk (48.0MHz)                              12.828ns      77.954MHz        0.326ns      1432        0.000ns
+	  b_pclk (48.0MHz)                              10.513ns      95.120MHz        0.326ns      1342        0.000ns
+	  clk_adc (6.0MHz)                             159.250ns       6.279MHz        0.326ns      1235        0.000ns
+	  a_sclk (168.0MHz)                              1.906ns     524.659MHz        0.254ns        71        0.000ns
+	  b_sclk (168.0MHz)                              2.080ns     480.769MHz        0.326ns        70        0.000ns
+	  S_clk_x2 (216.0MHz)                            2.210ns     452.489MHz        0.480ns        22        0.000ns
+	  S_clk_x4 (432.0MHz)                            1.435ns     696.864MHz        0.018ns         4        0.000ns
 	  S_clk_x4_90d (432.0MHz)                        3.125ns     320.000MHz        0.000ns         1       -0.811ns
 	Minimum input arrival time before clock: no constraint path
 	Maximum output required time after clock: no constraint path
@@ -1343,18 +1323,34 @@ Warning: No clock constraint on 3 clock net(s):
 		Check Type:	MAX
 		----------------------------------------------------------------------------------------------------
 		       Path Num     Constraint                                                                      
-		              0     set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ]
 		              0     set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[3]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d} ]
 		              0     set_false_path -setup -from [ get_pins {u_pll/pll_inst.clkc[1]} ] -to [ get_nets {u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2} ]
 		              1     set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ]
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] 
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 
+		              1     set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ]
+		              2     set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ]
 
 		Check Type:	MIN
 		----------------------------------------------------------------------------------------------------
 		       Path Num     Constraint                                                                      
-		              0     set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_mipi_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clka_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clka_cis_total_num/temp[*]} ]
+		             22     set_false_path -from [ get_nets {u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clkb_cis_total_num/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]} ]
+		             16     set_false_path -from [ get_nets {u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/temp[*]} ]
 		              1     set_false_path -from [ get_regs {BUSY_MIPI} ] -to [ get_regs {BUSY_MIPI_sync_d0} ]
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ] 
 		              0     set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ] 
+		              1     set_false_path -from [ get_nets {u_O_clk_lp_p/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_p/temp[*]} ]
+		              2     set_false_path -from [ get_nets {u_O_clk_lp_n/signal_from[*]} ] -to [ get_regs {u_O_clk_lp_n/temp[*]} ]
 
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db
index 15a41f1..c9cfcd8 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db
index ea2170c..5b3cdd8 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db and b/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
index e4626a9..bdcf7f6 100644
--- a/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
+++ b/src/prj/td_project/hg_anlogic_Runs/phy_1/run.log
@@ -4,7 +4,7 @@
    Executable = D:/Anlogic/TD5.6.2/bin/td.exe
    Built at =   20:34:38 Mar 21 2023
    Run by =     holdtecs
-   Run Date =   Mon Feb 19 10:57:51 2024
+   Run Date =   Tue Mar 12 14:52:10 2024
 
    Run on =     DESKTOP-5MQL5VE
 ============================================================
@@ -79,9 +79,7 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
@@ -99,19 +97,19 @@ HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in .
 HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
 HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
 HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
-HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
-HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
-HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
-HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
-HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
-HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
-HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
-HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
-HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
-HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
-HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
-HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
-HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
 HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
@@ -185,8 +183,6 @@ HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog
 HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
 HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
 HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
 RUN-1001 : Project manager successfully analyzed 61 source files.
 RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
 ARC-1001 : Device Initialization.
@@ -207,9 +203,9 @@ RUN-1001 : Import timing constraints
 RUN-1001 : Import IO constraints
 RUN-1001 : Import Inst constraints
 RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
-RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.171020s wall, 2.093750s user + 0.078125s system = 2.171875s CPU (100.0%)
+RUN-1003 : finish command "import_db ../syn_1/hg_anlogic_gate.db" in  2.470817s wall, 2.421875s user + 0.046875s system = 2.468750s CPU (99.9%)
 
-RUN-1004 : used memory is 336 MB, reserved memory is 314 MB, peak memory is 340 MB
+RUN-1004 : used memory is 354 MB, reserved memory is 324 MB, peak memory is 358 MB
 RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
 RUN-1002 : start command "get_ports clock_source"
 RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
@@ -247,8 +243,26 @@ RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_c
 RUN-1002 : start command "get_ports clock_source"
 RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
 RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
-RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
-RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
 RUN-1002 : start command "set_false_path -from  -to "
 RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
 RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
@@ -265,6 +279,12 @@ RUN-1002 : start command "set_false_path -from  -to "
 RUN-1002 : start command "get_regs clkubus_rstn"
 RUN-1002 : start command "get_nets b_pclk_rstn"
 RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
 RUN-1002 : start command "place"
 RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
 RUN-1001 : Print Global Property
@@ -277,6 +297,7 @@ RUN-1001 :        qor_monitor       |    off     |       off        |
 RUN-1001 :        syn_ip_flow       |    off     |       off        |        
 RUN-1001 :          thread          |    auto    |       auto       |        
 RUN-1001 : ---------------------------------------------------------------
+RUN-1002 : start command "set_param place opt_timing high"
 RUN-1001 : Print Place Property
 RUN-1001 : --------------------------------------------------------------
 RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
@@ -286,7 +307,7 @@ RUN-1001 :          effort         |   medium   |      medium      |
 RUN-1001 :         fix_hold        |    off     |       off        |        
 RUN-1001 :       legalization      |    ori     |       ori        |        
 RUN-1001 :      new_spreading      |     on     |        on        |        
-RUN-1001 :        opt_timing       |   medium   |      medium      |        
+RUN-1001 :        opt_timing       |    high    |      medium      |   *    
 RUN-1001 :   post_clock_route_opt  |    off     |       off        |        
 RUN-1001 :       pr_strategy       |     1      |        1         |        
 RUN-1001 :        relaxation       |    1.00    |       1.00       |        
@@ -346,15 +367,15 @@ SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/clk_config to
 SYN-4015 : Create BUFG instance for clk Net exdev_ctl_a/u_ADconfig/gret9lit16_n to drive 3 clock pins.
 SYN-4015 : Create BUFG instance for clk Net exdev_ctl_b/u_ADconfig/gret9lit16_n to drive 3 clock pins.
 PHY-1001 : Populate physical database on model huagao_mipi_top.
-RUN-1001 : There are total 17673 instances
-RUN-0007 : 7407 luts, 9043 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 20251 nets
+RUN-1001 : There are total 18313 instances
+RUN-0007 : 7475 luts, 9615 seqs, 704 mslices, 371 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 20891 nets
 RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 13316 nets have 2 pins
-RUN-1001 : 5518 nets have [3 - 5] pins
-RUN-1001 : 1004 nets have [6 - 10] pins
-RUN-1001 : 162 nets have [11 - 20] pins
-RUN-1001 : 177 nets have [21 - 99] pins
+RUN-1001 : 13879 nets have 2 pins
+RUN-1001 : 5557 nets have [3 - 5] pins
+RUN-1001 : 1043 nets have [6 - 10] pins
+RUN-1001 : 158 nets have [11 - 20] pins
+RUN-1001 : 180 nets have [21 - 99] pins
 RUN-1001 : 54 nets have 100+ pins
 PHY-1001 : Start to check user instance location assignments; please refer to ADC constraint.
 RUN-1001 : Report Control nets information:
@@ -363,7 +384,7 @@ RUN-1001 : ----------------------------------
 RUN-1001 :   CE   |  SSR  |  ASR  |  DFF Count  
 RUN-1001 : ----------------------------------
 RUN-1001 :   No   |  No   |  No   |     793     
-RUN-1001 :   No   |  No   |  Yes  |    1968     
+RUN-1001 :   No   |  No   |  Yes  |    2540     
 RUN-1001 :   No   |  Yes  |  No   |    3473     
 RUN-1001 :   Yes  |  No   |  No   |     64      
 RUN-1001 :   Yes  |  No   |  Yes  |     72      
@@ -377,923 +398,1211 @@ RUN-0007 :    12   |  76   |     57
 RUN-0007 : ---------------------------
 RUN-0007 : Control Set = 142
 PHY-3001 : Initial placement ...
-PHY-3001 : design contains 17671 instances, 7407 luts, 9043 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1163 with 5897 pins
-PHY-0007 : Cell area utilization is 48%
+PHY-3001 : design contains 18311 instances, 7475 luts, 9615 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6469 pins
+PHY-0007 : Cell area utilization is 49%
 PHY-3001 : Start timing update ...
 RUN-1002 : start command "start_timer -report"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602.
 TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in  1.161753s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (100.9%)
+RUN-1003 : finish command "start_timer -report" in  1.206386s wall, 1.187500s user + 0.015625s system = 1.203125s CPU (99.7%)
 
-RUN-1004 : used memory is 528 MB, reserved memory is 512 MB, peak memory is 528 MB
+RUN-1004 : used memory is 552 MB, reserved memory is 529 MB, peak memory is 552 MB
 TMR-2503 : Start to update net delay, extr mode = 2.
-TMR-2504 : Update delay of 20073 nets completely.
+TMR-2504 : Update delay of 20713 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 2.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
-TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
 TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
 TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  1.976174s wall, 1.968750s user + 0.015625s system = 1.984375s CPU (100.4%)
+PHY-3001 : End timing update;  2.026228s wall, 2.000000s user + 0.031250s system = 2.031250s CPU (100.2%)
 
-PHY-3001 : Found 1227 cells with 2 region constraints.
+PHY-3001 : Found 1222 cells with 2 region constraints.
 PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 4.09967e+06
+PHY-3001 : Initial: Len = 4.00806e+06
 PHY-3001 : Clustering ...
-PHY-3001 : Level 0 #clusters 17671.
-PHY-3001 : Level 1 #clusters 2000.
-PHY-3001 : End clustering;  0.125609s wall, 0.171875s user + 0.000000s system = 0.171875s CPU (136.8%)
+PHY-3001 : Level 0 #clusters 18311.
+PHY-3001 : Level 1 #clusters 2004.
+PHY-3001 : End clustering;  0.130135s wall, 0.156250s user + 0.031250s system = 0.187500s CPU (144.1%)
 
 PHY-3001 : Run with size of 4
-PHY-3001 : Cell area utilization is 48%
+PHY-3001 : Cell area utilization is 49%
 PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(1): len = 1.28668e+06, overlap = 484.094
-PHY-3002 : Step(2): len = 1.18318e+06, overlap = 557.375
-PHY-3002 : Step(3): len = 843931, overlap = 601.625
-PHY-3002 : Step(4): len = 791874, overlap = 624.344
-PHY-3002 : Step(5): len = 609615, overlap = 754.969
-PHY-3002 : Step(6): len = 529112, overlap = 805.719
-PHY-3002 : Step(7): len = 456874, overlap = 912.031
-PHY-3002 : Step(8): len = 425331, overlap = 995.844
-PHY-3002 : Step(9): len = 378282, overlap = 1057.66
-PHY-3002 : Step(10): len = 340965, overlap = 1115.97
-PHY-3002 : Step(11): len = 297218, overlap = 1185.28
-PHY-3002 : Step(12): len = 272422, overlap = 1214.28
-PHY-3002 : Step(13): len = 251103, overlap = 1252.66
-PHY-3002 : Step(14): len = 233830, overlap = 1297.31
-PHY-3002 : Step(15): len = 207240, overlap = 1327.09
-PHY-3002 : Step(16): len = 192315, overlap = 1358.84
-PHY-3002 : Step(17): len = 174239, overlap = 1404.44
-PHY-3002 : Step(18): len = 162009, overlap = 1423.03
-PHY-3002 : Step(19): len = 147685, overlap = 1465.97
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.2036e-06
-PHY-3002 : Step(20): len = 148424, overlap = 1423.66
-PHY-3002 : Step(21): len = 179191, overlap = 1304.53
-PHY-3002 : Step(22): len = 190294, overlap = 1232.22
-PHY-3002 : Step(23): len = 199319, overlap = 1189.78
-PHY-3002 : Step(24): len = 198566, overlap = 1179.34
-PHY-3002 : Step(25): len = 198247, overlap = 1163.12
-PHY-3002 : Step(26): len = 195020, overlap = 1157.25
-PHY-3002 : Step(27): len = 194648, overlap = 1158.09
-PHY-3002 : Step(28): len = 193918, overlap = 1142.66
-PHY-3002 : Step(29): len = 192851, overlap = 1149.03
-PHY-3002 : Step(30): len = 191764, overlap = 1148.06
-PHY-3002 : Step(31): len = 190566, overlap = 1168.28
-PHY-3002 : Step(32): len = 188829, overlap = 1145.56
-PHY-3002 : Step(33): len = 188125, overlap = 1149.47
-PHY-3002 : Step(34): len = 187128, overlap = 1136
-PHY-3002 : Step(35): len = 186806, overlap = 1099.56
-PHY-3002 : Step(36): len = 184419, overlap = 1073.5
-PHY-3002 : Step(37): len = 183688, overlap = 1074.06
-PHY-3002 : Step(38): len = 181963, overlap = 1075.84
-PHY-3002 : Step(39): len = 180821, overlap = 1100.16
-PHY-3002 : Step(40): len = 180049, overlap = 1107.62
-PHY-3002 : Step(41): len = 178563, overlap = 1115.78
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.40721e-06
-PHY-3002 : Step(42): len = 182212, overlap = 1088.72
-PHY-3002 : Step(43): len = 192003, overlap = 1041.94
-PHY-3002 : Step(44): len = 195313, overlap = 996.5
-PHY-3002 : Step(45): len = 200502, overlap = 971.938
-PHY-3002 : Step(46): len = 203704, overlap = 964.062
-PHY-3002 : Step(47): len = 207043, overlap = 946.125
-PHY-3002 : Step(48): len = 207363, overlap = 916.281
-PHY-3002 : Step(49): len = 207868, overlap = 907.031
-PHY-3002 : Step(50): len = 206820, overlap = 918.844
-PHY-3002 : Step(51): len = 206254, overlap = 931.125
-PHY-3002 : Step(52): len = 204603, overlap = 938.312
-PHY-3001 : :::3::: Try harder cell spreading with beta_ = 4.81441e-06
-PHY-3002 : Step(53): len = 211487, overlap = 931
-PHY-3002 : Step(54): len = 228174, overlap = 895.562
-PHY-3002 : Step(55): len = 237150, overlap = 803.812
-PHY-3002 : Step(56): len = 242854, overlap = 767.344
-PHY-3002 : Step(57): len = 244809, overlap = 750.625
-PHY-3002 : Step(58): len = 247200, overlap = 746.219
-PHY-3002 : Step(59): len = 246762, overlap = 749.906
-PHY-3002 : Step(60): len = 246476, overlap = 758.188
-PHY-3002 : Step(61): len = 245504, overlap = 776.312
-PHY-3001 : :::4::: Try harder cell spreading with beta_ = 9.62883e-06
-PHY-3002 : Step(62): len = 259270, overlap = 736.844
-PHY-3002 : Step(63): len = 280310, overlap = 622.125
-PHY-3002 : Step(64): len = 289452, overlap = 594.688
-PHY-3002 : Step(65): len = 292950, overlap = 596.625
-PHY-3002 : Step(66): len = 291834, overlap = 562.719
-PHY-3002 : Step(67): len = 289272, overlap = 547.375
-PHY-3002 : Step(68): len = 287091, overlap = 546.344
-PHY-3002 : Step(69): len = 287110, overlap = 528.281
-PHY-3002 : Step(70): len = 287591, overlap = 509.438
-PHY-3001 : :::5::: Try harder cell spreading with beta_ = 1.92577e-05
-PHY-3002 : Step(71): len = 306070, overlap = 487.531
-PHY-3002 : Step(72): len = 321535, overlap = 471.406
-PHY-3002 : Step(73): len = 327807, overlap = 437.219
-PHY-3002 : Step(74): len = 332649, overlap = 431.281
-PHY-3002 : Step(75): len = 331947, overlap = 424.094
-PHY-3002 : Step(76): len = 332519, overlap = 428.656
-PHY-3002 : Step(77): len = 332226, overlap = 415.594
-PHY-3002 : Step(78): len = 331189, overlap = 397.969
-PHY-3002 : Step(79): len = 330580, overlap = 386.438
-PHY-3002 : Step(80): len = 331430, overlap = 383.438
-PHY-3002 : Step(81): len = 332546, overlap = 365.906
-PHY-3002 : Step(82): len = 332833, overlap = 367.281
-PHY-3002 : Step(83): len = 331822, overlap = 367.219
-PHY-3002 : Step(84): len = 332233, overlap = 356.375
-PHY-3002 : Step(85): len = 331344, overlap = 344.094
-PHY-3001 : :::6::: Try harder cell spreading with beta_ = 3.85153e-05
-PHY-3002 : Step(86): len = 350518, overlap = 322.5
-PHY-3002 : Step(87): len = 360328, overlap = 306.594
-PHY-3002 : Step(88): len = 357880, overlap = 317.406
-PHY-3002 : Step(89): len = 358822, overlap = 305.344
-PHY-3002 : Step(90): len = 363911, overlap = 302.406
-PHY-3002 : Step(91): len = 367835, overlap = 304.938
-PHY-3002 : Step(92): len = 363522, overlap = 317.188
-PHY-3002 : Step(93): len = 365018, overlap = 310.875
-PHY-3002 : Step(94): len = 367761, overlap = 310.25
-PHY-3002 : Step(95): len = 369860, overlap = 319.094
-PHY-3002 : Step(96): len = 365177, overlap = 314.25
-PHY-3002 : Step(97): len = 363436, overlap = 316.188
-PHY-3002 : Step(98): len = 364963, overlap = 322.094
-PHY-3002 : Step(99): len = 366885, overlap = 314
-PHY-3002 : Step(100): len = 363632, overlap = 313.844
-PHY-3002 : Step(101): len = 363549, overlap = 310.25
-PHY-3002 : Step(102): len = 364192, overlap = 304.562
-PHY-3001 : :::7::: Try harder cell spreading with beta_ = 7.70306e-05
-PHY-3002 : Step(103): len = 382186, overlap = 300.719
-PHY-3002 : Step(104): len = 393320, overlap = 290.438
-PHY-3002 : Step(105): len = 390061, overlap = 265.469
-PHY-3002 : Step(106): len = 389428, overlap = 253.938
-PHY-3002 : Step(107): len = 394384, overlap = 237.344
-PHY-3002 : Step(108): len = 399627, overlap = 227.5
-PHY-3002 : Step(109): len = 397812, overlap = 236.219
-PHY-3002 : Step(110): len = 399415, overlap = 243.656
-PHY-3002 : Step(111): len = 402607, overlap = 242.125
-PHY-3002 : Step(112): len = 404322, overlap = 239.312
-PHY-3002 : Step(113): len = 400761, overlap = 240.844
-PHY-3002 : Step(114): len = 399368, overlap = 243.125
-PHY-3002 : Step(115): len = 401595, overlap = 233.938
-PHY-3002 : Step(116): len = 404676, overlap = 239.812
-PHY-3002 : Step(117): len = 400962, overlap = 247.219
-PHY-3002 : Step(118): len = 400739, overlap = 247.281
-PHY-3002 : Step(119): len = 402377, overlap = 239.938
-PHY-3002 : Step(120): len = 404242, overlap = 244.781
-PHY-3002 : Step(121): len = 401723, overlap = 248.594
-PHY-3002 : Step(122): len = 401871, overlap = 252.375
-PHY-3002 : Step(123): len = 404195, overlap = 251.375
-PHY-3002 : Step(124): len = 406140, overlap = 257.312
-PHY-3002 : Step(125): len = 403540, overlap = 259.656
-PHY-3002 : Step(126): len = 403245, overlap = 259.188
-PHY-3002 : Step(127): len = 403984, overlap = 258
-PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000154061
-PHY-3002 : Step(128): len = 419164, overlap = 244.906
-PHY-3002 : Step(129): len = 428463, overlap = 233.125
-PHY-3002 : Step(130): len = 426829, overlap = 217.812
-PHY-3002 : Step(131): len = 427102, overlap = 211.844
-PHY-3002 : Step(132): len = 429947, overlap = 210.938
-PHY-3002 : Step(133): len = 431921, overlap = 206.281
-PHY-3002 : Step(134): len = 429822, overlap = 204.156
-PHY-3002 : Step(135): len = 430225, overlap = 212.344
-PHY-3002 : Step(136): len = 432285, overlap = 210.5
-PHY-3002 : Step(137): len = 434226, overlap = 207.281
-PHY-3002 : Step(138): len = 433644, overlap = 199.531
-PHY-3002 : Step(139): len = 434785, overlap = 208.406
-PHY-3002 : Step(140): len = 436011, overlap = 203.75
-PHY-3002 : Step(141): len = 437222, overlap = 200.469
-PHY-3002 : Step(142): len = 436221, overlap = 201.188
-PHY-3002 : Step(143): len = 436724, overlap = 207.406
-PHY-3002 : Step(144): len = 437985, overlap = 207.875
-PHY-3002 : Step(145): len = 439045, overlap = 207.375
-PHY-3002 : Step(146): len = 437923, overlap = 207.281
-PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000297449
-PHY-3002 : Step(147): len = 447213, overlap = 201.406
-PHY-3002 : Step(148): len = 454452, overlap = 203.656
-PHY-3002 : Step(149): len = 454959, overlap = 198.281
-PHY-3002 : Step(150): len = 455780, overlap = 191
-PHY-3002 : Step(151): len = 458270, overlap = 186.562
-PHY-3002 : Step(152): len = 459849, overlap = 184
-PHY-3002 : Step(153): len = 458838, overlap = 186.688
-PHY-3002 : Step(154): len = 459485, overlap = 181.969
-PHY-3002 : Step(155): len = 461789, overlap = 184.562
-PHY-3002 : Step(156): len = 463496, overlap = 173.094
-PHY-3002 : Step(157): len = 462326, overlap = 171.438
-PHY-3002 : Step(158): len = 462656, overlap = 170.656
-PHY-3002 : Step(159): len = 464690, overlap = 167.469
-PHY-3002 : Step(160): len = 466201, overlap = 171.656
-PHY-3002 : Step(161): len = 465166, overlap = 165.188
-PHY-3002 : Step(162): len = 465218, overlap = 167.594
-PHY-3002 : Step(163): len = 466623, overlap = 165.719
-PHY-3002 : Step(164): len = 467287, overlap = 162.25
-PHY-3002 : Step(165): len = 466412, overlap = 161.688
-PHY-3002 : Step(166): len = 466327, overlap = 158.469
-PHY-3002 : Step(167): len = 467295, overlap = 161.75
-PHY-3002 : Step(168): len = 468354, overlap = 160.594
-PHY-3002 : Step(169): len = 468124, overlap = 155.656
-PHY-3002 : Step(170): len = 468614, overlap = 159.062
-PHY-3002 : Step(171): len = 469394, overlap = 153.281
-PHY-3002 : Step(172): len = 469789, overlap = 151.75
-PHY-3002 : Step(173): len = 470169, overlap = 135.656
-PHY-3002 : Step(174): len = 471663, overlap = 137.594
-PHY-3002 : Step(175): len = 472466, overlap = 133.844
-PHY-3002 : Step(176): len = 473025, overlap = 132.812
-PHY-3002 : Step(177): len = 472951, overlap = 135.25
-PHY-3002 : Step(178): len = 473084, overlap = 136.938
-PHY-3002 : Step(179): len = 473356, overlap = 135.25
-PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000566962
-PHY-3002 : Step(180): len = 479949, overlap = 132.312
-PHY-3002 : Step(181): len = 485650, overlap = 134
-PHY-3002 : Step(182): len = 486958, overlap = 125.781
-PHY-3002 : Step(183): len = 488201, overlap = 126
-PHY-3002 : Step(184): len = 490404, overlap = 126.844
-PHY-3002 : Step(185): len = 492125, overlap = 131.5
-PHY-3002 : Step(186): len = 492854, overlap = 128.094
-PHY-3002 : Step(187): len = 494116, overlap = 125.406
-PHY-3002 : Step(188): len = 496340, overlap = 126.312
-PHY-3002 : Step(189): len = 497988, overlap = 123.688
-PHY-3002 : Step(190): len = 498041, overlap = 122.812
-PHY-3002 : Step(191): len = 498102, overlap = 120.5
-PHY-3002 : Step(192): len = 498689, overlap = 124.594
-PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00109183
-PHY-3002 : Step(193): len = 502699, overlap = 120.406
-PHY-3002 : Step(194): len = 508726, overlap = 117.844
-PHY-3002 : Step(195): len = 511069, overlap = 114.281
-PHY-3002 : Step(196): len = 512644, overlap = 114.906
-PHY-3002 : Step(197): len = 513979, overlap = 114.875
-PHY-3002 : Step(198): len = 515197, overlap = 112.781
-PHY-3002 : Step(199): len = 515367, overlap = 112.906
-PHY-3002 : Step(200): len = 515820, overlap = 108.875
-PHY-3002 : Step(201): len = 516704, overlap = 111.188
-PHY-3002 : Step(202): len = 517142, overlap = 112.75
-PHY-3002 : Step(203): len = 517073, overlap = 107.688
-PHY-3002 : Step(204): len = 517115, overlap = 107.688
-PHY-3002 : Step(205): len = 517492, overlap = 112
-PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.00191502
-PHY-3002 : Step(206): len = 520575, overlap = 107.125
-PHY-3002 : Step(207): len = 525493, overlap = 102.531
-PHY-3002 : Step(208): len = 526615, overlap = 100.969
-PHY-3002 : Step(209): len = 527208, overlap = 101.75
-PHY-3002 : Step(210): len = 528067, overlap = 102.562
-PHY-3002 : Step(211): len = 529197, overlap = 104.125
-PHY-3002 : Step(212): len = 530271, overlap = 102.125
-PHY-3002 : Step(213): len = 532302, overlap = 102.125
-PHY-3002 : Step(214): len = 533399, overlap = 103.219
-PHY-3002 : Step(215): len = 533896, overlap = 100.969
-PHY-3002 : Step(216): len = 534380, overlap = 98.9375
-PHY-3002 : Step(217): len = 534814, overlap = 96.5
-PHY-3002 : Step(218): len = 535308, overlap = 96.6875
+PHY-3002 : Step(1): len = 1.25808e+06, overlap = 537.594
+PHY-3002 : Step(2): len = 1.17948e+06, overlap = 555.469
+PHY-3002 : Step(3): len = 805880, overlap = 617.25
+PHY-3002 : Step(4): len = 747389, overlap = 670.188
+PHY-3002 : Step(5): len = 580252, overlap = 828.438
+PHY-3002 : Step(6): len = 506405, overlap = 888.562
+PHY-3002 : Step(7): len = 438740, overlap = 953.062
+PHY-3002 : Step(8): len = 405793, overlap = 990.031
+PHY-3002 : Step(9): len = 368140, overlap = 999.406
+PHY-3002 : Step(10): len = 335219, overlap = 1063.25
+PHY-3002 : Step(11): len = 304746, overlap = 1095.97
+PHY-3002 : Step(12): len = 274497, overlap = 1117.5
+PHY-3002 : Step(13): len = 258167, overlap = 1150.56
+PHY-3002 : Step(14): len = 234928, overlap = 1220.59
+PHY-3002 : Step(15): len = 218432, overlap = 1280.91
+PHY-3002 : Step(16): len = 199574, overlap = 1330.09
+PHY-3002 : Step(17): len = 179244, overlap = 1360.41
+PHY-3002 : Step(18): len = 168619, overlap = 1364.97
+PHY-3002 : Step(19): len = 153530, overlap = 1394.62
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 1.37726e-06
+PHY-3002 : Step(20): len = 156286, overlap = 1372.84
+PHY-3002 : Step(21): len = 190148, overlap = 1281.91
+PHY-3002 : Step(22): len = 194863, overlap = 1229.56
+PHY-3002 : Step(23): len = 199569, overlap = 1171.84
+PHY-3002 : Step(24): len = 197760, overlap = 1203.22
+PHY-3002 : Step(25): len = 197337, overlap = 1227.56
+PHY-3002 : Step(26): len = 194838, overlap = 1227.19
+PHY-3002 : Step(27): len = 192802, overlap = 1221.19
+PHY-3002 : Step(28): len = 190823, overlap = 1218.09
+PHY-3002 : Step(29): len = 189585, overlap = 1208.81
+PHY-3002 : Step(30): len = 187401, overlap = 1200.69
+PHY-3002 : Step(31): len = 186285, overlap = 1197.38
+PHY-3002 : Step(32): len = 186493, overlap = 1166.91
+PHY-3002 : Step(33): len = 185759, overlap = 1155.12
+PHY-3002 : Step(34): len = 185102, overlap = 1127.38
+PHY-3002 : Step(35): len = 183975, overlap = 1115.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 2.75453e-06
+PHY-3002 : Step(36): len = 187471, overlap = 1107.03
+PHY-3002 : Step(37): len = 198764, overlap = 1090.66
+PHY-3002 : Step(38): len = 202928, overlap = 1067.75
+PHY-3002 : Step(39): len = 207381, overlap = 1034.38
+PHY-3002 : Step(40): len = 210559, overlap = 1015.44
+PHY-3002 : Step(41): len = 213446, overlap = 990
+PHY-3002 : Step(42): len = 212214, overlap = 968.312
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 5.50906e-06
+PHY-3002 : Step(43): len = 221098, overlap = 913.219
+PHY-3002 : Step(44): len = 242358, overlap = 819.594
+PHY-3002 : Step(45): len = 255165, overlap = 778.438
+PHY-3002 : Step(46): len = 267478, overlap = 731
+PHY-3002 : Step(47): len = 271662, overlap = 720.438
+PHY-3002 : Step(48): len = 271709, overlap = 706.906
+PHY-3002 : Step(49): len = 270113, overlap = 680
+PHY-3002 : Step(50): len = 269630, overlap = 679.875
+PHY-3002 : Step(51): len = 267425, overlap = 688.156
+PHY-3002 : Step(52): len = 265303, overlap = 695.812
+PHY-3002 : Step(53): len = 262713, overlap = 706.719
+PHY-3001 : :::4::: Try harder cell spreading with beta_ = 1.10181e-05
+PHY-3002 : Step(54): len = 281886, overlap = 673.031
+PHY-3002 : Step(55): len = 297627, overlap = 598.438
+PHY-3002 : Step(56): len = 304406, overlap = 543.031
+PHY-3002 : Step(57): len = 308710, overlap = 545.219
+PHY-3002 : Step(58): len = 307694, overlap = 551.438
+PHY-3002 : Step(59): len = 307802, overlap = 554.938
+PHY-3002 : Step(60): len = 304819, overlap = 550.656
+PHY-3002 : Step(61): len = 305086, overlap = 548.125
+PHY-3002 : Step(62): len = 303942, overlap = 549.188
+PHY-3002 : Step(63): len = 304623, overlap = 548.75
+PHY-3002 : Step(64): len = 301771, overlap = 538.562
+PHY-3002 : Step(65): len = 301740, overlap = 527.969
+PHY-3002 : Step(66): len = 301591, overlap = 528.219
+PHY-3001 : :::5::: Try harder cell spreading with beta_ = 2.20362e-05
+PHY-3002 : Step(67): len = 316913, overlap = 533.75
+PHY-3002 : Step(68): len = 328114, overlap = 511.719
+PHY-3002 : Step(69): len = 332758, overlap = 471.406
+PHY-3002 : Step(70): len = 335310, overlap = 472.625
+PHY-3002 : Step(71): len = 334783, overlap = 483.938
+PHY-3002 : Step(72): len = 337780, overlap = 470.219
+PHY-3002 : Step(73): len = 338712, overlap = 458.938
+PHY-3002 : Step(74): len = 340455, overlap = 459.062
+PHY-3002 : Step(75): len = 339404, overlap = 467.625
+PHY-3002 : Step(76): len = 340251, overlap = 463.375
+PHY-3002 : Step(77): len = 339541, overlap = 456.281
+PHY-3002 : Step(78): len = 340666, overlap = 462.219
+PHY-3002 : Step(79): len = 339598, overlap = 465.75
+PHY-3001 : :::6::: Try harder cell spreading with beta_ = 4.40725e-05
+PHY-3002 : Step(80): len = 358475, overlap = 417.094
+PHY-3002 : Step(81): len = 371673, overlap = 392.438
+PHY-3002 : Step(82): len = 371429, overlap = 384
+PHY-3002 : Step(83): len = 373076, overlap = 377.188
+PHY-3002 : Step(84): len = 375376, overlap = 382.594
+PHY-3002 : Step(85): len = 379126, overlap = 374.875
+PHY-3002 : Step(86): len = 376946, overlap = 358.219
+PHY-3002 : Step(87): len = 380036, overlap = 349.438
+PHY-3002 : Step(88): len = 381497, overlap = 324.781
+PHY-3002 : Step(89): len = 383751, overlap = 328.844
+PHY-3002 : Step(90): len = 378101, overlap = 320.062
+PHY-3002 : Step(91): len = 377588, overlap = 307.562
+PHY-3002 : Step(92): len = 380210, overlap = 315.656
+PHY-3002 : Step(93): len = 382216, overlap = 309.469
+PHY-3002 : Step(94): len = 377413, overlap = 316.156
+PHY-3002 : Step(95): len = 376819, overlap = 314.219
+PHY-3002 : Step(96): len = 378971, overlap = 320.594
+PHY-3002 : Step(97): len = 381832, overlap = 309.156
+PHY-3002 : Step(98): len = 378679, overlap = 322.562
+PHY-3002 : Step(99): len = 378909, overlap = 328.312
+PHY-3002 : Step(100): len = 381466, overlap = 320.75
+PHY-3002 : Step(101): len = 383108, overlap = 322.375
+PHY-3002 : Step(102): len = 379254, overlap = 323.375
+PHY-3002 : Step(103): len = 378855, overlap = 336.344
+PHY-3002 : Step(104): len = 382473, overlap = 334.438
+PHY-3002 : Step(105): len = 385118, overlap = 324.469
+PHY-3002 : Step(106): len = 379894, overlap = 330
+PHY-3002 : Step(107): len = 379380, overlap = 334
+PHY-3002 : Step(108): len = 381186, overlap = 337.844
+PHY-3002 : Step(109): len = 383820, overlap = 343.094
+PHY-3002 : Step(110): len = 380397, overlap = 343.188
+PHY-3002 : Step(111): len = 380110, overlap = 335.906
+PHY-3002 : Step(112): len = 381876, overlap = 333.656
+PHY-3002 : Step(113): len = 382988, overlap = 331.688
+PHY-3002 : Step(114): len = 379633, overlap = 340.5
+PHY-3001 : :::7::: Try harder cell spreading with beta_ = 8.69695e-05
+PHY-3002 : Step(115): len = 396380, overlap = 324.281
+PHY-3002 : Step(116): len = 404504, overlap = 316.625
+PHY-3002 : Step(117): len = 402189, overlap = 319.906
+PHY-3002 : Step(118): len = 402844, overlap = 307.562
+PHY-3002 : Step(119): len = 407559, overlap = 300.656
+PHY-3002 : Step(120): len = 410960, overlap = 293.938
+PHY-3002 : Step(121): len = 409023, overlap = 313.469
+PHY-3002 : Step(122): len = 410609, overlap = 307.719
+PHY-3002 : Step(123): len = 413005, overlap = 302.188
+PHY-3002 : Step(124): len = 415370, overlap = 304.281
+PHY-3002 : Step(125): len = 411929, overlap = 304.812
+PHY-3002 : Step(126): len = 411455, overlap = 301.156
+PHY-3002 : Step(127): len = 413253, overlap = 297.406
+PHY-3002 : Step(128): len = 415569, overlap = 296.688
+PHY-3002 : Step(129): len = 413280, overlap = 298.125
+PHY-3002 : Step(130): len = 414014, overlap = 299.562
+PHY-3002 : Step(131): len = 415804, overlap = 291.688
+PHY-3002 : Step(132): len = 416706, overlap = 287.562
+PHY-3002 : Step(133): len = 414488, overlap = 293.062
+PHY-3002 : Step(134): len = 414222, overlap = 296.188
+PHY-3002 : Step(135): len = 416186, overlap = 297.844
+PHY-3002 : Step(136): len = 418247, overlap = 297.594
+PHY-3002 : Step(137): len = 415157, overlap = 307.406
+PHY-3002 : Step(138): len = 414792, overlap = 302.969
+PHY-3002 : Step(139): len = 416141, overlap = 297.094
+PHY-3001 : :::8::: Try harder cell spreading with beta_ = 0.000173939
+PHY-3002 : Step(140): len = 429093, overlap = 281.469
+PHY-3002 : Step(141): len = 436379, overlap = 267.344
+PHY-3002 : Step(142): len = 436546, overlap = 270.844
+PHY-3002 : Step(143): len = 437380, overlap = 260
+PHY-3002 : Step(144): len = 439507, overlap = 261.031
+PHY-3002 : Step(145): len = 442472, overlap = 260.094
+PHY-3002 : Step(146): len = 443304, overlap = 254.219
+PHY-3002 : Step(147): len = 444774, overlap = 251.031
+PHY-3002 : Step(148): len = 447138, overlap = 255.531
+PHY-3002 : Step(149): len = 448747, overlap = 255.688
+PHY-3002 : Step(150): len = 447451, overlap = 243.031
+PHY-3002 : Step(151): len = 447432, overlap = 241.656
+PHY-3002 : Step(152): len = 447994, overlap = 237.375
+PHY-3002 : Step(153): len = 448451, overlap = 237.281
+PHY-3002 : Step(154): len = 446798, overlap = 237.188
+PHY-3002 : Step(155): len = 446275, overlap = 236.5
+PHY-3002 : Step(156): len = 447543, overlap = 230.219
+PHY-3002 : Step(157): len = 449128, overlap = 220.375
+PHY-3002 : Step(158): len = 447139, overlap = 219.219
+PHY-3002 : Step(159): len = 446549, overlap = 211.5
+PHY-3002 : Step(160): len = 447169, overlap = 214.344
+PHY-3002 : Step(161): len = 447800, overlap = 215.125
+PHY-3002 : Step(162): len = 446898, overlap = 207.406
+PHY-3002 : Step(163): len = 446875, overlap = 201.406
+PHY-3002 : Step(164): len = 447304, overlap = 210.5
+PHY-3001 : :::9::: Try harder cell spreading with beta_ = 0.000347504
+PHY-3002 : Step(165): len = 457687, overlap = 210.438
+PHY-3002 : Step(166): len = 465640, overlap = 207.938
+PHY-3002 : Step(167): len = 466285, overlap = 204.312
+PHY-3002 : Step(168): len = 467249, overlap = 195.25
+PHY-3002 : Step(169): len = 469554, overlap = 192.719
+PHY-3002 : Step(170): len = 471718, overlap = 200
+PHY-3002 : Step(171): len = 471191, overlap = 203.031
+PHY-3002 : Step(172): len = 471762, overlap = 203.625
+PHY-3002 : Step(173): len = 474201, overlap = 204.312
+PHY-3002 : Step(174): len = 475784, overlap = 201.562
+PHY-3002 : Step(175): len = 474873, overlap = 204.906
+PHY-3002 : Step(176): len = 474276, overlap = 202.906
+PHY-3002 : Step(177): len = 475208, overlap = 198.844
+PHY-3002 : Step(178): len = 478795, overlap = 189.438
+PHY-3002 : Step(179): len = 478779, overlap = 190.219
+PHY-3002 : Step(180): len = 479429, overlap = 196.031
+PHY-3002 : Step(181): len = 480439, overlap = 190.375
+PHY-3002 : Step(182): len = 481046, overlap = 190.844
+PHY-3002 : Step(183): len = 480074, overlap = 193.062
+PHY-3002 : Step(184): len = 479914, overlap = 196.062
+PHY-3002 : Step(185): len = 480011, overlap = 187.688
+PHY-3002 : Step(186): len = 480060, overlap = 186.594
+PHY-3002 : Step(187): len = 479977, overlap = 191.312
+PHY-3002 : Step(188): len = 480291, overlap = 189.219
+PHY-3002 : Step(189): len = 480033, overlap = 187.594
+PHY-3002 : Step(190): len = 480026, overlap = 184.906
+PHY-3002 : Step(191): len = 480182, overlap = 185.344
+PHY-3001 : :::10::: Try harder cell spreading with beta_ = 0.000629862
+PHY-3002 : Step(192): len = 484636, overlap = 185
+PHY-3002 : Step(193): len = 491568, overlap = 188.906
+PHY-3002 : Step(194): len = 492459, overlap = 174.625
+PHY-3002 : Step(195): len = 493328, overlap = 178.156
+PHY-3002 : Step(196): len = 494684, overlap = 175.781
+PHY-3002 : Step(197): len = 495973, overlap = 182.688
+PHY-3002 : Step(198): len = 496068, overlap = 180.688
+PHY-3002 : Step(199): len = 496492, overlap = 179.375
+PHY-3002 : Step(200): len = 497525, overlap = 179.062
+PHY-3002 : Step(201): len = 497860, overlap = 178.938
+PHY-3002 : Step(202): len = 497995, overlap = 176.688
+PHY-3001 : :::11::: Try harder cell spreading with beta_ = 0.00106194
+PHY-3002 : Step(203): len = 501189, overlap = 172.438
+PHY-3002 : Step(204): len = 505162, overlap = 170.562
+PHY-3002 : Step(205): len = 505875, overlap = 159.469
+PHY-3002 : Step(206): len = 506812, overlap = 163.594
+PHY-3002 : Step(207): len = 509113, overlap = 160.812
+PHY-3002 : Step(208): len = 511531, overlap = 160.969
+PHY-3002 : Step(209): len = 512285, overlap = 163.625
+PHY-3002 : Step(210): len = 512751, overlap = 164.281
+PHY-3002 : Step(211): len = 513549, overlap = 160.531
+PHY-3002 : Step(212): len = 514423, overlap = 165.031
+PHY-3002 : Step(213): len = 514641, overlap = 168.281
+PHY-3002 : Step(214): len = 515054, overlap = 166.562
+PHY-3002 : Step(215): len = 515798, overlap = 163.719
+PHY-3002 : Step(216): len = 516032, overlap = 161.594
+PHY-3002 : Step(217): len = 516078, overlap = 162.438
+PHY-3001 : :::12::: Try harder cell spreading with beta_ = 0.0017657
+PHY-3002 : Step(218): len = 519424, overlap = 162.188
+PHY-3002 : Step(219): len = 528170, overlap = 161.281
+PHY-3002 : Step(220): len = 528993, overlap = 160.875
+PHY-3002 : Step(221): len = 529757, overlap = 166
+PHY-3002 : Step(222): len = 531547, overlap = 169.75
+PHY-3002 : Step(223): len = 532471, overlap = 171.062
+PHY-3002 : Step(224): len = 532202, overlap = 169.25
+PHY-3002 : Step(225): len = 532186, overlap = 160.906
+PHY-3002 : Step(226): len = 533182, overlap = 164.469
+PHY-3002 : Step(227): len = 534273, overlap = 161.219
+PHY-3002 : Step(228): len = 534293, overlap = 156.25
+PHY-3002 : Step(229): len = 534480, overlap = 155.875
+PHY-3002 : Step(230): len = 535266, overlap = 157.812
+PHY-3002 : Step(231): len = 535593, overlap = 158.156
+PHY-3002 : Step(232): len = 535598, overlap = 156.781
+PHY-3002 : Step(233): len = 535732, overlap = 156.344
+PHY-3002 : Step(234): len = 536545, overlap = 158.906
+PHY-3002 : Step(235): len = 537668, overlap = 158.875
+PHY-3002 : Step(236): len = 537696, overlap = 160.156
+PHY-3002 : Step(237): len = 537796, overlap = 157.844
+PHY-3002 : Step(238): len = 538367, overlap = 157.031
 PHY-3001 : Legalization ...
-PHY-3001 : End legalization;  0.014083s wall, 0.031250s user + 0.015625s system = 0.046875s CPU (332.8%)
+PHY-3001 : End legalization;  0.014376s wall, 0.015625s user + 0.046875s system = 0.062500s CPU (434.7%)
 
 PHY-3001 : Run with size of 4
-PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Cell area utilization is 56%
 PHY-3001 : Analyzing congestion ...
 RUN-1001 : Generating global routing grids ...
 RUN-1001 : Building simple global routing graph ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 0/20251.
+PHY-1001 : Reuse net number 0/20891.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 705016, over cnt = 1536(4%), over = 7270, worst = 58
-PHY-1001 : End global iterations;  0.697043s wall, 1.015625s user + 0.046875s system = 1.062500s CPU (152.4%)
+PHY-1002 : len = 706104, over cnt = 1605(4%), over = 7585, worst = 45
+PHY-1001 : End global iterations;  0.688595s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (136.1%)
 
-PHY-1001 : Congestion index: top1 = 78.64, top5 = 60.55, top10 = 51.46, top15 = 45.82.
-PHY-3001 : End congestion estimation;  0.923953s wall, 1.265625s user + 0.046875s system = 1.312500s CPU (142.1%)
+PHY-1001 : Congestion index: top1 = 81.38, top5 = 61.13, top10 = 52.56, top15 = 47.12.
+PHY-3001 : End congestion estimation;  0.911135s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (126.9%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20073 nets completely.
+TMR-2504 : Update delay of 20713 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  0.844461s wall, 0.828125s user + 0.015625s system = 0.843750s CPU (99.9%)
+PHY-3001 : End timing update;  0.876627s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (101.6%)
 
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000143207
-PHY-3002 : Step(219): len = 646213, overlap = 36.1875
-PHY-3002 : Step(220): len = 644319, overlap = 34.0938
-PHY-3002 : Step(221): len = 639708, overlap = 39.3438
-PHY-3002 : Step(222): len = 639697, overlap = 46.5312
-PHY-3002 : Step(223): len = 642009, overlap = 48.0312
-PHY-3002 : Step(224): len = 641422, overlap = 47.8125
-PHY-3002 : Step(225): len = 640251, overlap = 44.2188
-PHY-3002 : Step(226): len = 638069, overlap = 35.5625
-PHY-3002 : Step(227): len = 635262, overlap = 23.5
-PHY-3002 : Step(228): len = 631544, overlap = 27.6875
-PHY-3002 : Step(229): len = 628555, overlap = 28.2812
-PHY-3002 : Step(230): len = 626551, overlap = 29.0312
-PHY-3002 : Step(231): len = 624331, overlap = 32.0312
-PHY-3002 : Step(232): len = 622629, overlap = 37.5625
-PHY-3002 : Step(233): len = 620279, overlap = 34.2812
-PHY-3002 : Step(234): len = 620152, overlap = 34.7812
-PHY-3002 : Step(235): len = 617309, overlap = 36.5625
-PHY-3002 : Step(236): len = 615563, overlap = 38.2188
-PHY-3002 : Step(237): len = 614250, overlap = 37.7812
-PHY-3002 : Step(238): len = 613568, overlap = 37.75
-PHY-3002 : Step(239): len = 611804, overlap = 36.5
-PHY-3002 : Step(240): len = 610938, overlap = 38.875
-PHY-3002 : Step(241): len = 609379, overlap = 39.9062
-PHY-3002 : Step(242): len = 608310, overlap = 39.2812
-PHY-3002 : Step(243): len = 607656, overlap = 40.0312
-PHY-3002 : Step(244): len = 605710, overlap = 41.8438
-PHY-3002 : Step(245): len = 605011, overlap = 44.0625
-PHY-3002 : Step(246): len = 603058, overlap = 43.3438
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000286414
-PHY-3002 : Step(247): len = 605841, overlap = 43.4688
-PHY-3002 : Step(248): len = 609140, overlap = 42.8438
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000469768
-PHY-3002 : Step(249): len = 613099, overlap = 42.2188
-PHY-3002 : Step(250): len = 620558, overlap = 41.125
-PHY-3002 : Step(251): len = 635556, overlap = 34.5938
-PHY-3002 : Step(252): len = 638311, overlap = 33.125
-PHY-3002 : Step(253): len = 640895, overlap = 31.9375
-PHY-3002 : Step(254): len = 642045, overlap = 32.5625
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000147396
+PHY-3002 : Step(239): len = 641511, overlap = 105.406
+PHY-3002 : Step(240): len = 640037, overlap = 96.4375
+PHY-3002 : Step(241): len = 635785, overlap = 90.5938
+PHY-3002 : Step(242): len = 635141, overlap = 80.8438
+PHY-3002 : Step(243): len = 635198, overlap = 74.8125
+PHY-3002 : Step(244): len = 631981, overlap = 69.3125
+PHY-3002 : Step(245): len = 628790, overlap = 63.875
+PHY-3002 : Step(246): len = 627388, overlap = 61.75
+PHY-3002 : Step(247): len = 624297, overlap = 57.1875
+PHY-3002 : Step(248): len = 620643, overlap = 57.3125
+PHY-3002 : Step(249): len = 618809, overlap = 59.7188
+PHY-3002 : Step(250): len = 616473, overlap = 58.375
+PHY-3002 : Step(251): len = 614842, overlap = 52.0312
+PHY-3002 : Step(252): len = 614370, overlap = 51.6562
+PHY-3002 : Step(253): len = 613433, overlap = 50.5938
+PHY-3002 : Step(254): len = 612101, overlap = 51.4375
+PHY-3002 : Step(255): len = 611656, overlap = 55.5312
+PHY-3002 : Step(256): len = 609221, overlap = 55.7812
+PHY-3002 : Step(257): len = 607441, overlap = 55.875
+PHY-3002 : Step(258): len = 605551, overlap = 56.7812
+PHY-3002 : Step(259): len = 603713, overlap = 56.9375
+PHY-3002 : Step(260): len = 601945, overlap = 58.375
+PHY-3002 : Step(261): len = 600761, overlap = 58.9688
+PHY-3002 : Step(262): len = 599246, overlap = 57.5312
+PHY-3002 : Step(263): len = 598384, overlap = 54.0625
+PHY-3002 : Step(264): len = 597774, overlap = 54.0312
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000294791
+PHY-3002 : Step(265): len = 602124, overlap = 52.9062
+PHY-3002 : Step(266): len = 602124, overlap = 52.9062
+PHY-3002 : Step(267): len = 602455, overlap = 51.9375
 PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 55%
+PHY-3001 : Cell area utilization is 56%
 PHY-3001 : Analyzing congestion ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 40/20251.
+PHY-1001 : Reuse net number 102/20891.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 731656, over cnt = 2654(7%), over = 12250, worst = 64
-PHY-1001 : End global iterations;  1.758166s wall, 2.359375s user + 0.046875s system = 2.406250s CPU (136.9%)
+PHY-1002 : len = 684712, over cnt = 2538(7%), over = 10926, worst = 61
+PHY-1001 : End global iterations;  1.668208s wall, 2.125000s user + 0.015625s system = 2.140625s CPU (128.3%)
 
-PHY-1001 : Congestion index: top1 = 85.02, top5 = 66.04, top10 = 57.79, top15 = 52.68.
-PHY-3001 : End congestion estimation;  2.028716s wall, 2.640625s user + 0.046875s system = 2.687500s CPU (132.5%)
+PHY-1001 : Congestion index: top1 = 79.40, top5 = 62.52, top10 = 54.61, top15 = 49.89.
+PHY-3001 : End congestion estimation;  1.942959s wall, 2.390625s user + 0.015625s system = 2.406250s CPU (123.8%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20073 nets completely.
+TMR-2504 : Update delay of 20713 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  1.066492s wall, 1.031250s user + 0.031250s system = 1.062500s CPU (99.6%)
+PHY-3001 : End timing update;  0.903062s wall, 0.906250s user + 0.000000s system = 0.906250s CPU (100.4%)
 
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.00012412
-PHY-3002 : Step(255): len = 634493, overlap = 218.594
-PHY-3002 : Step(256): len = 633945, overlap = 186.656
-PHY-3002 : Step(257): len = 624281, overlap = 182.938
-PHY-3002 : Step(258): len = 620956, overlap = 176.469
-PHY-3002 : Step(259): len = 616979, overlap = 157.156
-PHY-3002 : Step(260): len = 613520, overlap = 135.344
-PHY-3002 : Step(261): len = 609779, overlap = 127.906
-PHY-3002 : Step(262): len = 608368, overlap = 127.469
-PHY-3002 : Step(263): len = 603987, overlap = 124.812
-PHY-3002 : Step(264): len = 601816, overlap = 126.906
-PHY-3002 : Step(265): len = 599563, overlap = 125.969
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.00024824
-PHY-3002 : Step(266): len = 599695, overlap = 121.312
-PHY-3002 : Step(267): len = 601392, overlap = 118.5
-PHY-3002 : Step(268): len = 603887, overlap = 117.031
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000496481
-PHY-3002 : Step(269): len = 610653, overlap = 103.031
-PHY-3002 : Step(270): len = 617658, overlap = 96.375
-PHY-3002 : Step(271): len = 621957, overlap = 93.625
-PHY-3002 : Step(272): len = 624159, overlap = 89.5625
-PHY-3002 : Step(273): len = 623537, overlap = 89.2188
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 7.83893e-05
+PHY-3002 : Step(268): len = 602232, overlap = 264.625
+PHY-3002 : Step(269): len = 606216, overlap = 234.656
+PHY-3002 : Step(270): len = 600744, overlap = 225.219
+PHY-3002 : Step(271): len = 599256, overlap = 214.812
+PHY-3002 : Step(272): len = 596499, overlap = 207.125
+PHY-3002 : Step(273): len = 593592, overlap = 190.25
+PHY-3002 : Step(274): len = 593046, overlap = 180.375
+PHY-3002 : Step(275): len = 589416, overlap = 180.781
+PHY-3002 : Step(276): len = 587384, overlap = 179.938
+PHY-3002 : Step(277): len = 586438, overlap = 174.219
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000156779
+PHY-3002 : Step(278): len = 585723, overlap = 170.719
+PHY-3002 : Step(279): len = 588639, overlap = 164.906
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000298785
+PHY-3002 : Step(280): len = 597053, overlap = 150.094
+PHY-3002 : Step(281): len = 605801, overlap = 136.844
+PHY-3002 : Step(282): len = 609405, overlap = 129
+PHY-3002 : Step(283): len = 609633, overlap = 127.938
+PHY-3002 : Step(284): len = 609883, overlap = 125.094
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000597571
+PHY-3002 : Step(285): len = 612494, overlap = 118.562
+PHY-3002 : Step(286): len = 618492, overlap = 112.938
+PHY-3002 : Step(287): len = 622904, overlap = 102.719
 OPT-1001 : Start physical optimization ...
 RUN-1002 : start command "start_timer -report"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 84608, tnet num: 20073, tinst num: 17671, tnode num: 114692, tedge num: 135800.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 87149, tnet num: 20713, tinst num: 18311, tnode num: 118925, tedge num: 139602.
 TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in  1.458795s wall, 1.453125s user + 0.015625s system = 1.468750s CPU (100.7%)
+RUN-1003 : finish command "start_timer -report" in  1.460893s wall, 1.437500s user + 0.031250s system = 1.468750s CPU (100.5%)
 
-RUN-1004 : used memory is 572 MB, reserved memory is 561 MB, peak memory is 708 MB
-OPT-1001 : Total overflow 402.84 peak overflow 2.69
+RUN-1004 : used memory is 596 MB, reserved memory is 578 MB, peak memory is 734 MB
+OPT-1001 : Total overflow 433.69 peak overflow 3.00
 OPT-1001 : Start high-fanout net optimization ...
 OPT-1001 : Update timing in global mode
 PHY-1001 : Start incremental global routing, caller is place ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 966/20251.
+PHY-1001 : Reuse net number 1484/20891.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 725272, over cnt = 2983(8%), over = 10954, worst = 26
-PHY-1001 : End global iterations;  1.163434s wall, 1.734375s user + 0.015625s system = 1.750000s CPU (150.4%)
+PHY-1002 : len = 721464, over cnt = 3027(8%), over = 11212, worst = 32
+PHY-1001 : End global iterations;  1.187443s wall, 1.734375s user + 0.046875s system = 1.781250s CPU (150.0%)
 
-PHY-1001 : Congestion index: top1 = 65.78, top5 = 55.57, top10 = 50.32, top15 = 46.98.
-PHY-1001 : End incremental global routing;  1.485633s wall, 2.062500s user + 0.015625s system = 2.078125s CPU (139.9%)
+PHY-1001 : Congestion index: top1 = 70.32, top5 = 57.04, top10 = 50.86, top15 = 47.22.
+PHY-1001 : End incremental global routing;  1.526473s wall, 2.062500s user + 0.046875s system = 2.109375s CPU (138.2%)
 
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20073 nets completely.
+TMR-2504 : Update delay of 20713 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
-TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
 TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
 TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update;  0.906483s wall, 0.890625s user + 0.015625s system = 0.906250s CPU (100.0%)
+OPT-1001 : End timing update;  0.952616s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (100.1%)
 
-OPT-1001 : 51 high-fanout net processed.
+OPT-1001 : 50 high-fanout net processed.
 PHY-3001 : Start incremental placement ...
 PHY-1001 : Populate physical database on model huagao_mipi_top.
 PHY-3001 : Initial placement ...
 PHY-3001 : eco special cells: 1 has valid locations, 0 needs to be replaced
 PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 17535 has valid locations, 332 needs to be replaced
-PHY-3001 : design contains 17952 instances, 7503 luts, 9228 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1163 with 6004 pins
-PHY-3001 : Found 1238 cells with 2 region constraints.
+PHY-3001 : eco cells: 18176 has valid locations, 336 needs to be replaced
+PHY-3001 : design contains 18597 instances, 7580 luts, 9796 seqs, 1075 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 6584 pins
+PHY-3001 : Found 1231 cells with 2 region constraints.
 PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 648311
+PHY-3001 : Initial: Len = 646398
 PHY-3001 : Run with size of 4
-PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Cell area utilization is 57%
 PHY-3001 : Analyzing congestion ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16555/20532.
+PHY-1001 : Reuse net number 16965/21177.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 741400, over cnt = 3040(8%), over = 11005, worst = 23
-PHY-1001 : End global iterations;  0.250345s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (156.0%)
+PHY-1002 : len = 736936, over cnt = 3085(8%), over = 11319, worst = 32
+PHY-1001 : End global iterations;  0.236596s wall, 0.375000s user + 0.046875s system = 0.421875s CPU (178.3%)
 
-PHY-1001 : Congestion index: top1 = 66.03, top5 = 56.05, top10 = 50.69, top15 = 47.27.
-PHY-3001 : End congestion estimation;  0.525617s wall, 0.656250s user + 0.000000s system = 0.656250s CPU (124.9%)
+PHY-1001 : Congestion index: top1 = 70.15, top5 = 57.25, top10 = 51.37, top15 = 47.64.
+PHY-3001 : End congestion estimation;  0.492914s wall, 0.609375s user + 0.046875s system = 0.656250s CPU (133.1%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 RUN-1002 : start command "start_timer -report"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 85749, tnet num: 20354, tinst num: 17952, tnode num: 116398, tedge num: 137520.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 88307, tnet num: 20999, tinst num: 18597, tnode num: 120641, tedge num: 141346.
 TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in  1.456048s wall, 1.421875s user + 0.031250s system = 1.453125s CPU (99.8%)
+RUN-1003 : finish command "start_timer -report" in  1.476353s wall, 1.468750s user + 0.015625s system = 1.484375s CPU (100.5%)
 
-RUN-1004 : used memory is 616 MB, reserved memory is 619 MB, peak memory is 710 MB
+RUN-1004 : used memory is 642 MB, reserved memory is 641 MB, peak memory is 740 MB
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20354 nets completely.
+TMR-2504 : Update delay of 20999 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
-TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
 TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
 TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  2.402078s wall, 2.343750s user + 0.062500s system = 2.406250s CPU (100.2%)
+PHY-3001 : End timing update;  2.836114s wall, 2.812500s user + 0.031250s system = 2.843750s CPU (100.3%)
 
 PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(274): len = 647207, overlap = 0.4375
-PHY-3002 : Step(275): len = 646813, overlap = 0.4375
-PHY-3002 : Step(276): len = 646562, overlap = 0.4375
-PHY-3002 : Step(277): len = 646329, overlap = 0.4375
+PHY-3002 : Step(288): len = 645449, overlap = 0.28125
+PHY-3002 : Step(289): len = 645089, overlap = 0.1875
+PHY-3002 : Step(290): len = 644945, overlap = 0.125
+PHY-3002 : Step(291): len = 644686, overlap = 0.1875
 PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 56%
+PHY-3001 : Cell area utilization is 57%
 PHY-3001 : Analyzing congestion ...
 PHY-1001 : Generate routing nets ...
 PHY-1001 : Incremental mode ON
-PHY-1001 : Reuse net number 16669/20532.
+PHY-1001 : Reuse net number 17109/21177.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 738224, over cnt = 3040(8%), over = 11020, worst = 23
-PHY-1001 : End global iterations;  0.232955s wall, 0.296875s user + 0.015625s system = 0.312500s CPU (134.1%)
+PHY-1002 : len = 735064, over cnt = 3094(8%), over = 11333, worst = 32
+PHY-1001 : End global iterations;  0.184287s wall, 0.281250s user + 0.000000s system = 0.281250s CPU (152.6%)
 
-PHY-1001 : Congestion index: top1 = 66.44, top5 = 56.30, top10 = 50.96, top15 = 47.56.
-PHY-3001 : End congestion estimation;  0.494469s wall, 0.546875s user + 0.015625s system = 0.562500s CPU (113.8%)
+PHY-1001 : Congestion index: top1 = 70.75, top5 = 57.57, top10 = 51.49, top15 = 47.80.
+PHY-3001 : End congestion estimation;  0.439402s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (120.9%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 20354 nets completely.
+TMR-2504 : Update delay of 20999 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  1.000311s wall, 1.000000s user + 0.000000s system = 1.000000s CPU (100.0%)
+PHY-3001 : End timing update;  1.327813s wall, 1.328125s user + 0.000000s system = 1.328125s CPU (100.0%)
 
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000327438
-PHY-3002 : Step(278): len = 646336, overlap = 91.7812
-PHY-3002 : Step(279): len = 646431, overlap = 91.4062
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000654876
-PHY-3002 : Step(280): len = 646360, overlap = 90.7812
-PHY-3002 : Step(281): len = 646751, overlap = 91.4375
-PHY-3001 : Final: Len = 646751, Over = 91.4375
-PHY-3001 : End incremental placement;  5.153788s wall, 5.734375s user + 0.234375s system = 5.968750s CPU (115.8%)
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000425296
+PHY-3002 : Step(292): len = 644677, overlap = 104.375
+PHY-3002 : Step(293): len = 644738, overlap = 104.812
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000850593
+PHY-3002 : Step(294): len = 644784, overlap = 105.688
+PHY-3002 : Step(295): len = 645163, overlap = 106.156
+PHY-3001 : Final: Len = 645163, Over = 106.156
+PHY-3001 : End incremental placement;  5.757935s wall, 6.187500s user + 0.156250s system = 6.343750s CPU (110.2%)
 
-OPT-1001 : Total overflow 409.66 peak overflow 2.69
-OPT-1001 : End high-fanout net optimization;  8.186217s wall, 9.406250s user + 0.265625s system = 9.671875s CPU (118.1%)
+OPT-1001 : Total overflow 440.84 peak overflow 3.00
+OPT-1001 : End high-fanout net optimization;  8.788392s wall, 9.781250s user + 0.218750s system = 10.000000s CPU (113.8%)
 
-OPT-1001 : Current memory(MB): used = 715, reserve = 709, peak = 732.
-OPT-1001 : Start global optimization ...
+OPT-1001 : Current memory(MB): used = 741, reserve = 729, peak = 759.
+OPT-1001 : Start bottleneck based optimization ...
 OPT-1001 : Start congestion update ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 16602/20532.
+PHY-1001 : Reuse net number 17031/21177.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 740224, over cnt = 2991(8%), over = 9937, worst = 20
-PHY-1002 : len = 794184, over cnt = 2008(5%), over = 4860, worst = 18
-PHY-1002 : len = 828048, over cnt = 869(2%), over = 1996, worst = 17
-PHY-1002 : len = 852104, over cnt = 293(0%), over = 560, worst = 11
-PHY-1002 : len = 861664, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations;  2.010204s wall, 2.765625s user + 0.015625s system = 2.781250s CPU (138.4%)
+PHY-1002 : len = 738344, over cnt = 3046(8%), over = 10371, worst = 32
+PHY-1002 : len = 787592, over cnt = 2141(6%), over = 5560, worst = 22
+PHY-1002 : len = 839104, over cnt = 840(2%), over = 1899, worst = 15
+PHY-1002 : len = 860952, over cnt = 225(0%), over = 430, worst = 11
+PHY-1002 : len = 868704, over cnt = 15(0%), over = 15, worst = 1
+PHY-1001 : End global iterations;  2.151436s wall, 2.843750s user + 0.015625s system = 2.859375s CPU (132.9%)
 
-PHY-1001 : Congestion index: top1 = 55.04, top5 = 49.28, top10 = 45.86, top15 = 43.68.
-OPT-1001 : End congestion update;  2.319261s wall, 3.093750s user + 0.015625s system = 3.109375s CPU (134.1%)
+PHY-1001 : Congestion index: top1 = 57.20, top5 = 50.49, top10 = 46.81, top15 = 44.58.
+OPT-1001 : End congestion update;  2.414332s wall, 3.125000s user + 0.015625s system = 3.140625s CPU (130.1%)
 
 OPT-1001 : Update timing in Manhattan mode
 TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 20354 nets completely.
+TMR-2504 : Update delay of 20999 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 3.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update;  0.814386s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (99.8%)
+OPT-1001 : End timing update;  0.861345s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.8%)
 
-OPT-0007 : Start: WNS -1018 TNS -1565 NUM_FEPS 3
-OPT-0007 : Iter 1: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 96 cells processed and 6778 slack improved
-OPT-0007 : Iter 2: improved WNS -1018 TNS -1565 NUM_FEPS 3 with 7 cells processed and 350 slack improved
-OPT-1001 : End global optimization;  3.178466s wall, 3.953125s user + 0.015625s system = 3.968750s CPU (124.9%)
+OPT-0007 : Start: WNS 121 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 122 cells processed and 17592 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 40 cells processed and 5550 slack improved
+OPT-0007 : Iter 3: improved WNS 171 TNS 0 NUM_FEPS 0 with 3 cells processed and 350 slack improved
+OPT-0007 : Iter 4: improved WNS 171 TNS 0 NUM_FEPS 0 with 2 cells processed and 650 slack improved
+OPT-1001 : End bottleneck based optimization;  3.685889s wall, 4.390625s user + 0.015625s system = 4.406250s CPU (119.5%)
 
-OPT-1001 : Current memory(MB): used = 695, reserve = 693, peak = 732.
-OPT-1001 : End physical optimization;  13.329156s wall, 15.296875s user + 0.296875s system = 15.593750s CPU (117.0%)
+OPT-1001 : Current memory(MB): used = 718, reserve = 708, peak = 759.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 17073/21182.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 869152, over cnt = 117(0%), over = 155, worst = 5
+PHY-1002 : len = 868936, over cnt = 77(0%), over = 92, worst = 4
+PHY-1002 : len = 869448, over cnt = 28(0%), over = 29, worst = 2
+PHY-1002 : len = 869560, over cnt = 17(0%), over = 17, worst = 1
+PHY-1002 : len = 870112, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.740435s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (103.4%)
+
+PHY-1001 : Congestion index: top1 = 56.85, top5 = 50.10, top10 = 46.58, top15 = 44.41.
+OPT-1001 : End congestion update;  1.011846s wall, 1.046875s user + 0.000000s system = 1.046875s CPU (103.5%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 21004 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.823754s wall, 0.812500s user + 0.000000s system = 0.812500s CPU (98.6%)
+
+OPT-0007 : Start: WNS 171 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 171 TNS 0 NUM_FEPS 0 with 22 cells processed and 7500 slack improved
+OPT-0007 : Iter 2: improved WNS 171 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.954227s wall, 1.984375s user + 0.000000s system = 1.984375s CPU (101.5%)
+
+OPT-1001 : Current memory(MB): used = 726, reserve = 713, peak = 759.
+OPT-1001 : End physical optimization;  16.200395s wall, 17.875000s user + 0.296875s system = 18.171875s CPU (112.2%)
 
 PHY-3001 : Start packing ...
 SYN-4007 : Packing 0 MUX to BLE ...
 SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
-SYN-4007 : Packing 7503 LUT to BLE ...
-SYN-4008 : Packed 7503 LUT and 3133 SEQ to BLE.
-SYN-4003 : Packing 6095 remaining SEQ's ...
-SYN-4005 : Packed 3693 SEQ with LUT/SLICE
-SYN-4006 : 969 single LUT's are left
-SYN-4006 : 2402 single SEQ's are left
-SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 9905/13636 primitive instances ...
-PHY-3001 : End packing;  1.652991s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.2%)
+SYN-4007 : Packing 7580 LUT to BLE ...
+SYN-4008 : Packed 7580 LUT and 3158 SEQ to BLE.
+SYN-4003 : Packing 6643 remaining SEQ's ...
+SYN-4005 : Packed 3910 SEQ with LUT/SLICE
+SYN-4006 : 811 single LUT's are left
+SYN-4006 : 2733 single SEQ's are left
+SYN-4011 : Packing model "huagao_mipi_top" (AL_USER_NORMAL) with 10313/15192 primitive instances ...
+PHY-3001 : End packing;  1.740255s wall, 1.734375s user + 0.000000s system = 1.734375s CPU (99.7%)
 
 PHY-1001 : Populate physical database on model huagao_mipi_top.
-RUN-1001 : There are total 6890 instances
-RUN-1001 : 3371 mslices, 3371 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 17530 nets
+RUN-1001 : There are total 7112 instances
+RUN-1001 : 3482 mslices, 3482 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18155 nets
 RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 9969 nets have 2 pins
-RUN-1001 : 5758 nets have [3 - 5] pins
-RUN-1001 : 1123 nets have [6 - 10] pins
-RUN-1001 : 308 nets have [11 - 20] pins
-RUN-1001 : 340 nets have [21 - 99] pins
+RUN-1001 : 10478 nets have 2 pins
+RUN-1001 : 5820 nets have [3 - 5] pins
+RUN-1001 : 1171 nets have [6 - 10] pins
+RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 336 nets have [21 - 99] pins
 RUN-1001 : 12 nets have 100+ pins
-PHY-3001 : design contains 6888 instances, 6742 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1163 with 3560 pins
-PHY-3001 : Found 494 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : After packing: Len = 657912, Over = 251
+PHY-3001 : design contains 7110 instances, 6964 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3890 pins
+PHY-3001 : Found 481 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : After packing: Len = 658208, Over = 310.5
 PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Cell area utilization is 76%
 PHY-3001 : Analyzing congestion ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 7593/17530.
+PHY-1001 : Reuse net number 7633/18155.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 813888, over cnt = 1952(5%), over = 3148, worst = 7
-PHY-1002 : len = 821784, over cnt = 1230(3%), over = 1767, worst = 6
-PHY-1002 : len = 830520, over cnt = 722(2%), over = 1019, worst = 6
-PHY-1002 : len = 837008, over cnt = 475(1%), over = 681, worst = 6
-PHY-1002 : len = 845584, over cnt = 109(0%), over = 150, worst = 6
-PHY-1001 : End global iterations;  1.493644s wall, 2.187500s user + 0.000000s system = 2.187500s CPU (146.5%)
+PHY-1002 : len = 812144, over cnt = 2024(5%), over = 3420, worst = 9
+PHY-1002 : len = 820920, over cnt = 1386(3%), over = 2044, worst = 7
+PHY-1002 : len = 830728, over cnt = 842(2%), over = 1233, worst = 6
+PHY-1002 : len = 843928, over cnt = 332(0%), over = 466, worst = 6
+PHY-1002 : len = 852432, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.661414s wall, 2.250000s user + 0.000000s system = 2.250000s CPU (135.4%)
 
-PHY-1001 : Congestion index: top1 = 57.65, top5 = 50.04, top10 = 45.96, top15 = 43.38.
-PHY-3001 : End congestion estimation;  1.895549s wall, 2.578125s user + 0.000000s system = 2.578125s CPU (136.0%)
+PHY-1001 : Congestion index: top1 = 59.09, top5 = 50.37, top10 = 46.64, top15 = 44.09.
+PHY-3001 : End congestion estimation;  2.063662s wall, 2.656250s user + 0.000000s system = 2.656250s CPU (128.7%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 RUN-1002 : start command "start_timer -report"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6888, tnode num: 96233, tedge num: 123821.
-TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75983, tnet num: 17977, tinst num: 7110, tnode num: 99613, tedge num: 127314.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in  1.663680s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (100.5%)
+RUN-1003 : finish command "start_timer -report" in  1.666912s wall, 1.656250s user + 0.015625s system = 1.671875s CPU (100.3%)
 
-RUN-1004 : used memory is 608 MB, reserved memory is 603 MB, peak memory is 732 MB
+RUN-1004 : used memory is 639 MB, reserved memory is 634 MB, peak memory is 759 MB
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17352 nets completely.
+TMR-2504 : Update delay of 17977 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
-TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {u_pixel_cdc/multipy_xy[*]} ] -to [ get_regs {u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]} ].
-TMR-6513 Similar messages will be suppressed.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  2.524608s wall, 2.500000s user + 0.031250s system = 2.531250s CPU (100.3%)
+PHY-3001 : End timing update;  2.574225s wall, 2.562500s user + 0.015625s system = 2.578125s CPU (100.2%)
 
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.75783e-05
-PHY-3002 : Step(282): len = 645888, overlap = 249.75
-PHY-3002 : Step(283): len = 639979, overlap = 245.5
-PHY-3002 : Step(284): len = 636462, overlap = 252.5
-PHY-3002 : Step(285): len = 633658, overlap = 252.5
-PHY-3002 : Step(286): len = 630887, overlap = 260.75
-PHY-3002 : Step(287): len = 627447, overlap = 264
-PHY-3002 : Step(288): len = 624149, overlap = 268
-PHY-3002 : Step(289): len = 621609, overlap = 270.5
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 9.51567e-05
-PHY-3002 : Step(290): len = 624770, overlap = 262
-PHY-3002 : Step(291): len = 629314, overlap = 250.75
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000190313
-PHY-3002 : Step(292): len = 633723, overlap = 244
-PHY-3002 : Step(293): len = 645927, overlap = 215.75
-PHY-3002 : Step(294): len = 648474, overlap = 213.5
-PHY-3002 : Step(295): len = 649771, overlap = 210.25
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 4.15623e-05
+PHY-3002 : Step(296): len = 644818, overlap = 308.5
+PHY-3002 : Step(297): len = 638418, overlap = 308.25
+PHY-3002 : Step(298): len = 634474, overlap = 314.25
+PHY-3002 : Step(299): len = 632259, overlap = 317
+PHY-3002 : Step(300): len = 630446, overlap = 318.25
+PHY-3002 : Step(301): len = 628888, overlap = 310.25
+PHY-3002 : Step(302): len = 627240, overlap = 304.5
+PHY-3002 : Step(303): len = 625948, overlap = 300
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 8.31246e-05
+PHY-3002 : Step(304): len = 630038, overlap = 294.25
+PHY-3002 : Step(305): len = 633929, overlap = 286.75
+PHY-3002 : Step(306): len = 633553, overlap = 288.5
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000166249
+PHY-3002 : Step(307): len = 644507, overlap = 273.25
+PHY-3002 : Step(308): len = 652926, overlap = 259
+PHY-3002 : Step(309): len = 651075, overlap = 265.75
+PHY-3001 : :::3::: Try harder cell spreading with beta_ = 0.000332498
+PHY-3002 : Step(310): len = 659753, overlap = 252.75
+PHY-3002 : Step(311): len = 674197, overlap = 230
+PHY-3002 : Step(312): len = 672323, overlap = 229.5
+PHY-3002 : Step(313): len = 670444, overlap = 225.25
+PHY-3002 : Step(314): len = 670963, overlap = 218.75
 PHY-3001 : Legalization ...
-PHY-3001 : End legalization;  0.398554s wall, 0.328125s user + 0.453125s system = 0.781250s CPU (196.0%)
+PHY-3001 : End legalization;  0.377444s wall, 0.421875s user + 0.546875s system = 0.968750s CPU (256.7%)
 
-PHY-3001 : Trial Legalized: Len = 725964
+PHY-3001 : Trial Legalized: Len = 754658
 PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 73%
+PHY-3001 : Cell area utilization is 76%
 PHY-3001 : Analyzing congestion ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 759/17530.
+PHY-1001 : Reuse net number 690/18155.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 840944, over cnt = 2673(7%), over = 4537, worst = 8
-PHY-1002 : len = 859824, over cnt = 1524(4%), over = 2187, worst = 7
-PHY-1002 : len = 878400, over cnt = 481(1%), over = 720, worst = 7
-PHY-1002 : len = 886200, over cnt = 114(0%), over = 174, worst = 7
-PHY-1002 : len = 888632, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations;  2.310098s wall, 3.468750s user + 0.031250s system = 3.500000s CPU (151.5%)
+PHY-1002 : len = 872960, over cnt = 2762(7%), over = 4649, worst = 6
+PHY-1002 : len = 890384, over cnt = 1683(4%), over = 2460, worst = 6
+PHY-1002 : len = 911080, over cnt = 619(1%), over = 883, worst = 6
+PHY-1002 : len = 920896, over cnt = 198(0%), over = 280, worst = 4
+PHY-1002 : len = 925576, over cnt = 6(0%), over = 6, worst = 1
+PHY-1001 : End global iterations;  2.382388s wall, 3.484375s user + 0.015625s system = 3.500000s CPU (146.9%)
 
-PHY-1001 : Congestion index: top1 = 53.23, top5 = 48.36, top10 = 45.74, top15 = 43.97.
-PHY-3001 : End congestion estimation;  2.768120s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (142.8%)
+PHY-1001 : Congestion index: top1 = 56.08, top5 = 50.39, top10 = 47.39, top15 = 45.29.
+PHY-3001 : End congestion estimation;  2.843501s wall, 3.921875s user + 0.031250s system = 3.953125s CPU (139.0%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17352 nets completely.
+TMR-2504 : Update delay of 17977 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  0.857966s wall, 0.843750s user + 0.000000s system = 0.843750s CPU (98.3%)
+PHY-3001 : End timing update;  1.050007s wall, 1.015625s user + 0.031250s system = 1.046875s CPU (99.7%)
 
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000160038
-PHY-3002 : Step(296): len = 699842, overlap = 38.5
-PHY-3002 : Step(297): len = 685178, overlap = 66.25
-PHY-3002 : Step(298): len = 673051, overlap = 91.75
-PHY-3002 : Step(299): len = 666043, overlap = 117.25
-PHY-3002 : Step(300): len = 661142, overlap = 139.5
-PHY-3002 : Step(301): len = 658978, overlap = 146.25
-PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000320077
-PHY-3002 : Step(302): len = 665134, overlap = 141.75
-PHY-3002 : Step(303): len = 670968, overlap = 139.75
-PHY-3002 : Step(304): len = 671541, overlap = 147.25
-PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.00063987
-PHY-3002 : Step(305): len = 676138, overlap = 148.5
-PHY-3002 : Step(306): len = 686491, overlap = 145
-PHY-3002 : Step(307): len = 691560, overlap = 146.25
-PHY-3002 : Step(308): len = 692892, overlap = 151.75
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000155905
+PHY-3002 : Step(315): len = 726001, overlap = 47
+PHY-3002 : Step(316): len = 708939, overlap = 79
+PHY-3002 : Step(317): len = 693934, overlap = 107
+PHY-3002 : Step(318): len = 682022, overlap = 134.25
+PHY-3002 : Step(319): len = 675303, overlap = 153.75
+PHY-3002 : Step(320): len = 670910, overlap = 166.75
+PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000311809
+PHY-3002 : Step(321): len = 675899, overlap = 161
+PHY-3002 : Step(322): len = 680411, overlap = 157.25
+PHY-3002 : Step(323): len = 680703, overlap = 159
+PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000623619
+PHY-3002 : Step(324): len = 685248, overlap = 162
+PHY-3002 : Step(325): len = 694537, overlap = 157.25
 PHY-3001 : Legalization ...
-PHY-3001 : End legalization;  0.035092s wall, 0.031250s user + 0.000000s system = 0.031250s CPU (89.1%)
+PHY-3001 : End legalization;  0.036878s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (127.1%)
 
-PHY-3001 : Legalized: Len = 721430, Over = 0
-PHY-3001 : Spreading special nets. 418 overflows in 2952 tiles.
-PHY-3001 : End spreading;  0.110096s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (99.3%)
+PHY-3001 : Legalized: Len = 726660, Over = 0
+PHY-3001 : Spreading special nets. 535 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.122626s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (101.9%)
 
-PHY-3001 : 612 instances has been re-located, deltaX = 269, deltaY = 342, maxDist = 3.
-PHY-3001 : Final: Len = 732202, Over = 0
+PHY-3001 : 792 instances has been re-located, deltaX = 311, deltaY = 496, maxDist = 3.
+PHY-3001 : Final: Len = 740432, Over = 0
 PHY-3001 : BANK 2 DIFFRESISTOR:100 VOD:350M VCM:1.2
 PHY-3001 : BANK 5 DIFFRESISTOR:100 VOD:350M VCM:1.2
 PHY-3001 : BANK 6 DIFFRESISTOR:100 VOD:350M VCM:1.2
 OPT-1001 : Start physical optimization ...
 RUN-1002 : start command "start_timer -report"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73751, tnet num: 17352, tinst num: 6891, tnode num: 96233, tedge num: 123821.
-TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 75983, tnet num: 17977, tinst num: 7113, tnode num: 99613, tedge num: 127314.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in  1.874554s wall, 1.859375s user + 0.015625s system = 1.875000s CPU (100.0%)
+RUN-1003 : finish command "start_timer -report" in  1.912544s wall, 1.906250s user + 0.000000s system = 1.906250s CPU (99.7%)
 
-RUN-1004 : used memory is 612 MB, reserved memory is 607 MB, peak memory is 732 MB
+RUN-1004 : used memory is 659 MB, reserved memory is 669 MB, peak memory is 759 MB
 OPT-1001 : Total overflow 0.00 peak overflow 0.00
 OPT-1001 : Start high-fanout net optimization ...
 OPT-1001 : Update timing in global mode
 PHY-1001 : Start incremental global routing, caller is place ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 3456/17530.
+PHY-1001 : Reuse net number 4601/18155.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 859832, over cnt = 2564(7%), over = 4193, worst = 8
-PHY-1002 : len = 875568, over cnt = 1522(4%), over = 2156, worst = 6
-PHY-1002 : len = 887848, over cnt = 801(2%), over = 1128, worst = 6
-PHY-1002 : len = 899448, over cnt = 263(0%), over = 372, worst = 5
-PHY-1002 : len = 905456, over cnt = 12(0%), over = 15, worst = 2
-PHY-1001 : End global iterations;  1.903423s wall, 2.906250s user + 0.031250s system = 2.937500s CPU (154.3%)
+PHY-1002 : len = 875920, over cnt = 2595(7%), over = 4177, worst = 7
+PHY-1002 : len = 892216, over cnt = 1474(4%), over = 2070, worst = 7
+PHY-1002 : len = 907184, over cnt = 609(1%), over = 815, worst = 7
+PHY-1002 : len = 916400, over cnt = 215(0%), over = 283, worst = 6
+PHY-1002 : len = 920760, over cnt = 2(0%), over = 2, worst = 1
+PHY-1001 : End global iterations;  2.048733s wall, 2.859375s user + 0.000000s system = 2.859375s CPU (139.6%)
 
-PHY-1001 : Congestion index: top1 = 53.38, top5 = 48.42, top10 = 45.65, top15 = 43.88.
-PHY-1001 : End incremental global routing;  2.274139s wall, 3.281250s user + 0.046875s system = 3.328125s CPU (146.3%)
+PHY-1001 : Congestion index: top1 = 54.18, top5 = 48.76, top10 = 46.25, top15 = 44.51.
+PHY-1001 : End incremental global routing;  2.414312s wall, 3.218750s user + 0.000000s system = 3.218750s CPU (133.3%)
 
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17352 nets completely.
+TMR-2504 : Update delay of 17977 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {a_pclk_rstn} ].
+TMR-6513 WARNING: No path found for constraint(s):  set_false_path -from [ get_regs {clkubus_rstn} ] -to [ get_nets {b_pclk_rstn} ].
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update;  0.862982s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.6%)
+OPT-1001 : End timing update;  0.934980s wall, 0.921875s user + 0.015625s system = 0.937500s CPU (100.3%)
 
-OPT-1001 : 5 high-fanout net processed.
+OPT-1001 : 6 high-fanout net processed.
 PHY-3001 : Start incremental placement ...
 PHY-1001 : Populate physical database on model huagao_mipi_top.
 PHY-3001 : Initial placement ...
 PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
 PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6798 has valid locations, 27 needs to be replaced
-PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
-PHY-3001 : Found 497 cells with 2 region constraints.
+PHY-3001 : eco cells: 7019 has valid locations, 30 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
 PHY-3001 : Global placement ...
-PHY-3001 : Initial: Len = 735387
+PHY-3001 : Initial: Len = 744753
 PHY-3001 : Run with size of 4
-PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Cell area utilization is 76%
 PHY-3001 : Analyzing congestion ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 15975/17552.
+PHY-1001 : Reuse net number 16430/18187.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 909520, over cnt = 90(0%), over = 105, worst = 5
-PHY-1002 : len = 909704, over cnt = 43(0%), over = 44, worst = 2
-PHY-1002 : len = 910104, over cnt = 19(0%), over = 19, worst = 1
-PHY-1002 : len = 910456, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations;  0.622373s wall, 0.656250s user + 0.015625s system = 0.671875s CPU (108.0%)
+PHY-1002 : len = 926080, over cnt = 136(0%), over = 159, worst = 4
+PHY-1002 : len = 926352, over cnt = 49(0%), over = 50, worst = 2
+PHY-1002 : len = 926744, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 926864, over cnt = 3(0%), over = 3, worst = 1
+PHY-1002 : len = 926928, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  1.030650s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (83.4%)
 
-PHY-1001 : Congestion index: top1 = 53.36, top5 = 48.44, top10 = 45.71, top15 = 43.96.
-PHY-3001 : End congestion estimation;  0.931666s wall, 0.968750s user + 0.015625s system = 0.984375s CPU (105.7%)
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.91, top10 = 46.39, top15 = 44.65.
+PHY-3001 : End congestion estimation;  1.349627s wall, 1.171875s user + 0.000000s system = 1.171875s CPU (86.8%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 RUN-1002 : start command "start_timer -report"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
-TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76272, tnet num: 18009, tinst num: 7137, tnode num: 99971, tedge num: 127701.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in  1.842906s wall, 1.812500s user + 0.031250s system = 1.843750s CPU (100.0%)
+RUN-1003 : finish command "start_timer -report" in  1.886720s wall, 1.890625s user + 0.000000s system = 1.890625s CPU (100.2%)
 
-RUN-1004 : used memory is 661 MB, reserved memory is 665 MB, peak memory is 732 MB
+RUN-1004 : used memory is 685 MB, reserved memory is 685 MB, peak memory is 759 MB
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17374 nets completely.
+TMR-2504 : Update delay of 18009 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
+TMR-6513 Similar messages will be suppressed.
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  2.732448s wall, 2.671875s user + 0.062500s system = 2.734375s CPU (100.1%)
+PHY-3001 : End timing update;  2.797503s wall, 2.796875s user + 0.000000s system = 2.796875s CPU (100.0%)
 
 PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
-PHY-3002 : Step(309): len = 734474, overlap = 0
-PHY-3002 : Step(310): len = 734081, overlap = 0
+PHY-3002 : Step(326): len = 743867, overlap = 0
+PHY-3002 : Step(327): len = 743305, overlap = 0
 PHY-3001 : Run with size of 2
-PHY-3001 : Cell area utilization is 74%
+PHY-3001 : Cell area utilization is 76%
 PHY-3001 : Analyzing congestion ...
 PHY-1001 : Generate routing nets ...
 PHY-1001 : Incremental mode ON
-PHY-1001 : Reuse net number 15963/17552.
+PHY-1001 : Reuse net number 16418/18187.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 908160, over cnt = 75(0%), over = 95, worst = 4
-PHY-1002 : len = 908296, over cnt = 39(0%), over = 42, worst = 2
-PHY-1002 : len = 908824, over cnt = 4(0%), over = 4, worst = 1
-PHY-1002 : len = 908920, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations;  0.653769s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (112.3%)
+PHY-1002 : len = 924720, over cnt = 82(0%), over = 103, worst = 5
+PHY-1002 : len = 924960, over cnt = 35(0%), over = 37, worst = 2
+PHY-1002 : len = 925400, over cnt = 6(0%), over = 6, worst = 1
+PHY-1002 : len = 925448, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.595471s wall, 0.625000s user + 0.000000s system = 0.625000s CPU (105.0%)
 
-PHY-1001 : Congestion index: top1 = 53.30, top5 = 48.44, top10 = 45.71, top15 = 43.95.
-PHY-3001 : End congestion estimation;  0.987356s wall, 1.062500s user + 0.000000s system = 1.062500s CPU (107.6%)
+PHY-1001 : Congestion index: top1 = 54.44, top5 = 48.92, top10 = 46.35, top15 = 44.58.
+PHY-3001 : End congestion estimation;  0.911954s wall, 0.937500s user + 0.000000s system = 0.937500s CPU (102.8%)
 
 PHY-3001 : Update density targets...
 PHY-3001 : Update congestion history...
 PHY-3001 : Update timing in global mode ...
 TMR-2503 : Start to update net delay, extr mode = 5.
-TMR-2504 : Update delay of 17374 nets completely.
+TMR-2504 : Update delay of 18009 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 5.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-PHY-3001 : End timing update;  0.862313s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (99.7%)
+PHY-3001 : End timing update;  0.887492s wall, 0.890625s user + 0.000000s system = 0.890625s CPU (100.4%)
 
-PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000333503
-PHY-3002 : Step(311): len = 734109, overlap = 1.5
-PHY-3002 : Step(312): len = 734482, overlap = 1.5
+PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000923339
+PHY-3002 : Step(328): len = 743215, overlap = 2.75
+PHY-3002 : Step(329): len = 743191, overlap = 2.25
 PHY-3001 : Legalization ...
-PHY-3001 : End legalization;  0.005911s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
+PHY-3001 : End legalization;  0.005560s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
 
-PHY-3001 : Legalized: Len = 734542, Over = 0
-PHY-3001 : Spreading special nets. 9 overflows in 2952 tiles.
-PHY-3001 : End spreading;  0.059822s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (78.4%)
+PHY-3001 : Legalized: Len = 743458, Over = 0
+PHY-3001 : Spreading special nets. 3 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062842s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.5%)
 
-PHY-3001 : 14 instances has been re-located, deltaX = 13, deltaY = 3, maxDist = 2.
-PHY-3001 : Final: Len = 734724, Over = 0
-PHY-3001 : End incremental placement;  5.993245s wall, 6.046875s user + 0.171875s system = 6.218750s CPU (103.8%)
+PHY-3001 : 4 instances has been re-located, deltaX = 3, deltaY = 1, maxDist = 1.
+PHY-3001 : Final: Len = 743452, Over = 0
+PHY-3001 : End incremental placement;  6.439997s wall, 6.546875s user + 0.109375s system = 6.656250s CPU (103.4%)
 
 OPT-1001 : Total overflow 0.00 peak overflow 0.00
-OPT-1001 : End high-fanout net optimization;  9.612886s wall, 10.796875s user + 0.218750s system = 11.015625s CPU (114.6%)
+OPT-1001 : End high-fanout net optimization;  10.287435s wall, 11.187500s user + 0.125000s system = 11.312500s CPU (110.0%)
 
-OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 742.
-OPT-1001 : Start path based optimization ...
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start bottleneck based optimization ...
 OPT-1001 : Start congestion update ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 15926/17552.
+PHY-1001 : Reuse net number 16399/18187.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 909344, over cnt = 69(0%), over = 91, worst = 7
-PHY-1002 : len = 909360, over cnt = 28(0%), over = 28, worst = 1
-PHY-1002 : len = 909488, over cnt = 18(0%), over = 18, worst = 1
-PHY-1002 : len = 909728, over cnt = 2(0%), over = 2, worst = 1
-PHY-1002 : len = 909752, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations;  0.805598s wall, 0.859375s user + 0.000000s system = 0.859375s CPU (106.7%)
+PHY-1002 : len = 925280, over cnt = 75(0%), over = 98, worst = 6
+PHY-1002 : len = 925352, over cnt = 34(0%), over = 38, worst = 3
+PHY-1002 : len = 925488, over cnt = 7(0%), over = 7, worst = 1
+PHY-1002 : len = 925616, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.595918s wall, 0.640625s user + 0.000000s system = 0.640625s CPU (107.5%)
 
-PHY-1001 : Congestion index: top1 = 53.19, top5 = 48.37, top10 = 45.65, top15 = 43.90.
-OPT-1001 : End congestion update;  1.116446s wall, 1.156250s user + 0.000000s system = 1.156250s CPU (103.6%)
+PHY-1001 : Congestion index: top1 = 54.22, top5 = 48.82, top10 = 46.31, top15 = 44.55.
+OPT-1001 : End congestion update;  0.906222s wall, 0.953125s user + 0.000000s system = 0.953125s CPU (105.2%)
 
 OPT-1001 : Update timing in Manhattan mode
 TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17374 nets completely.
+TMR-2504 : Update delay of 18009 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 3.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update;  0.721944s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.6%)
+OPT-1001 : End timing update;  0.751194s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.8%)
 
-OPT-0007 : Start: WNS -1040 TNS -1754 NUM_FEPS 3
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
 PHY-3001 : Start incremental legalization ...
 PHY-1001 : Populate physical database on model huagao_mipi_top.
 PHY-3001 : Initial placement ...
 PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
 PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
-PHY-3001 : eco cells: 6825 has valid locations, 0 needs to be replaced
-PHY-3001 : design contains 6913 instances, 6764 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
-PHY-3001 : Huge net sys_initial_done_dup_1163 with 3639 pins
-PHY-3001 : Found 497 cells with 2 region constraints.
-PHY-3001 : Cell area utilization is 74%
-PHY-3001 : Initial: Len = 739128, Over = 0
-PHY-3001 : Spreading special nets. 19 overflows in 2952 tiles.
-PHY-3001 : End spreading;  0.063330s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (98.7%)
+PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 747310, Over = 0
+PHY-3001 : Spreading special nets. 23 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.070216s wall, 0.078125s user + 0.000000s system = 0.078125s CPU (111.3%)
 
-PHY-3001 : 29 instances has been re-located, deltaX = 25, deltaY = 15, maxDist = 3.
-PHY-3001 : Final: Len = 739360, Over = 0
-PHY-3001 : End incremental legalization;  0.392123s wall, 0.375000s user + 0.031250s system = 0.406250s CPU (103.6%)
+PHY-3001 : 32 instances has been re-located, deltaX = 22, deltaY = 14, maxDist = 2.
+PHY-3001 : Final: Len = 747890, Over = 0
+PHY-3001 : End incremental legalization;  0.441613s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (99.1%)
 
-OPT-0007 : Iter 1: improved WNS -990 TNS -1625 NUM_FEPS 2 with 35 cells processed and 11554 slack improved
-OPT-0007 : Iter 2: improved WNS -990 TNS -1625 NUM_FEPS 2 with 0 cells processed and 0 slack improved
-OPT-1001 : End path based optimization;  2.369147s wall, 2.390625s user + 0.031250s system = 2.421875s CPU (102.2%)
+OPT-0007 : Iter 1: improved WNS 121 TNS 0 NUM_FEPS 0 with 48 cells processed and 14898 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 749174, Over = 0
+PHY-3001 : Spreading special nets. 16 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062913s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.3%)
+
+PHY-3001 : 21 instances has been re-located, deltaX = 8, deltaY = 19, maxDist = 3.
+PHY-3001 : Final: Len = 749554, Over = 0
+PHY-3001 : End incremental legalization;  0.438820s wall, 0.546875s user + 0.000000s system = 0.546875s CPU (124.6%)
+
+OPT-0007 : Iter 2: improved WNS 121 TNS 0 NUM_FEPS 0 with 30 cells processed and 4936 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7049 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7137 instances, 6988 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3956 pins
+PHY-3001 : Found 487 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 749714, Over = 0
+PHY-3001 : Spreading special nets. 11 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.064612s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (96.7%)
+
+PHY-3001 : 13 instances has been re-located, deltaX = 4, deltaY = 11, maxDist = 3.
+PHY-3001 : Final: Len = 750026, Over = 0
+PHY-3001 : End incremental legalization;  0.396699s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.5%)
+
+OPT-0007 : Iter 3: improved WNS 21 TNS 0 NUM_FEPS 0 with 13 cells processed and 800 slack improved
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750160, Over = 0
+PHY-3001 : Spreading special nets. 4 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.062460s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (100.1%)
+
+PHY-3001 : 6 instances has been re-located, deltaX = 4, deltaY = 8, maxDist = 3.
+PHY-3001 : Final: Len = 750268, Over = 0
+PHY-3001 : End incremental legalization;  0.395010s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (122.6%)
+
+OPT-0007 : Iter 4: improved WNS 21 TNS 0 NUM_FEPS 0 with 3 cells processed and 571 slack improved
+OPT-1001 : End bottleneck based optimization;  3.925253s wall, 4.437500s user + 0.000000s system = 4.437500s CPU (113.1%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16033/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 932256, over cnt = 182(0%), over = 245, worst = 5
+PHY-1002 : len = 932488, over cnt = 90(0%), over = 102, worst = 4
+PHY-1002 : len = 933096, over cnt = 43(0%), over = 46, worst = 2
+PHY-1002 : len = 933736, over cnt = 4(0%), over = 4, worst = 1
+PHY-1002 : len = 933800, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.865332s wall, 0.921875s user + 0.000000s system = 0.921875s CPU (106.5%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.78, top10 = 46.37, top15 = 44.62.
+OPT-1001 : End congestion update;  1.186710s wall, 1.250000s user + 0.000000s system = 1.250000s CPU (105.3%)
 
-OPT-1001 : Current memory(MB): used = 736, reserve = 736, peak = 742.
 OPT-1001 : Update timing in Manhattan mode
 TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17374 nets completely.
+TMR-2504 : Update delay of 18010 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 3.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update;  0.726593s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (101.1%)
+OPT-1001 : End timing update;  0.765806s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (100.0%)
+
+OPT-0007 : Start: WNS 21 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750488, Over = 0
+PHY-3001 : Spreading special nets. 10 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.063977s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (97.7%)
+
+PHY-3001 : 11 instances has been re-located, deltaX = 4, deltaY = 9, maxDist = 3.
+PHY-3001 : Final: Len = 750544, Over = 0
+PHY-3001 : End incremental legalization;  0.397794s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (98.2%)
+
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 15 cells processed and 1500 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  2.477193s wall, 2.546875s user + 0.000000s system = 2.546875s CPU (102.8%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.744515s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.7%)
 
 OPT-1001 : Start pin optimization...
 OPT-1001 : skip pin optimization...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
-PHY-1001 : Reuse net number 15842/17552.
+PHY-1001 : Reuse net number 16404/18189.
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 913768, over cnt = 81(0%), over = 92, worst = 4
-PHY-1002 : len = 913880, over cnt = 38(0%), over = 40, worst = 2
-PHY-1002 : len = 914048, over cnt = 11(0%), over = 11, worst = 1
-PHY-1002 : len = 914240, over cnt = 1(0%), over = 1, worst = 1
-PHY-1002 : len = 914256, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations;  0.816002s wall, 0.875000s user + 0.015625s system = 0.890625s CPU (109.1%)
+PHY-1002 : len = 933968, over cnt = 17(0%), over = 20, worst = 2
+PHY-1002 : len = 933984, over cnt = 5(0%), over = 6, worst = 2
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.430153s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (98.1%)
 
-PHY-1001 : Congestion index: top1 = 53.56, top5 = 48.50, top10 = 45.71, top15 = 43.94.
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
 OPT-1001 : Update timing in Manhattan mode
 TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17374 nets completely.
+TMR-2504 : Update delay of 18010 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 3.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
-OPT-1001 : End timing update;  0.719422s wall, 0.718750s user + 0.000000s system = 0.718750s CPU (99.9%)
+OPT-1001 : End timing update;  0.746601s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (100.5%)
 
 RUN-1001 : QoR Analysis:
-OPT-0007 :   WNS -1040 TNS -1725 NUM_FEPS 2
-RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.103448
+OPT-0007 :   WNS 71 TNS 0 NUM_FEPS 0
+RUN-1001 :   No local congestion issue, and most congested 1% tile average routing util is 53.310345
 RUN-1001 :   Top critical paths
-RUN-1001 :       #1 path slack -1040ps with logic level 2 
-RUN-1001 :   0 HFN exist on timing critical paths out of 17552 nets
-RUN-1001 :   0 long nets exist on timing critical paths out of 17552 nets
-OPT-1001 : End physical optimization;  16.807141s wall, 18.046875s user + 0.281250s system = 18.328125s CPU (109.0%)
+RUN-1001 :       #1 path slack 71ps with logic level 1 
+RUN-1001 :   extra opt step will be enabled to improve QoR
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750544, Over = 0
+PHY-3001 : End spreading;  0.060422s wall, 0.046875s user + 0.000000s system = 0.046875s CPU (77.6%)
 
-RUN-1003 : finish command "place" in  59.234187s wall, 88.281250s user + 5.921875s system = 94.203125s CPU (159.0%)
+PHY-3001 : Final: Len = 750544, Over = 0
+PHY-3001 : End incremental legalization;  0.393231s wall, 0.375000s user + 0.000000s system = 0.375000s CPU (95.4%)
 
-RUN-1004 : used memory is 604 MB, reserved memory is 617 MB, peak memory is 742 MB
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.745243s wall, 0.734375s user + 0.000000s system = 0.734375s CPU (98.5%)
+
+OPT-1001 : Start path based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16457/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.130621s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (107.7%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
+OPT-1001 : End congestion update;  0.445948s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (98.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.739271s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (101.5%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+PHY-3001 : Start incremental legalization ...
+PHY-1001 : Populate physical database on model huagao_mipi_top.
+PHY-3001 : Initial placement ...
+PHY-3001 : eco special cells: 4 has valid locations, 0 needs to be replaced
+PHY-3001 : eco pad cells: 75 has valid locations, 0 needs to be replaced
+PHY-3001 : eco cells: 7052 has valid locations, 0 needs to be replaced
+PHY-3001 : design contains 7140 instances, 6991 slices, 222 macros(1075 instances: 704 mslices 371 lslices)
+PHY-3001 : Huge net sys_initial_done_dup_1163 with 3957 pins
+PHY-3001 : Found 489 cells with 2 region constraints.
+PHY-3001 : Cell area utilization is 76%
+PHY-3001 : Initial: Len = 750502, Over = 0
+PHY-3001 : Spreading special nets. 2 overflows in 2952 tiles.
+PHY-3001 : End spreading;  0.061781s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (101.2%)
+
+PHY-3001 : 2 instances has been re-located, deltaX = 1, deltaY = 2, maxDist = 2.
+PHY-3001 : Final: Len = 750544, Over = 0
+PHY-3001 : End incremental legalization;  0.390925s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (123.9%)
+
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 2 cells processed and 150 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End path based optimization;  1.698525s wall, 1.781250s user + 0.000000s system = 1.781250s CPU (104.9%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start bottleneck based optimization ...
+OPT-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16457/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.135864s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (103.5%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
+OPT-1001 : End congestion update;  0.479069s wall, 0.484375s user + 0.000000s system = 0.484375s CPU (101.1%)
+
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.770251s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.4%)
+
+OPT-0007 : Start: WNS 71 TNS 0 NUM_FEPS 0
+OPT-0007 : Iter 1: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-0007 : Iter 2: improved WNS 71 TNS 0 NUM_FEPS 0 with 0 cells processed and 0 slack improved
+OPT-1001 : End bottleneck based optimization;  1.412098s wall, 1.421875s user + 0.000000s system = 1.421875s CPU (100.7%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.756289s wall, 0.750000s user + 0.000000s system = 0.750000s CPU (99.2%)
+
+OPT-1001 : Start pin optimization...
+OPT-1001 : skip pin optimization...
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : Start congestion recovery ...
+RUN-1002 : start command "set_param place ofv 80"
+OPT-1001 : Update timing in Manhattan mode
+TMR-2503 : Start to update net delay, extr mode = 3.
+TMR-2504 : Update delay of 18010 nets completely.
+TMR-2502 : Annotate delay completely, extr mode = 3.
+TMR-3501 : Forward propagation: start to calculate arrival time...
+TMR-3502 : Backward propagation: start to calculate required time...
+TMR-3503 : Timing propagation completes.
+OPT-1001 : End timing update;  0.770803s wall, 0.765625s user + 0.000000s system = 0.765625s CPU (99.3%)
+
+RUN-1001 : Start congestion update ...
+RUN-1001 : Generating global routing grids ...
+PHY-1001 : Generate routing nets ...
+PHY-1001 : Reuse net number 16457/18189.
+PHY-1001 : Global iterations in 8 thread ...
+PHY-1002 : len = 934072, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  0.132917s wall, 0.125000s user + 0.000000s system = 0.125000s CPU (94.0%)
+
+PHY-1001 : Congestion index: top1 = 53.73, top5 = 48.76, top10 = 46.36, top15 = 44.61.
+RUN-1001 : End congestion update;  0.453021s wall, 0.453125s user + 0.000000s system = 0.453125s CPU (100.0%)
+ 
+RUN-1001 : design has 41 columns and 72 rows with 0 high-util (over 100 percentage) tiles versus total tile num 2952
+OPT-1001 : End congestion recovery;  1.227344s wall, 1.234375s user + 0.000000s system = 1.234375s CPU (100.6%)
+
+OPT-1001 : Current memory(MB): used = 767, reserve = 761, peak = 771.
+OPT-1001 : End physical optimization;  27.483302s wall, 29.062500s user + 0.140625s system = 29.203125s CPU (106.3%)
+
+RUN-1003 : finish command "place" in  73.177550s wall, 102.531250s user + 6.625000s system = 109.156250s CPU (149.2%)
+
+RUN-1004 : used memory is 659 MB, reserved memory is 660 MB, peak memory is 771 MB
 RUN-1002 : start command "export_db hg_anlogic_place.db"
 RUN-1001 : Exported /
 RUN-1001 : Exported flow parameters
@@ -1310,9 +1619,9 @@ RUN-1001 : Exported violations
 RUN-1001 : Exported timing constraints
 RUN-1001 : Exported IO constraints
 RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.701880s wall, 2.968750s user + 0.015625s system = 2.984375s CPU (175.4%)
+RUN-1003 : finish command "export_db hg_anlogic_place.db" in  1.736455s wall, 3.000000s user + 0.000000s system = 3.000000s CPU (172.8%)
 
-RUN-1004 : used memory is 605 MB, reserved memory is 618 MB, peak memory is 742 MB
+RUN-1004 : used memory is 659 MB, reserved memory is 661 MB, peak memory is 771 MB
 RUN-1002 : start command "route"
 RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
 RUN-1001 : Print Global Property
@@ -1337,30 +1646,30 @@ RUN-1001 :     priority     |   timing   |      timing      |
 RUN-1001 :     swap_pin     |     on     |        on        |        
 RUN-1001 : -------------------------------------------------------
 PHY-1001 : Route runs in 8 thread(s)
-RUN-1001 : There are total 6915 instances
-RUN-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
-RUN-1001 : There are total 17552 nets
+RUN-1001 : There are total 7142 instances
+RUN-1001 : 3487 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1001 : There are total 18189 nets
 RUN-6004 WARNING: There are 20 nets with only 1 pin.
-RUN-1001 : 9969 nets have 2 pins
-RUN-1001 : 5757 nets have [3 - 5] pins
-RUN-1001 : 1125 nets have [6 - 10] pins
-RUN-1001 : 318 nets have [11 - 20] pins
+RUN-1001 : 10477 nets have 2 pins
+RUN-1001 : 5822 nets have [3 - 5] pins
+RUN-1001 : 1180 nets have [6 - 10] pins
+RUN-1001 : 327 nets have [11 - 20] pins
 RUN-1001 : 355 nets have [21 - 99] pins
 RUN-1001 : 8 nets have 100+ pins
 RUN-1002 : start command "start_timer -report"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
-TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76296, tnet num: 18011, tinst num: 7140, tnode num: 100004, tedge num: 127731.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -report" in  1.725273s wall, 1.718750s user + 0.000000s system = 1.718750s CPU (99.6%)
+RUN-1003 : finish command "start_timer -report" in  1.669688s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (99.2%)
 
-RUN-1004 : used memory is 601 MB, reserved memory is 611 MB, peak memory is 742 MB
-PHY-1001 : 3380 mslices, 3384 lslices, 75 pads, 58 brams, 3 dsps
+RUN-1004 : used memory is 644 MB, reserved memory is 632 MB, peak memory is 771 MB
+PHY-1001 : 3487 mslices, 3504 lslices, 75 pads, 58 brams, 3 dsps
 TMR-2503 : Start to update net delay, extr mode = 3.
-TMR-2504 : Update delay of 17374 nets completely.
+TMR-2504 : Update delay of 18011 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 3.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
@@ -1369,18 +1678,18 @@ PHY-1001 : Start global routing, caller is route ...
 RUN-1001 : Generating global routing grids ...
 PHY-1001 : Generate routing nets ...
 PHY-1001 : Global iterations in 8 thread ...
-PHY-1002 : len = 847752, over cnt = 2759(7%), over = 4572, worst = 8
-PHY-1002 : len = 866784, over cnt = 1589(4%), over = 2268, worst = 8
-PHY-1002 : len = 884376, over cnt = 660(1%), over = 927, worst = 6
-PHY-1002 : len = 898472, over cnt = 2(0%), over = 2, worst = 1
-PHY-1002 : len = 898536, over cnt = 0(0%), over = 0, worst = 0
-PHY-1001 : End global iterations;  2.878729s wall, 3.984375s user + 0.078125s system = 4.062500s CPU (141.1%)
+PHY-1002 : len = 860440, over cnt = 2807(7%), over = 4694, worst = 8
+PHY-1002 : len = 878304, over cnt = 1769(5%), over = 2646, worst = 7
+PHY-1002 : len = 899936, over cnt = 722(2%), over = 1043, worst = 6
+PHY-1002 : len = 914928, over cnt = 24(0%), over = 33, worst = 5
+PHY-1002 : len = 915672, over cnt = 0(0%), over = 0, worst = 0
+PHY-1001 : End global iterations;  3.062873s wall, 4.062500s user + 0.015625s system = 4.078125s CPU (133.1%)
 
-PHY-1001 : Congestion index: top1 = 53.28, top5 = 48.37, top10 = 45.59, top15 = 43.67.
-PHY-1001 : End global routing;  3.212755s wall, 4.296875s user + 0.093750s system = 4.390625s CPU (136.7%)
+PHY-1001 : Congestion index: top1 = 53.77, top5 = 48.72, top10 = 45.99, top15 = 44.26.
+PHY-1001 : End global routing;  3.394154s wall, 4.406250s user + 0.015625s system = 4.421875s CPU (130.3%)
 
 PHY-1001 : Start detail routing ...
-PHY-1001 : Current memory(MB): used = 711, reserve = 715, peak = 742.
+PHY-1001 : Current memory(MB): used = 734, reserve = 732, peak = 771.
 PHY-1001 : Detailed router is running in normal mode.
 PHY-1001 : Generate detailed routing grids ...
 PHY-1001 : Generate nets ...
@@ -1410,131 +1719,147 @@ PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock me
 PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
 PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
 PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
-PHY-1001 : Current memory(MB): used = 988, reserve = 993, peak = 988.
-PHY-1001 : End build detailed router design. 3.992463s wall, 3.984375s user + 0.015625s system = 4.000000s CPU (100.2%)
+PHY-1001 : Current memory(MB): used = 1009, reserve = 1011, peak = 1009.
+PHY-1001 : End build detailed router design. 4.123919s wall, 4.093750s user + 0.031250s system = 4.125000s CPU (100.0%)
 
 PHY-1001 : Detail Route ...
 PHY-1001 : ===== Detail Route Phase 1 =====
 PHY-1001 : Clock net routing.....
 PHY-1001 : Routed 0% nets.
-PHY-1022 : len = 267120, over cnt = 4(0%), over = 4, worst = 1, crit = 0
-PHY-1001 : End initial clock net routed; 5.309327s wall, 5.281250s user + 0.015625s system = 5.296875s CPU (99.8%)
+PHY-1022 : len = 271128, over cnt = 4(0%), over = 4, worst = 1, crit = 0
+PHY-1001 : End initial clock net routed; 5.303886s wall, 5.312500s user + 0.000000s system = 5.312500s CPU (100.2%)
 
 PHY-1001 : Ripup-reroute.....
 PHY-1001 : ===== DR Iter 1 =====
-PHY-1022 : len = 267176, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End DR Iter 1; 0.431956s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (101.3%)
+PHY-1022 : len = 271184, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 1; 0.432936s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.4%)
 
-PHY-1001 : Current memory(MB): used = 1024, reserve = 1030, peak = 1024.
-PHY-1001 : End phase 1; 5.753878s wall, 5.734375s user + 0.015625s system = 5.750000s CPU (99.9%)
+PHY-1001 : Current memory(MB): used = 1044, reserve = 1047, peak = 1044.
+PHY-1001 : End phase 1; 5.749378s wall, 5.750000s user + 0.000000s system = 5.750000s CPU (100.0%)
 
 PHY-1001 : ===== Detail Route Phase 2 =====
 PHY-1001 : Initial routing.....
-PHY-1001 : Routed 44% nets.
-PHY-1001 : Routed 51% nets.
-PHY-1001 : Routed 61% nets.
-PHY-1001 : Routed 73% nets.
-PHY-1001 : Routed 93% nets.
-PHY-1022 : len = 2.31459e+06, over cnt = 1958(0%), over = 1962, worst = 2, crit = 0
-PHY-1001 : Current memory(MB): used = 1042, reserve = 1047, peak = 1042.
-PHY-1001 : End initial routed; 22.886717s wall, 57.109375s user + 0.343750s system = 57.453125s CPU (251.0%)
+PHY-1001 : Routed 45% nets.
+PHY-1001 : Routed 53% nets.
+PHY-1001 : Routed 62% nets.
+PHY-1001 : Routed 74% nets.
+PHY-1001 : Routed 94% nets.
+PHY-1022 : len = 2.35174e+06, over cnt = 1913(0%), over = 1916, worst = 2, crit = 0
+PHY-1001 : Current memory(MB): used = 1063, reserve = 1062, peak = 1063.
+PHY-1001 : End initial routed; 30.566888s wall, 61.609375s user + 0.359375s system = 61.968750s CPU (202.7%)
 
 PHY-1001 : Update timing.....
-PHY-1001 : 4/16475(0%) critical/total net(s).
+PHY-1001 : 3/17112(0%) critical/total net(s).
 RUN-1001 : --------------------------------------
 RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
 RUN-1001 : --------------------------------------
-RUN-1001 :   Setup  |  -2.084   |  -4.275   |   3   
+RUN-1001 :   Setup  |  -0.821   |  -1.201   |   5   
 RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
 RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.376894s wall, 3.359375s user + 0.015625s system = 3.375000s CPU (99.9%)
+PHY-1001 : End update timing; 3.373019s wall, 3.375000s user + 0.000000s system = 3.375000s CPU (100.1%)
 
-PHY-1001 : Current memory(MB): used = 1045, reserve = 1047, peak = 1045.
-PHY-1001 : End phase 2; 26.263678s wall, 60.468750s user + 0.359375s system = 60.828125s CPU (231.6%)
+PHY-1001 : Current memory(MB): used = 1071, reserve = 1069, peak = 1071.
+PHY-1001 : End phase 2; 33.939995s wall, 64.984375s user + 0.359375s system = 65.343750s CPU (192.5%)
 
 PHY-1001 : ===== Detail Route Phase 3 =====
 PHY-1001 : Optimize timing.....
 PHY-1001 : ===== OPT Iter 1 =====
-PHY-1001 : Processed 4 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
-PHY-1001 : End OPT Iter 1; 0.147381s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (106.0%)
+PHY-1001 : Processed 3 pins with SWNS -0.811ns STNS -0.811ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.152328s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (102.6%)
 
-PHY-1022 : len = 2.31459e+06, over cnt = 1960(0%), over = 1964, worst = 2, crit = 0
-PHY-1001 : End optimize timing; 0.412433s wall, 0.406250s user + 0.000000s system = 0.406250s CPU (98.5%)
+PHY-1022 : len = 2.35176e+06, over cnt = 1914(0%), over = 1917, worst = 2, crit = 0
+PHY-1001 : End optimize timing; 0.447400s wall, 0.437500s user + 0.000000s system = 0.437500s CPU (97.8%)
 
 PHY-1001 : Ripup-reroute.....
 PHY-1001 : ===== DR Iter 1 =====
-PHY-1022 : len = 2.28119e+06, over cnt = 722(0%), over = 722, worst = 1, crit = 0
-PHY-1001 : End DR Iter 1; 1.359431s wall, 2.500000s user + 0.000000s system = 2.500000s CPU (183.9%)
+PHY-1022 : len = 2.32276e+06, over cnt = 783(0%), over = 786, worst = 2, crit = 0
+PHY-1001 : End DR Iter 1; 1.138908s wall, 2.140625s user + 0.015625s system = 2.156250s CPU (189.3%)
 
 PHY-1001 : ===== DR Iter 2 =====
-PHY-1022 : len = 2.27972e+06, over cnt = 191(0%), over = 191, worst = 1, crit = 0
-PHY-1001 : End DR Iter 2; 0.616469s wall, 1.031250s user + 0.000000s system = 1.031250s CPU (167.3%)
+PHY-1022 : len = 2.31824e+06, over cnt = 149(0%), over = 150, worst = 2, crit = 0
+PHY-1001 : End DR Iter 2; 0.829325s wall, 1.203125s user + 0.015625s system = 1.218750s CPU (147.0%)
 
 PHY-1001 : ===== DR Iter 3 =====
-PHY-1022 : len = 2.28086e+06, over cnt = 22(0%), over = 22, worst = 1, crit = 0
-PHY-1001 : End DR Iter 3; 0.482993s wall, 0.578125s user + 0.000000s system = 0.578125s CPU (119.7%)
+PHY-1022 : len = 2.31907e+06, over cnt = 23(0%), over = 23, worst = 1, crit = 0
+PHY-1001 : End DR Iter 3; 0.450179s wall, 0.531250s user + 0.000000s system = 0.531250s CPU (118.0%)
 
 PHY-1001 : ===== DR Iter 4 =====
-PHY-1022 : len = 2.28087e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
-PHY-1001 : End DR Iter 4; 0.237032s wall, 0.250000s user + 0.000000s system = 0.250000s CPU (105.5%)
+PHY-1022 : len = 2.31944e+06, over cnt = 6(0%), over = 6, worst = 1, crit = 0
+PHY-1001 : End DR Iter 4; 0.278370s wall, 0.328125s user + 0.000000s system = 0.328125s CPU (117.9%)
 
 PHY-1001 : ===== DR Iter 5 =====
-PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End DR Iter 5; 0.207754s wall, 0.218750s user + 0.000000s system = 0.218750s CPU (105.3%)
+PHY-1022 : len = 2.31957e+06, over cnt = 2(0%), over = 2, worst = 1, crit = 0
+PHY-1001 : End DR Iter 5; 0.272769s wall, 0.312500s user + 0.000000s system = 0.312500s CPU (114.6%)
+
+PHY-1001 : ===== DR Iter 6 =====
+PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 6; 0.299020s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (99.3%)
+
+PHY-1001 : ===== DR Iter 7 =====
+PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 7; 0.291461s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (101.9%)
+
+PHY-1001 : ===== DR Iter 8 =====
+PHY-1022 : len = 2.3196e+06, over cnt = 1(0%), over = 1, worst = 1, crit = 0
+PHY-1001 : End DR Iter 8; 0.177934s wall, 0.171875s user + 0.031250s system = 0.203125s CPU (114.2%)
+
+PHY-1001 : ==== DR Iter 9 ====
+PHY-1022 : len = 2.3196e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End DR Iter 9; 0.177859s wall, 0.218750s user + 0.015625s system = 0.234375s CPU (131.8%)
 
 PHY-1001 : Update timing.....
-PHY-1001 : 4/16475(0%) critical/total net(s).
+PHY-1001 : 1/17112(0%) critical/total net(s).
 RUN-1001 : --------------------------------------
 RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
 RUN-1001 : --------------------------------------
-RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Setup  |  -0.811   |  -0.811   |   1   
 RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
 RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.278177s wall, 3.281250s user + 0.000000s system = 3.281250s CPU (100.1%)
+PHY-1001 : End update timing; 3.385904s wall, 3.390625s user + 0.000000s system = 3.390625s CPU (100.1%)
 
 PHY-1001 : Commit to database.....
-PHY-1001 : 589 feed throughs used by 429 nets
-PHY-1001 : End commit to database; 2.281274s wall, 2.281250s user + 0.000000s system = 2.281250s CPU (100.0%)
+PHY-1001 : 604 feed throughs used by 440 nets
+PHY-1001 : End commit to database; 2.263587s wall, 2.265625s user + 0.000000s system = 2.265625s CPU (100.1%)
 
-PHY-1001 : Current memory(MB): used = 1153, reserve = 1160, peak = 1153.
-PHY-1001 : End phase 3; 9.283671s wall, 10.937500s user + 0.000000s system = 10.937500s CPU (117.8%)
+PHY-1001 : Current memory(MB): used = 1178, reserve = 1182, peak = 1178.
+PHY-1001 : End phase 3; 10.447954s wall, 12.000000s user + 0.078125s system = 12.078125s CPU (115.6%)
 
 PHY-1001 : ===== Detail Route Phase 4 =====
 PHY-1001 : Optimize timing.....
 PHY-1001 : ===== OPT Iter 1 =====
-PHY-1001 : Processed 3 pins with SWNS -1.945ns STNS -4.090ns FEP 3.
-PHY-1001 : End OPT Iter 1; 0.157822s wall, 0.156250s user + 0.000000s system = 0.156250s CPU (99.0%)
+PHY-1001 : Processed 1 pins with SWNS -0.811ns STNS -0.811ns FEP 1.
+PHY-1001 : End OPT Iter 1; 0.140792s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (99.9%)
 
-PHY-1022 : len = 2.28094e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
-PHY-1001 : End optimize timing; 0.431752s wall, 0.421875s user + 0.000000s system = 0.421875s CPU (97.7%)
+PHY-1022 : len = 2.3196e+06, over cnt = 0(0%), over = 0, worst = 0, crit = 0
+PHY-1001 : End optimize timing; 0.389031s wall, 0.390625s user + 0.000000s system = 0.390625s CPU (100.4%)
 
-PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-1.945ns, -4.090ns, 3}
+PHY-0007 : Phase: 4; Congestion: {, , , }; Timing: {-0.811ns, -0.811ns, 1}
 PHY-1001 : Update timing.....
-PHY-1001 : 4/16475(0%) critical/total net(s).
+PHY-1001 : 1/17112(0%) critical/total net(s).
 RUN-1001 : --------------------------------------
 RUN-1001 :   Type   |  WNS(ns)  |  TNS(ns)  |  FEP  
 RUN-1001 : --------------------------------------
-RUN-1001 :   Setup  |  -1.945   |  -4.090   |   3   
+RUN-1001 :   Setup  |  -0.811   |  -0.811   |   1   
 RUN-1001 :   Hold   |   0.067   |   0.000   |   0   
 RUN-1001 : --------------------------------------
-PHY-1001 : End update timing; 3.367672s wall, 3.359375s user + 0.000000s system = 3.359375s CPU (99.8%)
+PHY-1001 : End update timing; 3.348725s wall, 3.343750s user + 0.000000s system = 3.343750s CPU (99.9%)
 
 PHY-1001 : Commit to database.....
-PHY-1001 : 589 feed throughs used by 429 nets
-PHY-1001 : End commit to database; 2.325026s wall, 2.328125s user + 0.000000s system = 2.328125s CPU (100.1%)
+PHY-1001 : 604 feed throughs used by 440 nets
+PHY-1001 : End commit to database; 2.386680s wall, 2.390625s user + 0.000000s system = 2.390625s CPU (100.2%)
 
-PHY-1001 : Current memory(MB): used = 1162, reserve = 1169, peak = 1162.
-PHY-1001 : End phase 4; 6.151986s wall, 6.156250s user + 0.000000s system = 6.156250s CPU (100.1%)
+PHY-1001 : Current memory(MB): used = 1188, reserve = 1191, peak = 1188.
+PHY-1001 : End phase 4; 6.151776s wall, 6.140625s user + 0.000000s system = 6.140625s CPU (99.8%)
 
-PHY-1003 : Routed, final wirelength = 2.28094e+06
-PHY-1001 : Current memory(MB): used = 1165, reserve = 1172, peak = 1165.
-PHY-1001 : End export database. 0.144027s wall, 0.140625s user + 0.000000s system = 0.140625s CPU (97.6%)
+PHY-1003 : Routed, final wirelength = 2.3196e+06
+PHY-1001 : Current memory(MB): used = 1189, reserve = 1193, peak = 1189.
+PHY-1001 : End export database. 0.062610s wall, 0.062500s user + 0.000000s system = 0.062500s CPU (99.8%)
 
-PHY-1001 : End detail routing;  51.989670s wall, 87.828125s user + 0.390625s system = 88.218750s CPU (169.7%)
+PHY-1001 : End detail routing;  60.875243s wall, 93.437500s user + 0.468750s system = 93.906250s CPU (154.3%)
 
-RUN-1003 : finish command "route" in  57.995979s wall, 94.890625s user + 0.484375s system = 95.375000s CPU (164.5%)
+RUN-1003 : finish command "route" in  67.053396s wall, 100.609375s user + 0.484375s system = 101.093750s CPU (150.8%)
 
-RUN-1004 : used memory is 1093 MB, reserved memory is 1105 MB, peak memory is 1165 MB
+RUN-1004 : used memory is 1116 MB, reserved memory is 1113 MB, peak memory is 1189 MB
 RUN-1002 : start command "report_area -io_info -file hg_anlogic_phy.area"
 RUN-1001 : standard
 ***Report Model: huagao_mipi_top Device: EG4D20EG176***
@@ -1546,12 +1871,12 @@ IO Statistics
   #inout                    0
 
 Utilization Statistics
-#lut                    10273   out of  19600   52.41%
-#reg                     9368   out of  19600   47.80%
-#le                     12618
-  #lut only              3250   out of  12618   25.76%
-  #reg only              2345   out of  12618   18.58%
-  #lut&reg               7023   out of  12618   55.66%
+#lut                    10421   out of  19600   53.17%
+#reg                     9955   out of  19600   50.79%
+#le                     13076
+  #lut only              3121   out of  13076   23.87%
+  #reg only              2655   out of  13076   20.30%
+  #lut&reg               7300   out of  13076   55.83%
 #dsp                        3   out of     29   10.34%
 #bram                      54   out of     64   84.38%
   #bram9k                  50
@@ -1566,17 +1891,17 @@ Utilization Statistics
 
 Clock Resource Statistics
 Index     ClockNet                                           Type               DriverType         Driver                                             Fanout
-#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1810
-#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1425
-#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1358
-#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               942
-#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    143
-#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          69
-#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         69
+#1        u_pll/clk0_buf                                     GCLK               pll                u_pll/pll_inst.clkc0                               1825
+#2        u_pll_lvds/clk0_buf                                GCLK               pll                u_pll_lvds/pll_inst.clkc0                          1432
+#3        uu_pll_lvds/clk0_buf                               GCLK               pll                uu_pll_lvds/pll_inst.clkc0                         1342
+#4        exdev_ctl_a/clk_adc                                GCLK               pll                u_pll/pll_inst.clkc4                               1235
+#5        exdev_ctl_a/u_ADconfig/clk_config                  GCLK               lslice             exdev_ctl_a/u_ADconfig/clk_config_reg_syn_14.q0    140
+#6        ua_lvds_rx/sclk                                    GCLK               pll                u_pll_lvds/pll_inst.clkc1                          71
+#7        ub_lvds_rx/sclk                                    GCLK               pll                uu_pll_lvds/pll_inst.clkc1                         70
 #8        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2    GCLK               pll                u_pll/pll_inst.clkc1                               26
 #9        u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4    GCLK               pll                u_pll/pll_inst.clkc2                               4
-#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               lslice             u_mipi_sot_min/reg1_syn_277.f1                     3
-#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/reg10_syn_122.f1                         3
+#10       exdev_ctl_a/u_ADconfig/gret9lit16_n                GCLK               mslice             u_mipi_eot_min/reg1_syn_299.f1                     3
+#11       exdev_ctl_b/u_ADconfig/gret9lit16_n                GCLK               mslice             u_bus_top/u_local_bus_slve_cis/reg45_syn_163.f0    3
 #12       a_lvds_clk_p_dup_1                                 GCLK               io                 a_lvds_clk_p_syn_2.di                              1
 #13       b_lvds_clk_p_dup_1                                 GCLK               io                 b_lvds_clk_p_syn_2.di                              1
 #14       clock_source_dup_1                                 GCLK               io                 clock_source_syn_2.di                              1
@@ -1614,8 +1939,8 @@ Detailed IO Report
   b_lvds_data_p[0](n)      INPUT        P122        LVDS25           N/A           NONE      IDDRX1   
      clock_source          INPUT        P176       LVCMOS33          N/A          PULLUP      NONE    
     global_reset_n         INPUT        P174       LVCMOS33          N/A          PULLUP      NONE    
-       onoff_in            INPUT        P148       LVCMOS33          N/A           N/A        NONE    
-       paper_in            INPUT        P106       LVCMOS25          N/A           N/A        NONE    
+       onoff_in            INPUT        P141       LVCMOS33          N/A           N/A        NONE    
+       paper_in            INPUT        P16        LVCMOS25          N/A           N/A        NONE    
         rxd_dsp            INPUT        P144       LVCMOS33          N/A          PULLUP      IREG    
       O_clk_hs_p          OUTPUT        P98         LVDS25           NA            NONE      ODDRX2L  
      O_clk_hs_p(n)        OUTPUT        P99         LVDS25           NA            NONE      ODDRX2L  
@@ -1656,108 +1981,109 @@ Detailed IO Report
        debug[0]           OUTPUT        P60        LVCMOS33           8            NONE       NONE    
         fan_pwm           OUTPUT        P139       LVCMOS33           8            N/A        NONE    
     frame_indicator       OUTPUT        P107       LVCMOS25           8            N/A        OREG    
-       onoff_out          OUTPUT        P169       LVCMOS33           8            N/A        NONE    
-       paper_out          OUTPUT        P91        LVCMOS25           8            N/A        NONE    
-       scan_out           OUTPUT        P66        LVCMOS25           8            N/A        NONE    
-   sys_initial_done       OUTPUT        P39        LVCMOS25           8            N/A        NONE    
+       onoff_out          OUTPUT        P111       LVCMOS25           8            N/A        NONE    
+       paper_out          OUTPUT        P106       LVCMOS25           8            N/A        NONE    
+       scan_out           OUTPUT        P84        LVCMOS25           8            N/A        NONE    
+   sys_initial_done       OUTPUT        P71        LVCMOS25           8            N/A        NONE    
         txd_dsp           OUTPUT        P145       LVCMOS33           8            NONE       OREG    
 
 Report Hierarchy Area:
 +---------------------------------------------------------------------------------------------------------+
 |Instance                      |Module               |le     |lut     |ripple  |seq     |bram    |dsp     |
 +---------------------------------------------------------------------------------------------------------+
-|top                           |huagao_mipi_top      |12618  |9246    |1027    |9400    |58      |3       |
-|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |561    |454     |23      |449     |4       |1       |
-|    U_fifo_w32_d8192          |fifo_w32_d8192       |110    |93      |4       |93      |4       |0       |
-|    U_crc16_24b               |crc16_24b            |32     |32      |0       |22      |0       |0       |
-|    U_ecc_gen                 |ecc_gen              |12     |12      |0       |9       |0       |0       |
-|  exdev_ctl_a                 |exdev_ctl            |781    |337     |96      |583     |0       |0       |
-|    u_ADconfig                |AD_config            |191    |118     |25      |142     |0       |0       |
-|    u_gen_sp                  |gen_sp               |269    |158     |71      |120     |0       |0       |
-|  exdev_ctl_b                 |exdev_ctl            |743    |379     |96      |554     |0       |0       |
-|    u_ADconfig                |AD_config            |177    |129     |25      |125     |0       |0       |
-|    u_gen_sp                  |gen_sp               |259    |144     |71      |122     |0       |0       |
-|  sampling_fe_a               |sampling_fe          |3071   |2501    |306     |2076    |25      |0       |
-|    u0_soft_n                 |cdc_sync             |6      |6       |0       |6       |0       |0       |
-|    u_ad_sampling             |ad_sampling          |180    |137     |17      |133     |0       |0       |
-|      u0_soft_n               |cdc_sync             |5      |4       |0       |5       |0       |0       |
-|    u_sort                    |sort                 |2855   |2346    |289     |1907    |25      |0       |
-|      rddpram_ctl             |rddpram_ctl          |2      |1       |0       |2       |0       |0       |
-|        u0_rdsoft_n           |cdc_sync             |2      |1       |0       |2       |0       |0       |
-|      u0_rdsoft_n             |cdc_sync             |9      |4       |0       |9       |0       |0       |
-|      u0_wrsoft_n             |cdc_sync             |6      |6       |0       |6       |0       |0       |
-|      u_data_prebuffer        |data_prebuffer       |2407   |1999    |253     |1544    |22      |0       |
-|        channelPart           |channel_part_8478    |143    |136     |3       |126     |0       |0       |
-|        fifo_adc              |fifo_adc             |58     |49      |9       |41      |0       |0       |
-|        ram_switch            |ram_switch           |1870   |1532    |197     |1149    |0       |0       |
-|          adc_addr_gen        |adc_addr_gen         |247    |220     |27      |123     |0       |0       |
-|            [0]$ch_addr_gen   |ch_addr_gen          |12     |9       |3       |5       |0       |0       |
-|            [1]$ch_addr_gen   |ch_addr_gen          |29     |26      |3       |15      |0       |0       |
-|            [2]$ch_addr_gen   |ch_addr_gen          |31     |28      |3       |17      |0       |0       |
-|            [3]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |13      |0       |0       |
-|            [4]$ch_addr_gen   |ch_addr_gen          |27     |24      |3       |13      |0       |0       |
-|            [5]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
-|            [6]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |11      |0       |0       |
-|            [7]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |10      |0       |0       |
-|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |11      |0       |0       |
-|          insert              |insert               |965    |654     |170     |661     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |658    |658     |0       |365     |0       |0       |
-|        read_ram_i            |read_ram             |300    |255     |44      |195     |0       |0       |
-|          read_ram_addr       |read_ram_addr        |240    |200     |40      |155     |0       |0       |
-|          read_ram_data       |read_ram_data        |56     |51      |4       |36      |0       |0       |
-|          u0_rdsoft_n         |cdc_sync             |4      |4       |0       |4       |0       |0       |
+|top                           |huagao_mipi_top      |13076  |9394    |1027    |9987    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |544    |438     |23      |443     |4       |1       |
+|    U_fifo_w32_d8192          |fifo_w32_d8192       |100    |80      |4       |87      |4       |0       |
+|    U_crc16_24b               |crc16_24b            |35     |35      |0       |24      |0       |0       |
+|    U_ecc_gen                 |ecc_gen              |8      |8       |0       |6       |0       |0       |
+|  exdev_ctl_a                 |exdev_ctl            |779    |386     |96      |580     |0       |0       |
+|    u_ADconfig                |AD_config            |204    |138     |25      |151     |0       |0       |
+|    u_gen_sp                  |gen_sp               |263    |160     |71      |117     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |739    |378     |96      |562     |0       |0       |
+|    u_ADconfig                |AD_config            |167    |122     |25      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |255    |147     |71      |120     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |3214   |2625    |306     |2077    |25      |0       |
+|    u0_soft_n                 |cdc_sync             |7      |2       |0       |7       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |184    |145     |17      |136     |0       |0       |
+|      u0_soft_n               |cdc_sync             |5      |5       |0       |5       |0       |0       |
+|    u_sort                    |sort                 |2998   |2468    |289     |1909    |25      |0       |
+|      rddpram_ctl             |rddpram_ctl          |5      |4       |0       |5       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |5      |4       |0       |5       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |4      |0       |0       |4       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |1       |0       |2       |0       |0       |
+|      u_data_prebuffer        |data_prebuffer       |2596   |2148    |253     |1582    |22      |0       |
+|        channelPart           |channel_part_8478    |160    |155     |3       |126     |0       |0       |
+|        fifo_adc              |fifo_adc             |56     |47      |9       |39      |0       |0       |
+|        ram_switch            |ram_switch           |2024   |1637    |197     |1169    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |255    |227     |27      |113     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |11     |7       |3       |5       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |25     |22      |3       |12      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |14      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |9       |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |13      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |10      |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |30     |27      |3       |16      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |28     |25      |3       |10      |0       |0       |
+|          insert              |insert               |987    |628     |170     |682     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |782    |782     |0       |374     |0       |0       |
+|        read_ram_i            |read_ram             |313    |266     |44      |209     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |251    |211     |40      |166     |0       |0       |
+|          read_ram_data       |read_ram_data        |57     |51      |4       |38      |0       |0       |
+|          u0_rdsoft_n         |cdc_sync             |5      |4       |0       |5       |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_10      |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
 |        u0_sort_ram_a_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_4       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_8       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_6       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_7       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
+|        u0_sort_ram_a_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_2       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_b_3       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
+|        u0_sort_ram_b_3       |SORT_RAM_9k          |2      |2       |0       |1       |1       |0       |
 |        u0_sort_ram_b_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_8       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_b_9       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|      u_transfer_300_to_200   |transfer_300_to_200  |337    |245     |36      |283     |3       |0       |
-|        u0_soft_n             |cdc_sync             |5      |3       |0       |5       |0       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |326    |252     |36      |271     |3       |0       |
+|        u0_soft_n             |cdc_sync             |1      |0       |0       |1       |0       |0       |
 |        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0      |0       |0       |0       |3       |0       |
-|  sampling_fe_b               |sampling_fe_rev      |3397   |2743    |349     |2088    |25      |1       |
-|    u0_soft_n                 |cdc_sync             |2      |2       |0       |2       |0       |0       |
-|    u_ad_sampling             |ad_sampling          |189    |127     |17      |147     |0       |0       |
-|      u0_soft_n               |cdc_sync             |3      |3       |0       |3       |0       |0       |
-|    u_sort                    |sort_rev             |3178   |2597    |332     |1911    |25      |1       |
-|      rddpram_ctl             |rddpram_ctl_rev      |4      |4       |0       |4       |0       |0       |
-|        u0_rdsoft_n           |cdc_sync             |4      |4       |0       |4       |0       |0       |
-|      u0_rdsoft_n             |cdc_sync             |4      |4       |0       |4       |0       |0       |
-|      u_data_prebuffer_rev    |data_prebuffer_rev   |2741   |2251    |290     |1561    |22      |1       |
-|        channelPart           |channel_part_8478    |243    |238     |3       |137     |0       |0       |
-|        fifo_adc              |fifo_adc             |60     |51      |9       |43      |0       |1       |
-|        ram_switch            |ram_switch           |2023   |1671    |197     |1132    |0       |0       |
-|          adc_addr_gen        |adc_addr_gen         |219    |192     |27      |98      |0       |0       |
-|            [0]$ch_addr_gen   |ch_addr_gen          |13     |10      |3       |6       |0       |0       |
-|            [1]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |9       |0       |0       |
-|            [2]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |11      |0       |0       |
-|            [3]$ch_addr_gen   |ch_addr_gen          |20     |17      |3       |12      |0       |0       |
-|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |10      |0       |0       |
-|            [5]$ch_addr_gen   |ch_addr_gen          |19     |16      |3       |6       |0       |0       |
-|            [6]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |9       |0       |0       |
-|            [7]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |8       |0       |0       |
-|            [8]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |12      |0       |0       |
-|          insert              |insert               |982    |658     |170     |674     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |822    |821     |0       |360     |0       |0       |
-|        read_ram_i            |read_ram_rev         |378    |263     |81      |214     |0       |0       |
-|          read_ram_addr       |read_ram_addr_rev    |311    |226     |73      |165     |0       |0       |
-|          read_ram_data       |read_ram_data_rev    |67     |37      |8       |49      |0       |0       |
+|  sampling_fe_b               |sampling_fe_rev      |3165   |2462    |349     |2109    |25      |1       |
+|    u0_soft_n                 |cdc_sync             |4      |2       |0       |4       |0       |0       |
+|    u_ad_sampling             |ad_sampling          |187    |105     |17      |148     |0       |0       |
+|      u0_soft_n               |cdc_sync             |4      |1       |0       |4       |0       |0       |
+|    u_sort                    |sort_rev             |2946   |2342    |332     |1929    |25      |1       |
+|      rddpram_ctl             |rddpram_ctl_rev      |6      |5       |0       |6       |0       |0       |
+|        u0_rdsoft_n           |cdc_sync             |6      |5       |0       |6       |0       |0       |
+|      u0_rdsoft_n             |cdc_sync             |2      |0       |0       |2       |0       |0       |
+|      u0_wrsoft_n             |cdc_sync             |2      |2       |0       |2       |0       |0       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |2485   |1993    |290     |1576    |22      |1       |
+|        channelPart           |channel_part_8478    |275    |272     |3       |151     |0       |0       |
+|        fifo_adc              |fifo_adc             |62     |53      |9       |45      |0       |1       |
+|        ram_switch            |ram_switch           |1756   |1391    |197     |1140    |0       |0       |
+|          adc_addr_gen        |adc_addr_gen         |198    |169     |27      |122     |0       |0       |
+|            [0]$ch_addr_gen   |ch_addr_gen          |13     |8       |3       |9       |0       |0       |
+|            [1]$ch_addr_gen   |ch_addr_gen          |26     |23      |3       |18      |0       |0       |
+|            [2]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [3]$ch_addr_gen   |ch_addr_gen          |24     |21      |3       |18      |0       |0       |
+|            [4]$ch_addr_gen   |ch_addr_gen          |22     |19      |3       |14      |0       |0       |
+|            [5]$ch_addr_gen   |ch_addr_gen          |16     |13      |3       |9       |0       |0       |
+|            [6]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |10      |0       |0       |
+|            [7]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |11      |0       |0       |
+|            [8]$ch_addr_gen   |ch_addr_gen          |18     |15      |3       |8       |0       |0       |
+|          insert              |insert               |1012   |680     |170     |674     |0       |0       |
+|          ram_switch_state    |ram_switch_state     |546    |542     |0       |344     |0       |0       |
+|        read_ram_i            |read_ram_rev         |363    |258     |81      |213     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |298    |218     |73      |166     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |65     |40      |8       |47      |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_10      |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
@@ -1766,23 +2092,22 @@ Report Hierarchy Area:
 |        u0_sort_ram_a_4       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_5       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |        u0_sort_ram_a_6       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
-|        u0_sort_ram_a_7       |SORT_RAM_9k          |0      |0       |0       |0       |1       |0       |
 |......                        |......               |-      |-       |-       |-       |-       |-       |
 +---------------------------------------------------------------------------------------------------------+
 
 
 DataNet Average Fanout:
 
-   Index     Fanout    Nets  
-    #1         1       9907  
-    #2         2       3801  
-    #3         3       1374  
-    #4         4       579   
-    #5        5-10     1189  
-    #6       11-50     584   
-    #7       51-100     22   
-    #8        >500      1    
-  Average     2.92           
+   Index     Fanout    Nets   
+    #1         1       10415  
+    #2         2       3902   
+    #3         3       1365   
+    #4         4        552   
+    #5        5-10     1241   
+    #6       11-50      592   
+    #7       51-100     26    
+    #8        >500       1    
+  Average     2.89            
 
 RUN-1002 : start command "export_db hg_anlogic_pr.db"
 RUN-1001 : Exported /
@@ -1800,23 +2125,23 @@ RUN-1001 : Exported violations
 RUN-1001 : Exported timing constraints
 RUN-1001 : Exported IO constraints
 RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.104425s wall, 3.593750s user + 0.000000s system = 3.593750s CPU (170.8%)
+RUN-1003 : finish command "export_db hg_anlogic_pr.db" in  2.122784s wall, 3.656250s user + 0.000000s system = 3.656250s CPU (172.2%)
 
-RUN-1004 : used memory is 1094 MB, reserved memory is 1106 MB, peak memory is 1165 MB
+RUN-1004 : used memory is 1117 MB, reserved memory is 1115 MB, peak memory is 1189 MB
 RUN-1002 : start command "start_timer"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 73989, tnet num: 17374, tinst num: 6913, tnode num: 96516, tedge num: 124127.
-TMR-2508 : Levelizing timing graph completed, there are 25 levels in total.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 76296, tnet num: 18011, tinst num: 7140, tnode num: 100004, tedge num: 127731.
+TMR-2508 : Levelizing timing graph completed, there are 23 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer" in  1.643211s wall, 1.656250s user + 0.000000s system = 1.656250s CPU (100.8%)
+RUN-1003 : finish command "start_timer" in  1.647971s wall, 1.640625s user + 0.000000s system = 1.640625s CPU (99.6%)
 
-RUN-1004 : used memory is 1098 MB, reserved memory is 1110 MB, peak memory is 1165 MB
+RUN-1004 : used memory is 1123 MB, reserved memory is 1121 MB, peak memory is 1189 MB
 RUN-1002 : start command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing"
 TMR-2503 : Start to update net delay, extr mode = 6.
-TMR-2504 : Update delay of 17374 nets completely.
+TMR-2504 : Update delay of 18011 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 6.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
@@ -1829,27 +2154,27 @@ TMR-5009 WARNING: No clock constraint on 3 clock net(s):
 		exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2
 TMR-3508 : Export timing summary.
 TMR-3507 : Timing report generated successfully in hg_anlogic_phy.timing, timing summary in hg_anlogic_phy.tsm.
-RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.458982s wall, 1.437500s user + 0.015625s system = 1.453125s CPU (99.6%)
+RUN-1003 : finish command "report_timing -mode FINAL -net_info -rpt_autogen true -file hg_anlogic_phy.timing" in  1.560815s wall, 1.562500s user + 0.000000s system = 1.562500s CPU (100.1%)
 
-RUN-1004 : used memory is 1102 MB, reserved memory is 1114 MB, peak memory is 1165 MB
+RUN-1004 : used memory is 1126 MB, reserved memory is 1123 MB, peak memory is 1189 MB
 RUN-1002 : start command "export_bid hg_anlogic_inst.bid"
 PRG-1000 : <!-- HMAC is: 844f3117af495dd5cfc64305f4e852ac5a7ad71256b4c0d3112e4fc3a83dca4b -->
 RUN-1002 : start command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin"
 BIT-1003 : Start to generate bitstream. 
 BIT-1002 : Init instances with 8 threads.
-BIT-1002 : Init instances completely, inst num: 6913
+BIT-1002 : Init instances completely, inst num: 7140
 BIT-1002 : Init pips with 8 threads.
-BIT-1002 : Init pips completely, net num: 17552, pip num: 172527
+BIT-1002 : Init pips completely, net num: 18189, pip num: 175850
 BIT-1002 : Init feedthrough with 8 threads.
-BIT-1002 : Init feedthrough completely, num: 589
+BIT-1002 : Init feedthrough completely, num: 604
 BIT-1003 : Multithreading accelaration with 8 threads.
-BIT-1003 : Generate bitstream completely, there are 3249 valid insts, and 479670 bits set as '1'.
+BIT-1003 : Generate bitstream completely, there are 3263 valid insts, and 489276 bits set as '1'.
 BIT-1004 : the usercode register value: 00000000101110110000000000000000
 BIT-1004 : PLL setting string = 1011
 BIT-1004 : Generate bits file hg_anlogic.bit.
 BIT-1004 : Generate bin file hg_anlogic.bin.
-RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  10.263146s wall, 65.328125s user + 0.125000s system = 65.453125s CPU (637.7%)
+RUN-1003 : finish command "bitgen -bit hg_anlogic.bit -bin hg_anlogic.bin" in  9.457605s wall, 62.250000s user + 0.156250s system = 62.406250s CPU (659.9%)
 
-RUN-1004 : used memory is 1265 MB, reserved memory is 1268 MB, peak memory is 1380 MB
-RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240219_105751.log"
+RUN-1004 : used memory is 1297 MB, reserved memory is 1293 MB, peak memory is 1412 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/phy_1/td_20240312_145210.log"
 RUN-1001 : Backing up run's log file succeed.
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
index 8bc5310..399fe85 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_gate.begin.f
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="6996">
+    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="17512">
     </Process>
 </ProcessHandle>
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
index 8bc5310..399fe85 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.opt_rtl.begin.f
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="6996">
+    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="17512">
     </Process>
 </ProcessHandle>
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
index 8bc5310..399fe85 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/.read_design.begin.f
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="6996">
+    <Process Ownner="holdtecs" Host="DESKTOP-5MQL5VE" Pid="17512">
     </Process>
 </ProcessHandle>
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
index 11cdc57..1ea84cb 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic.prj
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Project Version="3" Minor="2" RunTime="2024-02-19T10:56:24.896188">
+<Project Version="3" Minor="2" RunTime="2024-03-12T14:50:44.727439">
     <Project_Created_Time></Project_Created_Time>
     <TD_Encoding>UTF-8</TD_Encoding>
     <TD_Version>5.6.71036</TD_Version>
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db
index 7de4c54..a517400 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_elaborate.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
index 3727463..e2707b8 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.area
@@ -8,16 +8,16 @@ IO Statistics
   #inout                    0
 
 LUT Statistics
-#Total_luts              9962
-  #lut4                  5231
-  #lut5                  2176
+#Total_luts             10030
+  #lut4                  5343
+  #lut5                  2132
   #lut6                     0
   #lut5_mx41                0
   #lut4_alu1b            2555
 
 Utilization Statistics
-#lut                     9962   out of  19600   50.83%
-#reg                     9173   out of  19600   46.80%
+#lut                    10030   out of  19600   51.17%
+#reg                     9745   out of  19600   49.72%
 #le                         0
 #dsp                        3   out of     29   10.34%
 #bram                      54   out of     64   84.38%
@@ -35,30 +35,30 @@ Report Hierarchy Area:
 +-------------------------------------------------------------------------------------------------+
 |Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
 +-------------------------------------------------------------------------------------------------+
-|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
-|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|top                           |huagao_mipi_top      |7475    |2555    |9777    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
 |    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
 |    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
 |    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
-|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
-|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
-|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
-|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
-|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
-|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
-|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|  exdev_ctl_a                 |exdev_ctl            |283     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |93      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2334    |738     |1919    |25      |0       |
 |    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
 |    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
 |      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
-|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|    u_sort                    |sort                 |2264    |691     |1737    |25      |0       |
 |      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
 |        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
-|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|      u_data_prebuffer        |data_prebuffer       |1922    |615     |1391    |22      |0       |
 |        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
 |        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
-|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
 |          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
 |            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
 |            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
@@ -70,10 +70,10 @@ Report Hierarchy Area:
 |            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |          insert              |insert               |265     |323     |692     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
-|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
-|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
-|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |206     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |173     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |32      |13      |32      |0       |0       |
 |          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
@@ -100,19 +100,19 @@ Report Hierarchy Area:
 |      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
 |        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
 |        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
-|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|  sampling_fe_b               |sampling_fe_rev      |2334    |751     |1936    |25      |1       |
 |    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
 |    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
 |      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
-|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|    u_sort                    |sort_rev             |2264    |704     |1754    |25      |1       |
 |      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
 |        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
-|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1925    |628     |1408    |22      |1       |
 |        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
 |        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
-|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
 |          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
 |            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
 |            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
@@ -124,10 +124,10 @@ Report Hierarchy Area:
 |            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |          insert              |insert               |265     |323     |692     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
-|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
-|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
-|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |206     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |180     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |26      |26      |42      |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
@@ -150,13 +150,15 @@ Report Hierarchy Area:
 |        u0_sort_ram_b_7       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_b_8       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_b_9       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
-|      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
+|      u_transfer_300_to_200   |transfer_300_to_200  |126     |76      |276     |3       |0       |
 |        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
 |        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
 |  scan_start_diff             |scan_start_diff      |30      |0       |12      |0       |0       |
 |  u0_test_en                  |cdc_sync             |1       |0       |5       |0       |0       |
 |  u1_test_en                  |cdc_sync             |1       |0       |5       |0       |0       |
 |  u2_test_en                  |cdc_sync             |1       |0       |5       |0       |0       |
+|  u_O_clk_lp_n                |cdc_sync             |20      |0       |286     |0       |0       |
+|  u_O_clk_lp_p                |cdc_sync             |20      |0       |286     |0       |0       |
 |  u_a_pclk                    |cdc_sync             |1       |0       |5       |0       |0       |
 |  u_a_sp_sampling             |cdc_sync             |1       |0       |5       |0       |0       |
 |  u_a_sp_sampling_cam         |cdc_sync             |1       |0       |5       |0       |0       |
@@ -165,16 +167,16 @@ Report Hierarchy Area:
 |  u_b_sp_sampling             |cdc_sync             |1       |0       |5       |0       |0       |
 |  u_b_sp_sampling_cam         |cdc_sync             |1       |0       |5       |0       |0       |
 |  u_b_sp_sampling_last        |cdc_sync             |1       |0       |5       |0       |0       |
-|  u_bus_top                   |ubus_top             |805     |50      |1248    |0       |0       |
-|    u_local_bus_slve_cis      |local_bus_slve_cis   |711     |50      |721     |0       |0       |
-|      u_uart_2dsp             |uart_2dsp            |115     |31      |52      |0       |0       |
+|  u_bus_top                   |ubus_top             |817     |50      |1248    |0       |0       |
+|    u_local_bus_slve_cis      |local_bus_slve_cis   |723     |50      |721     |0       |0       |
+|      u_uart_2dsp             |uart_2dsp            |120     |31      |52      |0       |0       |
 |  u_dpi_mode                  |cdc_sync             |2       |0       |10      |0       |0       |
 |  u_eot                       |cdc_sync             |1       |0       |5       |0       |0       |
 |  u_lv_en_flag                |cdc_sync             |1       |0       |5       |0       |0       |
-|  u_mipi_dphy_tx_wrapper      |mipi_dphy_tx_wrapper |166     |61      |226     |4       |0       |
-|    u_hs_tx_wrapper           |hs_tx_wrapper        |110     |61      |198     |4       |0       |
-|      [0]$u_data_lane_wrapper |data_lane_wrapper    |52      |52      |93      |1       |0       |
-|        u_data_hs_generate    |data_hs_generate     |48      |52      |87      |1       |0       |
+|  u_mipi_dphy_tx_wrapper      |mipi_dphy_tx_wrapper |167     |61      |226     |4       |0       |
+|    u_hs_tx_wrapper           |hs_tx_wrapper        |111     |61      |198     |4       |0       |
+|      [0]$u_data_lane_wrapper |data_lane_wrapper    |54      |52      |93      |1       |0       |
+|        u_data_hs_generate    |data_hs_generate     |50      |52      |87      |1       |0       |
 |          u_dphy_tx_fifo      |dphy_tx_fifo         |2       |0       |0       |1       |0       |
 |            u_d1024_w8_fifo   |d1024_w8_fifo        |2       |0       |0       |1       |0       |
 |        u_data_lp_generate    |data_lp_generate     |4       |0       |6       |0       |0       |
@@ -193,7 +195,7 @@ Report Hierarchy Area:
 |      u_clk_lane_wrapper      |clk_lane_wrapper     |3       |0       |8       |0       |0       |
 |        u_clk_hs_generate     |clk_hs_generate      |3       |0       |4       |0       |0       |
 |        u_clk_lp_generate     |clk_lp_generate      |0       |0       |4       |0       |0       |
-|      u_hs_tx_controler       |hs_tx_controler      |25      |9       |12      |0       |0       |
+|      u_hs_tx_controler       |hs_tx_controler      |24      |9       |12      |0       |0       |
 |  u_mipi_eot_min              |cdc_sync             |20      |0       |65      |0       |0       |
 |  u_mipi_sot_min              |cdc_sync             |20      |0       |65      |0       |0       |
 |  u_pic_cnt                   |cdc_sync             |38      |0       |120     |0       |0       |
@@ -209,7 +211,7 @@ Report Hierarchy Area:
 |  u_pll_lvds                  |pll_lvds             |0       |0       |0       |0       |0       |
 |  u_softrst_done              |cdc_sync             |1       |0       |5       |0       |0       |
 |  u_softrst_fan_ctrl          |cdc_sync             |0       |0       |0       |0       |0       |
-|  ua_lvds_rx                  |lvds_rx              |97      |67      |209     |0       |0       |
-|  ub_lvds_rx                  |lvds_rx              |97      |67      |209     |0       |0       |
+|  ua_lvds_rx                  |lvds_rx              |96      |67      |209     |0       |0       |
+|  ub_lvds_rx                  |lvds_rx              |96      |67      |209     |0       |0       |
 |  uu_pll_lvds                 |pll_lvds             |0       |0       |0       |0       |0       |
 +-------------------------------------------------------------------------------------------------+
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db
index 5cf4c66..d780163 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
index 149becf..feb218a 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.area
@@ -8,7 +8,7 @@ IO Statistics
   #inout                    0
 
 Gate Statistics
-#Basic gates            13950
+#Basic gates            14522
   #and                   2480
   #nand                     0
   #or                    1078
@@ -20,19 +20,19 @@ Gate Statistics
   #bufif1                   5
   #MX21                   615
   #FADD                     0
-  #DFF                   9093
+  #DFF                   9665
   #LATCH                    6
 #MACRO_ADD                497
-#MACRO_EQ                 225
+#MACRO_EQ                 227
 #MACRO_MULT                 4
-#MACRO_MUX               4813
+#MACRO_MUX               4839
 #MACRO_OTHERS              73
 
 Report Hierarchy Area:
 +----------------------------------------------------------------------------+
 |Instance                      |Module               |gates  |seq    |macros |
 +----------------------------------------------------------------------------+
-|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|top                           |huagao_mipi_top      |4851   |9671   |801    |
 |  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
 |    U_crc16_24b               |crc16_24b            |67     |16     |0      |
 |    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
@@ -164,6 +164,8 @@ Report Hierarchy Area:
 |  u0_test_en                  |cdc_sync             |2      |5      |0      |
 |  u1_test_en                  |cdc_sync             |2      |5      |0      |
 |  u2_test_en                  |cdc_sync             |2      |5      |0      |
+|  u_O_clk_lp_n                |cdc_sync             |0      |286    |1      |
+|  u_O_clk_lp_p                |cdc_sync             |0      |286    |1      |
 |  u_a_pclk                    |cdc_sync             |2      |5      |0      |
 |  u_a_sp_sampling             |cdc_sync             |2      |5      |0      |
 |  u_a_sp_sampling_cam         |cdc_sync             |2      |5      |0      |
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db
index a1308c1..671666e 100644
Binary files a/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db and b/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db differ
diff --git a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
index ea888d7..16f8d0b 100644
--- a/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
+++ b/src/prj/td_project/hg_anlogic_Runs/syn_1/run.log
@@ -4,7 +4,7 @@
    Executable = D:/Anlogic/TD5.6.2/bin/td.exe
    Built at =   20:34:38 Mar 21 2023
    Run by =     holdtecs
-   Run Date =   Mon Feb 19 10:56:25 2024
+   Run Date =   Tue Mar 12 14:50:44 2024
 
    Run on =     DESKTOP-5MQL5VE
 ============================================================
@@ -79,9 +79,7 @@ HDL-1007 : analyze verilog file ../../../../hg_mp/fe/exdev_ctl.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/fan_ctrl.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/gen_sp.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl.v
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/rddpram_ctl_rev.v
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sampling_fe_rev.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/fe/sort.v
@@ -99,19 +97,19 @@ HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in .
 HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(150)
 HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(158)
 HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(159)
-HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(698)
-HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(707)
-HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(731)
-HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(733)
-HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(739)
-HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(742)
-HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(913)
-HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1002)
-HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1303)
-HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
-HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1332)
-HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
-HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(720)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(729)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(753)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(755)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(761)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(764)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(935)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1024)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1325)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1354)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
 HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
 HDL-1007 : analyze verilog file ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
@@ -185,8 +183,6 @@ HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog
 HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(61)
 HDL-5007 WARNING: block identifier is required on this block in ../../../../hg_mp/fe/read_ram_addr_rev.v(145)
 HDL-1007 : analyze verilog file ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
 RUN-1001 : Project manager successfully analyzed 61 source files.
 RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
 ARC-1001 : Device Initialization.
@@ -273,16 +269,16 @@ RUN-1001 :      infer_shifter      |     on     |        on        |
 RUN-1001 : --------------------------------------------------------------
 HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(126)
 HDL-1007 : port 'clk2_out' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(142)
-HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(574)
-HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(712)
-HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(937)
-HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
-HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
-HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
-HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
-HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
-HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
-HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-1007 : port 'cnt_trigger' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(596)
+HDL-1007 : port 'debug' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(734)
+HDL-1007 : port 'debug_2' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(959)
+HDL-5007 WARNING: port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'red_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'green_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'blue_times_a' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'red_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'green_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
+HDL-1007 : port 'blue_times_b' remains unconnected for this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
 HDL-1007 : elaborate module huagao_mipi_top in ../../../../hg_mp/drx_top/huagao_mipi_top.v(3)
 HDL-1007 : elaborate module pll in ../../../../hg_mp/anlogic_ip/pll/pll.v(26)
 HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(8)
@@ -296,6 +292,11 @@ HDL-1007 : extracting RAM for identifier '**' in encrypted_text(0)
 HDL-1007 : elaborate module iddr(DEVICE="EG4") in ../../../../hg_mp/lvds_rx/lvds_rx_enc.v(261)
 HDL-1007 : elaborate module EG_LOGIC_IDDR in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(76)
 HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-1007 : elaborate module cdc_sync(DEPTH=20,WIDTH=13) in ../../../../hg_mp/cdc/cdc_sync.v(1)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(356)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(357)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_from' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(366)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 13 for port 'signal_to' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(367)
 HDL-1007 : elaborate module cdc_sync(DEPTH=3) in ../../../../hg_mp/cdc/cdc_sync.v(1)
 HDL-1007 : elaborate module scan_start_diff in ../../../../hg_mp/scan_start/scan_start_diff.v(1)
 HDL-1007 : elaborate module exdev_ctl(YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/exdev_ctl.v(1)
@@ -350,7 +351,6 @@ HDL-1007 : elaborate module SORT_RAM_9k in ../../../../hg_mp/anlogic_ip/sort_ram
 HDL-1007 : elaborate module EG_LOGIC_BRAM(DATA_WIDTH_A=8,DATA_WIDTH_B=8,ADDR_WIDTH_B=10,DATA_DEPTH_A=1024,DATA_DEPTH_B=1024,MODE="PDPW",REGMODE_B="OUTREG") in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(1032)
 HDL-5007 WARNING: actual bit length 2 differs from formal bit length 1 for port 'beb' in ../../../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v(75)
 HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort.v(336)
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl.v(130)
 HDL-1007 : elaborate module rddpram_ctl(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl.v(1)
 HDL-1007 : elaborate module transfer_300_to_200 in ../../../../hg_mp/fe/transfer_300_to_200.v(1)
 HDL-1007 : elaborate module SORT_RAM_200DPI in ../../../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v(14)
@@ -374,23 +374,21 @@ HDL-1007 : elaborate module read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,P
 HDL-1007 : elaborate module read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11) in ../../../../hg_mp/fe/read_ram_addr_rev.v(1)
 HDL-5007 WARNING: using initial value of 'add_mem' since it is never assigned in ../../../../hg_mp/fe/read_ram_addr_rev.v(40)
 HDL-5007 WARNING: actual bit length 1 differs from formal bit length 12 for port 'rd_done_set' in ../../../../hg_mp/fe/sort_rev.v(368)
-HDL-5007 WARNING: 'pclk' is not declared in ../../../../hg_mp/fe/rddpram_ctl_rev.v(130)
 HDL-1007 : elaborate module rddpram_ctl_rev(RADDR_WIDTH=13,YPIXEL_WIDTH=22) in ../../../../hg_mp/fe/rddpram_ctl_rev.v(1)
 HDL-5007 WARNING: net 'q_a1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(72)
 HDL-5007 WARNING: net 'q_b1[23]' does not have a driver in ../../../../hg_mp/fe/sort_rev.v(74)
-HDL-1007 : port 'reg2nd_21' remains unconnected for this instance in ../../../../hg_mp/local_bus/ubus_top.v(207)
 HDL-1007 : elaborate module ubus_top in ../../../../hg_mp/local_bus/ubus_top.v(1)
 HDL-1007 : elaborate module local_bus_slve_cis in ../../../../hg_mp/local_bus/local_bus_slve_cis.v(3)
 HDL-1007 : elaborate module CRC4_D16 in ../../../../hg_mp/local_bus/CRC4_D16.v(7)
 HDL-1007 : elaborate module uart_2dsp in ../../../../hg_mp/local_bus/uart_2dsp_6M_921600.v(1)
-HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 18 for port 'vsp_config' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1336)
 HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=2) in ../../../../hg_mp/cdc/cdc_sync.v(1)
 HDL-1007 : elaborate module rgb_to_csi_pakage in ../../../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v(16)
 HDL-1007 : elaborate module crc16_24b in ../../../../hg_mp/mipi_dphy_tx/crc16_24b.v(3)
 HDL-1007 : elaborate module fifo_w32_d8192 in ../../../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v(14)
 HDL-1007 : elaborate module EG_LOGIC_RAMFIFO(DATA_WIDTH=32,ADDR_WIDTH=12) in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(793)
 HDL-1007 : elaborate module ecc_gen in ../../../../hg_mp/mipi_dphy_tx/ecc_gen.v(12)
-HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1393)
+HDL-5007 WARNING: actual bit length 17 differs from formal bit length 16 for port 'IMAGE_LINE_NUM' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1415)
 HDL-1007 : elaborate module mipi_dphy_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v(3)
 HDL-1007 : elaborate module hs_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(1)
 HDL-1007 : elaborate module hs_tx_controler(T_DATA_LPX=4,T_DATA_HS_PREPARE=4,T_DATA_HS_ZERO=10,T_DATA_HS_TRAIL=10,T_CLK_LPX=4,T_CLK_PREPARE=4,T_CLK_ZERO=10,T_CLK_PRE=10,T_CLK_POST=10,T_CLK_TRAIL=10) in ../../../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(3)
@@ -407,24 +405,24 @@ HDL-1007 : elaborate module EG_LOGIC_FIFO(DATA_WIDTH_W=8,DATA_WIDTH_R=8,DATA_DEP
 HDL-1007 : elaborate module EG_LOGIC_ODDRx2 in D:/Anlogic/TD5.6.2/arch/eagle_macro.v(117)
 HDL-1007 : elaborate module lp_tx_wrapper in ../../../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(2)
 HDL-1007 : elaborate module dphy_tx_fifo(DRAM_DEPTH=100) in ../../../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v(1)
-HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1476)
+HDL-5007 WARNING: actual bit length 32 differs from formal bit length 8 for port 'I_lp_tx_data' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1498)
 HDL-1007 : elaborate module pixel_cdc in ../../../../hg_mp/pixel_cdc/pixel_cdc.v(1)
 HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=22) in ../../../../hg_mp/cdc/cdc_sync.v(1)
 HDL-1007 : elaborate module cdc_sync(DEPTH=3,WIDTH=16) in ../../../../hg_mp/cdc/cdc_sync.v(1)
-HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-5007 WARNING: actual bit length 1 differs from formal bit length 16 for port 'cis_frame_num' in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1536)
 HDL-1007 : elaborate module lscc_sensor in ../../../../hg_mp/sensor_lane/lscc_sensor.v(1)
 HDL-1007 : elaborate module fan_ctrl in ../../../../hg_mp/fe/fan_ctrl.v(1)
 HDL-5007 WARNING: net 'S_hsync_nc' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(102)
-HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1910)
-HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1276)
+HDL-5007 WARNING: net 'clk_22m' does not have a driver in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1932)
+HDL-5007 WARNING: input port 'clk125m_a' is not connected on this instance in ../../../../hg_mp/drx_top/huagao_mipi_top.v(1298)
 HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
 HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
 HDL-5001 WARNING: Contains anonymous inst(s) and/or net(s) that have not been renamed
 HDL-1200 : Current top model is huagao_mipi_top
 HDL-1100 : Inferred 1 RAMs.
-RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.112400s wall, 1.109375s user + 0.000000s system = 1.109375s CPU (99.7%)
+RUN-1003 : finish command "elaborate -top huagao_mipi_top" in  1.071047s wall, 1.031250s user + 0.046875s system = 1.078125s CPU (100.7%)
 
-RUN-1004 : used memory is 193 MB, reserved memory is 171 MB, peak memory is 234 MB
+RUN-1004 : used memory is 202 MB, reserved memory is 177 MB, peak memory is 243 MB
 RUN-1002 : start command "export_db hg_anlogic_elaborate.db"
 RUN-1001 : Exported /
 RUN-1001 : Exported flow parameters
@@ -492,10 +490,11 @@ RUN-1002 : start command "set_pin_assignment  rxd_dsp   LOCATION = P144; IOSTAND
 RUN-1002 : start command "set_pin_assignment  txd_dsp   LOCATION = P145; IOSTANDARD = LVCMOS33; DRIVESTRENGTH = 8; PULLTYPE = NONE; "
 RUN-1002 : start command "set_inst_assignment u_pll/pll_inst location = x40y0z0;"
 RUN-1002 : start command "create_bound  bound2  -mode fixed -width 25 -height 25 -origin  0 0 "
-RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 20 -origin  23 0 "
+RUN-1002 : start command "create_bound  bound3  -mode fixed -width 18 -height 30 -origin  23 0 "
 RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  u_mipi_dphy_tx_wrapper "
 RUN-1002 : start command "add_cells_to_bound -bound  bound2  -cells  U_rgb_to_csi_pakage "
 RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper "
+RUN-1002 : start command "add_cells_to_bound -bound  bound3  -cells  u_mipi_dphy_tx_wrapper/u_lp_tx_wrapper "
 RUN-1001 : Starting of IO setups legality check.
 RUN-1001 : Starting of IO setups legality check.
 RUN-1001 : Starting of IO vref setups legality check.
@@ -604,6 +603,7 @@ SYN-1012 : SanityCheck: Model "read_ram_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBU
 SYN-1012 : SanityCheck: Model "read_ram_addr_rev(PBUFF_ADDR_WIDTH=10,RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
 SYN-1012 : SanityCheck: Model "read_ram_data_rev(RD_DONE_WIDTH=12,PBUFF_TAP_NUM=3,PBUFF_RAM_NUM=11)"
 SYN-1012 : SanityCheck: Model "scan_start_diff"
+SYN-1012 : SanityCheck: Model "cdc_sync(DEPTH=20,WIDTH=13)"
 SYN-1012 : SanityCheck: Model "ubus_top"
 SYN-1012 : SanityCheck: Model "local_bus_slve_cis"
 SYN-1012 : SanityCheck: Model "CRC4_D16"
@@ -653,15 +653,17 @@ RUN-1001 :     ua_lvds_rx    |      false       |           lvds_rx            |
 RUN-1001 :     ub_lvds_rx    |      false       |           lvds_rx            |  ../../../../hg_mp/drx_t...  
 RUN-1001 :   u_mipi_eot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
 RUN-1001 :   u_mipi_sot_min  |       true       |  cdc_sync(DEPTH=3,WIDTH=13)  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :    u_O_clk_lp_p   |       true       |  cdc_sync(DEPTH=20,WIDTH...  |  ../../../../hg_mp/drx_t...  
+RUN-1001 :    u_O_clk_lp_n   |       true       |  cdc_sync(DEPTH=20,WIDTH...  |  ../../../../hg_mp/drx_t...  
 RUN-1001 : ------------------------------------------------------------------------------------------------
-SYN-1032 : 53909/19207 useful/useless nets, 20692/1826 useful/useless insts
+SYN-1032 : 55777/19243 useful/useless nets, 21967/1798 useful/useless insts
 SYN-1001 : Optimize 156 less-than instances
-SYN-1016 : Merged 38313 instances.
+SYN-1016 : Merged 38316 instances.
 SYN-1025 : Merged 24 RAM ports.
 SYN-1027 : Infer Logic DRAM(ua_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
 SYN-1027 : Infer Logic DRAM(ub_lvds_rx/ramread0_syn_6) read 8x35, write 8x35
 SYN-1023 : Infer 2 Logic DRAMs, 0 Logic BRAMs.
-SYN-1032 : 42440/8976 useful/useless nets, 10974/4743 useful/useless insts
+SYN-1032 : 44304/8976 useful/useless nets, 12214/4743 useful/useless insts
 SYN-1016 : Merged 1876 instances.
 SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_2", d: "exdev_ctl_a/u_ADconfig/cnt_sdi[0]", q: "exdev_ctl_a/u_ADconfig/addr[0]" // ../../../../hg_mp/fe/AD_config.v(203)
 SYN-5015 WARNING: Found latch in "huagao_mipi_top", name: "exdev_ctl_a/u_ADconfig/reg5_syn_3", d: "exdev_ctl_a/u_ADconfig/cnt_sdi_b6[1]", q: "exdev_ctl_a/u_ADconfig/addr[1]" // ../../../../hg_mp/fe/AD_config.v(203)
@@ -1173,7 +1175,7 @@ SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/fe/fan_ctrl.v(16
 SYN-5014 WARNING: the net's pin: pin "clk" in ../../../../hg_mp/cdc/cdc_sync.v(19)
 SYN-5014 Similar messages will be suppressed.
 SYN-5025 WARNING: Using 0 for all undriven pins and nets
-SYN-1032 : 40113/363 useful/useless nets, 37310/558 useful/useless insts
+SYN-1032 : 41977/363 useful/useless nets, 39174/558 useful/useless insts
 SYN-1014 : Optimize round 1
 SYN-1017 : Remove 16 const input seq instances
 SYN-1002 :     U_rgb_to_csi_pakage/reg0_syn_12
@@ -1199,10 +1201,10 @@ SYN-1020 : Optimized 3951 distributor mux.
 SYN-1001 : Optimize 12 less-than instances
 SYN-1019 : Optimized 39 mux instances.
 SYN-1016 : Merged 6256 instances.
-SYN-1015 : Optimize round 1, 29880 better
+SYN-1015 : Optimize round 1, 30452 better
 SYN-1014 : Optimize round 2
 SYN-1044 : Optimized 15 inv instances.
-SYN-1032 : 25775/1547 useful/useless nets, 23064/7583 useful/useless insts
+SYN-1032 : 27603/1547 useful/useless nets, 24892/7583 useful/useless insts
 SYN-1017 : Remove 29 const input seq instances
 SYN-1002 :     reg18_syn_2
 SYN-1002 :     reg22_syn_2
@@ -1237,7 +1239,7 @@ SYN-1019 : Optimized 24 mux instances.
 SYN-1020 : Optimized 43 distributor mux.
 SYN-1016 : Merged 118 instances.
 SYN-1015 : Optimize round 2, 9427 better
-SYN-1032 : 25526/80 useful/useless nets, 22847/112 useful/useless insts
+SYN-1032 : 27354/80 useful/useless nets, 24675/112 useful/useless insts
 SYN-3004 : Optimized 2 const0 DFF(s)
 SYN-3004 : Optimized 8 const0 DFF(s)
 SYN-3008 : Optimized 1 const1 DFF(s)
@@ -1304,20 +1306,20 @@ SYN-3003 : Optimized 1 equivalent DFF(s)
 SYN-3003 : Optimized 1 equivalent DFF(s)
 SYN-3003 : Optimized 1 equivalent DFF(s)
 SYN-3004 : Optimized 2 const0 DFF(s)
-SYN-1032 : 25433/93 useful/useless nets, 22765/6 useful/useless insts
+SYN-1032 : 27261/93 useful/useless nets, 24593/6 useful/useless insts
 SYN-1014 : Optimize round 1
 SYN-1019 : Optimized 228 mux instances.
 SYN-1020 : Optimized 2 distributor mux.
 SYN-1016 : Merged 3 instances.
 SYN-1015 : Optimize round 1, 279 better
 SYN-1014 : Optimize round 2
-SYN-1032 : 25155/20 useful/useless nets, 22503/2 useful/useless insts
+SYN-1032 : 26983/20 useful/useless nets, 24331/2 useful/useless insts
 SYN-1015 : Optimize round 2, 2 better
 SYN-1014 : Optimize round 3
 SYN-1015 : Optimize round 3, 0 better
-RUN-1003 : finish command "optimize_rtl" in  18.908404s wall, 16.984375s user + 1.906250s system = 18.890625s CPU (99.9%)
+RUN-1003 : finish command "optimize_rtl" in  19.481519s wall, 16.921875s user + 2.562500s system = 19.484375s CPU (100.0%)
 
-RUN-1004 : used memory is 331 MB, reserved memory is 303 MB, peak memory is 349 MB
+RUN-1004 : used memory is 340 MB, reserved memory is 308 MB, peak memory is 359 MB
 RUN-1002 : start command "report_area -file hg_anlogic_rtl.area"
 RUN-1001 : standard
 ***Report Model: huagao_mipi_top Device: EG4D20EG176***
@@ -1329,7 +1331,7 @@ IO Statistics
   #inout                    0
 
 Gate Statistics
-#Basic gates            13950
+#Basic gates            14522
   #and                   2480
   #nand                     0
   #or                    1078
@@ -1341,19 +1343,19 @@ Gate Statistics
   #bufif1                   5
   #MX21                   615
   #FADD                     0
-  #DFF                   9093
+  #DFF                   9665
   #LATCH                    6
 #MACRO_ADD                497
-#MACRO_EQ                 225
+#MACRO_EQ                 227
 #MACRO_MULT                 4
-#MACRO_MUX               4813
+#MACRO_MUX               4839
 #MACRO_OTHERS              73
 
 Report Hierarchy Area:
 +----------------------------------------------------------------------------+
 |Instance                      |Module               |gates  |seq    |macros |
 +----------------------------------------------------------------------------+
-|top                           |huagao_mipi_top      |4851   |9099   |799    |
+|top                           |huagao_mipi_top      |4851   |9671   |801    |
 |  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |218    |351    |15     |
 |    U_crc16_24b               |crc16_24b            |67     |16     |0      |
 |    U_ecc_gen                 |ecc_gen              |37     |6      |0      |
@@ -1472,9 +1474,9 @@ RUN-1001 : Exported congestions
 RUN-1001 : Exported violations
 RUN-1001 : Exported IO constraints
 RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.053069s wall, 1.656250s user + 0.078125s system = 1.734375s CPU (164.7%)
+RUN-1003 : finish command "export_db hg_anlogic_rtl.db" in  1.122930s wall, 1.734375s user + 0.031250s system = 1.765625s CPU (157.2%)
 
-RUN-1004 : used memory is 326 MB, reserved memory is 301 MB, peak memory is 399 MB
+RUN-1004 : used memory is 336 MB, reserved memory is 306 MB, peak memory is 410 MB
 RUN-1002 : start command "read_sdc ../../hg_anlogic.sdc"
 RUN-1002 : start command "get_ports clock_source"
 RUN-1002 : start command "create_clock -name clock_source -period 41.666 -waveform 0 20.833 "
@@ -1512,8 +1514,26 @@ RUN-1002 : start command "create_generated_clock -name b_sclk -source  -master_c
 RUN-1002 : start command "get_ports clock_source"
 RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
 RUN-1002 : start command "create_generated_clock -name clk_adc -source  -master_clock clock_source -divide_by 4 -phase 0 "
-RUN-1002 : start command "get_regs u_pixel_cdc/multipy_xy[*]"
-RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/signal_to[*]"
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_mipi_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_mipi_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clka_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clka_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clkb_cis_total_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clkb_cis_total_num/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_mipi_pixel_y/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_mipi_pixel_y/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_pixel_cdc/u_clk_cis_frame_num/signal_from[*]"
+RUN-1002 : start command "get_regs u_pixel_cdc/u_clk_cis_frame_num/temp[*]"
 RUN-1002 : start command "set_false_path -from  -to "
 RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
 RUN-1002 : start command "get_nets u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d"
@@ -1530,6 +1550,12 @@ RUN-1002 : start command "set_false_path -from  -to "
 RUN-1002 : start command "get_regs clkubus_rstn"
 RUN-1002 : start command "get_nets b_pclk_rstn"
 RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_p/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_p/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
+RUN-1002 : start command "get_nets u_O_clk_lp_n/signal_from[*]"
+RUN-1002 : start command "get_regs u_O_clk_lp_n/temp[*]"
+RUN-1002 : start command "set_false_path -from  -to "
 RUN-1002 : start command "optimize_gate -maparea hg_anlogic_gate.area"
 RUN-1001 : Open license file D:/Anlogic/TD5.6.2/license/Anlogic.lic
 RUN-1001 : Print Global Property
@@ -1564,7 +1590,7 @@ RUN-1001 :            report           |  standard  |     standard     |
 RUN-1001 :           retiming          |    off     |       off        |        
 RUN-1001 : ------------------------------------------------------------------
 SYN-2001 : Map 61 IOs to PADs
-SYN-1032 : 25189/24 useful/useless nets, 22552/26 useful/useless insts
+SYN-1032 : 27017/24 useful/useless nets, 24380/26 useful/useless insts
 RUN-1002 : start command "update_pll_param -module huagao_mipi_top"
 SYN-2501 : Processed 0 LOGIC_BUF instances.
 SYN-2501 : 3 BUFG to GCLK
@@ -1628,7 +1654,7 @@ SYN-2531 : Dram(ua_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
 SYN-2531 : Dram(ub_lvds_rx/ramread0_syn_6) write 8x35, read 8x35
 SYN-2571 : Map 4 macro multiplier
 SYN-2571 : Optimize after map_dsp, round 1
-SYN-1032 : 25507/670 useful/useless nets, 22886/580 useful/useless insts
+SYN-1032 : 27335/670 useful/useless nets, 24714/580 useful/useless insts
 SYN-1016 : Merged 11 instances.
 SYN-2571 : Optimize after map_dsp, round 1, 1181 better
 SYN-2571 : Optimize after map_dsp, round 2
@@ -1636,7 +1662,7 @@ SYN-2571 : Optimize after map_dsp, round 2, 0 better
 SYN-1001 : Throwback 317 control mux instances
 SYN-1001 : Convert 12 adder
 SYN-2501 : Optimize round 1
-SYN-1032 : 28943/338 useful/useless nets, 26323/38 useful/useless insts
+SYN-1032 : 30821/338 useful/useless nets, 28201/38 useful/useless insts
 SYN-1016 : Merged 396 instances.
 SYN-2501 : Optimize round 1, 1774 better
 SYN-2501 : Optimize round 2
@@ -1667,30 +1693,30 @@ SYN-3001 : Mapper mapped 15 instances into 1 LUTs, name keeping = 100%.
 SYN-2501 : Inferred 22 ROM instances
 SYN-1019 : Optimized 9690 mux instances.
 SYN-1016 : Merged 12105 instances.
-SYN-1032 : 36487/296 useful/useless nets, 33761/0 useful/useless insts
+SYN-1032 : 38365/296 useful/useless nets, 35639/0 useful/useless insts
 RUN-1002 : start command "start_timer -prepack"
 TMR-2505 : Start building timing graph for model huagao_mipi_top.
-TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 121685, tnet num: 36489, tinst num: 33761, tnode num: 155649, tedge num: 179150.
+TMR-2506 : Build timing graph completely. Port num: 37, tpin num: 126687, tnet num: 38367, tinst num: 35639, tnode num: 164251, tedge num: 187234.
 TMR-2508 : Levelizing timing graph completed, there are 89 levels in total.
 TMR-2501 : Timing graph initialized successfully.
-RUN-1003 : finish command "start_timer -prepack" in  1.303515s wall, 1.281250s user + 0.031250s system = 1.312500s CPU (100.7%)
+RUN-1003 : finish command "start_timer -prepack" in  1.326087s wall, 1.281250s user + 0.046875s system = 1.328125s CPU (100.2%)
 
-RUN-1004 : used memory is 517 MB, reserved memory is 495 MB, peak memory is 517 MB
+RUN-1004 : used memory is 536 MB, reserved memory is 512 MB, peak memory is 536 MB
 TMR-2503 : Start to update net delay, extr mode = 2.
-TMR-2504 : Update delay of 36489 nets completely.
+TMR-2504 : Update delay of 38367 nets completely.
 TMR-2502 : Annotate delay completely, extr mode = 2.
 TMR-3001 : Initiate 12 clocks from SDC.
-TMR-3004 : Map sdc constraints, there are 6 constraints in total.
+TMR-3004 : Map sdc constraints, there are 14 constraints in total.
 TMR-3003 : Constraints initiated successfully.
 TMR-3501 : Forward propagation: start to calculate arrival time...
 TMR-3502 : Backward propagation: start to calculate required time...
 TMR-3503 : Timing propagation completes.
 SYN-3001 : Running gate level optimization.
-SYN-2581 : Mapping with K=5, #lut = 7497 (3.86), #lev = 10 (3.14)
+SYN-2581 : Mapping with K=5, #lut = 7521 (3.86), #lev = 9 (3.15)
 SYN-2551 : Post LUT mapping optimization.
-SYN-2581 : Mapping with K=5, #lut = 7359 (3.96), #lev = 7 (3.05)
-SYN-3001 : Logic optimization runtime opt =   1.20 sec, map =   0.00 sec
-SYN-3001 : Mapper mapped 18916 instances into 7387 LUTs, name keeping = 58%.
+SYN-2581 : Mapping with K=5, #lut = 7427 (3.95), #lev = 7 (3.06)
+SYN-3001 : Logic optimization runtime opt =   1.25 sec, map =   0.00 sec
+SYN-3001 : Mapper mapped 18994 instances into 7455 LUTs, name keeping = 58%.
 SYN-3001 : Mapper removed 2 lut buffers
 RUN-1002 : start command "report_area -file hg_anlogic_gate.area"
 RUN-1001 : standard
@@ -1703,16 +1729,16 @@ IO Statistics
   #inout                    0
 
 LUT Statistics
-#Total_luts              9962
-  #lut4                  5231
-  #lut5                  2176
+#Total_luts             10030
+  #lut4                  5343
+  #lut5                  2132
   #lut6                     0
   #lut5_mx41                0
   #lut4_alu1b            2555
 
 Utilization Statistics
-#lut                     9962   out of  19600   50.83%
-#reg                     9173   out of  19600   46.80%
+#lut                    10030   out of  19600   51.17%
+#reg                     9745   out of  19600   49.72%
 #le                         0
 #dsp                        3   out of     29   10.34%
 #bram                      54   out of     64   84.38%
@@ -1730,30 +1756,30 @@ Report Hierarchy Area:
 +-------------------------------------------------------------------------------------------------+
 |Instance                      |Module               |lut     |ripple  |seq     |bram    |dsp     |
 +-------------------------------------------------------------------------------------------------+
-|top                           |huagao_mipi_top      |7407    |2555    |9205    |58      |3       |
-|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |342     |81      |441     |4       |1       |
+|top                           |huagao_mipi_top      |7475    |2555    |9777    |58      |3       |
+|  U_rgb_to_csi_pakage         |rgb_to_csi_pakage    |336     |81      |441     |4       |1       |
 |    U_crc16_24b               |crc16_24b            |50      |0       |16      |0       |0       |
 |    U_ecc_gen                 |ecc_gen              |10      |0       |6       |0       |0       |
 |    U_fifo_w32_d8192          |fifo_w32_d8192       |53      |14      |90      |4       |0       |
-|  exdev_ctl_a                 |exdev_ctl            |282     |234     |559     |0       |0       |
-|    u_ADconfig                |AD_config            |99      |49      |138     |0       |0       |
-|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
-|  exdev_ctl_b                 |exdev_ctl            |274     |234     |546     |0       |0       |
-|    u_ADconfig                |AD_config            |91      |49      |125     |0       |0       |
-|    u_gen_sp                  |gen_sp               |125     |185     |104     |0       |0       |
-|  sampling_fe_a               |sampling_fe          |2317    |738     |1919    |25      |0       |
+|  exdev_ctl_a                 |exdev_ctl            |283     |234     |559     |0       |0       |
+|    u_ADconfig                |AD_config            |98      |49      |138     |0       |0       |
+|    u_gen_sp                  |gen_sp               |127     |185     |104     |0       |0       |
+|  exdev_ctl_b                 |exdev_ctl            |277     |234     |546     |0       |0       |
+|    u_ADconfig                |AD_config            |93      |49      |125     |0       |0       |
+|    u_gen_sp                  |gen_sp               |126     |185     |104     |0       |0       |
+|  sampling_fe_a               |sampling_fe          |2334    |738     |1919    |25      |0       |
 |    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
 |    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
 |      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
-|    u_sort                    |sort                 |2247    |691     |1737    |25      |0       |
+|    u_sort                    |sort                 |2264    |691     |1737    |25      |0       |
 |      rddpram_ctl             |rddpram_ctl          |1       |0       |5       |0       |0       |
 |        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
-|      u_data_prebuffer        |data_prebuffer       |1906    |615     |1391    |22      |0       |
+|      u_data_prebuffer        |data_prebuffer       |1922    |615     |1391    |22      |0       |
 |        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
 |        fifo_adc              |fifo_adc             |51      |24      |41      |0       |0       |
-|        ram_switch            |ram_switch           |1466    |422     |1023    |0       |0       |
+|        ram_switch            |ram_switch           |1483    |422     |1023    |0       |0       |
 |          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
 |            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
 |            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
@@ -1765,10 +1791,10 @@ Report Hierarchy Area:
 |            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |          insert              |insert               |265     |323     |692     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |1072    |0       |216     |0       |0       |
-|        read_ram_i            |read_ram             |207     |158     |164     |0       |0       |
-|          read_ram_addr       |read_ram_addr        |177     |145     |127     |0       |0       |
-|          read_ram_data       |read_ram_data        |29      |13      |32      |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1089    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram             |206     |158     |164     |0       |0       |
+|          read_ram_addr       |read_ram_addr        |173     |145     |127     |0       |0       |
+|          read_ram_data       |read_ram_data        |32      |13      |32      |0       |0       |
 |          u0_rdsoft_n         |cdc_sync             |1       |0       |5       |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
@@ -1795,19 +1821,19 @@ Report Hierarchy Area:
 |      u_transfer_300_to_200   |transfer_300_to_200  |128     |76      |276     |3       |0       |
 |        u0_soft_n             |cdc_sync             |1       |0       |5       |0       |0       |
 |        u_SORT_RAM_200DPI     |SORT_RAM_200DPI      |0       |0       |0       |3       |0       |
-|  sampling_fe_b               |sampling_fe_rev      |2335    |751     |1936    |25      |1       |
+|  sampling_fe_b               |sampling_fe_rev      |2334    |751     |1936    |25      |1       |
 |    u0_soft_n                 |cdc_sync             |1       |0       |5       |0       |0       |
 |    u_ad_sampling             |ad_sampling          |39      |47      |147     |0       |0       |
 |      u0_soft_n               |cdc_sync             |1       |0       |5       |0       |0       |
-|    u_sort                    |sort_rev             |2265    |704     |1754    |25      |1       |
+|    u_sort                    |sort_rev             |2264    |704     |1754    |25      |1       |
 |      rddpram_ctl             |rddpram_ctl_rev      |1       |0       |5       |0       |0       |
 |        u0_rdsoft_n           |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_rdsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
 |      u0_wrsoft_n             |cdc_sync             |1       |0       |5       |0       |0       |
-|      u_data_prebuffer_rev    |data_prebuffer_rev   |1924    |628     |1408    |22      |1       |
+|      u_data_prebuffer_rev    |data_prebuffer_rev   |1925    |628     |1408    |22      |1       |
 |        channelPart           |channel_part_8478    |146     |11      |144     |0       |0       |
 |        fifo_adc              |fifo_adc             |51      |24      |41      |0       |1       |
-|        ram_switch            |ram_switch           |1479    |422     |1023    |0       |0       |
+|        ram_switch            |ram_switch           |1484    |422     |1023    |0       |0       |
 |          adc_addr_gen        |adc_addr_gen         |129     |99      |115     |0       |0       |
 |            [0]$ch_addr_gen   |ch_addr_gen          |1       |11      |11      |0       |0       |
 |            [1]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
@@ -1819,10 +1845,10 @@ Report Hierarchy Area:
 |            [7]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |            [8]$ch_addr_gen   |ch_addr_gen          |13      |11      |11      |0       |0       |
 |          insert              |insert               |265     |323     |692     |0       |0       |
-|          ram_switch_state    |ram_switch_state     |1085    |0       |216     |0       |0       |
-|        read_ram_i            |read_ram_rev         |210     |171     |181     |0       |0       |
-|          read_ram_addr       |read_ram_addr_rev    |181     |145     |139     |0       |0       |
-|          read_ram_data       |read_ram_data_rev    |29      |26      |42      |0       |0       |
+|          ram_switch_state    |ram_switch_state     |1090    |0       |216     |0       |0       |
+|        read_ram_i            |read_ram_rev         |206     |171     |181     |0       |0       |
+|          read_ram_addr       |read_ram_addr_rev    |180     |145     |139     |0       |0       |
+|          read_ram_data       |read_ram_data_rev    |26      |26      |42      |0       |0       |
 |        u0_sort_ram_a_0       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_a_1       |SORT_RAM_9k          |1       |0       |0       |1       |0       |
 |        u0_sort_ram_a_10      |SORT_RAM_9k          |1       |0       |0       |1       |0       |
@@ -1838,7 +1864,7 @@ SYN-1001 : Packing model "huagao_mipi_top" ...
 SYN-4010 : Pack lib has 55 rtl pack models with 25 top pack blocks
 SYN-1014 : Optimize round 1
 SYN-1015 : Optimize round 1, 0 better
-SYN-4002 : Packing 9173 DFF/LATCH to SEQ ...
+SYN-4002 : Packing 9745 DFF/LATCH to SEQ ...
 SYN-4009 : Pack 83 carry chain into lslice
 SYN-4007 : Packing 1278 adder to BLE ...
 SYN-4008 : Packed 1278 adder and 126 SEQ to BLE.
@@ -1846,9 +1872,9 @@ SYN-4007 : Packing 0 gate4 to BLE ...
 SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
 SYN-4012 : Packed 0 FxMUX
 SYN-4013 : Packed 16 DRAM and 4 SEQ.
-RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  61.071613s wall, 60.671875s user + 0.375000s system = 61.046875s CPU (100.0%)
+RUN-1003 : finish command "optimize_gate -maparea hg_anlogic_gate.area" in  60.377693s wall, 59.921875s user + 0.453125s system = 60.375000s CPU (100.0%)
 
-RUN-1004 : used memory is 394 MB, reserved memory is 379 MB, peak memory is 699 MB
+RUN-1004 : used memory is 399 MB, reserved memory is 376 MB, peak memory is 726 MB
 RUN-1002 : start command "legalize_phy_inst"
 SYN-1011 : Flatten model huagao_mipi_top
 SYN-1001 : ADC: Instance "u_pll/pll_inst" LOCATION="X40Y0Z0"
@@ -1868,8 +1894,8 @@ RUN-1001 : Exported violations
 RUN-1001 : Exported timing constraints
 RUN-1001 : Exported IO constraints
 RUN-1001 : Exported Inst constraints
-RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.555646s wall, 2.687500s user + 0.031250s system = 2.718750s CPU (174.8%)
+RUN-1003 : finish command "export_db hg_anlogic_gate.db" in  1.605917s wall, 2.781250s user + 0.015625s system = 2.796875s CPU (174.2%)
 
-RUN-1004 : used memory is 403 MB, reserved memory is 384 MB, peak memory is 699 MB
-RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240219_105625.log"
+RUN-1004 : used memory is 415 MB, reserved memory is 399 MB, peak memory is 726 MB
+RUN-1002 : start command "backup_run_log run.log ../.logs/syn_1/td_20240312_145044.log"
 RUN-1001 : Backing up run's log file succeed.
diff --git a/src/prj/td_project/td_2024-03-11_09-44-52.log b/src/prj/td_project/td_2024-03-11_09-44-52.log
new file mode 100644
index 0000000..62d1649
--- /dev/null
+++ b/src/prj/td_project/td_2024-03-11_09-44-52.log
@@ -0,0 +1,4396 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 09:44:52 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 589 feed throughs used by 429 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  11.542757s wall, 11.421875s user + 0.468750s system = 11.890625s CPU (103.0%)
+
+RUN-1004 : used memory is 866 MB, reserved memory is 853 MB, peak memory is 879 MB
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-6001 WARNING: Failed to reset phy_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1
+RUN-6001 WARNING: Failed to reset syn_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 589 feed throughs used by 429 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.669880s wall, 8.625000s user + 0.421875s system = 9.046875s CPU (104.3%)
+
+RUN-1004 : used memory is 928 MB, reserved memory is 917 MB, peak memory is 943 MB
+TMR-3509 : Import timing summary.
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+TMR-3509 : Import timing summary.
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 589 feed throughs used by 429 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.677137s wall, 8.640625s user + 0.312500s system = 8.953125s CPU (103.2%)
+
+RUN-1004 : used memory is 1105 MB, reserved memory is 1071 MB, peak memory is 1281 MB
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 564 feed throughs used by 411 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.895754s wall, 8.750000s user + 0.437500s system = 9.187500s CPU (103.3%)
+
+RUN-1004 : used memory is 1108 MB, reserved memory is 1079 MB, peak memory is 1281 MB
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 564 feed throughs used by 437 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.850721s wall, 8.828125s user + 0.359375s system = 9.187500s CPU (103.8%)
+
+RUN-1004 : used memory is 1113 MB, reserved memory is 1086 MB, peak memory is 1281 MB
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 596 feed throughs used by 432 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.888462s wall, 8.750000s user + 0.296875s system = 9.046875s CPU (101.8%)
+
+RUN-1004 : used memory is 1129 MB, reserved memory is 1106 MB, peak memory is 1281 MB
+TMR-3509 : Import timing summary.
+RUN-1001 : End prepare routing data:  0.308900s wall, 0.296875s user + 0.000000s system = 0.296875s CPU (96.1%)
+
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 596 feed throughs used by 432 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.673278s wall, 8.609375s user + 0.437500s system = 9.046875s CPU (104.3%)
+
+RUN-1004 : used memory is 1170 MB, reserved memory is 1149 MB, peak memory is 1281 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.449142s wall, 0.265625s user + 0.437500s system = 0.703125s CPU (4.0%)
+
+RUN-1004 : used memory is 1200 MB, reserved memory is 1174 MB, peak memory is 1281 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.660448s wall, 0.359375s user + 0.500000s system = 0.859375s CPU (4.9%)
+
+RUN-1004 : used memory is 1200 MB, reserved memory is 1174 MB, peak memory is 1281 MB
+GUI-1001 : Downloading succeeded!
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 589 feed throughs used by 429 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.746056s wall, 8.703125s user + 0.296875s system = 9.000000s CPU (102.9%)
+
+RUN-1004 : used memory is 1211 MB, reserved memory is 1186 MB, peak memory is 1281 MB
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.591395s wall, 0.171875s user + 0.562500s system = 0.734375s CPU (4.2%)
+
+RUN-1004 : used memory is 1217 MB, reserved memory is 1192 MB, peak memory is 1281 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.804709s wall, 0.281250s user + 0.562500s system = 0.843750s CPU (4.7%)
+
+RUN-1004 : used memory is 1217 MB, reserved memory is 1192 MB, peak memory is 1281 MB
+GUI-1001 : Downloading succeeded!
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : open_run syn_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_gate.db" in  2.579175s wall, 2.515625s user + 0.125000s system = 2.640625s CPU (102.4%)
+
+RUN-1004 : used memory is 895 MB, reserved memory is 881 MB, peak memory is 1281 MB
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 561 feed throughs used by 419 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.573583s wall, 8.609375s user + 0.328125s system = 8.937500s CPU (104.2%)
+
+RUN-1004 : used memory is 1229 MB, reserved memory is 1207 MB, peak memory is 1281 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.485000s wall, 0.250000s user + 0.437500s system = 0.687500s CPU (3.9%)
+
+RUN-1004 : used memory is 1234 MB, reserved memory is 1209 MB, peak memory is 1281 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.700383s wall, 0.406250s user + 0.453125s system = 0.859375s CPU (4.9%)
+
+RUN-1004 : used memory is 1234 MB, reserved memory is 1209 MB, peak memory is 1281 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "svfgen -scan_mode prog_spi -level 1 -bin C:/Users/shuyou/Desktop/G100_37240223_1425_double_paper_m3_delay_svn12.bin -svf al_devicechain/hg_anlogic_L1.svf -opt no_comment -tool tde -bg_mode no -len_mode normal -rf_mode yes -bypass 11111111 -freq 1MHz"
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d1' directly in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d2' directly in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d3' directly in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d1' directly in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d2' directly in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: cannot access memory 'ram_en_sync_d1' directly in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d3' directly in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: cannot access memory 'ram_en_sync_d2' directly in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : Verilog file '../../hg_mp/fe/prebuffer.v' ignored due to errors
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d1' directly in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d2' directly in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d3' directly in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d1' directly in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: cannot access memory 'ram_en' directly in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d2' directly in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: cannot access memory 'ram_en_sync_d1' directly in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: cannot assign to memory 'ram_en_sync_d3' directly in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: cannot access memory 'ram_en_sync_d2' directly in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : Verilog file '../../hg_mp/fe/prebuffer.v' ignored due to errors
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-8007 ERROR: part-select of memory 'ram_en_sync_d1' is not allowed in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(355)
+HDL-8007 ERROR: part-select of memory 'ram_en_sync_d2' is not allowed in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(356)
+HDL-8007 ERROR: part-select of memory 'ram_en_sync_d3' is not allowed in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: cannot assign a packed type to an unpacked type in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(357)
+HDL-8007 ERROR: part-select of memory 'ram_en_sync_d1' is not allowed in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: cannot access memory 'ram_en' directly in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(360)
+HDL-8007 ERROR: part-select of memory 'ram_en_sync_d2' is not allowed in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: cannot access memory 'ram_en_sync_d1' directly in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(361)
+HDL-8007 ERROR: part-select of memory 'ram_en_sync_d3' is not allowed in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: cannot access memory 'ram_en_sync_d2' directly in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: unpacked value/target cannot be used in an assignment in ../../hg_mp/fe/prebuffer.v(362)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : Verilog file '../../hg_mp/fe/prebuffer.v' ignored due to errors
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step opt_route.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../hg_mp/fe/sort.v(291)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../hg_mp/fe/sort.v(291)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../hg_mp/fe/sort.v(292)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../hg_mp/fe/sort.v(290)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../hg_mp/fe/sort.v(292)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../hg_mp/fe/sort.v(294)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../hg_mp/fe/sort.v(294)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../hg_mp/fe/sort.v(295)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../hg_mp/fe/sort.v(293)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../hg_mp/fe/sort.v(295)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db" in  2.867552s wall, 2.843750s user + 0.234375s system = 3.078125s CPU (107.3%)
+
+RUN-1004 : used memory is 989 MB, reserved memory is 976 MB, peak memory is 1281 MB
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../hg_mp/fe/sort_rev.v(322)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../hg_mp/fe/sort_rev.v(322)
+HDL-5007 WARNING: data object 'lvds_flag_2d' is already declared in ../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_2d' is from here in ../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_2d' is ignored in ../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'lvds_flag_1d' is already declared in ../../hg_mp/fe/sort_rev.v(323)
+HDL-1007 : previous declaration of 'lvds_flag_1d' is from here in ../../hg_mp/fe/sort_rev.v(321)
+HDL-5007 WARNING: second declaration of 'lvds_flag_1d' is ignored in ../../hg_mp/fe/sort_rev.v(323)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../hg_mp/fe/sort_rev.v(325)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../hg_mp/fe/sort_rev.v(325)
+HDL-5007 WARNING: data object 'set_flag_2d' is already declared in ../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_2d' is from here in ../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_2d' is ignored in ../../hg_mp/fe/sort_rev.v(326)
+HDL-5007 WARNING: data object 'set_flag_1d' is already declared in ../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../hg_mp/fe/sort_rev.v(324)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../hg_mp/fe/sort_rev.v(326)
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(423)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 768 feed throughs used by 544 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.881625s wall, 8.843750s user + 0.328125s system = 9.171875s CPU (103.3%)
+
+RUN-1004 : used memory is 1325 MB, reserved memory is 1303 MB, peak memory is 1333 MB
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 710 feed throughs used by 507 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.960844s wall, 8.921875s user + 0.281250s system = 9.203125s CPU (102.7%)
+
+RUN-1004 : used memory is 1334 MB, reserved memory is 1314 MB, peak memory is 1341 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.446770s wall, 0.140625s user + 0.281250s system = 0.421875s CPU (2.4%)
+
+RUN-1004 : used memory is 1344 MB, reserved memory is 1321 MB, peak memory is 1363 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.659734s wall, 0.250000s user + 0.281250s system = 0.531250s CPU (3.0%)
+
+RUN-1004 : used memory is 1344 MB, reserved memory is 1321 MB, peak memory is 1363 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 629 feed throughs used by 442 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  11.929393s wall, 12.031250s user + 0.453125s system = 12.484375s CPU (104.7%)
+
+RUN-1004 : used memory is 1327 MB, reserved memory is 1305 MB, peak memory is 1363 MB
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 622 feed throughs used by 463 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.020822s wall, 8.984375s user + 0.359375s system = 9.343750s CPU (103.6%)
+
+RUN-1004 : used memory is 1348 MB, reserved memory is 1328 MB, peak memory is 1363 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.416658s wall, 0.109375s user + 0.265625s system = 0.375000s CPU (2.2%)
+
+RUN-1004 : used memory is 1357 MB, reserved memory is 1335 MB, peak memory is 1376 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.635991s wall, 0.218750s user + 0.312500s system = 0.531250s CPU (3.0%)
+
+RUN-1004 : used memory is 1357 MB, reserved memory is 1335 MB, peak memory is 1376 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 688 feed throughs used by 487 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.977415s wall, 8.953125s user + 0.296875s system = 9.250000s CPU (103.0%)
+
+RUN-1004 : used memory is 1368 MB, reserved memory is 1344 MB, peak memory is 1376 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.502193s wall, 0.359375s user + 0.265625s system = 0.625000s CPU (3.6%)
+
+RUN-1004 : used memory is 1374 MB, reserved memory is 1351 MB, peak memory is 1392 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.714092s wall, 0.468750s user + 0.265625s system = 0.734375s CPU (4.1%)
+
+RUN-1004 : used memory is 1374 MB, reserved memory is 1351 MB, peak memory is 1392 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(419)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 688 feed throughs used by 487 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.973033s wall, 8.953125s user + 0.281250s system = 9.234375s CPU (102.9%)
+
+RUN-1004 : used memory is 1387 MB, reserved memory is 1368 MB, peak memory is 1394 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.566606s wall, 0.203125s user + 0.046875s system = 0.250000s CPU (1.4%)
+
+RUN-1004 : used memory is 1397 MB, reserved memory is 1375 MB, peak memory is 1416 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.779757s wall, 0.296875s user + 0.062500s system = 0.359375s CPU (2.0%)
+
+RUN-1004 : used memory is 1397 MB, reserved memory is 1375 MB, peak memory is 1416 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step opt_place.
+RUN-1001 : phy_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'set_flag_1d' is already declared in ../../hg_mp/fe/sort.v(297)
+HDL-5007 WARNING: second declaration of 'set_flag_1d' is ignored in ../../hg_mp/fe/sort.v(297)
+HDL-1007 : previous declaration of 'set_flag_1d' is from here in ../../hg_mp/fe/sort.v(297)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(333)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(334)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(333)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(334)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'set_flag_2d' is not declared in ../../hg_mp/fe/sort.v(335)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 620 feed throughs used by 444 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.030240s wall, 9.015625s user + 0.250000s system = 9.265625s CPU (102.6%)
+
+RUN-1004 : used memory is 1403 MB, reserved memory is 1384 MB, peak memory is 1416 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.551303s wall, 0.250000s user + 0.171875s system = 0.421875s CPU (2.4%)
+
+RUN-1004 : used memory is 1412 MB, reserved memory is 1391 MB, peak memory is 1431 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.765093s wall, 0.359375s user + 0.171875s system = 0.531250s CPU (3.0%)
+
+RUN-1004 : used memory is 1412 MB, reserved memory is 1391 MB, peak memory is 1431 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step opt_route.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db" in  2.806376s wall, 2.796875s user + 0.125000s system = 2.921875s CPU (104.1%)
+
+RUN-1004 : used memory is 1180 MB, reserved memory is 1173 MB, peak memory is 1431 MB
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 724 feed throughs used by 509 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.575327s wall, 8.562500s user + 0.343750s system = 8.906250s CPU (103.9%)
+
+RUN-1004 : used memory is 1430 MB, reserved memory is 1409 MB, peak memory is 1438 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.556556s wall, 0.140625s user + 0.171875s system = 0.312500s CPU (1.8%)
+
+RUN-1004 : used memory is 1432 MB, reserved memory is 1410 MB, peak memory is 1451 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.776863s wall, 0.250000s user + 0.187500s system = 0.437500s CPU (2.5%)
+
+RUN-1004 : used memory is 1432 MB, reserved memory is 1410 MB, peak memory is 1451 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 629 feed throughs used by 478 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.911964s wall, 8.875000s user + 0.421875s system = 9.296875s CPU (104.3%)
+
+RUN-1004 : used memory is 1450 MB, reserved memory is 1428 MB, peak memory is 1456 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.560227s wall, 0.093750s user + 0.015625s system = 0.109375s CPU (0.6%)
+
+RUN-1004 : used memory is 1452 MB, reserved memory is 1430 MB, peak memory is 1471 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.775935s wall, 0.218750s user + 0.031250s system = 0.250000s CPU (1.4%)
+
+RUN-1004 : used memory is 1452 MB, reserved memory is 1430 MB, peak memory is 1471 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 683 feed throughs used by 469 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.910041s wall, 8.843750s user + 0.390625s system = 9.234375s CPU (103.6%)
+
+RUN-1004 : used memory is 1478 MB, reserved memory is 1456 MB, peak memory is 1484 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.627090s wall, 0.093750s user + 0.031250s system = 0.125000s CPU (0.7%)
+
+RUN-1004 : used memory is 1480 MB, reserved memory is 1458 MB, peak memory is 1499 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.845953s wall, 0.218750s user + 0.046875s system = 0.265625s CPU (1.5%)
+
+RUN-1004 : used memory is 1480 MB, reserved memory is 1458 MB, peak memory is 1499 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 683 feed throughs used by 469 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.809305s wall, 8.718750s user + 0.312500s system = 9.031250s CPU (102.5%)
+
+RUN-1004 : used memory is 1488 MB, reserved memory is 1471 MB, peak memory is 1499 MB
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/prebuffer.v(359)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-8007 ERROR: extra comma in port association list is not allowed in ../../hg_mp/fe/ram_switch.v(83)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/fe/ram_switch.v(2)
+HDL-1007 : Verilog file '../../hg_mp/fe/ram_switch.v' ignored due to errors
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+GUI-5005 WARNING: Unknown file icon ...
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(83)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(128)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(155)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(42)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(100)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(125)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(128)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(155)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(83)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(128)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(155)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(127)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(154)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(154)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(127)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(154)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/ram_switch.v(153)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 731 feed throughs used by 529 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.970112s wall, 10.031250s user + 0.218750s system = 10.250000s CPU (102.8%)
+
+RUN-1004 : used memory is 1533 MB, reserved memory is 1514 MB, peak memory is 1540 MB
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step opt_route.
+RUN-1001 : phy_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db" in  2.759507s wall, 2.765625s user + 0.140625s system = 2.906250s CPU (105.3%)
+
+RUN-1004 : used memory is 1358 MB, reserved memory is 1348 MB, peak memory is 1549 MB
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 675 feed throughs used by 482 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.612109s wall, 8.578125s user + 0.406250s system = 8.984375s CPU (104.3%)
+
+RUN-1004 : used memory is 1620 MB, reserved memory is 1604 MB, peak memory is 1627 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.562389s wall, 0.093750s user + 0.125000s system = 0.218750s CPU (1.2%)
+
+RUN-1004 : used memory is 1624 MB, reserved memory is 1605 MB, peak memory is 1643 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.782615s wall, 0.218750s user + 0.140625s system = 0.359375s CPU (2.0%)
+
+RUN-1004 : used memory is 1624 MB, reserved memory is 1605 MB, peak memory is 1643 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 249 feed throughs used by 192 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  7.613942s wall, 7.578125s user + 0.156250s system = 7.734375s CPU (101.6%)
+
+RUN-1004 : used memory is 1543 MB, reserved memory is 1527 MB, peak memory is 1643 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.527094s wall, 0.125000s user + 0.421875s system = 0.546875s CPU (3.1%)
+
+RUN-1004 : used memory is 1554 MB, reserved memory is 1538 MB, peak memory is 1643 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.738984s wall, 0.203125s user + 0.453125s system = 0.656250s CPU (3.7%)
+
+RUN-1004 : used memory is 1554 MB, reserved memory is 1538 MB, peak memory is 1643 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.591446s wall, 0.171875s user + 0.578125s system = 0.750000s CPU (4.3%)
+
+RUN-1004 : used memory is 1552 MB, reserved memory is 1536 MB, peak memory is 1643 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.810393s wall, 0.281250s user + 0.593750s system = 0.875000s CPU (4.9%)
+
+RUN-1004 : used memory is 1552 MB, reserved memory is 1536 MB, peak memory is 1643 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(419)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 194 feed throughs used by 154 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.087396s wall, 8.093750s user + 0.453125s system = 8.546875s CPU (105.7%)
+
+RUN-1004 : used memory is 1568 MB, reserved memory is 1556 MB, peak memory is 1643 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.581602s wall, 0.062500s user + 0.062500s system = 0.125000s CPU (0.7%)
+
+RUN-1004 : used memory is 1578 MB, reserved memory is 1561 MB, peak memory is 1643 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.795005s wall, 0.171875s user + 0.078125s system = 0.250000s CPU (1.4%)
+
+RUN-1004 : used memory is 1578 MB, reserved memory is 1562 MB, peak memory is 1643 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(216)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(216)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 678 feed throughs used by 502 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.533190s wall, 9.593750s user + 0.390625s system = 9.984375s CPU (104.7%)
+
+RUN-1004 : used memory is 1625 MB, reserved memory is 1608 MB, peak memory is 1643 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.622689s wall, 0.265625s user + 0.421875s system = 0.687500s CPU (3.9%)
+
+RUN-1004 : used memory is 1631 MB, reserved memory is 1614 MB, peak memory is 1648 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.839095s wall, 0.359375s user + 0.468750s system = 0.828125s CPU (4.6%)
+
+RUN-1004 : used memory is 1631 MB, reserved memory is 1614 MB, peak memory is 1648 MB
+GUI-1001 : Downloading succeeded!
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+PRG-1001 : SPI Flash ID is:  ef
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_EG176 -m program_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit" in  1.853972s wall, 1.750000s user + 0.140625s system = 1.890625s CPU (102.0%)
+
+RUN-1004 : used memory is 1979 MB, reserved memory is 1979 MB, peak memory is 1991 MB
+RUN-1002 : start command "program_spi -cable 0 -spd 7"
+RUN-1003 : finish command "program_spi -cable 0 -spd 7" in  107.900227s wall, 3.625000s user + 2.406250s system = 6.031250s CPU (5.6%)
+
+RUN-1004 : used memory is 1979 MB, reserved memory is 1978 MB, peak memory is 1991 MB
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m verify_spi -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -spd 4"
+RUN-1003 : finish command "program -cable 0 -spd 4" in  23.183960s wall, 0.390625s user + 0.406250s system = 0.796875s CPU (3.4%)
+
+RUN-1004 : used memory is 1827 MB, reserved memory is 1816 MB, peak memory is 1991 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode program_spi -v -spd 7 -sec 64 -cable 0 -flashsize 128" in  137.152422s wall, 7.578125s user + 3.109375s system = 10.687500s CPU (7.8%)
+
+RUN-1004 : used memory is 1827 MB, reserved memory is 1816 MB, peak memory is 1991 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/prebuffer.v(208)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-8007 ERROR: cannot find port 'trig_FIFO' on this module in ../../hg_mp/fe/prebuffer.v(208)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step bitgen.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 654 feed throughs used by 451 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.740941s wall, 8.656250s user + 0.328125s system = 8.984375s CPU (102.8%)
+
+RUN-1004 : used memory is 1845 MB, reserved memory is 1837 MB, peak memory is 1991 MB
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-5007 WARNING: data object 'DVAL' is already declared in ../../hg_mp/fe/read_ram_data.v(120)
+HDL-1007 : previous declaration of 'DVAL' is from here in ../../hg_mp/fe/read_ram_data.v(31)
+HDL-5007 WARNING: second declaration of 'DVAL' is ignored in ../../hg_mp/fe/read_ram_data.v(120)
+HDL-8007 ERROR: procedural assignment to a non-register 'camdata' is not permitted in ../../hg_mp/fe/read_ram_data.v(122)
+HDL-8007 ERROR: procedural assignment to a non-register 'camdata' is not permitted in ../../hg_mp/fe/read_ram_data.v(123)
+HDL-8007 ERROR: procedural assignment to a non-register 'camdata' is not permitted in ../../hg_mp/fe/read_ram_data.v(124)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(130)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(133)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(134)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(135)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(136)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/fe/read_ram_data.v(1)
+HDL-1007 : Verilog file '../../hg_mp/fe/read_ram_data.v' ignored due to errors
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-5007 WARNING: data object 'DVAL' is already declared in ../../hg_mp/fe/read_ram_data.v(120)
+HDL-1007 : previous declaration of 'DVAL' is from here in ../../hg_mp/fe/read_ram_data.v(31)
+HDL-5007 WARNING: second declaration of 'DVAL' is ignored in ../../hg_mp/fe/read_ram_data.v(120)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(130)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(133)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(134)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(135)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(136)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(130)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(133)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(134)
+HDL-5007 WARNING: 'DVAL_tmp' is not declared in ../../hg_mp/fe/read_ram_data.v(135)
+HDL-5007 Similar messages will be suppressed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 672 feed throughs used by 483 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.101407s wall, 9.046875s user + 0.328125s system = 9.375000s CPU (103.0%)
+
+RUN-1004 : used memory is 1903 MB, reserved memory is 1896 MB, peak memory is 1991 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.687157s wall, 0.234375s user + 0.406250s system = 0.640625s CPU (3.6%)
+
+RUN-1004 : used memory is 1907 MB, reserved memory is 1897 MB, peak memory is 1991 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.899164s wall, 0.343750s user + 0.406250s system = 0.750000s CPU (4.2%)
+
+RUN-1004 : used memory is 1907 MB, reserved memory is 1897 MB, peak memory is 1991 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : stop_run syn_1.
+RUN-1001 : reset_run syn_1 -step opt_rtl.
+RUN-1001 : syn_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-8007 ERROR: syntax error near 'always' in ../../hg_mp/fe/prebuffer.v(275)
+HDL-8007 ERROR: Verilog 2000 keyword 'always' used in incorrect context in ../../hg_mp/fe/prebuffer.v(275)
+HDL-8007 ERROR: syntax error near '<=' in ../../hg_mp/fe/prebuffer.v(277)
+HDL-8007 ERROR: syntax error near '<=' in ../../hg_mp/fe/prebuffer.v(278)
+HDL-8007 ERROR: syntax error near '}' in ../../hg_mp/fe/prebuffer.v(278)
+HDL-8007 ERROR: syntax error near '<=' in ../../hg_mp/fe/prebuffer.v(279)
+HDL-8007 ERROR: 'start_sp_wr' is not a constant in ../../hg_mp/fe/prebuffer.v(277)
+HDL-8007 ERROR: 'raw_switch' is not a type in ../../hg_mp/fe/prebuffer.v(277)
+HDL-8007 ERROR: 'trig_FIFO' is not a constant in ../../hg_mp/fe/prebuffer.v(278)
+HDL-8007 ERROR: 'raw_switch' is not a type in ../../hg_mp/fe/prebuffer.v(278)
+HDL-8007 ERROR: 'raw_switch' is not a type in ../../hg_mp/fe/prebuffer.v(279)
+HDL-8007 ERROR: ignore module module due to previous errors in ../../hg_mp/fe/prebuffer.v(3)
+HDL-1007 : Verilog file '../../hg_mp/fe/prebuffer.v' ignored due to errors
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 666 feed throughs used by 449 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.944394s wall, 8.906250s user + 0.343750s system = 9.250000s CPU (103.4%)
+
+RUN-1004 : used memory is 1958 MB, reserved memory is 1948 MB, peak memory is 1991 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.706373s wall, 0.109375s user + 0.390625s system = 0.500000s CPU (2.8%)
+
+RUN-1004 : used memory is 1965 MB, reserved memory is 1953 MB, peak memory is 1991 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.920474s wall, 0.234375s user + 0.406250s system = 0.640625s CPU (3.6%)
+
+RUN-1004 : used memory is 1965 MB, reserved memory is 1953 MB, peak memory is 1991 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(217)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(219)
+HDL-5007 WARNING: 'trig_ADC_r2' is not declared in ../../hg_mp/fe/prebuffer.v(153)
+HDL-5007 WARNING: 'trig_ADC_r2' is not declared in ../../hg_mp/fe/prebuffer.v(158)
+HDL-5007 WARNING: 'trig_ADC_r2' is not declared in ../../hg_mp/fe/prebuffer.v(160)
+HDL-5007 WARNING: 'trig_ADC_r2' is not declared in ../../hg_mp/fe/prebuffer.v(153)
+HDL-5007 WARNING: 'trig_ADC_r2' is not declared in ../../hg_mp/fe/prebuffer.v(158)
+HDL-5007 WARNING: 'trig_ADC_r2' is not declared in ../../hg_mp/fe/prebuffer.v(160)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(220)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(222)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 560 feed throughs used by 427 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.970866s wall, 9.000000s user + 0.312500s system = 9.312500s CPU (103.8%)
+
+RUN-1004 : used memory is 1968 MB, reserved memory is 1956 MB, peak memory is 1991 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.689698s wall, 0.234375s user + 0.468750s system = 0.703125s CPU (4.0%)
+
+RUN-1004 : used memory is 1972 MB, reserved memory is 1960 MB, peak memory is 1991 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.902050s wall, 0.343750s user + 0.484375s system = 0.828125s CPU (4.6%)
+
+RUN-1004 : used memory is 1972 MB, reserved memory is 1960 MB, peak memory is 1991 MB
+GUI-1001 : Downloading succeeded!
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 690 feed throughs used by 493 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.027229s wall, 9.062500s user + 0.343750s system = 9.406250s CPU (104.2%)
+
+RUN-1004 : used memory is 1985 MB, reserved memory is 1979 MB, peak memory is 2009 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.700788s wall, 1.046875s user + 0.734375s system = 1.781250s CPU (10.1%)
+
+RUN-1004 : used memory is 1994 MB, reserved memory is 1986 MB, peak memory is 2012 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.913869s wall, 1.156250s user + 0.734375s system = 1.890625s CPU (10.6%)
+
+RUN-1004 : used memory is 1994 MB, reserved memory is 1986 MB, peak memory is 2012 MB
+GUI-1001 : Downloading succeeded!
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 554 feed throughs used by 427 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.068099s wall, 9.046875s user + 0.312500s system = 9.359375s CPU (103.2%)
+
+RUN-1004 : used memory is 2014 MB, reserved memory is 2006 MB, peak memory is 2040 MB
+TMR-3509 : Import timing summary.
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-5007 WARNING: data object 'ram_data_tmp' is already declared in ../../hg_mp/fe/ram_switch.v(99)
+HDL-1007 : previous declaration of 'ram_data_tmp' is from here in ../../hg_mp/fe/ram_switch.v(52)
+HDL-5007 WARNING: second declaration of 'ram_data_tmp' is ignored in ../../hg_mp/fe/ram_switch.v(99)
+HDL-5007 WARNING: data object 'ram_addr_tmp' is already declared in ../../hg_mp/fe/ram_switch.v(100)
+HDL-1007 : previous declaration of 'ram_addr_tmp' is from here in ../../hg_mp/fe/ram_switch.v(53)
+HDL-5007 WARNING: second declaration of 'ram_addr_tmp' is ignored in ../../hg_mp/fe/ram_switch.v(100)
+HDL-5007 WARNING: data object 'ram_en_tmp' is already declared in ../../hg_mp/fe/ram_switch.v(101)
+HDL-1007 : previous declaration of 'ram_en_tmp' is from here in ../../hg_mp/fe/ram_switch.v(54)
+HDL-5007 WARNING: second declaration of 'ram_en_tmp' is ignored in ../../hg_mp/fe/ram_switch.v(101)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 656 feed throughs used by 479 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.403115s wall, 9.468750s user + 0.250000s system = 9.718750s CPU (103.4%)
+
+RUN-1004 : used memory is 2067 MB, reserved memory is 2063 MB, peak memory is 2086 MB
+TMR-3509 : Import timing summary.
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+RUN-1001 : set_run_property phy_1 -flow_property PlaceProperty::opt_timing::ultra.
+GUI-1001 : set_param simulation sim_lib  
+RUN-1001 : reset_run phy_1 -step opt_place.
+RUN-1001 : launch_runs phy_1 -step bitgen.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 542 feed throughs used by 440 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.108405s wall, 9.125000s user + 0.156250s system = 9.281250s CPU (101.9%)
+
+RUN-1004 : used memory is 2093 MB, reserved memory is 2099 MB, peak memory is 2289 MB
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[0]"
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[1]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[2]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[3]"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[0]"
+RUN-1002 : start command "get_pins u_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "get_ports a_lvds_clk_p"
+RUN-1002 : start command "get_pins uu_pll_lvds/pll_inst.clkc[1]"
+RUN-1002 : start command "get_ports b_lvds_clk_p"
+RUN-1002 : start command "get_pins u_pll/pll_inst.clkc[4]"
+RUN-1002 : start command "get_ports clock_source"
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 557 feed throughs used by 432 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.876791s wall, 8.937500s user + 0.281250s system = 9.218750s CPU (103.9%)
+
+RUN-1004 : used memory is 2188 MB, reserved memory is 2191 MB, peak memory is 2289 MB
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/local_bus/ubus_top.v(333)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/local_bus/ubus_top.v(351)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/local_bus/ubus_top.v(333)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/local_bus/ubus_top.v(351)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-8007 ERROR: cannot find port 'a_pclk' on this module in ../../hg_mp/drx_top/huagao_mipi_top.v(1279)
+HDL-8007 ERROR: cannot find port 'b_pclk' on this module in ../../hg_mp/drx_top/huagao_mipi_top.v(1280)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 573 feed throughs used by 421 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.852680s wall, 8.859375s user + 0.250000s system = 9.109375s CPU (102.9%)
+
+RUN-1004 : used memory is 2197 MB, reserved memory is 2204 MB, peak memory is 2289 MB
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-6001 WARNING: phy_1: run failed.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_place.db" in  2.838719s wall, 2.859375s user + 0.140625s system = 3.000000s CPU (105.7%)
+
+RUN-1004 : used memory is 2118 MB, reserved memory is 2125 MB, peak memory is 2289 MB
+RUN-1001 : set_run_property phy_1 -flow_property PlaceProperty::opt_timing::high.
+GUI-1001 : set_param simulation sim_lib  
+RUN-1001 : reset_run phy_1 -step opt_place.
+RUN-1001 : launch_runs phy_1 -step opt_route.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : launch_runs phy_1 -step bitgen.
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step bitgen.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 573 feed throughs used by 410 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.620705s wall, 8.609375s user + 0.218750s system = 8.828125s CPU (102.4%)
+
+RUN-1004 : used memory is 2230 MB, reserved memory is 2237 MB, peak memory is 2289 MB
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 573 feed throughs used by 410 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.833275s wall, 8.843750s user + 0.312500s system = 9.156250s CPU (103.7%)
+
+RUN-1004 : used memory is 2231 MB, reserved memory is 2238 MB, peak memory is 2289 MB
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 573 feed throughs used by 410 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.951923s wall, 9.000000s user + 0.265625s system = 9.265625s CPU (103.5%)
+
+RUN-1004 : used memory is 2233 MB, reserved memory is 2240 MB, peak memory is 2289 MB
+TMR-3509 : Import timing summary.
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 573 feed throughs used by 410 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.192478s wall, 9.281250s user + 0.250000s system = 9.531250s CPU (103.7%)
+
+RUN-1004 : used memory is 2253 MB, reserved memory is 2260 MB, peak memory is 2289 MB
+TMR-3509 : Import timing summary.
+RUN-1001 : reset_run phy_1 -step opt_place.
+RUN-8001 ERROR: Run syn_1 should be up to date.
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : stop_run phy_1.
+RUN-1001 : reset_run phy_1 -step opt_route.
+RUN-1001 : phy_1: run complete.
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 670 feed throughs used by 501 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.198652s wall, 9.265625s user + 0.343750s system = 9.609375s CPU (104.5%)
+
+RUN-1004 : used memory is 2255 MB, reserved memory is 2262 MB, peak memory is 2289 MB
+TMR-3509 : Import timing summary.
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_36M_921600.v
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(222)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-5010 WARNING: Net S_hs_last is skipped due to 0 input or output
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 558 feed throughs used by 416 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  9.076966s wall, 9.140625s user + 0.343750s system = 9.484375s CPU (104.5%)
+
+RUN-1004 : used memory is 2279 MB, reserved memory is 2281 MB, peak memory is 2303 MB
+TMR-3509 : Import timing summary.
+RUN-002 WARNING: File does not exist! D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1\encrypted_text
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.895153s wall, 0.203125s user + 0.093750s system = 0.296875s CPU (1.7%)
+
+RUN-1004 : used memory is 2283 MB, reserved memory is 2287 MB, peak memory is 2303 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  18.112451s wall, 0.328125s user + 0.093750s system = 0.421875s CPU (2.3%)
+
+RUN-1004 : used memory is 2283 MB, reserved memory is 2287 MB, peak memory is 2303 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.760823s wall, 0.140625s user + 0.125000s system = 0.265625s CPU (1.5%)
+
+RUN-1004 : used memory is 2283 MB, reserved memory is 2286 MB, peak memory is 2303 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.973444s wall, 0.250000s user + 0.140625s system = 0.390625s CPU (2.2%)
+
+RUN-1004 : used memory is 2283 MB, reserved memory is 2286 MB, peak memory is 2303 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : stop_run syn_1.
+RUN-1001 : reset_run syn_1 -step opt_gate.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : open_run syn_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db" in  1.740863s wall, 1.750000s user + 0.078125s system = 1.828125s CPU (105.0%)
+
+RUN-1004 : used memory is 2188 MB, reserved memory is 2190 MB, peak memory is 2303 MB
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 520 feed throughs used by 391 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.668745s wall, 8.750000s user + 0.453125s system = 9.203125s CPU (106.2%)
+
+RUN-1004 : used memory is 2279 MB, reserved memory is 2281 MB, peak memory is 2303 MB
+TMR-3509 : Import timing summary.
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.755061s wall, 0.218750s user + 0.453125s system = 0.671875s CPU (3.8%)
+
+RUN-1004 : used memory is 2283 MB, reserved memory is 2286 MB, peak memory is 2303 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.982933s wall, 0.359375s user + 0.453125s system = 0.812500s CPU (4.5%)
+
+RUN-1004 : used memory is 2283 MB, reserved memory is 2286 MB, peak memory is 2303 MB
+GUI-1001 : Downloading succeeded!
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  18.337813s wall, 3.156250s user + 0.171875s system = 3.328125s CPU (18.1%)
+
+RUN-1004 : used memory is 2280 MB, reserved memory is 2283 MB, peak memory is 2303 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  18.556458s wall, 3.281250s user + 0.203125s system = 3.484375s CPU (18.8%)
+
+RUN-1004 : used memory is 2280 MB, reserved memory is 2283 MB, peak memory is 2303 MB
+GUI-1001 : Downloading succeeded!
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: 'line_sync_a' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-5007 WARNING: 'line_sync_a' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+RUN-1001 : reset_run syn_1 phy_1.
+GUI-6001 WARNING: File D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic.bit does not exist!
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+HDL-5007 WARNING: 'line_snyc_a' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+HDL-5007 WARNING: 'line_snyc_a' is not declared in ../../hg_mp/drx_top/huagao_mipi_top.v(1705)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1305)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1316)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1334)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1516)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1912)
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-1001 : syn_1: run complete.
+RUN-1001 : phy_1: run complete.
+RUN-1001 : open_run phy_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+PHY-1001 : Generate detailed routing grids ...
+PHY-1001 : Generate nets ...
+PHY-1001 : net a_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net b_lvds_clk_p_dup_1 will be routed on clock mesh
+PHY-1001 : net clock_source_dup_1 will be routed on clock mesh
+PHY-5010 WARNING: Net eot_cnt_d2[9] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[8] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[7] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[6] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[5] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[4] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[3] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[2] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[1] is skipped due to 0 input or output
+PHY-5010 WARNING: Net eot_cnt_d2[0] is skipped due to 0 input or output
+PHY-1001 : clock net uu_pll_lvds/clk0_out will be merged with clock uu_pll_lvds/clk0_buf
+PHY-1001 : net ub_lvds_rx/sclk will be routed on clock mesh
+PHY-5010 Similar messages will be suppressed.
+PHY-1001 : net exdev_ctl_a/clk_adc will be routed on clock mesh
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/clk_config_syn_4 will be merged with clock exdev_ctl_a/u_ADconfig/clk_config
+PHY-1001 : clock net exdev_ctl_a/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_a/u_ADconfig/gret9lit16_n
+PHY-1001 : clock net exdev_ctl_b/u_ADconfig/gret9lit16_n_syn_2 will be merged with clock exdev_ctl_b/u_ADconfig/gret9lit16_n
+PHY-1001 : net ua_lvds_rx/sclk will be routed on clock mesh
+PHY-1001 : clock net u_pll_lvds/clk0_out will be merged with clock u_pll_lvds/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/I_hs_clk_x4_90d will be routed on clock mesh
+PHY-1001 : clock net u_mipi_dphy_tx_wrapper/I_lpdt_clk will be merged with clock u_pll/clk0_buf
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x2 will be routed on clock mesh
+PHY-1001 : net u_mipi_dphy_tx_wrapper/u_hs_tx_wrapper/I_clk_x4 will be routed on clock mesh
+PHY-1001 : eco open net = 0
+PHY-1001 : 545 feed throughs used by 409 nets
+RUN-1001 : Import timing constraints
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1/hg_anlogic_pr.db" in  8.962742s wall, 9.000000s user + 0.437500s system = 9.437500s CPU (105.3%)
+
+RUN-1004 : used memory is 2295 MB, reserved memory is 2297 MB, peak memory is 2309 MB
+RUN-1002 : start command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0"
+PRG-2014 : Chip validation success: EAGLE_S20_EG176
+RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_EG176 -m jtag_burst -freq 4 -bit hg_anlogic_Runs/phy_1/hg_anlogic.bit"
+RUN-1002 : start command "program -cable 0 -mode svf -spd 7 -p"
+RUN-1003 : finish command "program -cable 0 -mode svf -spd 7 -p" in  17.767807s wall, 0.109375s user + 0.187500s system = 0.296875s CPU (1.7%)
+
+RUN-1004 : used memory is 2295 MB, reserved memory is 2297 MB, peak memory is 2314 MB
+RUN-1003 : finish command "download -bit hg_anlogic_Runs\phy_1\hg_anlogic.bit -mode jtag -spd 7 -sec 64 -cable 0" in  17.982994s wall, 0.250000s user + 0.187500s system = 0.437500s CPU (2.4%)
+
+RUN-1004 : used memory is 2295 MB, reserved memory is 2297 MB, peak memory is 2314 MB
+GUI-1001 : Downloading succeeded!
+TMR-3509 : Import timing summary.
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-6001 WARNING: Failed to reset phy_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/phy_1
+RUN-6001 WARNING: Failed to reset syn_1: some files can't be removed in D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
+RUN-6001 WARNING: syn_1: run failed.
+RUN-1001 : open_run syn_1.
+RUN-1002 : start command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db"
+RUN-1001 : Importing database generated by Tang Dynasty, V5.6.71036.
+RUN-1001 : Database version number 46146.
+RUN-1001 : Import flow parameters
+RUN-1001 : Import IO constraints
+RUN-1001 : Import Inst constraints
+RUN-1001 : Import design success TD_VERSION=5.6.71036 , DB_VERSION=46146
+RUN-1003 : finish command "import_db D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/prj/td_project/hg_anlogic_Runs/syn_1/hg_anlogic_rtl.db" in  1.741703s wall, 1.703125s user + 0.140625s system = 1.843750s CPU (105.9%)
+
+RUN-1004 : used memory is 2212 MB, reserved memory is 2214 MB, peak memory is 2314 MB
+RUN-1001 : reset_run syn_1 phy_1.
+RUN-1001 : launch_runs syn_1 phy_1  -jobs 6.
diff --git a/src/prj/td_project/td_20240311_094450.log b/src/prj/td_project/td_20240311_094450.log
new file mode 100644
index 0000000..14688dd
--- /dev/null
+++ b/src/prj/td_project/td_20240311_094450.log
@@ -0,0 +1,207 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Mon Mar 11 09:44:50 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
+RUN-1002 : start command "open_project hg_anlogic.al -update"
+RUN-1001 : Print Global Property
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :        Parameters        |  Settings  |  Default Values  |  Note  
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 :          message         |  standard  |     standard     |        
+RUN-1001 :   mixed_pack_place_flow  |     on     |        on        |        
+RUN-1001 :        qor_monitor       |    off     |       off        |        
+RUN-1001 :        syn_ip_flow       |    off     |       off        |        
+RUN-1001 :          thread          |    auto    |       auto       |        
+RUN-1001 : ---------------------------------------------------------------
+RUN-1001 : Print Design Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :   default_reg_initial   |    auto    |       auto       |        
+RUN-1001 :        infer_add        |     on     |        on        |        
+RUN-1001 :        infer_fsm        |    off     |       off        |        
+RUN-1001 :        infer_mult       |     on     |        on        |        
+RUN-1001 :        infer_ram        |     on     |        on        |        
+RUN-1001 :        infer_reg        |     on     |        on        |        
+RUN-1001 :   infer_reg_init_value  |     on     |        on        |        
+RUN-1001 :        infer_rom        |     on     |        on        |        
+RUN-1001 :      infer_shifter      |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 : Print Rtl Property
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :        Parameters       |  Settings  |  Default Values  |  Note  
+RUN-1001 : --------------------------------------------------------------
+RUN-1001 :       compress_add      |   ripple   |      ripple      |        
+RUN-1001 :        elf_sload        |    off     |       off        |        
+RUN-1001 :       fix_undriven      |     0      |        0         |        
+RUN-1001 :         flatten         |    off     |       off        |        
+RUN-1001 :       gate_sharing      |     on     |        on        |        
+RUN-1001 :    hdl_warning_level    |   normal   |      normal      |        
+RUN-1001 :   impl_internal_tribuf  |     on     |        on        |        
+RUN-1001 :      impl_set_reset     |     on     |        on        |        
+RUN-1001 :        infer_gsr        |    off     |       off        |        
+RUN-1001 :      keep_hierarchy     |    auto    |       auto       |        
+RUN-1001 :        max_fanout       |    9999    |       9999       |        
+RUN-1001 :      max_oh2bin_len     |     10     |        10        |        
+RUN-1001 :       merge_equal       |     on     |        on        |        
+RUN-1001 :       merge_equiv       |     on     |        on        |        
+RUN-1001 :        merge_mux        |    off     |       off        |        
+RUN-1001 :     min_control_set     |     8      |        8         |        
+RUN-1001 :      min_ripple_len     |    auto    |       auto       |        
+RUN-1001 :       oh2bin_ratio      |    0.08    |       0.08       |        
+RUN-1001 :     opt_adder_fanout    |     on     |        on        |        
+RUN-1001 :        opt_arith        |     on     |        on        |        
+RUN-1001 :       opt_big_gate      |    off     |       off        |        
+RUN-1001 :        opt_const        |     on     |        on        |        
+RUN-1001 :      opt_const_mult     |     on     |        on        |        
+RUN-1001 :       opt_lessthan      |     on     |        on        |        
+RUN-1001 :         opt_mux         |    off     |       off        |        
+RUN-1001 :         opt_ram         |    high    |       high       |        
+RUN-1001 :      rtl_sim_model      |    off     |       off        |        
+RUN-1001 :         seq_syn         |     on     |        on        |        
+RUN-1001 : --------------------------------------------------------------
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll/pll.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll/pll.v(99)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram/SORT_RAM_9k.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/fifo_w32_d4096/fifo_w32_d4096.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v
+HDL-1007 : undeclared symbol 'open', assumed default net type 'wire' in ../../hg_mp/anlogic_ip/pll_lvds/pll_lvds.v(101)
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/sort_ram_200dpi/SORT_RAM_200DPI.v
+HDL-1007 : analyze verilog file ../../hg_mp/cdc/cdc_sync.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ad_sampling.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/exdev_ctl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fan_ctrl.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/gen_sp.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/rddpram_ctl_rev.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sampling_fe_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/sort_rev.v
+HDL-1007 : undeclared symbol 'flag_delay', assumed default net type 'wire' in ../../hg_mp/fe/sort_rev.v(400)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/wrdpram_ctl.v
+HDL-1007 : undeclared symbol 'neg_dval_i', assumed default net type 'wire' in ../../hg_mp/fe/wrdpram_ctl.v(375)
+HDL-5007 WARNING: parameter 'DPI300_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(24)
+HDL-5007 WARNING: parameter 'DPI600_DEPTH' becomes localparam in 'wrdpram_ctl' with formal parameter declaration list in ../../hg_mp/fe/wrdpram_ctl.v(25)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/CRC4_D16.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/local_bus_slve_cis.v
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/ubus_top.v
+HDL-1007 : analyze verilog file ../../hg_mp/pixel_cdc/pixel_cdc.v
+HDL-1007 : analyze verilog file ../../hg_mp/scan_start/scan_start_diff.v
+HDL-1007 : analyze verilog file ../../hg_mp/sensor_lane/lscc_sensor.v
+HDL-1007 : analyze verilog file ../../hg_mp/drx_top/huagao_mipi_top.v
+HDL-1007 : undeclared symbol 'pll_locked0', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(118)
+HDL-1007 : undeclared symbol 'pll_locked1', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(134)
+HDL-1007 : undeclared symbol 'pll_locked2', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(150)
+HDL-1007 : undeclared symbol 'rst_sys', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(158)
+HDL-1007 : undeclared symbol 'rst_sys_n', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(159)
+HDL-1007 : undeclared symbol 'a_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(698)
+HDL-1007 : undeclared symbol 'en_work_a', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(707)
+HDL-1007 : undeclared symbol 'b_sp_sampling_last', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(731)
+HDL-1007 : undeclared symbol 'b_cismode', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(733)
+HDL-1007 : undeclared symbol 'en_adc_cfg_all_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(739)
+HDL-1007 : undeclared symbol 'en_work_b', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(742)
+HDL-1007 : undeclared symbol 'sync_b_sp_sampling_cam', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(913)
+HDL-1007 : undeclared symbol 'b_pclk_rstn', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1002)
+HDL-1007 : undeclared symbol 'dis_led', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1303)
+HDL-1007 : undeclared symbol 'vsp_config', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1314)
+HDL-1007 : undeclared symbol 'debug_6', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1332)
+HDL-1007 : undeclared symbol 'cis_frame_num', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1514)
+HDL-1007 : undeclared symbol 'clk_22m', assumed default net type 'wire' in ../../hg_mp/drx_top/huagao_mipi_top.v(1910)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lane_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v
+Copyright (c) 1998-2019 The OpenSSL Project.  All rights reserved.
+This product includes software developed by the OpenSSL Project
+for use in the OpenSSL Toolkit (http://www.openssl.org/)
+Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
+All rights reserved.
+This product includes cryptographic software written by Eric Young (eay@cryptsoft.com)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/hs_tx_controler.v' in ../../hg_mp/mipi_dphy_tx/hs_tx_controler.v(170)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/mipi_dphy_tx/hs_tx_wrapper.v(106)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(114)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v' in ../../hg_mp/mipi_dphy_tx/lp_tx_wrapper.v(321)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/mipi_dphy_tx_wrapper.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/AD_config.v
+HDL-1007 : analyze verilog file ../../hg_mp/anlogic_ip/d512_w8_fifo/d512_w8_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/crc16_24b.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/ecc_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/rgb_to_csi_pakage.v
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_hs_generate.v(121)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/clk_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/clk_lp_generate.v(100)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_hs_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(139)
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_hs_generate.v' in ../../hg_mp/mipi_dphy_tx/data_hs_generate.v(249)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/data_lp_generate.v
+HDL-1007 : back to file '../../hg_mp/mipi_dphy_tx/data_lp_generate.v' in ../../hg_mp/mipi_dphy_tx/data_lp_generate.v(115)
+HDL-1007 : analyze verilog file ../../hg_mp/lvds_rx/lvds_rx_enc.v
+HDL-1007 : back to file '../../hg_mp/lvds_rx/lvds_rx_enc.v' in ../../hg_mp/lvds_rx/lvds_rx_enc.v(257)
+HDL-1007 : analyze verilog file ../../hg_mp/mipi_dphy_tx/dphy_tx_fifo.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/transfer_300_to_200.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/adc_addr_gen.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(40)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(98)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/adc_addr_gen.v(123)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ch_addr_gen.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/channel_part_8478.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/fifo_adc.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/insert.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(77)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/insert.v(83)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/link_line.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/link_line.v(20)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mapping.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_e.v
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/mux_e.v(16)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/mux_i.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/ram_switch_state.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(44)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(59)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr.v(128)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/prebuffer_rev.v
+HDL-1007 : undeclared symbol 'rd_en', assumed default net type 'wire' in ../../hg_mp/fe/prebuffer_rev.v(215)
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_data_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_rev.v
+HDL-1007 : analyze verilog file ../../hg_mp/fe/read_ram_addr_rev.v
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(46)
+HDL-5007 WARNING: begin/end is required for generate-for in this mode of Verilog in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(61)
+HDL-5007 WARNING: block identifier is required on this block in ../../hg_mp/fe/read_ram_addr_rev.v(145)
+HDL-1007 : analyze verilog file ../../hg_mp/local_bus/uart_2dsp_6M_921600.v
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl.v(130)
+HDL-5007 WARNING: 'pclk' is not declared in ../../hg_mp/fe/rddpram_ctl_rev.v(130)
+RUN-1001 : Project manager successfully analyzed 63 source files.
+RUN-1002 : start command "import_device eagle_s20.db -package EG4D20EG176"
+ARC-1001 : Device Initialization.
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :            OPTION            |            IO            |   SETTING   
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1001 :   cso_b/cclk/mosi/miso/dout  |  P140/P168/P166/P165/S5  |    gpio    
+ARC-1001 :             done             |           P10            |    gpio    
+ARC-1001 :           program_b          |           P134           |  dedicate  
+ARC-1001 :        tdi/tms/tck/tdo       |     P46/P44/P47/P43      |  dedicate  
+ARC-1001 : ----------------------------------------------------------------------
+ARC-1004 : Device setting, marked 5 dedicate IOs in total.
diff --git a/src/prj/td_project/td_20240312_112332.log b/src/prj/td_project/td_20240312_112332.log
new file mode 100644
index 0000000..a68ae57
--- /dev/null
+++ b/src/prj/td_project/td_20240312_112332.log
@@ -0,0 +1,12 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 11:23:32 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
+GUI-2000 : The IP files have been created successfully :{EG4D20EG176(D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/pll/pll.ipc)}
diff --git a/src/prj/td_project/td_20240312_135602.log b/src/prj/td_project/td_20240312_135602.log
new file mode 100644
index 0000000..5018dc6
--- /dev/null
+++ b/src/prj/td_project/td_20240312_135602.log
@@ -0,0 +1,12 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 13:56:02 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...
+GUI-2000 : The IP files have been created successfully :{EG4D20EG176(D:/huagao/huagao_anlogic_mono_lvds/huagao_mono_lvds_mode2-add_value-hualing-16m/src/hg_mp/anlogic_ip/pll/pll.ipc)}
diff --git a/src/prj/td_project/td_20240312_142050.log b/src/prj/td_project/td_20240312_142050.log
new file mode 100644
index 0000000..4a8c4c7
--- /dev/null
+++ b/src/prj/td_project/td_20240312_142050.log
@@ -0,0 +1,11 @@
+============================================================
+   Tang Dynasty, V5.6.71036
+      Copyright (c) 2012-2023 Anlogic Inc.
+   Executable = D:/Anlogic/TD5.6.2/bin/td.exe
+   Built at =   20:34:38 Mar 21 2023
+   Run by =     holdtecs
+   Run Date =   Tue Mar 12 14:20:50 2024
+
+   Run on =     DESKTOP-5MQL5VE
+============================================================
+RUN-001 : GUI based run...